EEE 3423:

MICROPROCESSORS & MICROCOMPUTERS

WEEK 05:
Software Architecture Of The 8088/8086
Microprocessors
"Failure is simply the
opportunity to begin
again, this time more
intelligently.“
-Henry Ford
 TOPIC COVERED THIS WEEK
1. Microarchitecture of the 7) Instruction Pointer
8088/8086 8) Data Registers
Microprocessor 9) Pointer and Index
2. Software Model Registers
3. Memory Address 10)Status Register
Space & Data 11)Generating a Memory
Organization Address
4. Data Types 12)The Stack
5. Segment Registers & 13)Input / Output Address
Memory Segmentation Space
6. Dedicated, Reserved &
General-Use Memory
8088/8086 PIPELINE ARCH.

INSTRUCTION
EU PIPELINE BIU

SYSTEM BUS
8088/8086 PIPELINE ARCH.
8088/8086 FUNCTIONAL PARTS
From week one, we have identify…

• BIU Contains: • EU contains:

• Instruction queue • Control circuitry
• Segment registers • Instruction decoder
• Instruction pointer • ALU
• Address adder • Pointer & index
register
• Flag register
8088/8086 BIU
• BIU handles all transactions of data and
address on the buses for EU
• Read / write memory
• Calculate address of memory operands
• Instruction fetching
• Queueing instruction to the instruction queue
8088/8086 EU
• Executes instruction from the instruction queue
• It also access data from the general-purpose
registers or memory
• Read instruction byte  Decode  Generates
data address (if required)  Pass to BIU for
operation (memory access)  Perform
operation
• It performed the arithmetic, logic, and shift
instructions required by the instruction
• It also access on status and control flags
8088/8086 SOFTWARE MODEL
• 16-bit internal
registers:
• IP
• 4 data registers
• 2 pointer registers
• 2 index registers
• 4 segment registers
• Additional SR
• Independent
• Memory (1Mbytes)
• I/O address space
(64Kbytes)
MEMORY ADD SPACE & DATA ORG
• Memory is organized as individual FFFFF
FFFFE
bytes.
FFFFD
• Range from 00000H to FFFFFH 
1Mbytes
• Data organization
• Byte – Content of any individual byte
address
• Word – Contents of 2 contiguous byte
addresses.
• Double-word – Contents of 4 contiguous
byte addresses. 00002
00001
00000
MEMORY ADD SPACE & DATA ORG
• Words and Double-words of
data can be stored at either
even or odd address
boundary.
• Words stored at an odd
address boundary 
aligned words.
• Words stored at an even
address boundary 
misaligned/unaligned
words.
MEMORY ADD SPACE & DATA ORG
• Aligned Double-words
are stored at even
addresses that are
multiple of 4.
• Example: 0, 4
• Misaligned Double-
words are stored at
address that are not
multiple of 4.
• Example: 1,2,3,5
DATA TYPES
• To examine the types of data that can be coded
into these format of processing.
• The data types are:
1. Integer data types  singed or unsigned
• Can either be byte-wide or word-wide.
2. BCD
3. ASCII
ASCII
SEGMENT REGISTER & MEMORY
SEGMENTATION
• Memory Segmentation
• Not all of the 8088/8086 address space is active at
one time
• Address value in a segment register points to the
lowest addressed byte in an active segment
• Size of each segment is 64K contiguous bytes
• Total active memory is 256k bytes
• 64K-bytes for code
• 64K-bytes for stack
• 128K-bytes for data
SEGMENT REGISTER & MEMORY
• Four Segment Registers
• Code segment (CS) register-
Code storage
• Stack segment (SS) register-
Stack storage
• Data segment (DS) register-
Data storage
• Extra segment (ES) register-
Data storage
SEGMENT REGISTER & MEMORY
• SR are user accessible
• Programmer can change
values under software control
• Permits access to other parts
of memory
• Restriction on the address of a
segment in memory
• Must reside on a 16-byte
address boundary.
• Orientation of segments
• Contiguous
• Adjacent
• Disjointed
• Overlapping
DEDICATED, RESERVED, AND
GENERAL-USE MEMORY
• Dedicated/Reserved
• 0H  7FH : interrupt vector table
• 1st 128 bytes
• 32 4-byte pointers
• 16-bit segment base address – 2 MSBytes.
• 16-bit offset – 2 LSBytes
• 0H  13H : internal interrupts & exceptions.
• 14H  7FH: reserved for external user defined
interrupts
• FFFF0H  FFFFBH : dedicated to hardware reset
• FFFFCH  FFFFFH: reserved for future products.
• Open (80H  FFFEFH)
• General use of memory for data & program instruction
are stored.
• Available for stack, code & data.
INSTRUCTION POINTER (IP)
• Identify the location of the next word of instruction code to be
fetched from the current code segment
• 16-bits offset – address pointer
• CS:IP  forms 20-bit physical address of next word instruction
code.
• Instruction fetch sequence
• Fetch from code segment in memory
• Word placed in the instruction queue to await execution.
• Instruction execution sequence
• Read from output of instruction queue and execute it.
• Operands read from data memory, internal registers or the
instruction queue
• Operation specified by the instruction performed on operands
• Results written to data memory or internal register.
DATA REGISTERS
• Four general purpose data REGISTER OPERATIONS
registers: AX Word multiply, word divide,
1) Accumulator (A) register word I/O
2) Base (B) register AL Byte multiply, byte divide,
3) Count (C) register byte I/O, translate, decimal
arithmetic
4) Data (D) register
AH Byte multiply, byte divide
BX Translate
CX String operations, loops
CL Variable shift and rotate
DX Word multiply, word divide,
indirect I/O
DATA REGISTERS
• Can hold 8-bit or 16-bit data
• AH/AL  high and low byte value
• AX  word value
• Use/Function
• Hold data such as source or destination operands for most
operation (arithmetic & logic)  ADD, AND
• Hold address pointer for accessing memory.
• Some data registers have dedicated special use:
• C  count for loop, repeat string, shift and rotate
operations
• B  lookup-table translation, base address
• D  indirect I/O and string I/O
POINTER & INDEX REGISTER
• Pointers are offset addresses
used to access information in a
segment of memory.
• Access information in ‘stack
segment’ of memory
• SP & BP are offset from current
value of the stack segment base
address
• 2 pointer register • Select a specific storage location
• Stack Pointer (SP) in the current 64Kbyte stack
• Base Pointer (BP) segment.
• 2 index register • SS:SP  point to top of stack
• Source Index (SI) • SS:BP  point to an element of
data in stack.
• Destination Index (DI)
POINTER & INDEX REGISTER
POINTER REGISTERS INDEX REGISTERS
• Pointers are offset addresses • Value in an index register is
used to access information in also and address pointer.
a segment of memory. • Access source & destination
• SP & BP are offset from operands in data segment of
current value of the stack memory
segment base address • DS:SI  points to source
• Select a specific storage operand in data segment
location in the current • DS:DI  point to destination
64Kbyte stack segment. operand in data segment
• SS:SP  point to top of • Can also used to access
stack information in ES.
• SS:BP  point to an element
of data in stack.
STATUS REG. aka FLAGS REG.
• Status (Conditional) Flags
• Indicate conditions result of
executing an instruction
• Execution of most
instruction update status
• Used by control flow
instructions as test cond.
• 16-bit register use to hold • Control Flags
single bit status and control • Control operating function of
information. the processor
• 9 active flags in real mode • Used by software to turn
• Can be categorized as ON/OFF operating
Status (Conditional) Flags or capabilities.
Control Flags
STATUS REG. aka FLAGS REG.
Type Flags Operation
CF Carry CF is set if there is a carry-out or a borrow-in for
the MSB, otherwise, CF is reset
PF Parity PF is set if the result produced has even parity –
that is contains an even number of bits at logic 1, if
odd PF is reset
AF Auxiliary AF is set if there is a carry-out from the low nibble
Status carry into high nibble or borrow-in from high nibble to
Flag low nibble in register AL, otherwise AF is reset
ZF Zero ZF is set if result produced is zero, otherwise ZF is
reset
SF Sign The MSB of the result is copy in SF
OF Overflow When OF is set, it indicated that the signed result
is out of range, if not OF remains reset
STATUS REG. aka FLAGS REG.
Type Flags Operation
IF Interrupt For the 8088 to recognize maskable interrupt
enable requests at its interrupt (INT) input, the IF must
be set. When IF is reset, request at INT are
ignored and the maskable interrupt interface is
disable
DF Direction DF determines the direction in which string
Control
operations will occur. When set, string
flags
instruction decrements the address. When reset,
string instruction increase the address
TF Trap If TF is set, the 8088 goes into single-step mode
of operation. In this mode, it executes an
instruction and jumps to a special service
routine. Useful for debugging programs.
GENERATING MEMORY ADDRESS
• Logical address  real mode
architecture described by a
segment address and an offset.
• Segment base address (CS,
DS, ES, SS)
• Offsets (IP, SI, DI, BX, DX,
SP, BP etc.)

• Physical address  actual

address used for accessing
memory.
THE STACK
• Temporary storage area for
information (data, addresses)
• Located in stack segment of
memory
• Real Mode – 64Kbytes long
• Organized as 32k words.
• Information saved as words,
not bytes.
• Organization of stack
• SS:0000H  end of stack
(lowest addressed word)
• SS:FFEH  bottom of stack
(highest addressed word)
• SS:SP  top of stack (last • Use when CALL, PUSH, POP
stack location to which data instruction is executed and return
was pushed operations
INPUT/OUTPUT ADDRESS SPACE
• Place I/O devices are
normally implemented.
• connect to external
system like keyboard,
printer and monitor
• I/O addresses are only 16-
bits in length.
• Independent 64K-bytes
address space
• Address range 0000H through FFFFH.
• Page 0  refer to map address 0000H through 00FFH.
• where certain I/O instruction can only be used on this I/O
address space
"Perseverance is the hard work you do
after you get tired of doing the hard work
you already did."

So, are you still here with me? :P