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Eventide Self Test
Self test procedure for the Eventide H3000
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Eventide Self Test
Self test procedure for the Eventide H3000
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RSION u25@ |S ess uss|{o uase LL?’ Ld usa] PS ]uest ai (ARoM MOD AREAEventide the next step ‘StmpuR, JUNE 1993 ‘The selftest ROM for the 113000 is either 512K or 1M. The one that is required for a particular unit depends upon the setup of jumpers on the main board. The jumpers are located between the software EPROMs and are numbered on the board. The 512K ROM is used if X6 and X7 have jumpers. The 1M ROM is used if X5 and X7 have jumpers. The selftest ROM for the 13500 is always a 1M ROM. Once it is determined which ROM can be used, the selftest ROM can be installed in any vacant socket. Note that the 512K ROM has to be installed to the right side of the socket as it has less pins than the socket. SELF-TEST version 2.18 has the following tests: #1 — Burn-in Test (Loop) #2 #3 — Quick Test (No Loop) #4 #5 Sampler all 1 meg (NL) #6 #7 Sampler all 4 meg (NL) #8 #9 Sampler all 16 meg (NL) _ S {#10 #11 Sampler all 2 meg (NL) #12 #13 Sampler all 8 meg (NL) #14 #15 N/A ‘#16 #17 Preset File Test #18 #19 Brain does Mail 0 #20 #21 Brain does Mail 2 #22 #23 Load PEL 2 #24 #25. Load Parameters Pel 1 #26 #27 Load Parameters Pel 3 #28 #29 Memory Data Test P2 #30 #31 Memory Address P1 #32 #33 Memory Address P3 #34 #35 More Address P2 #36, #37 Page 1 Mem Data P1 #38 #39 Big Page test 1 meg #40 #41 Big Page Test 4 meg #42 #43 ‘Big Page Test 16 meg S {#44 #45 Big Mem Comp 2 meg #46 #47 Bib Mem Comp 8 meg #48, #49 OS Rom Checksum #50 #51 App Rom 1 Checksum u 25! #52 #53 App Rom 3 Checksum U2S0 #54 #55 FastHand stat pel #56 #57 Sig Proc Inpt IRQ P1 #58 #59 IRQ Status from brain #60 #61 FIRQ Status from pel #62 #63 Flag Bit Latch 1 #64 QC Test (Loop) Test Audio (Loop) Sampler all 2 meg (NL) Sampler all 8 meg (NL) Sampler all 1 meg (NL) Sampler all 4 meg (NL) Sampler all 16 meg (NL) System Ram Test Brain Global Area Brain does Mail 1 Load PEL 1 Load PEL 3 Load Parameters Pel 2 ‘Memory Data Test P1 (Does Memory Data Test P3 Memory Address P2 “More Address P1 More Address P3 Page 1 More Address Big Page Test 2 meg Big Page Test 8 meg Big Mem Comp 1 meg Big Mem Comp 4 meg Big Mem Comp 16 meg App Rom 0 Checksum App Rom 2 Checksum Fast Handshake P1 FestHand Status brain IRQ Status from pel Fast Inpt FIRQ Pi FIRQ Status From Brain Flag Bit Latch 2 u ass a asz Nib) MODEACIORY EPROM GeEFT FOITE CHECKSUM WERIT We OK EVENTIDE INC + ONE ALSAN WAY « LITTLE FERRY, NEW JERSEY ©7643 + 201-641-1200 + FAX: 201-641-1640page 2 #65 Flag Bit Latch 3 #66 =~ Flag Bit Latch 4 #67 Flag Bit Latch 5 #68 Flag Bit Latch 0 #69 Pel Interrupted Pi #70 ‘Pel Interrupted P2 #71 Pel Interrupted P3 #72 Pel Interrupted Status #73 Non-Maskable Inpt. #74 — Right Freq Synth PL #15 Left Freq Synth P1 #16 MIDI Loop Test #77 PEL Sync-Short #78 PEL Sync-Long #79 6 PEL Sync-Short #80 6 PEL Sync-Long #81 Left Channel Noise #82 Right Channel Noise #83 Left Input MDAC #84 Right Input MDAC #85 Left Output MDAC #86 Right Output MDAC #87 Left Feedback MDAC #88 Right Feedback MDAC #89 Left Freq Response #90 — Right Freq Response #91 Left Distortion (int) #92 Right Distortion (int) #93 Left Distortion (ext) #94 — Right Distortion (ext) #95 Left DC Offset (gnd) #96 Right DC Offset (grnd) #97 Left DC Ofiset (in) #98 Right DC Offset (sin) #99 Left Channel Noise B #00 Right Channel Noise B #01 Left Distortion B (int) #02 Right Distortion B (int) #03 Left Distortion B (ext) #04 Right Distortion B (ext) #05 Left DC Offset B (gnd) #06 Right DC Offset (gnd) #07 Left DC Offset B (sin) #08 — Right DC Offset (sin) As can be seen from the tests, some of them may be redundant for each particular unit. Note that the tests do not run in the sequence that they are numbered. The sequence is as follows: #1 BURN IN TEST (LOOP) SEQUENCE 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 49, 51, 78, 54, 55, 58, 59, 60, 62, 61, 68, 63, 64, 65, 66, 67, 73, 72, 69, 70, 71, 74, 75, 76, 99, 00, 83, 88, 89, 90, 01, 02, 03, 04, 05, 06, 07page 3 Self Test Documentation for H3000 and H3500 Ultra Harmonizer Self Test Rev 2.18 How to get into self-test: ‘Once the unit is turned on: 1. Press PROGRAM twice to get to the menu where you can save a program. 2 Press the softkey all way to the right (there is no label for this softkey). Or, 1. With unit off, press and hold the "5" key on the keypad. 2 ‘Turn unit on. ‘You are now in Selftest Mode MORE: this gets you more softkeys VIRGIN: this will allow you to reset the Battery Backed Ram. How to use this is explained in the appendix of the 13000 and 113500 instruction manual. INFO: pressing this tells you more information about what is going on. If you are in the Main ‘Menu, then this tells you about the operating system and the revision. EXERCISE: This enables you to select the exercise you want to run. An exercise is a routine for testing the hardware. More details on this item to follow. SELFTEST: allows you to select a test to run on the unit. A test is where the hardware is exercised and compared to expected results to determine if the unit is working properly. ‘These tests are explained in the next section.page 4 Selecting a Selftest 1. After pressing "Selftest" the screen will look something like this: #1 P= 0 E= 0 BURN-IN TEST (LOOP) (START) (CONTINUE) #1: refers to the test number BURN-IN TEST (LOOP): js the description of the test NOTE: LOOP means that the output XLRs have to be connected to the Input XLRs and the MIDI input and output must be connected. P= 0: is how many passes this test went through since the last time the test was started is how many errors were found since the last time the test was started. The "#1 P= 0 E= 0% is referred to as the Status Window ‘Turning the knob will allow you to scroll through. the tests. START: will start the test. Every time you press START you will reset the pass and error count. BYPASS: allows you to exit a test. Some tests don’t look at bypass all the time so you may have to hold down the key until you get to a test that docs. INFO: available on some tests. Pressing this will give more information about what was found when the test was run. Some tests enable you to scroll through the information by turning the knob. Other tests will show information between the START and CONTINUE softkeys. NOTE: The pass and error counts are only updated after a pass of a test is completed. You may see other error indications before the error number changes. TEST ALL: tests will execute a group of tests. When the tests are running you will see a second Status Window. This tells you which test is being run, how many passes so far, and how many errors were found. During certain tests, the bottom of the display will contain additional information. ‘The number of errors in the first Status Window reflects how many passes of individual tests had errors. In other words, if an individual test such as "Load PEL 1" had any number of errors, the total error count for the "Test All" test goes up accordingly.page 5 General Error Logging Most tests confirm that number X is the same as number Y. With this is mind we have instituted a generalized system of logging errors: STIMULUS: is a number (16 bit) that is what it should be. RESPONSE: is the number that the test actually found, ERROR: a 0 bit represents where the Stimulus and the Response are the same. A 1 bit represents where the Stimulus and the Response are different (an error). COUNT: is usually some independent variable associated with the test such as address or byte count. The ACCUMULATED ERROR is a number that is updated every time an error occurs. Updated in the sense that during a given test if an error occurs, a 0 changes to a 1 in the error position of the number and will remain a 1 throughout the rest of the test. At the end of the test, when this number is examined, it will show which bits had an error during the test. This is called the SET IMAGE. A Set Image is a way we can teli you what bits were high when an error occurred, It is also a way we can give you a hint about where the problem lies. There is a Set Image for Errors, Stimulus, and Count. When you start running a test the Image is set to all 0s. If an error occurs, the bits which are set to "1" are transferred to the Set Image, When you are done you can see what bits can be high when errors occur. There is also a RESET IMAGE where you can see what bits were low when an error occurred. It is set to FFFFH when you start the program. What bits are low are correspondingly set low in the Image. You then have a record of what bits could go low when an error occurs. Also included with this logging method is a record of the first occurrence of an error. This gives you a snapshot of a particular error, INFO: (This is only available on certain tests) When you press this softkey you will be able to turn the knob and scroll through the following: ACCUMULATED ERRORS: Which bits had at times been different between the Stimulus and the Response. COUNTER SET IMAGE: Which bits of the counter had been at times High when errors occurred. A 1 indicates that the bit had been high when an error occurred, COUNTER RESET IMAGE: Which bits of the counter had been low when the error had occurred. A 0 indicates that the bit had been low when an error occurred.page 6 STIMULUS SET IMAGE: Which bits of the Stimulus had been at times High when errors occurred. A 1 indicates that the bit had been High when an error occurred. STIMULUS RESET IMAGE: Which bits of the Stimulus had been low when an error had occurred. A 0 indicates that the bit had been low when an error occurred. FIRST ERROR COUNT: What the counter was when the first error occurred. FIRST ERROR STIMULUS: What was expected during the first error. FIRST ERROR RESPONSE: What was found during the first error. FIRST ERROR: The difference between the first Stimulus and the first Response. Exercises EXERCISE: This softkey enables you to select which exercise you want to run. ‘An exercise is a routine written to help test the hardware. Most of the routines usually go through reading and writing a small piece of hardware repetitively. Because of this, you may prefer to save time by using your scope to sce if the hardware is working properly. A lot of the exercises use incrementing numbers. These are simply a sequence of binary numbers that count up (1,2,3, ete). ‘These numbers appear as square waves on your scope if the exercise is writing to a latch with outputs enabled. The significance of a bit determines the frequency of the square wave. Bit 0 (least significant) is twice the frequency of Bit 1, Bit 1 is twice the frequency of Bit 2, etc. NOTE: These routines were written when the H3000 was being developed and have never been updated. We included them because, in certain cases, they may be helpful. These routines cannot be counted on to diagnose a problem in every case.
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