QM81050

Boost-Buck PMIC for Mobile Applications

Product Overview
The QM81050 is a power management unit with a boost-buck
DCDC converter designed for use in conjunction with power
amplifiers in a multi-mode 3G/4G/5G handheld system. It can
also support HPUE/PC2 operation. Package: WLCSP, 2.48mm x 1.77mm x 0.67mm
The boost-buck mechanism of the DCDC converter allows for
operation in a wide range of supply voltages, while still
maintaining system performance such as linearity, output
power, and high efficiency. The converter has a fast response Key Features
to load and line transients. It supplies an output voltage with
minimal ripple over a wide output voltage range. • Uses a Boost-Buck Architecture
• High Efficiency Over Various Loads
• Variable Output Voltage: 0V to 5.5V
• MIPI® RFFE Programmable Control Interface
Functional Block Diagram

Applications
• 3G/4G/5G Multimode, Multiband Handsets, Data Cards
• HPUE/PC2 Handsets, Data Cards

Ordering Information
Part Number Description
QM81050SR DCDC Converter IC Sample Reel
QM81050TR13-5K DCDC Converter IC 5000 pcs Reel

QM81050 Data Sheet – Rev H | Subject to change without notice www.qorvo.com

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Absolute Maximum Ratings

Parameter Ratings Units
VBATTERY1 Supply Voltage (1) -0.3 to +6.0 V
(Standby, Idle, and Operating Modes)
VBATTERY2 Supply Voltage (1) -0.3 to +6.0 V
(Standby, Idle, and Operating Modes)
Storage Temperature (Non-Operational) -40 to +125 °C
Note: Operation of this device outside the parameter ranges given above may cause permanent damage.

Recommended Operating Conditions

Parameter Min. Typ. Max. Unit Conditions
Overall
Extended Operating Temperature Range
-30 - 85 °C
(Operational)
VBATTERY1,2 = 3.6V, VIO = 0V, No load,
IBATT Leakage Current - - 10 µA
Room Temperature
VBATTERY1,2 = 3.6V, VIO = 1.8V, No Load,
IBATT Idle Current - - 10 µA
No MIPI RFFE R/W, Room Temperature
UVLO (Under voltage Lockout) 2.5 - - V
OVP has a DAC clamp that cannot exceed
OVP (Over voltage Protection) - - 6.35 V
what’s programmed (>6.35V is default)
Over current protection coupled with Over
OCP (Over current Protection) - - TBD A
temperature protection.
Maximum Output Load current – Buck
1 - - A Vcc < 3.4V
Mode
Maximum Output Load current – Boost
1.4 - - A 3.4V ≥ Vcc ≤ 5.5V
Mode
Switching Frequency 0.125 - 7.875 MHz
Boost-Buck Converter Electrical
Interface
VCC performance will be degraded at
VBATTERY1 Supply Voltage (1) 2.5 3.6 5.1 V
VBATTERY1 = 2.5V - 2.9V
VCC performance will be degraded at
VBATTERY2 Supply Voltage (1) 2.5 3.6 5.1 V
VBATTERY2 = 2.5V - 2.9V
VCC Output Voltage Range 0 - 5.5 V VBATTERY1,2 ≥ 3.4V
VBATTERY1,2 = 4V, VCC = Vdac = 4.2V,
- 85.5 - %
ILOAD = 1200mA;
VBATTERY1,2 = 3.6V, VCC = Vdac = 5.5V,
- 86.5 - %
ILOAD = 1400mA;
Efficiency - Boost Mode
VBATTERY1,2 = 3.6V, VCC = Vdac = 4.85V,
- 85.5 - %
ILOAD = 500mA;
VBATTERY1,2 = 3.6V, VCC = Vdac = 3.9V,
- 84.5 - %
ILOAD = 500mA;
VBATTERY1,2 = 4V, VCC = Vdac = 3.4V,
- 93 - %
ILOAD = 650mA;
Efficiency - Buck Mode
VBATTERY1,2 = 3.6V, VCC = Vdac = 2.45V,
- 90.5 - %
ILOAD = 200mA;

QM81050 Datasheet – Rev H | Subject to change without notice www.qorvo.com

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Parameter Min. Typ. Max. Unit Conditions

Boost-Buck Converter Electrical
Interface
Initial Start Up Time - - 20 µs At device power-on
Vout(VCC) Transition time – 1V to 5.5V - - 10 µs 10% to 90%
Vout(VCC) Transition time – 1V transitions - 6 - µs 10% to 90%
Transient response - Load - 100 TBD mV 2MHz switching frequency
Transient response - Line - - 100 mV 2MHz switching frequency
Accuracy - Load - - 5 %
Accuracy - Line - - 5 %
For <15µs rise time, the maximum
capacitance allowed on the output should be
Output Capcitance - - 10 µF <10µF. This translates to 2.2µF + 0.68µF
from converter side capacitors and 2.2uF +
4.7uF from PA side capacitors.
Note 1: VBATTERY1 and VBATTERY2 are intended to be tied to the same supply and need to be kept at the same potential, or
permanent damage may occur.

Digital Interface Voltage and Timing

Requirements
Externally supplied voltage that must be
VIO Supply Voltage 1.6 1.8 2 V supplied the entire time the device is
operational. Internally level shifted.
- - 5 mA Master read operation.
VIO Supply Current
- - 1.25 mA Master write operation.
Input High Voltage 0.7*VIO - VIO V
Input Low Voltage -0.3 - 0.3*VIO V
Output High Voltage 0.8VIO - VIO V
Output Low Voltage -0.3 - 0.2*VIO V
Clock Frequency 0.1 - 55 MHz
Clock Duty Cycle 45 50 - %
Electrical specifications are measured at specified test conditions. Specifications are not guaranteed over all recommended operating conditions.

QM81050 Datasheet – Rev H | Subject to change without notice www.qorvo.com

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Detailed Functional Block Diagram

QM81050 Datasheet – Rev H | Subject to change without notice www.qorvo.com

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Pin Configuration and Description

Pin Number Label Description

A1 cb_h Main charge-pump phase "b" fly capacitor positive connection
B1 L PWM output to be connected to external power inductor
C1 L PWM output to be connected to external power inductor
D1 ca_h Main charge-pump phase "a" fly capacitor positive connection
A2 VDD Battery supply connection for high power charge-pump phase "b"
B2 GND Ground return for the high power charge-pump phase "b"
C2 GND Ground return for the high power charge-pump phase "a"
D2 VDD Battery supply connection for high power charge-pump phase "a"
A3 cb_l Main charge-pump phase "b" fly capacitor negative connection
B3 pbulk Holding capacitor for CMOS substrate
C3 GND Ground return for the high power charge-pump phase "a"
D3 ca_l Main charge-pump phase "a" fly capacitor negative connection
A4 vio Serial interface supply
B4 sclk Serial interface clock input
C4 GND Ground return for the pump
D4 Lbuck PWM output to be connected to external power inductor
A5 Vout_fb Voltage feedback input for the high power charge-pump
B5 sdata Serial interface data I/O
C5 VDD Battery supply for the pump
D5 Lbuck PWM output to be connected to external power inductor
A6 GNDA GND for the analog
B6 Mux_out Mixed-signal MUX output
C6 GNDA Ground return for quiet side of chip. Used for circuits other than the Main Charge Pump
D6 VDDA Battery supply connection for CMOS circuitry

QM81050 Datasheet – Rev H | Subject to change without notice www.qorvo.com

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Register Map

Register 2, Addr: 0x02

Bit(s) Field Name Description Default Trig R/W
Enables the support circuitry
0 = Turns OFF the bandgap, voltage references, and clock
7 DeviceEN generator 0 0-2 R/W
1 = Turns ON the bandgap, voltage references, and clock
generator
Vdac[6:0] defines the output voltage the part will seek to
6:0 Vdac[6:0] deliver. It's step resolution (the lsb of this voltage DAC 000 0000 0-2 R/W
output) is 50mV

Register 3, Addr: 0x03

Bit(s) Field Name Description Default Trig R/W
Main Charge-Pump operating modes
00 = Ultra Low Power Mode (Buck DCM Mode)
7:6 MainCPModes[1:0] 01 = Buck Mode (Buck CCM Mode) 00 0-2 R/W
10 = Reserved
11 = High Power (Boost Mode)
Switcher Frequency Setting definition depends upon other
register bit settings as defined below. This table reflects the
routing of these bits throught the digital truth table.

Dithering Disabled, SemiAuto=0, FullAuto_EN=0:

switcher frequency (single frequency mode)
Dithering Disabled, SemiAuto=1 OR FullAuto_EN=1:
5:0 Fminb[5:0] switcher frequency for Buck-Only CCM mode 11 1110 0-2 R/W
Dithering Enabled, SemiAuto=0, FullAuto_EN=0:
switcher Fmin for dithering control
Dithering Enabled, SemiAuto=1 OR FullAuto_EN=1:
switcher Fmin for dithering control

Binary weighted frequency with lsb = ~0.125 MHz.

0b000000 = 0.125 MHz

Register 4, Addr: 0x04

Bit(s) Field Name Description Default Trig R/W
Switcher Frequency Setting depends upon other register bit
settings as defined below. This table reflects the routing of
these bits throught the digital truth table.

Dithering Disabled, SemiAuto=0, FullAuto_EN=0: Not Used

Dithering Disabled, SemiAuto=1 OR FullAuto_EN=1:
switcher frequency for Pump-Buck mode
5:0 Fminp[5:0] 11 1111 0-2 R/W
Dithering Enabled, SemiAuto=0, FullAuto_EN=0:
switcher Fmax for dithering control
Dithering Enabled, SemiAuto=1 OR FullAuto_EN=1:
switcher Fmin for dithering (Pump-Buck)

Binary weighted frequency with lsb = ~0.125 MHz.

0b000000 = 0.125 MHz

QM81050 Datasheet – Rev H | Subject to change without notice www.qorvo.com

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Register 5, Addr: 0x05
Bit(s) Field Name Description Default Trig R/W
Switcher Frequency Setting depends upon other register bit
settings as defined below. This table reflects the routing of
these bits throught the digital truth table.

Dithering Disabled, SemiAuto=0, FullAuto_EN=0: Not Used

Dithering Disabled, SemiAuto=1 OR FullAuto_EN=1:
5:0 Fmind[5:0] switcher frequency for Buck-Only DCM mode 11 1111 0-2 R/W
Dithering Enabled, SemiAuto=0, FullAuto_EN=0: Not Used
Dithering Enabled, SemiAuto=1 OR FullAuto_EN=1:
switcher Fmin for dithering (Buck DCM)

Binary weighted frequency with lsb = ~0.125 MHz.

0b000000 = 0.125 MHz

Register 6, Addr: 0x06

Bit(s) Field Name Description Default Trig R/W
Switcher Frequency Setting depends upon other register bit
settings as defined below. This table reflects the routing of
these bits throught the digital truth table.

Dithering Disabled, SemiAuto=0, FullAuto_EN=0: Not Used

5:0 Fmaxb[5:0] Dithering Disabled, SemiAuto=1 OR FullAuto_EN=1: Not Used 11 1111 0-2 R/W
Dithering Enabled, SemiAuto=0, FullAuto_EN=0: Not Used
Dithering Enabled, SemiAuto=1 OR FullAuto_EN=1:
switcher Fmax for dithering (Buck CCM)

Binary weighted frequency with lsb = ~0.125 MHz.

0b000000 = 0.125 MHz

Register 7, Addr: 0x07

Bit(s) Field Name Description Default Trig R/W
Switcher Frequency Setting depends upon other register bit
settings as defined below. This table reflects the routing of
these bits throught the digital truth table.

Dithering Disabled, SemiAuto=0, FullAuto_EN=0: Not Used

Dithering Disabled, SemiAuto=1 OR FullAuto_EN=1: Not Used
5:0 Fmaxp[5:0] 11 1111 0-2 R/W
Dithering Enabled, SemiAuto=0, FullAuto_EN=0: Not Used
Dithering Enabled, SemiAuto=1 OR FullAuto_EN=1:
switcher Fmax for dithering (Pump-Buck)

Binary weighted frequency with lsb = ~0.125 MHz.

0b000000 = 0.125 MHz

QM81050 Datasheet – Rev H | Subject to change without notice www.qorvo.com

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Register 8, Addr: 0x08
Bit(s) Field Name Description Default Trig R/W
Enables reduction to 1x Buck FETS when in DCM mode
7 BuckDCM1x_EN 0 = Disabled (3x Buck FETS always) 0 0-2 R/W
1 = Enabled (1x Buck FETS when in DCM mode)
Switcher Frequency Setting depends upon other register bit
settings as defined below. This table reflects the routing of
these bits throught the digital truth table.

Dithering Disabled, SemiAuto=0, FullAuto_EN=0: Not Used

Dithering Disabled, SemiAuto=1 OR FullAuto_EN=1: Not Used
5:0 Fmaxd[5:0] 11 1111 0-2 R/W
Dithering Enabled, SemiAuto=0, FullAuto_EN=0: Not Used
Dithering Enabled, SemiAuto=1 OR FullAuto_EN=1:
switcher Fmax for dithering (Buck DCM)

Binary weighted frequency with lsb = ~0.125 MHz.

0b000000 = 0.125 MHz

Register 9, Addr: 0x09

Bit(s) Field Name Description Default Trig R/W
Enables SemiAuto mode. When Enabled, if the
programmed Vdac[6:0] is less than or equal to the
SemiAuto_Vdac_Thresh[6:0], then the part will
7 SemiAuto_EN automatically switch into Buck Only mode, regardless of the 1 0-2 R/W
MainCPModes[1:0] selected.
0 = Disabled (OFF)
1 = Enabled (ON)
6:0 SemiAutoVth_pump[6:0] Threshold used for SemiAuto Mode determination 100 0100 0-2 R/W

Register 10, Addr: 0x0A

Bit(s) Field Name Description Default Trig R/W
Enables AutoBuckDCM mode. When Enabled, if the
programmed Vdac[6:0] is less than or equal to the
AutoBuckDCM_Vdac_Thresh[6:0], then the part will
7 AutoBuckDCM_EN automatically switch into Buck Only DCM mode, 1 0-2 R/W
regardless of the MainCPModes[1:0] selected.
0 = Disabled (OFF)
1 = Enabled (ON)
6:0 AutoBuckDCMVth_dcm[6:0] Threshold used for AutoBuckDCM Mode determination 000 1010 0-2 R/W

QM81050 Datasheet – Rev H | Subject to change without notice www.qorvo.com

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Register 12, Addr: 0x0C

Bit(s) Field Name Description Default Trig R/W
Dither Control Selection
000 = Dithering OFF (Switching Frequency set by
Fmin[5:0]
001 = Reserved
010 = Reserved
7:5 DitheringCtrl[2:0] 000 0-2 R/W
011 = Reserved
100 = Reserved
101 = 3D Dithering (Slow random & Fast Linear)
110 = Reserved for future use
111 = Reserved for future use
Enable Protection Circuits. When this bit is 1 (asserted),
then protections will start reporting their status. Shutdown
only occurs if specific protections are also enabled
4 ProtectionCktsEN 1 0-2 R/W
(asserted) below.
0 =Protections Circuits are off
1 = Protection Circuits are on
Enable Over-Temperature Protections.
0 = Over-Termperature Protections (shutdown when
device over temperature) are disabled,
3 OverTempEN 1 = Over-Temperature Pretections are enabled/operating 1 0-2 R/W
Note: When DeviceEn = 0, this bit’s default is 0. When
DeviceEn is set high, this bit will automatically turn
itself to 1.
Enable Short-Circuit Protections.
0= Short-Circuit Protections (shutdown when device
seems to be a short-circuit or is sourcing extremely
excessive current) are disabled,
2 ShortCircuitEN 1 0-2 R/W
1 = Short-Circuit Pretections are enabled/operating
Note: When DeviceEn = 0, this bit’s default is 0. When
DeviceEn is set high, this bit will automatically turn
itself to 1.
1 LowVbatProtectEN Do not change from Power-On default 0 0-2 R/W
0 BGVoltProtectEN Do not change from Power-On default 0 0-2 R/W

Register 13, Addr: 0x0D

Bit(s) Field Name Description Default Trig R/W
Enable softoff. Lowers undershoot when device is turned
1 SoftOff_EN 0 0-2 R/W
off.
Enables UnderVoltage Protections (shutdown part when
Vbat < 2.5V)
0 UVLo_EN 0 0-2 R/W
0 = Disabled
1 = Enabled

QM81050 Datasheet – Rev H | Subject to change without notice www.qorvo.com

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Register 15, Addr: 0x0F

Bit(s) Field Name Description Default Trig R/W
Enables the Vdac Clamp
7 Vdac_Clamp_EN 0 = Disabled 0 0-2 R/W
1 = Enabled
Vdac Clamp setting. When enabled, prevents the Vdac
6:0 Vdac_Clamp[6:0] 111 1111 0-2 R/W
from going above this setting

Register 20, Addr: 0x14

Bit(s) Field Name Description Default Trig R/W
Extreme Over-Temperature Shutdown Event.
0 = Over-Termperature Protections (shutdown when
HotProtectionHalt
7 device over temperature) are disabled 0 No R
(hot_fault)
1 = Over-Temperature Pretections are
enabled/operating
Extreme Current Shutdown Event.
0 = Over-Termperature Protections (shutdown when
HiCurProtectionHalt
6 device over temperature) are disabled 0 No R
(hiCur_fault)
1 = Over-Temperature Pretections are
enabled/operating
3 UVLoHalt Undervoltage protection circuit 0 No R
Over-Temperature Condition Detected.
1 = Over-Temperature Condition Detected & Device is in
Shutdown Protections Mode,
0 = All seems OK.
1 DeviceHot 0 No R
NOTE: This is a latched bit, meaning if a "1" is detected
on the input at any time, then that "1" is latched into this
output. This bit is reset to its default value whenever Vspi
is toggled.
Short-Circuit Condition Detected.
1 = Short Circuit Condition Detected & Device is in
Shutdown Protections Mode,
0 = All seems OK.
0 DeviceWarm 0 No R
NOTE: This is a latched bit, meaning if a "1" is detected
on the input at any time, then that "1" is latched into this
output. This bit is reset to its default value whenever Vspi
is toggled.

QM81050 Datasheet – Rev H | Subject to change without notice www.qorvo.com

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Register 28, Addr: 0x1C

Bit(s) Field Name Description Default Trig R/W
00: ACTIVE - Normal Operation
01: STARTUP - Reset all registers to default settings
10: LOW POWER - Retain register values, Antenna in
isolation
7:6 PWR_MODE[1:0] 10 No R/W
11: Reserved

Note: Setting PWR_MODE to STARTUP is identical to a

hardware reset initiated by the VIO signal.
Setting bit TriggerMask[N] disables Trigger[N]
TriggerMask[N] updates before Trigger[N] is processed

Note: When Trigger[N] is disabled, writing to a register

5:3 TriggerMask[2:0] associated with Trigger[N] sends data directly to that 000 No R/W
register.
If a register is associated with multiple triggers, then
all associated triggers must be disabled to allow direct
writes to the associated register.
Setting bit Trigger[N] loads Trigger[N]'s associated
registers
Note: When Trigger[N] is enabled, writing to a register
associated with Trigger[N] sends data to that register's
2:0 Trigger[2:0] 000 No R/W
shadow. Setting the Trigger[N] bit loads data from
shadow. All triggers are processed immediately and
simultaneously and then cleared. Trigger[0], [1], and [2]
will always read as 0.

Register 29, Addr: 0x1D

Bit(s) Field Name Description Default Trig R/W
Lower eight bits of Product Number
Note: This is a read-only register. However, as part of the
7:0 PROD_ID[7:0] special programming sequence for writing USID, a write 0000 0001 No R
command sequence is performed on this register, but
does not update it. See MIPI 6.8.3 for details.

Register 30, Addr: 0x1E

Bit(s) Field Name Description Default Trig R/W
Lower eight bits of MIPI Manufacturer ID
Note: This is a read-only register. However, as part of the
7:0 MFG_ID_LSB[7:0] special programming sequence for writing USID, a write 11000110 No R
command sequence is performed on this register, but
does not update it. See MIPI 6.8.3 for details.

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Register 31, Addr: 0x1F

Bit(s) Field Name Description Default Trig R/W
These are read-only bits that are reserved and yield a
7:6 Reserved_Reg31[7:6] 00 No R
value of 00 at readback.
Upper two bits of MIPI Manufacturer ID
Note: This is a read-only field. However, as part of the
5:4 MFG_ID_MSB[9:8] special programming sequence for writing USID, a write 11 No R
command sequence is performed on this field, but does
not update it. See MIPI 6.8.3 for details.
Programmable Unique Slave ID
3:0 USID[3:0] 0101 No R/W
Note: USID is only writeable using a special programming
sequence. See MIPI 6.8.3 for details.

Register 66, Addr: 0x42

Bit(s) Field Name Description Default Trig R/W
set high to reload the eFUSE data into the Register Map.
0 FuseLatch This bit now automatically resets to 0 and kicks off the 0 No R/W
complete loading of all eFUSE assiciated bit information

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Evaluation Board Layout

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Evaluation Board Schematic

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Evaluation Board Bill of Materials (BOM)

Reference Designator Case Size Value Comments

C2, C4, C7 0805 10 uF CAP, 10uF, 10%, 6.3V, X5R, 0805

C8 0603 2.2 uF CAP, 2.2uF, 10%, 10V, X5R, 0603

C1 0402 1 uF CAP, 1uF, 10%, 10V, X5R, 0402

C9 0402 0.68 uF CAP, 0.68uF, 10%, 6.3V, X5R, 0402

C5, C6 0402 2.2 uF CAP, 2.2uF, 20%, 6.3V, X5R, 0402

C3 0402 0.1 uF CAP, 0.1uF, 10%, 50V, STD, 0402

R1 0402 0 ohm RES, 0 OHM, 5%, 1/10W, 0402

IND, PWR,1uH, 20%, 1.5A,
L1 1008 1 uH
2x2.5x1.2mm,SMD

QM81050 Datasheet – Rev H | Subject to change without notice www.qorvo.com

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Package Outline and Branding Drawing
Dimension in millimeters.

1 2 3 4 5 6 6 5 4 3 2 1

A A

B B

C C

D D

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PCB Design Guidelines
PCB Metal Land and Solder Mask Pattern
Dimension in millimeters

QM81050 Datasheet – Rev H | Subject to change without notice www.qorvo.com

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Tape and Reel Information

Qorvo Part Reel Diameter Hub Diameter Pocket Pitch Units Per
Width (mm) Feed
Number Inch (mm) Inch (mm) (mm) Reel
QM81050TR13-5K N/A 4 (102) 8 4 Single 5000

Tape and reel specifications for this part are also available on the Qorvo website.

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Handling Precautions
Parameter Rating Standard
ESD – Human Body Model (HBM) 1C ANSI/ESDA/JEDEC JS-001 Caution!

ESD – Charge Device Model (CDM) C3 ANSI /ESD/JEDEC JS-002 ESD sensitive device
MSL – Moisture Sensitivity Level MSL1 J-STD-020

RoHS Compliance
This part is compliant with the 2011/65/EU RoHS directive (Restrictions on the Use of Certain Hazardous Substances in Electrical and
Electronic Equipment), as amended by Directive 2015/863/EU.

This product also has the following attributes:

• Lead free
• Halogen Free (Chlorine, Bromine)
• Antimony Free
•
•
TBBP-A (C15H12Br402) Free
SVHC Free
Pb

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REVISION HISTORY
REVISION DATE DESCRIPTION
A 2017-10-02 Initial Release
B 2017-10-18 Register map added
C 2017-11-22 Register map modified, Reg12 & Reg13
D 2018-05-25 Limits based on CM review
E 2018-08-13 Limits adjusted, updated pin mapping, updated ordering information
F 2018-10-08 Updated AMR table and Handling precautions
G 2019-03-18 Updated Pin descriptions and EVB schematic
Updated POD and branding drawing, added CDM rating, added tape and reel info, added and modified
H 2020-06-24
parameters in operating conditions.

Contact Information
For the latest specifications, additional product information, worldwide sales and distribution locations:
Web: www.qorvo.com
Tel: 1-844-890-8163
Email: [email protected]

Important Notice
The information contained herein is believed to be reliable; however, Qorvo makes no warranties regarding the information contained herein and assumes no responsibility or
liability whatsoever for the use of the information contained herein. All information contained herein is subject to change without notice. Customers should obtain and verify the
latest relevant information before placing orders for Qorvo products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to
any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such information. THIS
INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO THE PRODUCTS DESCRIBED HEREIN, AND QORVO HEREBY DISCLAIMS ANY AND
ALL WARRANTIES WITH RESPECT TO SUCH PRODUCTS WHETHER EXPRESS OR IMPLIED BY LAW, COURSE OF DEALING, COURSE OF PERFORMANCE,
USAGE OF TRADE OR OTHERWISE, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
Without limiting the generality of the foregoing, Qorvo products are not warranted or authorized for use as critical components in medical, life-saving, or life-sustaining
applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death.

Copyright 2016 © Qorvo, Inc. | Qorvo is a registered trademark of Qorvo, Inc.

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