ELE2503: 

Electronic Systems 

Assessment 2: Report 1 

Due: 11:59 pm 22 August 2022 

Weighting: 200 marks (20 %) 

Topic: Analogue to Digital Conversion (ADC) System 

Late Submissions: As per USQ Policy 

Rationale: 

In this assessment you will be given a schematic for an analogue to digital converter. It will take an 
analogue value at V_In and approximate it to digital signals and B1 – B4, using a simplified variation of 
successive approximation. 

This  type  of  circuit  is  not  usually  one  you  would  build  from  discrete  parts,  as  there  are  integrated 
circuits  that  can  perform  the  task.  However,  as  it  is  a  task  we  perform  often  in  many  different 
applications, it is an interesting system to investigate nonetheless as it combines fundamental digital 
logic operations while also using simple analogue electronic signals.  

Aims: 

 Determine and describe the operation of the system using block diagrams and simple circuit 
analysis techniques.  
 Simulate the circuit in CircuitLab to verify operation.  
 Consider the impact of changes to the system, in particular changing the resolution and clock 
speed. 
 Make simple changes to the given system to improve the performance and increase flexibility.  
 Identify practical considerations when prototyping and testing the circuit.  

Related Couse Content: 

This assessment relies mostly on the content in Modules 1 and 2, with some elements of Modules 3 
and 4 in minor aspects.  

Objectives Assessed: 1,2,3,4,5,6 

   
Tasks: 

Part A: Overview 

1. Access  the  circuit  given  in  the  Schematic  file  ELE2503_Report_1_Schematic.pdf.  Values  for 
your components will be found in the separate file ELE2503_Report_1_Values.pdf.  

Note your individual values here. 

2. Using your knowledge of block diagrams and circuit elements, separate the circuit into blocks, 
drawing an equivalent block diagram of the circuit.  

3. Based on the block diagram, write a simple description of the circuit. This should be about half 
a  page  in  length.  (You  should  revisit  the  block  diagram  and  description  once  you  have 
successfully simulated the circuit operation, revising if necessary.) 

Part B: Analysis 

Calculate the following: 

1. The current flowing through R20, and hence the voltage at nodes M and N for each of the 
combinations of the digital signals at A, B, C, and D. (Please show sample calculations. A table 
would be best for collating the results.) 

2. What is the resolution of the system in the schematic? (Please include your calculations. Give 
you answer in V.) 

3. For the given value of Test V_in (in your individual values), determine what OA3 will do for the 
each of the combinations of A, B, C and D. (Another table would be useful here.) 

Part C: Simulation 

1. Build the circuit in CircuitLab and verify the operation is as expected. Step V_in through the 
range 0 to 5 V in 0.5 V steps, noting the voltage at Node N and the Digital results at Node T, 
B1, B2, B3 and B4 at each step.  Include this testing as a results table. Make sure that you use 
suitable propagation delays for the digital logic devices – refer to a data sheet to determine a 
value. Please include the name of the Data Sheet that you used here.  

2. Select a suitable time period and capture a timing chart that demonstrates the operation of 
your system using the value Test V_In. Comment on the operation. (Please see sample timing 
chart later in this document.) 
Part D: Modification 

The following questions should be answered as a short paragraph (around 200 words), supported by 
any relevant mathematical equations, CircuitLab timing charts and a snapshot of any new schematic 
sections made to the original schematic (supplied). The following modifications should build on each 
other. It is suggested that you save your schematic in CircuitLab as a new schematic at each stage. The 
final schematic should be included in its entirety as a PDF with your submission. 

1. The maximum voltage that you obtain at node N is not a neat integer. What changes can you 
make to the system to make it scale to the new maximum value given to you?  

2. Make changes to the circuit to ensure that the voltage remains within +/‐ 1 V of the specified 
input  range?  (The  specified  input  range  is  0  to  your  maximum  value  used  in  the  previous 
question.) You should test your system with a voltage that exceeds the accepted range by +/‐ 
2 V. For example, if your specified input range is 0 to 10 V then the circuit should limit input 
voltages to the range ‐1 to 10 V, and you would test across the range ‐3 to 12 V. 

3. Discuss  the  impact  of  increasing  the  number  of  bits  in  the  ADC  from  4  to  6.  (No  changes 
necessary to the system at this stage – discussion only.) 

4. Discuss the impact of increasing the clock speed. (No changes necessary to the system at this 
stage – discussion only.) 

5. Discuss  the  impact  of  increasing  both  the  clock  speed  and  increasing  the  bits  from  4  to  6. 
Choose a suitable clock signal and modify the system be a 6‐bit system. Are there any other 
changes you need to make?  

6. Create a parts list for the modified circuit. You will need to identify suitable components (such 
as a suitable Op Amp chip) and research price and availability for a reputable supplier, such as 
RS  Components.  Present  the  parts  list  in  tabular  format,  including  quantity,  part  number, 
manufacturer, description, price and availability.  

   
Part E: Implementation Planning 

1. Create a plan for laying out the circuit on a breadboard. Start by selecting a standard large 
breadboard (such as this 1660 hole model). Create a template which shows the hole layout. 
Place the components onto the breadboard, adding wiring connections between them. Use 
additional breadboards if needed.  
 
2. If you were planning to implement the revised circuit on the breadboard to verify operation, 
what approach would you take to building and testing the circuit? In a short paragraph, explain 
your process. 

Submission Requirements 

Submit  your  report  as  a  PDF,  with  a  separate  PDF  schematic  of  your  final  circuit  to  the  Report  1 
Submission area on StudyDesk.    
Sample Timing Chart

This is a description of the timing chart – what values are plotted, what was the time period, and what noteworthy things happened?
ELE2503 Report 1 Marking Rubric

Marks
Criteria Insufficient Limited Developing Effective Comprehensive
(of total 200)

Part A

The block diagram is The block diagram shows a The block diagram closely The block diagram accurately
Block Diagram 10 The block diagram is mostly
significantly incomplete or reasonable description of the describes the circuit and nearly describes the circuit, and all
incomplete or inaccurate.
inaccurate. circuit including most elements. all elements are included. elements are included.

The description of the circuit is The description of the circuit is

Circuit The description of the circuit The description of the circuit is
10 The description of the circuit has generally clear, covering most generally clear and concise,
Description covers at least one area of clear and concise, covering all
been attempted. critical areas with some errors covering all critical areas with
importance accurately. critical areas with no errors.
evident. minor errors.

Part B

Most relevant calculations are

Calculations Some relevant calculations are Most relevant calculations are All relevant calculations are
20 A limited attempt at calculations identified, and an attempt made
Table identified, and an attempt made identified, correctly calculated, identified, correctly calculated,
is included. to calculate, apply, and suitably
to calculate, apply, and present. applied and logically presented. applied and logically presented.
present.

No attempt found or the

Resolution 5 The resolution was incorrectly The resolution was correctly
resolution was incorrectly
calculated with minor errors. calculated.
calculated with significant errors.

The operation of OA3 was The operation of OA3 was The operation of OA3 was
OA3 Operation 5
incorrectly determined or not determined and explained with correctly determined and
explained. minor errors. explained.

Part C

The results table shows that The results table shows that
Simulation There is insufficient
10 most important circuit values most important circuit values
Results Table documentary evidence that the .
have been recorded, but do not have been recorded and they
circuit was simulated.
correlate with those calculated. correlate with those calculated.

Propagation The propagation delay was not The propagation delay has been
10 The propagation delay has been
Delay Values considered or has not been suitably researched and the
suitably researched.
researched. source noted.

The timing chart does not The timing chart clearly shows
Timing Chart of The timing chart clearly shows
10 include the important signals, or the important signals and is
Simulation some of the signals and is taken
the timeframe is exceedingly taken over an appropriate
over an appropriate interval.
long or short. interval.
 Marks
Criteria Insufficient Limited Developing Effective Comprehensive
(of total 200)

Part D

The proposed modification has The proposed modification is The proposed modification is
Voltage Scaling The proposed modification is There are some significant flaws
10 several significant flaws that suitable for the task, supported highly suitable for the task,
(Node N) highly unsuitable or incapable of in the proposed modification and
would prevent the system from by a technically correct supported by a technically
completing the task. the supporting resources.
operating as specified. description and diagrams... correct description & diagrams

The proposed modification has The proposed modification is The proposed modification is
The proposed modification is There are some significant flaws
V_in limitation 10 several significant flaws that suitable for the task, supported highly suitable for the task,
highly unsuitable or incapable of in the proposed modification and
would prevent the system from by a technically correct supported by a technically
completing the task. the supporting resources.
operating as specified. description and diagrams. correct description & diagrams.

Improving The discussion is mostly The discussion is technically

10 The discussion is incorrect or
Resolution technically correct and correct and supported by
not supported by diagrams.
supported by some diagrams. relevant diagrams.

Increasing The discussion is mostly The discussion is technically

10 The discussion is incorrect or
Speed technically correct and correct and supported by
not supported by diagrams.
supported by some diagrams. relevant diagrams.

The proposed modification has The proposed modification is The proposed modification is
Optimal Clock at The proposed modification is There are some significant flaws
10 several significant flaws that suitable for the task, supported highly suitable for the task,
6 bits. highly unsuitable or incapable of in the proposed modification and
would prevent the system from by a technically correct supported by a technically
completing the task. the supporting resources.
operating as specified. description and diagrams. correct description & diagrams.

The parts list contains a few 
Parts List 20 The parts list is incomplete and  The parts list is mostly  The parts list contains several  The parts list is complete, and 
incorrect. incomplete. errors.  errors.  all details are correct. 

Part E

A generally logical approach

The approach for building and A cohesive, logical approach
The approach for building and was presented for building and A cohesive, logical approach
Implementation 20 testing the circuit was was presented for building and
testing the circuit was testing the circuit with some was presented for building and
incomplete or difficult to testing the circuit, with some
inadequate or not explained. significant areas for testing the circuit.
understand. minor areas for improvement.
improvement.

Layout Plan 30 The proposed layout is highly The proposed layout has several There are some significant flaws The proposed layout is suitable The proposed layout is highly
unsuitable. significant flaws. in the proposed layout. despite some minor flaws. suitable.