Nand TTL

Prepared by: Ac.No

Mostafa morshed al-hothefi 2019/403
Hamza abdulkhalig otaif 2018/110
Abdulraheem Mahmoud al-sabri 2018/288
Anas dadiq al-dhaifani 2018/313
Saif aref saif al-ahdal 2018/348
Transistor–transistor logic (TTL) is a logic family built
from bipolar junction transistors. Its name signifies that
transistors perform both the logic function (the first "transistor")
and the amplifying function (the second "transistor"), as
opposed to resistor–transistor logic (RTL) or diode–transistor
logic (DTL).
TTL integrated circuits (ICs) were widely used in applications
such as computers, industrial controls, test equipment and
instrumentation, consumer electronics, and synthesizers.
Sometimes TTL-compatible logic levels are not associated
directly with TTL integrated circuits, for example, they may be
used at the inputs and outputs of electronic instruments.
After their introduction in integrated circuit form in 1963
by Sylvania Electric Products, TTL integrated circuits were
manufactured by several semiconductor companies. The 7400
series by Texas Instruments became particularly popular. TTL
manufacturers offered a wide range of logic gates, flip-flops,
counters, and other circuits. Variations of the original TTL
circuit design offered higher speed or lower power dissipation to
allow design optimization. TTL devices were originally made in
ceramic and plastic dual in-line package(s) and in flat-pack
form. Some TTL chips are now also made in surface-mount
technology packages.
TTL became the foundation of computers and other digital
electronics. Even after Very-Large-Scale
Integration (VLSI) CMOS integrated
circuit microprocessors made multiple-chip processors obsolete,
TTL devices still found extensive use as glue logic interfacing
between more densely integrated components.
Fundamental TTL gate:

Two-input TTL NAND gate with a simple output stage (simplified)

TTL inputs are the emitters of bipolar transistors. In the case of

NAND inputs, the inputs are the emitters of multiple-emitter
transistors, functionally equivalent to multiple transistors where
the bases and collectors are tied together. The output is buffered
by a common emitter amplifier.
Inputs both logical ones. When all the inputs are held at high
voltage, the base–emitter junctions of the multiple-emitter
transistor are reverse-biased. Unlike DTL, a small “collector”
current (approximately 10µA) is drawn by each of the inputs.
This is because the transistor is in reverse-active mode. An
approximately constant current flows from the positive rail,
through the resistor and into the base of the multiple emitter
transistor. This current passes through the base–emitter junction
of the output transistor, allowing it to conduct and pulling the
output voltage low (logical zero).
An input logical zero. Note that the base–collector junction of
the multiple-emitter transistor and the base–emitter junction of
the output transistor are in series between the bottom of the
resistor and ground. If one input voltage becomes zero, the
corresponding base–emitter junction of the multiple-emitter
transistor is in parallel with these two junctions. A phenomenon
called current steering means that when two voltage-stable
elements with different threshold voltages are connected in
parallel, the current flows through the path with the smaller
threshold voltage. That is, current flows out of this input and
into the zero (low) voltage source. As a result, no current flows
through the base of the output transistor, causing it to stop
conducting and the output voltage becomes high (logical one).
During the transition the input transistor is briefly in its active
region; so it draws a large current away from the base of the
output transistor and thus quickly discharges its base. This is a
critical advantage of TTL over DTL that speeds up the transition
over a diode input structure.
The main disadvantage of TTL with a simple output stage is the
relatively high output resistance at output logical "1" that is
completely determined by the output collector resistor. It limits
the number of inputs that can be connected (the fanout). Some
advantage of the simple output stage is the high voltage level
(up to VCC) of the output logical "1" when the output is not
loaded.
A common variation omits the collector resistor of the output
transistor, making an open-collector output. This allows the
designer to fabricate logic by connecting the open-collector
outputs of several logic gates together and providing a single
external pull-up resistor. If any of the logic gates becomes logic
low (transistor conducting), the combined output will be low.
Examples of this type of gate are the 7401 and 7403 series.
Open-collector outputs of some gates have a higher maximum
voltage, such as 15 V for the 7426, useful when driving other
than TTL loads.
TTL with a "totem-pole" output stage

Standard TTL NAND with a "totem-pole" output stage, one of four in 7400

To solve the problem with the high output resistance of the

simple output stage the second schematic adds to this a "totem-
pole" ("push–pull") output. It consists of the two n-p-n
transistors V3 and V4, the "lifting" diode V5 and the current-
limiting resistor R3 (see the figure on the right). It is driven by
applying the same current steering idea as above.
When V2 is "off", V4 is "off" as well and V3 operates in active
region as a voltage follower producing high output voltage
(logical "1").
When V2 is "on", it activates V4, driving low voltage (logical
"0") to the output. Again there is a current-steering effect: the
series combination of V2's C-E junction and V4's B-E junction
is in parallel with the series of V3 B-E, V5's anode-cathode
junction, and V4 C-E. The second series combination has the
higher threshold voltage, so no current flows through it, i.e.
V3 base current is deprived. Transistor V3 turns "off" and it
does not impact on the output.
In the middle of the transition, the resistor R3 limits the current
flowing directly through the series connected transistor V3,
diode V5 and transistor V4 that are all conducting. It also limits
the output current in the case of output logical "1" and short
connection to the ground. The strength of the gate may be
increased without proportionally affecting the power
consumption by removing the pull-up and pull-down resistors
from the output stage.
The main advantage of TTL with a "totem-pole" output stage is
the low output resistance at output logical "1". It is determined
by the upper output transistor V3 operating in active region as
an emitter follower. The resistor R3 does not increase the output
resistance since it is connected in the V3 collector and its
influence is compensated by the negative feedback. A
disadvantage of the "totem-pole" output stage is the decreased
voltage level (no more than 3.5 V) of the output logical "1"
(even if the output is unloaded). The reason of this reduction are
the voltage drops across the V3 base–emitter and V5 anode–
cathode junctions.

Explain a TTL NAND gate and its operation,

Computer Engineering
Operation of TTL NAND Gate: Fig.(d) Demonstrates a TTL
NAND gate with a totem pole output. The totem pole output
implies that transistor T4 sits atop T3 in order to give low output
impedance. The low output impedance means a short time
constant RC therefore the output can change rapidly from one
state to the other. T1 is a multiple type emitter transistor. Such
transistor can be thought of like a combination of various
transistors along with a common collector and base. Multiple
emitter transistors along with about 60 emitters have been
developed. In this figure, T1 has 3 emitters thus there can be
three inputs A, B, C. The transistor T2 functions as a phase
splitter since the emitter voltage is out of phase along with the
collector voltage. The transistors T3 and T4 by the totem pole
output, the capacitance CL shows the stray capacitance and so
on. The diode D is added to make sure that T4 is cut off while
output is low. The voltage drop of diode D remains the base-
emitter junction of T4 reverse biased therefore only T3 conducts
while output is low. The operation can be described briefly by
three conditions as specified below:
Condition 1: At least one input is low (that is, 0). Transistor
T1 saturates. Thus, the base voltage of T2 is almost zero. T2 is
cut off and forces T3 to cut off. T4 functions as an emitter
follower and couples a high voltage to load. Output is high (that
is Y=1).
Condition 2: Each input is high. The emitter base junctions of
T1 are reverse biased. The collector base junction of T1 is
forward biased. Therefore, T1 is in reverse active mode. The
collector current of T1 flows in reverse direction. Because this
current is flowing in the base of T2, the transistors T2 and
T3 saturate and then output Y is low.
Condition 3: The circuit is operating under II while one of the
inputs becomes low. The consequent emitter base junction of
T1 starts conducting and T1 base voltage drops to a low
value. Thus, T1 is in forward active mode. The high collector
current of T1 shifts the stored charge in T2 and T3 and hence,
T2 and T3 go to cut-off and T1 saturates and then output Y
returns to high.

Fig.(d) Logic Diagram of TTL NAND Gate with Totem Pole Output