E3-238 ANALOG VLSI CIRCUITS

LAB 5: OPAMP DESIGN

NAME: Sohan Debnath

SR NO.: 04-01-01-10-51-22-1-21104

COURSE: M. Tech in Microelectronics and VLSI Design

DEPARTMENT: Electronic Systems Engineering

GROUP: 8
PROBLEM DESCRIPTION:
In this homework, you are to design a basic two-stage CMOS operational amplifier
(op-amp), as shown in Figure 1, for the specifications given in Table 1. The op-amp
consists of a differential input stage (𝑀1 and 𝑀2) driving a current mirror load (𝑀3
and 𝑀4) followed by a common-source amplifier stage (𝑀7). The devices 𝑀5 and 𝑀7
form the tail current source for the differential stage and the current source load for
the common- source stage. 𝐶c and 𝑅𝑧 are the compensation capacitor and the zero-
nulling resistor.

Table 1 Design specifications @ [Supply voltage = 1.8 V, Load CL = 100 fF, and
Temperature = 27°C]
SN Parameter Symbol Value
1000 V/V
1. Open-loop, differential-mode, DC voltage gain 𝐴0 ≥
(60 dB)
2. Unity-gain frequency 𝑓𝑈𝐺 ≥ 10 MHz
3. Phase margin PM ≥ 75°
4. Common-mode rejection ratio CMRR ≥ 50 dB
5. Power dissipation 𝑃𝑑 ≤ 30 µW

The designing of the op-amp consists of selecting device sizes and biasing
conditions, compensating the op-amp for stability, and simulating the op-amp open-
loop gain (𝐴0), unity-gain frequency (𝑓UG), phase margin (PM), common-mode
rejection ratio (CMRR), common- mode range (CMR), output swing (𝑆), Slew rate
(SR) and power dissipation (𝑃𝑑).
Circuit Diagram:
The circuit diagram of the two-stage op-amp is shown in Fig. 1.

Fig. 1. Schematic of the two-stage op-amp.

The symbol of the two-stage op-amp is shown in Fig. 2.

Fig. 2. Symbol of the two-stage op-amp.

The values of the design parameters are enlisted in Table I.

Table I: Design parameter values of the two-stage op-amp
Parameter Value
𝐿𝑖 (𝑖 = 1,2, … ,7) 500 𝑛𝑚
𝑊1 = 𝑊2 3 𝜇𝑚
𝑊3 = 𝑊4 7 𝜇𝑚
𝑊5 5 𝜇𝑚
𝑊6 10 𝜇𝑚
𝑊7 3 𝜇𝑚
𝐶𝑐 1 𝑝𝐹
𝑅𝑧 10 𝑘Ω
𝑉𝑏 530 mV
DC Analysis:
The schematic of the testbench for DC analysis is shown in Fig. 3.

Fig. 3. Testbench for DC analysis.

 The common mode range (CMR) curve is presented in Fig. 4 where the output voltage
(𝑉𝑜𝑢𝑡 ) is plotted by changing the common mode input voltage (𝑉𝑖𝑐 ).

1.8

1.6

1.4

1.2
Vout (V)

1.0

0.8

0.6

0.4

0.2

0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Vic (V)

Fig. 4. 𝑉𝑜𝑢𝑡 vs. 𝑉𝑖𝑐 (CMR curve).

 The voltage transfer characteristic (VTC) is shown in Fig. 5 by plotting 𝑉𝑜𝑢𝑡 with respect
to the differential input voltage (𝑉𝑖𝑑 ).

1.8

1.6

1.4

1.2 Vout = 0.9 V

Vout (V)

1.0

0.8

0.6

0.4
Vid = -85.84 mV
0.2

0.0
-4 -2 0 2 4
Vid (mV)

Fig. 5. 𝑉𝑜𝑢𝑡 vs. 𝑉𝑖𝑑 (VTC).

 It is observed from Fig. 6 that when 𝑉𝑖𝑑 = −85.84 𝜇𝑉, 𝑉𝑜𝑢𝑡 = 0.9 𝑉 which is the mid-rail
voltage.
Thus, the input referred DC offset voltage is 𝑉𝑜𝑓𝑓𝑠𝑒𝑡 = −85.84 𝜇𝑉.
 The differential mode of DC voltage gain curve is computed by taking the derivative of
VTC with respect to 𝑉𝑖𝑑 and plotted in Fig. 6.

6000

5000

4000
A0 (V/V)

3000

2000

1000

0
-4 -2 0 2 4
Vid (mV)

Fig. 6. The differential mode of DC voltage gain curve.

  The following values are obtained at 𝑉𝑖𝑐 = 0.9 𝑉 and 𝑉𝑖𝑑 = −85.84 𝜇𝑉.
a) DC differential mode voltage gain (𝐴0 ) = 5791 V/V = 75.3 dB.
b) DC common mode voltage gain (𝐴𝑐𝑚0 ) = 0.8398 V/V = -1.5 dB.
c) Bias current into both the input terminals 𝐼𝑏𝑖𝑎𝑠,𝑖𝑛1 = 𝐼𝑏𝑖𝑎𝑠,𝑖𝑛2 = 0.
d) Offset current (𝐼𝑜𝑓𝑓𝑠𝑒𝑡 = |𝐼𝑏𝑖𝑎𝑠,𝑖𝑛1 − 𝐼𝑏𝑖𝑎𝑠,𝑖𝑛2 |) = 0.
e) Positive output saturation limit (𝑉 + ) = 1.784 V.
Negative output saturation limit (𝑉 − ) = 0.12 mV.
f) Power dissipation (𝑃𝑑𝑖𝑠𝑠 = 𝑉𝐷𝐷 ∗ 𝐼𝐷𝐷 ) = 29.16 µW.

AC Analysis:
The schematic of the testbench for AC analysis is shown in Fig. 7.

Fig. 7. Testbench for AC analysis.

The magnitude response of the differential mode voltage gain in open-loop configuration for both
the uncompensated and compensated op-amp is shown in Fig. 8.

80

60

40
Gain magnitude (dB)

20

-20

-40 f =13.3 MHz

Uncompensated f =164.7 MHz
-60 Compensated

1 10 100 1k 10k 100k 1M 10M 100M 1G 10G

Frequency (Hz)

Fig. 8. Magnitude response of differential mode voltage gain.

Fig. 9 presents the phase response of the differential mode voltage gain in open-loop configuration
for both uncompensated and compensated op-amp.

-50

-102.7o
Gain phase (degree)
-100

-150

-194.8o
-200

-250
f =13.3 MHz
Uncompensated f =164.7 MHz
-300 Compensated

1 10 100 1k 10k 100k 1M 10M 100M 1G 10G

Frequency (Hz)

Fig. 9. Phase response of differential mode voltage gain.

The parameters obtained from the AC analysis are enlisted in Table II.
Table II: Parameters obtained from AC analysis
Uncompensated Compensated
Parameter value
op-amp op-amp
0 dB magnitude crossover frequency
164.7 MHz 13.3 MHz
(𝑓0𝑑𝐵 )
Phase at 𝑓0𝑑𝐵 (𝑃ℎ𝑎𝑠𝑒𝑓0𝑑𝐵 ) -194.8° -102.7°
Phase margin (PM) -14.8° 77.3°
Stability Analysis:
The schematic of the testbench for stability analysis is shown in Fig. 10.

Fig. 10. Testbench for stability analysis.

The loop gain for both the uncompensated and compensated op-amp is shown in Fig. 11.

80

60

40
Gain magnitude (dB)

(66.3 MHz,16.64 dB)

20
(162.6 MHz,0 dB)
0
(13.3 MHz,0 dB)

-20
(107.6 MHz,-20.61 dB)

-40

-60 Uncompensated
Compensated
-80
1 10 100 1k 10k 100k 1M 10M 100M 1G 10G
Frequency (Hz)

Fig. 11. Loop gain vs. frequency.

Fig. 12 presents the loop phase for both uncompensated and compensated op-amp.

150

100
Gain phase (degree)

(13.3 MHz, 76.87o)

50

(107.6 MHz, 0)
0 (66.3 MHz, 0)

(162.6 MHz, -16.35o)

-50
Uncompensated
Compensated
-100

1 10 100 1k 10k 100k 1M 10M 100M 1G 10G

Frequency (Hz)

Fig. 12. Loop phase vs. frequency.

The parameters obtained from the stability analysis are enlisted in Table III.
Table III: Parameters obtained from stability analysis
Uncompensated Compensated
Parameter value
op-amp op-amp
Gain margin -16.64 dB 20.61 dB
Phase margin -16.35° 76.87°
Transient Analysis:
The schematic of the testbench for stability analysis is shown in Fig. 13.

Fig. 13. Testbench for stability analysis.

The response to a positive step input for the uncompensated and compensated op-amp in voltage
follower configuration is shown in Fig. 14(a) and the negative step response in shown in Fig. 14(b).

1.8 1.2
Input
1.0
Output, uncompensated
Output, compensated
1.6

0.8
Voltage (V)

Voltage (V)

1.4
0.6

1.2 0.4

Input 0.2
1.0 Output, uncompensated
Output, compensated
0.0
0 100 200 0 100 200
Time (ns) Time (ns)

(a) (b)

Fig. 14. Step response for uncompensated and compensated op-amp (a) positive step and (b) negative step.
The slew rates obtained from the transient analysis are enlisted in Table IV.
Table IV: Slew rates obtained from transient analysis
Uncompensated Compensated
Slew rate
op-amp op-amp
Positive slew rate 485 𝑉𝜇𝑠 −1 10.4 𝑉𝜇𝑠 −1
Negative slew rate 51.1 𝑉𝜇𝑠 −1 6 𝑉𝜇𝑠 −1

All the op-amp parameters are summarized in Table V.

Table V: Op-amp parameter value.
Value
Parameter Symbol Uncompensated Compensated
op-amp op-amp
Input referred DC offset voltage 𝑉𝑜𝑓𝑓𝑠𝑒𝑡 −85.84 𝜇𝑉 −85.84 𝜇𝑉
Open-loop, differential-mode, DC
𝐴0 75.3 𝑑𝐵 75.3 𝑑𝐵
voltage gain
DC common mode voltage gain 𝐴𝑐𝑚0 −1.5 𝑑𝐵 −1.5 𝑑𝐵
Common-mode rejection ratio 𝐶𝑀𝑅𝑅 76.8 𝑑𝐵 76.8 𝑑𝐵
Bias current 𝐼𝑏𝑖𝑎𝑠 0 0
Offset current 𝐼𝑜𝑓𝑓𝑠𝑒𝑡 0 0
Positive output saturation limit 𝑉+ 1.784 𝑉 1.784 𝑉
Negative output saturation limit 𝑉− 0.12 𝑚𝑉 0.12 𝑚𝑉
Power dissipation 𝑃𝑑𝑖𝑠𝑠 29.16 𝜇𝑊 29.16 𝜇𝑊
0 dB magnitude crossover frequency 𝑓0𝑑𝐵 164.7 𝑀𝐻𝑧 13.3 𝑀𝐻𝑧
Gain margin GM −16.64 𝑑𝐵 20.61 𝑑𝐵
Phase margin PM −16.35° 76.87°
Positive slew rate - 485 𝑉𝜇𝑠 −1 10.4 𝑉𝜇𝑠 −1
Negative slew rate - 51.1 𝑉𝜇𝑠 −1 6 𝑉𝜇𝑠 −1