UM1653

User manual
STM32 Advanced NAND Flash Driver for SLC NAND

Introduction
The NAND driver library for STM32 is a generic library from which STM32 can access
NAND with advanced features like garbage collection, wear leveling, bad block
management, ECC checking etc.
The NAND Flash driver supports dynamic NAND Flash detection based on the Device ID.
The driver automatically detects the mounted SLC NAND Flash and works accordingly
(described in more detail in Section 2.8). This solution runs on the STM32F1, STM32F2 &
STM32F4 series of microcontrollers using the FSMC interface.
The board can run in two modes: USB Mass Storage mode and Standalone mode.
 In USB Mass Storage mode, the NAND Flash works as USB mass storage media.
 In Standalone mode, the .bmp images stored in the ‘pics’ folder of the root directory are
read using FatFS file system, and displayed on the onboard TFT LCD.
Six evaluation boards are available for this SLC NAND FLASH Driver:
 STEVAL_CCM006V1: USB mass storage mode demo using STM32F103ZET6
 STEVAL_CCM006V2: Standalone mode demo using STM32F103ZET6
 STEVAL_CCM007V1: USB Mass Storage mode Demo using STM32F205ZET6
 STEVAL_CCM007V2: Standalone mode Demo using STM32F205ZET6
 STEVAL_CCM008V1: USB Mass Storage mode Demo using STM32F405ZGT6
 STEVAL_CCM008V2: Standalone mode Demo using STM32F405ZGT6
NAND is a non-volatile Flash memory device where address lines are multiplexed with data
input/output and commands input. The NAND driver library has the following features:
1. Supports both FAT file system and USB MSC device.
2. Supports SLC NAND with page size of 512 Bytes & 2 KBytes.
3. Garbage collection.
4. Wear leveling.
5. Bad block management.
6. ECC check.
This document applies to the following microcontrollers:
 STM32L151xD, STM32L152xD, STM32L1562xD.
 STM32F405/415, STM32F407/417, STM32F427/437, STM32F429/439 lines.
 STM32F2 Series.
 STM32F103xC, STM32F103xD and STM32F103xE, STM32F103xF, STM32F103xG,
STM32F101xC, STM32F101xD and STM32F101xE, STM32F101xF, STM32F101xG,
STM32F100xC, STM32F100xD, STM32F100xE.

November 2013 DocID025024 Rev 1 1/45

www.st.com
Contents UM1653

Contents

1 STM32 NAND driver blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 STM32 USB peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 USB mass storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 FSMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 NAND architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5 NAND pin mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2 NAND driver firmware modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2 Wear leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.3 ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.1 Hamming code for NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.2 Error detection and correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5 Look up table (LUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6 File system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.7 NAND driver files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.7.1 nand_drv.c, nand_drv.h functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.7.2 fsmc_nand_if.c, fsmc_nand_if.h functions . . . . . . . . . . . . . . . . . . . . . . . 28
2.8 Supported NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3 NAND evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.1 Working with evaluation boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.1.1 Running in USB Mass Storage mode (STEVAL-CCM006/7/8V1) . . . . . 36
3.1.2 Running in Standalone mode (STEVAL-CCM006/7/8V2) . . . . . . . . . . . 37
3.2 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.3 NAND evaluation board images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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UM1653 List of tables

List of tables

Table 1. Spare area format for small NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. Spare area format for large NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. File system interface functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. NAND_Init . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. NAND_Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. NAND_Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. NAND_WriteECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. NAND_PostWriteECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. NAND_CleanLUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. NAND_WearLeveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. SBLK_NAND_WearLeveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. LBLK_NAND_WearLeveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 13. NAND_GetFreeBlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 14. SBLK_NAND_ReadSpareArea. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 15. LBLK_NAND_ReadSpareArea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 16. WriteSpareArea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 17. NAND_Copy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 18. NAND_CopyBack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 19. NAND_Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 20. NAND_PostWrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 21. SBLK_NAND_PostWrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 22. LBLK_NAND_PostWrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 23. NAND_GarbageCollection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 24. NAND_UpdateWearLevelCounter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 25. NAND_ConvertPhyAddress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 26. NAND_BuildLUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 27. SBLK_NAND_BuildLUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 28. LBLK_NAND_BuildLUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 29. GetParity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 30. Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 31. WritePage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 32. SBLK_NAND_WritePage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 33. LBLK_NAND_WritePage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 34. ReadPage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 35. SBLK_NAND_ReadPage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 36. LBLK_NAND_ReadPage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 37. BitCount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 38. FSMC_SelectNANDType . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 39. FSMC_NAND_NON_ONFI_Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 40. FSMC_NAND_Init. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 41. FSMC_NAND_ReadID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 42. FSMC_NAND_WriteSmallPage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 43. FSMC_NAND_ReadSmallPage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 44. FSMC_NAND_WriteSpareArea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 45. FSMC_NAND_ReadSpareArea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 46. FSMC_NAND_EraseBlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 47. FSMC_NAND_Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 48. FSMC_NAND_GetStatus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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List of tables UM1653

Table 49. FSMC_SBLK_NAND_CopyBack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 50. FSMC_LBLK_NAND_CopyBack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 51. FSMC_NAND_ReadStatus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 52. FSMC_NAND_AddressIncrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 53. FSMC_NAND_ONFI_Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 54. FSMC_SBLK_NAND_SendAddress. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 55. FSMC_LBLK_NAND_SendAddress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 56. Supported NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 57. NAND Flash driver file code size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 58. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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UM1653 List of figures

List of figures

Figure 1. Application architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. BOT protocol architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. NAND block architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Flow of wear leveling mechanism for STEVAL-CCM006V1 . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Flow of wear leveling mechanism for STEVAL-CCM007V1/ 008V1. . . . . . . . . . . . . . . . . . 13
Figure 6. Example of decomposition of a data packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Flow chart for error detection and correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Flow chart for bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. Flow chart for File System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Evaluation board: top side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 11. Evaluation board: bottom side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 12. Demo running in Standalone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 13. Microcontroller schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 14. USB Full Speed schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 15. USB High Speed schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 16. Touch Screen schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 17. TFT Connector schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 18. Power schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 19. NAND Flash schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 20. NAND Flash Signals schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 21. JTAG schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 22. Top side of PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 23. Bottom side of PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

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STM32 NAND driver blocks UM1653

1 STM32 NAND driver blocks

This document describes how to connect a NAND Flash device to an STM32 family
microcontroller and communicate using FSMC. NAND driver library for STM32 is a generic
library where STM32 can access NAND with some advanced features like garbage
collection, wear leveling, bad block management, ECC checking etc. The library supports
both FAT file system and USB MSC device.

Figure 1. Application architecture

STM32 Lib

File System

Flash translation layer

FTL Interface

Garbage collection Wear Leveling

Hardware Adaption Layer

ECC: Error correction code
LLD ECC BBM BBM: Bad block management
LLD: Low level driver

NAND Flash Device

MS33215V1

1.1 STM32 USB peripheral

The STM32F embeds a USB peripheral that supports USB full-speed and high speed.
The development of Endpoint and support suspend / resume are configured by software.
The USB device provides a connection between the host and the function implemented by
the microcontroller.
Data transfer between the host and the memory system is through a dedicated packet buffer
memory accessed directly from the USB device. The size of buffer memory is dependent on
the number of endpoints used and the maximum packet size. This dedicated memory is 512
bytes.

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1.2 USB mass storage

The USB device is provided to the host as a particular class, which determines how the host
cross reacts with the embedded system.
In our case, the USB device must appear in the driver as a Mass Storage Class USB, which
defines that SCSI commands will be used with the protocol “bulk-only transport” (BOT).

Bulk-only-transport (BOT)
A general BOT transaction is based on a simple basic state machine. It begins with ready
state (idle state) and if a CBW is received from the host three cases can be managed:
 DATA-OUT-STAGE: when direction flag is set to 0, Device shall prepare itself to receive
an amount of data indicated in dCBWDataTransferLength in the CBW block. At the end
of data transfer a CSW is returned with the remaining data length and the STATUS
field.
 DATA-IN-STAGE: when direction flag is set to 1, Device shall prepare itself to send an
amount of data indicated in dCBWDataTransferLength in the CBW block. At the end of
data transfer a CSW is returned with the remaining data length and the STATUS field.
 ZERO DATA: no data stage is needed so CSW block is sent immediately after CBW.
The BOT transport protocol encapsulates SCSI commands and transfers them in three
steps:
1. Send the command block CBW.
2. Transfer data.
3. Return the status of the block CSW.

Figure 2. BOT protocol architecture

Ready

Command transport
CBW

Data Out Data In

Status
Transport

MS33216V1

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Bulk-Only Transport State machine

#define BOT_IDLE 0 //Idle state
#define BOT_DATA_OUT 1 //Data Out state
#define BOT_DATA_IN 2 //Data In state
#define BOT_DATA_IN_LAST 3 //Last Data In Last
#define BOT_CSW_Send 4 //Command Status Wrapper
#define BOT_ERROR 5 //error state

#define BOT_CBW_SIGNATURE 0x43425355 //1st 4 bytes of CBW pkt

#define BOT_CSW_SIGNATURE 0x53425355 //1st 4 bytes of CSW pkt

#define BOT_CBW_PACKET_LENGTH 31
#define CSW_DATA_LENGTH 13

CSW Status Definitions

#define CSW_CMD_PASSED 0x00
#define CSW_CMD_FAILED 0x01
#define CSW_PHASE_ERROR 0x02

#define SEND_CSW_DISABLE 0
#define SEND_CSW_ENABLE 1

#define DIR_IN 0
#define DIR_OUT 1
#define BOTH_DIR 2

1.3 FSMC
The FSMC block is able to communicate with the synchronous and asynchronous memory.
Its main purpose is to:
 Translate the AHB protocol transactions of external devices
 Respect the access time of external devices
The FSMC provides a single access to an external device.
The FSMC has four blocks:
 AHB Interface
 Controller NOR Flash / PSRAM
 Controller NAND Flash / PC Card
 Interface to external device
The FSMC generates the appropriate signals to drive the NAND Flash memory.
The FSMC controller consists of two blocks of code error correction hardware. They reduce
the workload on the host processor when processing code error correction by the system
software. These two blocks are identical and are respectively associated with banks 2 and
3. The ECC algorithm used in the FSMC can perform 1- and 2-bit error detection.

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1.4 NAND architecture

NAND is a non-volatile Flash memory device where address lines are multiplexed with data
input/output as well as with commands input.
 NAND Flash consists of a number of blocks. Each block consists of a number of pages,
typically 32 or 64.
 Pages can be written individually, one at a time. When writing to a page, bits can only
be written from 1 to 0.
 The erase operation is done by block. Erase operation makes all the memory bits of all
the pages in the block to logical 1.
The small NAND Flash contains 528-byte pages (512 data area and 16 byte spare area).
The page size for 2K NAND is 2112 (2048 data and 64 spare area).
The page size for 4K NAND is 4224 (4096 data and 128 spare area).
The page size for 8K NAND is 8448 (8192 data and 256 spare area).

Figure 3. NAND block architecture

Block 0 0x000
Page 0
Block 1 Data
Page 1 +
Spare area

Page m 0x83F
2K Physical pages
Physical block
or
Block N 0X000
Data
Block N-1
Spare area 0x200
0x20F
512 Physical page (unit)
Physical zone

MS33217V1

The spare area contains information about the page and the code error correction:
For small page (512 + 16 Byte) NAND Flash:

Table 1. Spare area format for small NAND Flash

Logical Index Block Status Data Status Wear Leveling counter ECC

For Large page (2048 + 64 Byte) NAND Flash:

Table 2. Spare area format for large NAND Flash

Block Status Data Status Logical Index Wear Leveling counter ECC

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 The Logical Index contains the logical address of the block.

 The Block Status returns the status of the block if it is valid or not.
 The Data Status informs if the page is valid or invalid.
 Wear Leveling Counter is the number of times the block has been erased.
 The ECC is the error correction code calculated for each page.
NAND INTERFACE
 x8 or x16 bus width
 Multiplexed Address/ Data
 Pinout compatibility for all densities
SUPPLY VOLTAGE
 1.8V device: VCC = 1.65 to 1.95V
 3.0V device: VCC = 2.7 to 3.6V
PAGE SIZE
 x8 device: (512 + 16 spare) Bytes
 x16 device: (256 + 8 spare) Words
 x8 device: (2048 + 64 spare) Bytes
 x16 device: (1024 + 32 spare) Words

1.5 NAND pin mapping

I/O 8-15 Data Input/Outputs: for x16 devices. The I/O pins are used to input data,
address, command and output data during read operation.
I/O 0-7 Data Input/Outputs: Address Inputs, or Command Inputs for x8 and x16 devices.
ALE Address Latch Enable: When active, an address can be written.
CLE Command Latch Enable: This pin should be LOW while writing commands to the
command register.
CE/ Chip Enable: The CE input enables the device. Signal is active low. If the signal
is inactive the device will be in standby.
RE/ Read Enable: The RE input is the serial data out control. Signal is active low to
out data.
RB/ Ready/Busy (open-drain output) The RB output provides the status of the device
operation. It is an open drain output, hence should be connected to a GPIO with
pull-up.
 LOW: a program, erase or read operation is in process.
 HIGH: the process is complete.
WE/ Write Enable: The WE input controls write operations to I/O port. Commands,
data and address are latched on the rising edge of WE.
WP/ Write Protect: Typically connected to Vcc, but may also be connected to a GPIO.

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2 NAND driver firmware modules

The NAND driver library has the following modules:

1. Garbage collection
2. Wear leveling
3. Bad block management
4. ECC check
5. LUT
6. FAT file system

2.1 Garbage collection

The Garbage Collection software copies the valid data into a new (free) area and erases the
original invalid data.
Garbage Collection is performed when a virtual block is full or the number of free pages in
the whole device is lower than a specified threshold value.
The basic operations involved in Garbage Collection are the following:
1. The virtual blocks meeting the conditions are selected for erasure.
2. The valid physical pages are copied into a free area.
3. The selected physical blocks are erased.
As virtual blocks can contain more than one physical block, the Garbage Collection may
erase more than one physical block.

2.2 Wear leveling

Wear leveling is a technique to increase the lifetime of NAND Flash memory. The number of
reliable write cycles in NAND Flash is 100,000 erase/write cycles. If some of the blocks are
written repeatedly, wearing of these blocks will happen earlier than other blocks. To balance
the erase cycles over all the blocks, a wear leveling technique is introduced.
All new data is written to the empty blocks. The memory controller selects the new empty
block based on the number of write / erase cycles it has experienced.
After the new data is written, the controller updates the LUT to point to the position of the
selected physical block. The block containing the old data is erased and the number of
write/erase cycles increments.

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Figure 4. Flow of wear leveling mechanism for STEVAL-CCM006V1

USB_Istr
main
CTR_LP

Set_SystemA
Write_Memory

MAL_Config
MAL_Write

MAL_Init
NAND_Write

NAND_Init

Yes Is another Zone

NAND_CleanLUT
requested?

NAND_WearLeveling No

Write in current Zone

of NAND Flash
No Small Block
NAND?
LBLK_NAND_WearLeveling
Yes

SBLK_NAND_WearLeveling
MS33218V1

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Figure 5. Flow of wear leveling mechanism for STEVAL-CCM007V1/ 008V1

OTG_FS_IRQHandler

main USBD_OTG_ISR_Handler

DCD_HandleOutEP_ISR
NAND_Init

USBD_DataOutStage
Yes Is another Zone
NAND_CleanLUT
requested?
USBD_MSC_DataOut
No
NAND_WearLeveling
Write in current Zone MSC_BOT_Data_Out
of NAND Flash

SCSI_ProcessCmd

No
Small Block SCSI_Write10
NAND?
LBLK_NAND_WearLeveling Yes SCSI_ProcessWrite

SBLK_NAND_WearLeveling
STORAGE_Write

NAND_Write

MS33219V1

The above figure gives an overview of the firmware flow with respect to the way the Wear
Leveling Mechanism is implemented.
Let us consider a scenario in which the host is trying to send the data to the controller via
USB and write it to the NAND Flash. The corresponding CBW has to be decoded. The
function given below is called in such a case, to write to the memory which uses the
information provided from the CBW

void SCSI_Write10_Cmd(uint8_t lun, uint32_t LBA, uint32_t BlockNbr)

This function has the following arguments, the logical unit number, Logical block address
(LBA) and the block number. The LBA passed from the host is sequential and maps to the
address of the block in NAND Flash memory which comes out to be sequential.
A structure is used to store the address:
typedef struct
{
uint16_t Zone;
uint16_t Block;
uint16_t Page;
} NAND_ADDRESS;

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NAND_ADDRESS NAND_GetAddress (uint32_t Address)

The above function translates a logical address into a physical one and stores it in a
structure element of type NAND_ADDRESS.
While writing to the NAND, the wear level algorithm should return the block to be written of
which the erase count is least. To maintain the list of USED, FREE and BAD blocks an array
is maintained: LUT[ ].
The previously fetched address for writing, and the free block obtained with least erase
counts are swapped in LUT and updated, this ensures that the write takes place at the block
with least erase count.

uint16_t NAND_GetFreeBlock (void)

The above function is called to get the free block for swap. The function returns the first free
block it finds in the LUT[ ]. This implies that the LUT[ ] should have the free blocks arranged
in the increasing order of erase count. The LUT[ ] is updated by the following function.

uint16_t NAND_BuildLUT (uint8_t ZoneNbr)

The above function arranges the bad block at the bottom of the array and the used and free
blocks are located in the upper part of the array.

uint16_t NAND_WearLeveling (void)

The above function sorts the free blocks in the ascending order based on the wear level
count. Now, the free block used for writing in the NAND would be the one with the least
erase count.

2.3 ECC
Unlike NOR Flash memory that does not require error correction code, NAND memory
needs to ensure data integrity.
The disadvantage of the NAND configuration is that when a cell is read, the sense amplifier
detects a signal much lower than for the NOR configuration because many transistors are in
series. Therefore access to a cell is not straightforward and must necessarily go through all
the cells in series which reduces precision and makes code error correction required.
There are three error correction codes:
 The Hamming code can correct only one bit error.
 The Reed Solomon code can correct more errors.
 The BCH code can correct many errors and is more efficient than Reed Solomon.

2.3.1 Hamming code for NAND Flash

The Hamming code algorithm used by NAND Flash-based applications calculates two
values of ECC for a data packet. Each bit in the values of ECC parity represents half of the
bits of the data packet.

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For one byte

The trick is how the data bits are partitioned for each of the parity calculations. To calculate
ECC, the data bits are first divided into halves, quarters, eighths and so on until you reach
the bit unit.

Figure 6. Example of decomposition of a data packet

Bit position 7 6 5 4 3 2 1 0
1 1 1 1 Even bits

0 1 0 1 Even quarters

0 1 0 1 Even halves

Data packet 0 1 0 1 0 1 0 1

0 1 0 1 Odd bits

0 1 0 1 Odd quarters

0 0 0 0 Odd halves
MS33220V1

After the partition of the data packet, the parity of each group is calculated to generate two
values of ECC. The results are concatenated to form the ECC values.
ECC even = 0 ^ 1 ^ 0 ^ 1, 0 ^ 1 ^ 0 ^ 1, 1 ^ 1 ^ 1 ^ 1 = 000
ECC odd = 0 ^ 1 ^ 0 ^ 1, 0 ^ 1 ^ 0 ^ 1, 0 ^ 0 ^ 0 ^ 0 = 000
These ECC bits allow us to identify the error position when the data packet is analyzed at a
later date. Data packets require larger number of ECC values. Each data packet of 2n-bit
ECC requires a value of n bits.
Based on this calculation, both the data packet and the ECC values are programmed into
the NAND Flash memory. Later, when the data packet is read from the NAND, the ECC
values are recalculated. Data corruption is indicated when the values of the newly
calculated ECC differ from those programmed into the NAND Flash.
Applying “exclusive or” to all four values of ECC (two old and two new), one can determine
whether one or more bits have been corrupted. If the result is 000 there is no corruption. If
the result is 111 then a single bit is wrong. If two or more bits were damaged, this code
allows the detection of two errors and the correction of only one bit.
ECCeven (old) ^ ECCodd (old) ^ ECCeven (new) ^ ECCodd (new)
When the result shows that a bit has been corrupted, the address of this bit can be identified
by the application of “exclusive or” on both ECC odd values
ECCodd (old) ^ ECCodd (new)
The erroneous bit position is identified by the position of the 1 in the "exclusive or" value.

For a package of several bytes

As the size of data packets increases, the Hamming algorithm becomes more efficient.
Each doubling of the data packet requires two additional bits in the ECC. A data packet size
of 512 bytes (the size of a page of the NAND memory used) requires 24 bits of ECC. The
extension of a 1 byte packet to a 512 byte packet requires only a change to the size of data
partitions, the algorithm remains the same.

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2.3.2 Error detection and correction

Figure 7. Flow chart for error detection and correction

New ECC generated

during read

XOR previous ECC

with new ECC

No No
All results >1 bit
= zero? = zero?

Yes

12 bit No
= one?

24 bit data = 0 12 bit data = 1 All other 23 bit data = 1

No Error Correctable error Non Correctable error ECC Error

MS33221V1

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2.4 Bad block management

Bad blocks contain one or more invalid bits whose reliability is not guaranteed. They may be
present when the device is shipped, or may develop during the lifetime of the device.

Figure 8. Flow chart for bad block management

Start

Block address = Block 0

Increment block address

Block No
status Update bad block table
=FFh?
Yes

Last No
block?

Yes

End

MS33222V1

2.5 Look up table (LUT)

The LUT is used to find the Application Block Number corresponding to the Logical address
(SCSI_LBA). All blocks are scanned and User data is read from the Spare area of each
block of NAND Flash to build the LUT.

2.6 File system

The free file system used in the NAND library is FAT_FS_ELM from ChaN. The NAND file
system interface module “ff_user_interface.c” allows interfacing of file systems with the
NAND driver. In standalone mode it displays the .bmp images stored in the “pics” folder of
NAND Flash. This module should be ported to the selected file system.

Table 3. File system interface functions

Function Description

disk_initialize Initialize disk drive.

disk_read Interface function for a logical page read.
disk_write Interface function for a logical page write.
disk_status Interface function for testing if unit is ready.
disk_ioctl Control device-dependent features.

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Figure 9. Flow chart for File System

NAND

Main
USB

FAT_FS not defined

Set_System USB_Disconnect_Config FAT_FS

MAL_
Config

FSMC Clock Enable

MAL_Init Set_USBClock
USB_Interrupts_Config
USB_Init

FAT_FS not defined

NAND_Init

disk_initialize

read write

disk_read disk_write

NAND_Read(sector, buff, 512); NAND_Write(sector, (BYTE*)buff, 512);

NAND_Post_Write

PreCopy old first pages

PostCopy remaining Pages

Assign LBA to New block

MS32851V1

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2.7 NAND driver files

2.7.1 nand_drv.c, nand_drv.h functions

Table 4. NAND_Init
Function name NAND_Init.
Prototype uint16_t NAND_Init(void)
Behavior description Initializes NAND Interface
Input parameter None
Status of NAND Initialization. This parameter can be:
Output parameter – NAND_OK: when the NAND is OK.
– NAND_FAIL: when NAND fails to initialize.

Table 5. NAND_Write
Function name NAND_Write.
uint16_t NAND_Write(uint32_t Memory_Offset,
Prototype uint8_t *Writebuff,
uint16_t Transfer_Length)
Behavior description Writes one sector at once
Memory_Offset: Memory Offset.
Input parameter Writebuff: Pointer to the data to be written.
Transfer_Length: Number of byte to write.
Status of NAND Write. This parameter can be:
Output parameter – NAND_OK: when the NAND Write is successful
– NAND_FAIL: when NAND fails to Write.

Table 6. NAND_Read
Function name NAND_Read.
uint16_t NAND_Read(uint32_t Memory_Offset,
Prototype uint8_t *Readbuff,
uint16_t Transfer_Length)
Behavior description Reads sectors.
Memory_Offset: Memory Offset.
Input parameter Readbuff: Pointer to store the read data.
Transfer_Length: Number of byte to read.
Status of NAND Read. This parameter can be:
Output parameter – NAND_OK: when the NAND Read is successful.
– NAND_FAIL: when NAND fails to Read.

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Table 7. NAND_WriteECC
Function name NAND_WriteECC.
uint16_t NAND_WriteECC(uint32_t Memory_Offset,
Prototype uint8_t *Writebuff,
uint16_t NumByte)
Behavior description Writes one sector & copy rest Block during ECC Correctable Error Case.
Memory_Offset: Memory Offset.
Input parameter Writebuff: Pointer to the data to be written.
Transfer_Length: Number of byte to write.
Status of NAND Write. This parameter can be:
Output parameter – NAND_OK: when the NAND Write is successful
– NAND_FAIL: when NAND fails to Write

Table 8. NAND_PostWriteECC
Function name NAND_PostWriteECC.
Prototype uint16_t NAND_PostWriteECC(void)
Behavior description Copies whole block after writing corrected page in ECC Correction.
Input parameter None
Output parameter Status of NAND Write.

Table 9. NAND_CleanLUT
Function name NAND_CleanLUT.
Prototype uint16_t NAND_CleanLUT (uint8_t ZoneNum)
Behavior description Rebuilds the Look Up Table.
Input parameter ZoneNbr: Zone Number to Rebuild the Look Up Table.
Status of NAND Build look up table. This parameter can be:
Output parameter – NAND_OK: when the NAND Clean is successful.
– NAND_FAIL: when NAND fails to clean look up table.

Table 10. NAND_WearLeveling

Function name NAND_WearLeveling.
Prototype uint16_t NAND_WearLeveling (uint8_t ZoneNumber)
Behavior description Builds the Look Up Table According to the Wear Count.
Input parameter ZoneNumber: Zone Number.
Status of NAND wear Leveling. This parameter can be:
Output parameter – NAND_OK: when the NAND wear leveling is successful.
– NAND_FAIL: when NAND fails to wear leveling.

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Table 11. SBLK_NAND_WearLeveling

Function name SBLK_NAND_WearLeveling.
Prototype uint16_t SBLK_NAND_WearLeveling (uint8_t ZoneNumber)
Behavior description Builds the Look Up Table According to the Wear Count.
Input parameter ZoneNumber: Zone Number.
Status of SBLK_NAND_WearLeveling. This parameter can be:
Output parameter – NAND_OK: when the NAND wear leveling is successful
– NAND_FAIL: when NAND fails to wear leveling.

Table 12. LBLK_NAND_WearLeveling

Function name LBLK_NAND_WearLeveling.
Prototype uint16_t LBLK_NAND_WearLeveling (uint8_t ZoneNumber)
Behavior description Builds the Look Up Table According to the Wear Count.
Input parameter ZoneNumber: Zone Number.
Status of LBLK_NAND_WearLeveling. This parameter can be:
Output parameter – NAND_OK: when the NAND wear leveling is successful
– NAND_FAIL: when NAND fails to wear leveling.

Table 13. NAND_GetFreeBlock

Function name NAND_GetFreeBlock.
Prototype uint16_t NAND_GetFreeBlock (void)
Behavior description Looks for a free Block for data exchange from Look Up Table.
Input parameter None
Output parameter Logical Block Number of free Block.

Table 14. SBLK_NAND_ReadSpareArea

Function name SBLK_NAND_ReadSpareArea.
Prototype SPARE_AREA SBLK_NAND_ReadSpareArea (uint32_t address)
Behavior description Page Number in multiple of 512 Byte per Page.
Input parameter address: Corresponding Page Number of Spare Area to be read.
Output parameter SPARE AREA after reading.

Table 15. LBLK_NAND_ReadSpareArea

Function name LBLK_NAND_ReadSpareArea.
Prototype LBLK_SPARE_AREA LBLK_NAND_ReadSpareArea (uint32_t address)
Behavior description Page Number in multiple of 512 Byte per Page.
Input parameter address: Corresponding Page Number of Spare Area to be read.
Output parameter LBLK_SPARE_AREA after reading.

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Table 16. WriteSpareArea

Function name WriteSpareArea.
uint16_t WriteSpareArea (uint32_t address,
Prototype
uint8_t *buff)
Behavior description Page Number in multiple of 512 Byte.
address: Corresponding Page Number of Spare Area to be read.
Input parameter
buff: Pointer to the data to be written in SPARE AREA.
Status of WriteSpareArea. This parameter can be:
Output parameter – NAND_OK: when Write SPARE AREA is successful.
– NAND_FAIL: when Write SPARE AREA fails to Write.

Table 17. NAND_Copy

Function name NAND_Copy.
uint16_t NAND_Copy (NAND_ADDRESS Address_Src,
Prototype NAND_ADDRESS Address_Dest,
uint16_t PageToCopy)
Behavior description Copies pages from source to destination.
Address_Src: Source Address.
Input parameter Address_Dest: Destination Address.
PageToCopy: Number of Page to copy.
Status of NAND Copy. This parameter can be:
Output parameter – NAND_OK: when the NAND copy is successful
– NAND_FAIL: when NAND fails to copy.

Table 18. NAND_CopyBack

Function name NAND_CopyBack.
uint16_t NAND_CopyBack (NAND_ADDRESS Address_Src,
Prototype NAND_ADDRESS Address_Dest,
uint16_t PageToCopy)
Copies pages from Source to Destination. (Source & Destination address
Behavior description
must have same page number).
Address_Src: Source Address.
Input parameter Address_Dest: Destination Address.
PageToCopy: Number of Page to copy
Status of NAND Copy. This parameter can be:
Output parameter – NAND_OK: when the NAND copy is successful
– NAND_FAIL: when NAND fails to copy.

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Table 19. NAND_Format

Function name NAND_Format.
Prototype uint16_t NAND_Format (void)
Behavior description Format the entire NAND Flash.
Input parameter None
Status of NAND Format. This parameter can be:
Output parameter – NAND_OK: when the NAND Format is successful
– NAND_FAIL: when NAND fails to Format.

Table 20. NAND_PostWrite

Function name NAND_PostWrite.
Prototype uint16_t NAND_PostWrite (void)
Behavior description NAND Post Write.
Input parameter None
Status of NAND Post Write. This parameter can be:
Output parameter – NAND_OK: when the NAND Post Write is successful
– NAND_FAIL: when NAND fails to Post Write.

Table 21. SBLK_NAND_PostWrite

Function name SBLK_NAND_PostWrite.
Prototype void SBLK_NAND_PostWrite (void)
Behavior description Small Block NAND_PostWrite.
Input parameter None
Output parameter None

Table 22. LBLK_NAND_PostWrite

Function name LBLK_NAND_PostWrite.
Prototype void LBLK_NAND_PostWrite (void)
Behavior description Large Block NAND Post Write.
Input parameter None
Output parameter None

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Table 23. NAND_GarbageCollection

Function name NAND_GarbageCollection.
Prototype uint16_t NAND_GarbageCollection(void)
Behavior description Erases Blocks every time the write operation is stopped.
Input parameter None
Status of NAND Garbage collection. This parameter can be:
Output parameter – NAND_OK: when the NAND Garbage collection is successful
– NAND_FAIL: when NAND fails to Garbage collection.

Table 24. NAND_UpdateWearLevelCounter

Function name NAND_UpdateWearLevelCounter.
Prototype uint16_t NAND_UpdateWearLevelCounter (NAND_ADDRESS Address)
Behavior description Increments the value of Wear Level counter after every erase.
Input parameter Address: Logical Address.
Status of NAND Update Wear Level. This parameter can be:
Output parameter – NAND_OK: when the NAND Update Wear Level is successful
– NAND_FAIL: when NAND fails to Update Wear Level.

Table 25. NAND_ConvertPhyAddress

Function name NAND_ConvertPhyAddress.
Prototype NAND_ADDRESS NAND_ConvertPhyAddress (uint32_t Address)
Behavior description Converts Memory Offset into Physical Address.
Input parameter Address: Memory Offset in Multiple of 512B(0,512/512,1024/512...).
Output parameter Physical Address.

Table 26. NAND_BuildLUT

Function name NAND_BuildLUT.
Prototype uint16_t NAND_BuildLUT (uint8_t Zone)
Behavior description Builds the Look Up Table.
Input parameter ZoneNbr: The Zone Number.
Status of NAND Build Look Up Table. This parameter can be:
Output parameter – NAND_OK: when the NAND Build Look Up Table is successful
– NAND_FAIL: when NAND fails to Build Look Up Table.

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Table 27. SBLK_NAND_BuildLUT

Function name SBLK_NAND_BuildLUT.
Prototype uint16_t SBLK_NAND_BuildLUT (uint8_t ZoneNumber)
Behavior description Builds the Look Up Table.
Input parameter ZoneNbr: The Zone Number.
Status of NAND Build Look Up Table. This parameter can be:
Output parameter – NAND_OK: when the NAND Build Look Up Table is successful
– NAND_FAIL: when NAND fails to Build Look Up Table.

Table 28. LBLK_NAND_BuildLUT

Function name LBLK_NAND_BuildLUT.
Prototype uint16_t LBLK_NAND_BuildLUT (uint8_t ZoneNbr)
Behavior description Builds the Look Up Table.
Input parameter ZoneNbr: The Zone Number.
Status of NAND Build Look Up Table. This parameter can be:
Output parameter – NAND_OK: when the NAND Build Look Up Table is successful
– NAND_FAIL: when NAND fails to Build Look Up Table.

Table 29. GetParity

Function name GetParity.
Prototype uint8_t GetParity (uint16_t in_value)
Behavior description Calculate parity.
Input parameter in_value: 16-bit value.
Output parameter Status.

Table 30. Swap

Function name Swap.
Prototype uint16_t Swap (uint16_t in)
Behavior description Swaps a 16-bit.
Input parameter in: 16-bit value.
Output parameter swapped value.

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Table 31. WritePage

Function name WritePage.
void NAND_WritePage(NAND_ADDRESS Address,
Prototype uint8_t *buff,
uint16_t len)
Behavior description Writes a page & Corresponding SPARE AREA.
Address: The address of the page to write.
Input parameter *buff: The buffer to write in.
len: The Number of page to write.
Output parameter None

Table 32. SBLK_NAND_WritePage

Function name SBLK_NAND_WritePage.
void SBLK_NAND_WritePage(NAND_ADDRESS Address,
Prototype uint8_t *buff,
uint16_t len)
Behavior description Writes page & Corresponding ECC in SPARE AREA in Small Block NAND.
Address: The address of the page to write.
Input parameter *buff: The buffer to write in.
len: The Number of page to write.
Output parameter None

Table 33. LBLK_NAND_WritePage

Function name LBLK_NAND_WritePage.
void LBLK_NAND_WritePage(NAND_ADDRESS Address,
Prototype uint8_t *buff,
uint16_t len)
Write a page & Corresponding ECC in SPARE AREA in Small Block
Behavior description
NAND.
Address: The address of the page to write.
Input parameter *buff: The buffer to write in.
len: The Number of page to write.
Output parameter None

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Table 34. ReadPage

Function name ReadPage.
void NAND_ReadPage (NAND_ADDRESS Address,
Prototype uint8_t *buff,
uint16_t len)
Behavior description Reads a page considering Error correction code(1 bit per 512 Byte).
Address: The address of the page to read.
Input parameter *buff: The buffer to read from.
len: The number of page to read.
Output parameter None

Table 35. SBLK_NAND_ReadPage

Function name SBLK_NAND_ReadPage.
void SBLK_NAND_ReadPage (NAND_ADDRESS Address,
Prototype uint8_t *buff,
uint16_t len)
Reads a page considering Error correction code (1 bit per 512 Byte) in
Behavior description
Small Block NAND.
Address: The address of the page to read.
Input parameter *buff: The buffer to read from.
len: The number of page to read.
Output parameter None

Table 36. LBLK_NAND_ReadPage

Function name LBLK_NAND_ReadPage.
void LBLK_NAND_ReadPage (NAND_ADDRESS Address,
Prototype uint8_t *buff,
uint16_t len)
Reads a page considering Error correction code (1 bit per 512 Byte) in
Behavior description
Large Block NAND.
Address: The address of the page to read.
Input parameter *buff: The buffer to read from.
len: The number of page to read.
Output parameter None

Table 37. BitCount

Function name BitCount.
Prototype uint8_t BitCount(uint32_t num)
Behavior description Counts the number of 1's in 32 bit Number.
Input parameter num: The number in which number of 1's to be counted.
Output parameter The number of one in 32 bit number.

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2.7.2 fsmc_nand_if.c, fsmc_nand_if.h functions

Table 38. FSMC_SelectNANDType

Function name FSMC_SelectNANDType.
Prototype void FSMC_SelectNANDType(void)
Selects the NAND Type & sets the Required Parameter accordingly. NAND
Behavior description
may be SBLK_NAND or LBLK_NAND.
Input parameter None
Output parameter None

Table 39. FSMC_NAND_NON_ONFI_Compliance

Function name FSMC_NAND_NON_ONFI_Compliance.
Prototype void FSMC_NAND_NON_ONFI_Compliance(void)
Selects the NON ONFI NAND Type & sets the Required Parameter
Behavior description
accordingly. NAND may be SBLK_NAND or LBLK_NAND.
Input parameter None
Output parameter None

Table 40. FSMC_NAND_Init

Function name FSMC_NAND_Init.
Prototype void FSMC_NAND_Init(void)
Configures the FSMC and GPIOs to interface with the NAND memory. This
Behavior description
function must be called before any write/read operation.
Input parameter None
Output parameter None

Table 41. FSMC_NAND_ReadID

Function name FSMC_NAND_ReadID
Prototype void FSMC_NAND_ReadID(NAND_IDTypeDef* NAND_ID)
Behavior description Reads NAND memory's Manufacturer and Device ID.
Input parameter NAND_ID: pointer to a NAND_IDTypeDef structure
Output parameter None

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Table 42. FSMC_NAND_WriteSmallPage

Function name FSMC_NAND_WriteSmallPage.
uint32_t FSMC_NAND_WriteSmallPage(uint8_t *pBuffer,
Prototype NAND_ADDRESS Address,
uint32_t NumPageToWrite)
Behavior description Writes one or several 512 Bytes Page size.
pBuffer: pointer on the Buffer containing data to be written.
Input parameter Address: First page address.
NumPageToWrite: Number of page to write.
New status of the NAND operation. This parameter can be:
– NAND_TIMEOUT_ERROR: when the previous operation generate a
Timeout error.
Output parameter – NAND_READY: when memory is ready for the next operation
New status of the increment address operation. It can be:
– NAND_VALID_ADDRESS: When the new address is valid.
– NAND_INVALID_ADDRESS: When the new address is invalid.

Table 43. FSMC_NAND_ReadSmallPage

Function name FSMC_NAND_ReadSmallPage.
uint32_t FSMC_NAND_ReadSmallPage(uint8_t *pBuffer,
Prototype NAND_ADDRESS Address,
uint32_t NumPageToRead)
Behavior description Sequential read from one or several 512 Bytes Page size.
pBuffer: pointer on the Buffer to fill.
Input parameter Address: First page address.
NumPageToRead: Number of page to read.
New status of the NAND operation. This parameter can be:
– NAND_TIMEOUT_ERROR: when the previous operation generate a
Timeout error.
Output parameter – NAND_READY: when memory is ready for the next operation.
New status of the increment address operation. It can be:
– NAND_VALID_ADDRESS: When the new address is valid.
– NAND_INVALID_ADDRESS: When the new address is invalid.

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Table 44. FSMC_NAND_WriteSpareArea

Function name FSMC_NAND_WriteSpareArea.
uint32_t FSMC_NAND_WriteSpareArea(uint8_t *pBuffer,
Prototype NAND_ADDRESS Address,
uint32_t NumSpareAreaTowrite)
Behavior description Writes spare area information for specified page addresses.
pBuffer: pointer on the Buffer containing data to be written.
Input parameter Address: First page address.
NumSpareAreaTowrite: Number of Spare Area to write.
New status of the NAND operation. This parameter can be:
– NAND_TIMEOUT_ERROR: when the previous operation generate a
Timeout error.
Output parameter – NAND_READY: when memory is ready for the next operation
New status of the increment address operation. It can be:
– NAND_VALID_ADDRESS: When the new address is valid.
– NAND_INVALID_ADDRESS: When the new address is invalid.

Table 45. FSMC_NAND_ReadSpareArea

Function name FSMC_NAND_ReadSpareArea.
uint32_t FSMC_NAND_ReadSpareArea(uint8_t *pBuffer,
Prototype NAND_ADDRESS Address,
uint32_t NumSpareAreaToRead)
Behavior description Reads the spare area information from the specified page addresses.
pBuffer: pointer on the Buffer to fill.
Input parameter Address: First page address.
NumSpareAreaToRead: Number of Spare Area to read.
New status of the NAND operation. This parameter can be:
– NAND_TIMEOUT_ERROR: when the previous operation generated a
Timeout error.
Output parameter – NAND_READY: when memory is ready for the next operation
New status of the increment address operation. It can be:
– NAND_VALID_ADDRESS: When the new address is valid.
– NAND_INVALID_ADDRESS: When the new address is invalid.

Table 46. FSMC_NAND_EraseBlock

Function name FSMC_NAND_EraseBlock.
Prototype uint32_t FSMC_NAND_EraseBlock(NAND_ADDRESS Address)
Behavior description Erases complete block from NAND FLASH.
Input parameter Address: Any address into block to be erased.
New status of the NAND operation. This parameter can be:
– NAND_TIMEOUT_ERROR: when the previous operation generate a
Output parameter
Timeout error.
– NAND_READY: when memory is ready for the next operation.

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Table 47. FSMC_NAND_Reset

Function name FSMC_NAND_Reset.
Prototype uint32_t FSMC_NAND_Reset(void)
Behavior description Resets the NAND FLASH.
Input parameter None
Output parameter NAND_READY.

Table 48. FSMC_NAND_GetStatus

Function name FSMC_NAND_GetStatus.
Prototype uint32_t FSMC_NAND_GetStatus(void)
Behavior description Gets the NAND operation status.
Input parameter None
New status of the NAND operation. This parameter can be:
– NAND_TIMEOUT_ERROR: when the previous operation generate a
Output parameter
Timeout error.
– NAND_READY: when memory is ready for the next operation.

Table 49. FSMC_SBLK_NAND_CopyBack

Function name FSMC_SBLK_NAND_CopyBack.
uint32_t FSMC_SBLK_NAND_CopyBack(NAND_ADDRESS src,
Prototype
NAND_ADDRESS dest)
Copies One Page from Source Address to Destination Address without
Behavior description
utilizing external Memory.
src: Source Address.
Input parameter
dest: Destination Address.
The status of the NAND memory. This parameter can be:
– NAND_BUSY: when memory is busy.
Output parameter
– NAND_READY: when memory is ready for the next operation.
– NAND_ERROR: when the previous operation generates error.

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Table 50. FSMC_LBLK_NAND_CopyBack

Function name FSMC_LBLK_NAND_CopyBack.
uint32_t FSMC_LBLK_NAND_CopyBack(NAND_ADDRESS src,
Prototype
NAND_ADDRESS dest)
Copies One Page from Source Address to Destination Address without
Behavior description
utilizing external Memory.
src: Source Address.
Input parameter
dest: Destination Address.
The status of the NAND memory. This parameter can be:
– NAND_BUSY: when memory is busy.
Output parameter
– NAND_READY: when memory is ready for the next operation.
– NAND_ERROR: when the previous operation generates error.

Table 51. FSMC_NAND_ReadStatus

Function name FSMC_NAND_ReadStatus.
Prototype uint32_t FSMC_NAND_ReadStatus(void)
Behavior description Reads the NAND memory status using the Read status command.
Input parameter None
The status of the NAND memory. This parameter can be:
– NAND_BUSY: when memory is busy.
Output parameter
– NAND_READY: when memory is ready for the next operation.
– NAND_ERROR: when the previous operation generates Error.

Table 52. FSMC_NAND_AddressIncrement

Function name FSMC_NAND_AddressIncrement.
Prototype uint32_t FSMC_NAND_AddressIncrement(NAND_ADDRESS* Address)
Behavior description Increments the NAND memory address.
Input parameter Address: address to increment.
The new status of the increment address operation. It can be:
Output parameter – NAND_VALID_ADDRESS: When the new address is valid address.
– NAND_INVALID_ADDRESS: When the new address is invalid address.

Table 53. FSMC_NAND_ONFI_Compliance

Function name FSMC_NAND_ONFI_Compliance.
Prototype void FSMC_NAND_ONFI_Compliance(void)
Selects the ONFI NAND Type & sets the Required Parameter accordingly.
Behavior description
NAND may be SBLK_NAND or LBLK_NAND.
Input parameter None
Output parameter None

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Table 54. FSMC_SBLK_NAND_SendAddress

Function name FSMC_SBLK_NAND_SendAddress.
Prototype void FSMC_SBLK_NAND_SendAddress(NAND_ADDRESS Addr)
Behavior description Sends the address for Small Block NAND.
Input parameter Addr: NAND_ADRESS to be sent.
Output parameter None.

Table 55. FSMC_LBLK_NAND_SendAddress

Function name FSMC_LBLK_NAND_SendAddress.
void FSMC_LBLK_NAND_SendAddress(uint32_t row,
Prototype
uint32_t column)
Behavior description Sends the row & column address for Large Block NAND.
row: Row Address.
Input parameter
column: Column address.
Output parameter None.

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2.8 Supported NAND Flash

Below is the list of supported NAND Flash in our firmware.

Table 56. Supported NAND Flash

Supported NAND Capacity Tested

Small block NAND

1 NAND128R3A 128 Mbits Y

2 NAND128W3A 128 Mbits Y
3 NAND256R3A 256 Mbits Y
4 NAND256W3A 256 Mbits Y
5 NAND512R3A 512 Mbits Y
6 NAND512W3A 512 Mbits Y
7 NAND01GR3A 1 Gbits Y
8 NAND01GW3A 1 Gbits Y
9 K9F5608U0A 256 MBits Y

Large block NAND

1 NAND512R3B 512 Mbits N

2 NAND512W3B 512 Mbits N
3 NAND01GR3B 1 Gbits Y
4 NAND01GW3B 1 Gbits Y
5 NAND02GR3B 2 Gbits N
6 NAND02GW3B 2 Gbits N
7 NAND04GR3B 4 Gbits N
8 NAND04GW3B 4 Gbits N
9 NAND08GR3B 8 Gbits N
10 NAND08GW3B 8 Gbits N
11 H27U4G8F2DTR 1 Gbits Y
12 TC58NVG0S3BFT00 4 Gbits Y

The firmware supports other manufacturer's NAND Flash with same device ID without any
change to hardware or firmware.
The code size for the NAND Flash Driver files (nand_drv.c & fsmc_nand_if.c) is

Table 57. NAND Flash driver file code size

Code Size Flash RAM

With Optimization (High size) 6.5 KB 5 KB

Without Optimization 11.7 KB 5 KB

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3 NAND evaluation board

3.1 Working with evaluation boards

The evaluation boards STEVAL-CCM006V1, STEVAL-CCM007V1 and STEVAL-
CCM008V1 work in USB Mass Storage mode. In this mode NAND Flash behaves as mass
storage media.
The evaluation boards STEVAL-CCM006V2, STEVAL-CCM007V2 and STEVAL-
CCM008V2 work in Standalone mode. In this mode, the bmp images stored in the pics
folder of root directory are displayed using the File System on the mounted TFT.
Figure 10 & Figure 11 show the component layout to help the user locate the various
components and sections on the board.

Figure 10. Evaluation board: top side

JTAG connector

Touch screen controller

TFT connector

MS33246V1

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Figure 11. Evaluation board: bottom side

RESET switch

Mini USB Port (Full Speed)

STM32

Voltage Regulator

Micro USB Port (High Speed)

NAND Flash NAND Flash socket footprint USB High Speed PHY*
MS33245V1

Note: The USB High Speed section is only present in STEVAL-CCM007V1, STEVAL-CCM007V2,
STEVAL-CCM008V1 and STEVAL-CCM008V2.

3.1.1 Running in USB Mass Storage mode (STEVAL-CCM006/7/8V1)

The STEVAL-CCM006V1, STEVAL-CCM007V1, STEVAL-CCM008V1 boards are
programmed for USB Full Speed by default. To run USB High Speed, you must program the
board using proper firmware using available tool chain.
1. Connect the mini-USB cable between a jumper on the PCB and the Host (PC)
– J4 for USB FS Demo.
– J7 for USB HS Demo.
2. The device is detected as a USB mass storage device in Device Manager of Host (PC).

3. The device appears as a Removable Drive on the Host (PC).

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4. This drive can be used as Mass Storage Media.

3.1.2 Running in Standalone mode (STEVAL-CCM006/7/8V2)

The STEVAL-CCM006V2, STEVAL-CCM007V2, STEVAL-CCM008V2 boards run in
Standalone mode.
1. By default TFT is mounted on J6.
2. Connect mini-USB cable between J4 on the PCB and the Host (PC).
3. The bmp images stored in the "pics" folder of root directory are displayed on the TFT.

Figure 12. Demo running in Standalone mode

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3.2 Schematics
Figure 13. Microcontroller schematic

GND
R1

PG14_TSCREEN_INT
GND

3V3

PG10_FSMC_NE3
R2

PB5_OTG_HS_ULPI_D7
0 Ohm

PA14_JTAG_JTCK
PB4_JTAG_JNTRST

PA15_JTAG_JTDI
10K

PB3_JTAG_JTDO

PD4_FSMC_NOE

PD1_FSMC_D3
PD0_FSMC_D2
PG9_FSMC_NCE3
PD7_FSMC_NCE2
PD6_FSMC_NWAIT

PD5_FSMC_NWE
SW1
R3

PB7_I2C1_SDA
PB6_I2C1_SCL
3V3
NRST 0 Ohm

PB9
PB8
N
PUSH BUTT ON

GND

3V3
GND
3V3
C1 R
R4 3V3
100nF 10K

144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
U1

VDD_SA
VDD_3
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD_11
VSS_11
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDD_10
VSS_10
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
D1
R5
PE2 GND PE2 1 108 3V3
PE2 VDD_2
PE3 2 107 GND
1K PE3 VSS_2 VCAP
3 106
PE4 VCAP_2
TEST_LED1 4 105 PA13_JTAG_JTMS
PE5 PA13
5 104 PA12_OTG_FS_DP_USB
D2 PE6 PA12
6 103 PA11_OTG_FS_DM_USB
R6 VBAT PA11
7 102 PA10_OTG_FS_ID_USB
PC13-TAMPER-RTC PA10
PE3 GND 8 101 PA9_OTG_FS_VBUS_USB
PC14-OSC32_IN PA9
9 100
1K PC15-OSC32_OUT PA8
PF0_FSMC_ADDR_A0 10 99
PF0 PC9
TEST_LED2 11 98
PF1 PC8
12 97
PF2 PC7
13 96
PH0_OSC_IN
14
PF3
PF4
STM32F103ZET6/ PC6
VDD_9
95 3V3
C2 15 94
20pF GND 16
PF5 STM32F205ZET6/ VSS_9
93
GND
VSS_5 PG8 PG8_USB_PU
3V3 17
18
VDD_5 STM32F405ZGT6 PG7
92
91
PG7_FSMC_INT3
PF6 PG6 PG6_FSMC_INT2
Y1 19 90
PF7 PG5
25MHz 20 89
PF8 PG4
21 88
R7 PF9 PG3
22 87
C3 PH1_OSC_OUT PF10 PG2
PH0_OSC_IN 23 86 PD15_FSMC_D1
20pF OSC_IN PD15
PH1_OSC_OUT 24 85 PD14_FSMC_D0
390 OSC_OUT PD14
NRST 25 84 3V3
NRST VDD_8
PC0_OTG_HS_ULPI_STP 26 83 GND
PC0 VSS_8
27 82
PC1 PD13
PC2_OTG_HS_ULPI_DIR 28 81 PD12_FSMC_ADDR_A17
PC2 PD12
PC3_OTG_HS_ULPI_NXT 29 80 PD11_FSMC_ADDR_A16
PC3 PD11
For STM32F10xx 30 79 PD10_FSMC_D15
GND R8 GND VDD_12 PD10
Y1----- 8MHz 31 78 PD9_FSMC_D14
VSSA PD9
0 Ohm 32 77 PD8_FSMC_D13
3V3 VREF+ PD8
For STM32F2xxx & STM32F4xxx 33
VDDA PB15
76
Y1------ 25MHz 34 75
PA0_WKUP PB14
35 74 PB13_OTG_HS_ULPI_D6
PA1 PB13
36 73

PB2-BOOT1
R9 PA2 PB12 PB12_OTG_HS_ULPI_D5
3V3

VCAP_1
0 Ohm

VDD_4

VDD_6

VDD_7

VDD_1
VSS_4

VSS_6

VSS_7

PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
PF11
PF12

PF13
PF14
PF15
PG0
PG1
PC4
PC5
PA3

PA4
PA5
PA6
PA7

PB0
PB1

PE7
PE8
PE9
VCAP TP1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1

C4 C5
2.2uF 2.2uF TEST POINT
10K

3V3
3V3

3V3

3V3
R10
GND

GND

GND
For STM32F10xx VCAP

PE7_FSMC_D4
PE8_FSMC_D5
PE9_FSMC_D6

PE10_FSMC_D7
PE11_FSMC_D8
PE12_FSMC_D9
PE13_FSMC_D10
PE14_FSMC_D11
PE15_FSMC_D12
PB0_OTG_HS_ULPI_D1
PB1_OTG_HS_ULPI_D2
PA5_OTG_HS_ULPI_CK

PB10_OTG_HS_ULPI_D3
PB11_OTG_HS_ULPI_D4
Mount --- R1,R8,R11
PA3_OTG_HS_ULPI_D0

DNM --- R3,R9 R11

GND
0 Ohm

For STM32F2xxx & STM32F4xxx

J1
Mount --- R3,R9
DNM --- R1,R8,R11

GND
1 3V3
2 PB8
3 GND
1K

CONN TRBLK 3

3V3

J2 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17

F
100nF F
100nF F
100nF 100nF
F F
100nF F
100nF 100nF
F F
100nF 100nF
F F
100nF F
100nF 100nF
F
1 R13
3V3
2 PB9
3 GND
1K

CONN TRBLK 3

MS33224V1

Figure 14. USB Full Speed schematic

R14
PG8_USB_PU PA12_OTG_FS_DP_USB
1.5k

J4
USB5V_FS 1 6
USB_VCC SHELL
2 7
USBDM SHELL
3 8
C22 USBDP SHELL
4 9
ID SHELL
10uF 5
USB_GND
USB_MINIA/B TYPE

PA9_OTG_FS_VBUS_USB
R31
PA11_OTG_FS_DM_USB R32 1M C23
22 4.7nF
PA12_OTG_FS_DP_USB R34
22
PA10_OTG_FS_ID_USB R36
0

U4
1 6 D3
I/O1 I/O1
2 5
GND VBUS R40
3 4
I/O2 I/O2 1k
USBLC6-2P6
LED_GREEN
MS33225V1

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Figure 15. USB High Speed schematic

3V3_HS

XTAL1
XTAL2
C27 C28 C29 C30 R43
10K
0.1uF 0.1uF 0.1uF 0.1uF

C36
4.7uF

31
16

30
25
27
28
6
U6
D6
R44 1K

REG_EN
VDD3.3
VDD3.3
VDD3.3
VDD3.3
XO
XI
33
GNDPAD LED_GREEN
1
GND
PA3_OTG_HS_ULPI_D0 24 2
DATA0 GND
PB0_OTG_HS_ULPI_D1 23 3
DATA1 CPEN
PB1_OTG_HS_ULPI_D2 22 10 J7
DATA2 EXTVBUS R46 12K
PB10_OTG_HS_ULPI_D3 21 32 L1
DATA3 RBIAS USB5V_HS
PB11_OTG_HS_ULPI_D4 20 4 1
DATA4 VBUS R47 820 USB_VCC
PB12_OTG_HS_ULPI_D5 19 8 2 6
DATA5 DM USBDM SHELL
PB13_OTG_HS_ULPI_D6 18 7 3
DATA6 DP USBDP BEAD
PB5_OTG_HS_ULPI_D7 17 5 4 7
DATA7 ID ID SHELL
5

VDDA1.8
USB_GND

CLKOUT
VDD1.8

VDD1.8
RESET
NXT

STP
DIR
9
11
12
13
14
15
29
26
USB3300
PC3_OTG_HS_ULPI_NXT

PC0_OTG_HS_ULPI_STP
PA5_OTG_HS_ULPI_CK
PC2_OTG_HS_ULPI_DIR

C41 XTAL1
33pF

C42
Y2 R50
24MHz 1M 0.1uF C43
C46 C44
0.1uF 4.7uF
C45 XTAL2
33pF 4.7uF 3V3 R52
3V3_HS
0

MS33226V1

Figure 16. Touch Screen schematic

AGND AGND

C31 C32 C33 C34

2pF 2pF 2pF 2pF

R57
TSC_YU

TSC_XR

TSC_YD

TSC_XL

AGND GND

0
AGND

AGND
12

11

10

U7
IN3

IN2

GND

IN1

TSC_XR 13
X+
8
L2 IN0
3V3 14
VIO
7
BEAD TSC_YU DATA_IN 3V3
15
C37 Y+
1uF C38
STMPE811 6
100nF VCC C39 C40
TSC_XL 16 5 SDAT 100nF 10uF
X- SDAT
SCLK
INT

AGND
A0
Y-

AGND 3V3
1

R49
PG14_TSCREEN_INT

R48 4.7K
TSC_YD SCLK
AGND

4.7K

22
SCLK R51 PB6_I2C1_SCL

22
SDAT R53 PB7_I2C1_SDA
R54 3V3
10k

C47
100nF

AGND MS33227V1

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Figure 17. TFT Connector schematic

J6

PG10_FSMC_NE3 1 2 PF0_FSMC_ADDR_A0
PD5_FSMC_NWE 3 4 PD4_FSMC_NOE
NRST 5 6 PD14_FSMC_D0
PD15_FSMC_D1 7 8 PD0_FSMC_D2
PD1_FSMC_D3 9 10 PE7_FSMC_D4
PE8_FSMC_D5 11 12 PE9_FSMC_D6
PE10_FSMC_D7 13 14 PE11_FSMC_D8
PE12_FSMC_D9 15 16 PE13_FSMC_D10
PE14_FSMC_D11 17 18 PE15_FSMC_D12
PD8_FSMC_D13 19 20 PD9_FSMC_D14
PD10_FSMC_D15 21 22 GND
5V0 23 24 3V3
3V3 25 26 GND
GND 27 28 5V0
29 30
TSC_XL 31 32 TSC_XR
TSC_YD 33 34 TSC_YU
35 36
37 38
39 40

CONNECTOR20x2
MS33228V1

Figure 18. Power schematic

D4
USB5V_FS 3V3

STPS1L30U U5
GND 1 8
GND NC C26
D5 2 7
VOUT VOUT 10uF
3 6
5V0 VOUT VOUT
USB5V_HS 4 5
VIN NC
STPS1L30U LD1117D33 TR
C48 C35
10uF 100nF

R45 D7

GND 3V3

1k LED_GREEN
MS33229V1

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R56
3V3 3V3_NAND2
R55
3V3 3V3_NAND1 0 Ohm

0 Ohm

3V3_NAND1 3V3_NAND1 3V3_NAND2 3V3_NAND2

C18 C19 C20 C21

R19 R20 100nF 100nF R21 R22 100nF 100nF
10K 10K 10K 10K

PG6_FSMC_INT2 PG7_FSMC_INT3

PD6_FSMC_NWAIT GND PD6_FSMC_NWAIT GND

R25 0 Ohm R27 0 Ohm

U2 U3
1 48 1 48
NC NC NC NC
R28 2 47 R29 2 47
NC NC NC NC
3 46 3 46
NC NC NC NC

DocID025024 Rev 1
PD7_FSMC_NCE2 R26 0 Ohm 4 45 PG9_FSMC_NCE3 R30 0 Ohm 4 45
NC NC NC NC
5 44 PE10_FSMC_D7 5 44 PE10_FSMC_D7
22 Ohm NC I/O7 22 Ohm NC I/O7
6 43 PE9_FSMC_D6 6 43 PE9_FSMC_D6
NC I/O6 NC I/O6
7 42 PE8_FSMC_D5 7 42 PE8_FSMC_D5
R33 RB I/O5 R35 RB I/O5
PD4_FSMC_NOE 8 41 PE7_FSMC_D4 PD4_FSMC_NOE 8 41 PE7_FSMC_D4
R I/O4 R I/O4
3V3_NAND1 9 40 3V3_NAND2 9 40
E NC E NC
10 39 10 39
10K NC NC 10K NC NC
11 38 11 38
NC NC NC NC
3V3_NAND1 12 37 3V3_NAND1 3V3_NAND2 12 37 3V3_NAND2
VDD VDD VDD VDD
GND 13 36 GND GND 13 36 GND
VSS VSS VSS VSS
14 35 14 35
NC NC NC NC
15 34 15 34
NC NC NC NC
PD11_FSMC_ADDR_A16 16 33 PD11_FSMC_ADDR_A16 16 33
CL NC CL NC
PD12_FSMC_ADDR_A17 17 32 PD1_FSMC_D3 PD12_FSMC_ADDR_A17 17 32 PD1_FSMC_D3
AL I/O3 AL I/O3
PD5_FSMC_NWE 18 31 PD0_FSMC_D2 PD5_FSMC_NWE 18 31 PD0_FSMC_D2
W I/O2 W I/O2
Figure 19. NAND Flash schematic

19 30 PD15_FSMC_D1 19 30 PD15_FSMC_D1
R41 WP I/O1 R42 WP I/O1
20 29 PD14_FSMC_D0 20 29 PD14_FSMC_D0
NC I/O0 NC I/O0
3V3_NAND1 21 28 3V3_NAND2 21 28
C24 NC NC C25 NC NC
22 27 22 27
10K 100nF NC NC 10K 100nF NC NC
23 26 23 26
NC NC NC NC
24 25 24 25
NC NC NC NC

GND NAND512B GND NAND512B

MS33230V1

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NAND evaluation board UM1653

Figure 20. NAND Flash Signals schematic

J3

PD14_FSMC_D0 1
PD15_FSMC_D1 2
PD0_FSMC_D2 3
PD1_FSMC_D3 4
PE7_FSMC_D4 5
PE8_FSMC_D5 6
PE9_FSMC_D6 7
PE10_FSMC_D7 8
PD11_FSMC_ADDR_A16 9
PD12_FSMC_ADDR_A17 10
PD4_FSMC_NOE 11
PD5_FSMC_NWE 12
PD7_FSMC_NCE2 13
PG9_FSMC_NCE3 14
PG6_FSMC_INT2 15
PG7_FSMC_INT3 16
PD6_FSMC_NWAIT 17
GND 18
3V3 19
GND 20

CON20
MS33231V1

Figure 21. JTAG schematic

PB4_JTAG_JNTRST PB4_JTAG_JNTRST 3V3
PA14_JTAG_JTCK
PA14_JTAG_JTCK
PB3_JTAG_JTDO
PB3_JTAG_JTDO
NRST R15 R16 R17 R18
NRST
PA13_JTAG_JTMS 10k 10k 10k 10k
PA13_JTAG_JTMS
PA15_JTAG_JTDI PA15_JTAG_JTDI

J5 R23
1 3V3 0
2
3 PB4_JTAG_JNTRST R24
4 10k
5 PA15_JTAG_JTDI
6
7 PA13_JTAG_JTMS
NRST
8
9 PA14_JTAG_JTCK
10
11 RTCK
12
13 PB3_JTAG_JTDO
14
15 NRST R37
16 10k
17 DBGRQ R38
18 10k
19 DBGACK R39
20 10k

JTAG_CONN

MS33232V1

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3.3 NAND evaluation board images

Figure 22. Top side of PCB

Figure 23. Bottom side of PCB

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Revision history UM1653

4 Revision history

Table 58. Document revision history

Date Revision Changes

28-Nov-2013 1 Initial release.

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