MOTOROLA

MICROPROCESSORS
DATA MANUAL

• Quality
• Reliability
• Technology
 Motorola's •
Microprocessor/Microcomputer Families ,

•
The Motorola M6800 Generic Bus
Concept and Use

Reliability
•
Data Sheets
•
Mechanical Data
•
~echnical Training
•
Memory Products
•
Development Systems and
Board-Level Products
II
 MOTOROLA
MICROPROCESSORS

Prepared by
Technical Information Center

This book is intended to provide the design engineer with the technical
data needed to completely and successfully design a microprocessor or
microcomputer based system. The data sheets for Motorola's
microprocessor, microcomputer, and peripheral components are included.

The information in this book has been carefully checked; no responsibility,

however, is assumed for inaccuracies. Furthermore, this information does
not convey to the purchaser of microelectronic devices any license under
the patent rights of the manufacturer.

Additional information about memory products, technical training, and

system development products is also provided. For further marketing and
applications information, please contact:

Motorola Inc.
MOS Integrated Circuits Group
Microprocessor Division
Austin, Texas
(512)928-6800

Series B
©MOTOROLA INC., 1981
Previous Edition ©1978
Printed in U.S.A. "All Rights Reserved"
 Product Preview data sheets herein contain information on a product under
development. Motorola reserves the right to change or discontinue these
products without notice.

Advance Information data sheets herein contain information on new pro-

ducts. Specifications and information are subject to change without
notice.

Sentry is a registered trademark of Fairchild.

EXORciser is a registered trademark of Motorola.
EXORciser II, EXORterm, EXORdisk, EXORmacs, EXORset, MOOS, and VERSAmoduie are trademarks
of Motorola. .

ii
 TABLE OF CONTENTS

Title Page No.

Chapter 1 - Motorola's Microprocessor and Mircocomputer Families
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
8-Bit Microprocessors (MPUs) .................................. 1-3
MC6800 M icropr6cessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
MC6802 Microprocessor with Clock and Optional RAM ......... 1-4
MC6803 Microcomputer/Microprocessor. . . . . . . . . . . . . . . . . . . . . 1-5
MC6808 Microprocessor with Clock. . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
MC6809 8·/16-Bit HMOS Microprocessor. . . . . . . . . . . . . . . . . . . . . . 1-5
MC6809E 8-/16-Bit HMOS Microprocessor (External Clock) ...... 1-6
MC146805E2 CMOS Microprocessor with RAM and I/O . . . . . . . . . . 1-6
8-Bit Microprocessors Features Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
8-Bit Microprocessors Selector Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Single-Chip Microcomputer (MCUs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
TheCMOSM6805Components ................................. 1-11
Single-Chip Microcomputer Families Features Matrix. . . . . . . . . . . . .. 1-14
Single-Chip Microcomputer Families Selector Guide ............... 1-14
16-Bit Microprocessors (MPUs) .................................. 1-16
16-Bit Product Listing .......................................... 1-16
Peripheral and Interface Components ............................ 1-17
Peripheral and Interface Components Selector Guide. . . . . . . . . . . . . .. 1-17

Chapter 2 - The Motorola M6800 Generic Bus Concept and Use

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-3
Diagram/Table Use. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-8
The CMOS Generic Bus ........................................ 2-11

Chapter 3 - Reliability
The MC6800 Microprocessor Family - Reliability Report No. 8110. . .. 3-3
Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-23
The "Better" Program ......................................... 3-26

Chapter 4 - Data Sheets

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3
Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3

Chapter 5 - Mechanical Data

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-3

Chapter 6 - Technical Training

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-3
Course Offerings ............................................. 6-3

iii
 TABLE OF CONTENTS
Title Page No.

Chapter 7 - Memory Products

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7·3

Chapter 8 Development Systems and Board·Level Products

Development Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8·3
Micromodules - 8-Bit Board-Level Products. . . . . . . . . . . . . . . . . . . . .. 8-6
VERSAmodules - 16-Bit Board-Level Products ........ "............ 8-10
Reference Guide: Selection by MPUlMCU Supported ............... 8-13

iv
 ALPHANUMERICAL INDEX

Device No. Description Page No.

MC1372 Color Television Modulator. . . . . ....... . ... . . .. ... .. . 4-5
MC3446A Quad Bidirectional Bus Transceiver. . . . . . . . . . . . . . . . . .. 4-13
MC3447 Octal Bidirectionallnst. Bus (GPIA) Transceiver. . . . . . .. 4-16
MC3448A Quad Bidirectionallnst.Bus (GPIA) Transceiver. . . . . . .. 4-22
MC3482/MC6882 Quad Buffer/Latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-28
MC3870 8-Bit Single·Chip Microcontroller . . . . . . . . . . . . . . . . . . . .. 4-32
MC6800 8-Bit Microprocessor Unit (MPU) . . . . . . . . . . . . . . . . . . . .. 4-55
MC6801/03/03NR 8-Bit Microcomputer/Microprocessor Unit (MCU/M PU) . .. 4-84
MC6802/02NS/08 8-Bit Microprocessor with Clock and Optional RAM ..... 4-125
MC6805P2 8-Bit HMOS 1K Single·Chip Microcomputer ............ 4-146
MC6805P4 8-Bit HMOS 2K Microcomputer ....................... 4-168
MC6805R2 8-Bit HMOS 2K Single·Chip Microcomputer with A/D .... 4-191
MC6805T2 8-Bit HMOS 2K Single·Chip Microcomputer with PLL .... 4-216
MC6805U2 8-Bit HMOS 2K Single·Chip Microcomputer ............ 4.243
MC6809 8-/16-Bit HMOS Microprocessor ...................... 4.266
MC6809E 8-/16-Bit HMOS Microprocessor ...................... 4.298
MCM6810 128 X 8 Static RAM ................................. 4.330
MC6821 Peripheral Interface Adapter ......................... 4.335
MC6822 Industrial Interface Adapter ......................... 4.345
MC6828 Priority Interrupt Controller .......................... 4.348
MC6829 Memory Management Unit .......................... 4.356
MC6835 CRT Controller .................................... 4.371
MC6839 Floating·Point ROM ................................ 4.392
MC6840 Programmable Timer ............................... 4.406
MC6843 Floppy·Disk Controller .............................. 4.419
MC6844 Direct Memory Access Controller ..................... 4.441
MC6845 CRT Controller .................................... 4.457
MC6846 ROM·I/O·Timer .................................... 4.480
MC6847 Video Display Generator ............................ 4.499 .
MC6850 Asynchronous Interface Adapter ..................... 4.527
MC6852 Synchronous Serial Data Adapter .................... 4.536
MC6854 Advanced Data Link Controller ....................... 4.550
MC6855 Serial Direct Memory Access Processor ............... 4.572
MC6859 Data Security Device ............................... 4.574
MC6860 0-600 BPS Digital Modem ........................... 4.583
MC6862 2400 BPS Digital Modulator .......................... 4.597
MC6870A/71A Two·Phase Microprocessor Clock .................... 4.605
MC6875 Two·Phase Clock Generator ......................... 4.612
MC6880A/8T26 Quad Bus Transceiver .............................. 4.624
MC6883 Synchronous Address Multiplexer .................... 4.630
MC6889/MC8T28 Quad Bus Transceiver .............................. 4-655
MC68000 16-Bit HMOS Microprocessor ........................ 4-661
MC68120/121 Intelligent Peripheral Controller ...................... 4-711
MC68122 Cluster Terminal Controller .......................... 4-755

v
 ALPHANUMERICAL INDEX

Device No. Description Page No.

MC68230 Paraliellnterface/Timer ............................ . 4-783
MC68450 Direct Memory Access Controller .................... . 4-812
MC68451 Memory Management Unit ......................... . 4-818
MC68488 General Purpose Interface Adapter .................. . 4-836
MC68701 EPROM Microcomputer/Microprocessor .............. . 4-855
MC68705P3 8·Bit HMOS 1.8K EPROM Single·Chip Microcomputer .. . 4-894
MC68705R3 8·Bit HMOS 3.7K EPROM Single·Chip Microcomputer
with AID ....................................... . 4-918
MC68705U3 8-Bit HMOS 3.7K EPROM Single-Chip Microcomputer .. . 4-945
MC141000 4-Bit CMOS 1K Microcomputer ...................... . 4-968
MC141099 4-Bit CMOS 1K Microcomputer (External ROM) ........ . 4-968
MC141200 4-Bit CMOS 1K Microcomputer ...................... . 4-968
MC146805E2 8-Bit CMOS Microprocessor with RAM and 1/0 ......... . 4-985
MC146805F2 8-Bit CMOS 1K Single-Chip Microcomputer ........... . 4-1019
MC146805G2 8-Bit CMOS 2K Single-Chip Microcomputer ........... . 4-1021
MC146818 CMOS Real-Time Clock plus RAM ................... . 4-1046
MC146823 CMOS Parallel Interface ........................... . 4-1066

vi
 Motorola's
Microprocessor/Microcomputer Families
•

1-1
•

1·2
 MOTOROLA'S
MICROPROCESSOR AND MICROCOMPUTER FAMILIES

Serving as the "heart" of every microcomputer system is a microprocessor.

Start with the chip set that precisely meets your design objective. Motorola
manufacturers the industry's most complete selection of sold-state
microcomputer components to give you the performance you need and the
•
design flexibility you want.

The family concept has been extremely popular in the microprocessor in-
dustry. Motorola pioneered this family concept with the introduction of the
M6800 Family in 1974. Since then the MPU/MCU Family has evolved in
several directions, as shown in Figure 1-1, in order to fill expanding use
concepts. In addition, the basic M6800 Family has been enhanced. A large
number of peripheral devices have been developed to support the expan-
ding family of microprocessors and microcomputers.

8·BIT MICROPROCESSORS (MPUs)

MC6800 - MC6802 - MC6803 - MC6808-
MC6809 - MC6809E - MC146805E2

The MC6800 MPU was the first of the M6800 MPU Family and still remains
a highly cost-effective processor for a great many process-control and
data-communications applications. Seventy-two instructions and six dif-
ferent addreSSing modes give it powerful capability, and a full range of
compatible peripheral chips offer the widest possible latitude in system
implementation. After years of field experience, the MC6800 has earned an
enviable reputation as one of the easiest-to-use processors available.

Moreover, to tai lor the system to your specific needs at the lowest cost, the
MC6800 (and its peripherals) is available in three different packages, three
different temperature ranges, and three speed ranges, as follows:

1.5 MHz 1.5 MHz 2 MHz

o to 70°C -40 to +85°C - 55 to + 125°C o to 70°C -40 to 85°C o to 70°C
Plastic MC6800P MC6800CP - MC68AOOP MC68AOOCP MC68BOOP
Cerdip MC6800S MC6800CS MC6800BQCS - - -
Ceramic MC6800L MC6800CL - MC68AOOL MC68AOOCL MC68BOOL

1-3
 FIGURE 1·1. GENEALOGY OF THE COHESIVE
M6800 MICROPROCESSOR/MICROCOMPUTER FAMILY

• 15-

12.5-

10 -

7.5-
,,------ ... ,
'- ---_ ..... /

6.0-
OJ
()
c
ro
E
5.0-
/
,.----
0 /
't: 4.0-
OJ
c... /
OJ 3.0- /
> /
~
Q)
cr: 2.5- /,-----------~ ~--~
/
2.0- /
/
1.5 - /
//
1.2- /. 68701
~--~
>----.. .-----.. . ,
,----~/

1.0- 6800
.".---,"""

0.75- 6805P2 )
....... _---'"

I I I I I I I I I
1974 1975 1976 1977 1978 1979 1980 1981 1982

Introduction Year

The MC6802 MPU has all the attributes of the basic MC6800, but it
reduces the component count of a minimum microcomputer system to only
two.

The MC6802 adds an on·chip clock oscillator and 128 bytes of RAM to the
capability of an MC6800. Data in the first 32 bytes of the built-in RAM can
be retained in a low-power mode by an external power source, allowing
memory retention during a power-down situation.

Using this microprocessor, a minimum microcomputer system consists of:

1- MC6802 Microprocessing Unit
1- MC6846 ROM-I/O-Timer Unit
Of course, the system is expandable to any requirement with the adapters,
expanders, and other peripheral chips that are a part of the M6800 Family.

The MC6802 is available in both ceramic (suffix L) and plastic (suffix P)

packages.

1-4
The MC6803 MPU is the microprocessor version of the MC6801 single-
chip microcomputer. The MC6803 accomodates applications where exter-
nal ROM is present. With 13 parallel input/output lines, a 16-bit timer, and a
serial communications interface the MC6803 offers a great deal of freedom
in system needs. One of the most desirable attributes of the multi-
generation MC6803 is its compatibility with existing software and hard-
ware. The MC6803 easily meets this goal by being thoroughly integrated in-
to the total M6800 family of components. In addition, since the MC6803 is
an HMOS device, it requires only a single + 5 volt power supply and inter-
faces with both TTL and MOS peripherals. The concept of an integrated
family of devices is predicated on continuity in both design and develop-
ment. As a member of the M6800 family, the MC6803 shares many of the at-
tributes of the basic MC6800 MPU. For example, the MC6803 encompasses
the full MC6800 instruction set, yet new instructions have been incor-
porated for even greater system capability and ease of programming. Many
MC6803 instructions execute in fewer cycles than on the MC6800. More
and faster instructions increase throughput and reduce software conver-
sion and development time. Some of the features of the MC6803 are:

• Expanded MC6800 Instruction Set

• Full Duplex Serial Communications Interface
• Upward MC6800 Source and Object Code Compatibility
• 16-Bit Timer with Three Modes
• 16-Bit Multiplexed Address Bus Providing 64K-Byte Memory Space
• 128 Bytes of On-Chip RAM (64 Bytes Retainable with Battery
Backup)
• 13 Parallel I/O Lines
• Internal Clock (Divide-by-Four)
• TTL-Compatible Inputs and Outputs
• Interrupt Capability (Maskable and Non-Maskable)

The MC6808 low-cost version of the MC6802 microprocessor has an on-

chip clock oscillator and driver, but no on-chip memory. The MC6808 can
use up to 64K of external RAM, ROM, or peripherals.

The MC6809 microprocessor, with five internal 16-bit registers, offers up

to five times higher performance than the MC6800, yet, due to the 8-bit bus
is fully compatible with all M6800 bus-oriented supplementary circuits and
peripherals. Here's how the MC6809 stacks up:

Architectural Improvements:
• Additional 16-Bit Index and Stack Registers
• Direct Page Register
• Increased Addressing Modes

1-5
 • 16-Bit Operations and 16-Bit Accumulator
• 8 x 8 Multiplier

•
• Fast Interrupt

Software Improvements:
• Designed for efficient handling of high-level languages, including
Pascal, Basic, MPL, Cobol, and Fortran.
• Position-independent coding and reentrant-programming capability
encourage development of "canned software," with modular
program interchangeability.
• Structural, high subroutined code enhanced by two 16-bit
index registers and program counter usable for indexing.
• Multi-task and multi-processor organization.
• Stack-oriented compiler instructions with both user and hardware
stack registers available.
Although the MC6809 is compatible with the extensive existing M6800
Family, Motorola is designing even more peripherals to enhance systems
designed with the MC6809. These new peripherals (e.g., the MC6829
Memory Management Unit, the MC6839 Floating Point ROM, and the
MC6855 Serial DMA Processor) allow an MC6809 user to realize the full
potential of the processor.
The MC6809 is a logical step for applications that crowd the capacity limits
of today's conventional 8-bit processor - yet, hardware and software
(upward) compatibility with existing M6800 processors protects previous
software investment.

The MC6809E includes all the features of the MC6809 plus external clock-
ing to provide the flexibility required in a multi-processor system.

The MC146805E2 initiates the CMOS side of Motorola's microprocessor

family. Battery-oriented and noise sensitive applications have long sought
an M6800 MPU implemented in CMOS. The MC146805E2 includes an 8-bit
optimized processor the equal of the MC6800 in speed and performance,
plus on-chip RAM, timer, parallel 110 ports, and clock oscillator. Complete
CMOS systems are assembled using the MC146823 Parallel Interface,
MC146818 Real-Time Clock plus RAM, MCM65516 CMOS 2K ROM, and
many MSI and SSI support parts. The MC146805E2 also serves as a ROM-
less prototype device for the CMOS and HMOS M6805 Family single-chip
MCUs.
The processor has sixty-one basic instructions that are similar to those of
the popular MC6800 microprocessor, plus some unique enhancements. A
complete set of bit-manipulation and test instructions/allow any bit in RAM
or any 110 pin to be individually set or cleared or tested as a conditional
branch, all with a single instruction. The table look-up indexing modes have
also been enhanced and made more ROM efficient.

1-6
The very low power requirement of static CMOS make the MC146804E2
family of processors and peripherals extremely attractive for those applica-

•
tions where power is a major consideration (portable instruments, telecom-
munications, point-of-sale terminals, remote instrumentation, industrial
control, applicance controllers, etc.). The operating voltage range is from 3
to 6 volts, while current usage ranges from microamps upward depending
upon frequency, voltage, standby modes, and operating duty cycle. Other
MC146805E2 features include:

• Expansion Bus Addressing 8K Bytes of Memory

• 112 Bytes of RAM
• 16 Bidirectional 110 Lines in Addition to the Bus
• 2 Program Initiated Low-Power Standby Modes
• Timer/Counter:
- 8-Bit Programmable Counter
- 7-Bit Software-Selectable Prescaler
- External Timer Input
- Maskable Timer Interrupt
• Maskable External Interrupt
• 40-Pin Package
• Fully Static Operation for Lower Power Needs
• Oscillator Frequency to 5 MHz at 5 V
• Compatible ROM Available - MCM65516 (2K x 8)

1-7
 8·BIT MICROPROCESSORS FEATURES MATRIX
RAM I/O Special Mnem Ext Data

•
Device Tech Pins 8X Lines I/O Inst' Addr Size Clock Timer
MC6800 NMOS 40 - - - 72 64K 8 No -
MC6802 NMOS 40 128 - - 72 64K 8 Yes -
MC6802NS NMOS 40 128 - - 72 64K 8 Yes -
MC6803 HMOS 40 128 13 Serial 82 64K 8 Yes 16-Bit
MC6803NR HMOS 40 - 13 Serial 82 64K 8 Yes 16-Bit
MC6808 HMOS 40 - - - 72 64K 8 Yes -
MC6809 HMOS 40 - - - 59 64K2 8 Yes -
MC6809E HMOS 40 - - - 59 64K2 8 No -
MC146805E2 CMOS 40 112 16 - 61 8K 8 Yes 8-Bit +
Prescaler
NOTES:
1. Some Mnemonic Instructions can have many Opcode Instructions. As a result a Microprocessor
normally has many more Opcode Instructions than Mnemonic Instructions. For instance the
MC6809 has 59 Mnemonic Instructions and 1464 Opcode Instructions.

2. Two megabytes when used with the MC6829 Memory Management Unit.

8·BIT MICROPROCESSORS SELECTOR GUIDE

TECHNOLOGY PROCESSING POWER

HMOS/NMOS Page CMOS Page 8-Bit Page
4-55 MC146805E24-985 MC6800 4-55
MC6800
MC6802 4-125 MC6802 4-125
MC6802NS 4-125 MC6802NS 4-125
MC6803 4-84 MC6803 4-84
MC6803NR 4-84 MC6803NR 4-84
MC6808 4-125 MC6808 4-125
MC6809 4-266 MC6809 4-266
MC6809E 4-298 MC6809E 4-298
MC146805E2 4-985

FUNCTIONAL BLOCKS LANGUAGE ORIENTATION

MPU with Low-Level High-Level
MPU Page On-Chip RAM Page Language Page Language Page
MC6800 4-55 MC6802 4-125 MC6800 4-55 MC6809 4-266
MC6803NR 4-84 MC6802NS 4-125 MC6802 4-125 MC6809E 4-298
MC6808 4-125 MC6803 4-84 MC6802NS 4-125
MC6809 4-266 MC146805E2 4-985 MC6803 4-84
MC6809E 4-298 MC6803NR 4-84
MC6808 4-125
MC146805E2 4-985

1-8
 SINGLE·CHIP MICROCOMPUTERS (MCUs)
THE M6801 - M6805 - M3870 - M141000 FAMILIES

•
Take a basic MPU; add an on-chip clock oscillator and timer; put in enough
Read-Only Memory (ROM) to handle the program routines for dedicated
application, and enought Ready/Write (RAM) Memory capacity to handle
the associated data manipulations; cap it off with sufficient input/output
capability to interface with a number of parallel and serially oriented
peripherals and you have a single-chip microcomputer.
The single-chip system doesn't necessarily have all the flexibility of a
multi-chip system, but with adequate capacity to handle a specific require-
ment, it can save both component cost and equipment manufacturing cost.
Motorola offers single-chip microcomputers across a broad spectrum of
processor performance and system functionality. Motorola's first high
volume production single-chip MCU is the second source of the popular
3870. The 4-bit CMOS M141000 Family includes two ROM-based parts, plus
a ROM-less version. The M6801 Family includes the high performance
single-chip MCU, plus EPROM and ROM-less versions. The rapidly expan-
ding M6805 Family includes a number of memory and package sizes with
various special 1/0 functions, in both HMOS and CMOS.

PERFORMANCE - Processor performance, or program efficiency, for

the application is an important single-chip MCU selection criteria. The
M6801 Family is the throughput leader with 16-bit data operations, binary
multiply, and an average of only 3.7 cycles per instruction. Bit modify and
test instructions and powerful indexing modes put the M6805 Family in
second place on the performance scale. The MC3870 offers a very suc-
cessful 8-bit architecture, while the M141000_ Family parts are clasic 4-bit
processors.

TECHNOLOGY - The very high production volumes of high-density

NMOS (HMOS) permit low cost single-chip solutions. CMOS, as a relatively
new microcomputer technology, offers very low power consumption and
wide power supply tolerance at performance levels similar to HMOS. The
M6801 Family, M6805 Family, and MC3870 are produced in HMOS while the
M6805 and M141000 Families make CMOS benefits available. The M6805
Family is the first microcomputer that allows you to look at the technology
trade-offs independent of the architectural and supplier choices.

ROM SIZE - The mask ROM capacities of the present single-chip MCUs
range from 1K bytes for the M6805 and the M141000 Families up to 2.5K
bytes on one M6805 Family version. However, the M6801 and M6805
Families may in the future be implemented with as much as 64K bytes of
on-chip ROM without any architectural changes. In selecting the ROM size,
the ROM usage efficiency of the instruction set should be considered,
along with the application to be programmed. Architectures of the
M141000 and MC3870 class offer short one and two byte instructions. The
M6801 and M6805 Families use many multi-function instructions such as

1-9
 bit manipulation, memory modification, indexing, and multiply to do the
function of two or more instructions in traditional MCUs.

•
NON·MASK·ROM VERSIONS - EPROM versions andlor ROM-less ver-
sions of practically all single-chip MCUs are offered. They serve for limited
volume applications, prototype debugging, and field trials. EPROM ver-
sions are available in the M6805 and M6801 Families. ROM-less versions
are offered in the M6801, M6805, and M141000 Families.

RAM SIZE - On-chip RAM sizes range from 32 bytes in the M141000 Fami-
ly (organized as 64 nibbles) to 128 bytes in the M6801 Family. Between
these present limits are the M6805 Family versions and the M3870 at 64
bytes and 112 bytes. Architectures such as the M6801 and M6805 Families
which permit multi-level subroutines plus ROM and RAM data tables allow
you to trade-off ROM and RAM utilization. ROM usage can be minimized
with subroutines and look-up tables, while RAM use can be optimized with
ROM tables and fewer subroutines.

DIGITAL 1/0 - Single-chip MCUs are available in 40-pin dual-in-lioe

packages as well as the smaller (and lower cost) 28-pin packages. All four
MCU families include 40-pin versions, while the M6805 and M141000
Families also have 28-pin members. Five to seven pins serve power and
control functions permitting up to 23110 pins in a 28-pin package and up to
34 1/0 pins in 40-pin versions (including interrupts, timers, and special 1/0
functions). The M141000 Family has four dedicated input pins, with all
other 1/0 pins being outputs. All of the other MCUs offer essentially any mix
of inputs and outputs. Higher output drive current is available in the M6805
and M141000 Families.

EXPANSION BUS - The ROM-less versions include a bus to access off-

chip program memory and additional 1/0. However, the M6801 Family
single-chip MCUs also include three bus structure modes for off-chip ex-
pansion. The three bus modes permit the number of bus pins to be optimiz-
ed for the amount of address space needed off-chip.

INTERRUPTS - When an application program must synchronize to two or

more external events, interrupt hardware in some form is usually
necessary. The M6801 and M6805 Families include fully automatic inter-
rupts (registers are saved) with programmable vectors for both external
pins and internal timers. The MC3870 interrupt scheme requires more pro-
gram overhead. The M141000 Family serves the straight forward applica-
tions that do not need interrupts.

1-10
TIMERS - On-chip timers are the most frequently used special 1/0 func-
tion. Timers may generate interrupts to a program at a periodic rate, may
measure external values, may count external events, and may generate
measured output values. The M6801 Family includes a 16-bit timer that may
be used to perform three of the above functions simultaneously. The M6805
Family timer consists of a programmable 8-bit counter and a selectable
7-bit prescaler. The MC3870 timer is 8 bits with a decimal prescaler. The
M141000 Family does not include on-chip timers.
•
SPECIAL FUNCTIONS - Various members of the MCU families include
additional 1/0 functions. For example, the MC6801 Family includes a full
8-bit UART with baud rate generator on-chip. A 4-channel 8-bit AID con-
verter is included on a few M6805 Family versions. A 7-segment display
decoder is included on the M141000 Family parts. The digital portion of an
RF frequency synthesizer is added to an M6805 Family member.

DEVELOPMENT SUPPORT - All four families are fully supported on the

EXORciser development system. Included are assemblers, keyboard
debugging including breakpoints, user system emulation, and stand-alone
emulation. The M6801 Family has the added benefit of various high level
languages and compatibility with MC6800 programs.

THE CMOS M6805 COMPONENTS

Motorola offers an 8-bit CMOS processor in the MC146805E2. The CMOS
portion of the M6805 Family of 8-bit microprocessors, peripherals, and
single-chip microcomputers combines the low power characteristic of
CMOS, with the application flexibility of the M6800 Family.
The M6805 Family has evolved from the M6800 Family. The M6805 Family
includes similar programmable bidirection 110, flexible memory organiza-
tion, many memory reference instructions, interrupts, and multi-level
subroutine nesting. ROM use efficiency, bit manipulation instructions, and
improved table look-up indexing are M6805 Family enhancements of the
M6800 heritage.
The benefits of CMOS are added to Motorola's microprocessor repertiore.
Low operating power, and even lower standby power consumption, permit
battery operation, cut cooling costs, and reduces power supply expense.
The wider operating voltage range of CMOS offers higher noise immunity
and easier switching to standby power. Static CMOS parts permit true
standby operation plus power optimization with lower frequencies and
voltages.

1-11
PROGRAMMING - The enhanced M6800 architectural features make the
M6800 Family easy to program. The stack pOinter permits up to 32
subroutine levels. Three ROM-efficient indexed addressing modes allow
for look-up tables anywhere in memory. Any I/O pin or RAM bit may be
modified with a Single instruction. A branch may be taken depending upon
the bit state of any I/O pin or RAM bit with only a single instruction. RAM,
ROM, and I/O registers are all accessed with the same powerful memory
addressing instructions. An efficient instruction set permits programs to
be written faster, more easily optimized, and, therefore, more reliable.

INTERRUPTS - Real-time applications require sensing, measuring, and

controlling system events. Five vectored interrupts, which stack the pro-
gram registers, are included in M6805 Family processors to implement
these applications. For time dependent tasks, a programmable 8-bit
counter generates an interrupt when zero is reached. The timer includes a
program-selectable 7-bit prescaler and a software selectable input. The
timer input may be an external signal, pulse width measurement, or the on-
chip oscillator. An external interrupt pin is also provided. Software tech-
niques for external event synchronization are not needed.

MOTEL - The MOTEL concept (for MOtorola and InTEL bus compatibility)
allows both types of processors to be interchanged on a bus without
changing the design of the peripheral/memory system. The MOTEL circuit
automatically detects which type of processor is connected, and interprets
the bus control signals appropriately. The MCM65516 2K CMOS ROM,
MC146818 Real-Time Clock plus RAM, and MC146823 Parallel Interface in-
corporate the MOTEL concept to provide a high degree of system flexibility.

SINGLE·CHIP MICROCOMPUTERS - Dedicated single-chip MCUs are

also included in the M6805 Family. The MC146805F2 has 1K bytes of on-
chip ROM, while the MC146805G2 has a 2K ROM. The MC146805G2 also in-
cludes 112 RAM bytes, 32 input/output lines, programmable timer, external
and timer interrupts, and high current output pins. The 1K MC146805F2 has
the same interrupt features but fewer 110 lines, 28 pins, and a smaller RAM,
64 bytes. The MC146805E2 microprocessor serves as the ROM-less pro-
totyping part for both single-chip MCUs.

PERIPHERALS - Two types of CMOS peripherals are being added to

Motorola's CMOS family. Parallel bus-oriented peripherals support
microprocessors such as the MC146805E2, while single-chip microcom-
puters are supported by port-oriented I/O, usually using serial data transfer.
The MC146823 Parallel Interface offers three 8-bit ports (24 lines) of digital
interfacing, including port latch control Signals, to multiplexed-bus
microprocessors such as the MC146805E2. The MC146818 Real-Time Clock

1-12
plus RAM relieves the processor of maintaining the time and date,
generates timed interrupts, and includes 50 bytes of CMOS RAM. Program
memory is provided by the completely bus compatible MC65516 2K CMOS
ROM. Other support circuits include LCD drivers (MC1450OP, MC145001,
MC144115, and MC144117), LED drivers (MC14499 and MC144100), DIA con-
verters (MC144110 and MC144111), AID subsystem (MC14443 and
MC14447), latches (MC14099, MC14597, MC14598, and MC14599), remote
1/0 (MC14469) and frequency synthesizers (MC14156 and MC145144).

POWER SAVINGS - Energy efficiency is, of course, the chief CMOS at-
traction. CMOS MPUs are seriously considered anywhere a battery is used,
whether it be the primary or a back-up power source. The operating current
can be orders-of-magnitude lower. Standby modes can have power usages
order-of-magnitude lower yet. Since the M6805 Family is static in design,
low-speed operating current is extremely low.

STATIC DESIGN - The clock of a static CMOS microprocessor may be at

any frequency below the specified maximum. CMOS users frequently lower
the frequency, to conserve power, approaching the pOint where the pro-
cessor is fully loaded during the worst-case program cycle. A static MPU
allows operation at 1 kHz or 10 kHz in applications where battery drain is
critical, and the work load light. A static processor can also be stopped dur-
ing any cycle without losing any volatile information, which assures ex-
tremely low standby current.

PROGRAM CONTROL OF POWER - Typical CMOS microprocessor ap-

plications require considerable attention to minimizing power consump-
tion. The M6805 Family CMOS processors include program control of
power usage, as well as the traditional external power optimizing tools. The
program may initiate either of two standby modes, called Stop and Wait,
which halt program execution. The external or timer interrupts automatical-
ly turn the processor back on to allow execution to resume. Why not save
power when the program has no work to do? The program can be restarted
when there is work that needs doing. Battery drain is the average of
operating and standby current for the average work duty cycle.

LOW POWER DISSIPATION - A major side benefit of low power usage

is that the heat dissipated is also low. The costs of cooling equipment is
not needed. Fan noise in an office environment, as well as fan unreliability,
need not be endured. Systems may be enclosed in smaller housings. Air
tight systems need not have special heat conducting mechanisms.

WIDER VOLTAGE RANGE - The initial CMOS MPU products are

characterized to operate from 3.0 to 6.0 voltages. The voltage range is be-
ing extended to higher voltages in upcoming versions. The wider voltage
range permits lower cost power regulation, easier switching to back-up
sources, and lower cost batteries. The higher voltage parts add noise im-
munity to the wide voltage range benefits.

1-13
 SINGLE·CHIP MICROCOMPUTER FAMILIES FEATURES MATRIX

141000 Family M680S Family

•
MC1410001 MC141200 I MC141 099 MC3870 MC680SP2 I MC680SP4 I MC680SU2 I MC680SR2 I MC6805T2
Bits 4 Bits 8 Bits 8 Bits
Instruction Set TMS1000 F8 Control Optimization of MCS800
Registers 7 Special Registers 7 Registers 2 General Purpose and 3 Special Registers
Addressing Modes 5 Addressing Modes 5 Addr Modes 10 Addressing Modes
Processor
BaSIC Inst Types 43 Basic Inst Types 54 Basic Inst 59 Basic Instruction Types
Total Instructions 43 Total Instructions 76 Total Inst 207 Total Instructions
!,slAvg Inst 10 !'sllnstruction 1600 kHzl 4.7 !'sllnst 4.9 to 5.4 !'s per Average Instruction 11 MHzl
Subroutines 1 Subroutine Level 1 Level 13 Subroutine Levels
Technology CMOS NMOS HMOS
Mask ROM lK ROM lK ROM No ROM 2K ROM lK ROM 'lK ROM 2K ROM 2K ROM 2.5K ROM
Memory EPROM - - - - - - - - -
RAM Bytes 32 RAM 32 RAM 32 RAM 64 RAM 64 RAM 112 RAM 64 RAM 64 RAM 64 RAM
Package Size 28 Pins 40 Pins 48 Pins 40 Pins 28 Pins 28 Pins 40 Pins 40 Pins 28 Pins
Inputs 4 Inputs 4 Inputs 4 Inputs - - - 8 Inputs 2 to 5 In -
Inputl Outputs 19 Outputs 24 Outputs 21 Outputs - - - - - -
Output Mask Bidu - - - 32 I/O - - - - -
Pins Prog 8idir - - - - 20 I/O 20 I/O 241/0 24110 191/0
Spec. Func - - - - - - - 1 to 4 Analog 2 Special
Expansion Bus - - o ROM, PLA - - - - - -
Display Oecoder 7·Segment PLA - - - - - - -
Special High Current Orive 20 mA, All Outputs - 10 mA Drive on 8 Pins
Function Analog Inputs - - - - - - - 8·BIIAID -
I/O Serial I/O - - - - Shift Register I/O With Bit Mampulation Instructions
Freq Synth - - - - - - - - Freq Synth
Standby RAM - - - - - Stby. RAM - - -
Prescale Bits : 200 Prescale 7 Prescaler Bits
Timer Counter Bits No Timer 8·Bit Counter B·Bit Counter
Timer Functions 1 function 1 Timer FunCllon at a Time
Timer Interrupt Timer IRO or Trer Interrupt
Interrupts External IRO No Interrupts 1 Ext IRO 1 Ext IRO 2 Ext IROs 1 Ext IRO
Serial I/O IRO - - - - - -
ICs ROM·Less Version - EPROM and ROM· Less Versions
Dev System EXORciser'" EXORciser'" EXORCiser'"
Development
Emulation User System Emulator USE User System Emulator
Support
Assembler Assembler Assembler Macro Assembler
HL Language - - -

SINGLE·CHIP MICROCOMPUTER FAMILIES SELECTOR GUIDE

TECHNOLOGY PROCESSING POWER

HMOS/NMOS Page CMOS Page 4-Bit Page a-Bit Page
MC6805P2 4-146 MC141000 4-968 MC141000 4-968 MC6805P2 4-146
MC6805P4 4-168 MC141099 4-968 MC141099 4-968 MC6805P4 4-168
MC6805R2 4-191 MC141200 4-968 MC141200 4-968 MC6805R2 4-191
MC6805T2 4-216 MC146805E2 4-985 MC6805T2 4-216
MC6805U2 4-243 MC146805F2 4-1019 MC6805U2 4-243
MC68705P3 4-894 MC146805G24-1021 MC68705P3 4-894
MC68705R3 4-918 MC68705R3 4-918
MC68705U3 4-945 MC68705U3 4-945
MC3870 4-32 MC3870 4-32
MC146805E2 4-985
MC146805F2 4-1019
MC146805G2 4-1021

1-14
 MC6805 Family (continued) M6801 Family

•
MC68705P3JMC88705U31MC68705R31 MC146805G21 MC146805F21 MC146805E2 MC6801 1 MC68701 1 MC6803
8 BIts 8 Bits B,ts
Control OptimIzatIon of MC6800 Super Set of MC6800 Instruction Set
2 General Purpose and 3 SpecIal RegIsters 2 General. 4 SpeCIal Reg. RegIsters
10 AddressIng Modes 7 AddressIng Modes AddressIng Modes
59 BasIc Instruction Types 61 BasIc Inst Types 75 BasIc Inst Types BasIc Inst Types Processor
207 Total InstructIons 209 Total InstructIons 219 Total InstructIons Total Instructions
.9 to 5.4 "s per Average InstructIon (1 MHzl 3.9 to 4.0 "slAvg Inst (1 MHzl 3.7 "slAvg Inst (1 MHz) "slAvg Inst
13 Subroutone levels L
29 levels . 13 levels . t 29 levels IndefInite levels SubroutInes
HMOS CMOS HMOS Technology
- - - 2K ROM lK ROM No ROM 2K ROM - No ROM Mask ROM
1.8K EPROM 3.8K EPROM 3.8K EPROM - - - - 2K EPROM - EPROM Memory
112 RAM 112 RAM 112 RAM 112 RAM 64 RAM 112 RAM 128 RAM 128 RAM 128 RAM RAM Bytes
28 Pins 40 Pons 40 Pons 40 PIns 28 PIns 40 PIns 40 P,ns 40 P,ns 40 Pins Package Size
- 8 Inputs 2 to 5 In - 4 Inputs - Inputs
- - - - - - - - - Outputs Inputl
- - - - - - - - - Mask Bldor Output
20 I/O 241/0 241/0 321/0 16110 161/0 24 to 31 110 Prog Bldlr Pons
- - 1 to 4 Analog - - - o to 7 SpeCIal Funct PIns Spec. Func
- - - - - 8K Addr 64K Addressabdl\y ExpansIon Bus
- - - - - - - - - D,splay Decoder
lOrnA Drove on 8 PIns 10 rnA. 4 P,ns - - - - - HIgh Current Drove SpecIal
- - 8·Blt AID - - - - - - Analog Inputs FunctIon
Shoft RegIster 110 wIth BIt ManipulatIon InstructIons 8·Blt UART + BIt Rate Gen. Seroall/D I/O
- - - - - - - - - Freq Synth
- - - - - - - - - Standby RAM
7 Prescaler BIts - - - Prescale BIts
8·Blt Counter 16·Bit T,mer Counter B,ts T,mer
1 Timer FunctIon at a T,me 3 Simultaneous Timer FunctIons Tomer FunctIons

1 Ex~IRO I -
2 Ext IROs
-
T,mer (terru:
1 ExtlRO
- -
3 Timer Interrupts
2 Ext Interrupts
2 Seroal I/O IRQs
TImer Interrupt
External IRQ
Seroall/D IRQ
Interrupts

EPROM and ROM· less VersIOns EPROM and ROM-less VersIons ICs
EXORciser'" EXORcIser'" Dev System Development
User System Emulator User System Emulator EmulatIon Support
Macro Assembler Macro Assembler Assembler
- Fortran. BasIc. MPl Hllanguage

FUNCTIONAL BLOCKS LANGUAGE ORIENTATION

Low-Level
MPU with Language Page
On-Chip RAM Page MCU Page MC6805P2 4-146
MC141099 4-498 MC6805P2 4-146 MC6805P4 4-168
MC146805E2 4-985 MC6805P4 4-168 MC6805R2 4-191
MC6805R2 4-191 MC6805T2 4-216
MC6805T2 4-216 MC6805U2 4-243
MC6805U2 4-243 MC68705P3 4-894
MC68705P3 4-894 MC68705R3 4-918
MC68705R3 4-918 MC68705U3 4-945
MC68705U3 4-945 MC3870 4-32
MC3870 4-32 MC141000 4-968
MC141000 4-968 MC141099 4-968
MC141200 4-968 MC141200 4-968
MC146805F2 4-1019 MC146805E2 4-985
MC146805G2 4-1021 MC146805F2 4-1019

1-15
------- -
 16·BIT MICROPROCESSORS (MPUs)
THE M68000 FAMILY AN INVESTMENT IN THE FUTURE

• The family concept has been extremely popular in the Microprocessor in-
dustry. Motorola pioneered this family concept with the introduction of the
M6800 Family in 1974. Led by the MC68000 Microprocessing Unit (MPU) in
1979 and followed by a host of peripherals, the M68000 Family offers the
engineer a set of building blocks to construct cost-effective solutions to an
ever-widening range of complex 16/32 bit applications. The tremendous
popularity of the M68000 Family is not without warrant. HMOS technology,
performance, and support are but a few of the many reasons why the
M68000 Family continues to be the 16-bit industry leader.
It should be noted that the M68000 Family is a not-so-distant relative of the
MC6800. All M6800 Family peripherals interface directly with the MC68000,
so upward compatibility is built-in. Where lost cost and medium perform-
ance are required, they present a very attractive alternative. The plan for
the M68000 Family is a simple one. Provide the marketplace with the best
16-bit family and back it up with support that is second to none. And it's
happening now.
What about expandability? The M68000 Family is designed with this in
mind. All the way from an internal microcoded 32-bit architecture to the
third-generation EXORmacs development system. Efficient high level
language support provided by Pascal allows upward compatibility of soft-
ware from 8-bit to 16-bit to 32-bit machines.

The majority of today's 16-bit microprocessor applications are quite

complex, with long design times. Clearly, the required investment in design
resources requires finished products to have increased longevity. Motorola
understands this, and is committed to offering a family which will allow
these products to remain state-of-the-art for years to come. Thus, the
M68000 Family is an investment in the future.
The following list represents the currently available 16-bit products. Con-
tact your Motorola representative for additional information.

16·BIT PRODUCT LISTING

Processor Page
MC68000 - 16-8it Microprocessing Unit .................... 4-661

Peripherals
MC68120/121 - Intelligent Peripheral Controller .............. 4-711
MC68122 - Cluster Terminal Controller ..................... 4-755
MC68230 - Parallellnterface/Timer ........................ 4-783
MC68450 - Memory Management Unit ...................... 4-812
MC68451 - Direct Memory Access Controller ............. " .. 4-818

1-16
 PERIPHERAL AND INTERFACE COMPONENTS

Motorola manufactures and is continuing in new design efforts to provide

you with an extensive selection of efficient, cost effective peripheral and
interface components.

PERIPHERAL AND INTERFACE COMPONENTS SELECTOR GUIDE

FOR NMOS/HMOS MICROPROCESSOR SYSTEMS Page

For MC6800 Two·Phase Clock Generation
MC6870A, 6871A, 6871 B - Two-Phase Microprocessor Clocks .. .4-605
MC6875 - Two-Phase Clock Generator ..................... .4-612

For Parallel·Oriented Applications

MC6821 - Peripheral Interface Adapter ..................... .4-335
MC6822 - Industrial Interface Adapter ....................... 4-345
MC6828 - Priority Interrupt Controller ...................... .4-348
MC6840 - Programmable Timer ........................... .4-406
MC68488 - General Purpose Interface Adapter. .............. .4-836

For Serial Applications

MC6850 - Asynchronous I nterface Adapter .................. 4-527
MC6852 - Synchronous Serial Data Adapter .................. 4-536
MC6854 - Advanced Data Link Controller ................... .4-550
MC6855 - Serial Direct Memory Access Controller ............ 4-572
MC6860 - Digital Modem .................................. 4-583
MC6862 - Digital Modulator ............................... 4-597
MC68122 - Cluster Terminal Controller ...................... 4-755

For Complex Peripheral Control

MC6829 - Memory Management Unit ........................ 4-356
MC6835 - CRT Controller .................................. 4-371
MC6839 - Floating Point ROM ............................ .4-392
MC6843 - Floppy Disk Controller ........................... 4-419
MC6844 - Direct Memory Access ........................... 4-441
MC6855 - Serial Direct Memory Access Processor ............ 4-572
MC6859 - Data Security Device ............................. 4-574
MC68120/MC68121 - Intelligent Peripheral Controller .......... 4-711

For Television Display

MC1372 - Color TV Video Modulator. . . . . . . . . . . . . . . . . . . . . . .. 4-5
MC6847 - Video Display Generator ......................... 4-499

1-17
 PERIPHERAL AND INTERFACE COMPONENTS
SELECTOR GUIDE (CONTINUED)

• FOR SYSTEM EXPANSION

MC3446 - Quad Bidirectional Bus Transceiver .......................... . 4-13
MC3447 - Octal Bidirectionallnst. Bus (GPIA) Transceiver ..... . 4·16
MC3448 - Quad Bidirectional Inst. Bus (GPIB) Transceiver ..... . 4-22
Page

MC34821MC6882 - Quad Buffer Latch ........................................ . 4-28

MC6880AlMC68T26 - Quad Bus Transceiver ............................ .. 4·624
MC6889/MC8T28 - Quad Bus Transceiver .................................. . 4-655

FOR CMOS SYSTEMS

MC146818 - Real·Time Clock plus RAM .................... 4.1046
MC146823 - Parallel Interface ............................ 4-1066

1·18
The Motorola M6800 Generic Bus
Concept and Use
•

2-1
II

2·2
 THE M6800 GENERIC BUS CONCEPT AND USE
M6800 - M6801 - M6802 - M6809
M6800 FAMILY PERIPHERALS
After more than 5 years of experience shipping many millions of
microprocessors and peripherals, Motorola has collected, coordinated,
and improved the bus timing parameters for these 8-bit devices. The
smaller geometries and reduced capacitances obtained by introduction of

•
optical reductions of existing mask sets, the use of new process tech-
niques such as HMOS I and HMOS II, and the natural improvement in prod-
uct yield that comes with experience have allowed Motorola to improve
many performance parameters.

The new enhanced peripheral bus timing specifications allow their use in
even wider ranges of applications and yet maintain complete compatibility
with existing systems. This section provides a discussion about:
• The Generic Bus concept for both a-bit NMOS/HMOS and CMOS
devices.
• A complete set of bus timing for all of the a-bit microprocessors
(except the MC6800) and peripherals in one table (grouped by
speed).
• A set of equations for calculating worst-case bus timing. These
appear as notes under appropriate Generic Bus timing diagram.
The bus timing diagram shown in Figure 2-1 illustrates the waveforms
needed for or generated by all but two of Motorola'S mid-range family of
8-bit microprocessors and peripherals. (The MC6800, although it began the
family, is not shown, due to the nature of the 4>1,4>2, and DBE input signals.)
A generic bus timing characteristics table gives a side-by-side comparison
of major microprocessor types within the M6800 family, along with the in-
put and output specifications common to all bus peripherals. These tables
are shown as Tables 2-1 through 2-3.

A subset of the generic bus timing diagram and characteristics table ap-
pears in each data sheet (except the MC6800 and MCM6810) showing only
the signals and identification numbers appropriate to that part.

A standard bus specification such as this allows a comparison of

multiplexed and non-multiplexed processors; all timings associated with a
particular system are shown together, which makes worst-case design
easier.

2-3
 FIGURE 2·1. NMOS/HMOS GENERIC BUS TIMING DIAGRAM

"i'
~
--= 2
E V 1\
-. 4-0 07)_ _ f3'
-+ +-0 0 ..... ~
~
6
~
kD
r 0 J

•
J 6

- - I~
Q

*"-0 ~ ~ 1+0 -~
~
~ >~,,:,;
R/W, Address
INon-Muxedl ~
.--@ @Notel0 @)
12

~ l@ -,. @)
1+115
cs V
Note 7 I@+ 1+ \
~f-® 30 ®.~®-+ ~ 1
Read Data MPU Read Data Non-Muxed
Non-Muxed Ir

I+F--€>' ®
Note 9
Note 11
-I" ~118
Addr/Data
Muxed m-
-. *-® OO
Note 8
Read Data Muxed
~
'22'. 19 ®... ~@~
Write Data MPU Write Data Non-Muxed
Non-Muxed Ir
~ @ @) Note 12 @- ~
Addr/Data Write Data M uxed
Muxed
I---
00 Note 8 Ir-
@ @)- f4-- ~@-+
I-@~
Address
Strobe lAS 1 II 1\
-~
0-+ I+- ~ I-@)
~ ~

NOTES.
1 Not all signals are applicable to every part
2. Voltage levels shown are VLSO 4 V, VH~2A V, unless otherwise specified
3 Measurement POints shown are 0 8 V and 20 V, unless otherwise specified
4 For MC6800, write data IS referenced to DBE, not E, see M6800 pages.
5. For MC6800, address delay IS referenced to <1>1, not E, see M6800 pages
6 Clock pulse rise and fall time for MC6800 measured to V CC - 06 V, see M6800 pages
7. CS and CS on MC6810 have same timing
8 Address valid on the occurrence of the latest of 11, 12, 16, 22, or 23
9 Usable acce'ss time IS computed by 1 - 14 + 11 + 171, or 12 + 4 - 17, see note 8 lexcept for MC6809,
for MC6809, by 1-4-7 max +10-171
10. Usable address buffer time IS computed by 2- III + 131, see note 8 lexcept for MC6809,
for MC6809, by. 2-7 max+ 10-131.
11 Usable read data buffer time IS computed by 3 - 117 + 301
12 Usable write data buffer time IS computed by' 3-119+311, except for MC6809;
for MC6809, by: 1- 14+ 7 max+4+ 20+ 311

2-4
 TABLE 2·1. NMOS/HMOS GENERIC BUS TIMING CHARACTERISTICS
FOR 1.0 MHz OPERATION
68211
Ident. 6800 6801 6802 6809 6859
Number Characteristics Symbol Min Max Min Max Min Max Min Max Min Max Unit
1 Cycle Time teye 1.0 10 10 2.0 10 10 10 10 10 10 "s
2 Pulse Width, E Low (See Note 6) PWEL 405 9500 430 1000 450 5000 430 5000 430 9500 ns

•
3 Pulse Width, E 'Hlgh (See Note 6) PWEH 450 9500 450 1000 450 9500 450 9500 450 9500 ns
4 Clock Rise and Fall Time (See Note 61 tr,tf - 100 - 25 - 25 - 25 - 25 ns
5 Pulse Width, Q High PWQH - - - - - - 430 5000 - - ns
6 Pulse Width, Q Low PWQL - - - - - - 450 9500 - - ns
7 Delay Time, E to Q Rise· tAVQ - - - - - - 200 250 - - ns
9 Address Hold Time tAH 30 - 20 - 20 - 20 - 10 - ns
10 Address Valid Time to Q Rise> tAQ - - - - - - 50 - ns
11 Address Delay from E Low (See Note 51 tAD - 270 - - - - - - - - ns
12 Non-Muxed AddressValldTlmeto E> (MPUI tAV - - 200 - 160 - - - - - ns
13 Addres Setup Time Before E (Penph I tAS - - - - - - - - 80 - ns
14 Chip Select Setup Time Before E tcs - - - - - - - - 80 - ns
15 Chip Select Hold Time tCH - - - - - - - - 10 - ns
16 Non-Muxed Address Delay Time from AS tAD - - - - - - - - - - ns
17 Read Data Setup Time tDSR 100 - 80 - 100 - 80 - - - ns
18 Read Data Hold Time TDHR 10 - 10 - 10 - 10 - 20 50 ns
19 Write Data Delay Time (See Note 41 tDDW - 225 - 225 - 225 - - - - ns
20 Data Delay Time from Q tDDQ - - - - - - - 200 - - ns
21 Write Data Hold Time (See Note 41 tDHW 10 - 20 - 30 - 30 - 10 - ns
22 Muxed Address Valid Time to E Rise> tAVM - - 200 - - - - - - - ns
23 Muxed Address Delay Time from AS tADAS - - - - - - - - - - ns
24 Muxed Address Valid Time to AS Fall> tASL - - 60 - - - - - - - ns
25 Muxed Address Hold Time tAHL - - 20 - - - - - - - ns
26 Delay Time, AS to E Rise> tASD - - 90 - - - - - - - ns
27 Pulse Width, AS High> PWASH - - 220 - - - - - - - ns
28 Delay Time, AS to E Rise> tASED - - 90 - - - - - - - ns
29 Usable Access Time> (See Note 91 tACC 605 - 570 - 605 - 695 - - - ns
30 Peripheral Output Data Delay Time tDDR - - - - - - - - - 290 ns
31 Peripheral Input Data Setup Time tDSW - - - - - - - - 165 - ns
Buffer Loglc....Q.elay..!!me
32
Address, CS, RIW (See Note 101 tBDA 55 - 120 - 100 - 150 - - - ns

Buffer Delay Time, Read Data

33
(See Note 11) tBDR 60 - 80 - 60 - 80 - - - ns

Buffer Delay Time, Write Data

34
(See Note 121 tBDW 60 - 60 - 60 - 365 - - - ns

>At specified cycle time

2·5
 TABLE 2·2. NMOS/HMOS GENERIC BUS TIMING CHARACTERISTICS
FOR 1.5 MHz OPERATION

68A211
Ident. 68AOO 68A01 68A02 68AOS 68A59
Number Characteristics Symbol Min Max Min Max Min Max Min Max Min Max Unit
1 Cycle Time tcyc 0667 10 0667 2.0 0.667 10 0667 10 0667 10 I's
2 Pulse Width, E Low (See Note 6) PWEL 230 9500 300 1000 280 5000 280 5000 280 9500 ns

•
3 Pulse Width, E High (See Note 6) PWEH 280 9500 300 1000 280 9700 280 9700 280 9500
4 Clock Rise and FaU Time (See Note 6) tr,tf - 100 - 25 - 25 - 25 - 25 ns
5 Pulse Width, a High PWaH - - - - - - 280 5000 - - ns
6 Pulse Width, a Low PWaL - - - - - - 280 9700 - - ns
7 Delay Time, E to a Rise" tAva - - - - - - 130 165 - - ns
9 Address Hold Time tAH 30 - 20 - 20 - 20 - 10 - ns
10 Address Vahd Time to a Rise" tAa - - - - - - 25 - - - ns
11 Address Delay from E Low (See Note 5) tAD - 180 - - - - - - - - ns
12 Non-Muxed AddressVahdTlmetoE"(MPU) tAV - - 115 - 100 - - - - - ns
13 Address Setup Time Before E (Perlph ) tAS - - - - - -. - - 60 - ns
14 Chip Select Setup Time Before E tcs - - - - - - - - 60 - ns
15 Chip Select Hold Time tCH - - - - - - - - 10 - ns
16 Non-Muxed Address Delay Time from AS tAD - - - - - - - - - - ns
17 Read Data Setup Time tDSR 60 - 60 - 70 - 60 - - - ns
lB Read Data Hold Time TDHR 10 - 10 - 10 - 10 - 20 50 ns
19 Wnte Data Delay Time (See Note 4) to OW - 200 - 170 - 170 - - - - ns
20 Data Delay Time from a tDDa - - - - - - - 140 - - ns
21 Wnte Data Hold Time (See Note 4) tDHW 10 - 20 - 20 - 30 - 10 - ns
22 Muxed Address Vahd Time to E Rise" tAVM - - 115 - - - - - - - ns
23 Muxed Address Delay Time from AS tADAS - - - - - - - - - - ns
24 Muxed Address Vahd Time to AS FaU" tASL - - 40 - - - - - - - ns
25 Muxed Address Hold Time tAHL - - 20 - - - - - - - ns
26 Delay Time, AS to E Rise" tASD - - 60 - - - - - - - ns
27 Pulse Width, AS High" PWASH - - 140 - - - - - - - ns
28 Delay Time, AS to E Rise' tASED - - 60 - - - - ns
29 Usable Access Time" (See Note 9) tACC 400 - 345 - 310 - 440 - ns
30 Peripheral Output Data Delay Time tDDR - - - - - - - 180 ns
31 Peripheral Input Data Setup Time tDSW - - - - - - - 80 ns
Buffer LogiC Delay Time
32
Address, CS, R/W (See Note 101 tBDA 40 - 55 - 40 - 80 - - - ns

Buffer Delay Time, Read Data

33
(See Note 11) tBDR 30 - 40 - 20 - 30 - - - ns

Buffer Delay Time, Wnte Data

34
(See Note 12) tBDW 0 - 50 - 30 - 230 - - - ns

" At specified cycle time

2·6
 TABLE 2·3. NMOS/HMOS GENERIC BUS TIMING CHARACTERISTICS
FOR 2.0 MHz OPERATION

68B21 1
Ident. 68BOO 68B01 68B02 68B09 68B59
Number' Characteristics Symbol Min Max Min Max Min Max Min Max Min Max Unit
1 Cycle Time teye 05 10 05 20 05 10 05 10 05 10 I's
2 Pulse Width. E Low ISee Note 61 PWEL 210 9500 210 1000 210 5000 210 5000 210 9700 ns

•
3 Pulse Width. E High ISee Note 61 PWEH 220 950 220 1000 220 9700 220 9700 220 9700 ns
4 Clock Rise and Fall Time ISee Note 61 t r• tf - 100 - 20 - 20 - 20 - 20 ns
5 Pulse Width. 0 High PWOH - - - - - - 210 5000 - - ns
6 Pulse Width, 0 Low PWOL - - - - - - 220 9700 - - ns
7 Delay Time, E to 0 Rise' tAVO - - - - - - 80 125 - - ns
9 Address Hold tAH 30 - 10 - 20 - 20 - 10 - ns
10 Address Valid to 0 Rise' tAO - - - - - - 15 - - - ns
11 Address Delay from E Low I See Note 51 tAD - 150 - - - - - - - - ns
12 Non-Muxed Address Valid T,metoE'IMPU) tAV - - 70 - 50 - - - - - ns
13 Address Setup Time Before E IPeriph I tAS - - - - - - - - 40 - ns
14 Chip Select Setup Time Before E tcs - - - - - - - - 40 - ns
15 Chip Select Hold Time tCH - - - - - - - - 10 - ns
16 Non-Muxed Address Delay Time from AS tAD - - - - - - - - - - ns
17 Read Data Setup Time tDSR 40 - 40 - 60 - 40 - - - ns
18 Read Data Hold Time TDHR 10 - 10 - 10 - 10 - 20 50 ns
19 Wnte Data Delay Time ISee Note 41 to OW - 160 - 120 - 160 - - - - ns
20 Data Delay Time from 0 tDDO - - - - - - - 110 - - ns
21 Wnte Data Hold Time ISee Note 4) tDHW 10 - 10 - 20 - 30 - 10 - ns
22 Muxed Address Valid Time to E Rise' tAVM - - BO - - - - - - - ns
23 Muxed Address Delay Time from AS tADAS - - - - - - - - - - ns
24 Muxed Address Valid Time to AS Fall' tASL - - 20 - - - - - - - ns
25 Muxed Address Hold Time tAHL - - 10 - - - - - - - ns
26 Delay Time, AS to E Rise' tASD - - 45 - - - - - - - ns
27 Pulse Width, AS High' PWASH - - 110 - - - - - - - ns
28 Delay Time, AS to E Rise' tASED - - 45 - - - - - - - ns
29 Usable Access Time" ISee Note 9) tACC 290 - 260 - 235 - 330 - - - ns
30 Peripheral Output Data Delay Time tDDR - - - - - - - - - 150 ns
31 Peripheral Input Data Setup Time tDSW - - - - - - - - 60 - ns
Buffer Logl"-.Qelay2!me - - - - -
32 tBDA 20 30 10 60 ns
Address, CS, R/W ISee Note 101
Buffer Delay Time, Read Data
33
ISee Note 111 tBDR 30 - 30 - 15 - 30 - - - ns

Buffer Delay Time, Write Data - - - - -

34 tBDW 0 - 40 0 160 ns
I See Note 121

• At specified cycle time

2·7
 DIAGRAM/TABLE USE

As an example of the use of the timing diagram, consider the simple bus
connections of an MC6809 executing a read bus cycle with a peripheral
such as the MC6821 shown in Figure 2-2. The bus cycle, identified as #1 in
Figure 2-1 begins when E (#4) falls. The address output of the MC6809 is
valid prior to the rising edge of Q by time #10.

• The MC6821, as well as all other bus peripherals, requires that the register
select inputs, derived from the address bus, be valid prior to the rising edge
of E by time #13. Similarly, address decoding for assertion of chip select(s)
must be valid by time #14. The time available for address buffers and
decoding logic is given by #32 and can be calculated from the equation in
note 10.

FIGURE 2·2. SIMPLE BUS CONNECTION - EXAMPLE

Address RSO, 1
AO-A15 CSO
Address CS1
MPU Decode MC6821
CS2
MC6809 PIA

Data
DBO-DB7

2-8
At 1 MHz, the characteristics table for the MC6809 shows that 150
nanoseconds are available for the combination of the two 74LS240 address
buffers in series with the address decoding logic shown in Figure 2-2. Stan-
dard LS-series buffers and gates may easily be used in such a case. At
2 MHz, the MC6809 provides 60 nanoseconds for address decoding logic.
Characteristic #32 on the 2 MHz table also illustrates the dramatic improve-
ment in technology attendant with the introduction of the MC6801 and
MC6809 when compared with the MC6800 and MC6802. Schottky buffering
is easily done in a 2 MHz system with either of these newer processors; the
MC6809 even allows ample time for use of LS-series buffers at 2 MHz. II
To continue with the example, data access occurs and output buffers are
enabled within the MC6821 for the duration of E (#3) when chip select is
asserted. The peripheral output data will be valid by time #30. Propagation
through any data bus buffer must be done quickly to ensure valid data to
the MC6809 on or before the read data setup time (#17). This read buffer
delay time is #33. The overall time between the existence of a valid address
output from the microprocessor and the required input data valid (read
setup time) is called the usable access time and is characteristic #29. This
is the time provided by the microprocessor at any given bus rate, for ad-
dress buffers, address decoders, ROM/RAM access time, and data bus buf-
fers.

Table 2-4 shows a comparison of the different buffering arrangements

possible in the various speed ranges for the MC6809 used in the example,
and also for the MC6802 in a similar system. The buffers and gates listed
are a representative sampling of those available. At 2 MHz, the MC68B02
does not provide any buffer delay time for a write operation. As a result,
when operating at 2 MHz, the MC68B02 is limited to small unbuffered
systems.

2-9
 TABLE 2·4. BUFFER TIME EXAMPLES

Available Available Available

Available Margin
Address Buffers Margin Data
MPU Buffers (ns)
Buffer / Decode and Decode (ns)
Buffer Time (ns) (ns)
Time (ns) (ns) R W

•
R W
MC6888/8T28 MC68801
MC6809 150 +7440 108 80 365 8T26 52 337
(10+ 10+22) (14+14)
MC6888/8T28 MC68801
MC68A09 80 MC+ 74LS40 36 30 230 8T26 2 202
(10+ 10+24) (14+4)
MC6888/8T28 MC68801
MC68B09 60 MC+ 74LS40 16 30 160 8T26 2 132
(10+10+24) (14+14)
MC74LS240
MC6802 100 MC+ 74LS40 44 60 60 MC74LS240 28 28
(14+ 18+24)
MC74LS240
74S240
MC68A02 40 MC+74LS40 2 20 30 6 16
(7+ 7)
(7+ 7+24)
MC68802 10 74S40= (6) 4 15 0 - 15 0

In the case of multiplexed·bus parts such as the MC6801 and MC68120, ad·
ditional consideration must be given to the multiplexed address output.
The address is defined to be valid, in the case of the MC6801, prior to the
fall of address strobe by time #24. (In the MC68120, address is valid after
the rise of address strobe by time #23.) This is sufficient time to allow cap·
ture of the address by a transparent latch, such as the 74LS373. The prop·
agation time required by this latch, and the location of address strobe
within the E low time, reduces the time available for address decoding.

2·10
When this approach is used with processors that include an on-chip
oscillator (e.g., MC6801, MC6802, MC6809), specify address valid by
xx (#10, #12, or #24) nanoseconds before E or Q rise or AS fall.

When this approach is used with processors that require external E or AS

input (e.g., MC6809E or MC68120), specify address valid by xx (#11 or #23)
nanoseconds after E fall or AS rise.

Do not consider the address output of any microprocessor valid until all ap-
propriate parameters (#11, #12, #16, #22, or #23) have been considered.

THE CMOS GENERIC BUS

The timing diagrams shown in Figure 2-3 and the timing characteristics
given in Table 2-5 may be considered as a special case of the generic bus.
This information pertains to Motorola's rapidly expanding family of CMOS
microprocessors and peripherals, beginning with the MC146805E2 and the
MC146818.

The identification numbers shown are consistent with those in Figure 2-1
for the NMOS/HMOS generic bus. The waveforms have been drawn to in-
dicate the input and output relationships of the MC146805E2 and
MC146818. The characteristic table shows, in addition to the MC146805E2
and the MC146818, timing characteristics for Motorola's CMOS ROM, the
MCM65516, available in two speed ranges. Both the MCM65516 and the
MC146818 contain the MOTEL circuit, allowing direct application to both
the Motorola generic bus and the competitive 8085-type bus. Always refer
to the latest data sheet or other technical documentation for up-to-date
characteristics for all Motorola microcomponents.

2-11
 FIGURE 2·3. CMOS GENERIC BUS TIMING DIAGRAM

~~

•
AS
1/

----,
0-- - 0- ~@..
CD f--@-- - ~0

DS ~-- 0 '3'

®
-+
8,_ ~0
-00 13
--+ ~0 0--
-
-.-0
R/W
00
ro@@@)~ 1+-,
1+-- 19/ _
~@+ ::@~~- ®
_(16
~

A8-A 11
W() N~te ( Valid AD DR

-- ~ ~
--\ 1-0-0 @- --
/

-
Note4
® @ ®
~ ~ ~ -@--®---@- ~ -+ ;§2
80-8 7
MPU Write
~ 'IJ Valid ADDR
00 lftjJ Valid
Write
Data~ IJ __
-- -@ -+
-@- .@..
~@
@
~ -@--=; ~ -- ~@

--
k:--=-

~
80-8 7 Valid ( Valid Read Data
ADDR
MPU Read

@
-+
-® Note3

Note 1
NOTES:
1. Available access time:
mux=24 (MPU) +28+3-17
non-mux= 27 + 28+3-17 -16
2. Buffer delay (address):
mux= 24 (MPU) - 24 (penpheral)
non-mux=27-16-24 (penpheral)
3. Buffer delay (data read) = 3- 30-17
4. Buffer delay (data wnte)=3-19-31
5. VLow=0.5 V, VHlgh=2.0 V for VOO=3 V;
VLow=0.8 V, VHlgh=VOO-2.0 V for VOO=5 V ± 10%.

2-12
 TABLE 2·5. CMOS GENERIC BUS TIMING CHARACTERISTICS
FOR 1.0 MHz OPERATION

Ident. MCl46805E2 MCl46818 MC65516-43 MC65516-55

Characteristic Symbol Unit
Number Min Max Min Max Min Max Min Max

•
1 Bus Cycle Time tcyc 1000 DC 953 DC 580 DC 725 - ns
2 Pulse Width, OS Low PWDSL 560 300 ns
3 Pulse Width, OS High PWDSH 375 - 325 - - - - - ns
4 Clock Rise and Fall Time t r , tf - 30 - 30 - - - - ns
8 R/W Hold Time tRWH 10 - - - - - - - ns
9 Non-Muxed Address Hold Time tAH 100 - - - 50** - 80 - ns
11 R/W Delay Time from OS tRW.ll. - 300 - - - - - - ns
13 R/W Setup Time to OS tRWS - 195 - - - - - - ns
14 Chip Enable Setup Time to AS Fall tCES - - 55 - 50 - 50 - ns
15 Chip Enable Hold Time tCEH - - 0 - 50** - 80 - ns
16 Non-Muxed Address Delay Time from AS tAD 0 100 - - - - - - ns
17 Read Data Setup Time tDSR 115 - - - - - - - ns
18 Read Data Hold Time tDHR 0 140 10 100 0 160 0 160 ns
19 Wnte Data Delay Time tDDW - 120 - - - - - - ns
21 Write Data Hold Time tDHW 55 - 0 - - - - - ns
23 Muxed Address Delay Time from AS tADAS 0 120 - - - - - - ns
24 Muxed Address Valid Time to AS Fall * 1ASl 55 - 55 - 50 - 50 - ms
25 Muxed Address Hold Time tAHL 60 180 20 - 50 - 80 - ns
26 Delay Time, OS to AS Rise * tDSD 180 - 50 - 50 - 50 - ns
27 Pulse Width, AS Hlgh* PWASH 175 - 100 - 150 - 175 - ns
28 Delay Time, AS to OS Rise * tASDSD 180 - 90 - 100 - 160 - ns
29 Usable Access Tlme*(See Note 11 tACC 475 - - - - 430 - 550 ns
30 Peripheral Output Data Delay Time tDDR 260 - 20 240 175 - 200 - ns
31 Peripheral Input Data Setup Time tDSW - - 220 - - - - - ns
32 Buffer LogiC Delay Time Address, CS, R/W - - - - - - -
tBDA 5 ns
(See Note 21
33 Buffer Delay Time, Read Data (See Note 31 tSDR 20 - - - - - - - ns
34 Buffer Delay Time, Wnte Data (See Note 41 tBDW 35 - - - - - - - ns

*At specified cycle time

** Hold times for MCM65516 are from AS fall and are easily met by MCl46805E2

2·13
II

2-14
 Reliability •

3-1
II

3-2
 MOTOROL.A INC.
MOS Integrated Circuits Division

RELIABILITY REPORT
NUMBER 8110

THE MC6800
MICROPROCESSOR FAMILY

MARCH 1981

PREPARED BY: k'-"<JO-<J l"'j

DANDASTANG
MICROPROCESSOR

g
RELIABILITY ENGINEERING

APPROVED B Y : C / :!:.
ED DASSE, M NAGER
MOS RELIABILITY ENGINEERING

Motorola: the Reliability Name In Semiconductors

Test results contained herein are for information only. This report does not alter
Motorola's standard warranty or product specifications.

3-3
 Introduction
Motorola conducts extensive reliability testing to evaluate new processes and
materials, and to monitor performance levels. The test methods used to evaluate the
MC6800 family of NMOS LSI microprocessors and peripheral device types are described
in this report. Data reduction techniques and prediction models are included, in addition
to a comprehensive summary of life and environmental test data. The life test data base
consists of results obtained on 8,761 devices representing twenty different types, in·
cluding two recently introduced circuits. Sixty percent of the life test data and all of the
environmental test results constitute new information not available in previous reports.
After five million device-hours of 125°C testing, an overall 70·C failure rate of
0.032%/1000 hours was observed. This performance is particularly impressive when the
complexity and density of microprocessors are considered.
Also of significance is the exceptional environmental performance demonstrated by

II the MC68XX plastic package. The low operating potentials and moderate power levels of
NMOS microprocessors result in excellent moisture resistance verified by temperature-
humidity-bias testing. The integrity of die and wire bonds, as well as the matching of ex-
pansion coefficients, are examined in the temperature cycle test where 40-pin packages
were shown to perform as well as 14-pin devices.
This report, describing MC68XX reliability, is the most comprehensive to date. The
1980 reliability data bases are expanded and revised with new test information which im-
proves the accuracy of the reliability predictions. In addition, the report includes applica-
tion data useful in system design and qualification of MC68XX devices. The excellent
reliability of the MC6800 family reflects the high priority given to reliability and quality
standards by Motorola as an integral part of its corporate objectives.

Accelerated Life Testing

Accelerated operating life testing is used to simulate continuous system operation
while decreasing the time required to observe long-term effects. The test is typically con-
ducted at an ambient temperature of 125°C for 1008 hours with electrical measurements
performed at the 0, 24, 168,504, and 1008 hour points. The value of the resultant failure
rate is dependent on many variables, the most important being:
1. Temperature
2. Voltage
3. Biasing Technique
4. Failure Criteria
5. Acceleration Factor
6. Confidence Limit
Since the manipulation of these can produce a wide range of results, it is imperative that
the customer have an adequate understanding of how these variables can contribute to
the reported failure rate. This section provides a brief narrative describing the test condi-
tions and results while more details are found in the appendices.

3-4
Methods

The life test circuits were designed to simulate system operation by dynamically exer-
cising the internal circuitry of each device type. Dynamic biasing is preferred to static
biasing of LSI devices since the continual switching of internal nodes more closely
simulates the application. Appendix B, Accelerated Life Test Techniques, describes the
biasing arrangements used in life testing.
Electrical measurements were obtained with Fairchild Sentry Systems and test pro-
grams employing exhaustive functional routines under worst-case supply and clock con-
ditions. Pass/fail criteria are established for each circuit type based on data sheet limits
of AC, DC, and timing parameters. Devices which do not meet a test criterion are
segregated by failure mode, data logged and analyzed, when appropriate, to determine
specific failure mechanisms.

•
Equivalent device-hours and individual MC68XX failure rates are based on junction
temperatures measured on test samples. A significant characteristic of NMOS devices is
a decreasing power versus temperature relationship; this characteristic improves device
reliability in severe environments since the rate of junction temperature rise decreases
with increasing ambient temperature. The calculation of acceleration factors and failure
rates using junctions rather than ambient temperature is a more conservative approach
and is employed in all MOS reliability data. The Chi-Square distribution was used at the
60% confidence level to determine the failure rate values shown in this report (Tables 1
and 2, Figure C2). Appendix B illustrates in detail the steps involved in this calculation.

Results

Table 1 summarizes the life test results obtained by Motorola on devices sourced from
mask sets used in production during 1980. The system failure rate reflects the expected
field performance due to catastrophic failures while the total failure rate also includes
devices demonstrating parametric degradation which is not likely to impair system per-
formance.
The life test results presented in Table 2 include over three hundred million device-
hours and an overall 70·C system failure rate of 0.018%/1000 hours (MTBF = 5.6 x 106
hours) measured on standard product without preconditioning. Plastic and ceramic
devices demonstrated failure rates of 0.022%/1000 hours and 0.012%/1000 hours, respec-
tively. For a detailed description of failure modes observed during accelerated life
testing refer to Appendix D, Electrical Testing and Failure Characteristics.

TABLE 1
SUMMARY OF 1980 LIFE TEST DATA

70'e System 70'e Total

Device Wafer Test 70'C EquIvalent
Failure Rate Failure Rate
GroupIng Lots Devices Device-Hours
(%/1000 Hrs.) (%/1000 Hrs.)
Microprocessors 92 4,462 120 1 x 106 0027 0039
Peripheral Devices 59 2.962 1566x106 0018 0033
RAMS 5 353 179xl06 0017 0040
ROMS 23 984 597x106 0009 0014
Total 179 8,761 3543xl06 0018 0032

3-5
 TABLE 2
MC8BOO FAMILY RELIABILITY

Average
- 70' 70' Total
Failures Actual 70'C Junction System Failure
MaS Wafer Test
Device Type Device- Equivalent Temperature at Failure Rate Rate
Technology Lots Devices
Catastrophic Total Hours Device-Hours TA=70°C %/ %/
Ceramic Plastic 1000 Hrs. 1000 Hrs.
Microprocessors
MC6800 N 25 1.069 13 18 895,628 544xlQ6 83 92 0025 0034
MC6802/08 N 42 1,665 15 24 1,576,864 460xlQ6 91 116 0035 0051
MC6805 H 19 1,499 2 2 234,672 108x106 88 102 0028 0028
MC8809 H 6 229 2 3 188,359 89x106 88 107 0034 0046

Peripheral Logie
MC8821 N 19 1,113 6 13 1,067,069 59 2x 106 79 92 0012 0023

II
MC8840 N 4 159 a a 159,632 108xl06 80 87 0008 0008
MC8845 N 3 135 a a 90,720 5 a x 106 89 105 0018 0018
MC8846 N 5 294 5 6 356,688 108xl06 89 109 0057 0066
MC8847 N 3 133 2 6 110,040 54x106 83 94 0052 0120
MC8850 N 11 477 2 3 478,223 27 1 x 106 81 92 a all 0015
MC6852 N 3 117 1 7 129,350 811x106 83 91 0025 0100
MC8854 N 4 207 1 3 205,176 91 x 106 89 101 0022 0045
MC6880 N 2 76 4 4 72.984 57x106 79 81 0091 0091
MC6862 N 3 170 5 7 159,740 12 2x 106 78 84 0051 0066
MC88488 N 2 81 1 2 78,336 32 x 106 85 98 0061 0095

RAM
MCM68lO N 5 353 2 6 384,912 17 9x lQ6 83 92 0017 0040

ROMs
MCM6830/3Q8 N 10 361 2 4 287,981 21 Ox 106 81 88 0014 0025
MCM68316 N 6 218 0 a 133,728 57 x lQ6 86 96 0016 0016
MCM68332 N 4 274 1 2 156,984 10 8x 106 78 83 0019 0029
MCM68384 H 3 131 1 1 284,096 222xl06 75 78 0009 0009

3-6
Plastic Package Environmental Performance
Molded dual-in-line packages are an attractive, low-cost alternative to hermetically-
sealed systems. Plastic is lighter, less expensive, and much more resistant to physical
damage than a ceramic device. However, there are four primary concerns: contamina-
tion, moisture resistance (corrosion), wire bond integrity, and thermal performance. The
accelerated life test described in the previous section produced no significant difference
in plastic and ceramic performance, thereby indicating the absence of a plastiC con-
tamination mechanism. This section addresses the moisture resistance and wire bond
integrity of the product. Refer to Appendix A for additional descriptions of the packaging
systems and their thermal characteristics.

•
Temperature·Humidity·Bias Testing

The Temperature-Humidity-Bias (THB) test is used to evaluate the moisture resistance

of plastic devices by employing severe conditions (85°C, 85% RH, 5 V) to accelerate cor-
rosion of the metallization. The biasing circuits used in THB testing create static electric
fields between adjacent metal areas, thereby increasing the incidence of electrolytic
cells while minimizing power dissipation.
Each THB sample is sourced from a separate wafer lot and tested for a period of 1008
hours. Electrical measurements are performed at the 0, 168, 336, 504, and 1008 hour
pOints using Sentry test systems with complete parametric and functional test pro·
grams. The pass/fail criteria used for life test samples are also employed with THB
samples. A worst-case analysis is presented since all electrical failures are conSidered
instead of only those associated with the corrosion mechanisms.

TABLE 3
TEMPERATURE·HUMIDITY·BIAS (85°C/85% R.H.I + 5 V) TEST RESULTS

Cumulative Test Time (Hr.l

168 336 504 1008
Test Devices 576 338 569 561
Failures 2 1 4 3
Percent Defective 035 030 070 053
Cumulative % Defective 035 065 135 188

The data presented in Table 3 is based on testing of 576 devices in which ten failures
were observed. A Weibull plot (Figure 1) shows a comparison of the performance
measured in 1979 and 1980, respectively. This excellent performance is attributed to two
factors. First, corrosion takes place because an electrolytic cell is present which is field·
strength dependent and, therefore, has a lower reaction rate with 5·volt bias than with
higher supply levels. Secondly, the cell requires an electrolyte which is created by the in·
gression of moisture reacting with minute quantities of ionic material. The power
dissipation of these devices lncreases the temperature of the die surface, helping to
drive off moisture which prevents cell formation.

3-7
 FIGURE 1 - WEIBULL PLOT OF TEMPERATURE·HUMIDITY·BIAS TEST RESULTS
500

300
200

100 Performance
Measured In 1979
...
50

10

05
,.,.r - ...... 15/
.'
Performance
Measured In 1980

.....
01

II
005

001
168 336 504 1008 10K
Test Time In Hours

Temperature Cycle Testing

The integrity of wires and die bonds in plastic packages can be accurately evaluated
through temperature cycle testing. MIL-STD-8838, Method 1010.4, Condition C is
employed to permit easy comparison with other sources of data. Condition C dictates a
cycle from - 65·C to + 150·C with a fifteen minute dwell time. This is a particularly
severe range which induces stress on the wires and bonds due to differences in the ther-
mal coefficients of expansion between the wire, lead frame, and encapsulant. Air-to-air
cycling has been shown to be more severe than liquid-to-liquid thermal shock testing of
this mechanism. This surprising difference is probably due to the longer dwell time for
temperature cycle and the fact that the internal movement involves a relatively slow relax-
ation of the package components. The predominant failure mechanism is wire breakage
above the ball bond where the heat and stress of the bonding process reduce the
strength of the wire. End point continuity testing at 125·C is used to detect potential in-
termittents.

TABLE 4
TEMPERATURE·CYCLE TEST RESULTS

Cumulative Test Cycles

100 250 500 750 1000
T 8St DeVices 2250 2218 2193 2086 2050
Failures 2 7 8 5 8
Percent Defective 009 032 036 024 039
CumulatIVe % Defective 009 041 077 101 140

3-8
 The temperature cycle test results presented in Table 4 reflect the effort directed
toward process control and its achievement of a consistently reliable bonding system.
Over two thousand plastic devices from thirty separate assembly lots were tested to 1000
cycles resulting in thirty failures. Of these, twelve were caused by broken bond wires,
while the remainder involved non mechanical problems.

Handling Precautions

•
All MOS and many bipolar technologies require precautions against high static
voltages. It is important that conductive or antistatic materials be employed at all work
stations. Operators should use wrist straps and work surfaces should be conductive. At-
tention should be paid to the completed boards as well as the components since high-
impedance circuit nodes are readily accessible. Although most static damages cause
failures immediately, a small portion may continue to function and fail in the field.
A second type of precaution involves the CERDIP package. Since this device employs
a glass seal, a high stress on the leads can cause hermeticity failure which will eventual-
ly result in aluminum corrosion on the die. To avoid this, the leads should never be flexed
above the seating plane. All insertion tools or automated equipment should contact the
lead at its narrowest dimension allowing it to bend without affecting the wide portion
above the seating plane.

FIGURE 2 - CERDIP INSERTION PRECAUTIONS

CERDIP Package
Insertion Tool

Glass Seal

15 Mil
M,OImum Width

3-9
 Quality And Testing
A complete Reliability and Quality Assurance System is in place to monitor and con-
trol the performance of Motorola MOS products. Incoming Quality Control inspects start-
ing wafers, masks, chemicals, package piece parts, and molding compounds. Process
Engineering and In-Process Quality Control perform step-by·step inspections in the
wafer area to check the oxidation, diffusion, photoresist, and metallization operations.
Final visual, class probe and capacitance voltage plot screens complete the wafer area
inspections. In the assembly area, In-Process Quality Control performs monitor (random
sample) and gate (all lots) inspections at each of the major process steps. The Outgoing
Quality Control group continues this philosophy in the final test area by gating electrical,
mechanical, visual, and clerical requirements. Refer to Appendix A for descriptions of the
process flow for ceramic and plastic MC68XX devices.
The Reliability Engineering group performs qualifications of new designs and process

II changes prior to introduction. Many short term tests are performed on an ongoing basis
to monitor the trends of all process lines; these provide rapid feedback to correct
negative perturbations before they can affect device performance. Supporting the efforts
of these groups are the Standards Laboratory, the Metrology Laboratory, the Chemical
Laboratory, and a sophisticated Product Analysis Laboratory.

FIGURE 3 - RELIABILITY AND QUALITY ASSURANCE ORGANIZATION

I Rellabliity And Quality Assurance

I
1
1 I I I I
Process
Reliability
Engineering
I Development
Reliability I Quality
Assurance
I Quality
Control
I Analytical
Laboratones
l
r- LogiC and Special - New Processes - Burn-In and - Incoming Quality Chemical Laboratory
Functions EnVironmental Control
Laboratory
I- Memory New Technologies ~ Lot Processing - Wafer Fabncatlon Product AnalYSIS
In-Process Laboratory
Quality Control
L- Microprocessors New EqUipment r-- Outgoing Ouality Assembly In-Process
Control Quality Control

I-- Quality Control Metrology

Engineering Laboratory

S peelfle at I0 n S S...,a nd af ds
Department Laboratory

3-10
Conclusion
The reliability data examined in this report represents the cumulative results of recent-
ly completed test programs. The specific tests were chosen to be those most represen-
tative of MC68XX field performance. Failure rate estimates were based on the outcome
of tests and data analysis which are widely accepted and conservative. The level of per-
formance predicted by this data is among the best available in the industry and far ex-
ceeds the requirements of most applications. Comparison to previous reports verifies a
history of continuous improvement which has made Motorola MOS LSI the optimum
choice for system reliability.
Copies of this and other reliability reports may be obtained from your local Motorola
representative. For additional information, contact Reliability (512)928-6640 or Marketing
(512)928-6800 organizations or write to:

Reliability Engineering
Motorola Inc.
3501 Ed Bluestein Blvd.
Austin, Texas 78721

3-11
 APPENDIX A
A COMPARISON OF PACKAGING SYSTEMS

The MC6800 family of microcomputers and NMOS peripheral device types are produc-
ed in plastic, CERDIP and sidebraze packages. The ceramic packages are hermetically
sealed to protect the integrated circuit from environmental factors and permit operation
over extreme temperature ranges. Although plastic devices are nonhermetic, modern
epoxies exhibit extremely high moisture resistance and long lifetimes may therefore be
expected from these integrated circuits in typical environments. Extensive reliability
testing has been performed to evaluate the three package types as specified in Report
7639-2, Package Qualification Program Plan.

II Plastic

Encapsulated integrated circuits incorporate the simplest processing and package

construction of the various systems available. The die is attached to a lead frame, wire
bonded and encapsulated by a filled resin. The lead frame may be copper, or alloy 42, and
the die attach may be epoxy, gold silicon eutectic, or a variety of eutectic forming metal
foils. Wire bonding may be thermocompression or thermosonic, but the wire is always
gold. This system has evolved from early industry experiments with aluminum ultrasonic
wire bonding which experienced high rates of opens and intermittents. The encapsulant
is the most critical component of the system since it controls contamination, moisture
resistance, and stress effects. Epoxy novolacs have become the standard molding com-
pound since they combine excellent characteristics in all these areas. Silicones are very
susceptible to moisture and contamination ingresAion, and die coats have induced
disasterous stresses on the wire bonds.
The plastic package is, by far, the most resistant to physical damage since the die is
completely encapsulated and cavity hermeticity is not a concern. Since the package is
light in weight and the plastic is less brittle than ceramic, chipping and cosmetic damage
are not problems. The lead frame and plating are equivalent to CERDIP, and modern
epoxies pose no danger from contamination. Only two areas have yielded poorer perfor-
mance: moisture resistance and thermal resistance. Moisture resistance is a function of
encapsulant porosity and adhesion to the lead frame. Vendors of molding compounds
are constantly improving these parameters; but, even in their present state, the low
voltage and moderate power dissipation of microprocessor devices provide excellent
performance which is rarely distinguishable from hermetic performance (refer to
Figure 1). Thermal resistance has been improved dramatically through the introduction
of copper lead frames and heat spreaders with values even lower than those of currently
available ceramic packages.

3-12
 FIGURE A1 - PLASTIC PROCESS FLOW

Wafer Electrical Saw Break In-Process Ole Bond Wire Bono

Inv8r;\tory Probe Quality Control
(IPQC) O,e
High-Power Gate

IPOC Mold IPQC

Monitor Wire Puli

Deflash lead Visual !POC Trlm/Forml IPOC

Finish Inspection Solderability Carrier Load Visual Gate
And
Visual Gate

Finished Goods Outgoing Outgoing Quality Mark Electrical

Warehouse Quality Control Control Test
Visual! Sample
Mechanical Gate Electrical Test

Hermetic

Two package styles are commonly used for dual-in-line hermetic applications. The
CERDIP package is composed of two layers of black alumina with the seal formed be-
tween these by a glass frit layer. The kovar or alloy 42 lead frame is embedded in the
glass and has aluminum deposited on the internal lead tips to provide a compatible sur-
face for ultrasonic aluminum wire bonding. The lead frame is formed into the dual-in-line
configuration prior to assembly to prevent unnecessary stress of the glass seal. Both the
lid and the base alumina have recesses to provide a cavity and the base recess is usually
coated with a gold or paladium silver frit for die bonding. Glass die bonding is occa-
sionally used for small die but LSI devices require a eutectic bond to minimize the ther-
mal expansion mismatch. Tin plating is applied to the leads subsequent to the sealing
operation.

3-13
 The solder seal package is composed of three layers of alumina whihh are screened
with a refractory metal such as tungsten or moly manganese and fired together to form
the package body with a cavity for the die. The refractory metal is then plated and kovar
or alloy 42 lead frames are brazed to the bottom, sides or top of the package, depending
on the vendor. The advantage of the sidebraze version is accurate lead alignment without
the need for forming. The final piece part operation is plating which may be gold or tin
with a selective gold plate in the cavity. Versions are also available, without a metal seal
ring, for a frit seal ceramic lid similar to the CERDIP package. Although epoxy die bond-
ing is feasible in this package due to the lower sealing temperature, most manufacturers
employ a eutectic bond. Both aluminum ultrasonic wire bonding and gold thermocom-
pression bonding are used.

II FIGURE A2 - HERMETIC PROCESS FLOW

IPOC
Wire Pull
Monitor

Wafer Electrlcai Saw Break

Inventory Probe

lead Finish Fine Leak Gross Leak Seal IPOC Precap IPOC Ole
ITm-P!ated Test Sample Precap Inspection Bond/Wire
Packages Only I Gate (As Applicable) Bond Gate

• Mil-Std 8838 Method 1010 4

Condition C (- 65° to 150°CI

Visual IPOC Trim/Carner Electrical Mark Outgoing Outgoing Finished Goods

Inspection Solderability Load Test Quality Control Quality Control Warehouse
And Visual Gate Sample Sample
Electrical Test Visual! Mechanical
Gate

3-14
 TABLE A1
A COMPARISON OF PACKAGING
MATERIALS AND PROPERTIES

Sidebraze CERDIP Plastic

Package Body Alumina Alumina Epoxy Novolac
External Leads Brazed Kovar Formed Alloy 42 Formed Alloy 42/ Copper
I nternal Leads Gold-Plated Tungsten Aluminum-Coated Alloy 42 Gold-Plated AllOY 42/
Sliver-Plated Copper
External Lead Plating Tin Tin Tin/Solder
Seal Solder Glass NA
Ole Bond Eutectic Eutectic Eutectic! Epoxy
Wire Bond Ultrasonic Ultrasonic Thermo- Compression
Wire Aluminum-Silicon Aluminum-Silicon Gold

TYPical Thermal
ReSistance 16JAi

•
Leads
24 52 52 120/80
2B 50 51 112174
40 40 50 95/42

Marking Suffix L S P

Some tradeoffs exist in the performance characteristics of the two hermetic packages
as they are offered by Motorola. Both are ceramic, hermetic, employ a eutectic die bond,
use ultrasonic aluminum wire bonding, and have tin plating. The thermal resistance of
the packages is very similar, with the sidebraze having a slight advantage. Both
packages perform well on the standard thermal and mechanical environmental tests, but
each is susceptible to handling damage. Loose shipping rail packaging or high velocity
impacts during testing can chip the sidebraze package and sever the interlayer metalliza·
tion. This type of handling will not affect the 10 mil thick lead frame of the CERDIP
package, but hermeticity failures can occur. The CERDIP package is slightly thicker and
heavier, but no conductive surfaces are exposed so the shorting potential in dense
packaging is reduced. Another difference is the fact that CERDIP devices employ an all
aluminum wire bonding system and are immune to the intermetallic problems of
multi metal systems. Extensive testing of 24·, 28-, and 40-lead CERDIP and sidebraze
devices has indicated no significant difference in reliability.

3-15
 APPENDIX B
ACCELERATED LIFE TEST TECHNIQUES

The test results reported in previous sections were obtained through the use of pro-
cedures employed throughout the semiconductor industry. This section details those
methods as applied by Motorola to perform accelerated tests and the subsequent
analysis.

TEST TECHNIQUES

Accelerated Life Testing is used to simulate continuous system operation while

decreasing the time required to observe long-term effects. This test method is designed

II to detect latent defects in the integrated circuit and some types of packaging defects
which occur in accordance with the relatively well-defined models described in this sec-
tion. The operating parameters of temperature, time, and voltage are controlled during
the test, while moisture and other atmospheric constituents are assumed to be insignifi-
cant.
The accelerated life test is widely accepted as a qualification test method for in-
tegrated circuits and is consistent with Method 1005.3, Steady State Life, Conditions D
and F, contained in MIL-STD-883B. Each device type uses a distinct driver circuit capable
of dynamically exercising internal nodes of the integrated circuit. Most of the waveforms
are derivatives of a common clock signal and are therefore easily implemented with a
minimum of circuitry. The VDD supply levels are regulated at the nominal rated value of
the devices. It is also important that supply lines be adequately decoupled and be of suf-
ficient cross-sectional area to prevent excessive voltage drop. Signal-carrying metal
traces on oven trays are limited to the shortest possible physical distances to prevent
undesired reflections and cross talk between lines. In order to insure that test devices
are properly exercised during the test, mid-range clock frequencies are chosen for each
device type based on data sheet limits. Increasing clock speed does not have a signifi-
cant effect on the power dissipation of MC68XX devices with unloaded outputs and is
not, therefore, an important factor in determining reliability. These circuits permit high
density testing and avoid the potential for accidental overstress of the parallel test
devices. Some pins are electrically isolated from device to device, since parallel connec-
tions may prevent device functions or lead to overstress; this is accomplished by remov-
ing designated socket pins from the life-test oven board.
The ambient test temperature is typically 125°C, although any value above the max-
imum system temperature will provide acceleration. Junction temperatures become a
limiting factor near 180°C for laminated ceramic devices and 150°C for plastic devices.
At these temperatures gold-aluminum intermetallics begin to form in the ceramic
packages and plastic encapsulants start to decompose. Junction temperature for CER-
DIP devices is limited only by circuit leakages which affect all package types above
150°C. A supply current measurement during the test will reveal the maximum permissi-
ble ambient temperature. Since supply currents will decrease with temperature at an
average rate of - 0.25%/OC, extrapolations are possible if a reference point is obtained
initially. Test duration is 1008 hours, and electrical measurements are performed at 0,
168,504, and 1008 hours. More frequent measurements are performed to observe infant
mortality characteristics, but frequent handling increases the likelihood of physical or
electrical damage to the sample.

3-16
ANALYSIS OF RESULT5

Upon completion of the test, failed devices are examined to characterize failure modes
and determine whether a pattern exists which would justify a physical analysis of the
failure mechanism. Failure rates are expressed in failures-per-hour and are calculated
using the Chi-Square distribution in the equation:

Where: (1)
A. = Failure Rate
x 2 = Chi-Square Function

ex =
100 - Confidence Level
100
d.f. = Degrees of Freedom = 2r + 2
r =Numbers of Rejects
t =Device-hours
If a test has been conducted at the ambient temperature of the system, then device-
•
hours can be calculated directly and substituted into Equation 1. Since it is not practical
to observe long-term effects at system temperatures, the test is accelerated and
therefore requires a basis for equating device-hours at the test temperature to device-
hours at the temperature of operation. Acceleration factors express this ratio and are
derived from the Arrhenius relationship in Equation 2. One electron-volt is used as the ac-
tivation energy value based on Motorola's experience and data from other industry
sources.

Fa = exp [(O/K)' (T~ - ~t)] (2)

Where:
Fa =Acceleration Factor
0= Activation Energy in eV
K = Soltzman's Constant, 8.62 x 10 - 5 eV/oK
To = Operating Temperature in ° K
Tt =Test Temperature in °K

3-17
 Parameters Tt and To of Equation 2 are the average junction temperatures present
during the test and in system operation, respectively. Motorola uses junction rather than
ambient temperatures since they produce more conservative and representative ac-
celeration factors. Junction temperatures can be derived from power dissipation
measurements and Equation 3. The thermal resistance (8JA) values of MC68XX devices
are given in Appendix A and may be measured using the procedure outlined in Reliability
Report 7843, Thermal Resistance Measurement Method for Microcomponent Devices.
These values were obtained under "still-air" conditions and are, therefore, slightly
pessimistic for most systems. MIL-STD-8838 Method 1005.3 provides a derating curve for
thermal resistance based on linear air movement.

Where: (3)
TJ = Junction Temperature in °C

II TA = Ambient Temperature in °C
Po = Average Power Dissipation in Watts
8JA = Thermal Resistance. Junction-to-Ambient in °CIW

3-18
 APPENDIX C
APPLYING LIFE TEST DATA

The reliability test results reported in previous sections, although obtained under
severe conditions, can be extrapolated to predict failure rates expected in system ap-
plications. The conservative methods employed by Motorola in determining acceleration
factors and in electrical testing permit the calculation of system level failure rates with a
high level of confidence. This section details the techniques used in applying the
reported data to actual system conditions.

FIGURE C1

•
TIME DEPENDENT RELIABILITY

III

Failure Rate

"

OPERATING LIFETIME

The time dependent reliability of semiconductor devices is illustrated by the "bathtub

curve" of Figure C1. Three regions are presented: I, a region of relatively high declining
failure rate known as "infant mortality"; II, a region of constant, random failures; and
III, a region of increasing failure rate due to wear-out mechanisms. Careful attention to
manufacturing details and process screens help to eliminate the effects observed in
Region I. It is significant to note that wear-out phenomena have not been observed during
life testing of MC68XX devices. Failure rates are expressed in percent failures-per-
thousand hours. Mean-Time-Between-Failures (MTBF) is another frequently used
parameter which is the reciprocal of the failure rate (failures-per-hour) and is expressed
in units of time.

MTBF=+

The failure rate characteristics of LSI Circuits may be observed in a short period of
time using the accelerating effects of temperature. The Arrhenius equation described in
Appendix B establishes an exponential relationship between time and temperature
which permits a quantitative extrapolation of the data.

3-19
 FAILURE RATE DETERMINATION

Table 2 provides 70·C failure rate values for twenty MC68XX device types. Explained in
that section was the distinction between the Total Failure Rate, which includes all life
test failures, and the System Failure Rate, which includes only catastrophic failures. Ex-
trapolating this data to operating temperatures other than 70·C can be accomplished
using the curves in Figure C2. For a specific device type, plot the 70·C failure rate value
and corresponding junction temperature on the graph and draw a line through this point
parallel to the 1 eV curves shown. This line represents the failure rate values at cor-
responding junction temperatures for that device type. Measure the device power
dissipation at the maximum operating temperature and compute the corresponding junc-
tion temperature value using Equation 3. The failure rate for that temperature can then be
determined directly from the graph and will represent the operating condition of the

•
device in the system .

FIGURE C2
FAILURE RATE VERSUS JUNCTION TEMPERATURE
l000/0K
23 25 27 29 31 33 35

10

'\.I'\.
r\.\.

'\.

01 \.~
Total
'\.

00 1
System<ll
.\.

'\.

0001 .\.

'\.

00001
\ l'\..

"\ I\.
150 125 100 85 70 50 25
Junction Temperature (OC)

3·20
 APPENDIX D
ELECTRICAL TESTING AND FAILURE
CHARACTERISTICS

The electrical measurements performed on life test and temperature-humidity-bias

(THB) samples were obtained using Fairchild Sentry Test Systems and programs employ-
ing exhaustive functional routines under worst-case supply and clock conditions.
Devices which do not meet a test criterion, including those failing for parametric
reasons, are first segregated into "bin outs" defined by the test program. A data log is
obtained from which each failing device is then assigned to one of six failure mode
categories. An analysis to determine specific failure mechanisms is performed when the
level or pattern of failure indicates that it is appropriate. THB rejects are routinely decap-
sulated and inspected for corrosion of the metallization.
The electrical test programs are typically constructed in the following manner:
TABLE D1
TYPICAL MC68XX ELECTRICAL TEST SEQUENCE
"Opens" test
"Shorts" t8St
3 Functionality under nominal supply and clock conditions
4 Input leakage
5 Three-State leakage
6 Functionality to data sheet limits during worst-case conditions
of VOD level and clock frequency combinations
7 Output buffer current dnve capability
8 Power diSSipation test

Failure modes categorized according to these tests do not always indicate a specific
problem and individual test programs deviate from the sequence shown above as re-
quired for complete testing of the specific device type. Microprocessors and other LSI
logic circuits do not readily lend themselves to the identification of failure modes since
their complexity creates an astronomical number of possible combinations, some of
which are very subtle. Attempts to categorize these modes by the test sequence in·
variably result in groupings which are not mutually exclusive or related to physical
mechanisms.
The most valuable method of classification is a dichotomy based on system func-
tionality. Semiconductor devices failing a rigorous electrical test frequently function
adequately under nominal operating conditions such that they would not cause a system
failure. These units have parameters which exceed data sheet limits, but which do not
impact system reliability to the extent of catastrophic failures. Nearly half of the failures
observed in life testing were non-catastrophic in nature. The ultimate classification
criterion must be predicated upon the maintenance of system operation and MC68XX life
test failure modes are, therefore, categorized as being either catastrophic or non-
catastrophic. Opens, shorts, or functional (logic state) failure modes are considered to
be catastrophic, and are used in the determination of the "System Failure Rate." Input
leakage, three-state leakage, and parametric failure modes are non-catastrophic and are
combined with the catastrophic failures in the "Total Failure Rate."

3-21
 TABLE 02
FREQUENCY OF FAILURE MODES ON MC68XX DEPLETION· LOAD DEVICES

Three·
Input
Faolure Modes Opens Shons Functional State Parametric
Leakage
Leakage
Percentage of Occurrances 72% 60% 379% 227% 48% 214%

TABLE 03
DEFINITION OF FAILURE MODES

I. CATASTROPHIC MODES
A. Opens - No electrical connection between an external terminal and corresponding die circUitry (possibly Intermittent)
MOS Inputs are normally high Impedance ports and opens are detected by forward· biasing the substrate diode

II B. Shorts - An unintended resistive path of relatively low value between one terminal and any other terminal
C. Functional - Failure of one or more output terminals to respond with a correct logical state under nommal supply, clock,
and VIH/VIL levels a violation of the Internal Boolean relationships defined by the CIrCUit design
II. NON·CATASTROPHIC MODES
A. Input Leakage - A current of either polarity which exceeds data sheet limits for Input terminals Large values of leakage
may be classified as shorts
B. Three-State Leakage - A current of either polarity which exceeds data sheet lImIts for 1/0 termInals when under three-
stated condItions This parameter IS also tlmmg dependent and when catastrophic IS classlfled as a functional failure mode
C Parametric ~ A broad claSSification of non-catastrophIc faIlure modes which exclude leakages but Include
1 FaIlure to respond at one or more output terminals with a correct logical state under worst-case supply clock, and
VIH/VIL conditions, usually the result of exceSSive propagation delays, Improper VOH/VOL levels, nOise, or a
dynamiC logIC state which should be static, etc Must be 100% functional under nomInal condItions and may be
assocIated with leakage currents not prevIously detected
2 ExceSSive power dIssipatIon not caused by leakage currents DeVIce I~ 100% functIOnal
3 Incorrect output analog voltage or current level not resultIng In a functIonal failure

The distribution of failure modes and meChanisms observed during life testing appear
to be the result of random manufacturing anomalies and do not, therefore, indicate
trends correlatable to specific process or design deficiencies. These results are consis·
tent with careful attention to process controls and reflect Motorola's high priority on
quality and reliability.

3-22
 POWER CONSIDERATIONS

The previous paragraphs have shown that circuit performance and long-
term circuit reliability are affected by die temperature. Performance and
reliability are both improved by keeping junction temperatures low. Elec-
trical power dissipation by the integrated circuit causes an increase in the
die temperature relative to some reference point, usually the ambient
temperature. This increase in temperature depends on the amount of
power dissipated in the circuit and on the thermal resistance between the
heat source and the reference pOint. The average chip-junction
temperature, TJ, in degrees C can be obtained from:

•
T J =TA+ (PD e 6JA) (1 )
Where:
TA=Ambient Temperature, °c
6JA= Package Thermal Resistance, Junctlon-to-Ambient, °C/W
PD = PINT + PPORT
PINT= ICC x VCe. Watts - Chip Internal Power
PPORT= Port Power Dissipation, Watts - User Determined
For most applications PPORT<C PINT and can be neglected. PPORT may become
significant if the device is configured to drive Darlington bases or sink LED loads.
An approximate relationship between PD and T J (if PPORT is neglected) is:
PD= K+ (T J + 273°C) (2)
Where K is a constant pertaining to the particular part.
Solving equations 1 and 2 for K gives:
K=PD e (TA+273°C)+6JAe PD 2 (3)

The constant K can be determined from equation (3) by measuring Po at

the T A given in the data sheet (worst case), or by measuring Po (at
equilibrium) for a known T A. Remember that power dissipation specifica-
tions on Motorola's microprocessor, single-chip microcomputer, and
peripheral data sheets are specified at steady state current, maximum
power supply voltage, and minimum operating temperature. The value for
6JA for a particular package can be found in the data sheet. Using the
calculated value for K, the values of Po and TJ can be obtained by solving
equations (1) and (2) iteratively for any value of TA.

Example:
In this example the power dissipation (PO) and junction temperature (TJ)
for the MC6821 P are calculated for an ambient temperature (T A) of 70°C.

The MC6821 P data sheet specifies Po = 0.55 W @ TA = DoC. ()JA for a

plastic 40-lead package is 100° C/W.

3-23
 Solving for K:
K= POo(TA + 273°C) + OJAoP 0 2 (3)
K= 180.4

TJ is calculated from equation (1)

TJ = TA + (POoOJA) (1)
TJ = O°C + (100°C/W)(0.55 W) = 55°C

Equation 1 must be used to calculate TJ. This equation, however, assumes

that Po at the specified TA is known. Since Po at 70°C is not known, an
iterative process must be used. Since the only known Po is at O°C, this
number is used for the 1st pass iteration. Now TJ can be calculated. Once
calculated, equation 2 can be used to calculate Po given the TJ calculated
from equation 1. If this Po is different from the value used to calculate TJ,

II then another iteration is required. For successive iterations the value of Po

obtained from the last iteration should be used for the next calculations.
When the calculated values of Po and TJ satisfy both equations 1 and 2,
the iteration is complete

First Iteration:
Equation (1) TJ = TA(POoOJA)
TJ = 70 + (0.55)(100)
TJ = 125°C

Equation (2) Po = K + (TJ + 273°C)

Po = 180.4 + (125 + 273)
Po = 0.453 W

Second Iteration:
Substituting Po back into equation (1):
TJ = 70 + (0.453)(100)
TJ = 115.3°C
Po = 180.4 + (115.3 + 273)
Po =0.456 W

Continuing in this iterative manner the values TJ = 116.3°C and

Po = 0.463 W satisfy both equations.

1/0 PORT POWER - Microcomputing units (MCUs) contain another source

of power dissipation - the 1/0 ports (PPORT). Fortunately, PPORT
becomes a significant value only if the port pin is configured to sink LED
load currents or drive Darlington pair bases. If PPORT cannot be neglected,
the following equation should be used to obtain a value for PPORT:

3·24
 LED Drive Darlington Drive
PPORT = E(VOU e ( IIIL I) + E(VCC - VOLHlloH I) (4)
1 1
to to
n n
where n = # of port pins

Once a number is obtained for PPORT, it may be added directly to PD to ge

a total device power dissipation value. This total value should be used in
place of PD in equations (1) and (2).

INSTANTANEOUS POWER - The junction temperature rise above ambient

reaches equilibrium in a few minutes due to power dissipation. This ther-

•
mal response should be considered when measuring power and must be
considered when measuring power as part of a high-speed test.

The maximum power demand by any device occurs during turn-on when
=
TJ TA. The following example should be followed when calculating worst-
case power supply values.

Example:
Continuing to use the MC6821 P example to determine PD @ TA =TJ =O°C,
Equation (2) =
PD K + (TJ + 273°C)
PD = 180.4 + (0 + 273)
PD = 0.66 W
Thus, the maximum instantaneous power supply demand is 0.66 W.

SUMMARY - The calculated value of TJ should not exceed the data sheet
value of TJ (maximum) for a particular IC package. If TJ (calculated) is in ex-
cess of TJ (maximum), something must be done to reduce the junction
temperature. Equation (5) shows that ()JA consists of two parts, ()JC and
()CA·
=
()JA ()JC + ()CA (5)
=
()JC thermal resistance, junction-to-case, °C/W
=
()CA thermal resistance, case-to-ambient, °C/W

Junction-to-case thermal resistance (()JC) is a function of die construction

and therefore cannot be changed. However, ()CA may be varied. Lowering
()CA can be accomplished by increasing the surface area of the package
with the addition of a heat sink, or by blowing air across the package to pro-
mote improved heat dissipation. Alternatively, ()CA may be lowered by
selecting a different package.

3-25
 THE "BETTER" PROGRAM

Motorola standard commerical integrated circuits are manufactured under

stringent in-process controls and quality inspections combined with the in-
dustry's finest outgoing quality inspections. The "BETTER" program offers
three levels of extra processing, each tailored to meet different user needs
at nominal costs.
The program is designed to:
• Eliminate Incoming Electrical Inspection
• Eliminate Need for Independent Test Labs and Associated Extra Time
and Costs
• Reduce Field Failures

•
• Reduce Service Calls
• Reduce Equipment Downtime
• Reduce Board and System Rework
• Reduce Infant Mortality
• Save Time and Money
• Increase End-Customer Satisfaction

BETTER PROCESSING - STANDARD PRODUCT PLUS:

Level I (Suffix S)
• 100% temperature cycling per MIL-STD-883A. Method 1010, ten cycles
from - 25°C to + 150°C.
• 100% high temperature functional test at + 100°C.
Level II (Suffix D)
• 100% burn-in to MIL-STD-883A test conditions equivalent to 160 hours
at + 125°C.
• 100% post burn-in DC parametric test at 25°C.
Level III (Suffix OS)
• Combination of Levels I and II above.

TABLE 4-5. "BETTER" AQL GUARANTEES

AQL
Test Condition
Levell Levell! Level III
High Temperature Functional TA=TMax 0.15 0.15' 0.10
DC Parametric TA=25°C 0.28 0.28 0.28
AC Parametric TA=25°C 0.65 0.65 0.65
External Visual and Mechanical Major 0.11 0.11 0.11
Minor 2.50 2.50 2.50
Hermeticity Gross 0.46 0.46 0.46
(Not applicable to plastic packages)
TMax = Maximum Operating Temperature of Device Under Test
"25°C
NOTES:
1. Major Defects - Affects Form, Fit, or Function
Minor Defects - Cosmetic
2. General Inspection Level"

3·26
PART MARKING - The part is marked with a suffix letter(s) as shown to in-
dicate the level of testing that the part received.

MC68XXX CP s
I T T
I I I
Part Standard "BETTER"
Identification Package Processing
Suffix =
Level I Suffix S
=
Level II Suffix D
=
Level III Suffix DS

ORDERING INFORMATION - The Standard Motorola part number with the

corresponding "BETTER" suffix can be ordered from your local authorized
Motorola distributor or Motorola sales offices. "BETTER" pricing will 'be
quoted as an adder to standard commercial product price.

3-27
II

3-28
 Data Sheets II

4-1
•

4·2
 DATA SHEETS

Data sheets at Motorola are grouped into one of three categories depen-
ding on the amount of information presented. These categories are:

Product Preview - This is the first official information released about a

potential device. It contains very basic information about a product and
usually precedes sample devices by approximately six months. This type of
data sheet is distinguished by the words "Product Preview" appearing in
the header of the first page as shown in Figure 4-1.

Advanced Information - This information is released with sample devices.

It contains an extensive discussion of device operation and provides com-
plete parametric information such as Maximum Ratings, Thermal
Characteristics, Electrical Characteristics, Bus Timing, and 1/0 Port Timing
as applicable. Timing diagrams are included to support the tabular
material. All of the parametric information given is the result of early
testing of initial product from the manufacturing process. Values given are
subject to change without notice. This type of data sheet is distinguished
by the words "Advanced Information" appearing in the header of the first
page as shown in Figure 4-1.

Final Data Sheet - This data sheet evolves from the Advanced Information
II
data sheet. It is a result of test information collected from a fully-
implemented manufacturing process. The parametric information has been
analyzed and approved. Motorola considers this is a fully characterized
device. This type of data sheet is distinguished by the absence of any designa-
tion appearing in the header of the first page as shown in Figure 4-1.

DATA SHEET ORGANIZATION

The data sheets that follow are arranged in ascending numerical order
disregarding the prefix letters and any speed designation letters.

When device numbers are essentially identical as in the MC6805 and

MC6809 families, the alphabetical letters used to distinguish the family
members are arranged in ascending alphabetical order. When one data
sheet covers closely related devices such as the MC6801, MC6803, and
MC6803NR, it is sorted by the lowest part number - in this case, MC6801.

MECHANICAL DATA

The package availability for each device is indicated on the front page of
the individual data sheet. Mechanical data for the different package types
used is located in a separate chapter of the manual. The data is arranged
by package size (pin count) and then package type (plastic, ceramic, etc.).

4-3
 Figure 4·1. DATA SHEET TYPE DESIGNATIONS

® MOTOROLA

SEMICONDUCTORS
3501 ED BLUESTEIN BLVD., AUSTIN, TEXAS 78721

I Product Previe-vv Ir
[;=__8-_B_IT_M_IC_R_~OMPUTER UNIT ~

• ® MOTOROI.A

SEMICONDUCTORS
3501 ED BLUESTEIN BLVD., AUSTIN, TEXAS 78721

c=='----------l-=:J
I Advance In:forInation II
I

® MOTOROLA

SEMICONDUCTORS
3501 ED BLUESTEIN BLVD., AUSTIN, TEXAS 78721

MC6847/MC6847Y VIDEO DISPLAY GENERATOR (VDG)

4·4
® MOTOROLA MC1372

COLOR TV
VIDEO
MODULATOR CIRCUIT
COLOR TV VIDEO MODULATOR
SILICON MONOLITHIC
· .. an integrated circuit used to generate an R F TV signal from
INTEGRATED CIRCUIT
baseband color-difference and luminance signals.
The MC1372 contains a chroma subcarrier oscillator, a lead and
lag network, a quasi-quadrature suppressed carrier DSB chroma
modulator, an R F oscillator and modulator, and an LSTTL com-
patib
e clock driver with adjustable duty cycle.

-
The MC1372 is a companion part to the MC6847 Video Display
Generator, providing and accepting the correct dc interconnection ,
levels. This device may also be used as a general-purpose modulator 14
P SUFFIX
with a variety of video signal generating devices such as video games, PLASTIC PACKAGE
test equipment, video tape recorders, etc. CASE 646

• Single 5.0 Vdc Supply Operation for NMOS

and TTL Compatibility

•
Pin Connections
• Minimal External Components
• Compatible with MC6847 Video Display Generator Clock
Output
• Sound Carrier Addition Capability OscIllator
Input
• Modulates Channel 3 or 4 Carrier with Encoded Video Signal
Duty Cycle
• Low Power Dissipation Ad)

• Linear Chroma Modulators for High Versatility

Color B Chromlnance
• Composite Video Signal Generation Capability Input Input
• Ground-Referenced Video Prevents Overmodulation Color Ref Luminance
Input Input
Color A Chroma
Input Modulator
Output

FIGURE 1 - BLOCK OIAGRAM

RF
Color B Lummance Modulator
Vee Input Input Output
11

Oscillator 2 Chrominance
Input Input
Chrominance
Oscillator
and .----, .----ii----+-o Modulator
Clock Output
Driver

Clock
OutPut

4
Ground Duty Cycle Color A Color
AF Tank
Adjust I nput Reference
Input

4-5
 MC1372

MAXIMUM RATINGS (TA = 25°C unless otherwISe noted)

Ratmg Value Unit

Supply Voltage 8.0 Vdc
Operating Ambient Temperature Range o to +70 °c
Storage Temperature Range -65 to +150 °c
Junction Temperature 150 °c
Power DISSipation, Package 125 Watts
Derate above 2SoC 13 mW/oC

RECOMMENDED OPERATING CONDITIONS

Supply Voltage 5.0 Vdc
Luma Input Voltage - Sync TIp 10 Vdc
Peak White 035
Color Reference Voltage 1.5 Vdc
Color A, B Input Voltage Range 1.0 to 2 0 Vdc

ELECTRICAL CHARACTERISTICS (VCC = +5 Vdc, TA = 25°C, Test CirCUit 1 unless otherwISe noted)

Characteristic
Operating Supply Voltage
Supply Current

CHROMA OSCILLATOR/CLOCK DRIVER (Measured at Pin 1 unless otherwise noted)

•
Output Voltage (VOL) - - 0.4 Vdc
(VOH) 24 - -
Rise Time (Vl 04 to 2 4 Vdc) - - 50 ns
Fall Time (Vl - 2 4 to 0 4 Vdcl - - 50 ns
Duty Cycle Adjustment Range (V3 :: 5 0 Vdc) 70 - 30 %
(Measured at V1 1 4 V)
::0

Inherent Duty Cycle (No connection to Pin 3) - 50 - %

CHROMA MODULATOR (V5 = V6 = V7 = 1 5 Vdc unless otherwISe noted)
Input Common Mode Voltage Range (Pins 5, 6,7) 08 - 23 Vdc
Oscillator Feedthrough (Measured at Pin 8) - 15 31 mV(p-p)
Modulation Angle [e8(V7 =2 0 Vdc) - e8(V5 =2 0 Vdcll 85 100 115 degrees
ConversIOn Gain [V8/(V7 - V6), V8/(V5 - V611 - 0.6 - V (p-p)!Vdc
Input Current (Pins 5, 6, 7) - - -20 pA
Input ReSistance (Pins 5, 6,7) 100 - - kn
Input Capacitance (Pins 5, 6, 7) - - 50 pF
Chroma MOdulator Linearity - 40 - %
(V5 = 10 to 20 V, V7 = 1 0 to 2 0 VI
RF MODULATOR
LUma Input DynamiC Range (Pin 9, Test CircUit 2) 0 - 1.5 Volts
RF Output Voltage (f - 67 25 MHz, V9 -10 V) - 15 - mVrms
Luma Conversion Gain
("V12/"V9, V9 = 01 to 1 0 Vdc) Test CirCUit 2 - 0.8 - V!V
Chroma Conversion Gain V!V
("V12/"Vl0, Vl0 = 15 Vp-p, V9 = 10 Vdc) Test CirCUit 2 - 0.95 -
Chroma Llneartty (Pin 12, Vl0 '" 1.5 Vp-p) Test CirCUit 2 - 10 - %
Luma Linearity (Pin 12, V9 = 0 to 1 5 Vdc) Test Circuit 2 - 20 - %
Input Current (Pin g) - - -20 pA
Input ReSistance (Pin 10) - 800 - n
Input ReSistance (Pin 9) 100 - - kn
Input Capacitance (Pins 9, 10) - - 50 pF
Residual 920 kHz (Measured at Pin 12) See Note 1 - 50 - dB
Output Current (Pm 12, V9 = 0 V) Test CirCUit 2 - 1.0 - mA
TEMPERATURE CHARACTERISTICS (V = 5 Vdc, T
Chroma Oscillator DeViation (fo = 3.579545 MHz)
RF Oscillator DeViation (fo = 67.25 MHz)
Clock Drive Duty Cycle Stability

NOTE 1 V9 = 1.0 Vdc, Vc = 300 mV(p-p) @ 3.58 MHz,

Vs = 250 mV(p-p) @4.5 MHz, Source Impedance = 75 n.

4-6
MC1372

FIGURE 2 - TEST CIRCUIT 1

+5 V

10"F~ 240 75

.
o
N 0.1 "H
V12
RF Output
56 pF

3579545 MHz 11 13
~~~2~~--~--~
9-35
pF
5.6 k

•
Va
Clock
Output
O~t------,~--~o-;i-r __-r__-r__-r__-r__-r~~~I~~~~~-,~o

FIGURE 3 - TEST CIRCUIT 2

+5 V
+7 V

360 2 k
1N4001 V12
Video Output

14 12
~..--<o-o..f-'----'~-------'-------~ S Chroma Modulator
Output
9-35
pF
56k MC1372

Clock Va 10
outPuto-~------------~~-L~__~__~__~__~__~ E-<> V10
01 "F

V5 V6 V7 V9

4-7
 II
FIGURE 4 - SCHEMATIC DIAGRAM
3:
Duty CYcle
Adjust
Oscillator
Input
Clock
Driver
Luma
Input
Chrommance
Input
RF Modulator
Output
RF
Tank
n....
3 2 - 10 12 - Co\)
11 13 14
VccO-~4-~------~----------~~---------}---.--------.--+--.---~+------.~~---.~------~~~--~~--~t---,
~
Rl R3 R5 R13 R14
R19
25 k 2.5 k 4.7 k 600 16k

tt .--
~4
R12

n
20 k
RS
R4 R6 ~5
R9

R2
o.. k
01
11k~
R1
02

RIO
.
-"

Ul R26 ~ R21
25k 01 3.6 k ?
a:: 4
o Ground
~I
;t

~
.--+-----,,'C3 R49
.02 150
RSO M
R28 R31
SChroma

C4
" ~ fR30
MOdulator
Output

030
C2
M

C5
M
o~ R31
032

0311---,
R38
1 k
R39
1 k
033~_
O~
R42

,.
~~-)
Q~
~I
R43

t
I R44

I3 4
. •

041
t'"
~ R48
34.

orr 034 036

R36 R45 R46

R33 R34 R35 R41
IR52

6_ 1u
Color B Color Reference Color A
Input Input Input
MC1372

OPERATIONAL DESCRIPTION Pin 11 - VCC

Positive supply voltage
Pin 1 - Clock Output
Provides a rectangular pulse output waveform with Pin 12 - R F Modulator Output
frequency equal to the chrominance subcarrier oscillator. Common collector of output modulator stage. Output
This output is capable of driving one LS-TTL load. impedance and stage gain may be selected by choice of
resistor connected between this pin and de supply.
Pin 2 - Oscillator Input
Color subcarrier oscillator feedback input. Signal from Pins 13 and 14 - RF Tank
the clock output is externally phase shifted and ac cou- A tuned circuit connected between these pins deter-
pled to this pin. mines the R F oscillator frequency. The tuned circuit must
provide a low de resistance shunt. Applying a dc offset
Pin 3 - Duty Cycle Adjust
voltage between these pins results in baseband composite
A dc voltage applied to this pin adjusts the duty cycle
video at the R F Modulator Output.
of the clock output signal. If the pin is left unconnected,
the duty cycle is approximately 5U%.
MC1372 CIRCUIT DESCRIPTION
Pin 4 - Ground
The chromlnance oscillator and clock driver conSISt of
Pin 5 - Color B Input
emitter follower Q4 and inverting amplifier Q5. Signal

•
Dc coupled Input to Chroma Modulator B. whose
presented at clock driver output Pin 1 IS coupled to
phase leads modulator A by approximately 1000 . The
oscillator input pin 2 through an external RC and crystal
modulator output amplitude and polarity correspond to
network, which prOVides 1800 phase shift at the resonant
the voltage difference between this pin and the Color
frequency. The duty cycle of the output waveform 15
Reference Voltage at Pin 6.
determined by the dc component at Pin 1 Internally
Pin 6 - Color Reference Input coupled through R 12 to the base of Q4. As pin 1 dc
The dc voltage applied to this pin establishes the voltage Increases, a smaller portion of the SinUSOidal
reference voltage to which Color A and Color B Inputs feedback signal at Pin 2 exceeds the Q4 base voltage of
are compared. two times VBE reqUired for conduction. As the dc level
is reduced, deVice Q4 and thus Q5 IS turned on for a
Pin 7 - Color A Input
longer percentage of the cycle. TranSistors QO, Ql,
Dc coupled Input to Chroma Modulator A, whose
Q2 and diode D 1 prOVide the biaSing network which
phase lags modulator B by approximately 100°. The
determines the dc operating level of the oscillator. The
modulator output amplitude and polarity correspond to
tranSistor Q2 and reSIStors R5, R6, and R 7 form a voltage
the voltage difference between thiS pin and the Color
reference of four times VBE at the collector of Q2. The
Reference Voltage at Pin 6.
dc voltage at pin 1 IS determined by the values of R4,
Pin 8 - Chroma Modulator Output R8, and R 12 and the applied duty cycle adjust voltage
Low Impedance (emitter follower) output which at pin 3. Since these reSIStors are nominally equal, the
prOVides the vectorial sum of chroma modulators A voltage at Pin 1 will always approximate the dc voltage
and B. at Pin 3.
The oscillator Signal at pin 1 is Internally coupled to
Pin 9 - Luminance Input
active filter 044. ThiS filter reduces the frequency content
Input to R F modulator. ThiS pin accepts a dc coupled
above 4 MHz. The output of the filter at the emitter of
luminance and sync signal. The amplitude of the RF signal
Q44 IS ac coupled through C3 to the Input of the lead/lag
output increases with positive voltage applied to the pin,
network. R32 and Cl prOVide approximately 50 0 of phase
and ground potential results in zero output (i.e., 100%
lag, while C2 and R29 prOVide approximately 50 0 of
modulation). A signal with positive-going sync should phase lead. These two quasi-quadrature waveforms are
be used.
used to switch chroma modulators B and A, respectively.
Pin 10 - Chrominance Input The transistors Q22 through Q25 and Q32-Q33 form
Input to the R F modulator. This pin accepts ac coupled a doubly balanced modulator. The input Signal applied
chrominance provided by the Chroma Modulator Output at pin 5 is compared to the color dc reference voltage
(pin 8). The signal is reduced by an internal resistor divider applied at pin 6 in differential amplifier Q32-033. The
before being applied to the R F modulator. The resistor source current provided by tranSIStor Q34 is partitioned
divider consists of a 300 ohm series resistor and a 500 in transistors Q32 and 033 according to the differential
ohm shunt resistor. Additional gain reduction may be input signal. The bases of transistors Q23 and Q24 are
obtained by the addition of external series resistance connected to the dc reference voltage at the emitter of
to pin 10. Q30. The bases of transistors Q22 and Q25 are connected

4·9
 MC1372

to the phase delayed oscillator signal at the emitter of associated equipment. The duty cycle may be adjusted
buffer transistor 021. The diffarential signal currents by varying the de voltage applied to pin 3. This adjust·
provided by 032 and 033 are switched in transistors ment may be made with the use of a potentiometer
022 through 025 and the resultant signal voltage is (10 kO) between supply and ground. With no connection
developed across R49. This signal has the phase and to pin 3, the duty cycle is approximately 50%.
frequency of the oscillator signal at the emitter of 021.
Chroma Modulator
The amplitude is proportional to the differential input
The chrominance oscillator is internally phase shifted
signal applied between pins 5 and 6. Transistors 026
and appl ied to chroma modulators A and B. No external
through 029 and 038-039 form chroma modulator B.
lead/lag networks are necessary. The phase relationship
This modulator develops a signal voltage which is propor·
between the modulators is approximately 100 0 , which
tional to the differential voltage appl ied between pins
was chosen to provide the best rendition of colors using
7 and 6. The phase and frequency of the output is equal
equal amplitude color·difference signals. The voltage
to the phase advanced chroma oscillator at the emitter
applied to pin 5, 6, or 7 must always be within the Input
of buffer transistor 020. Both chroma modulators A and
Common Mode Voltage Range. Since the amplitude of
B share the same output resistor, R49, so the output
chrominance output is proportional to the voltage dif·
signal presented at the emitter of 042 (pin 8) is the
ference between pins 5 and 6 or 7 and 6, it is desirable
algebraic sum of modulators A and B.
to select the Color Reference Voltage applied to pin 6 to
The RF oscillator consists of differential amplifier be midway between V5 max and V5 m in (which should

•
018 and 019 cross·coupled through emitter followers be V7 max and V7 m in)' The Chroma B Modulator will be
016 and 017. The oscillator will operate at the parallel defined as a (B·Y) modulator if a burst flag signal is
resonant frequency of the network connected between applied to the Color B Input (pin 5) at the appropriate
pins 13 and 14. The oscillator output is used to switch time. This voltage should be negative with respect to the
the doubly balanced RF modulator, 09 through 015. Color Reference Voltage, and typically has an amplitude
Transistors 07 and 08 provide level shifting and a high equal to 1/2[V6-V5m in]. Since the phase of burst is
input impedance to the luminance input pin 9. The always defined as -(B·Y). the Chroma A Modulator
bases of transistors 09 and 010 are both biased through approximates an (R·Y) modulator; however, the phase
resistors R 17 and R 18, respectively, to the same dc is offset by 100 from the nominal 90 0 , to provide the
reference voltage at 06 emitter. The base voltage at 010 1000 phase shift as discussed previously.
may only be offset in a negative direction by luminance
signal current source 08. This design insures that over· R F Modulator and Oscillator
modulation due to the luminance signal will never occur. The coil and capacitor connected between pins 13 and
The chrominance signal developed at pin 8 is externally 14 should be selected to have a parallel resonance at the
ac coupled to pin 10 where it is reduced by resistor carrier frequency of the deSIred TV channel. The values
dividers R20 and R17, and added to the luminance of 56 pF and 0.1 IlH shown in Figure 5 were chosen
signal in 09. The resultant differential composite video for a Channel 4 carrier frequency of 67.25 MHz. For
currents are switched at the appropriate R F frequency Channel 3 operation, the resonant frequency should
in 012 through a 15. The output signal current IS presented be 61.25 MHz (C = 75 pF, L = 0.1 IlH). Resistors R4 and
at pin 12. R5 are chosen to provide an adequate amplitude of
Transistors 036, 041 and resistors R44, R47 provide switching voltage, whereas R6 is used to lower the maxi-
a highly stable voltage reference for biasing current sources mum dc level of switch ing voltage below VCC, thus
043,034,035, and 011. preventing saturation within the IC.
Composite Luminance and Sync should be dc coupled
to Luminance Input, pin 9. This signal must be within
MC1372 APPLICATION INFORMATION the Luma Input Dynamic Range to insure Imearity.
Since an increase in dc voltage applied to pin 9 results
Chrominance Oscillator in an increase in R F output, the input signal should
The oscillator is used as a clock signal for driving have positive-going sync to generate an NTSC compatible
associated external circuitry, in addition to providing a signal. As long as the input signal is positive, over-
switching signal for the chroma modulators. The IC uses modulation is prevented by the integrated circuit.
an external crystal in a Colpitts configuration, as shown Chrominance information should be ac coupled to
in Figure 5. Resistor R 1 provides current limiting to Chrominance Input, pin 10. This pin is internally con-
reduce the signal swing. Capacitor C2 is adjusted for nected to a resistor divider consisting of a series 300
the exact frequency desired (3.579545 MHz). ohms and a shunt 500 ohms resistor. The input impedance
In some applications, the duty cycle of the clock signal is thus BOO ohms, and a coupling capacitor should be
at pin 1 must be modified to overcome gate delays in appropriately chosen.

4·10
MC1372

FIGURE 5 - TYPICAL APPLICATION CIRCUIT

r---------------------------------------~--------~--------~~+5Vdc

C5 "T'
. Clock In 0001~

AF
11 A3 Output
75
12

MC6847 A6
Vid-e:o 4 240
DisplaV
Generator Color B
MC1372
Color TV
-= A4
240
Video
Modulator 13
Color Ref 6
C4
56
Color A 01 f,lH

LUna and Sync 9 14

A5
8 10 6725 MHz
240
Ch 4

C3 A2
01 750

The Luminance to Chrominance ratio (L:C) may be tage at pin 12 is high enough to prevent the output
modified with the addition of an external resistor in series devices from reaching saturation (approximately 4.5 V
with pin 10 (as shown in Figure 5). The unmodified L:C with components in Figure 5). The peak current out of
(Ao) is determined by the ratio of the respective Conver· pin 12 is typically 2 mAo Hence, a load resistance of up
sion Gain for equal amplitude signals (typically, 0.883 = to 250 ohms may be safely used with a 5 V supply.
-1.6 dB). The modified L:C will be governed by the
Composite Video Signal Generation
equation Ao(l + Rext/800) for equal amplitude input
The R F modulator may be easily used as a composite
signals.
video generator by replacing the RF oscillator tank
The internal chrominance modulators are not inter· circuit with a diode as shown in Figure 3. This results in
nally connected to the RF modulator; therefore, the user the output modulator being biased so the summation of
has the option of connecting an externally generated luminance and chrominance appears unswitched at
chrominance signal to the RF modulator. In addition, pin 12. The polarity of the output waveform is con·
the RF modulator is wideband, and a 4.5 MHz FM audio trolled by the direction of the diode. Inverted video:
signal may be added to the chrominance input at pin 10. Anode to pin 14, cathode to pin 13. Non·inverted
This may be accomplished by selecting an appropriate series video: Anode to pin 13, cathode to pin 14. Note that the
input resistor to provide the correct Luminance:Sound supply resistor must always be connected to the anode
ratio. of the diode.
The modulated R F signal is presented as a current The amplitude of signal may be increased by increasing
at R F Modulator Output, pin 12. Since this pin represents the load resistor on pin 12 and returning it to a higher
a current source, any load impedance may be selected for supply voltage. Any voltage up to the Absolute Maximum
matching purposes and gain selection, as long as the vol· Rating may be used.

4·11
 MC1372

RECOMMENDED CHROMA-LUMA SIGNALS

Applications with MC6847 Video Display Generator Pm #9 Pin #7 Pin #6 Pm #5
The MC1372 may be easily interfaced to the MC6847 Luminance
as shown In Figure 5. The dc levels generated and reqUired 'nput ColorA Color Ref. Color B
IVdc) (Vdc) (Vdc) (Vdc)
by the VDG are compatible with the MC1372, so that
Sync 10 1.5 1.5 1.5
pins 1, 5, 6, 7, and 9 may be directly coupled to the
Blanking 075 1.5 1.5 1.5
appropriate MC6847 pins. Both Integrated CirCUits as
Burst 0.75 1.5 1.5 1.25
well as any associated NMOS MPU may be driven from
Black 0.70 1.5 1.5 1.5
a common 5 Vdc supply.
Green 0.50 1.0 1.5 1.0
Yellow 0.38 1.5 1.5 1.0
Recommended Chroma-Luma Signals Blue 0.62 15 1.5 20
A chroma modulation angle of 1000 was chosen to Red 062 2.0 1.5 15
facilitate a deSIrable selection of colors with a minimum Cyan 050 10 15 15
number of Input Signal levels. The following table demon- Magenta 050 20 1.5 2.0
strates applicable Signal levels for a variety of colors. Orange 050 20 1.5 10
Buff 038 15 1.5 1.5

• OUTLINE DIMENSIONS

ROJA
P SUFFIX
PLASTIC PACKAGE
CASE 646-04
= 100 0 C/W TYPLcal

THERMAL INFORMATION
The maXimum power consumption an Integrated CirCUit can
tolerate at a given operating ambient temperature can be found
from the equation

PDITA) = TJlmax)-TA
ReJAltyp)
where PDn A) =: Power DISSipation allowable at a given operating
ambient temperature. ThiS must be greater than the sum of the NOTES
MILLIMETERS INCHES 1 LEADS WITHIN 0 13 mm
products of the supply voltages and supply currents at the worst- DIM MIN MAX MIN MAX (00051 RADIUS OF TRUE
case operating condition A 1803 1956 0710 0770 POSITION AT SEATING
8 6.10 660 a 240 0260 PLANE AT MAXIMUM
T J(max) = MaXimum Operating JunctLon Temperature as listed C 5.08 0200 MATERIAL CONDITION
10 the MaXimum Ratings Section o 038 0.53 0015 0021 2 DIMENSION "L" TO
F 102 1.78 a 040 0070 CENTER OF LEADS
TA = MaXimum DeSired OperatIng AmbLent Temperature G 2548S a 08 WHEN FORMED
H 132 241 0.052 0095 PARALLEL
R8JA(tyP) = Typical Thermal ReSistance JunctIon to Ambient J 020 038 0008 0015 3 OIMENSION "8" DOES NOT
K 292 0115 INCLUDE MOLD FLASH
L 7628SC 0300 8SC 4 OIMENSION "R" TO BE
M 0° 15 00 150 MEASURED AT THE TOP OF
N 051 0020 THE LEADS (NOT AT THE
R 826 0325 TIPS)

4-12
@ MOTOROLA MC3446A

QUAD GENERAL-PURPOSE INTERFACE

BUS (GPIB) TRANSCEIVER QUAD INTERFACE
BUS TRANSCEIVER
The MC3446A IS a quad bus transceiver Intended for usage in SILICON MONOLITHIC
Instruments and programmable calculators equipped for Interconnec· INTEGRATED CIRCUIT
tlon Into complete measurement systems. This transceiver allows the
bidirectIOnal flow of digital data and commands between the various
Instruments. The transceiver provides four open·collector drivers and
four receivers featuring hysteresIs.

-
• Tailored to Meet the IEEE Standard 488-1978 (Digital Interface
for Programmable Ipstrumentatlon) and the Proposed IEC
Standard on Instrument Interface
• Provides Electrical Compatibility with General·Purpose Interface
Bus (GPIBI
P SUFFIX

•
• MOS Compatible with High Impedance Inputs PLASTIC PACKAGE
CASE 648
• Driver Output Guaranteed Off DUring Power Up/Power Down
• Low Power - Average Power Supply Current = 12 mA
• Terminations Provided

PIN CONNECTIONS

TYPICAL MEASUREMENT SYSTEM APPLICATION

Receiver ~
Vcc
Output A
Receiver
Bus A Output 0

DTlver Bus 0
--- - Input A
Dnver
Enable
Instrument Input 0
ABC
l
I
A
(With GPIS) Dnver '" Enable 0

, J
Programmable
Calculator
(with GPIS)
I Input B

Bus B

ReceIVer ....
Driver
Input C

Bus C
Output B
Instrument Receiver
, "" Output C
B I Gnd

I (With GPIS)

----

16 Lines Total - T - = 8us Termination

4-13
 MC3446A

MAXIMUM RATINGS (T'A= un 8 .. ath.rwi. notedt

Roting Symbol Volu. Unit
Po_, Supply Voltage VCC 7.0 Vdc
Input Voltage VI 5.5 Vdc
Driver Output Current IQiQl 150 mA
Junction Temperature TJ 150 °c
Operating Ambient Temperature Range TA o to +70 °c
Storage Temperature Range T stg -65 to +150 °c

ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, 4.5 V '" Vee"';: 5.5 V and 0, TAos;;; 70De, tYPical values are at TA = 2SoC, Vee = 5.0 V)
Ch.racteristic Symbol Min Typ MIX Unit
DRIVER PORTION
Input Voltage - High Logic State VltilQl 2.0 - - V
Input Voltage - Low logic State VUD) - - 0.8 V
Input Current - High Logic State IIH(D) - 50 40 ~A
IVIH = 24 V)
Input Current - Low Logic State IILID) - -0.2 -0.25 mA
IVIL = O.4V. VCC= SOY, TA= 25°C)
I nput Clamp Voltage VIK(D) - - -1.5 V
(11K = -12mAI
Output Voltage - High logic State (1) VOHIDI 2.5 33 3 7 V

•
IVIH(S) = 2.4 V or VIH(D) = 2.0 V)
Output Voltage - LOW Logic State VaLID) - - 05
IVI LISI = 0 8 V, VIL(DI = 0 8 V, IOLIDI = 48 mAl
Input Breakdown Current - - 10 mA
118(DI
IVtlDI = 5.5 V)
RECEIVER PORTION
I nput HysteresIs 400 625 - mV
Input Threshold Voltage - Low to High Output Logic State VILHIR) - 1.66 2.0 V
Input Threshold Voltage - High to Low Output Logic State VIHLlRI 0.8 1.03 - V
Output Voltage - High Logic State VOH(R) 2.4 - - V
IVIHIR) = 20 V, IOHIR) = -400/lAI
Output Voltage Low Logic State VOLIR) 0.5 V
IVILIR) = 0 8 V, IOLIRI = 8 0 mAl
Output Short-CircUit Current IOSIRI 40 - 14 mA
(V IH (R J "" 2 0 V) (Only one output may be shorted at a time)

8US LOAD CHARACTERISTICS

8us Voltage IVIH(E) - 24 V) VIBUS) 25 33 3 7 V
IIBUS = -12 mAl - - -15
Bus Current (VIHIDI- 24 V, VBUS;>50 VI I(BUS) 07 - mA
IVIHIDI = 24 V, VBUS = 0.5 VI -13 - -32
IVBUS" 5.5 VI - 25
(Vce = 0,0 V" VBUS" 2 75 V) - - 0.0'4
TOTAL DEVICE POWER CONSUMPTION
Power Supply Current
(All Drivers OFF)
(All Drivers ON)

SWITCHING CHARACTER ISTICS IVCC = 5.0 V, T A = 25°C)

Characteristic
DRIVER PORTION
Propagation Delay Time from Driver Input to Low Logic State 8us Output tPHLIDI - - 50 ns
Propagation Delay Time from Driver Input to High Logic State 8us Output tpLH~DJ - - 40 ns
Propagation Delay Time from Enable Input to Low Logic State BusOutput tPHLlE) - _. 50 ns
Propagation Delay Time from Enable Input to High Logic State BusOutput tPLH(E) - - 50 ns
RECEIVER PORTION
Propagation Delay Time from Bus Input to High Logic State Receiver Output
Propagation Delay Time from 8us I nput to Low Logic State Receiver Output

4-14
MC3446A

FIGURE 1 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
RECEIVER INPUT (BUS) TO OUTPUT

To Scope
(Output) +5.0 V

Input
To Scope
ov (Input)
tpLH(R)

Output
VOL

Pulse Input

FIGURE 2 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
DRIVER AND COMMON ENABLE INPUTS TO OUTPUT (BUS)

Pulse
To Scope
(Input)
+50 V

VOH
•
Output
VOL----'
Input

• Includes Probe and JIg Capacitance

FIGURE 3 - TYP)CAL RECEIVER HYSTERESIS FIGURE 4 - TYPICAL BUS LOAD LINE

CHARACTER ISTICS

0 60

r--- VCC~150V 40
T
TA ~ 25°C I
~

-
40 20
o :<
E I i---
~
w ...z I-- I
'" 30 w -20
~
~
~ (
o B -40
>
~ 20
~
=> I

I~~-
~ -60
~
o ~ -80 < -.> -:--

~ 10 10
II
IT 918
1_
12
- ~
o 14 II
o 05 10 15 2.0 -40 -20 20 40 60
VI. INPUT VOLTAGE (VOLTS) VBUS. BUS VOLTAGE (VOLTS)

4-15
 ® MOTOROLA MC3447

BIDIRECTIONAL INSTRUMENTATION OCTAL BIDIRECTIONAL

BUS (GPIB) TRANSCEIVER BUS TRANSCEIVER
WITH
This bidirectional bus transceiver is intended as the interface TERMINATION NETWORKS
between TTL or MOS logic and the IEEE Standard Instrumentation
Bus (4B8-1978, often referred to as GPIB). The required bus termi- SILICON MONOLITHIC
nation IS internally provided. INTEGRATED CIRCUIT
Low power consumption has been achieved by trading a minimum
of speed for low current drain on non-critical channels. A fast
channel is provided for critical A TN and EOI paths.
Each driver/receiver pair forms the complete Interface between
L SUFFIX
the bus and an Instrument. Either the driver or the receiver of each CERAMIC PACKAGE
channel IS enabled by a Send/Receive input with the disabled output CASE 623

of the pair forced to a high impedance state. The receivers have

input hysteresis to improve noise margin, and their input loading
follows the bus standard specifications.
P3 SUFFIX

•
• Low Power - Average Power Supply Current = 30 mA listening PLASTIC PACKAGE
75 mA Talking CASE 724
• Eight Driver/Receiver Pairs
• Three-State Outputs
• High Impedance Inputs
PIN ASSIGNMENTS
• Receiver HysteresIs - 600 mV (Typ)
• Fast Propagation Times - 15-20 ns (Typ)
Vee
• TTL Compatible Receiver Outputs
• Single +5 Volt Supply Bus 0
• Open Collector Driver Output with Terminations
• Power Up/Power Down Protection (No Invalid ~--~~~------~-r:2:D8us1
I nformation Transmitted to Bus)
• No Bus Loading When Power is Removed From Device Bus 2
• Required Termination Characteristics Provided

MAXIMUM RATINGS ITA = 25°C unless otherwISe noted)

Bus 4
Rating Symbol Value Unit
Power Supply Voltage VCC 70 Vdc
Bus 5
Input Voltage VI 5.5 Vdc
Dnver Output Current IOID) 150 mA
-41
Junction Temperature TJ 150 °c
Operating Ambient Temperature Range TA o to +70 °c
Storage Temperature Range T stg -65 to +150 °c

I Instrument
A I "
- --
,
-,
TYPICAL MEASUREM ENT
SYSTEM APPLICATI ON

I
(With GPIB)

......... Programmable

I
Calculator Vee

~u,
(With GPIB)
Instrument
B
(With GPIB) ,
,I
,
--- ---'f--<) Bus - Indicates
~ ~ Term,",,,on,
---
16 Lines Total Gnd

4-16
MC3447

ELECTRICAL CHARACTERISTICS
(Unless otherwise noted 450 V.;;;;, Vee';;;; 550 V and 0 ~ T A ~ 70 D e tYPical values are at T A"" 25 DC Vee"" 5 0 V)
Characteristic - Note 2 Symbol Min Typ Max Unit
Bus Voltage V
IBu, Pin OpenI(VIIS/R) = 0 8 V) VIBu,) 25 - 3.7
IIIBu,) = -12 rnA) VICIBu,) - - -15
Bus Current IlBu,) mA
150 V <; V IBu,) <; 55 V) 07 - 2.5
IVIBu,) = 0 5 V) -1.3 - -32
IVCC = 0 V, 0 V <; VIBu,) <; 2 75 V) - - +004
Receiver Input HysteresIs - 400 600 - mV
IVIIS/l'\) = 0 8 V)
Receiver Input Threshold V
IVIIS/R) = 0 8 V) Low to High VILHIR) - 16 20
High to Low VIHLlR) 08 10 -
Receiver Output Voltage - High Logic State VOHIR) 24 - - V
IVIIS/R) = 0 8 V, IOHIR) = -200 MA, VIBu,) = 2 0 V)
Receiver Output Voltage - Low Logic State VOLlR) - - 05 V
IVIIS/R) = 0 8 V, IOLlR) = 4 0 mA, IVIBu,) = 0 8 V
Receiver Output Short Circuit Current IOSIR) -40 - -20 mA
a V)

•
IVIIS/RI = 0 8 V, VIBu,1 = 2
Driver Input Voltage - High Logic State VIHIO) 20 - - V
IVIIS/R) = 2 a V)
Driver Input Voltage - Low Logic State VILlO) - - 08 V
IVIIS/R) = 2 0 V)
Driver Input Current - Data Pms MA
IVIIS/R) = 2 0 V)
105<;VIIO)<;27VI 11101 -100 - 40
IVIIO) =55V) IIBIO) - - 200
Input Current - Send/Receive MA
10 5 <; VIIS/R) <; 2 7 V) IIIS/R) -250 - 20
IVIIS/RI = 5 5 V) IIBIS/R) - - 100
Driver Input Clamp Voltage VICIO) - - -15 V
IVIIS/RI = 2 0 V, IICIO) = -18 mAl .,
Driver Output Voltage- High LogiC State VOHIOI 25 V
IVIS/R) = 2 0 V, VIHIO) = 2.0 V)
Driver Output Voltage - Low LogiC State (Note 1) vOLIO) - - 05 V
IVIIS/R) = 2 0 V, VILIO) = 0.8 V, IOLlO) = 48 mAl
Power Supply Current mA
(Listening Mode - All Receivers On) leCL - 30 45
(Talking Mode - All Drivers On) ICCH - 75 95

SWITCHING CHARACTERISTICS IVCC = 50 V TA = 25°C unless otherWISe noted)

Propagation Delay of Driver n,
(Output Low to High) tPLHIO) - 70 15
(Output High to Low) tPHLiO) - 16 30
Propagation Delay of Receiver (Channels a to 5, 7) n,
(Output Low to High) tPLHIR) - 28 50
(Output High to Low) tpHLiR) - 15 30
Propagation Delay of Receiver (Channel 6, Note 3) n,
(Output Low to High) tPLHIRI - 17 30
(Output High to Low) tpHLIR) - 12 22

NOTES 1. The IEEE 488-1978 Bus Standard changes VOL(OJ from 0.4 to 0.5 V maximum to permit the use of Schottky technology

2 Specified test conditions for VIIS/A) are 0.8 V (Low) and 2.0 V (High) Where VI(S/R) IS specified as a test condition, VI(S/R)
uses the oppoSite logiC levels
3. In order to meet the IEEE 488-1978 standard for total system delay on the ATN and EOI channels, a fast receiver has been
provided on Channel 6 (pms 9 and 16).

4-17
 MC3447

SWITCHING CHARACTERISTICS (continued) (Vcc = 5.0 V. TA = 25°C unless otherwISe noted)

Characteristic Symbol Min TVp Max Unit
Propagation Delay Time - Send/Receiver to Data ns
Logic High to Th ird State tpHZ(R) - 15 30
Third State to Logic High tpZH(R) - 15 30
Logic Low to Third State tpLZ(R) - 15 25
Third State to Logic Low tpZUR) - 10 25
Propagation Delay Time - Send/Receiver to Bus ns
Logic Low to ThIrd State tpLZ(D) - 13 25
Third State to Logic Low tpZL(D) - 30 50

PROPAGATION DELAY TEST CIRCUITS AND WAVEFORMS

FIGURE 1 - BUS INPUT TO DATA OUTPUT (RECEIVER)

To Scope
(Output) +5 av
Input
,---------....,
\15V 30 V
To Scope 1 k

~~L~R~
(Input) Data
tPl.HIRi

Output 1N916

I
or Equlv

tTLH = tTHL ~ 5 a ns (10-90)

Duty Cycle"" 50%
Pulse Sendl "'ncludes Jig
Generator Ree and Probe Capacitance

FIGURE 2 - DATA INPUT TO BUS OUTPUT (DRIVER)

30 V
To Scope
(Output) 3 av
Sendl

51
Pulse Bus

CL'130PF
f=10MHz
·Includes Jig
tTLH = tTHL";;:; 5 0 ns (10-90)\
and Probe Capacitance
Duty Cycle = 50%

FIGURE 3 - SEND/RECEIVE INPUT TO BUS OUTPUT (DRIVER)

To Scope
(Output)

Data Bus
Input
Send/Ree

Output
To Scope Low to Open
51
(Input)
Pulse
51
Generator 30V f=10MHz
CL = 30 pF (Includes Jig and
tTLH = tTHL "" ~ 5 0 ns (10-90)
Probe Capacitance
Duty Cycle = 50%

4·18
MC3447

FIGURE 4 - SEND/RECEiVE INPUT TO DATA OUTPUT (RECEIVER)

,...-------.-----3.0 V
5.0 V Input
OV

1.2 k
Output
HIgh to Open

Output
Low to Open
I_______ I-.-;.-==:...:..:~O V
2.0 V
51 CL = 15 pF (Includes Jig f= 1 OMHz
Pulse
and Probe CapacItance) tTLH "" tTHL =.s;; 50 ns (10-90)
Duty Cycle = 50%

. FIGURE 5 - TYPICAL RECEIVER HYSTERESIS

CHARACTERISTICS FIGURE 6 - TYPICAL BUS LOAD LINE
50 60
4.0
T

-r-
VCC~50V
I
-

-
4.0
I- TA ~ 15'C 10
T
Col)
:; ;;( .....-,
o .§
2:
w .... I ~
to 30 ~ -20 ........
'"
:;
o ~ -4.0
> jljon-6h,dIldA...
~ ~ -60
20 eon'OIIII'tu
!;
o
~-8.0 Paratfjlpb 3-5,31lif -;-
IEEE_d
~ 10 -10 _1918. ~

o
-12
-14
... "CC· S.QV
~I .I
-
o 0.5 1.0 15 10 -4.0 -20 20 40 6.0
VI. INPUT VOLTAGE (VOLTS) VBUS. BUS VOLTAGE (VOLTS)

FIGURE 7 - SUGGESTED PRINTED CIRCUIT BOARD LAYOUT USING MC3447. AND MC68488

10 MC68488 0

0 o _________
2 MC3447s
--JA~ ___________,

'r~"!"'~O 1§!fi.
0
0
0
0
0
0
0
0
0 : 0 i 0 4 0 I c>--- 0108
0 167 5 0 I c>---~~;
SIR (5) o-S/R(1-4)~

l Ii? : O------~_
0 T/R 1

:~~~ l/
0

~ 11 fiI""" "",,
0
DAV
DAC
,0<
RFD 0-_ _ _ _-' SR00---4 W 1 Gnd Gnd Gnd Gnd

0 REN 0----0
Jumper or second
0 T'FC level metal

4·19
 MC3447

FIGURE 8 - SIMPLE SYSTEM CONFIGURATION

+5 V

T/R 1 D80 D0

r-------...,I T/R2
Data

2 MC3447s D87 D7
I
I
I
DAV DAV R/Vii R/W
MC6802
RS0 A0
0101 iBll Me6S00
RS2 Address MPU

DI03 iB2

A15

I
0105 184

IRQ IRQ

0107 186

NDAC DAC

en
:;)
III EOI EOI
00
....
~
cO IFC we
...w
00
MC68488
w t--------~ GPIA
!!! I
SRQ SRQ

0102 181

DI04 183

DI06 185

0108 187

NRFD RFD NOTE l ' Although the MC3447 transceivers

are non~mvertlng, the 488-1978 bus callouts
appear mverted with respect to the MC68488
ATN pin designations This is because the 488-1978
ATN
Standard is defined for negative logic, while all
M6800 MPU components make use of POSitive
REN REN
logic format.

L ______ ...JI
Tng

-=

4·20
MC3447

FIGURE 9 - SUGGESTED PIN DESIGNATIONS FOR USE WITH MC68488

MC68488 MC68488
Connections MC3447 Pin Designations Connections
A B A B

T/R 2 VCC SIR 10) ~ VCC VCC VCC

OAV SRO Data 0 0 2 23 Bus 0 OAV SRO

IB0 iB1 Data 1 3 22 Bus 1 0101 0102

IB2 IB3 Data 2 4 21 Bus 2 0103 0104 MC68488

GPIA Instrument
IB4 IB5 Data 3 5 20 Bus 3 0105 0106

IB6 IB7 Data 4 6 Octal 19 Bus 4 0107 0108

GPtB
OAC RFO Data 5 7 Transceiver 18 Bus 5 NDAC NRFO
MC3447
T/R 2 T/R 2 SiR 15) 8 17 SIR 11-4) T/R 2 T/R 2
12)
EOI ATN Data 6 9 16 Bus 6 EOI ATN

iFC REN Data 7 10 15 Bus 7 IFC REN

•
T/R 1 Gnd SIR 16) 11 14 SiR 17) Gnd Gnd

Gnd Gnd Logic Gnd 12 13 Bus Gnd Gnd Gnd

OUTLINE DIMENSIONS
L SUFFIX P3 SUFFIX
CERAMIC PACKAGE PLASTIC PACKAGE
CASE 623-04 CASE 724-02
'JAllyp)" 53 0 CIW 'JAllypl" 90 0 CIW

NOTE
1 LEADS, TRUE POSITIONED WITHIN
025 mm (0 OlD) DIA AT SEATING
PLANE AT MAXIMUM MATERIAL
CONDITION (DIM 0)

MllllMEHRS INCHES
DIM
NOTES
MIN MAX MIN MAX
1 DIM "L"TO CENTER OF
A 3124 3217 1230 1290 lEADS WHEN FORMED
•
C
1270
406
1549
5"
0 ..0
0160
0610
0220
PARAllEL
2 LEADS WITHIN 0 13 mm
0 041 051 0016 0020 {ODDS) RADIUS OF TRUE
F 117 152 0050 0050 POSITION AT SEATING
G 254 sse olDDBSC PLANE AT MAXIMUM
J 020 030 ODD. 0012 MATERIAL CONDITION
0090 0160
K
l
M
'"
0'
406
152485(;
t5'
o BOOBse
0' t5'
(WHEN FORMED PARALLEL)

N 051 12' 0020 0050

THERMAL INFORMATION
The maximum power consumption an Integrated CirCUit the sum of the products of the supply voltages and supply
can tolerate at a given operating ambient temperature, can currents at the worst case operating condition
be found from the equation
T J(max) = MaXimum Operating Junction Temperature
TJ(max)-TA
as listed In the MaXimum Ratings Section
PD(T A) = ReJAITyp)
T A = MaXimum DeSIred Operating Ambient
Where PD(T A) = Power DISSipation allowable at a given Temperature
ReJA(Typ) = TYPical Thermal ReSIStance JunctIOn to
operating ambient temperature ThiS must be greater than
Ambient

4·21
 ® MOTOROLA MC3448A

BIDIRECTIONAL INSTRUMENTATION
BUS (GPIB) TRANSCEIVER
This bidirectional bus transceiver is Intended as the interface QUAD THREE-STATE
between TTL or MOS logic and the IEEE Standard Instrumentation BUS TRANSCEIVER WITH
Bus (488-1978. often referred to as GPIB). The required bus TERMINATION NETWORKS
termination is Internally provided.
SILICON MONOLITHIC
Each driver/receiver pair forms the complete interface between
INTEGRATED CIRCUIT
the bus and an Instrument. Either the driver or the receiver of each
channel is enabled by its corresponding Send/Receive input with
the disabled output of the pair forced to a high Impedance state. An
additional option allows the driver outputs to be operated In an
open collector(l) or active pull·up configuration. The receivers have

J'Iffm
Input hysteresIs to improve noise margin. and their input loading
follows the bus standard specifications.
• Four Independent Driver/Receiver Pairs
• Three-State Outputs
• High Impedance Inputs
CERAMIC PACKAGE
LSUFFIX ""'"
• Receiver HysteresIs - 600 mV (Typ) CASE 620

I
• Fast Propagation Times - 15-20 ns (Typ)
• TTL Compatible Receiver Outputs t. t

• Single +5 Volt Supply PSUFFIX

• Open Collector Driver Output Optlon(l) PLASTIC PACKAGE
• Power Up/Power Down Protection CASE 648

(No Invalid Information Transmitted to Bus)

• No Bus Loading When Power Is. Removed From Device
• ReqUired Termination Characteristics Provided

(1) Selection of the "Open Collector" configuration, In fact, selects an open collector device
with a passive pull-up load/termtnatlon which conforms to Figure 7, IEEE 488-1978 Send/Ree.
VCC
Bus Standard. Input A

MAXIMUM RATINGS IT A = 25 0 e unless otherwIse noted) Data A

Send/Rae.
Input 0
Rating Symbol Value Unit
Power Supply Voltage 7.0 Vdc BUIA Data 0
Vee
Input Voltage 5.5 Vdc Pull·Up
VI BUIO
Drtver Output Current laiD) 150 mA InputA-B Pull·Up
Junction Temperature TJ 150 °e BUI B Enabl.
Operating Ambient Temperature Range TA Oto+70 °e Input C-O
Storage Temperature Range Tstg -65 to +150 °e Date B BUIC

Sand/Ree. D.tee
Input B
Sond/Roc.
TYPICAL MEASUREME NT
--- - SYSTEM APPLICATIO N
Instrumant
.
I A
(With GPIB)
I '"
"

"
,- . J
Instrument
B
IWlth GPIB)
I TRUTH TABLE
Programmable Send/Rec Enabte Info. Flow Commentt
Calculator I I .............
I (With GPIB)

----
0 X 8us~Data

Data~Bus
Data -+Bus
Active Pull· Up
Open Col.

X '"' Don't Care

16 Lin .. Total

4-22
MC3448A

ELECTRICAL CHARACTERISTICS
IUnless otherwISe noted 4.75 V .;; VCC';; 5.25 V and 0.;; T A';; 70°C; typical values are at TA ~ 25°C, VCC ~ 5.0 V)
Characteristic Symbol Min Typ Max Unit
Bus Voltage V
IBus Pm Open)IVIIS/R) ~ 0.8 V) VIBUS) 2.75 - 3.7
(lIBUS) ~ -12 mAl VICIBUS) - - -1.5
8us Current IIBUS) mA
15.0 V .;; V IBUS) .;; 5.5 V) 0.7 - 2.5
IVIBUS) ~ 0.5 V) -1.3 - -3.2
IVcc ~ 0 V, 0 v.;; VIBUS)';; 2.75 V) - - +0.04
Receiver Input HysteresIs - 400 600 - mV
IVIIS/R) ~ 0.8 V)
Receiver Input Threshold V
IVIIS/R) ~ 0.8 V, Low to High) VILHIR) - 1.6 1.8
IVIIS/R) = 0.8 V, High to Low) VIHLlR) 0.8 1.0 -
Receiver Output Voltage - High Logic State VOH(R) 2.7 - - V
IVIIS/R) ~ 0.8 V, 10HIR) ~ -800 J.lA, VIBUS) = 2.0 V)
Receiver Output Voltage - Low Logic State VOLlR) - 0.5 V
(VIIS/R) ~ 0.8 V, 10LlR) ~ 16 rnA, VIBUS) ~ 0.8 V)
Receiver Output Short Circuit Current 10SIR) -15 - -75 rnA

•
IVIIS/R) ~ 0.8 V, VIBUS) ~ 2.0 V)
Driver Input Voltage High LogiC State VIH(O) 2.0 - - V
IVIIS/R) ~ 2.0 V)
Drtver Input Voltage - Low LogiC State VILIO) - - 0.8 V
IVIIS/R) = 2.0 V)
Drtver Input Current - Data Pins J.lA
IVIIS/R) = VilE) ~ 2 0 V)
10.5';; VIIO) .;; 2.7 V) 11(0) -200 - 40
IVI(O) ~ 5.5 V) IIB(O) - - 200
Input Current - Send/Receive J.lA
10.5';; VIIS/R)';; 2.7 V) IIiS/R) -100 - 20
IVIIS/R) = 5.5 V) IIBIS/R) - - 100
Input Current - Enable J.lA
10.5';; VIIEI .;; 2.7 V) IIIE) -200 - 20
IVIIE) ~ 5.5 V) IIBIE) - - 100
Driver Input Clamp Voltage VICIO) - - -1.5 V
IVI(S/R) = 2.0 V, IICIO) = -18 mAl
Driver Output Voltage - High LogiC State VOHIO) 2.5 - - V
IVIIS/R) ~ 2.0 V, VIHIO) = 2.0 V, VIHIE) ~ 2.0 V, 10H ~ -5.2 rnA)
Driver Output Voltage - Low LogiC State (Note 1) VOLIO) - - 0.5 V
IVIIS/R) ~ 2.0 V, 10LlO) ~ 48 mAl
Output Short CircuIt Current 10S(0) -30 - -120 rnA
IVIIS/R) = 2.0 V, VIHIO) = 2.0 V, VIH(E) ~ 2.0 V)
Power Supply Current mA
(Listening Mode - All Receivers On) ICCL - 63 85
ITalkmg Mode - All Onvers On) ICCH - 106 125

SWITCHING CHARACTERISTICS IVCC ~ 5.0 V,'TA ~ 25°C unless otherwise noted)

Propagation Delay of Driver ns

10utput Low to High) tPLHIO) - - 15
10utput High to Low) tPHLlO) - - 17
Propagation Delay of Receiver ns
10utput Low to High) tPLH(R) - - 25
10utput High to Low) tPHLlR) - - 23

NOTE 1. A modification of the IEEE 488-1978 8us Standard changes VOLtO) from" 0.4 to 0.5 V maximum to permit the use of
Schottky technology.

4-23
 MC3448A

SWITCHING CHARACTERISTICS (continued) (Vee = 5.0 V. TA = 25 0 C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit
Propagation Delay Time - Send/Receive to Data I ns
Logic High to Third State tPHZ(R) - - 30
Third State to Logic High tpZH(R) - - 30
Logic Low to Third State tPLZ(R) - - 30
Third State to Logic Low tpZL(R) - - 30
Propagation Delay Time - Send/Receive to Bus I ns
Logic High to Third State tpHZ(D) - - 30
Third State to Logic High tPZH(D) - - 30
Logic Low to Third State tpLZ(D) - - 30
Third State to Logic Low tPZUDI - - 30
Turn·On Time - Enable to Bus ns
Pull·Up Enable to Open Collector tpOFF(E) - - 30
Open Collector to Pull-Up Enable tPON(E) - - 20

PROPAGATION DELAY TEST CIRCUITS AND WAVEFORMS

FIGURE 1 - BUS INPUT TO DATA OUTPUT (RECEIVER)

To Scope
(Output) +50 V
30V
Input
\15V To Scope 240

~~L~R~
(Input)

• r-------_-
tPLH(R)
---VOH
Output 1.5 V lN916
or Equlv.

tTLH = tTHL::5O; 5 O,ns (10-90)

Duty Cycle = 50%
Pulse * Includes Jig and Sendl
Generator Probe Capacitance Rec

FIGURE 2 - DATA INPUT TO BUS OUTPUT (DRIVER)

To Scope 3.0 V

h
(Input)
To Scope

Sendl
(Output) • 23 V

Dnverlnp~t1 5 V
r--------. 30 V

Pulse
_+--<:>-.. Rec
£.... . .

Bus

CL'130 P F
383
or Enable

Output
tPLH(D) F
•
20 V
1 5 V

08 V
£tPH~(~)
---VOH

VOL
f= 1 QMHz
* Includes JIg
and Probe Capacitance Pull-Up Enable tTLH = tTHL'; 50 ns (10-90)
Duty Cycle = 50%

FIGURE 3 - SEND/RECEIVE INPUT TO BUS OUTPUT (DRIVER)

30V

To Scope ,-----30V
(Output) Input

Output
High to Open

To Scope
Output
(Input)
Low to Open
Pulse
Generator
51
CL =- 15 pF (Includes Jig and
f= 1.0MHz
Probe Capacitance
tTLH = tTHL =.; 5.0 ns (10-90)
Duty Cycle = 50%

4-24
MC3448A

FIGURE 4 - SEND/RECEIVE INPUT TO DATA OUTPUT (RECEIVER)

,--------".-----30 V
50V Input
1'----0 V

280
Output
High to Open

Output
Low to Open

51 CL = 15 pF (Includes Jig f =1 0 MHz

Pulse
and Probe Capacitance) tTLH = tTHL =.;;;; 5 0 ns (10-90)
DutY Cycle = 50%

30 V
FIGURE 5 - ENABLE INPUT TO BUS OUTPUT (DRIVER)

To Scope
(Output)
II
,---------,.·----30 V
Data 15 V 1 5 V
OV
Send/Ree
~F(EI
To Scope 480 ----90-%~ VOH
(Input)
Output

Pulse Voe
51 f= 1 OMHz
Generator CL = 15 pF (Includes Jig
and Probe Capacitance tTLH = tTHL =.;;;; 5 0 ns (10-90)
Duty Cycle = 50%

FIGURE 6 - TYPICAL RECEIVER HYSTERESIS

CHARACTERISTICS FIGURE 7 - TYPICAL BUS LOAD LINE
50 6.0
I

-
40
I
40 -
VCC- 5OV
~ - TA 25°C 20
I r--
'S"'
-
00
~
w >- I "...
,/"
I
'" 30 ~ -20
'"
~
00 ~ -4.0
> Non.shaded Area .;.
~ 20 ~ -6.0 Conto.... t. r-
!;
00
~ -8.0 l'\I,agraph 3-5.3 of f - -
IEEElltllndar4
~ 10 -10 48&.18l18 .. f--
-12 VCC"5.oV f---
o
< -, ,
-14
o 05 10 15 2.0 -4.0 -2.0 2.0 40 60
VI. INPUT VOLTAGE (VOLTS) VBUS. BUS VOLTAGE (VOLTS)

4-25
 MC3448A

FIGURE 8 - SIMPLE SYSTEM CONFIGURATION

+5 V

TIFt 1 DB?, O~

Data
TIFt 2
OB7 07

EOI EOI R/Vi R/W

MC6802
DR
SRO SRO R~Ja' A~
MC6800
RS2 MPU
Address
c
E REN REN

• .
~
,
o C
IFC IFC
A15
"'::;;

1--------1 IRO IRO

~ ATN r-~I------_t--+_-+--~ ATN

<Jl
:J
'"
""''"
;
f:::: OAC

RFO

lOAV OAV
~
W MC68488
W GPIA
W
0101 IBIi

IBI

IB2

IB3

IB4

NOTE 1! Although the MC3448A transceivers

IB5
are non-inverting, the 488-1978 bus callouts
appear Inverted with respect to the MC68488
pin designations, This is because the 488-1978
IB6 Standard is defmed for negative logic, while
all M6800 MPU components make use of
positive logic format.
IB7
NOTE 2. Unless proper considerations are
provided, It is recommended that the pull-up
Trig
enable pins on the MC3448As be grounded,
selecting the open-collector mode.

4-26
MC3448A

OUTLINE DIMENSIONS

NOTES

•
1 LEADS WITHIN 0 13 mm (0 005) RADIUS
OF TRUE POSITION AT SEATING PLANE
AT MAXIMUM MATERIAL CONDITION
2 PKG INDEX NOTCH IN LEAD
NOTCH IN CERAMIC OR INK DOT
3 DIM "L" TO CENTER OF LEADS
WHEN FORMED PARALLEL
NOTES
MILLIMETERS INCHES
1 lEADS WITHIN 0.13 mm
OIM MIN MAX MIN MAX (0005) RADIUS OF TRUE
MILLIMETERS INCHES A lB BO 21.34 0740 0 B40 POSITION AT SEATING
DIM MIN MAX MIN MAX B 610 660 0240 0260 PLANE AT MAXIMUM
e 406 50B 0160 0200 MATERIAL CONDITION
A 1905 19B1 0750 07BO o 03B 053 0015 0021
8 622 69B 0245 0275 2 DIMENSION "l" TO
F 102 17B 0040 0070 CENTER OF LEADS
e 406 50B 0160 0200 G 2548SC 0100BSC
D 03B 051 0015 0020 WHEN FORMED
H 038 241 0015 0095 PARALLEL
F 140165 0055 0065 J 020 03B OOOB 0015
G 2.548se o100 sse K 2 3.43 0 115 0 135
3 DIMENSION "B" DOES NOT
H 051 114 0020 0045 INCLUDE MalO FLASH
L 762 BSC 0300 BSC
J 020 030 OOOB 0012 M 00 100 00 100 4 "F" DIMENSION IS FOR FUll
K 3 18 4 06 0125 0160 051 102 0020 0040 LEADS "HALF" LEADS ARE
L 737 7B7 0290 0310 OPTIONAL AT LEAD POSITIONS
M 150 15° 1,8,9, and 16)
N 051 102 0020 0040 5 ROUNDED CORNERS OPTIONAL

CASE 620-02 CASE 648-05

THERMAL INFORMATION
The maximum power consumption an integrated Circuit the sum of the products of the supply voltages and supply
can tolerate at a given operating ambient temperature, can currents at the worst case operating condition_
be found from the equation:
TJ(max) -TA T J(max) = Maximum Operating Junction Temperature
as listed in the Maximum Ratings Section
PD(T A) = ReJA(Typ)
TA = Maximum Desired Operating Ambient
Where: PD(T A) = Power DISSipation allowable at a given Temperature
operating ambient temperature_ This must be greater than ReJA(Typ) = TYPical Thermal Resistance Junction to
Ambient

4·27
 MC3482 A/MC6882 A
® MOTOROLA MC34828/MC68828
ThIS deVice may be ordered under
either of the above type numbers.

OCTAL THREE-STATE BUFFER/LATCH OCTAL THREE-STATE

BUFFER/LATCH
This series of devices combines four features usually found
desirable in bus-oriented systems: 1) High impedance logic inputs
insure that these devices do not seriously load the
bus; 2) Three-state logic configuration allows buffers not being
utilized to be effectively removed from the bus; 3) Schottky
technology allows for high-speed operation; 4) 4B mA drive
capability.
• Invertrng and Non-Invertrng Options of Data
• SN74S373 Function Prnouts
• Eight Transparent Latches/Buffers rn a Single Package
L SUFFIX
• Full Parallel-Access for Loadrng and Reloading CASE 732
• Buffered Control Inputs
• All Inputs Have HystereSis to Improve NOISe Rejection
• High Speed - B.O ns (Typ)

II •
•
•
•
Three-State LogiC Configuration
Srngle +5 V Power Supply ReqUirement
Compatible with 74S LogiC or M6BOO Microprocessor Systems
High Impedance PNP Inputs Assure Mrnlmal Loadrng of the Bus
INPUT EQUIVALENT
CIRCUIT

MICROPROCESSOR BUS EXTENDER APPLICATION

(Clock)
Gnd+5V¢1 rp2

OUTPUT EQUIVALENT
CIRCUIT
vec

ORDERING INFORMATION
(Temperature Range for the following
devices'" 0 to + 75°C)
Package
Ceramic DIP
Ceramic DIP

4-28
MC~2A/MC~A·MC~2B/MC~2B

MAXIMUM RATINGS (TA = 25°C unless otherwISe noted.1

Rating Symbol Value Unit
Power Supply Voltage VCC B.O Vdc
Input Voltage VI 5.5 Vdc
Operatmg Ambient Temperature Range TA o to +75 vc
Storage Temperature Range T stg -65 to +150 °c
Operatmg Junction Temperature TJ °c
Ceramic Package 175

ELECTRICAL CHARACTERISTICS (Unless otherwISe noted OOC ';;TA ';;750 C and 4.75 V ';;VCC';;5 25 VI
Characteristic Symbol Min Typ Max Unit
Input Voltage - High Logic State VIH 2.0 - - V
(VCC = 4.75 V, TA = 250 CI
Input Voltage - Low Logic State VIL - - 0.8 V
(VCC = 4.75 V, TA = 250 CI
Input Current - HIgh Logic State IIH - - 40 )lA
(VCC = 5.25 V, VIH = 2.4 VI
Input Current - Low Logic State IlL - - -250 )lA

..
(VCC = 5.25 V, VIL = 0.5 V, VIL(OEI = 0.5 VI
Output Voltage - High Logic State VOH 2.4 - - V
(VCC = 4.75 V, 10H = -20 mAl
Output Voltage - Low Logic State VOL - - 0.5 V
IIOL = 48 mAl
Output Current - High Impedance State 10Z )lA
(VCC = 5.25 V, VOH = 2.4 VI - - 100
(VCC = 5.25 V, VOL = 0.5 VI - - -100
Output Short-Circuit CUrrent lOS -30 -80 -130 mA
(Vee = 5.25 V, Vo = 0) (only one output can be shorted at a time)
Power Supply Current MC3482A/MC68B2A ICC - 130 rnA
(VCC = 5.25 VI MC34828/MC68828 150
Input Clamp Voltage V IK - - -1.2 V
(VCC = 4.75 V, 11K = -12 mAl

SWITCHING CHARACTERISTICS (V cc = 50 V, O°C <; TA <; +75°C, unless otherwIse noted,lVPlcal @T A = 25°C I

MC3482AI MC348281
Characteristics Symbol MC6882A MC68828 Unit
Min Typ Max Min Typ Max
Propagation Delay Times ns
Data to Output
Low to High tpLH(DI
CL=50pF 40 90 16 40 90 16
CL = 250 pF _. 12 20 - 12 20
CL = 375 pF - 14 22 - 14 22
CL = 500 pF 10 16 24 10 16 24
High to Low tpHL(DI
CL = 50 pF 4.0 B.O 16 40 B.O 16
CL = 250 pF - 15 22 - 15 22
CL = 375 pF -- 18 25 -- 17 24
CL = 500 pF 16 21 28 14 18 27
Propagation Delay Times ns
Latch Disable (Low to High)
to Output
Low to High tPLH(LI
CL=50pF - 22 30 - 18 30
High to Low tpHLILI
CL = 50 pF - 23 30 - 14 25
Propagation Delay Times ns
(CL = 20 pFI
High Output Level to High Impedance tPHZ(OEI - 8.0 15 - 6.0 13
Low Output to High Impedance tpLZ(OEI - 20 27 - 15 23
High Impedance to High Output tPZH(OEI - 9.0 16 - 11 18
High Impedance to Low Output tPZL(OEI - 13 20 - 9.0 16

4-29
 MC~A/MC~A·MC~B/MC~B

AC SETUP CHARACTERISTICS (V cc = 5.0 V, o°c.;; T A ';; +75°C, unless otherwise noted, typical@T A = 25°C.)
MC3482AI MC3482BI
Characteristic Symbol MC6882A MC6882B Unit
Min Typ Max Min Typ Max
Setup Time ",u(D) 10 0 - 7.0 0 - ns
(Data to Negative Going Latch Enable)
Hold Time th(D) 10 - - B.O - - ns
(Data to Negative Going Latch Enable)
Minimum Latch Enable Pulse Width tWILl - 15 - - 15 - ns
(High or Low)

PIN CONNECTIONS AND TRUTH TABLES

.. MC3482A/MC6882A MC3482B/MC6882B

Output
Enable 1 Vee

Out 5

Output .output
Enable Latch Input Output Enable latch Input Output
0 1 0 1 0 1 0 0
0 1 1 0 0 1 1 1
0 0 X Qo 0 0 X Qo
1 X X Z 1 X X Z

4-30
MC~A/MC~2A·MC~B/MC~B

FIGURE 2 WAVEFORMS FOR PROPAGATION OELAY

FIGURE 1 - TEST CIRCUIT FOR SWITCHING CHARACTERISTICS TIMES DATA TO OUTPUT
To Scope r-----y----- 3 V
To Scope (Input)
Output
Closed for
Input or tpLZ(QE), tpZUOE) only
Enable +5 V
~
1 k Output
MC34B2A/MC6BB2A
50 1 N3064
Pulse
or EqUivalent
Generator

Output
MC34B2B/MC6BB2B _ _ _J
10k
C L Includes Probe and
Jig Capacitance
1 Closed for
tpHZ(OE),tPZH(OE) only
Input Pulse Conditions
tTHL"" tTLH < 5 ns
f= 10 MHz

MILLIMETERS INCHES
NOTES DIM MIN MAX MIN MAX
1 LEADS WITHIN 025 rnm (0 010) A 2388 25.15 0940 0990
CIA, TRUE POSITION AT
•

•
660 749 0260 0295
SEATING PLANE, AT MAXIMUM C 381 5.08 0.150 0.200
MATERIAL CONDITION 0 038 0.66 0015 0.022
2 DIM L TO CENTER OF LEADS 14 I
FIGURE 3 - WAVE FORMS FOR AC SETUP AND WHEN FORMED PARALLEL 0 2.54BSC 0.100 sse
3 DIM A At-.lO B INCLUOES 0.51 127 0.020 0.050
LATCH DISABLE TO OUTPUT DELAY MENISCUS J 0.20 0.30 0.008 0.012
.1 408 0.125 0.160
L 7.B2BSC 0.300 BSC
0' l' 0' 15'
N 025 1.02 .00 0.40

Latch

Input

(Data) ""'''''''''''''''+';''':~

tpLH(DI t
Output 1.5 V I --------

FIGURE 4- WAVEFORMS FOR PROPAGATION DELAY

TIMES - OUTPUT ENABLE TO OUTPUT

4-31
 ® MOTOROLA MC3870

Advance Inf'orxnation
MOS
SINGLE-CHIP MICRO CONTROLLER IN-CHANNEL, SILICON-GATE
DEPLETION LOAD)
The MC3870 IS a monolithic 8-blt microcomputer utilizing lon-
Implanted, N-channel silicon-gate technology and advanced CirCUit SINGLE-CHIP
design techniques The single-chip 3870 offers maximum cost effec-
MICROCONTROllER
tiveness "' a wide range of control and logic replacement applications

,
• Software Compatible with F8 Family
• 2048 Byte Mask Programmable ROM
• 64 Byte Scratchpad RAM
• 32 Bits 14 Ports) TTL-Compatible 1/0 L SUFFIX
CERAMIC PACKAGE
• Programmable Binary Timer CASE 715
Interval T'mer Mode
Pulse Width Measurement Mode

~ '
Event Counter Mode
,,' SSUFFIX
• External Interrup'
, " I CERDIP PACKAGE
• Crystal, LC, RC, External ,l'

II
I \ I, I ' CASE 734
• Low Power 1275 mW Typ )

~"l"
• Single + 5 Volt ± 10% Power Supply

; , !I ... ' . P SUFFIX

i i .• ' - PLASTIC PACKAGE
CASE 711

FIGURE 1 - PIN ASSIGNMENT

XTL 1
ABSOLUTE MAXIMUM RATINGS'
Operating Temperature XTL 2
o to 70'C 40 to + 85'C PO-O EXT INT
Temperature Under Bias - 20°C to + 85°C - 50°C to + 100°C
PO-1 P1-0
Storage Temperature - 65°C to + 150°C - 65°C to + 150°C
PO-2 P1-1
Voltage on any Pin with Respect to Ground
-10Vto+7V -10Vto+7V
(Except open-drain pins and TEST) PO-3 P1-2
Voltage on TEST with Respect to Ground -10 V to +9 V -10 V to +9 V P1-3
STROBE
Voltage to Open-Drain P:ns with Respect
-1 0 V to + 13 5 V -1 0 V to + 135 V P4-0 P5-0
to Ground
Power DISSipation 15W 15W P4-1 P5-1
Power DISSipation by any One 110 Pin 60 mW 60 mW P5-2
P4-2
Power DISSipation by All 110 Pins 600 mW 600 mW
P4-3 P5-3
• Stresses above those listed under" Absolute Maxtmurn Ratings" may cause permanent dam- P44 P5-4
age to the devIce ThiS IS a stress rating only and functional operation of the deVice at these or
P4-5 P5-5
any other conditions above those Indicated In the operatlona! sections of thiS specification IS
not Implied Exposure to absolute maximum rating conditions for extended periods may af- P4-6 P5-6
fect deVice reliability
P4-7 P5-7
PO-7 P1-7
PO-6 P1-6
P1-5
P1-4
TEST

4·32
MC3870

FIGURE 2 - BLOCK DIAGRAM

XTL '--l Clock EXT INT

XTL 2 - . lL -_ _ _..J

ROM
Address
Registers
PO, P, OC, DCl

Indirect Accumulator
Scratchpad and
Address Status Control
Logic

..
Register

Test

AC CHARACTERISTICS

Signal Symbol Parameter

o to 70'C -40° to +85°C
Unit Notes
Min Max Min Max
XTLl
to Time Base Penod, all clock modes 250 1000 250 500 ns
XTL2
texlHI External clock pulse width high 90 700 100 390 ns
texll} External clock pulse width low 100 700 110 390 ns
<I> t<l> Internal q, clock 2tO 2tO
WRITE tw Internal WRITE Clock penod 4t<l> 4t<l> Short Cycle
6t<l> 6t<l> Long Cycle
50 pF plus
tdl/O Output delay from Internal WRITE clock 0 1000 0 1200 ns
1/0 one TTL load
tsl/O Input setup time to Internal WRITE clock 1000 1200 ns
3t<l> 3t<l> 3t<l> 3t<l> 1/0 load~
tl/O-s Output valid to STROBE delay n;
-1000 +250 -1200 +300 50 pF + 1 TTL load
STROBE
8t<l> 12t<l> 8t<l> 12t<l> STROBE load~
tsL STROBE low time ns
- 250 +250 --300 +300 50 pF + 3 TTL loads
- -
RESET hold time, low
6t<l> 6t<l>
ns
tRH +750 +1000
- -
RESET
power power
--
RESET hold time, low for power clear
supply supply
ms
tRPOC rise flse
time +01 time + 015
6t<l> 6t<l> To trigger
EXT INT tEH EXT tNT hold tIme In active and inactive state +750 +1000 ns interrupt
2t<l> 2t<l> ns To trigger timer

4-33
 MC3870

DC CHARACTERISTICS 11/0 Power D,ss,pation:;; 100 mWI INote 21

Ot070+C -40 to +86'C
Symbol Parameter Min Max Min Max
Unit Conditions

VCC Power Supply Voltage 45 55 475 525 V

VII::IEX External Clock Input H'9h Level 24 Vec 24 VCC V
VILEX External Clock Input Low Level -03 06 -03 06 V
IIHEX External Clock Input High Current - 100 - 130 ~A VIHEX=VCC
IILEX External Clock Input Low Current - -100 - -130 ~A VILEX=VSS
20 VCC 22 VCC V Standard Pullup
VIHI/O Input High Level, I/O PinS
20 132 22 132 V Open Drain 111
VIHR Input High Level, RESET 20 VCC 22 VCC V
V HEI Input High Level, EXT INT 20 VCC 22 VCC
VIL Input Low Level -03 08 -03 07 V 111
IlL Input Low Current, All Pins with Standard PuUup Resistor - -16 - -19 mA VIN-04V
Input Leakage Current. Open Dram Pins, -- +10 - +18 VIN=132V
IL ~A
and Inputs with No Pull up Resistor - -5 - -8 VIN=02V
10H Output High Current Pins with Standard Pullup Resistor -100 - -90 - ~A VOH=24V
-15 - -13 - VOH-15V
IOHDD Output High Current Direct Dnve Pins mA
- -85 - -11 VOH=07V

II 10HS
10L
10LS
ICC
PD
STROBE OU1PUl High Current
Output Low Current
STROBE Output Low Current
Power Supply Current
Power DISSipation
-300
18
50
-
-
-
-
-
85
400
-270
165
45
-
-
-
-
-
110
525
~A VOL =24 V
mA VOL=04V
rnA VOL=04V
rnA Outputs Open
mW Oulputs Open

RESET and EXT INT have Internal Schmitt triggers giVing mmlmum 0 2 V hysteresIs
Power dlsslpal10n for I/O PinS IS calculated by EIVCC- VILI qllLI! = EIVCC- VOHlllioHI! = EIVOLIIIOLI

TIMER AC CHARACTERISTICS

Definitions
Error:::: Indicated time value ~ actual time value
tpse:::: t~ x Prescale Value

Interval Timei Mode:

Single Interval error, free running (Note 3) ±6t<l>
Cumulative Interval error free running (Note 3) o
Error between two Timer reads (Note 2) ± Itpsc + 1<1>1
Start Tlrner to stop Timer error INotes 1,4) + 1<1>10 - Itpse + t<l>l
Start Timer to read Timer error INotes 1,2) - 5t<l> 10 - Itpse + 7t<l>I
Start Timer to Interrupt request error (Notes 1,3) -2t<l> 10 -81<1>
Load Timer to Stop Timer error (Note 1) + t<l> 10 - Itpcs + 2t<l>I
Load Timer to read Timer error (Notes 1, 2) - 51 ± 10 - Itpse + 8t<l>I
Load Timer to Interrupt request error (Notes 1,3) -2t<l> 10 -9t<l>

Pulse Width Measurement Mode:

Measurement accuracy (Note 4) T 1<1> 10 -llpse+21<1>1
Minimum pulse width of EXT INT Pin 21<1>

Event Counter Mode:

Minimum active time of EXT INT Pin 2t<l>
Minimum inactive time of EXT INT pin 21<1>

NOTES
1 All times which entail loading, starting, or stopping the Timer are referenced from the end of the last machine cycle of the OUT or OUTS
Instruction
All times which entail reading the Timer are referenced from the end of the last machine cycle of the IN or INS Instruction
3 All times which entail the generation of an Interrupt request are referenced from the start of the machine cycle In which the appropriate in-
terrupt request latch IS set Additional time may elapse If the Interrupt request occurs dUring a pflvlleged or multlcycle Instruction
4 Error may be cumulative If operation IS repetitively performed

4-34
MC3870

FIGURE 3 - STROBE SOURCE CAPABILITY FIGURE 4 - S'fR5Be SINK CAPABILITY

(TYPICALATVCC=5V, TA=25°CI (TYPICALATVCC=5V. TA=25°C)
-15

+ 100

~
~
~

"'" L.oI
"'" 1"'0 I~

.....
,...
OUTPUT VOLT AGE

OUTPUT VOLTAGE

-1.5
FIGURE 5 - STANDARD 110 PORT SOURCE CAPABILITY
(TYPICALATVCC=5V, TA=25°C)
FIGURE 6 - DIRECT DRIVE I/O PORT SOURCE CAPABILITY

-10
(TYPICALATVCC~5V. TA=25°C)
II
1I -1.0
....
1-"'"

I
~
~
"" ....
!§ -0.5
~ "'"
""
~
OUTPUT VOLTAGE
"
4

OUTPUT VOLTAGE

FIGURE 7 - 110 PORT SINK CAPABILITY FIGURE 8 - MAXIMUM OPERATING TEMPERATURE

(TYPICALATVCC=5V. TA=25°C) vs 110 POWER DISSIPATION

10 0
+6 0

.
e
+5 0
..
<.>
I
... ... I ..
1+40 50
i'J.As7lC CERAMIC
ffi
1+3 0
"j
a
~+2
v; ~
... ...,1""

+1 0 100 200 300 400 500 600 1000

PoI/O-mW

OUTPUT VOLTAGE

4·35
 MC3870

FIGURE 9 - MC3870 100 vs TEMPERATURE (VCC= 5 VI

90

80 /'Il1o
l""
70 f'Io.
~
I"'"
'" 60
E l!!!o ~ r'"
I
I" r'"
050
9 I"I'!!0 "'"
40 "" i"o
30 ""
20
-40 -20 +20 +40 +60 +80 +100
TEMPERATURE TA - °c

• External Clock
FIGURE 10 - AC TIMING DIAGRAM

Internal 4> Clock

I/O Port Output

tSL J

EXT INT {-------,'CP

Bot 2 = ~ lE,,"=I'-----___
-'="-"~ ~
NOTE All measurements are referenced to VIL max. VIH min. VOL max, or VOH min

4·36
MC3870

FIGURE 11 - INPUT/OUTPUT AC TIMING

Intern al Cycle Timing

Write Depends on Instruction
Clock
~ p 31l s •

Port Addr
r
311:'"

Port Data
rp Next
rf..---J" '-
IN or INS
'Cycle Timing Op Code Placed on Driven on to Op Code
Shown for Fetched Data Bus Data Bus Fetched
4 MHz External
Clock
Port PillS )( IX
1 ~s
Setup
Max

•
t SilO
A Input on Port 4 or 5

Internal Cycle Timing

Depends on Instruction

Port Addr Accumulator Next

on Data Contents Op Code
Bus On Data Bus Fetched

Port PinS

STROBE ----+--1-"\1 Stays Low

(Active for Port 4 Only) l---F::'o'::r!..T::'w'::o=W-r-'t-e-..J
Cycles
500 ns" min
II/O-s
B. Output on Port 4 or 5

Internal

1 ~s
Max
Setup
1
Max
"s
C. Inpot on Port 0 or 1 D Output on Port 0, 1

4-37
 MC3870

3870 CLOCKS

The time base for the 3870 may originate from one of four system-to-system IS unsurpassed The 3870 has an Internal
sources The four configurations are shown In Figure 12 dlvlde-by-two to allow the use of inexpenSive and Widely
There IS an Internal 26 pF capacitor between XTL 1 and GND available TV Color Burst Crystals 1358 MHzl The follOWing
and an Internal 26 pF capacitor between XTL 2 and GND crystal parameters are suggested for 3870 applications
Thus, external capacitors are not necessarily required In all
external clock modes the external time-base frequency IS a) Parallel Resonance, Fundamental Mode AT-Cut.
diVided by two to form the Internal", clock. The external H C-33/ I' holder
clock frequency IS diVided by eight dUring short Instruction
bl Frequency Tolerance measured With 18 pF load
cycles and IS diVided by twelve dUring long Instruction cycles
(0 1% accuracy) - drive level 10 mW
as given per Instruction In the Instruction set towards the end
c) Shunt capaCItance (Col = 7 pF max
of thiS data sheet To get the total instruction cycle time,
diVide the external clock frequency by eight, Invert the d) Series reSistance IRs)
number, then multiply by the short number of cycles Then
diVide the external clock frequency by twelve and Invert the
number IYx) then multiply by the number of long cycles f= 1 MHz Rs = 550 ohms max
Add these two numbers to get the number of nanoseconds
f=2MHz Rs = 300 ohms max
per Instruction for a given clock frequency
f-3 MHz Rs= 100 ohms max

•
CRYSTAL SELECTION
f=358MHz Rs= 100 ohms max
The use of a crystal as the time base IS highly recommend-
f=4MHz Rs = 100 ohms max
ed as the frequency stability and reproducability from

FIGURE 12 - CLOCK CONFIGURATION

RC Mode Crystal Mode External Mode

9 t~Lr'
Minimum R= 4 kll
..L
'T' Cexternal (optional I
AT Cut 1 - 4 MHz
Open External
..L Clock
C=26 5 pF ±2 6 pF+Cexternal

LC Mode
Re CLOCK MOOE OF MC3870

:"'~

MInimum L = 0 1 mH
MInimum Q=4O
Cexternal (optional)

MaXimum Cexternal = 30 pF
C=13pF ±13pF+Cexternal
"""""
MAXIMUM 14.5·5.5 y, 0·C.70·ti
TYPICALIYCC-5 Y, TA-25·CI
MINIMUM 14.5·5.5 y, 0·C·70·CI
-
~= ;;.. ~--
1 10 12 14 16 18 20 22
f =2 ".,fIT: EXTERNAL RESISTOR IN KILOHMS

4·38
MC3870

FUNCTIONAL PIN DESCRIPTION MAIN CONTROL LOGIC

The Instruction Register IIRI receives the operation code
po-o - PO-7 AND Pl-0 - p;::; lOP codel or the Instruction to be executed from the pro-
Ports 1 and 2 are 16 lines which can be individually used as gram ROM via the data bus DUring all OP code fetches eIght
standard TTL-type Inputs or latched outputs bits are latched Into the I R Some Instructions are completely
specIfied by the upper four bits of the OP corle In those In-
P4-0 - m AND P1Ri - P5-7 structions the lower four bits are an Immediate register ad-
Ports 4 and 5 are 1611nes which can be individually used as dress or an Immediate 4-blt operand Once latched Into the
standard, open drain, or direct drive type latched outputs or I R the main control logiC decodes the Instruction and pro-
Inputs Refer to Figure 15 for more Information on port op- vides the necessary control gating signals to all CIrCUit
tions elements

STROBE ROM ADDRESS REGISTERS

ThiS output, which IS normally high, provides a single low There are four ll-blt registers associated With the 2K x 8
pulse after valid data IS present on port 4 (P4-0 - P4-71 dUring ROM These are the Program Counter IPOI, the Stack
an output instruction RegIster (PI, the Data Counter IDCI, and the AUXiliary Data
Counter IDC 11 The Program Counter IS used to address In-
RESET structions or Immediate operands P IS used to save the con-
tents of PO dUring an Interrupt or subroutIne call Thus, P
ThiS active low Input IS used to reset the Internal state of
contains the return address at which processing IS to resume
the microcomputer When allowed to go high, program ex-

•
upon completion of the subroutme or the Interrupt routine
ecution begins at $000
The Data Counter IDCI,s used to address data tables ThiS
register IS auto-Incrementing Of the two data counters only
EXT/INT
DC can access the ROM However, the XDC Instruction
ThiS Input IS an external Interrupt Its active state IS soft-
allows DC and DCl to be exchanged
ware programmable The Input IS also used In conlunctlon
ASSOCiated With the address registers IS an 11-blt Ad-
with the timer for pulse width measurement and event coun-
der/lncrementer ThiS logiC elerr.ent IS used to Increment PO
ting or DC when required an I ,s also used to add displacements
to PO on relative branches or to add the data bus contents to
XTL 1 AND XTL 2
DC In the ADC IAdd Data Counterl Instruction
These two Inputs Interface a crystal 11 to 4 MHzl, LC net-
work, RC network, or an external Single-phase clock to the
microcomputer
2048 x 8 ROM
The microcomputer program and data constants are
TEST
stored In the program ROM When a ROM access IS re-
TEST IS an Input used only In testing the MC3870 For nor- qUired, the appropriate address register (PO or DCI IS gated
mal CIrCUit functIOnality, thiS pin IS left unconnected or may
onto the ROM address bus and the ROM output IS gated on-
be grounded to the main data bus The first byte In the ROM IS location
zero
Vee
ThiS IS the power supply Input 1+5 V ± 10% I
SCRATCHPAD AND IS
Pin Name Description Type The scratch pad proVides 64 8-blt registers which may be
PO-O - PO-7 I/O Port 0 Bidirectional used as general purpose RAM memory The Indirect Scrat-
rn Pl-7 I/O Port 1 BidirectIOnal chpad Address Register liSI IS a 6-blt register used to ad-
dress the 64 registers All 64 registers may be accessed uSing
P4-0 P4-7 I/O Port 4 81dlrectlonal
IS In addition, the lower order 12 registers may also be
P5-0 - P5-7 I/O Port 5 Bldlrecllonal
directly addressed
STROBE Ready Strobe Output IS can be visualized as holdIng two octal digits ThiS diVI-
EXT INT External Interrupt Input sIon of I S IS lmportant since a number of instructIons Incre-
RESET External Reset Input ment or decrement only the least-slgplilcant three bits of IS
TEST Test Line Input when referenCing scratchpad bytes via IS ThiS makes It easy
to reference a buffer consisting of contiguous scratch pad
XTL 1, XTL 2 Time Base Input
bytes For example, when the low order octal digit IS in-
VCC, GND Power Supply Lines Input cremented or decremented I S IS Incremented from octal 27
10'28'1 to 0'20'1 or IS decremented from 0'20' to 0'27' ThiS
feature of the I S IS very useful In many program sequences
All SIX bits of IS may be loaded at one time or either half may
3870 ARCHITECTURE
be loaded Independently
ThiS section describes the baSIC funcllonal elements of the Scratchpad registers 9 through 15 (decimal I are given
3870 as shown In the block dIagram of F,gure 2 A program- mnemolliC names IJ, H, K, and QI because of speCial
ming model IS shown In Figure 13 linkages between these registers and other registers such as

4-39
 MC3870

the Stack Register These special linkages facilitate the Im- Just, add with carry, decrement, and Increment The logiC
plementation of multi-level Interrupts and subroullne operations that can be performed are AND, OR, EXCLUSIVE
nesting For example, the instruction LR K, P stores the OR, "l's" complement, shift right, and shift left Besides
lower eight bits of the Stack Register Into register 13 (K providing the result on the result bus, the ALU also prOVides
lower or KLI and stores the upper three bits of P Into register four Signals representing the status of the result These
12 (K upper or KU) Signals, stored 'r the Status Register (W), represent
CARRY, OVERFLOW, SIGN, and ZERO condition of the
result of the operation
ARITHMETIC AND LOGIC UNIT (ALU)
After receiving commands from the main control logic, the ACCUMULATOR (A)
ALU performs the reqUired arithmetic or logiC operations The Accumulator (A) IS the principal register for data
(using the data presented on the two Input buses) and pru- manipulation within the 3870 The A serves as one Input to
vldes the result on the result bus The arithmetic operations the ALU for arithmetiC or logical operations The result of
that can be performed In the ALU are binary add, deCimal ad- ALU operations are stored In the A

FIGURE 13 - MC3870 PROGRAMMABLE REGISTERS, PORTS, AND MEMORY MAP

Accumulator
Indirect
A Scratchpad
Address Aeglster Scratch pad Dec Hex OCI
7 __ 8BIIs_0
I I~ I o o

H
o

•
Status ISU ISl
Register 5 32 0
IWI _68,ts _ _

UHzlclsl
I 0 Z C S Program
J
HU
q
10
9
A
11
12
N V E A I Counter HL 11 B 13
TEA A G
A A 0
C L
N 0
F
A N
Y
I
10
POU
PO

8 7
I POL
I
0
KU
Kl
QU
12
13
14
C
o
E
14
15
16
TW -118115_ Ql 15 17
A
L
Stack I
4--5B,ts-0

I
Binary
Timer

Port 7
7 __ 8 Bits --0
10
PU

- 1 1 Blts_
Register

8 7
P
I Pl
I
0
§
7_8B,ts_0
61
62
63
3D
3E
3F
75
76
77

Interrupt
Control Port

I Port 6
Data
Counter Main Memory

I I
DC Memory Dec HEX
7--88,ts--0

R
DCU DCl 0 0
I
10 8 7 0
110 Ports
_ _ _ 11 Bits - - -
Port 5 A
0
I I
Aux Data M I I

~
Counter
Port 4
DCl
lOCI U I DCl l 2046 7FE
Port 1 10 8 7 o 2047 7FF
_IIB,ts_

PortO

4-40
MC3870

THE STATUS REGISTER (W) INTERRUPT CONTROL BIT IICB)

The Status Register (also called the W reglsterl holds five 1 he ICB may be used to allow or disallow Interrupts In the
status flags as shown In Figure 14 MC3870 ThiS bit IS not the same as the two Interrupt enable
bits In the Interrupt Control Port (ICPI If the ICB IS set anei
FIGURE 14 - STATUS REGISTER (WI the MC3870 Interrupt logic communicates an Interrupt re-
quest to the CPU section, the Interrupt Will be acknowledged
and processed upon completion of the first non-pnvileged In-
4
struction If the ICB IS cleared an Interrupt request will not be
Status Register (WI acknowledged or processed until the ICB IS set

1/0 PORTS
Sign The MC3870 proVides four complete bidirectional In-
putlOutput ports These are ports 0,1,4, and 5 In addition,
Carry the Interrupt Control Port IS addressed as port 6 and the
Zero binary timer IS addressed as pOI t 7 An output instruction
lOUT or OUTSI causes the contents of A to be latched Into
Overflow 11m dddressed port An Input instruction (IN or INSI transfers
Interrupt Control the cuntents of the port to A (port 6 IS an exception w~lch IS
Sit lJ(Jscflbed later) The schematiC of an I/O pin and lVJllahl8
(llJ1PlJ\ drive options are shown In Figure 18

Summary of Status Bits An output ready strobe IS associated With port 4 ThiS flag
may be used to signal a penpheral device that the MC3870

•
OVERFLOW~ CarrY7<1l CARRY6
has Just completed an output of new data to port 4 The
ZERO ~ ALU7AALU6AALU5AALU4AALU3AALU2A strobe provides a Single low pulse shortly after the output
Arn1
AALU O operation IS completely finished, so either edge may be used
CARRY ~ CARI'Y7 to signal the penpheral STROBE may also be used as an In-
SIGN~ALU7
put strobe Simply by dOing a dummy output of H '00' strobe
to port 4 after completing the Input operation

FtGURE 15 - 1/0 PIN CONCEPTUAL OIAGRAM WITH OUTPUT BUFFER OPTIONS

c0
~ Port
~ I/O
t: ;;
'"
c
0
U
0
11. Il. Pin

II:
0
& --']
II:
0

"0
~

II Output Buffer Options

1 n Typ

Standard Open Drain D1rect Drive

Output Output Output
Ports a and 1 are Standard Output type only
Ports 4 and 5 may both be any of the three output options (programmable blt-by-blt)
The STROBE output IS always configured Similar to a Direct Dnve Output except that It IS capable of driVing 3 TTL loads
RESET and EXT tNT may have standard 6 kO (typical) pullup or may have no pullup These two Inputs have Schmitt trigger Inputs
With a minimum of a 2 volts of hysteresIs

4·41
 MC3870

TIMER AND INTERRUPT CONTROL PORT reading the Interrupt Control Port (port 61 bit 7 of the Ac-
The Timer IS an 8-blt binary down counter which IS soft- cumulator IS loaded With the actual logiC level being applied
ware programmable to operate In one of three modes the In- to the EXT INT pin, regardless of the status of ICP b,t 2 (the
terval Timer Mode, the Pulse Width Measurement Mode, or eXT INT Active Level b,tl, that IS, If EXT INT IS a + 5 V blr 7
the Event Counter Mode As shown In Figure 16, associated of the Accumulator IS set to a log,e "1", but If EXT INT IS at
with the Timer are an 8-blt register called the Interurpt con- G NO then Accumulator bit 7 IS reset to logiC "0" ThiS
trol port, a programmable prescaler, and an 8-blt modulo-N capability IS useful In establishing a high speed polled hand-
register A functIOnal logiC dlag,am IS shown In Figure 17 shake procedure or for us,ng EXT INT as an extra Input pin 'f
external Interrupts are not requrred and the Timer IS used on-
INTERRUPT CONTROL PORT (PORT 6) ly In the Interval Timer Mode However, If It 's deSirable to
read the contents of the ICP then one of the 64 scratch pad
The deSired timer mode, prescale value, start,ng and stop-
registers or one byte of RAM may be used to save a copy of
ping the t,mer, act,ve level of the EXT INT pin, and local
whatever IS written to the ICP
enabhng or disabling of Interrupts are selected by outputtrr,g
the proper b't conf'gurat,on from the Accumulator to the In- The rate at which the timer IS clocked In the Internal Timer
terrupt Control Port (port 61 w'th an OUT or OUTS Instruc- Mode IS determined by the frequency of an Internal ¢ clock
tion Bits Within the Interrupt Control Port are defined as and by the diVISion value selected for the prescaler !The In-
follows
Bit °- External Interrupt Enable
Bit 1 - Timer Interrupt Enable
ternal ¢ clock operates at one-half the external time-base fre-
quencyl If ICP bit 5 IS set and bits 6 and 7 are cleared, the
prescaler diVides ¢ by 2 LikeWise, If bit 6 or 7 's individually
Bit 2 - EXT INT Act,ve Level set, the prescaler diVides ¢ by 5 or 20 respectively Combina-
Bit 3 - Startl Stop Timer tions of bits 5, 6, and 7 may also be selected For example, If
Bit 4 - Pulse Wldthllnterval Timer bits 5 and 7 are set while 6 IS cleared the prescale, Will diVide

•
B't 5 -- - 2 Prescale by 40 Thus, possible prescaler values are - 2, -- 5, - 10,
Bit 6 - - 5 Prescale - 20, - 40, - 100, and - 200
B,t 7 - - 20 Prescale
A spec,al situation exrsts when reading the Interrupt Con- Any of three conditions will cause the prescaler to be
trol Port (With IN or INS ,nstructlonl The Accumulator IS nor reset whenever the timer IS stopped by clearing ICP bit 3,
loaded With the content of the ICP, Instead, Accumulator
°
bits through 6 are loaded With "D's" while bit 7 IS loaded
With the logiC level being applied to the EXT INT pin, thus
execution of an output Instruction 10 Port 7, (the timer IS
assigned port address 71, or on the tra,ltng edge transition of
the EXT INT pin when In the Pulse Width Measurement
allOWing the status of EXT INT to be determined without the Mode These last two conditions are explained In more detail
necessity of servIcing an external Interrupt request When below

FIGURE 16 - TIMER AND CONTROL PORT BLOCK DIAGRAM

Timer
External Timer
Prescaler Clock Interrupt
Time 8-Blt Down Counter
Request
Base (Port 71
+2,5,10,20,40,100, or 200 Latch

Modulo-N Register
Interrupt a-Bits
Control
Port

E
(Port 61
7 6 5 4 3 2
External

Event Counter Mode . . - 0

, 0 0 I L External 'nterrupt Enable
Interrupt
Request

~
-:-2 Prescale _0 0
Latch
75 Prescale
-;-10 Prescale
_0
-0 , , 0 Timer Interrupt Enable

- ,,
-- ,
-;-20 Prescale 0 0 EXT INT Active Level
740 Prescale 0
-:-100 Prescale 0 Start/Stop Timer
-:-200 Prescale
' - - - - - - - - _ ... Pulse Width/Interval Timer

NOTE See Figure 17 for a more detailed functional dIagram

4·42
 FIGURE 17 - MC3870 TIMER/INTERRUPT FUNCTIONAL DIAGRAM
~
(")

~
From Interrupt Control Port
------------------- \
62 • 64 • 63 '65 , 66 , 67 .'INS 7' • 60 , 61 o
External

of the first non privileged

Instruction

~ ~ Acknowledge
.. Timer
~ Interrupt
.i:. 'OUTS 7'
c.l
'I' = Pulse Width Mode

External J"L
Interrupt r.-----JI
Input

JL.....

H 'OAO' upon completion

of the first nonprivllegad
Instruction

'DI'

Acknowledge
External
Interrupt

II
 MC3870

An OUT or OUTS Instruction to Port 7 will load the con- definitely and Will resume counting when bit 3 IS again set
tent of the Accumulator to both the Timer and the 8-blt Recall however that the prescaler IS reset whenever the
modulo-N register, reset the prescaler, and clear any Timer IS stopped, thus a series of starting and stoPPing will
preViously stored timer Interrupt request As preViously result In a cumulative truncation error
noted, the Timer IS an 8-blt down counter which IS clocked A summary of other timer errors IS given In the timing sec-
by the prescaler In the Interval Timer mode and In the Pulse tion of their speCification For a free running timer In the In-
Width Measurement Mode The prescaler IS not used In the terval Timer Mode the time Interval between any two inter-
Event Counter Mode The modulo-N register IS a buffer rupt requests may be In error by ± 6 '" clock periods although
whose function IS to save the value which was most recently the cumulative error over many Intervals IS zero The
outputted to Port 7 The modulo-N register IS used In an prescaler and Timer generate precise Intervals for setting the
three timer modes timer Interrupt request latch but the time out may occur at
any time Within a machine cycle IThere dee two types of
Interval Timer Mode - When ICP bit 4 IS cleared 1I0gic 01 machine cycles, short cycles which consist of 4 '" clock
and at least one prescale bit IS set the Timer operates In the periods and long cycles which consist of 6 '" clock pen ods 1
Interval Timer Mode when bit 3 of the ICP IS set the Timer In,<'rrupt requests 3re synchronIZed With the Internal
Will start counting down froM the modulo-N value After machine clock thus, giving nse to the pOSSible ± 6", error
counting down to H '01', the Timer returns to the modulo-N Additional errors may arise due to the Interrupt request oc-
value at the next count On the transition from H '01' to H 'N' cunng while a priVileged instruction or multlcycle instruction
the Timer sets a timer Interrut request latch Note that the in- IS being executed Nevertheless, for most applications all of
terrupt request latch IS set by the transition to H 'N' and not the above errors are negllblble, espeCially If the deSired time
be the presence of H 'N' In the timer, thus allOWing a full 256 Interval IS greater than 1 ms
counts If the modulo-N register IS preset to H '00' If bit 1 of

•
the ICP IS set, the Interrept request .s passed on to the CPU Pulse Width Measurement Mode - When ICP bit 4 IS set
section of the MC3870 However, If bit 1 of the ICP IS a logic Iloglc 11 and at least one prescale bit IS set, the Timer
o the Interrupt request IS not passed on to the CPU section operates In the Pulse Width Measurement Mode ThiS mode
but the Interrupt request latch remains set If ICP bit 1 IS IS used for accurately measuring the duration of a pulse ap-
subsequently set, the Interrupt request will then be passed plied to the EXT INT pin The Timer IS stopped and the
on to the CPU section I Recall from the discussion of the prescaler IS reset whenever EXT INT IS at ItS Inactive level
Status Register's Interrupt Control Bit that the Interrupt re- The active level of EXT INT IS defined by ICP bit 2, If cleared,
quest will be acknowledged by the CPU section only If ICB IS EXT INT IS active low, If set EXT INT IS active high If ICP bit
set) Only two events can reset the timer Interrupt request 3 IS set, the prescaler and Timer will start counting when EXT
latch when the timer Interrupt request latch IS acknowledg- INT tranSitions to the active level When EXT INT returns to
the inactive level the Timer then stops, the prescaler resets,
ed by the CPU section, or when a new load of the modulo-N
register IS performed and If lep bit a IS set an external Interrupt request latch IS set
ConSider an example In which the modulo-N register IS IUnl,ke timer Interrupts, external Interrupts are not latched If
loaded With H '64' Ideclmal 100) The timer Interrupt request the ICP Interrupt Enable bit IS not set 1
latch will be set at the l00th count follOWing the timer start As In the Interval Timer Mode, the Timer may be read at
and the timer Interrupt request latch Will repeatedly be set on any time, may be stopped at any time by clearing ICP bit 3,
precise 100 counter Intervals If the prescaler IS set at - 40 the prescaler and ICP bit 1 function as preViously deSCribed,
the timer Interrupt request latch will be set every 400 '" clock and the Timer stili functions as an 8-blt binary down counter
penods For a 2 MHz", clock 14 MHz time-base freuqencyl With the timer Interrupt request latch being set on the
thiS Will produce 2 millisecond Intervals Timer's transition fre,m H '01' to H 'N' Note that the EXT
The range of pOSSible Intervals IS from 2 to 51,200 '" clock INT pin has nothing to do With loading the Timer, ItS action IS
pen ods Ill's to 25 6 ms for a 2 MHz clockl However, ap- that of automatically starting and stoppmg the Timer and of
proXimately 50 '" penods IS a practical minimum because the generating external Interrupts Pulse Widths longer than the
time between setting the Interrupt request latch and the ex- prescale value times the modulo-N value are easily measured
ecution of the first Instruction of the Interrupt service routine by uSing the timer Interrupt service routine to store the
IS at least 29 '" periods Ithe response time IS dependent upon number of timer Interrupts In one or more scratch pad
how many priVileged instructions are encountered when the registers
request occursl, 29 IS based on the timer Interrupt occurlng As for accuracy, the actual pulse duration IS tYPically
at the beginning of a non-prlvllaged short instruction To slightly longer than the measured value because the status of
establish time Intervals greater than 51,200 '" clock penods IS the prescaler IS not readable and IS reset when the Timer IS
a Simple matter of uSing the timer Interrupt serVice routine to stopped Thus, for maximum accuracy, It IS adVisable to use
count the number of Interrupts, saving the result In one or a small diVISion setting for the prescaler
more of the scratch pad registers until the deSired Interval IS
achieved With thiS technique VIrtually any time Interval, or Event Counter Mode - When ICP bit 4 IS cleared and all
several time Intervals, may be generated prescale bits IICP bits 5, 6, and 71 are cleared, the Timer
The Timer may be read at any time and In any mode uSing operates In the Event Counter Mode ThiS mode IS used for
an Input instruction liN 7 or INS 71 and may take place "on counting pulses applied to the EXT INT pin If ICP bit 31s set.
the fly" Without Interfering With normal timer operatlcn the Timer Will decrement on each transition from the inactive
Also, the Timer may be stopped at any time by clearing bit 3 level to the active level of the EXT INT pm The prescaler IS
of the ICP The Timer will hold ItS current contents In- not used In thiS mode, but as In the other two timer modes,

4-44
MC3870

the Timer may be read at any time, may be stopped at any add I ess for a timer Interrupt IS H '020' The vector address
time by clearing ICP bit 3, ICP bit 1 functions previously for external Interrupts IS H 'DAD' After the vector address IS
described, and the timer Interrupt request latch IS set on the passed to the Program Counter, the CPU section sends an
Timer's transition from H '01' to H 'N' acknowledge Signal to the appropriate Interrupt request latch
Normally ICP bit 0 should be kept cleared In the Event which clears that latch The execution of the Interrupt ser-
Counter Mode, otherWise, external Interrupts Will be vice routine Will then commence The return address of the
generated on the transition from the inactive level to the ac- Original program IS automatically saved In the Stack Register,
tive level of the EXT INT pin P
For the Event Counter Mode, the minimum pulse Width re-
qUired on EXT INT IS 2 '" clock periods and the minimum In- The Interrupt Control Bit of W IStatus Register) IS
automatically reset when an Interrupt request IS acknowledg-
active time IS 2 '" clock periods, therefore, the maXI~lum
repetition rate IS 500 kHz ed It IS then the programmer's responsibility to determine
when ICB Will again be set Iby executing an EI instruction)
External Interrupts - When the timer IS In the Interval ThiS action prevents an Interrupt service routine from being
Timer Mode the EXT INT pin IS available for non-timer Interrupted unless the programmer so deSIres
related Interrupts If ICP bit 0 IS set, an external Interrupt re- Figure 18 details the Interrupt sequence which occurs
Quest latch IS set when there IS a transition from the inactive whether the Interrupt request IS from an external source via
level to the active level of EXT INT IEXT INf IS an edge- EXT INT or from the MC3870's Internal timer tvents are
triggered Input) The Interrupt request IS latched until either labeled With the letters A through G and are deSCribed
acknowledged by the CPU section or untillCP bit 0 IS cleared below
lunllke timer Interrupt requests which remain latched even
when ICP bit 1 IS clearedl External Interrupts are handled In Event A - An Interrupt request must satisfy a hold time

•
the same fashion when the Timer IS In the Pulse Width requirement as speCified In the AC Characteristics In order to
Measurement Mode or In th8 Event Counter Mode, except guarantee that It IS ,alid on the rising edge of the WRITE
that only In the Pulse Width Measurement Mode the external clock
Interrupt request latch IS set on the trailing edge of EXT I NT,
that IS, on the tranSItIOn from the active level to the Inactive Event B - Event B represents the instruction being ex-
level ecuted when the Interrupt occurs The last cycle of B IS nor-
mally the InstructIOn fetch for the next cycle However, If B IS
INTERRUPT HANDLING not a privileged Instruction al1d the CPU's Interrupt Control
When either a timer or an external Interrupt request IS Bit IS set, then the last cycle becomes a "freeze" cycle rather
communicated to the CPU section of the MC3870, It will be thar, a fetch At the end of the freeze cycle the Interrupt re-
acknowledged and processed at th6 completion of the first quest latches are Inhibited from altering the Interrupt dalsy-
non-privileged InstructIOn If the Interrupt Control Bit of the chain so that suffiCient time will be allowed for the dalsy-
Status Register IS S6t If the Interrupt Control Bit IS not set, chain to settle Ilf B IS a priVileged instruction, the instruction
the Interrupt request Will continue until either the Interrupt fetch IS not replaced by a freeze cycle, Instead, the fetch IS
Control Bit IS set and the CPU section acknowledges the In- performed and the next instructIOn IS executed Although
terrupt or until the Interrupt request IS cleared as previously unlikely to be encountered, a series of privileged Instructions
deSCribed Will be sequentially executed Without Interrupt One more in-
If there IS both a tlnler Interrupt request and an external In- struction, called a 'protected' Instruction, Will always be ex-
terrupt request when the CPU section starts to process the ecuted after the last priVileged Instruction The last cycle of
requests, the timer Interrupt IS handled first the protected Instruction then performs the freeze i
When an Interrupt IS allowed the CPU section Will request The dashed lines on EXT INT Illustrate the last opportunity
that the Interrupting element pass ItS Interl upt vector ad- for EXT INT to cause the last cycle of a non-protected In-
dress to the Program Counter via the data bus The vector structIOn to becorne a freeze cycle

FIGURE 18 - INTERRUPT SEQUENCE

Freeze Cycle

f----B --;1" C+D-T-E--j--FT G

INT REO
(Internal)

4·45
 MC3870

The freeze cycle IS a short cycle 14 '" clock periods) In all rupt response time IS 3 long cycles plus 2 short cycles plus
cases except where B IS the Decrement Scratch pad IIlStruC- one WRITE clock pulse Width plus a setup time of EXT INT
tlon, In which case the freeze cycle IS a long cycle 16", clock prior to the leading edge of the WRITE pulse - a total of 27
periods). '" clock periods plus the setup time At a 2 MHz", thiS IS
INT REO goes Iowan the next negative edge of WRITE If 14251's Although the maximum could theoretically be In-
both PRIIN IS low and the appropriate Interrupt enable bit of finite, a practical maximum IS 35 I's Ibased on the Interrupt
the Interrupt Control Port IS set. Both INT REO and WRITE request occurring near the beginning at a PI and LR K, P se-
are Internal signals quence)

Event C - A NO-OP long cycle to allow time for the Inter· POWER-ON RESET
nal priority chain to settle The intent of the Power-On Reset CIrCUitry on the MC3870
IS to automatically reset the deVice follOWing a tYPical power-
Event 0 - The Program Counter IPO) IS pushed I') tne up SituatIOn, thus saving external reset circuitry In many ap-
stack register IP) In order to save the return address The In- plications ThiS circuitry IS not guaranteed 10 sense a" Brown
terrupt Circuitry places the lower 8 bits of the Interrupt vector Out" lIow voltage) condition nor IS It guaranteed to operate
address onto the data bus This IS always a long cycle under all pOSSible power-on Situations
Three conditions are reqUired before the MC387C will leave
Event E - A long cycle In which the Interrupt CIrcuitry the reset state and begin operation Refer to Figure 19 as an
places the upper 8 bits of the Interrupt vector address onto aid to the follOWing deSCriptIOns The On-Chip V CC detector
the data bus senses a minimum value of V CC before It wl:1 allow the
MC3870 to operate The threshold of thiS detector IS set by
Event F - A short cycle ,n which the interrupting Interrupt analog Circuitry because a stable voltage reference IS not
request latch IS cleared. Also, the CPU's Interrupt Control Bit available With n-channel MaS processing. Processing varia-

I IS cleared, thus disabling Interrupts until an EI instruction IS

performed. The fetch of the next Instruction from the Inter-
rupt address

Event G _. Begin execution of the first Instruction of the

Interrupt service routine
tions Will cause thiS threshold to vary from a low of 3 0 volts
to a high of 4 3 volts With 3 5 volts being typical
The MC3870 uses a substrate bias as a technique to pro-
Vide Improved performarces versus power consumption
relative to conventIOnal grounded substrate approaches
ThiS bias generator may start operating as low as
V CC = 3 volts on some deVices while others may require
SUMMARY OF INTERRUPT SEOUENCE V CC = 4 volts in order 10 get adequate substrate bias Until
For the MC3870 the Interrupt response time IS defined as the substrate reaches the proper bias, the MC3870 Will not
the time elapsed between the occurrence of EXT INT gOing be released from the reset state The final condition required
active lor the Timer transltlonlng 10 H 'N') and the beginning IS that the clocks of the MC3870 must be functiOning
of execution of the first Instruction of the Interrupt service Typically the clocks Will start to functIOn at VCC equal to 3 to
routine The Interrupt response time IS a variable dependent 3 5 volts but since the part IS tested at 4 5 volts, Motorola
upon what the microprocessor IS dOing when the Interrupt can not guarantee any operation below 4 5 volts The output
request occurs As shown In Figure 18, the minimum Inter- of the delay CirCUit In Figure 19 will stay low until the clocks

FIGURE 19 - POWER ON RESET BLOCK DIAGRAM

To Internal
Wnte 3870 LogiC
Reset State = 1

4-46
MC3870

start to function If the Input to the delay CirCUit IS high, Into Vibrational motion ThiS time IS basically dependent on
tYPically after 100 cycles of the WRITE clock (800 cycles of the frequency Imass) of the crystal 4 MHz crystals tYPically
the external clock) the output of the delay CIrcuit will go high reqUire about 2-3 ms to start while 1 MHz crystals require
allowing the MC3870 to begin execution 60-70 ms to start oscillating Of course, thiS time may vary
If VCC falls to ground for at least a few hundred greatly from crystal to crystal and IS also a function of the
nanoseconds the output of the delay CIrCUit will go low Im- power supply rise time characteristic, however, the hlgh-
mediately and the MC3870 will reset frequency crystals start faster and are definitely recommend-
The Internal logic may detect a valid V CC, bias and clocks ed II e , 3-4 MHz)
at VCC=3 5 volts and allow the MC3870 to start executing The condition of the port pins dUring the power-In-clear
after the time delay With a slowly rising power supply, the sequence IS often asked The port pins or the STR08E line
part may start running before V CC IS above 4 5 volts which IS cannot be speCified until VCC reaches 45 V and the MC3870
below the guaranteed voltage range When power-an-clear enters the RESET state 8efore thiS, the port PinS may stay
IS required with a slowly rising power supply, an external at VSS, may track VCC as It rises, or they may track VCC
capacitor must be used on the RESET pin to hold It below part way up then return to VSS (ports 4 and 5 Will go to VCC
08 volts until VCC IS stable above 45 volts (Note The op- once the clocks are running and the MC3870 has sufficient
tion to disconnect the Internal pullup resistor on RESET IS VCC to properly operate the Internal control logiC and I/O
available which allows the use of a larger external pullup portsl
resistor and a small capacitor on RESET )
In many applications It IS desirable If the unit does an EXTERNAL RESET
automatic power-an-clear, but not mandatory The unit will When RESET IS taken low, the content of the Program
have a RESET push bulton and If the unit does not power-up Counter IS pushed to the Stack Register and then the Pro-
correctly or malfunctions because of some disturbance on gram Counter and the ICB bit of the W Status Register are

•
the VCC line, the operator Will simply press RESET and cleared The original Stack Register content IS lost Ports 4,
restore normal operation It IS for these applications that the 5, 6, and 7 are loaded With H '00' The contents of all other
Internal power-an-clear circuitry was designed registers and ports are unchanged or undefined When
In some applications It IS reqUired that the microcomputer RESET IS taken high, the first program Instruction IS fetched
continue to run properly without operator Intervention after from ROM location H '000' When an external reset of the
brown-outs, power line disturbances, electrical nOise, com- MC3870 occurs, PO IS pushed Into P and the old contents of
puter malfunction due to a programming bug, or any other P are lost It must be noted that an external reset IS recog-
disturbance except a catastrophic failure of some compo- nIZed at the start of a machine cycle and not necessanly at
nent the end of an instruction Thus, If the MC3870 IS executing a
One concept used to keep computers running IS that of multi-cycle instruction, that Instruction IS not completed and
the "WATCHDOG TIMER" The computer IS programmed the contents of P upon reset may not necessanly be the ad-
to periodically reset the watchdog timer dUring the normal dress of the instruction that would have been executed next
execution of ItS program (thiS IS easily done In the MC3870 as It may, for example, pOint to an Immediate operand If the
ItS normal application IS In some control function which IS reset occurred dunng the second cycle of an LI or CI Instruc-
tYPically periodic) As long as the computer continues to ex- tion Additionally, several instructions IJMP, PI, PI, LR, PO,
ecute ItS program the watchdog timer IS continually reset Q) as well as the Interrupt acknowledge sequence modify PO
and never times out Should the computer stop executing ItS In parts That IS, they alter PO by first loading one part then
program for whatever reason, the watchdog timer will time the other and the entlfe operation takes more than one cycle
out prodUCing a RESET pulse to the CPU re-startlng execu- Should reset occur dunng thiS modification process the
tion This IS a very positive way to assUle that the computer value pushed Into P Will be part of the old PO (the as yet un-
IS dOing ItS job, Ie, executing the program It IS Important modified part) and part of the new PO (already modified
that the software driving the watchdog timer test as many part) Thus, care should be taken Iperhaps by external
functional blocks (timer, ALU, scratchpad RAM, and ports) gating) to Insure that reset does not occur at an undeSirable
of the MC3870 as possible before resetting the watchdog time if any Significance IS to be given to the contents of P
timer This IS because operation of the MC3870, With an out after a reset occurs
of specification power supply, may allow some of the func-
tions to operate correctly while other functions are not Vcc DECOUPLING
operable The MC3870 family deVices have dynamiC CIrcuitry Inter-
Motorola can guarantee correct operation of the MC3870 nally which requires a good high frequency decoupling
only while the V CC voltage remains Within ItS specified capacitor to surpress nOise on the VCC line A 0 01 ~F or
limits If proper operation of the MC3870 must be o 1 I'F ceramic capacitor should be placed between V CC and
guaranteed after a disturbance on the VCC line, then an ex- ground, located phYSically close to the MC3870 deVice ThiS
ternal CirCUit must be used to mOnitor the V CC line and pro- Will reduce nOise generated by the MC3870 to about
duce RESET to the MC3870 whenever VCC IS out of the 70-100 mV on the VCC line
specified limits
A related characteristic to power-an-clear IS the startup TEST LOGIC
time of the basIc timing element The LC and RC oscillators SpeCial test logiC IS Implemented to allow access to the in-
begin to function almost Immediately once V CC IS high ternal main data bus for test purposes
enough to allow the on-board oscillator to operate In normal operation, the TEST Pin IS unconnected or IS
IV CC = 3 5 V) Operation With a crystal IS partly mechanical connected to GND When TEST IS placed at a TTL level
and some start time IS reqUired to get the mass of the crystal (2 0 V to 2 6 V) port 4 becomes an output of the Internal data

4-47
 MC3870

bus The data appearing on the port 4 pins IS logically true +5 V, bit 7 of the Accumulator IS set to a logiC "1", but, If
whereas Input data forced on port 5 must be logically false EXT INT IS at GND, then Accumulator bit 7 IS reset to logiC
When TEST IS placed at a high level (60 V to 70 V), the "0"
ports act as above and additionally the 2K x 8 program ROM
IS prevented from driVing the data bus In thiS mode, In the MC3870 (F8 COMPATIBLE) INSTRUCTION SET
operands and instructions may be forced externally through summary, the number of cycles shown are "nominal"
port 5 Instead of being accessed from the program ROM machine cycles A nominal machine cycle IS defined as 4 </J
When TEST IS In either the TTL state or the high state, clock periods, thus, requiring 21's for a 2 MHz </J clock fre-
STROBE ceases Its normal function and becomes a machine quency (4 MHz external time-base frequency)
cycle clock (,dent,cal to the F8 multi-chip system WRITE
Also, the summary uses an older nomenclature for register
clock except Inverted)
names The translation IS as follows
TlrTling complexities render the capabilities associated With
the TEST pin Impractical for use In a user's application, but PCO= PO Program Counter
these capabilities are thoroughly suffiCient to provide a rapid PCl = P Stack Register
method for thoroughly testing the MC3870 DCO= DC Data Counter
DCl = DCl Auxrlrary Data Counter
SUPPLEMENTARY NOTES The nomenclature IS used In order to be consistent With the
assembly language mnemonics
The Interrupt Control Bit of the W Status Register IS
For the MC3870, execution of an INS or OUTS Instruction
autc)matlcally reset when an Interrupt request IS acknow-
requires 2 machine cycles fur ports 0 and 1, whereas ports 4
ledgeo It IS then the programmer's responsibility to deter-
and 5 require 4 machine cycles
mine when ICB will again be set (by execution an EI instruc-
tion) ThiS action prevents an Interrupt serVice routine from

I
being Interrupted unless the programmer so deSires INSTRUCTION EXECUTION
When reading the Interrupt Control Port (port 6), bit 7 of
the Accumulator IS loaded With the actual logiC level berng ThiS section details the tlmrng and execution of the
applied to the EXT INT pin, regardless of the status of ICP MC3870 Instruction set Refer 10 Frgure 20 for a MC3870 Pro-
bit 2 (the EX r INT Active Level bit) ThiS IS, If EXT INT IS at gramming Model

4·48
 FIGURE 20 - MC3870 PROGRAMMING MODEL
s:
r---------------------~--~IAOC~
EI
01
------------~~ILNK~

sl w
OUTS 7

INS' 7
Timer
i
Ports
2 1 0
LISL

1 OUTS 6

IH~
Int Cntl

-,
IS INS' 6t Ports

LlSU
Scratch pad OUTS 0, I, 4, 5
Registers I/O
a 0 INS' 0, 1,4,5 Ports

Aux Data
Counter
3
4 4
3
n~I~ ~
~
ROM
xocrl OClt I
5
6
5
6
LR

I~
MEM
2048x8 8 10
LR ~o]_
~ LR 9 11
.J,..
<0 ~~l OCI l .. I oct ~ ~
LR _r A
B
U 12
Ht::13

Data Counter
---, c
o
K~
L 15 ~S~' ~ OS'
SL4
SRI
E U 16 SR4 ROM
-Q--
F L 17 Mem
AM' 2048 x 8
Pt ~ 11 1'~ 20 AMO

H~~~

Lf:I
XM
~
3C 74
pot 3D 75 t--CM'-""
JMP PI2 h:R 3E 76
L-J-..j~ ~ Program 3F 77
LM ••
Counter Hex Octal
IDC7L-----J
Int. Vector Reset Transfers PO to P and
From
Timer
H '020' 1 .1 then clears PO, ICB BIt of W
and Ports 4, 5,6. and 7

H 'OAO' .. These instructions set status

t The value of the external Interrupt mput IS loaded to Bn 7 of the accumulator (with Bits 0 through 6 loaded with zeros)
t H '000' RESET .1 when the Instruction 'INS 6' IS executed ThiS Instruction also sets status
External Interrupt ttPO, P. DC. and DCl are 12-bIt registers

NOTE The Instructions PI and PK are shown In two sequential parts (PI 1. PI2 and PK 1, PK2),

•
 MC3870

MC3870 INSTRUCTION SET

ACCUMULATOR GROUP INSTRUCTIONS

Mnemonic Machine Cycles Status Bits

Operation Operand Function
Op Code Code Bytes Short Long 12 MHz"l OVR ZERO CRY SIGN
Add Carry LNK A-IAI+ CR i 19 1 1 2 1/0 1/0 1/0 1/0
Add Immediate AI A-(A}+H'p' 2411 1/0 1/0 1/0 1/0
And Immediate NI A-IAIAH'II' 2111 1/0 1/0
Clear CLR A-H'OO' 70
Compare Immediate CI H'II' +(AJ+l 2511 1/0 1/0 1/0 1/0
Complement COM A-IAI + H'FF' 18 1/0 0 1/0
ExclusIve or Immediate XI A-{A)+H'II' 2311 1/0 0 1/0
Increment INC A-IAI+l IF 1/0 1/0 1/0 1/0
Load Immediate II A-H'II' 2011
Load Immediate Short LIS A-H'OI' 71
OR Immediate 01 A-(A)vH'I1' 2211 1/0 1/0
Shift Left One SL Shift Left 1 13 1/0 1/0
Shift Left Four SL Shift Left 4 15 1/0 1/0
Shift Right One SR Shift Right 1 12 1/0
Shift Right Four SR Shift Right 4 14 1/0

I BRANCH INSTRUCTIONS In all conditIOnal branches PO-IPO) + 211 the test conditIOn IS not met Execution IS complete In 3 short cycles

Operation
Branch on Carry
MnemOniC
Op Code
BC
Operand

aa
Function

PO-{PQ}+l+H'aa'
If CRY~ 1
Machine
Code
82aa
Bytes
2
Cycles
Short
2
long
1
Status Bits
12 MHz <1>1 OVR ZERO CRY SIGN

Branch on Positive BP aa PO-IPOI+ 1 + H'aa' 81aa

If SIGN~l

Branch on Zero BZ aa PO- IPOI + 1 + 'Haa' B4aa

If Zero= 1
Branch on True BT taa PO-IPOI+l+'Haa' 8taa
If any test IS true

Branch If Negative 8M aa PO-(POl+l+H'aa' 91aa

If SIGN~O
Branch If No Carry BNC aa PO-IPOI+l+H'aa' 92aa
If CARRY~O

Branch If No Overflow BNO aa PO- IPOI + 1 + H'aa' 98aa

If OVR ~O

Branch If Not Zero BNZ aa PO-IPOI + 1 + H'aa' B4aa

If ZERO~O

Branch If False Test BF taa PO- IPOI + 1 + H'aa' 9taa

TEST CONDITION If all false test bits

IO~F Iz~~ol C~Y Is~~NI

Branch If ISAR (Lower) BR7 aa PO- IPOI + 1 + H'aa' 8Faa
*7 ISARL*7
PO- IPOI + 2 If
ISARL~ 7

Branch Relative BR aa PO-IPOI+ 1 + H'aa' 90aa

Jump· JMP aaaa PO-H'aaaa' 29aaaa 11

·Prlvlleged Instruction, accumulator contents altered dunng execution JMP

4·50
MC3870

MEMORY REFERENCE INSTRUCTIONS In all Memory Reference Instructions, the Data Counter IS Incremented DC - (DCI +1
Mnemonic Machine Cycles Status Bits
Operation Operand Function
Op Code Code Byte. Short Long (2 MHz ¢I OVR ZERO CRY SIGN
Add Binary AM A-(AI+[lDCII BB 1 1 5 1/0 1/0 1/0 1/0
Add Decimal AMD A-(AI+[IDCII· 89 1/0 1/0 1/0 1/0
BCD Adlust
AND NM A-(AIAlIDCII 8A 1/0 0 1/0
Compare CM [IDCII + (AI + 1 8D 1/0 1/0 1/0 1/0
Exclusive OR XM A-IAle[lDCII 8C a 1/0 0 1/0
Load LM A-[IDCII 16
Logical OR OM A-IAlv[IDCII 88 1/0 1/0
Store 5T A-[IDCII 17

ADDRESS REGISTER GROUP INSTRUCTIONS

Mnemonic Machine Cycles Status Bits
Operation Operand Function
Op Code Code Bytes Short Long 12 MHz "I OVR ZERO CRY SIGN
Add to Data Counter ADC DC-IDCI+IAI 8E 1 1
Call to Subroutine- PK POU-(r121, OC
POL-lr131,
P-IPOI
Cail to Subroutine PI aaaa P-IPOI, 28aaaa 13
Imlredlate* PO- H'aaaa
Exchange DC
Load Data Counter

Load Data Counter

Load DC Immediate
XDC
LR

LR

DCI
DC, 0

DC, H

aaaa
IDCI=IDCll
DCU-lr141,
DCL-(r151
DCU-(rlO1,
DCL-lrlll
DC H'aaaa
2C
OF

10

2Aaaaa 12
II
Load Program Counter LR PO, 0 POU -lr141, OD 8
POL - Ir151
Load Stack Register LR P, K PU -lr121, 09
PL-r131
Return from POP PO=IPI lC
Subroutine·
Store Data Counter LR 0, DC r14-IDCUI, OE
r15-IDCLI
Store Data Counter LR H,DC rl0- DCU, 11
rl1-(OCLl
Store Stack Register LR K, P r12-IPUI, 08
r13-IPLI

SCRATCHPAD REGISTER INSTRUCTIONS (Refer to Scralchpad Addressing Modesl

MnemOniC Machine Cycles Status Bits

OperatIon Operand Function
Op Code Code Bytes Short Long (2 MHz ~I OVR ZERO CRY SIGN
Add Binary AS A-IAI+lrl Cr 1 1 2 1/0 1/0 1/0 1/0
Add DeCimal A5D A-(AI+lrl Dr 1/0 1/0 1/0 1/0
Decrement DS r - (rl + H'FF' 3r 1/0 1/0 1/0 1/0
Load LR A, r A-Irl 4r
Load LR A, KU A-lr121 00
Load LR A, KL A-lr131 01
Load LR A,OU A-(r141 02
Load LR A,OL A-lr151 03
Load LR r, A r-(Al 5r
Load LR KU,A r12-IAI 04
Load LR KL, A r13-IAI 05
Load LR OU,A r14-IAI 06
Load LR OL, A r15-IAI 07
AND N5 A-IAIAlrl Fr '2 1/0 1/0
Exclusive OR XS A-IAI+lrl Er 2 110 1/0

• Privileged Instruction, accumulator contents altered dunng execution of PI Instruction

4-51
 MC3870

MISCELLANEOUS INSTRUCTIONS

Mnemonic Machine Cycles Status Bits

Operation Operand Function
Op Code Code Byte. Short Long 12 MHz <PI OVR ZERO CRY SIGN
Disable Interrupt DI Reset ICB lA 1 1
Enable Interrupt" EI Set ICB lB
Input IN 04,05,00,07 A-Ilnput Port aal 26aa 1(0 1(0
Input Short INS 0,1 A-(lnput Port AO,At 1(0 1(0
o or 1)
Input Short INS 4,5,6,7 A- (Input Port a) Aa 1(0 1(0
Load ISAR LR ISA IS-IAI OB
Load tSAR Lower LlSL bbb ISL-bbb 610bbbl"
Load ISAR Upper LlSU bbb ISU-bbb 611bbbl"
Load Status Register" LR W,J W-lr91 1D 1(0 1(0 1(0 1(0
No Operation NOP $ PO-IPOI+ 1 2B
Output" OUT 04,05,06,07 Output Port 27aa
aa-(A)
Output Short OUTS 0, 1 Output Port BO,Bl
Oor 1-IAI
Output Short OUTS 4,5,6,7 Output Port a - (AI Ba
Store tSAR LR A,IS A-IISI OA
Store Status Reg LR J,W r9-IWI lE

I
.. Pnvlleged Instruction
**b= 1-blt Immediate operand

NOTES
Lower case denotes variables specified by programmer KL Register 13
KU Register 12
Function Definitions PO Program Counter
IS replaced by POL Least Significant 8 Bits of Program Counter
I I the contents of POU Most Significant 8 bits of Program Counter
I I Binary "15" complement of P Stack Register

.+
A
ArithmetiC Add (Binary or Decima))
Logical "OR" exclUSive
Logical" AND"
PL
PU
a
Least Significant 8 bits of Program Counter
Most Significant 8 bits of Active Stack Register
Reglstels 14 and 15
Logical "OR" inclUSive aL Relgster 15
H" Hexadecimal digit au Register 14
[I II Contents of memory speCified by ( a
Scratchpad Register (any address through B)
a Address Vanable (four bits) ISee Belowl
A Accumulator W Status Register
b One bit Immediate operand
Scratchpad Addressing Modes USing IS, Ir .. O through BI
DC Data Counter (Indirect Address Register)
r= H'C' Register Addressed by IS IS IUnmodlfledl
DCl Data Counter 1 (AuXIliary Data Counter)
r= H'D' Register Addressed by IS IS Incremented
DCL Least Significant 8 bits of Data Counter Addressed
r=HT Register Addressed by IS IS Decremented
DCU Most Significant 8 bits of Data Counter Addressed
r=H'F' Illegal OP Code
H Scratchpad Register 10 and 11
I Immediate operand (four bits) Status Register
ICB Interrupt Control Bit No change In condition
IS Indirect Scratchpad Address Register 1/0 IS set to "1" or "0" depending on conditions
ISL Least Significant 3 bits of ISAR CRY Carry Flag
ISU Most Significant 3 bits of ISAR OVR Overflow Flag
Scratchpad Register 9 SIGN Sign of Result Flag
K Registers 12 and 13 ZERO Zero Flag

4-52
MC3870

ORDERING INFORMATIC"l with a listing verification form The listing should be

thoroughly checked and the verification form completed,
The following information IS required when ordering a signed, and returned to Motorola The signed verification
custom MCU This Information may be transmitted to form constitutes the contractual agreement for creation of
Motorola In the following media the custorner mask If deSired, Motorola Will program a blank
PROM(s) MCM2716s or MCM2708s 2716 EPROM (supplied by the customer) from the data trle
MDOS disk file used to create the custom mask to aid In the verification pro-
cess
To initiate a ROM pattern for the MCU It IS necessary to
first contact your local field service office, local sales person,
or your local Motorola representative ROM VERIFICATION UNITS
Ten MC3870s containing the customer's ROM pattern Will
PROMs - The MCM2708 or MCM2716 type PROMs, pro- be sent for program verification These units Will have been
grammed with the customer program (positive logiC sense made uSing the custom mask but are for the purpose of
for address and data), may be submitted for pattern genera- ROM verification only For expediency they are usually un-
tion The PROMs must be clearly marked to Indicate which marked, packaged In ceramiC, and tested only at room
PROM corresponds to which address space (OOO-3FF HEX), temperature and 5 volts These RVUs are Included In the
1400-7FF) or IOOO-7FF) See Figure 21 for recomrnended mask charge and are not production parts
marking procedure
After the PROM Is) are marked they should be placed In
conductive IC carners and securely packed Do not use FLEXIBLE DISKS
styrofoam The disk media submitted must be Single-sided, slngle-

•
denSity, 8-lnch, MDOS compatible flOPPies The customer
FIGURE 21 - PROM MARKING must write the binary file name and company name on the
disk with a felt-tip pee The floppies are not to be returned by
Motorola as they are used for archival storage The minimum
MDOS system files must be on the dtsk as well as the ab-
solute binary object file I ("ename La type of file) from the
MC3870 cross assembler An object file made from a
memory dump uSing the ROLLOUT command IS also ad-
missable Consider submitting a source listing as well as the
follOWing ftles filename LX IEXORclser® loadable format)
and filename S,4 IASCII Source Code) These files Will of
000 400 course be kept confidential and are used 1) to speed up the
process in house If any problems arise, and 2) to speed up
xxx:::: Customer ID our customer to factory Interface If a user finds any 30ftware
errors and needs assistance qUickly from the factory
VERIFICATION MEDIA representatives
All original pattern media IPROMs or Floppy Disk) are filed MDOS IS Motorola's Disk Operatrng System available on
for contractual purposes and are not returned A computer development svstems such as EXORCisers, or EXORsets,
listing of the ROM code Will be generated and returned along etc

4·53
 MC3870

MC3870 ORDERING INFORMATION

Date _ _ _ _ _ _ _ _ _ _ _ _ _ Customer PO Number _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Customer Name _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Address _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

City _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ State _ _ _ _ _ _ _ _ _ _ _ _ _ _ ZIP _ _ __

Country _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Phone _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Extension _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Contact _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Customer Part Number

Options
Reset Pullup CJ No Pullup CJ
External Interrupt Pullup CJ No Pullup CJ

•
Port Options
Standard TTL Open Drain Direct DriVe

P4-0 CJ CJ Cl
P4-1 Cl CJ Cl
P4-2 Cl CJ Cl
P4-3 Cl CJ Cl
P4-4 Cl CJ Cl
P4-5 Cl CJ Cl
P4-6 Cl CJ Cl
P4-7 Cl CJ Cl
P5-0 CJ CJ Cl
P5-1 Cl CJ Cl
P5-2 Cl Cl Cl
P5-3 Cl CJ Cl
P5-4 Cl CJ Cl
P5-5 Cl Cl Cl
P5-6 Cl Cl Cl
P5-7 CJ CJ CJ

Pattern Media

c::J PROMs IMCM2716 or MCM27081 c::J Floppy Disk

(Customer can send In two extra PROMs,
Motorola will program the customer's c:J Other _ _ _ _ _ __
code on these PROMs for code Verification

Clock Mode _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
c:::J XT AL CJ RC CJ LC CJ External

Clock Freq

Temp Range _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
c:J 0-70'C CJ -40-+85'C

Marking Information (12 Characters Maximum)

NOTE All other media requires prior factory approval

4-54
 MC6800
® MOTOROLA
(1.0 MHzl
MC68AOO
(1.5 MHzl
MC68BOO
(2.0 MHzl

8-BIT MICROPROCESSING UNIT (MPUI MOS

The MC6800 IS a monolithic 8-blt microprocessor forming the central IN-CHANNEL, SILiCON-GATE,
control function for Motorola's M6800 family. Compatible With TTL, the DEPLETION LOAD)
MC6800, as With all M6800 system parts, requires only one + 50-volt
power supply, and no external TTL devices for bus Interface. MICROPROCESSOR
The MC6800 IS capable of addreSSing 64K bytes of memory With ItS
16-bit address lines The 8-blt data bus IS bidirectional as well as three-

~
state, making direct memory addreSSing and multiprocessing applica-
tions realizable.
• 8-Blt Parallel Processing SSUFFIX
• .' c CERDIP PACKAGE
• Bidirectional Data Bus

~,,::~
• 16-Blt Address Bus - 64K Bytes of AddreSSing
• 72 Instructions - Vanable Length
• Seven AddreSSing Modes - Direct, Relative, Immediate, Indexed,
Extended, Implied and Accumulator
PLASTIC PACKAGE
• Vanable Length Stack
CASE 711
• Vectored Restart
• Maskable Interrupt Vector
• Separate Non-Maskable Interrupt -

•
Stack
Internal Registers Saved In

SIX Internal Registers - Two Accumulators, Index Register,

Program Counter, Stack POinter and Condition Code Register
• Direct Memory AddreSSing (DMA) and Multiple Processor
L SUFFIX
CERAMIC PACKAGE
CASE 715
II
Capability
• Simplified Clocking Charactenstlcs
• Clock Rates as High as 2.0 MHz
PIN ASSIGNMENT
• Simple Bus Interface Without TTL
• Halt and Single Instruction Execution Capability VSS RESET

HALT TSC
1/>1 NC

TIm 1/>2
MAXIMUM RATINGS VMA OBE

Rating Symbol Value Untt NMI NC

Supply Voltage VCC -03to+70 V BA R/W
Input Voltage V ,n -03to+70 V DO
VCC
Operating Temperature Range TL to TH
01
MC~,MCOOAOO,MCOOBOO TA o to+70 ·C
MC~C, MCOOAOOC -40 to +85 Al 02
Storage Temperature Range T s1g -55to +150 'c A2 03
D4
A4 13 05
THERMAL RESISTANCE
Rating Symbol Value Unit A5 14 06
PlastiC Package 100 A6 15 07
Cerdlp Package 8JA 60 'C/W
A7 16 A15
Ceramic Package 50
A8 17 A14

ThiS device contains circuitry to protect the Inputs against damage due to high A9 16 A13
static voltages or electncal fields. however, It IS adVised that normal precautions 19 A12
Ala
be taken to aVOid application of any voltage higher than maximum-rated
voltages to thiS high-Impedance CtrCUlt Reliability of operation IS enhanced If All 20 Vss
unused Inputs are tied to an appropriate logic voltage Ie g , either VSS or VCC)

4-55
 MC~MC~AOO·MC~BOO

POWER CONSIDERATIONS

The average chip-Junction temperature, T J, In °C can be obtained from:

T J = TA + (PO· 6JA) (11
Where:
TA-Ambient Temperature, °C
6JA. Package Thermal Resistance, JunctlOn-to-Amblent, °C/W
Po - PINT + PPORT
PINT-ICC x VCC, Watts - Chip Internal Power
PPORT-Port Power Olsslpatlon, Watts - User Oetermlned
For most applications PPORToC PINT and can be neglected. PPORT may become significant If the device IS configured to
dnve Oarlington bases or sink LEO loads.
An approximate relationship between Po and T J (,f PPORT IS neglected) IS:
PO= K~(TJ+273°CI (2)
Solving equations 1 and 2 for K gives:
K= Po ··(TA+ 273°C) +8JA • P02 (3)
Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measunng Po (at eqUllibnum)
for a known T A. Using this value of K the values of Po and T J can be obtained by solving equations (1) and (2) Iteratively for any'
value of TA.

DC ELECTRICAL CHARACTERISTICS (Vcc=5 0 Vdc, ±5%, Vss=O, TA=lL to TH unless otherwise noted I

Characteristic Symbol Min Typ Max Unit

•
Input High Voltage LogiC VIH VSS+20 - VCC V
</>1,</>2 VIHC VCC-06 - VCC+03
Input Low Voltage LogiC VIL VSS-03 - VSS+O 8
V
</>1,</>2 VILC VSS-03 - VSS+04
Input Leakage Current
(V,n =Ot05 25 V, Vcc=Maxl LogiC lin - 10 25 p.A
IVIn=O to 5.25 V, VCC=O V to 5 25 VI </>1,</>2 - - 100
Three-State Input Leakage Current DD-D7 20 10
liZ p.A
(VIn =0.4t02 4 V, VCC= Maxi AO-A15, R/W - - 100
Output High Voltage
ULoad= -205,.A, Vcc=Mlnl DQ.D7 VSS+24 - - V
VOH
ULoad= -l45p.A, VCC= Mini AD-A15, R/W, VMA VSS+24 - -
ULoad= -loo,.A, VCC= Mini BA VSS+24 - -
Output Low Voltage ULoad-1.6 mA, VCC- Mini VOL - - VSS+04 V
Internal Power DISSipatIOn IMeasured at T A - TLI PINT - 05 10 W
Capacitance
(V,n=O, TA=25°C, 1= 1.0MHzI </>1 - 25 35
</>2 Cin - 45 70 pF
DD-D7 - 10 125
LogiC Inputs - 65 10
AD-AI5, R/W, VMA Cout - - 12 pF

CLOCK TIMING (VCC=5 0 V ±5% VSS=O TA=TL to TH unless otherwise noted)

Characteristic Symbol Min Typ Max Unit
Frequency 01 Operation MC6BOO 0.1 - 1.0
MC68Aoo I 01 - 15 MHz
MC68Boo 0.1 - 2.0
Cycle Time (Figure 1) MC6BOO 1000 - 10
MC68Aoo tcyc 0.666 - 10 p.s
MC68Boo 0.500 - 10
Clock Pulse Width </>l,</>2-MC6BOO 400 - 9500
(Measured at VCC-O.B VI </>1,</>2 - MC68Aoo PW</>H 230 - 9500 ns
</>1,</>2 - MC6BBoo 180 - 9500
Total </>1 and </>2 Up Time MC6BOO 900 - -
MC6BAoo tut 600 - - ns
MC6BBOO 440 - -
Rise and Fall Time (Measured between VSS+O.4 and VCC-O.BI tr,tl - - 100 ns
Delay Time or Clock Separation (Figure 11
(Measured at VOV=VSS+0.6 V@tr=tl:sloons) 1d 0 - 9100 ns
(Measured at VOV=VSS+ 1.0 V@tr=tl:S35nsl 0 - 9100

4-56
MC6800-MC680AOO-MC68BOO

FIGURE 1 - CLOCK TIMING WAVEFORM

~-----------------tcvc----------------~

~-----------------'u'------------~
tt/>f

Id

~VIHC
t/> V,LC
--j
Vov
___________________

't/>r
L =rt
I,::::

PWt/>H I-- 't/>f

READ/WRITE TIMING (Reference Figures 2 through 6, S, 9, 11, 12 and 13)

MC6IIOO MC68AOO MCII8BOO

Characteristic Symbol Unit
Min Typ Max Min Typ Max Min Typ Max
Address Delay
C= 90 pF tAD - - 270 - - 180 - - 150 ns

•
C=3O pF - - 250 - - 166 - - 135
Penpheral Read -Access Time
tacc=tut- (tAD+tDSR)
tacc 606 - --- 400 - -- 290 - - ns

Data Setup Time (Read) tDSR 100 - - 60 - - 40 - - ns

Input Data Hold Time tH 10 - - 10 - - 10 - - ns
Output Data Hold Time tH 10 25 - 10 25 - 10 25 - ns
Address Hold Time (Address, R/W, VMA) tAH 30 50 - 30 50 - 30 50 - ns
Enable High Time for DBE Input tEH 450 - - 280 - - 220 - - ns
Data Delay Time (Write) tDDW - - 225 - - 200 - - 160 ns
Processor Controls
Processor Control Setup Time tpcs 200 - - 140 - - 110 - -
Processor Control Rise and Fall Time tPCr, tpCf - - 100 - - 100 - - 100
Bus Available Delay tSA - - 250 - - 165 - - 135
ns
Three-State Enable tTSE - - 40 - - 40 - - 40
Three-State Delay tTSD - - 270 - - 270 - - 220
Data Bus Enable Down Time Dunng t/>1 Up Time lOBE 150 - - 120 - - 75 - -
Data Bus Enable Rise and Fall Times tOBEr, IDBEf - - 25 - - 25 - - 25

FIGURE 2 - READ DATA FROM MEMORY OR PERIPHERALS

/ Start of Cycle

</>2

Address
From MPU

--_"'""_________-'tacc __________~+_~

FromOa"
Memory _____ ~____________________________~2~O~V~~~st~~~~~~
or Pertpherals 08 V

4-57
 MC6800· MC68AOO. MC68BOO

FIGURE 3 - WRITE IN MEMORY OR PERIPHERALS

, - - Start of CYcle

~-----------------------teyc----------------------~

AddreS$
F'omMPU __~~~~~~~~~~~____________________________________+1~~

v MA _ _ _ _ -f"'~

• OBe

08t8 MPU
From
~------------tEH------------~

---------------------~--~~~~r_~----~~~~----~~
Data Valid ~>------

~~ O.t. Not Valid

FIGURE 4 - TYPICAL DATA BUS OUTPUT DELAY FIGURE 5 - TYPICAL READ/WRITE, VMA, AND ADDRESS
versus CAPACITIVE LOADING (TDDWI OUTPUT DELAY versus CAPACITIVE LOADING (TAD)
600 600
IOH =-205"A [email protected] 10H =-145"A max@2 4 V
IOL = 16 mA [email protected] IOL'" 1 SmA max@04V
500 VCC = 5.0V VCC = 5.0 V
500
lA = 25'C TA=25'C

- --
400 ] 400
~
,.
w

-
~ i= VMA
i= 300
>- 300 I
>-
g ,...... V- Address. RN(-- -

--
~
0 200
..- V 200
~ ~I-"" f.--
100
_I----
100

CL includes stray capacitance CL mcludes stray capacitance

100 200 300 400 500 600 100 200 300 400 500 600
CL. LOAD CAPACITANCE (pFI CL LOAD CAPACITANCE (pFI

4-58
MC68OQ-MC68AOO-MC68BOO

FIGURE 6 - BUS TIMING TEST LOADS

vcc
RL = 2.2 kll
TEST CONDITIONS
Test POint 0-_-.....-..,1+-... MM06150
or Equiv
The dynamic test load for the Data Bus IS
130 pF and one standard TTL load Ib shown.
The Address. R/W. and VMA outputs are tested
C R under two conditions to allow optimum opera-
MM07000
tion In both buffered and unbuffered systams.
or Equiv. The r.s,stor (R) is chosen to Insure specified
load currents dUring VOH measurement.
Netlcs that the Data Bus hnes, the Address
Itnes, the Interrupt Request hne, and the DBE
C"" 130 pF for 00-07. E
line are all speclf.ed and tested to guarantee
= 90 pF for AO-A 15, R/W, and VMA 04 V of dynamiC nOise Immunity at both
(Except tA02) "'" and "0" logiC levels.
.. 30 pF for AO-A 15, RIW, and VMA
(tA02 only)
= 30 pF for SA
R"" 11 7 kG for 00-07
= 16 5 k{}. for AO-A1S. RtW. and VMA
"" 24 kO for SA

A15
26
A14
24
A13
23
FIGURE 7 - EXPANDED BLOCK DIAGRAM

A12
22
A11
20
A10
19
A9
18
A8
17
A7
16
A6
15
A5
14
A4
13
A3
12
A2
11
A1
10
AO
9 ..
Clock, .1 3

Clock, .2 37

RESET 40
Non-Maskable Interrupt 6

HALT 2 Instruction
Interrupt Request 4 Decode
and
Three-State Control 39
Control
Data Bus Enable 36

Bus Available
Valid Memory Address 5

Read/Wrlte, R/W 34

Vcc=Pin 8 32 33
26 'IT 28 29 30 31
VSS=Plns 1, 21
D7 DB 05 04 D3 02 D1 DO

4·59
 MC6800-MC68AOO-MC68BOO

MPU SIGNAL DESCRIPTION

Proper operation of the MPU requires that certain control Read (high) or Write (low) state. The normal standby state of
and timing signals be provided to accomplish specific func- thiS signal IS Read (high). Three-State Control going high Will
tions and that other signal lines be mOnitored to determine turn Read/Write to the off (high Impedance) state. Also,
the state of the processor. when the processor IS halted, It Will be In the off state. ThiS
output IS capable of driving one standard TTL load and
Clocks Phase One and Phase Two (4)1, 4>2) - Two pins 90 pF.
are used for a two-phase non-overlapping clock that runs at
the VCC voltage level. RESET - The RESET Input IS used to reset and start the
Figure 1 shows the microprocessor clocks. The high level MPU from a power down condition resulting from a power
IS speclfled at VIHC and the low level IS specified at VILC failure or initial start-up of the processor. This level sensitive
The allowable clock frequency IS specified by f (frequency). input can also be used to relnltlallzll the machine at any time
The minimum 4> 1 and 4>2 high level pulse Widths are specified after start-up.
by PW4>H (pulse Width high time) To guarantee the required If a high level IS detected In thiS Input, thiS will signal the
access time for the peripherals, the clock up time, tut, IS M PU to begin the reset sequence. DUring the reset se-
specified. Clock separation, td, IS measured at a maximum quence, the contents of the last two locations (FFFE, FFFF)
voltage of Vav (overlap voltage). ThiS allows for a multitude In memory Will be loaded Into the Program Counter to pOint
of clock variations at the system frequency rate. to the beginning of the reset routine. During the reset
routine, the Interrupt mask bit IS set and must be cleared
under program control before the MPU can be Interrupted by
Address Bus (AO-A15) - Sixteen pins are used for the ad- IRQ. While RESET IS low (assuming a minimum of B clock
dress bus. The-outputs are three-state bus drivers capable of cycles have occurred) the MPU output Signals will be In the

II
driving one standard TTL load and 90 pF When the output is following states: VMA= low, BA= low, Data Bus= high Im-
turned off, it IS essentially an open CircUit. ThiS permits the pedance, R/IN= high (read state), and the Address Bus Will
MPU to be used In DMA applications Putting TSC In ItS high contain the reset address FFFE. Figure 8 illustrates a power
state forces the Address bus to go Into the three-stllte mode up sequence uSing the RESET control line. After the power
supply reaches 4.75 V, a minimum of eight clock cycles are
Data Bus (DO-07) - Eight PinS are used for the data bus reqUired for the processor to stabilize In preparation for
It IS bidirectional, transferring data to and from the memory restarting During these eight cycles, VMA Will be In an In-
and peripheral deVices. It also has three-state output buffers determinate state so any deVices that are enabled by VMA
capable of driVing one standard TTL load and 130 pF Data which could accept a false write dUring thiS time (such as
Bus is placed In the three-state mode when DBE IS low. battery-backed RAM) must be disabled until VMA IS forced
low after eight cycles RESET can go high asynchronously
Data Bus Enable (OBE) - ThiS level sensitive Input is the With the system clock any time after the eighth cycle.
three-state control signal for the M PU data bus and Will
enable the bus drivers when in the high state. ThiS Input IS RE'SET timing IS shown In Figure 8 The maximum rise and
TTL compatible; however In normal operation, It would be fall transition times are speCified by tPCr and tPCf If RESET
driven by the phase two clock. During an MPU read cycle, IS high at tpcs (processor control setup time), as shown In
the data bus drivers Will be disabled Internally. When It IS Figure 8, In any given cycle then the restart sequence Will
deSired that another deVice control the data bus, such as In begin on the next cycle as shown The RESET control line
Direct Memory Access (OMA) applications, DBE should be may also be used to relnltlallze the M PU system at any time
held low. dUring ItS operation ThiS IS accomplished by pulSing RESET
If additional data setup or hold time is reqUired on an M PU low for the duration of a minimum of three complete 4>2
write, the DBE down time can be decreased, as shown In cycles. The RESET pulse can be completely asynchronous
Figure 3 (DBE"4>2). The minimum down time for DBE is With the MPU system clock and Will be recognized dUring 4>2
tDBE as shown. By skeWing DBE With respect to E, data If setup time tpcs IS met.
setup or hold time can be Increased
Interrupt Request IiRQ) - ThiS level sensitive Input re-
Bus Available (BA) - The Bus Available signal Will nor- quests that an Interrupt sequence be generated within the
mally be in the low state; when activated, It will go to the machine. The processor Will walt until It completes the cur-
high state indicating that the microprocessor has stopped rent instruction that IS bemg executed before It recognizes
and that the address bus IS available. ThiS will occur If the the request. At that time, If the Interrupt mask bit In the Con-
HALT line is In the low state or the processor IS In the WAIT dition Code Register IS not set, the mach me Will begin an m-
state as a result of the execution of a WAIT Instruction. At terrupt sequence The Index Register, Program Counter, Ac-
such time, all three-state output drivers will go to their off cumulators, and Condition Code Register are stored away on
state and other outputs to their normally Inactive level. The the stack. Next, the MPU Will respond to the Interrupt re-
processor IS removed from the WAIT state by the occurrence quest by setting the mterrupt mask bit high so that no further
of a maskable (mask bit 1= Ol or nonmaskable interrupt. ThiS interrupts may occur. At the e~d of the cycle, a 16-blt ad-
output is capable of driving one standard TTL load and dress Will be loaded that pOints to a vectoring address which
30 pF. If TSC is In the high state, Bus Available will be low. is located m memory locations FFFB and FFF9. An address
loaded at these locations causes the MPU to branch to an In-
Read/Write (R/W) - ThiS TTL compatible output signals terrupt routine in memory. Interrupt timing IS shown m
the peripherals and memory devices wether the MPU IS In a Figure g.

4·60
 ~

~•
FIGURE 8 - REm TIMING
I Cycle
I #1
I #2 1#5 #6 #7 #8 #9 In + lin + 21n + ~I n+41 n+51 1m + + 21m + + 31

p-
~~
~:::;. J
On

s..""'y -f 5_25 V
4_15 V
II

JJ
I
f
"t
(I
------1
_
tpcs ~
JLJLJl-J
I<

'~
f---
I

tpcs
~
(')

~•
~
RESET If Ir----/i I~,;-_ _ _ _- (')
---1 t--- tpc, ---1 I-- tPCf
~
::
:=res5 S\\\\\\\\\\\\\\\\\\\\\"""""1.\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\~f=:=-'-,-="-=-'-~==-~=~--:d:,"_-J\_~~~,,"=,-=,,===
==:~~t:\m~==:'\\\\\\\Y FFFE ~f FFFE FFFE I FFFE FFFF New PC ~E
OJ
8
0 _ Bus \\\\\\\\\\\\\\\\\\\\\\\\\SW~\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\~ ~
PC 8-15 PC 0-7 FIrst

.I:>-
BA i\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\~~\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ (f 'n"'uetlan rt
m
-" ~ = Indeterminate

FIGURE 9 - INTERRUPT TIMING

Cycle
#1 #2 #3 #4 #5 #6 #7 #8 #9 #10 #11 #12 #13 r #14 #15

Address
Bus

IRQ at

-~
'..-.upt

--=~~~~~~-------------=====~======~====~;=====~======~====~r=t=====~~/
~ BUS====~~====~======)(====)(====~<=====:x======)[====~<======x======)[=t====~~~~x=====~<=====:x======)( New PC 8-1SNew PC 0-7 ~Irst Inst of

~===========---I~
Address Address Interrupt Routine

RNi llllllUJ'
VMA ""till.

II ----~----- --- - ._- -

 MC6800. MC68AOO. MC68BOO

The HALT line must be in the high state for Interrupts to time PW</>H Without destroYing data Within the MPU TSC
be serviced. Interrupts will be latched Internally while HALT then can be used In a short Direct Memory Access IDMA)
IS low. application.
The IRO has a high-Impedance pull up device Internal to Figure 12 shows the effect of TSC on the MPU TSC must
the chip; however, a 3 kG external resistor to VCC should be have its transitions at tTSE (three-state enable) while holding
used for wire-OR and optimum control of Interrupts. </>1 high and </>2 low as shown The Address Bus and R/Vi
line will reach the high-Impedance state at tTSD (three-state
Non-Maskable Interrupt (NMII and Wait for Interrupt delay), With VMA being forced low. In this example, the
(WAil - The MC6800 is capable of handling two types of in- Data Bus IS also In the high-Impedance state while </>2 IS be-
terrupts. maskable IIRO) as described earlier, and non- Ing held low Since DBE=</>2. At thiS pOint In time, a DMA
maskable (NMIl which IS an edge sensitive Input. IRO IS transfer could occur on cycles #3 and #4. When TSC IS
maskable by the Interrupt mask In the condition code register returned low, the MPU Address and R/W lines return to the
while NMlls not maskable The handling of these Interrupts bus. Because It is too late m cycle #5 to access memory, thiS
by the M PU IS the same except that each has ItS own vector cycle IS dead and used for synchronization Program execu-
address The behaVior of the MPU when Interrupted IS tion resumes in cycle #6
shown In Figure 9 which details the MPU response to an in-
terrupt while the MPU IS executing the control program The Valid Memory Address (VMA) ~ ThiS output ,ndicates to
Interrupt shown could be either IRO or NMI and can be asyn- peripheral deVices that there IS a valid address on the address
chronous with respect to </>2 The Interrupt 'IS shown gOing bus. In normal operation, thiS signal should be utilized for
low at time tpcs In cycle #1 which precedes the first cycle of enabling peripheral mterfaces such a~ the PIA and ACIA
an Instruction (OP code fetch). ThiS Instruction IS not ex- This signal IS not three-state. One standard TTL load and
ecuted but Instead the Program Counter !PC), Index 90 pF may be directly driven by thiS active high signal.

•
Register (IX), Accumulators (ACCX), and the ConditIOn
Code Register (CCR) are pushed onto the stack. HALT - When thiS level senSitive Input IS In the low state,
The Interrupt Mask bit IS set to prevent further mterrupts. all activity In the machine Will be halted This Input is level
The address of the Interrupt service routine IS then fetched senSitive.
from FFFC, FFFD for an NMllnterrupt and from FFF8, FFF9 The HALT line proVides an Input to the MPU to allow con-
for an IRO Interrupt. Upon completion of the Interrupt ser- trol of program execution by an outSide source. If HALT IS
vice routine, the execution of RTI Will pull the PC, IX, ACCX, high, the MPU will execute the Instructions, If It is low, the
and CCR off the stack; the Interrupt Mask bit IS restored to MPU Will go to a halted or Idle mode. A response Signal, Bus
Its condition prior to Interrupts (see Figure 10) Available (BA) proVides an indication of the current MPU
Figure 11 IS a Similar interrupt sequence, except In thiS status. When BA IS low, the MPU IS In the process of ex-
case, a WAIT instruction has been executed In preparatIOn ecuting the control program; If BA IS high, the MPU has
for the Interrupt. ThiS technique speeds up the MPU's halted and all Internal activity has stopped
response to the interrupt because the stacking of the PC, IX, When BA IS high, the Address Bus, Data Bus, and R/W
ACCX, and the CCR IS already done While the MPU IS line will be In a high-impedance state, effectively removing
waiting for the Interrupt, Bus Available Will go high In- the MPU from the system bus VMA IS forced low so that the
dicating the follOWing states of the control lines VMA IS low, floating system bus will not activate any device on the bus
and the Address Bus, R/W and Data Bus are all In the high that IS enabled by VMA.
Impedance state. After the Interrupt occurs, It IS serviced as While the MPU IS halted, all program activity IS stopped,
previously described. and If either an NMI or IRO interrupt occurs, It Will be latched
A 3-10 kG external resistor to V CC should be used for wlre- into the MPU and acted on as soon as the MPU IS taken out
OR and optimum control of Interrupts. of the halted mode. If a RESET command occurs while the
MPU IS halted', the follOWing states occur' VMA= low,
MEMORY MAP FOR INTERRUPT VECTORS BA=low, Data Bus=hlgh Impedance, R/W=hlgh (read
state), and the Address Bus Will contain address FFFE as
Vector long as RESET IS low As soon as the RESET line goes high,
Description
MS LS the MPU Will go to locations FFFE and FFFF for the address
FFFE FFFF Reset of the reset routine
FFFC FFFD Non-Maskable Interrupt Figure 13 shows the timing relationships Involved when
FFFA FFFB Software Interrupt halting the MPU. The Instruction Illustrated is a one byte, 2
FFF8 FFF9 Interrupt Request cycle Instruction such as CLRA. When HALT goes low, the
Refer to Figure 10 for program flow for Interrupts
MPU will halt after completing execution of the current in-
struction. The transition of HALT'must occur tpcs before
Three-State Control (TSC) - When the level sensitive the trailing edge of </>1 of the last cycle of an Instruction
Three-State Control (TSC) line IS a logiC "1", the Address (point A of Figure 13). HALT must not go low any time later
Bus and the R/W line are placed In a high-impedance state. than the minmum tpcs speCified
VMA and BA are forced low when TSC= "1" to prevent The fetch of the OP code by the MPU IS the first cycle of
false reads or writes on any deVice enabled by VMA. It IS the instruction. If HALf had not been low at POint A but
necessary to delay program execution while TSC IS held went low dUring </>2 of that cycle, the MPU would have
high. This IS done by inSUring that no transitions of </>1 (or </>2) halted after completion of the follOWing Instruction. BA Will
occur during this period. (Logic levels of the clocks are Ifrele- go high by time tBA (bus available delay time) after the last
vant so long as they do not change!. Since the MPU is a instruction cycle. At thiS pOint in time, VMA IS low and R/Vii,
dynamic deVice, the</> 1 clock can be stopped for a maximum Address Bus, and the Data Bus are In the high-Impedance
state.

4-62
MC6800- MC68AOO-MC68BOO

To debug programs It IS advantageous to step through lines are back on the bus. A single byte, 2 cycle Instruction
programs instruction by instruction. To do thiS, HALT must such as LSR IS used for thiS example also. DUring the first cy-
be brought high for one MPU cycle and then returned low as cle, the Instruction Y IS fetched from address M + 1. BA
shown at POint B of Figure 13 Again, the transitions of returns high at tBA on the last cycle of the Instruction In-
HALT must occur tpes before the trailing edge of <1>1 BA dicating the MPU IS off the bus. If instruction Y had been
will go low at tBA after the leading edge of the neyt <1>1, in- three cycles, the width of the BA low time would have been
dicating that the Address Bus, Data Bus, VMA and R/Vii Increased by one cycle

FIGURE 10 - MPU FLOW CHART

Notes
1 Reset IS recognized at any pOSition In the flowchart
2 Instructions which affect the I-Bit act upon 8 one-blt buffer reglSter.
"ITMP" ThiS has tho effect of delaying any CLEARING of tho I-Bit one
clock. time. Setting the I-Bit. however. IS not delayed
3. See Tables 6-11 for details of Instruction Execution

4·63
 FIGURE 11 - WAIT INSTRUCTION TIMING
• s:
~•
Cycle
#1 #2 #3 #4 #5 #6 #7 #6 #9 #10 1 n+1 1 n+21 n+31 n+4In+51
r
4>2
s:
n

~s:•
Address
Bus

RM

VMA

~OJ
Interrupt
Mask First Inst
of Interrupt
IROor Routine
Niiiii
Data Bus 8
Wait
Inst
PC 0-7 PC 8-15 10-7 18-15 ACCA ACCB CCR
Address Address
BA

Note Midrange waveform indicates

high impedance state.

"""
m
"""
FIGURE 12 - THREE-STATE CONTROL TIMING

Cycle
#1 "2 #3 ~4 ~5 ~6 ~7 '-8

System
""
(p1

MPU (/11

Address~~===tt=~--~~----~~---tt-i=====x======>~====)(======x======>c=
Bus _

Fl/W

VMA
...f\ II 'f II r
~~:a ---X1U II (
(:>2= DBE

TSC I

~t--tTSE tTSE I-+-

MC6800. MC68AOO. MC68BOO

FIGURE 13 - HALT AND SINGLE INSTRUCTION EXECUTION FOR SYSTEM DEBUG

</>1

</>2

SA ' ' -_ _ _ _ _- . . . I r
VMA ~---,L----------1{:t- _____-1/ c=:=\
R/W ~--------ill~-----_/
Fetch Execute
'<'---~~>-
~~:ress _..J~~~!x'J..__~>----------j/.--------C< Addr X,____..) -

..
1M +1

Bus _
Data -=====:X==)(====)C==~---------1~----------<
Inst
X
Inst
y

Note" Midrange waveform Indicates

high Impedance state.

MPU REGISTERS

The MPU has three 16-blt registers and three 8-bit FIGURE 14 - PROGRAMMING MODEL OF
registers available for use by the programmer (Figure 14) THE MICROPROCESSING UNIT

Program Counter - The program counter IS a two byte

(16 bits) register that POints to the current program address.
I Accumulator A
Stack Pointer - The stack ponter IS a two byte register ';------~o
that contains the address of the next available location In an
external push-down/pop-up stack This stack IS normally a
random access Read/Wnte memory that may have any loca-
tion (address) that IS convenient. In those applications that
require storage of information in the stack when power is
lost, the stack must be nonvolatile.

Index Register - The Index register IS a two byte register

that IS used to store data or a sixteen bit memory address for '-I______-:-______~I Stack Pointer
the Indexed mode of memory addressing
Condition Code
Accumulators - The MPU contains two 8-blt ac- ~'-'r'-r'-r'-t..,...,... Register
cumulators that are used to hold operands and results from
an anthmetlc logiC Unit (ALUI. Carry (From Bit 7)

Overflow
Condition Code Register - The condition code register In- Z.ro
dicates the results of an Anthmetlc LogiC Unit operation:
Negative
Negative (N), Zero (Z), Overflow (V), Carry from bit 7 (C),
and half carry from bit 3 (HI. These bits of the Condition Interrupt

Code Register are used as testable conditions for the condi- " - - - - - - Half Carry (From Bit 3)
tional branch Instructions. Bit 4 is the Interrupt mask bit (Il.
The unused bits of the Condition Code Register (b6 and b7)
are ones.

4·65
 MC~MC~AOO·MC~BOO

MPU INSTRUCTION SET

The MC6800 Instructions are described In detail In the When an instruction translates Into two or three bytes of
M6800 Programming Manual. ThiS Section will provide a code, the second byte, or the second and third bytes con-
brief Introduction and discuss their use In developing taln(s) an operand, an address, or Information from which an
MC6800 control programs. The MC6800 has a set of 72 dif- address IS obtained dUring execution
ferent executable source Instructions. Included are binary Microprocessor Instructions are often diVided Into three
and deCimal arithmetic, logical, Shift, rotate, load, store, general claSSifications. (1) memory reference, so called
conditional or unconditional branch, Interrupt and stack because they operate on specific memory locations; (2)
mampulation instructions. operating Instructions that function without needing a
Each of the 72 executable Instructions of the source memory reference; (3) I/O instructions for transferring data
language assembles into 1 to 3 bytes of machine code. The between the microprocessor and peripheral deVices.
number of bytes depends on the particular Instruction and In many instances, the MC6800 performs the same opera-
on the addressing mode. (The addressing modes which are tion on both ItS Internal accumulators and the external
available for use With the various executive instructions are memory locations. In additIOn, the MC6800 Interface
discussed later) adapters (PIA and ACIA) allow the MPU to treat peripheral
The coding of the first (or only) byte corresponding to an deVices exactly like other memory locations, hence, no I/O
executable Instruction IS sufficient to identify the instruction Instructions as such are reqUired Because of these features,
and the addreSSing mode. The hexadecimal eqUivalents of other claSSifications are more sUitable for introdUCing the
the binary codes, which result from the translation of the 72 MC6800's instructIOn set· (1) Accumulator and memory
instructions In all valid modes of addreSSing, are shown In operatIOns; (2) Program control operations, (3) Condition
Table 1 There are 197 valid machine codes, 59 of the 256 Code Register operations.
possible codes being unassigned

TABLE 1 - HEXADECIMAL VALUES OF MACHINE CODES

• 00
01
02
03
04
05
06
07
08
09
OA
OB
oc
00
NOP

TAP
TPA
INX
DEX
CLV
SEV
CLC
SEC
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
NEG

COM
LSR

ROR
ASR
ASL
ROL
DEC

INC
TST
A

A
A

A
A
A
A
A

A
A
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
80
SUB
CMP
SBC

AND
BIT
LOA

EOR
ADC
ORA
ADD
CPX
BSR
A
A
A

A
A
A

A
A
A
A
A
IMM
IMM
IMM

IMM
IMM
IMM

IMM
IMM
IMM
IMM
IMM
REL
CO
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
SUB
CMP
SBC

AND
BIT
LOA

EOR
ADC
ORA
ADD
B
B
B

B
B
B

B
B
B
B
IMM
IMM
IMM

IMM
IMM
IMM

IMM
IMM
IMM
IMM
Notes 1 AddreSSing Modes
A
B
REl
INO
IMM
= Accumulator A
=
=
=
Accumulator B
Relative
Indexed
= Immediate
OE CLI OIR = Olrect
4E 8E LOS IMM CE LOX IMM
OF SEI 4F CLR A 8F CF
10 SBA 50 NEG B 90 SUB A DIR DO SUB B DIR
11 CSA 51 91 CMP A DIR 01
2 Unassigned code Indicated by " • " •
CMP B DIR
12 52 92 sec A DIR 02 SBC B DIR
13 53 COM B 93 03
14 54 LSR B 94 AND A DIR D4 AND B DIR
15 55 95 BIT A DIR 05 BIT B DIR
16 TAB 56 ROR B 96 LOA A DIR 06 LOA B DIR
17 TSA 57 ASR B 97 STA A DIR 07 STA B DIR
18 66 ASL B 98 EOR A DIR DB EOR B DIR
19 DAA 59 ROL B 99 ADC A DIR 09 ADC B DIR
1A 5A DEC B 9A ORA A DIR DA ORA B DIR
1B ABA 58 9B ADD A DIR DB ADD B DIR
1C 50 INC B 9C CPX DIR DC
10 50 TST B 90 DO
1E 5E 9E LOS DIR DE LOX DIR
1F 5F CLR B 9F STS DIR OF STX DIR
20 BRA REL 60 NEG IND AO SUB A IND EO SUB B IND
21 81 A1 CMP A IND E1 CMP S IND
22 SHI REL 62 A2 sec A IND E2 sec B IND
23 BLS REL 63 COM IND A3 E3
24 Bec REL 64 LSR IND A4 AND A IND E4 AND B IND
25 BCS REL 65 AS BIT A IND E5 BIT B IND
26 BNE REL 66 ROR IND A6 LOA A IND E6 LOA B IND
27 BEO REL 87 ASR IND A7 STA A IND E7 STA B IND
28 BVC' REL 66 ASL IND AS EOR A IND E8 EOR B IND
29 BVS REL 69 ROL IND A9 ADC A IND E9 ADC B IND
2A BPL REL 6A DEC IND AA ORA A IND EA ORA B IND
2B BMI REL 6B AB ADD A IND EB
2C
20
BGE
BLT
REL
REL
6C
60
INC
TST
IND
IND
AC
AD
CPX
JSR
IND
IND
EC
ED
ADD
" IND

2E BGT REL 6E JMP IND AE LOS IND EE LOX IND

2F BlE REL 6F CLR IND AF STS IND EF STX IND
30 TSX 70 NEG EXT eo SUB A EXT FO SUB B EXT
31 INS 71 B1 CMP A EXT F1 CMP B EXT
32 PUL A 72 B2 sec A EXT F2 sec B EXT
33 PUL B 73 COM EXT B3 F3
34 DES 74 LSR EXT B4 AND A EXT F4 AND B EXT
35 TXS 75 B6 BIT A EXT F5 BIT B EXT
36 PSH A 76 ROR EXT B6 LOA A EXT F6 LOA B EXT
37 PSH B 77 ASR EXT B7 STA A EXT F7 STA B EXT
38 78 ASL EXT B8 EOR A EXT F8 EOR B EXT
39 RTS 79 ROL EXT B9 ADC A EXT F9 ADe B EXT
3A 7A DEC EXT SA ORA A EXT FA ORA B EXT
3B RTI 7B BB ADD A EXT FB ADO B EXT
3C 7C INC EXT BC CPX EXT FC
3D 70 TST EXT BD JSR EXT FD
3E WAI 7E JMP EXT BE LOS EXT FE LOX EXT
3F SWI 7F CLR EXT BF STS EXT FF STX EXT

4·66
MC6800. MC68AOO· MC68BOO

TABLE 2 - ACCUMULATOR AND MEMORY OPERATIONS

ADDRESSING MODES BOOLEAN/ARITHMETIC OPERATION CONO CODE REG
IMMED DIRECT INDEX EXTNO IMPllED {All register labels , • 3 2
1 0
OPERATIONS MNEMONIC OP = OP - = OP - =
,,
OP - = OP - = refer to tOnlents! H I N Z V C
Add AQOA 3B 2 2 9B 3 2 AB 2 B8
•• 3 A ~ M 'A I

,,
I I I 1
··,, , ,,, ,,
·
ADOS CB 2 2 DB 3 2 EB 2 F6 3 B + M -8 I I
Add Acmllrs ABA
,, 16 2 1 :

··.·.·,,, ,, ·
A + B 'A
Add with Carr~ AOCA B9 2 2 99 3 2 A' 2 B9
•• 3 A + M + C 'A t I
AQeS CO 2 2 09 3 2 E9
,, 2 F9 3 B + M + C •B I I I I

" •
And ANDA 84 2 2 94 3 2 A4 2 3 A M -A R •

BII Tesl

Clear
ANOS
BITA
BITS
CLA
C4
85
C5
2
2
2
2
2
2
D'

"
05
3
3
3
2
2
2
E4
A'
E5
7
,, 2
2
2
F4
B5
F5
••
4

6
3
3
3
3
B'M -8
A- M
B M
00 • M
··.. , I I R

I
A •
A •

ClAA " 2 7F
4F 2 1 00 'A
• • A S A A
A S A A

··..,, ,, ,
• •

Compare
CLRB
CMPA 81 2 2 91 3 2 AI ,, 2 B1 • 3
Sf 2 1 00 '8
A M
• • A S A R
I I I

Compare Acmllr!
CMPB
CBA
C1 2 2 01 3 2 E1 2 F1
• 3
11 2 1
8· M
A 8
··.., , I I I
I
Complelnenl, ,'s COM
COMA
COMB
63 7 2 73 6 3
43
53
2
2
1
1
M -M
~ -'A
Ii ~ B ···..., ,
I I A S
I A S
A S

CIlmpiement,2's
iNegatel
NEG
NEGA
60 7 2 70 6 3
40 2 1
00 - M 'M
00 - A -A I
··..,
,<D(z)
1<D(z)
Oetlmai Adjust, A
NEGB
DAA
50
19
2
2
1
1
00 B -8
Con~er1s Blnarv Add of BCD Characters I
·.
1<D(z)
I 1(3)

Decrement DEC
InlO BCD Format

··..,,, ,, ··
···... , , ·
6A 7 2 7A 6 3 M - 1 ·M 4
CECA 4A 2 1 A -l-'A I 4
DECa 5A 2 1 8-1-8 4 •

,
··.., , ..
ExclUSIVe OR EORA 2 A8 5 2 3 A®M~A
" 2 9B J 2 8B 4 I A

•
EORB CB 2 2 DB J 2 EB 2 FB 4 3 B(!)M·... S
Increment INC 6C 7 2 7C 6 3 M + ' ...... M I If

···..., ,,,
INCA de 2 1 A+ 1 ·A :
INCB 5C 2 1 8' 1 -B I ,@.
lead Acmltr LDAA B6 2 2 96 J 2 A6 5 2 B6 4 3 M-A I A •

Or, InclusIVe
LOAS
DRAA
C6
8A
2
2
2
2
06
9A
J
3
2 E6
2 AA
5
5
2 F6
2 8A
4
4
3
3
M 'B
A+ M .... A
··..·...
! A •

,
A •
DRAB CA 2 2 DA 3 2 EA 5 2 FA 4 3 B +M ...... a

···...··...
I A •

···...·,, ...
Push Data PSHA J6 4 1 A--- MSP,SP-l-->SP

...
PSHB 37 4 1 B-->MSP,SP-l-->SP
Pull Data PULA 32 4 1 SP+ l .... SP. MSp--> A
PULa 33 4 1 Sp+' .... SP.MSp-->B

~} LD - CIII!IIIJ:J
Rolale left AOL 69 7 2 7S 6 3 ! 6 I
ROlA
ROlB
49
59
2
2
1
1 B C b7 - bD
··.. ,, :~:
!
Rotale Righi AOA
RORA
RORB
66 7 2 16 6 3
46
56
2
2
1
1
~} COC
8
- iIIIIIII}:J
bJ - bO I
···...
I@,

! !
Shih left, Anthmeht ASL
ASlA
68 7 2 78 6 3
48 2 1
n 0- = - 0
- I
I
··..
I ,
II'
I 1

···...
ASlB 2 1 C b7 bO , !
" I

~} I~',
Shih RighI, ArithmetiC ASA 6/ 7 2 )) 6 3 !
ASRA 47 2 1 ctrnTI:rn - 0 I I

'f
ASRB 2 1 B b1 bO C !
"
n -
Shift Right, Lagle LSA 64 7 2 74 6 3 , !
• • A
LSRA 44 2 1 o-aIIIIDJ - 0 • • A I !

Store Acmltr
lSRB
STAA 97 4 2 A7 6 2 Bl ,, 3
54 2 1
A-M
bJ bO C
• •
• •
A !
I
I I A •
STAB 07 4 2 El 6 2 f) 3 8-M ! A •

···...,
• • I
Subtract SUBA
SUBS
80
CO
2
2
2
2
80
00
3
3
2
2
AD
eo ,
5 2
2
BD
Fa
4
4
3
3
A-M . . . A
B-M ..... a
• • ! ! I I
! ! !
Subtract Acmltrs SBA ID 2 1 A-S .... A ! ! ! !

···... ,
Subtr With Carry SBeA B2 2 2 92 3 2 A2 5 2 B2 4 3 A-M-C .... A I ! I I
seCB C2 2 2 02 J 2 E2 5 2 F2 4 3 B - M - C---B I I I !
Tran5fer Acmltrs TAB 16 2 1 A-8 I I A •

Test, Zero or MinUS

TBA
TST 60 7 2 70 6 3
17 2 1 8-A
M -00
··.. ! I
I
A
A
•
A
TSlA
TS16
40
'0
2
2
1
1
A-DO
B - 00
·. ! I
I I
H I N Z V C
A
A
A
A

LEGEND CONDITION CODE SYMBOLS CONDITION CODE REGISTER NOTES:

OP Operation Code (Hexadlclmall, (Sit set It test IS true and cleared otherwlse~
Number of MPU Cycles, Half carry from bit 3,
(Bit VI Test Result'" 100000001
# Number of Program Bytes, Interrupt mask
AnthmatlcPlus, Negative (sign bit)
(Bit CI Test Result'" OOOOOOOO?
Arithmetic Minus, Zero (byte) (Bit C) Test DeCimal value of most slgmflcant BCD
Boolean AND, Overflow, 2's tompl~m'nt Character greater than mne?
MSp Contents of memory IDeatiOn pOinted to be Stack POinter, Carryfromblt7 (Not cleared If preVIOUsly set)
Boolean InclUSive OR, Reset Always (Bit VI Test Operand'" 10000000 prior to execution?
e Boolean ExclUSive OR, Set Always (Bit VI Test Operand = 01111111 prIOr to execution?
Complement of M, Test and set If true, cleared otherWise (Bit V) Test Set equal to result of NC±>C after shift has occurred
Transfer Into, Not Affected
OBit" Zero,
00 Byte" Zero,

Nore - Accumulator addreSSing mode instructions are Included In the column for IMPLIED addreSSing

4-67
 MC6800-MC68AOO-MC68BOO

PROGRAM CONTROL OPERATIONS

Program Control operation can be subdivided into two Stack POinter IS automatically Incremented by one Just prior
categories' (1) Index Register/Stack POinter Instructions, (2) to the data transfer so that It Will pOint to the last byte stack-
Jump and Br~~ch' operations. ed rather than the next empty location Note that the PULL
Instruction does not "remove" the data from memory, In the
Index Register/Stack,Pointer Operations example, 1A IS still In location (m+ 1) follOWing execution of
The instructions for direct operation on the MPU's Index PULA. A subsequent PUSH Instruction would overwrite that
Register and Stack POinter are summarized In Table 3. location With the new "pushed" <jata
Decrement (DEX, DES), Increment IINX, INS), load ILDX, Execution of the Branch to Subroutine (BSR) and Jump to
LDS); and store (STX, STS) instructions are provided for Subroutine (JSR) instructions cause a return address to be
both 'The Compare InstruqtlOn, CPX, can be used to com- saved on the stack as shown In Figures 18 through 20 The
pare the Index Regl,ster to Ii 16-blt value and ~pdate the Con- stack IS decremented after each byte of the return address IS
dition Code Register accbrdlngly pushed onto the stack For both of these InstrUctIOns, the
The TSX Instruction causes the Index Register to be load- return address IS the memory location follOWing the bytes of
ed with the address of the last data byte put onto the code that correspond to the BSR and JSR Instruction. The
"stack" The TXS instruction loads the Stack POinter with a code reqUired for BSR or JSR may be either two or three
value equal tb one less than the current contents of the Index bytes, depending on whether the JSR IS In the Indexed (two
Register ThiS causes, the next byte to be pulled from the bytes) or the extended (three bytes) addreSSing mode
"stack" to come from the location indicated by the Index Before It IS stacked, the Program Counter IS automatically in-
, Register. The utility of these two Instructions can be clarified cremented the correct number of times to be pOinting at the
by describing the "stack" concept relative to the M6800 location of the next Instruction The Return from Subroutine

•
system Instruction, RTS, causes the return address to be retrieved
The "stack" can be thought of as a sequential list of data and loaded Into the Program Counter as shown In Figure 21.
stored In the MPU's read/write memory. The Stack POinter There are several operations that cause the status of the
contains a 16-blt memory address that IS used to access the MPU to be saved on the stack. The Software Interrupt (SWIl
list from one end on a last-In-flrst-out (LIFO) baSIS In contrast and Walt for Interrupt (WAil InstructIOns as well as the
to the random access mode used by the MPU's other ad- maskable (IRQ) and non-maskable (NMi) hardware inter-
dreSSing modes' rupts all cause the MPU's Internal registers (except for the
The MC6800 Instruction set and Interrupt structure allow Stack POinter Itself) to be stacked as shown In Figure 23
extensive use of the stack concept for effiCient handling of MPU status IS restored by the Return from Interrupt, RTI, as
data movement, subroutines and Interrupts. The instructions shown In Figure 22
can be used to establish one or more "stacks" anywhere In
read/write memory Stack length IS limited only by the Jump and Branch Operation
amount of memory that IS made available. The Jump and Branch instructions are summarized In
Operation of the Stack POinter with the Push and Pull in- Table 4. These Instructions are used to control the transfer or
structions IS Illustrated In Figures 15 and 16 The Push In- operation from one pOint to another In the control program
structIOn (PSHA) causes the contents of the Indicated ac- The No Operation InstruCtIOn, NOP, while Included here,
cumulator IA In thiS example) to be stored In memory at the IS a Jump operation In a very limited sense Its only effect IS to
location Indicated by the Stack POinter The Stack POinter IS Increment the Program Counter by one. It IS useful dUring
automatically decremented by one follOWing the storage program development as a "stand-In" for some other In-
operation and IS "pointing" to the next empty stack location struction that IS to be determined dUring debug It IS also us-
The Pull instructIOn IPULA or PULB) causes the last byte ed for equaliZing the execution time through alternate paths
stacked to be loaded Into the appropriate accumulator The In a control program

TABLE 3 - INDEX REGISTER AND STACK POINTER INSTRUCTIONS

CONO CODE REG
IMMED DIRECT INDEX EXTND IMPLlEO 5 4 3 2 1 0

- " - " - - -
POINTER OPERATIONS
Co~pafe Index Reg
Decrement Index Reg
MNEMONIC
CPX
DEX
OP
BC 3 3
OP
9C 4 2
DP
AC 6
"2 OP
BC 5
= OP
3
P9 4
=

I
BOOlEAN/ARITHMET)C OPERATION
XH - M. Xl - 1M + 1)
X -I-X
···...·.··..
H I N Z V C
CD: 2 •

··• ..• ·.··..

• 1
Decrement Stack Potr DES 34 4 I SP - I -SP
Increment Index Reg INX OB 4 I X + 1 ...... X
• !
Increment Stack Pntr INS 31 4 I SP + 1 ..... SP
load Index Reg
load Stack Pntr
lOX•• CE
BE
3
3
3
3
DE
9E
4 2 EE
2 AE
6
6
2 FE
2 BE
5
5
3 M-XH,(M+ll-~Xl
M-SPH.IM+II-SPl
··..
Q)!
Q):
R
R
•
•

··..·.·• .•
lOS 4 3
Store Index Reg STX ·DF 5 2 EF 7 2 FF 6 3 XH-M.Xl-IM+1/ Q): R •
Store Stack Potr STS 9F 2 AF 7 2 BF 6 SPH-M.SPl-IM+ II Q): R •

·.·.
5 3
Indx Reg ..... Stack Pntr TXS 35 X-I -SP
Stack Pntr-+lndlC Reg TSX 3U
.4 1 '1 SP+ 1 'X

<D(SIt N) Test Sign bit of most Significant (MS) byte of result = 11

® (Bit V) Test 2's complement overflow from SUbtraction of ms bytes'?
~ (SIt N) Test Result less than :taro? (Sit 15 = 1)

4·68
MC6800-MC68AOO-MC68BOO

FIGURE 15 - STACK OPERATION, PUSH INSTRUCTION

MPU MPU

ACCA ACCA

~
m - 2 m - 2

m -1

SP --+0. m

7F
.
3
":;
o
New Data F3

7F
PrevIously
Stacked J::: 63
Previously '
mm++2
63

1
Stacked (
Data Data
m +3 FO m +3 FO

3C 3C

PC _ _
PSHA

Next Instr,

(a) Before PSHA

PC--
PSHA

Next Instr.

(b) After PSHA

•
FIGURE 16 - STACK OPERATION, PULL INSTRUCTION
MPU MPU

ACCA ACCA

m - 2 m - 2

m -1 m -1

J:: ~
1A SP -+- m +1 1A
Previously
Stacked 3C
J 3C
Data
1 m +3 05
PrevlouslV
Stacked
Data 1
m

m
+2

+3
05

PC-+- PULA PULA

Next lostr. PC Next Instr.

(a) Before PU LA (b) After PULA

4-69
 MC6800e MC68AOOe MC68BOO

TABLE 4 - JUMP AND BRANCH INSTRUCTIONS

CONO CODE REG
RELATIVE INDEX EXTNO IMPLIED 5 4 3 2 I 0
OPERATIONS
Branch Always
MNEMONIC
BRA
OP
20
-
4
#
2
OP - # OP - # OP - #
None
BRANCH TEST H
0
I
0
N
0
Z
0
V
0
C
0
Branch If Carry Clear Bee 24 4 2 e"o 0 0 0 0 0 0
Branch If Carry Set BCS 25 4 2 C= 1 0 0 0 0 0 0
Branch If =Zero BED 27 4 2 Z" I 0 0 0 0 0 0
Branch If;;;;' Zero BGE 2C 4 2 N (j) V" 0 0 0 0 0 0 0
Branch If > Zero BGT 2E 4 2 Z+IN(j)VI"O 0 0 0 0 0 0
Branch It Higher BHI 22 4 2 C+2=0 0 0 0 0 0 0
Branch If ~ Zero BLE 2F 4 2 Z + (N (f) VI '" 1 0 0 0 0 0 0
Branch If lower Or Same BLS 23 4 2 C+Z=l 0 0 0 0 0 0
< Zero

. .
Branch If BLT 20 4 2 N@V=l 0 0 0 0 0 0
Branch If Minus BMI 2B 4 2 N" 1 0 0 0 0 0 0
Blanch If Not Equal Zero BNE 26 4 2 ZoO 0 0 0 0 0
Branch If Overflow Clear BVe 2B 4 2 v=o 0 0 0 0 0

·.
Branch If Overflow Set BVS 29 4 2 V"l 0 0 0 0 0 0
Branch If Plus BPL 2A 4 2 N"O 0 0 0 0 0 0
Branch To Subroutine BSR 80 8 2 0 0 0 0

}
·· .. ..CD--
..!.. ..
Jump JMP 6E 4 2 7E 3 3 See SpecIal Operations 0 0 0 0 0 0
Jump To Subroutme JSR AD 8 2 BO 9 3
No Operation NOP 01 2 1 Advances Prog Cntr Only
Return From Interrupt RTI 3B 10 1 ---

•
Return From Subroutrne RTS 39 5 1
Software Interrupt
Walt for Interrupt*
SWI
WAI
3F
3E
12
9
1
1
} See SpeCial Operations •• ®-)j.• •• •• ••
01°':1-
0
1
0
1
0

WAr puts Address Bus, Rm, and Data Bus In the three-state mode while VMA IS held low

<D (All) Load Condition Code Register from Stack (See SpeCial Operations)
® (Bit 1) Set when Interrupt occurs. If preViously set, a Non-Maskable Interrupt
IS required to exit the walt state

Execution of the Jump Instruction, JMP, and Branch cle faster than JSR, The Return from Subroutine, RTS, IS
, Always, BRA, affects program flow as shown In Figure 17, used as the end of a subroutine to return to the main pro-
When the MPU encounters the Jump Iindexediinstructlon, gram as indicated In Figure 21,
It adds the offset to the value In the Index Register and uses The effect of executing the Software Interrupt, SWI. and
the result as the address of the next Instruction to be ex- the Wait for Interrupt, WAI, and their relationship to the
ecuted, In the extended addreSSing mode, the address of the hardware Interrupts IS shown In Figure 22 SWI causes the
next Instruction to be executed IS fetched from the two loca- MPU contents to be stacked and then fetches the starting
tions Immediately following the JMP instruction, The Branch address of the Interrupt routine from the memory locations
Always IBRAllnstructlon IS Similar to the JMP lextendedlln- that respond to the addresses FFFA and FFFB Note that as
structlon except that the relative addreSSing mode applies In the case of the subroutine instructions, the Program
and the branch IS limited to the range within - 125 or + 127 Counter IS Incremented to pOint at the correct return address
bytes of the branch Instruction Itself, The opcode for the before being stacked, The Return from Interrupt instruction,
BRA instruction requires one less byte than JMP lextended) RTI, IFlgure 22) IS used at the end of an Interrupt routine to
but takes one more cycle to execute restore control to the main program The SWI Instruction IS
The effect on program flow for the Jump to Subroutine useful for inserting break pOints In the control program, that
IJSRI and Branch to Subroutine IBSRI IS shown In Figures IS, It can be used to stop operation and put the MPU
18 through 20 Note that the Program Counter IS properly In- registers In memory where they can be examined The WAI
cremented to be pOinting at the correct return address Instruction IS used to decrease the time reqUired to service a
before It is stacked Operation of the Branch to Subroutine hardware Interrupt, It stacks the MPU contents ,and then
and Jump to Subroutine lextendedllnstructlon IS Similar ex- walts for the Interrupt to occur, effectively removing the
cept for the range The BSR Instruction reqUires less opcode stacking time from a hardware Interrupt sequence,
than JS R 12 bytes versus 3 bytesl and a1so executes one cy-

FIGURE 17 - PROGRAM FLOW FOR JUMP AND BRANCH INSTRUCTIONS

PC Main Program
Main Program

n+~
PC
lE= JMP

n+~
KH = Next Address
{ n+1
INDXD EXTND { n+2 KL = Next Address

X+K Next Instruction In+21±K L -_

Next Instruction
_ _- - '
K Next InstructIon

"K= Signed 7-blt value

lal Jump Ibl Branch

4-70
MC6800-MC68AOO- MC68BOO

SP--" m
m -2

m-l
,--
--- FIGURE 18 - PROGRAM FLOW FOR BSR

SP-"'m-2

m-l (n

(n
-
+ 2)H

+ 2}L

m+ 1 7E m+l 7E

PC -----.. n
L...---
7A

BSR
---- - BSR

n +1 ±K = Offset· n +1 ±K'" Offset

n+2 Next Main Instr. n+2 Next Main Instr.

L---

•
-
·K =Signed 7-Bit Value PC""(n+2}±K 1st Subr. Instr.

(8) Befor. Execution (b) After Execution

-- --
FIGURE 19 - PROGRAM FLOW FOR JSR (EXTENDED) FIGURE 20 - PROGRAM FLOW FOR JSR (INDEXED)

m -3 m -2 sp-+-m - 2
m -2 SP--...m-2
m-, m-l (n + 2)H

m -, m-' r - - +- - - i In 31H SP---.. m (n + 21L

SP---'m In + 3)L m+ , 7' m + 1 7'

m+ 1

m+2
7'

7A
m+ 1

m +2
7.
7A
7A

---- 7A
-

pc~n

n + ,
'---
70

-
JSFI = BD

SH = Subr. Addr. n +'

JSA

SH • Sub,. Addr
PC--+- n

n+2
+1
JSR = AD

K "'Offset-

Next Main Inltr

n

n<2
+'
JSR = AD

K - Offset

Next Matn Inur

n +2 SL· Subr. Addr n +2 SL '" Subr. Addr.

-K =8·Blt Unstgned Value PC--...x. + K 1st Subr I nstr
n +3 Next Main Instr. n +3 NeKt Mam Instr

-
(a) Before E XBcutlon ·Contents of Index Aaglster
PC~S 1st Subr. InStf

(e) .for. Execution (b) After Execution

(b) Aftttr Execution

4·71
 MC6800- MC68AOO- MC68BOO

SP~m-2

m -1

m
-
--
FIGURE 21 -

Cn + 3)H

Cn + 3)L
PROGRAM FLOW FOR RTS

SP---+- m
m-2

m-l

+1 7E

---
m + 1 7E m

7A 7A
I..----

JSR = BO JSA = SO

n +1 SH = Subr. Addr. n +1 SH "" Subr. Addr.

n +2 SL = Subr. Addr. n+2 SL = Subr. Addr.

n+3 Next Main Instr. Next Main Instr.

-----
• Last Subr. Instr.

ATS

(a) Before Execution

Last Subr. Instr.

ATS

(b) After Execution

-- ---
FIGURE 22 - PROGRAM FLOW FOR RTI

SP ______ m - 7
m - 7

m -6 CCA m -6 eCR

m - 5 ACCS m - 5 ACeB

m -4 ACCA m -4 ACCA

m - 3 XH (Index Reg) m - 3 XH

m -2 XL (Index Reg) Xl

m -1 PC(n+1)H m -1 PCH
SP _ _
PC(n+1)L PCl

~ ~

n +1 PC- n+ 1

Sn Last Inter. Instr. Last Subr. Instr.

PC_ ATI ATI

(a) Before Execution (b) After ExecutIon

4-72
MC68OQ-MC68AOO- MC68BOO

FIGURE 23 - PROGRAM FLOW FOR INTERRUPTS

Na

c::>
sp- m -7
m-6
m -5
m-4
Stack

Condition Code
Acmltr. B
Acmltr A
I
m -3 Index Register (X H)
m -2 Index RegISter (X I
m-I PCln + IIH
PC(n + IlL

SWI HOWR WAI NMI

INT
Hdwr
Int.
Na Req NMI
Walt Loop

FFFA FFF8 FFFE

FFFB FFF9 FFFF

Interrupt Memory Asslgnment 1

FFFB IRO MS
FFF9 IRO LS
FFFA SWI MS First Instr
FFFB SWI LS r--Joo...... Addr Farmed
MS L..-.y' By Fetching
FFFC NMI 2·Byte. From
FFFO NMI LS Per Mem
FFFE Reset MS Assign.
FFFF Reset LS

NOTE' MS =Mast Slg",'"ant Address Byte.

LS = least Significant Address Byte;

4-73
 MC6800- MC68AOO- MC68BOO

FIGURE 24 - CONDITIONAL BRANCH INSTRUCTIONS for testing relative magnitude when the values being tested
BMI BEQ Z-l are regarded as unsigned binary numbers, that IS, the values
N- 1
BPl BNE are In the range 00 Ilowest) to FF Ihlghest!. BCC follOWing a
N-" Z-"
companson ICMP) Will cause a branch If the lunslgned!
value in the accumulator IS higher than or the same as the
BVC
BVS
V-"
V-I
BCC
BCS
C-"
C-l value of the operand. Conversely, BCS Will cause a branch If
the accumulator value IS lower than the operand
BHI C+Z=¢ BlT NEIlV-l The fifth complementary pair, Branch On Higher IBHII and
BlS C+Z=1 BGE NEIlV-" Branch On lower or Same IBlS! are, In a sense, com-
plements to BCC and BCS. BHI tests for both C and Z=O; If
BlE Z+{NEIlV}-l used follOWing a CMP, It Will cause a branch If the value In
BGT Z+INEIlV}-" the accumulator IS higher than the operand Conversely,
BlS Will cause a branch If the unsigned binary value in the
accumulator is lower than or the same as the operand.
The conditional branch instructions, Figure 24, consists of The remaining two pairs are useful In testing results of
seven pairs of complementary instructions. They are used to operations In which the values are regarded as signed two's

•
test the results of the preceding operation and either con- complement numbers. ThiS differs from the unsigned binary
tinue with the next Instruction In sequence Itest falls) or case In the following sense: In unsigned, the onentatlon IS
cause a branch to another pOInt In the program Itest suc- higher or lower; In signed two's complement, the com-
ceeds!. panson IS between larger or smaller where the range of
Four of the pairs are used for simple tests of status bits N, values IS between -128 and + 127.
Z, V, and C: Branch On less Than Zero IBlT! and Branch On Greater
1. Branch on Minus IBMII and Branch On Plus IBPU tests Than Or Equal Zero IBGE) test the status bits for N E& V = 1
the sign bit, N, to determine If the prevIous result was and NEIlV=O, respectively BlT Will always cause a branch
negative or positive, respectively. follOWing an operation In which two negative numbers were
2. Branch On Equal IBEQ) and Branch On Not Equal added. In addition, It Will cause a branch follOWing a CMP In
IBNE) are used to test the zero status bit, Z, to determine which the value In the accumulator was negative and the
whether or not the result of the previous operation was equal operand was positive. Bl T Will never cause a branch follow-
to zero. These two instructions are useful follOWing a Com- Ing a CMP In which the accumulator value was positive and
pare ICMP) Instruction to test for equality between an ac- the operand negative. BGE, the complement to BlT, Will
cumulator and the operand. They are also used following the cause a branch follOWing operations In which two positive
Bit Test IBIT! to determine whether or not the same bit POSI- values were added or In which the result was zero.
tions are set in an accumulator and the operand. The last pair, Branch On less Than Or Equal Zero IBlE!
3. Branch On Overflow Clear I BVC) and Branch On and Branch On Greater Than Zero IBGT) test the status bits
Overflow Set IBVS) tests the state of the V bit to determine for ZE&IN+V)=1 and ZEIlIN+V!=O, respectively. The ac-
If the prevIous operation caused an arithmetic overflow. tion of BlE is identical to that for BlT except that a branch
4. Branch On Carry Clear IBCC) and Branch On Carry Set will also occur If the result of the prevIous result was zero.
I BCS) tests the state of the C bit to determine If the prevIous Conversely, BGT IS Similar to BGE except that no branch Will
operation caused a carry to occur. BCC and BCS are useful occur following a zero result.

CONDITION CODE REGISTER

OPERATIONS

The Condltton Code Register ICCR) IS a 6-bIt register to precede any SEI Instruction With an odd opcode such
Within the MPU that IS useful In controlling program flow as NOP These precautions are not necessary for MC6800
during system operation The bits are defined In Figure 25. processors Indicating manufacture In November 1977 or
The Instructions shown in Table 5 are available to the user later.
for direct manipulation of the CCR. Svstems which require an Interrupt Window to be opened
A CLI-WAI Instruction sequence operated properly, With under program control should use a CLI-NOP-SEI sequence
early MC6800 processors, only If the preceding Instruction rather than CLI-SEI.
was odd Ileast Significant Blt= 1). Similarly It was adVisable

4-74
MC68OQeMC68AOOe MC68BOO

FIGURE 25 - CONDITION CODE REGISTER BIT DEFINITION

b5 b4 b3 b2 b, bO

IHI N z vlcl
H = Half-carry; set whenever a carry from b3 to b4 of the result IS generated
by ADD, ABA, ADC, cleared If no b3 to b4 carry, not affected by other
Instructions.

Interrupt Mask, set by hardware or software Interrupt or SEI Instruction,

cleared by ell instruction. (Normally not used In arithmetic operations)
Restored to a zero as a result of an RT1 Instruction If Im stored on the
stacked is low

N = Negative, set if high order bit (b7) of result IS set, cleared otherWise.

Z = Zero, set if result = 0, cleared otherwise.

•
= Overlow;set if there wasanthmetic overflow as a result of the operation,
cleared otherwise.

C = Carry, set If there was a carry from the most Significant bit (b7) of the
result; cleared otherWise.

TABLE 5 - CONDITION CODE REGISTER INSTRUCTIONS

CONO CODE REG

~ 5 4 3 2 1 0
OPERATIONS
Cillar Carry
MNEMONIC
Cle
OP
De
-
2
~

1
BOOLEAN OPERATION
o~e
H
0
I
..
N
0 ..
Z V C
R

.
Clear Interrupt Mask CLI DE 2 1 O~I 0 R 0 0 0 0

. ..
Clear Overflow elV OA 2 1 O-V 0 0 0 0 R 0

.--CD--
Set Carry SEe 00 2 1 1-e 0 0 0 0 S
Set Interrupt Mask SEI OF 2 1 1-1 0 S 0 0 0
SetOverflow SEV DB 2 1 1-V 0 0 S
Acmltr A -.-)0 eCR TAP 06 2 I A-.-)oCCR
CGA ...... Acmltr A TPA 07 2 1 eCA A-.-)0 01010101010

R == Reset
S == Set
• '" Not affected
G> (ALL) Set according to the contents of Accumulator A

ADDRESSING MODES
The MPU operates on 8-blt binary numbers presented to It appropriate opcode then depends on the method used. If
via the Data Bus A given number (byte) may represent manual translation IS used, the addreSSing mode IS Inherent
either data or an instruction to be executed, depending on In the opcode For example, the Immediate, Direct, Indexed,
where it IS encountered In the control program. The M6BOO and Extended modes may all be used with the ADD instruc-
has 72 unique Instructions, however, it recognizes and takes tion. The proper mode IS determined by selecting (hex-
action on 197 of the 256 possibliltis that can occur using an adecimal notation) 8B, 9B, AB, or BB, respectively
B-blt word length. ThiS larger number of instructions results The source statement format Includes adequate Informa-
from the fact that many of the executive instructions have tion for the selection If an assembler program is used to
more than one addressing mode. generate the opcode. For Instance, the Immediate mode IS
These addressing modes refer to the manner In which the selected by the Assembler whenever it encounters the" #"
program causes the MPU to obtain its Instructions and data. symbol in the operand field. Similarly, an "X" In the operand
The programmer must have a mothod for addreSSing the field causes the Indexed mode to be selected. Only the
MPU's internal registers and all of the external memory loca- Relative rnode applies to the branch Instructions, therefore,
tions the mnemonic instruction Itself is enough for the Assembler
Selection of the deSired addreSSing mode IS made by the to determine addreSSing mode.
user as the source statements are written. Translation Into

4-75
 MC68QO. MC68AOO· MC68BOO

For the Instructions that use both Direct and Extended "operands" but the space between them and the operator
modes, the Assembler selects the Direct mode If the operand may be omitted. ThiS IS commonly done, resulting In ap-
value IS In the range 0-255 and Extended otherwise. There parent four character mnemonics for those Instructions
are a number of Instructions for which the Extended mode IS The addition instruction, ADD, provides an example of
valid but the Direct IS not For these instructions, the dual addressing In the operand field.
Assembler automatically selects the Extended mode even If
the operand IS In the 0-255 range The addressing modes are Operator Operand Comment
summarized In Figure 26. ADDA MEM12 ADD CONTENTS OF MEM12 TO ACCA
or
Inherent (Includes" Accumulator Addressing" Model ADDB MEM12 ADD CONTENTS OF MEM12 TO ACCB
The successive fields In a sta tement are normally
separated by one or more spaces An exception to thiS rule The example used earlier forthe test InstrUCtion, TST, also
occurs for Instructions that use dual addressing In the applies to the accumulators and uses the "accumulator ad-
operand field and for instructions that must distinguish be- dressing mode" to designate which of the two accumulators
tween the two accumulators In these cases, A and Bare IS being tested'

FIGURE 26 - ADDRESSING MODE SUMMARY

Direct: DO Instruction Immediate: Instruction

Example SUBS Z Example LDAA #K
Addr. Range '" 0-255 n + 1 Z "" Oprnd Address n + 1 K == Operand
(K '" One~8yte Oprnd)

•
& n + 2 Next Instr. n+2 Next Inst.

• OR

• (K == Two-Byte Oprnd)
(CPX, LOX, and LOS)
Instruction

• n + 1 KH '" Operand

(K ;;: One-Byte Oprnd) Z

I K = Operand -.-oJ n + 2 KL ;;: Operand

OR n +3 Next Instr.

(K ::: Two·Byte Oprnd) Z KH == Operand

Z + 1 K L '" Operand
Relative: Instruction

& If Z ~255, Assembler Select Direct Mode Example: BNE K n +1 ±K :: Brnch Offset
If Z >255, !:xtended Mode IS selected
(K "" Signed 7-Bit Value) n + 2 Next I nstr. &
Addr. Range:
-125 to +129 •
Relative to n.
•
Extended: FO Instruction
•
EXample: CMPA Z n+1
In + 21 ±K 1~_N_._xt_ln_._tr_._&
__-'
ZH = Oprnd Addr•••

Addr, Range:
n +2
& If Brnch T.t Fal •• , & If Brnch T.t Tru •.
& 256-65535
Z L = Oprnd Addre••

n +3 Next Inltr,

• Indexed: Inltruction

• Exampla, ADDA Z, X n + 1 Z -= Offset

• Addr. Range:
0-255 Relative to
n+2 Next Instr.

(K = One-Byte Oprnd) Z
I K = Operand

OR
Index Register, X
•
•
(K = Two-Byte Oprnd) Z KH "" Operand
•
Kl = Operand (Z = 8-Blt Unsigned X+Z K =: Operand
Z + 1 Value)

4-76
MC68OQ·MC68AOO·MC68BOO

Operator Comment mode, the "address" of the operand is effectively the

TSTB TEST CONTENTS OF ACCB memory location Immediately follOWing the Instruction Itself
or Table 7 shows the cycle-by-cycie operation for the Im-
TSTA TEST CONTENTS OF ACCA mediate addreSSing mode

A number of the Instructions either alone or together with Direct and Extended Addressing Modes - In the Direct
an accumulator operand contain all of the address Informa- and Extended modes of addressing, the operand field of the
tion that IS required, that IS, "Inherent" In the instruction source statement IS the address of the value that IS to be
Itself For Instance, the Instruction ABA causes the MPU to operated on. The Direct and Extended modes differ only In
add the contents of accmulators A and B together and place the range of memory locations to which they can direct the
the result In accumulator A The Instruction INCB, another MPU. Direct addreSSing generates a Single 8-bit operand
example of "accumulator addressing," causes the contents and, hence, can address only memory locations 0 through
of accumulator B to be Increased by one S:milarly, INX, in- 255; a two byte operand IS generated for Extended address-
crement the Index Register, causes the contents of the Index Ing, enabling the MPU to reach the remaining memory loca-
Register to be Increased by one tions, 256 through 65535. An example of Direct addreSSing
Program flow for instructions of this tipe IS Illustrated In and ItS effect on program flow IS Illustrated In Figure 30
Figures 27 and 28 In these figures, the general case IS shown The MPU, after encountenng the opcode for the Instruc-
on the left and a specific example IS shown on the nght. tion LDAA (Dlrectl at memory location 5004 (Program
Numerical examples are In deCimal notation Instructions of Counter = 5004), looks in the next location, 5005, for the ad-
thiS type require only one byte of opcode. Cycle:by-cycle dress of the operand. It then sets the program counter equal
operation of the Inherent mode IS shown In Table 6 to the value found there (100 In the example) and fetches the

•
operand, In thiS case a value to be loaded Into accumulator
Immediate Addressing Mode - In the Immediate address- A, from that location. For instructions requiring a two-byte
Ing mode, the operand IS the value that IS to be operated on. operand such as LDX (Load the Index Register!, the operand
For Instance, the Instruction bytes would be retneved from locations 100 and 101 Table 8
Operator Operand Comment shows the cycle-by-cycle operation for the direct moqe of
LDAA #25 LOAD 25 INTO ACCA addressing.
Extended addreSSing, Figure 31, IS Similar except that a
causes the MPU to "Immediately load accumulator A With two-byte address IS obtained from locations 5007 and 5008
the value 25", no further address reference IS required The after the LDAB (Extended) opcode shows up In location
Immediate mode IS selected by preceding the operand value 5006 Extended addreSSing can be thought of as the "stan-
With the "r symbol Program flow for thiS addressing mode dard" addreSSing mode, that is, It IS a method of reaching
IS Illustrated In Figure 29 any place In memory. Direct addressing, since only one ad-
The operand format allows either properly defined sym- dress byte IS required, proVides a faster method of process-
bols or numencal values. Except ior the instructions CPX, Ing data and generates fewer bytes of control code. In most
LDX, and LDS, the operand may be any value In the range 0 applications, the direct addreSSing range, memory locations
to 255. Since Compare Index Register (CPXl. Load Index 0-255, are reserved for RAM. They are used for data buffer-
Register (LDXI, and Load Stack POinter (LDSI, reqUIre 16-brt Ing and temporary storage of system vanables, the area In
values, the Immediate mode for these three instructions re- which faster addressing IS of most value Cycle-by-cycle
qUire two-byte operands. In the Immediate addressing operation IS shown In Table 9 for Extended Addressing.

FIGURE 27 - INHERENT ADDRESSING FIGURE 28 - ACCUMULATOR ADDRESSING

MPU

PC ,--=-,---" PC - 5000 ,---="-----,,

GENERAL FLOW EXAMPLE

EXAMPLE

4-77
 MC6800. MC68AOO. MC68BOO

Relative Address Mode - In both the Direct and Extended the unconditional Jump IJMP), Jump to subroutine IJSR),
modes, the address obtained by the MPU IS an absolute and return from subroutine IRTS) are used.
numencal address The Relative addressing mode, Im- In Figure 32, when the MPU encounters the opcode for
plemented for the MPU's branch Instructions, specifies a 8EQ 18ranch If result of last Instruction was zero), It tests the
memory location relative to the Program Counter's current Zero bltm the Condition Code Register. If that bit IS "0," in-
Incatlon Branch Instructions generate two bytes of machine dicating a non-zero result, the MPU continues execution
code, one for the instruction opcode and one for the with the next Instruction (in location 5010 In Figure 32). If the
"relative" address Isee Figure 32) Since It IS desirable to be prevIous result was zero, the branch condition IS satisfied
able to branch In either direction, the 8-blt address byte IS in- and the MPU adds the offset, 151n this case, to PC+2 and
terpreted as a signed 7-blt value, the 8th bit of the operand IS branches to location 5025 for the next instruction,
treated as a sign bit, "0" = plus and "1" = minus The re- The branch instructions allow the programmer to effiCient-
maining seven bits represent the numencal value This ly direct the MPU to one pOint or another In the control pro-
results In a relative addressing range of ± 127 with respect to gram depending on the outcome of test results, Since the
the location of the branch Instruction Itself However, the control program IS normally In read-only memory and cannot
branch range IS computed with respect to the next instruc- be changed, the relative address used In execution of branch
tion that would be executed If the branch conditions are not Instructions IS a constant numencal value. Cycle-by-cycle
satisfied Since two bytes are generated, the next Instruction operation IS shown In Table 10 for relative addreSSing.
IS located at PC + 2 If D IS defined as the address of the
branch destination, the range IS then Indexed Addressing Mode - With Indexed addreSSing,
IPC+2)-127sDsIPC+2)+ 127 the numencal address IS vanable and depends on the current
or contents of the Index Register A source statement such as
PC-125s Ds PC+ 129
Operator Operand Comment
that IS, the destination of the branch Instruction must be STAA X PUT A IN INDEXED LOCATION
within - 125 to + 129 memory locations of the branch In-

II
structIOn Itself For transferring control beyond this range, causes the MPU to store the contents of accumulator A In

TABLE 6 - INHERENT MODE CYCLE-BY-CYCLE OPERATION

Address Mode
and Instructions Address Bus Data Bus

ABA DAA SEC t 1 Op Code Address 1 Op Code

ASL DEC SEI 2
2 1 Op Code Address + 1 1 Op Code of Next Instruction
ASR INC SEV
CBA
CLC
CLI
CLR
LSR
NEG
NOP
ROL
TAB
TAP
TBA
TPA
I
CLV ROR TST
COM SBA
DES 1 1 Op Code Address 1 Op Code
DEX Op Code A.ddress + 1 1 Op Code of Next Instruction
2 1
INS
INX I 1
3 0 PrevIous Register Contents 1 Irrelevant Data (Note 1)
4 0 New Register Contents 1 Irrelevant Data (Note 1)
PSH 1 1 Op Code Address 1 Op Code
2 1 Op Code Acdress + 1 1 Op Code of Next Instruction
4
3 1 Stack POinter 0 Accumulator Data
4 0 Stack POinter - 1 1 Accumulator Data
PUL 1 1 Op Code Addres~ 1 Op Code
2 1 Op Code Address + 1 1 Op Code of Next Instruction
4
3 0 Stack POinter 1 Irrelevant Data (Note 1)
4 1 Stack POinter + 1 1 Operand Data from Stack
TSX 1 1 Op Code Address 1 Op Code
2 1 Op Code Address + 1 1 Qp Code Cff Next InstructIOn
4
3 0 Stack POinter 1 Irrelevant Data (Note 1)
4 0 New Index Register 1 Irrelevant Data (Note 1)
TXS 1 1 Op Code Address 1 Op Code
2 1 Op Code Address + 1 1 Op Code of Next Instruction
4
3 0 Index Register 1 Irrelevant Data
4 0 New Stack Pointer 1 Irrelevant Data
RTS 1 1 Op Code Address 1 Op Code
2 1 Op Code Address + 1 1 Irrelevant Data (Note 2)
5 3 0 Stack Po 10 ter 1 Irrelevant Data (Note 1)
4 1 Stack POinter + 1 1 Address of Next Instruction (High
Order Byte)
5 1 Stack POinter + 2 1 Address of Next Instruction (Low
Order Byte)

4-78
MC6800. MC68AOO· MC68BOO

TABLE 6 - INHERENT MODE CYCLE-BY-CYCLE OPERATION (CONTINUED)

Address Mode Cycle VMA R/W

and Instructions Cycles jt Line Address Bus Lme Data Bus

WAI 1 1 Qp Code Address ·1 Op Code

2 1 Op Code Address + , 1 Op Code of Next Instruction
3 1 Stack POinter 0 Return Address (Low Order Byte)
4 1 Stack Pomter - 1 0 Return Address (High Order Byte)
9 5 1 Stack Pointer - 2 0 Index Register (low Order Byte)
6 1 Stack POIOter - 3 0 Index Register (High Order Byte)
7 1 Stack Pointer - 4 0 Contents of Accumulator A
8 1 Stack POinter - 5 0 Contents of Accumulator B
9 1 Stack Pomter - 6 (Note 3) 1 Contents of Condo Code Register
RTI 1 1 Op Code Address 1 Op Code
2 1 Op Code Address + 1 1 Irrelevant Data (Note 2)
3 0 Stack Pomter 1 Irrelevant Data (Note 11
4 1 Stack POinter + 1 1 Contents of Cond Code Register from
Stack

•
10 1 +2 1 Contents of Accumulator B from Stack
5 Stack POinter
6 1 Stack Po,nter + 3 1 Contents of Accumulator A from Stack
7 1 Stack Pointer + 4 1 Index Register from Stack (High Order
8yte)
8 1 Stack POinter + 5 1 Inc;lex Register from Stack (Low Order
8yte)
9 1 Stack POinter + 6 1 Next I nstructlon Address from Stack
(HIgh Order Byte)
10 1 Stack POinter + 7 1 Next Instruction Address from Stack
{Low Order Byte}
SWI 1 1 Op Code Address 1 .Op Code
2 1 Op Code Address + 1 1 Irrelevant Data (Note 1)
3 1 Stack POinter 0 Return Address {Low Order Byte}
4 1 Stack POinter - 1 0 Return Address (High Order Byte)
5 1 Stack Pointer -- 2 0 Index Register (Low Order Byte)
6 1 Stack POinter - 3 0 Index Register (High Order Byte)
12
7 1 Stack POinter - 4 0 Contents of Accumulator A
8 1 Stack POinter -- 5 0 Contents of Accumulator 8
9 1 Stack POinter - 6 0 Contents of Cond Code Reglst~r

10 0 Stack POinter -, 7 1 Irrelevant Data (Note 1)

11 1 Vector Address FFFA (Hex) 1 Address of Subroutine (High Order
8yte)
12 1 Vector Address FFFB {Hex} 1 Address of Subroutine (Low Order
8yte)

Note 1 If deVice which IS addressed during thiS cycie uses VMA, then the Data Bus Will go to the high impedance three-state condition.
Depending on bus capacitance, data from the prevIous cycle may be retained on the Data Bus.
Note 2 Data is ignored by the MPU
Note 3. While the MPU IS waiting for the Interrupt, Bus Available will go high Indicating the followlOg states of the control lines. VMA IS
low; Address Bus, RNi. and Data Bus are ail In the high impedance state

the memory 10catJon specified by the contents of the Index location 5006. It looks In the next memory location for the
Register (recall that the label "X" IS reserved to deSignate the value to be added to X (5 In the example) and calculates the
Index Register) Since there are Instructions for manipulating reqUired address by adding 5 to the present Index Register
X dUring program execution (LOX, INX, DEC, etc.), the In- value of 400. In the operand format, the offset may be
dexed addressmg mode provides a dynamiC ··on the fly" way represented by a label or a numerical value In the range 0-255
to modify program activity as In the example In the earlier example, ST AA X, the
The operand field ca~ also contem a numerical value that operand IS eqUivalent 10 0, X, that IS, the 0 may be omitted
will be automatically added to X dUring execution ThiS for- when the deSired address IS equal to X Table 11 shows the
mat IS Illustrated In Figure 33. cycle-by-cycle operation for the Indexed Mode of Address-
When the MPU encounters the LDAB (Indexed) opcode m mg

4-79
 MC6800- MC68AOO-MC68BOO

FIGURE 29 - IMMEDIATE ADDRESSING MODE FIGURE 30 - DIRECT ADDRESSING MODE

MPU MPU MPU MPU

ADDR r-==-f'., ADDR = 100 r-'-::!:--I'

PC = 5004 1-==-1
5005 1-_;';""_1'

ADDR = O~255
GENERAL flOW EXAMPLE
GENERAL FLOW EXAMPLE

• ADC
ADO
AND
BIT
CMP
Address Mode
and Instructions

EOR
LOA
ORA
SBC
SUB
2
TABLE 7 -

1
2
1
1
IMMEDIATE MODE CYCLE-BY-CYCLE OPERATION

Address Bus

Op Code Address
Op Code Address +1
RM
Line

1
1
Op Code
Operand Data
Data Bus

CPX 1 1 Op Code Address 1 Op Code

LOS
LDX
3 2 1 Op Code Address + 1 1 Operand Data (High Order Bytel
3 1 Op Code Address + 2 1 Operand Data (Low Order Byte)

TABLE B - DIRECT MODE CYCLE-BY-CYCLE OPERATION

Address Mode RM
and Instructions Address Bus Line Data Bus

ADC EOR 1 1 Op Code Address 1 Op Code

ADD LOA Address of Operand
AND ORA 3 2 1 Op Code Address +1 1
BIT SBC 3 1 Address of Operand 1 Operand Data
CMP SUB
CPX 1 1 Op Code Address 1 Op Code
LDS 2 1 Op Code Address + 1 1 Address of Operand
lDX 4
3 1 Address of Operand 1 Operand Data (High Order Byte)
4 1 Operand Address +1 1 Operand Data (low Order Byte)
STA 1 1 Op Code Address 1 Op Code
2 1 Op Code Address + 1 1 Destination Address
4
3 0 Destination Address 1 Irrelevant Data (Note 1)
4 1 Destination Address 0 Data from Accumulator
STS 1 1 Op Code Address 1 Op Code
STX 2 1 Op Code Address +1 1 Address of Operand
5 3 0 Address of Operand 1 Irrelevant Data (Note 1)
4 1 Address of Operand 0 Register Data (High Order Byte)
5 1 Address of Operand + 1 0 Register Data (Low Order Byte)

Note 1 If device which IS address dUring thiS cycle uses VMA, then the Data Bus will go to the high Impedance three·state condition
Depending on bus capacitance, data from the prevIous cycle may be retained on the Data 8us

4-80
MC6800- MC68AOO- MC68BOO

FIGURE 31 - EXTENDED ADDRESSING MODE

MPU

ADDR f-==-I'..

ADDR 256
GENERAL FLOW EXAMPLE

TABLE 9 - EXTENDED MODE CYCLE-BY-CYCLE

Address Mode Cycle VMA R/W

•
and Instructions Cycles ~ Line Address Bus Lme Data Bus

STS
STX
1
,
1 Op Code Address 1
, Op Code

6
2
3 , Cp Code Address + 1
ap Code Address + 2 , Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
4 a Address of Operand 1 Irrelevant Data (Note 1)
1 a
5
, Address of Operand
Address of Operand + 1 a
Operand Data (High Order Byte)

JSR , ,
6
, Operand Data (Low Order Byte)
ap Code
, Op Code Address
,
2
, Op Code Address + 1
Op Code Address + 2 , Address of Subroutine (High Order Byte)
3
, , Address of Subroutme (Low Order Byte)
4
, Subroutine Startmg Address
a
Op Code of Next Instruction
9 5
, Stack POinter
a
Return Address (Low Order Byte)
6
a
Stack Pomter - 1
, Return Address (High Order Byte)
7
a
Stack Pomter -~ 2
, Irrelevant Data (Note 1 )
8
, Op Code Address + 2
Op Code Address + 2 , Irrelevant Data (Note 1)
9
, , , Addrpss of Subroutine (Low Order Byte)
JMP
, Op Code Address
, Op Code
3 2
, Op Code Address + 1
, Jump Address (High Order Byte)

,3 Op Code Address + 2 Jump Address (Low Order Byte)

ADC EOR
ADD LOA
1
, Op Code Address
,1 Op Code

AND ORA 4
2
, Op Code Address + 1
Op Code Address + 2 , Address of Operand (High Order Byte)
BIT SBC
CMP SUB
3
, , Address of Operand (Low Order Byte)

, ,
4 Address of Operand
, Operand Data
CPX
LOS , Op Code Address
, Op Code

LOX
2
, Op Code Address + 1
, Addrelos of Operand (High Order Byte)
5 3
, Qp Code Address + 2
, Address of Operand (Low Order Byte)
4
, Address of Operand Operand Data (High Order Byte)

STAA
, ,
5 Address of Operand + 1
Op Code Address
1
1
Operand Data (Low Order Byte)
Op Code
STA B 2
,
1 Op Code Address + 1 1 Destination Address (High Order Byte)
5
4
3
a
Qp Code Address + 2
Operand Destination Address ,
1 Destination Address (Low Order Byte)
Irrelevant Data (Note 1)
a
5
,
1 Operand Destination Address
, Data from Accumulator
ASL
ASR
LSR
NEG
1
, Op Code Address
, Op Code

CLR ROL
2
, Op Code Address + 1 Address of Operand (High Order Byte)
COM
DEC
INC
ROR
TST
6
3
4 , Op Code Address + 2
Address of Operand ,
1 Address of Operand (Low Order Byte)
Current Operand Data
5 a Address of Operand 1 Irrelevant Data (Note 1 )
6 1/0 Address of Operand a New Operand Data (Note 2)
(Note
2)

Note 1 If deVice which IS addressed during thiS cycle uses VMA, then the Data Bus Will go to the high Impedance three-state condition
Depending on bus capaCitance, data from the prevIous cycle may be retained on the Data Bus
Note 2 For TST, VMA '" 0 and Operand data does not change

4-81
 MC6800-MC68AOO-MC68BOO

FIGURE 32 - RELATIVE ADDRESSING MODE

Program Program
Memory Memory

PC Instr.
Offset PC
(PC + 2) Next Instr.
PC

(PC + 2) + (Offset) Next Instt PC 5025 Next Instr .

• FIGURE 33 -

MPU
INDEXED ADDRESSING MODE

ADOR '" INDX I-==-V"

+ OFFSET r==---1i"'-. AODR '" 4051-.....:5;:.9_-r.....

PC " 5006 I-":'::';;::'_~ J,A.......I

GENERAL FLOW EXAMPLE

TABLE 10 - RELATIVE MODE CYCLE-BY-CYCLE OPERATION

Address Mode R/W

and Instructions Address Bus Line Data Bus

BCC BHI BNE 1 1 Op Code Address 1 Op Code

BCS BlE BPl Op Code Address + 1 Branch Offset
BEQ
2 1 1
BLS BRA 4
BGE BLT BVC 3 0 Op Code Address + 2 1 Irrelevant Data (Note 1)
BGT BMI BVS Irrelevant Data (Note 1)
4 0 Branch Address 1
BSR 1 1 Op Code Address 1 Op Code
2 1 Op Code Address + 1 1 Branch Offset
3 0 Return Address of Main Program 1 Irrelevant Data (Note 1)
4 1 Stack POinter 0 Return Address (Low Order Byte)
8
51 Stack POinter - 1 0 Return Address (Hu;,h Order Byte)
60 Stack Pointer - 2 1 Irrelevant Data (Note 1)
7 0 Return Address of Main Program 1 Irrelevant Data (Note 1)
8 0 Subroutine Address 1 Irrelevant Data (Note 1)
Note 1. If deVice which IS addressed dunng thiS cycle uses VMA, then the Data 8us will go to the high Impedance three-state condition.
Depending on bus capacitance, data from the prevIous cycle may be retained on the Data 8us.

4-82
MC6800- MC68AOO-MC68BOO

TABLE 11 - INDEXED MODE CYCLE-BY-CYCLE

AddreaMode R
and Instructions Addr. . Bul Line
INDEXED
JMP 1 1 Op Code Addre.. 1 Op Code
2 1 Op Cod. Addre.. + 1 1 Offset
4
3 0 Index Register 1 Irrelevant Data (Note 1 )
4 0 Index Register Plus Offset (w/o Carry) 1 Irrelevant Data (Note 1)
ADC EDR 1 1 Dp Code Addre.. 1 Op Code
ADD LOA
2 1 Op Code Addre.. + 1 1 Offset
AND ORA
BIT SBC 5 3 0 Index Register 1 Irrelevant Data (Note 1 )
CMP SUB 1
4 0 Index Register Plus Offset (w/o Carry) Irrelevant Data (Note 11
5 1 Index Register Plus Offset 1 Operand Data
CPX 1 1 Op Code Address 1 Dp Code
LOS
LOX 2 1 Op Code Address +1 1 Offset
3 0 Index Register 1 I rrelevant Data (Note 1)
6
4 0 Index Register Plus Offset (w/o Carry) 1 Irrelevant Data (Note 1)

•
5 1 Index Register Plus Offset 1 Operand Data (High Order Byte)
6 1 Index Register Plus Offset + 1 1 Operand Data (Low Order Byte)

STA 1 1 Op Code Address 1 OpCode

2 1 Op Code Addra.. + 1 1 Offset

6 3 0 Index Register 1 Irrelevant Data (Note 11

4 0 Index RegISter Plus Offset (w/o Carry) 1 ,rrelevant Data (Note 1)
5 0 I ndex Register Plus Offset 1 Irrelevant Data INote 1)
6 1 Index RegISter Plus Offset 0 Operand Data
ASL LSR 1 1 Op Code Address 1 Op Code
ASR NEG 2 1 Op Code Address +1 1 Offset
CLR ROL
COM ROR 3 0 Index Register 1 Irrelevant Data INote 1)
7
DEC TST 4 0 Index Register Plus Offset (w/o Carry) 1 Irrelevant Data (Note 11
INC
5 1 I ndex Register Plus Offset 1 Current Operand Data
6 0 I ndex Register Plus Otfset 1 Irrelevant Data INote 1)
7 1/0 Index Register Plus Offset 0 New Operand Data {Note 21
(Note
2)
STS 1 1 Op Code Address 1 Op Code
STX 2 1 Op Code Address + 1 1 Offset
3 0 I ndex Register 1 Irrelevant Data (Note 1 )
7
4 0 Index Register Plus Offset (w/o Carry) 1 I rrelevant Data I Note 1)

5 0 Index Register Plus Offset 1 Irrelevant Data (Note 1)

6 1 Index Register Plus Offset 0 Operand Data (High Order Byte)

7 1 Index Register Plus Offset +1 0 Operand Data (Low Order Byte)

JSR 1 1 Op Code Address 1 Op Code

2 1 Op Code Addre.. + 1 1 Offset
3 0 Index Register 1 Irrelevant Dat8 (Note 1)

4 1 St8ck Pointer 0 Raturn Addre.. (Low Order Byte)

8
5 1 Stack Pointer - 1 0 Return Addre.. (High Order Byte)
6 0 Stack Pointer - 2 1 Irrelevant Data (Note 1 )
7 0 Index Register 1 Irrelevant Data (Noto 1)
8 0 Index Re.ister Plus Offset (w/o Carry) 1 Irrelevant Data (Note 1)
Note 1. If deVice which is addressed during this cycle uses VMA, then the Data Bus will go to the high impedance three.oState condition.
Depending on bus capacitance, data from the previOus cvcle may be retained on the Data Bus.
Note 2 For TST. VMA - 0 and Operand data does not change.

4·83
 MC6S01
@ MOTOROLA MC6S03
MC6S03NR

MICROCOMPUTER/MICROPROCESSOR (MCU/MPU)

The MC6801 IS an 8-blt single-chip microcomputer unit IMCU) which MOS

significantly enhances the capabilities of the M6800 family of parts It In- IN-CHANNEL, SILICON-GATE,
cludes an upgraded M6800 microprocessor unit IMPU) with upward- OEPLETION LOAO)
source and object-code compatibility Execution times of key Instruc-
tIOns have been Improved and several new Instructions have been add- MICROCOMPUTER
ed including an unsigned multiply The MCU can function as a MICROPROCESSOR
monolithic microcomputer or can be expanded to a 64K byte address
space It IS TTL compatible and reqUires one + 5-volt power supply. On-
chip resources Include 2048 bytes of ROM, 128 bytes of RAM, a Senal
CommunicatIOns Interface ISCI), parallel I/O, and a three function Pro-
grammable Timer The MC6803 can be conSidered as an MC6801

~""
operating In Modes 2 or 3 The MC6803NR IS comparable to MC6801
operating In Mode 3. An EPROM verSion of the MC6801, the MC68701
' ~ ~ ;"'"
microcomputer, IS available for systems development The MC68701 IS
I ,. G SUFFIX
pin and code compatible with the MC6801/03/03NR and can be used to
. 1 ":' PLASTIC PACKAGE
emulate the MC6801 /03/03NR The MC68701 IS descnbed In a separate . . CASE 711
Advance Information publication MC6801 MCU Family features In-
clude.

•
• Enhanced MC6800 Instruction Set
• 8 x 8 Multiply Instruction
• Serial Communications Interface ISCI)
• Upward Source and Object Code Compatibility With the M6800
• 16-Blt Three-Function Programmable Timer
• Single-Chip or Expanded OperatIOn to 64K Byte Address Space
• Bus Compatibility With the M6800 Family'
.2048 Bytes of ROM IMC6801) FIGURE I - PIN ASSIGNMENT
• 128 Bytes of RAM IMC6801 and MC6803)
• 64 Bytes of RAM Retalnable Dunng Powerdown IMC6801 VSS
and MC6803)
XTAL1 39 SCI
• 29 Parallel I/O and Two Handshake Control Lines
• Internal Clock Generator With Dlvlde-by-Four Output EXTAL2 SC2
NMI 4 P30
TIiCl1 P31
RESET 6 P32
VCC P33
PART NUMBER DESIGNATED P20 8 P34
BY SPEED P21 9 P35
P22 P36
MC6801 MC68A01
P23 P37
MC6803 MC68A03 "
P24 P40
MC6803NR MC68A03NR
P10 P41
(1.0 MHz) (1.5 MHz)
P11 P42
P12 P43
MC6801-1 MC68B01
P13 P44
MC6803-1 MC68B03'
P14 P45
MC6803NR-1 MC68B03NR
(1.25 MHz) (2.0 MHz) P15 P46
P16 P47
P17 VCC
Standby

4·84
MC6801. MC6803·MC6803NR

MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage Vcc -03to+70 V
This device contains Circuitry to protect the in-
Input Voltage Y,n -03to +70 V
puts against damage due to high static voltages
Operating Temperature Range 'TA o to 70 °c or electric fields, however, It IS advised that nor-
Storage Temperature Range Tstg -55 to +150 °C mal precautions be taken to aVOId appliCation of
any voltage higher than maximum rated voltages
'An extended temperature device, the MC6801C IS available With TA= -40°C to 85°C
to this high-Impedance Circuit For proper opera-
tion It IS recommended that V In and Vout be Con-
THERMAL CHARACTERISTICS strained to the range VSS '" IV,n or Voutl '" VCC
Input protection IS enhanced by connecting
Characteristic Symbol Value Rating unused Inputs to either VDD or VSS
Thermal Resistance
Plastic 8JA 50 °C/W
Ceramic 50

POWER CONSIDERATIONS

•
The average chip-Junction temperature, T j, In °C can be obtained from
T j= TA+ (P0 0 6jA)
Where.
TA,,"Amblent Temperature, °C
6jA .. Package Therma) Resistance, junctlOn-to-Amblent, °C/W
PO'" PINT + PPORT
PINT .. ICC x VCC, Watts - Chip Internal Power
PPORT- Port Power Oissipatlon, Watts - User Oetermlned
For most applications PPORT<C PINT and can be neglected PPORT may become Significant If the device IS configured to
drive Darlington bases or sink LEO loads
An approximate relatIOnship between Po and T j (,f PPORT IS neglected) IS
PD=K-lTj+273°C) (2)
Solving equations 1 and 2 for K gives.
K= Poo(TA+273°C) +6JAoP 0 2 (3)
Where K IS a constant pertaining to the particular part K can be determined from equation 3 by measuring Po (at eqUilibrium)
for a known T A USing thiS value of K the values of Po and T J can be obtained by solVing equations (1) and (2) Iteratively for any
value of TA

CONTROL TIMING IVCC=5 0 V ±5%, VSS=O, TA=O to 70°CI

MC6801 MC6801-1 MC68A01 MC68B01
Characteristic Symbol Unk
Min Max Min Max 'Min [Max Min Max
Frequency 01 Operation 10 05 10 05 1.25 05 15 05 20 MHz
Crystal Frequency IXTAL 3579 40 3579 50 3579 60 3579 80 MHz
External OSCillator Frequency 410 20 40 20 50 20 60 20 80 MHz
Crystal OSCillator Start Up Time trc - 100 - 100 - 100 - 100 ms
Processor Control Setup Time tpcs 200 - 170 - 140 - 110 - ns

4·85
 MC6801-MC6803-MC6803NR

DC ELECTRICAL CHARACTERISTICS (VCC=50 Vdc ±5% VSS=O TA=O to lOoC unless otherwise noted I
Characteristic Symbol Min Typ Max Unit
Input High Voltage i'i'E'Sn VSS+40 - VCC V
VIH
Other Inputs' VSS+20 - VCC
Input Low Voltage All Inputs' VIL VSS-O 3 - VSS+08 V
Input Load Current Port 4
lin
- - 05
rnA
(V,n = 0 to 2.4 VI SC1 - - 08
Input Leakage Current
(V,n=Oto 525 VI NliiIl, iRl!i, RESET lin - 15 25 "A
Three-State (Off Statel Input Current
(VIn =05t02.4VI P10-P17, P30-P37 ITSI - 20 10 "A
P20-P24 - 100 100
Output High Voltage
"Ioad= -100 "A, Vcc=mlnl P30-P37 VSS+24 - -
VOH V
"Ioad= -65 "A, Vcc=mlnl" P40-P47, E, SCI, SC2 VSS+24 - -
"load = -loo"A, Vcc=mlnl Other Outputs VSS+24 - -
Output Low Voltage
"load=2 OmA, Vcc=mlnl All Outputs VOL - - VSS+O 5 V

Darlington Drive Current

10H 10 25 100 rnA
(VO=1.5VI Pl0-P17
Internal Power DIssipation (Measured at TA = O°C In Steady-State Operation I PINT - - 1200 mW
Input Capacitance
(VIn=O, TA=25°C, fo= 1 0 MHzl P30-P37, P40-P47, SCI C,n - - 125 pF
Other Inputs - - 100

•
VCC Standby Powerdown VSBB 40 - 525
V
Powerup VSB 475 - 5.25
Standby Current Powerdown ISBB - - 60 rnA
'Except Mode Programming Levels, See Figure 16
"Negotiable to -100 "A (for further information contact the factoryl
FIGURE 2 - M6801 MICROCOMPUTER FAMILY BLOCK DIAGRAM

I Ii Expanded MultIplexed
Expanded Non-Multiplexed

30 P37
I
AlID7 D7 110
Single Chip ,

P20 " pel

peo l
P36 A6/D6 D6 110 P21 q II
P35 A5/D5 D5 110 PUID PC'1, CU'\ L
P34 A4/D4 D4 110 P23 II RX
P33
P32
A3/D3
A2/D2
D3
D2
110
110
P24 \'L 11
ITm1
P31 Al/Dl Dl 1/0
3"'1 P30 AO/DO DO 110
3'6' SC2 R(W R/W ~
,'1 SCI AS im ~

2 .. P47 A15 A7 110 PIO ~

P46 A14 A6 110 Pll
P45 A13 A5 110 P12
P44 A12 A4 110 P13
P43 All A3 110 P14
P42 A10 A2 110 P15
P41 A9 Al 110 P16
'<~ P40 A8 AO 110 P17 "l-U

(11 No functIOning RAM In MC6803NR

(21 No functioning ROM In MC6803 and MC6803NR

4·86
MC6801·MC6803·MC6803NR

PERIPHERAL PORT TIMING IRefer to Figures 3-61

Characteristics Symbol Min Typ Max Unit
Peripheral Data Setup Time tpDSU 200 - - ns
Peripheral Data Hold Time tpDH 200 - - ns
Delay Time, Enable Positive Transition to 0$3 Negative Transition tOSDl - - 350 ns
Delay Time, Enable Posltlve TranSitIon to 033 Positive TranSition tOSD2 - - 350 ns
Delay Time, Enable Negative TranSition to Peripheral Data Valid
Port 1 tpWD - - 350 ns
Port 2, 3, 4 - - 350
Delay Time, Enable Negative TranSition to Peripheral CMOS Data Valid tCMOS - - 20 ~s

Input Strobe Pulse Width tpWIS 200 - - ns

Input Data Hold Time tlH 50 - - ns
Input Data Setup Time !(S 20 - - ns

FIGURE 3 - DATA SETUP AND HOLD TIMES FIGURE 4 - DATA SETUP AND HOLD TIMES
IMPU READ)

, M P U Read
r
(MPU WRITE)

MPUWrHe

PlO-Pt 7
P20-P24
P40-P47
~ ~/ {CMOS

tPWD _ --0 7 Vec

II
Inputs AIIDalJ
Data Valid
Port Outputs _ _ _ _ _ _ _ _~ 1\-_ _ _ __
P30-P37
Inputs·
NorES
"Port 3 Non-Latched Operation (LATCH ENABLE 0)
1 10 k Pullup reSistor requlled for Port 2 to reach 0 7 Vee
Not applicable to P21
Paf! 4 cannot be pulled above Vee

FIGURE 5 - PORT 3 OUTPUT STROBE TIMING FIGURE 6 - PORT 3 LATCH TIMING

(MC6801 SINGLE-CHIP MODE) (MC6801 SINGLE-CHIP MODE)

t MPU access of Port 3~

Address
Bus

P30-P37
Inputs

*Access matches Output Strobe Select (OSS = 0, a read,

OSS =" a wnte~

NOTE Timing measurements are referenced to and from a low voltage of 0 8 volts and a high voltage of 20 volts, unless otherwise noted

4·87
 MC6801· MC6803. MC6803N R

BUS TIMING (See Notes 1 and 2)

MC6801 MC6801-1 MC68AOI MC68BOI
Ident, MC6803 MC6803-1 MC68A03 MC68B03
Characteristics Symbol Unit
Number MC6803NR MCtBXlNR-1 MC68A03NR MC68B03NR
Min Max Min. Max Min Max Min Max
I Cycle Time tcyc 10 20 08 20 0667 20 05 20 p's

2 Pulse Width, E Low PWEL 430 1000 350 1000 300 1000 210 1000 ns
3 Pulse Width, E High PWEH 450 1000 350 1000 300 1000 220 1000 ns
4 Clock Rise and Fall Time tr, tf - 25 - 25 - 25 - 20 ns
9 Address Hold Time tAH 20 - 20 - 20 - 10 - ns
12 Non-Muxed Address Valid Time to E' tAV 200 - 150 - 115 - 70 - ns
17 Read Data Setup Time tDSR 50 - 70 - 50 - 40 - ns
18 Read Data Hold Time tDHR 10 - 10 - 10 - 10 - ns
19 Write Data Delay Time tDDW - 225 - 200 - 170 - 120 ns
21 Write Data Hold Time tDHW 20 - 20 - 20 - 10 - ns
22 Muxed Address Valid Time to E Rise' tAVM 200 - 150 - 115 - 50 - ns
24 Muxed Address Valid Time to AS Fall' tASL 60 - 50 - 40 - 20 - ns
25 Muxed Address Hold Time tAHL 20 - 20 - 20 - 10 - ns
26 Delay Time, E to AS Rise' tASD 90" - 70" - 50" - 45" - ns

•
27 Pulse Width, AS High' PWASH 220 - 170 - 140 - 110 - ns
28 Delay Time, AS to E Rise' tASED 90 - 70 - 60 - 45 - ns
29 Usable Access Time' ISee Note 9) tACC 595 - 465 - 380 - 270 - ns
• At specified cycle time
"tASD parameters listed assume external TTL clock drive with 50% ± 5% duty cycle DeVices driven by an external TTL clock with 50% ± 1%
duty cycle or which use a crystal have the following tASD specifications 100 ms min 11,0 MHz deVices), 80 ms min, 11 25 MHz deVice),
65 ms min, 11 5 MHz deVices), 50 ms min 120 MHz deVices)
FIGURE 7 - BUS TIMING

R/W,lOS,
Address ----i~~~~JC~~------------------rt--------------------------------rt~~~
(Non-Muxed) -----+~~~~~~~~------------------_i_t------------------------------------ri~~~

Addr I Data -----t-.ll:-r""

Muxed

Addr/Data
Muxed

Address
Strobe IASi ___________-''f'1

NOTES
Voltage levels shown are VL.$O 5 \I, VH2:2 4 V, unless otherwise specified
Measurement pOints shown are 0 8 V and 2 0 V, unless otherWise specified
Usable access time IS computed by 12 + 3 - 17 + 4
Memory deVices should be enabled only dUring E high to avoid Port 3 bus contention

4-88
MC6801- MC6803- MC6803N R

FIGURE 8 - CMOS LOAD FIGURE 9 - TIMING TEST LOAD PORTS 1,2,3,4

1rl
Vee
RL18kO

Test POint MMD6150

Test POint or Equlv

C R MMD7000
or Equlv
~ ~

C~90 pF for P30·P37, P40·P47, E, SCI, SC2

~30 pF for P10-P17, P20-P24
R~37 kO for P4O·P47, E, SCI, SC2
~ 24 kO for Pl0·P17, P20·P24
~ 24 kO for P30·P37

The MC6801 IS an 8·blt monolithic microcomputer which

INTRODUCTION

can be configured to function In a Wide vallety of applica-

tions The facility which provides this extraordinary flexibility
The term "port," by Itself, refers to all of the hardware
associated with the port When the port IS used as a "data
port" or "1/0 port," It IS controlled by the port Data Direc-
•
IS ItS ability to be hardware programmed Into eight different tion Register and the programmer has direct access to the
operating modes. The operating mode controls the con- port pins uSing the port Data Register. Port PinS are labled as
figuration of 18 of the 40 MCU pinS, available on-chip PII where I Identifies one of four ports and I indicates the par-
resources, memory map, location (Internal or external) of In- ticular bit
terrupt vectors, and type of external bus. The configuration The Microprocessor Unit (MPU) IS an enhanced MC6800
of the remaining 22 pinS IS not dependent on the operating MPU with additional capabilities and greater throughput. It IS
mode upward source and oblect code compatible with the
Twenty-nine pins are organized as three 8-blt ports and MC6800 The programming model IS depicted In Figure la,
one 5-b't port. Each port consists of at least a Data Register where Accumulator D IS a concatenation of Accumulators A
and a wnte-only Data Direction Register The Data Direction and 8 A list of new operations added to the M6800 instruc-
Register IS used to define whether corresponding bits In the tion set are shown In Table 1.
Data Register are configured as an Input (clear) or output The MC6803 can be considered an MC6801 that operates
(set) In Modes 2 and 3 only The MC6803NR IS comparable to an
MC6801 that operates In Mode 3 only

4-89
 MC6801- MC6803- MC6803NR

FIGURE 10 - PROGRAMMING MODEL

~ A °U7
15--------- B
D ---------
~ 8-Blt Accumulators A and B
~
Or 16-BIt Double Accumulator D

..ll_5_________X_ _ _ _ _ _ _ _ _ _O""llndex Register (XI

..ll_5_________S_P_ _ _ _ _ _ _ _ _O...1Stack POinter (SPI

..ll_5_________P_C_ _ _ _ _ _ _ _ _O...1Program Counter (PCI

ConditIOn Code Register (CCRI

~......Lr'-I~.Lr''"r'"-r'
Carry/Borrow from MSB
Overflow
Zero
Negative

•
Interrupt
L.._ _ _ _ _ _ Half Carry (From Bit 31

OPERATING MODES

The MC6801 provides eight different operating modes Non-Multiplexed IS Mode 5 and the remaining five are Ex-
(Modes a through 7), the MC6803 provides two operaling pRnded Multiplexed modes Table 2 summarIZes the
modes (Modes 2 and 3), and the MC6803NR provides one characteristics of the operating modes
operating mode (Mode 31 The operating modes are hard-
ware selectable and determine the device memory map, the MC6801 Single-Chip Modes (4, 7)
configuration of Port 3, Port 4, SCI, SC2, and the phYSical In the Single-Chip Mode, the four MCU ports are con-
location of the Interrupt vectors figured as parallel Input/output data ports, as shown In
Figure 11 The MCU functions as a monohthlc microcom-
FUNDAMENTAL MODES puter In these two modes Without external address or data
The eight operating modes can be grouped Into three fun- buses A maximum of 29 110 hnes and two Port 3 control
damental modes which refer to the type of bus It supports hnes are provided Peripherals or another MCU can be inter-
Single ChiP, Expanded Non-Multiplexed, and Expanded faced to Port 3 In a loosely coupled dual processor configura-
Multiplexed Single chip modes Include 4 and 7, Expanded tion, as shown In Figure 12

TABLE 1 - NEW INSTRUCTIONS

Instruction Description
ABX UnSigned addition of Accumulator B to Index Register
ADDD Adds (without carry) the double accumulator to memory and leaves the sum," the double accumulator
ASLD or LSLD Shifts the double accumulator left (towards MSBI one bit, the LSB IS cleared and the MSB IS shifted mto the C-blt
BHS Branch If Higher or Same, unSigned conditional branch (same as BCC)
BLO Branch If Lower, UnSigned conditional branch (same as BCS)
BRN Branch Never
JSR Additional addreSSing mode direct
LDD Loads double accumulator from memory
LSL Shifts memory or accumulator left (towards MSB) one bit, the LSB IS cleared and the MSB 's shifted Into the C-bIt (same as
ASL)
LSRD Sh,fts the double accumulator right (towards LSB) one bit, the MSB IS cleared and the LSB IS shifted Into the C-blt
MUL UnSigned multiply. multiplies the two accumulators and leaves the product In the double accumulator
PSHX Pushes the Index Register to stack
PULX Pulls the Index Register from stack
STD Stores the double accumulator to memory
SUBD Subtracts memory from the double accumulator and leaves the difference In the double accumulator
CPX Internal processing modified to permit Its use With any conditional branch instruction

4·90
MC6801·MC6803·MC6803NR

In Single-Chip Test Mode (41, the RAM responds to bidirectional data bus and Port 4 IS configured Initially
$XX80 through $XXFF and the ROM IS removed from the in- as an Input data port Any combination of the eight least-
ternal address map A test program must first be loaded Into significant address lines may be ob18lned by writing to the
the RAM uSing modes 0, 1, 2, or 6 If the MCU IS Reset and Port 4 Data Direction Register Stated alternatively, any
then programmed Into Mode 4, execution will begin at combination of AO to A7 may be provided while retaining the
$XXFE XXFF Mode 5 can be irreversibly entered from Mode remainder as Input data lines Internal pullup rGSlstors pull
4 without asserting RESET by setting bit 5 of the Port 2 Data the Port 4 lines high until the port IS configured
Register ThiS mode IS used primarily to test Ports 3 and 4 ,n
the Single-Chip and Non-Multiplexed Modes
Figure 13 Illustrates a tYPical system configuration In the
Expanded Non-Multiplexed Mode The MCU Interfaces
MC6801 Expanded Non-Multiplexed Mode (51 directly With M6800 family parts and can access 256 bytes of
Amodest amount of external memory space IS provided In external address space at $100 through $1 FF lOS provides
the Expanded Non-Multiplexed Mode while significant on- an address decode of external memory ($100-$1 FFI and can
chip resources are retained. Port 3 functions as an 8-blt be used as a memory page select or chip select line

TABLE 2 - SUMMARY OF MC6801/03/03NR OPERATING MODES

Common to all Modes:

•
Reserved Register Area
Port 1
Port 2
Programmable Timer
Senal Communications Interface
Single Chip Mode 7
128 bytes of RAM, 2048 bytes of ROM
Port 3 IS a parallel 1/ 0 port With two control lines
Port 4 IS a parallel 1/0 port
SC1 IS Input Strobe 3 IIS~
SC2 IS Output Strobe 3 IOS31
Expanded Non-Multiplexed Mode 5
128 bytes of RAM, 2048 bytes of ROM
256 bytes of external memory space
Port 3 IS an 8-blt data bus
Port 4 IS an Input port! address bus
SCI IS Input/Output Select IIOSI
SC2 IS Read/Write IR/WI
Expanded Multiplexed Modes 1, 2, 3, 6'
Four memory space options (64K address spacel
111 No tnternal RAM or ROM IMode 31
12/ Internal RAM, no ROM IMode 21
13/ Internal RAM and ROM IMode 11
14/ Internal RAM, ROM With partial address bus IMode 61
Port 3 IS a multiplexed addressl data bus
Port 4 IS an address bus (,nputs/address In Mode 6)
SCI IS Address Strobe lAS)
SC2 IS Aead/Write IA/W)
Test Modes 0 and 4
Expanded Multiplexed Test Mode 0
May be used to test RAM and ROM
Single Chip and Non-Multiplexed Test Mode 4
111 May be changed to Mode 5 Without gOing through Reset
12/ May be used to test Ports 3 and 4 as I/O ports

"The MC6803 operates only In modes 2 and 3, the MC6803NR operates only In Mode 3

4·91
 II
FIGURE 11 - SINGLE-CHIP MOOE FIGURE 12 - SINGLE-CHIP OUAL PROCESSOR CONFIGURATION
s:
n
§....

-
Vee Vee Vee

XTALI

n
s:•
§
Port 3
Port 1
81/0
Port 1
81/0
s:•
I II II IiS3
~z
Port 1
8 110 Lones 8110 Lones LInes LInes

0S3
I Port 2 Port 4
Port 4
8110 Lones
•
II ~ Port 2
5110 Lones I 5 110 Lones
SCI
81/0
Lines
:::c
'::" Senall/O
16-811 TImer
-= -=
VSS VSS VSS
Lines
16-81t Timer

~
cO
I\.)

FIGURE 13 - EXPANDED NON-MULTIPLEXED CONFIGURATION

-
Vee Vee
I
~ XTALI Port3 8
~(DO-D71
Port4 8
(AO-A71
-c::_ EXTAL2 iOS /
lOS
Vee Standby_ R/W R/W
RESET- E E
MC6801
NM-I~

IRol--
Port 3
Port 1
8 1/0 Lones 8 Data lines Port 1 .... ....
R/W 81/0 ...
Port 2
51/0
lOS
Port 2 ....
"
Port 4 --"
5 110
Lines
Senall/O
To 8 SCI ... --,.
16-81t Timer
-=-
Timer
~
VSS VSS
RAM PIA ACIA

----- ---- .
MC6801.MC6803· MC6803N R

Expanded-Multiplexed Modes (0, 1, 2, 3, 6) Multiplexed Modes Address Strobe can be used to control a
A 64K byte memory space IS provided In the expanded transparent D-type latch to capture addresses AO-A7, as
multiplexed modes In each of the expanded multiplexed shown In Figure 15 ThiS allows Port 3 to function as a Data
modes Port 3 functions as a time multiplexed address/data Bus when E IS high
bus with address valid on the negative edge of Address
Strobe lAS), and data valid while E IS high )n Modes 0 to 3, PROGRAMMING THE MODE
Port4 provides address lines AS to A 15 )n Mode 6, however, The operating mode IS determined at RESET by the levels
Port 4 initially IS configured at RESET as an Input data port asserted on P22, P21, and P20 These levels are latched Into
The port 4 Data Direction Register can then be changed to PC2, PC1, and PCO of the program control register on the
prOVide any combination of address lines, AS to A 15 Stated positive edge of RES ET The operating mode may be read
alternatlve)y, any subset of AS to A 15 can be provided whl)e from the Port 2 Data Register as shown below, and program-
retaining the remaining port 4 lines as Input data lines Inter- ming levels and timing must be met as shown In Figure 16 A
na) pullup resistors pull the Port 4 )Ines high until software brief outline of the operating modes IS shown In Table 3
configures the port
In Mode 0, the Reset vector IS external for the first two PORT 2 DATA REGISTER
E-cycles after the positive edge of RES ET, and Internal 7 6 5 4 3 2 o
thereafter In addition, the Internal and external data buses
are connected so there must be no memory map overlap In
order to avoid potential bus conflicts Mode 0 IS used
I PC21 PCl I I
PCO P241 P231 P221 P21 I I
P20 $0003
primarily to verify the ROM pattern and mOnitor the Internal

•
data bus With the automated test equipment CircUitry to proVide the programmmg levels IS dependent
Only the MC6801 can operate In each of the expanded primarily on the normal system usage of the three pms If
multplexed modes The MC6803 operates only In Modes 2 configured as outputs, the circuit shown In Figure 17 may be
and 3, while the MC6803NR operates only In Mode 3 used, otherWise, three-state buffers can be used to proVide
Figure 14 depicts a tYPical configuration for the Expanded- Isolation, while programming the mode

TABLE 3 - MODE SELECTION SUMMARY

P22 P2l P20 Interrupt Bus Operating

Mode" PC2 PCl PCO ROM RAM Vectors Mode Mode
7 H H H I I I I Single Chip

c
6 H H L I I I MUXI5,61 Multiplexed/Partial Decode

5 H L H I I I NMUXI5,61 Non-Multlplexed/Parttal Decode

4 H L L 1121 1111 I I Single Chip Test
3 L H H E E E MUXI41 Multiplexed/No RAM or ROM
2 0 (HI (C1 E I E MUXI41 Multiplexed/RAM
1 L L H I I E MUXI41 Multiplexed/RAM & ROM
0 L L L I I 1131 MUXI41 Multiplexed Test
~
Legend Notes
!=-internal -----rriTnternal RAM IS addressed at SXX80
E - External (2) Internal ROM IS disabled
MUX - Multiplexed (3) RESET vector IS external for 2 cycles after RESET goes high
NMUX - Non-Multiplexed (4) Addresses associated With Ports 3 and 4 are conSIdered external," Modes 0,
L - LogiC "0" I, 2, and 3
H - LogiC "I" (5) Addresses associated With Port 3 are conSidered external In Modes 5 and 6
(6) Port 4 default IS user data input, address output IS optional by writing to Port 4
Data DIrection Register

'The MC6803 operates only In Modes 2 and 3, the MC6803NR operates only In Mode 3

4·93
 MC6801-MC6803-MC6803NR

FIGURE 14 - EXPANDED MULTIPLEXED CONFIGURATION

Vee

Port 1 Port 3
8 I/O Lines

Port 2
Port 4
5 I/O lmes 8 Lines
Serrall/O Address Bus
16-BII Timer

VSS
V C

XTAl1

•
fXTAb2
Vee Sldndby
REsTI MC6801 1-_ _..L--,.,....-,r+____'"'T'"+____ril-_. . Addres~ Bus
NMi MC6803 16 (AD A151
R/W
iJillj MC6803NR 1------rlH---4"++---......t-I--. . RIN

Port 1
81/0
Port 2
5 I/O
SCI
TImer

VSS

NOTE To avoid data bus (Port 31 contention In the expanded multiplexed modes, memory devices should be enabled only dUring E high time

FIGURE 15 - TYPICAL LATCH ARRANGEMENT

GND
AS

11
G OC

M'''~ ~A,
Dl at

Port 3
AddresslData lf 74LS373
ITYPlcal1 }

08 08

} ~ .. 000,

4-94
MC6801-MC6803-MC6803NR

FIGURE 16 - MODE PROGRAMMING TIMING

See Figure 17

for~DIOde
Arrangement~ VMPDD
.,
..... - - V
(P20, P21, P221 " " MPL
_ _ ___ " ---.- Mode Latch
Mode Inputs ~ I Level
(P20, P21, P221

MODE PROGRAMMING IRefer to Figure 161

Characteristic Symbol Min Max Unit
Mode Programming Input Voltage Low VMPL - 18 V
Mode Programming Input Voltage High VMPH 40 - V
Mode Programming Diode Differential (If Diodes are Used) VMPDD 06 - V
RESET Low Pulse Width PWRSTL 30 - E-Cycles
Mode Programming Setup Time tMPS 20 - E-Cycles
Mode Programming Hold Time
RtSET Rise Trme~ 1 ~s tMPH 0 - ns

II
RESET Rise T,me< 1 ~s 100 -

FIGURE 17 - TYPICAL MODE PROGRAMMING CIRCUIT

VCC

1
>-
R2 : > Rl ~> Rl R,>
>

6
RESET RESET
8
P20 P20lPCOI
9
P2 1 P21 (PCll
10
P22 P22 (PC21

Mode
Control MC6801
SWitches MC6803
MC6803NR

D D D

Notes

I-....
1 Mode 7 as shown
2 R2-C =: Reset time constant C
3 Rl = 10 k ItYPlcall
4 D= lN914, lN4001 Ityplcall
5 Diode Vf should not exceed VMPDD min

MEMORY MAPS 6R, the MC6801 ROM has been relocated by a mask option
The M6801 Family can provide up to 64K byte address The first 32 locations of each map are reserved for the inter-
space depending on the operating mode A memory map for nal register area, as shown In Table 4, with exceptions as In-
each operating mode IS shown In Figure 18 In Modes 1Rand dicated

4·95
 • ~

~
......
~
•
FIGURE 18 - MC6801/03/03NR MEMORY MAPS ~•
~

Multiplexed Test mode

MC6S0!
Mode
o ~
Z
:JJ
soooonl 17nnnn;:;:;,
Internal RegIsters
$OOlF ~«'K
External Memory Space Notes
$0080 ~7/77777777;K 1) Excludes the following addresses which may
beusedexternally S04, S05, S06, S07and SOF
Internal RAM
~ 2) Addresses SFFFE and SFFFF are considered

~ $OOFF 1/£/£//««/i( external If accessed within 2 cycles after a

positive edge of RESET and mternal at all other
times
3) After 2 MPU cycles, there must be no over-
External Memory Space lapPing of Internal and external memory
spaces to aVOid driving the data bus with more
than one device
4) This mode 15 theonlymodpwhlch maybe used
SFSOO bnnnnnJ( to examine the Interrupt vectors In Internal
ROM uSing an external RESET vector
Internal ROM

$FFFF!2J [//uu«u«v Internal Interrupt Vectors I.,!)

 s:
n
~
-"

s:•
FIGURE 18 - MC6801/03/03NR MEMORY MAPS (CONTINUED)

MC6801
Mode
1 MC6801
Mode 1R MC6801
MC6803
2 ~•
Mode
s:
MultIplexed/RAM & ROM

$0000(11 v?77777J77JJt\.
MultIplexed/RAM & ROM

SOO00{11 OJ77nhn7A<--
Multlple)(ed/RAM
~
Z
Internal Registers Internal Registers I nternal Registers ::XJ
SOOl F I"<U////U/'j( $ 001 F ru««<'l<'l«K SOOl F f ( ( ( ( / / f i J I ! '1(
External Memory Space External Memory Space External Memory Space
S0080 b777777JJJJAC S0080 b77777777JzA( S0080 1,,,,,, u" ,ok'
Internal RAM Internal RAM Internal RAM
SOOFF r'/i/II((((/1(
SOOF F ~?///(«(~ SOOF F fIt // ((u///'K
~
cO '=xternal Memory Space
~
External Memory Space
SX800 121 It);))) 7J7JnK External Memory Space

Internal ROM(21
SF800 b777777777J:A<
SXFF:= F ( { { « ( ( ( ( ( ( U 11

Internal ROM
$FFEF 1//L///////L1(
SFFFO
SFFFF
External Interrupt Vectors
:::~ t t External Interrupt Vectors
$FFFF I v
External I nterrupt Vectors

Notes Notl(s Notes

1) Excludes the following addresses which may 1) Excludes the follOWing addresses which may 1) Excludes the follOWing addresses which may
be used externally S04, S05, S06, S07 and be used externally S04, S05, S06, S07, and be used externally S04, S05, S06, S07, and
SOF SOF SOF
2) Internal ROM addresses SFFFO to SFFFF are 2) Starting addresses for the Internal ROM may
not usable be SC800, SD800 or SE800 as a mask optIon

II
 .' s:
FIGURE 18 - MC6801/03/03NR MEMORY MAPS (CONTINUEDI
~....
s:•
~•
MC6801
MC6803
MC6803NR
Mode
3 MC6801
Mode
4 MC6801
Mode 5
Multiplexed/No RAM or ROM Single Chip Test Non~MuJtlplexed/ Partial Decode
s:
(')
$0000 111
$oooo~lnternal ~~ Internal
~
f///////////4( Internal RegIsters Registers Registers
$oolF $001 F""~~Lf':LL.:-L>

~::::, ::,,' ""'

Z
:0

$OlFFY
External Memory Space Unusablel1l141
I
Unusable
-'='"
~
Internal ROM
$FFFOI r $XX80~lnternal RAM
External Interrupt Vectors 0"//////,/(1) Internal Interrupt Vectors
$FFFFI II $XXFF . Internal Interrupt Vectors

Notes Notes Notes

1) Excludes the following addresses which may be 11 The Internal ROM IS disabled 1) Excludes the follOWing addresses which may not
used externally $04, $05, $06, $07 and $OF 21 Mode 4 may be changed to Mode 5 without hav- be used externally $04, $06, and $OF INa lOS 1
Ing to assert RESET by writing a "1" Into the 2) ThiS mode may be entered without gOing
peo bIt of Port 2 Data Register through RESET by uSing Mode 4 and subse-
31 Addresses A8 to A 15 are treated as "don't quently writing a "1" IOta the peo bit of Port 2
cares" to decode Internal RAM Data Register
41 Internal RAM Will appear at $XX80 to $XXFF 3) Address lines AO to A7 will not contaIn addresses
until the Data Dlrect!on RegIster for Port 4 has
been wntten wIth "1's" m the appropriate bits
These address Imes will assert "1 's" until made
outputs by wntmg the Data DirectIon Register
 ~

FIGURE 18 - MC6801/03/03NR MEMORY MAPS (CONCLUDEDI ~.....

s:•
MC6801
Mode 6 Me6801
Mode
6 R MC68D1
Mode 7 ~•
~

~z
Multiplexed/Partial Decode

$0000 ~ Internal Registers

')OOlll 1/))7)77)777)"
Internal Registers Internal Registers
S001Fu~~.-
External Memory Space External Memory Space
:c
S0080 _ Internal RAM
Internal RAM Internal RAM

SOOFF 1
External Memory Space

~ Unusable
External Memory Space
cO
CO
fnternal ROM Ij)

External Memory Space

Internal ROM llnternal ROM

Internal Interrupt Vectors

SFFFF I 1/
External Interrupt Vectors
SFFFF V/%////h//41
r Internal Interrupt Vectors

Notes Notes
1) Excludes the following addresses which may be 1) Excludes the following addresses which may
used extern",ly S04, S06, SOF be used externally $04, S06, $OF
2) Address lines AS-A 15 will not contain 2) Address lines A8-A 15 will not contain
addresses until the Data Direction Reglsterfor addresses until the Data DlrectlOn Register
Port 4 has been written with '"l's" In the for Port 4 has been written with "1 's" In the
appropriate bits These address Imes will appropriate bits These address lines will
assert "1 '5" unt,1 made outputs by writing the assert "l's" until made outputs by wrltmg the
Data DirectIon Register Data Direction Register
3) Starting addresses for the mternal ROM may
be SC800, SD800 or SE800

•
 MC6801- MC6803- MC6803NR

MC6801/OO/OONR INTERRUPTS between them to prevent supplYing power to V CC dUring

powerdown operation V CC Standby should be tied to
The M6801 Family supports two types of Interrupt re- ground In Mode 3
quests maskable and non-maskable A Non-Maskable Inter-
rupt (NMII,s always recognized and acted upon at the com- TABLE 4 - INTERNAL REGISTER AREA
pletion of the current Instruction Maskable Interrupts are
Register Address
controlled by the Condition Code Register I-bit and by In-
dividual enable bits The I-bit controls all maskable inter- Port 1 Data Direction Register"· 00
Port 2 Data DIrectIOn Register··· 01
rupts Of the maskable Interrupts, there are two types iRQi
Port 1 Data Register 02
and Ti'i'<TI The Programmable Timer and Serial Communica- Port 2 Data Register 03
tIOns Interface use an Internal ~ Interrupt line, as shown
In Figure 2 External deVices (and IS3) use rnm An IR011n- Port 3 Data Direction Register """ 04'
terrupt IS serviced before ~ If both are pending Port 4 Data Direction Register """ 05"
All IR02 Interrupts use hardware prioritized vectors The Port 3 Data Register OS'
Single SCI Interrupt and three timer Interrupts are serviced In Port 4 Data Register 07"
a Prioritized order and each IS vectored to a separate loca-
TImer Control and Status Register 08
tIOn All Interrupt vector locations are shown In Table 5 Counter (High Byte) 09
The Interrupt flowchart IS depicted In Figure 19 and IS Counter (Low Byte) OA
common to every Interrupt excluding reset DUring Interrupt Output Compare Register (HIgh Byte) OB
servIcing the Program Counter, Index Register, A Ac-
cumulator, B Accumulator, and Condition Code Register are Output Compare RegIster (Low Bvte) OC

•
pushed to the stack The I-bit IS set to Inhibit maskable Inter- Input Capture Register (High Byte) 00
Input Caplure Register (Low Byte) OE
rupts and a vector IS fetched corresponding to the current
Port 3 Control and Status Register OF'
highest Priority Interrupt The vector IS transferred to the
Program Counter and Instruction execution IS resumed In- Rate and Mode Control Register 10
terrupt and REm timing are Illustrated In Figures 20 and 21 Transmit/Receive Control and Status Register 11
Receive Data Register 12
FUNCTIONAL PIN DESCRIPTIONS Transmit Data Register 13

RAM Control Register 14

Vec ANDVSS
Reserved 15-1F
V CC and V S S prOVide power to a large portion of the
MCU The power supply should proVide + 5 volts (± 5%) to External addresses In Modes 0, 1, 2, 3, 5, 6, cannot be accessed
In Mode 5 (No lOS)
VCC, and VSS should be tied to ground Total power
""External addresses In Modes 0, 1, 2, 3
diSSipation (including V CC Standby), will not exceed PD
"""1 = Output, 0= Input
mllhwatts

Vec STANDBY TABLE 5 - MCU INTERRUPT VECTOR LOCATIONS

VCC Standby prOVides power to the standby portIOn ($80 MSB LSB Interrupt
through $BF) of the RAM and the STBY PWR and RAME
FFFE FFFF RESET
bits of the RAM Control Register Voltage requirements de-
FFFC FFFO NMI
pend on whether the deVice IS In a powerup or powerdown
state In the powerup state, the power supply should proVide FFFA FFFB Software Interrupt (SWI)
+5 volts (±5%) and must reach VSB volts before RESET FFF8 FFF9 IRQ1 (or 153)
reaches 40 volts DUring powerdown, VCC Standby must FFF6 FFF7 ICF (Input Capture)"
remain above VSBB (min) to sustain the standby RAM and OCF (Output Compare)"
FFF4 FFF5
STBY PWR bit While In powerdown operation, the standby
FFF2 FFF3 TOF !Timer Overflow)"
current Will not exceed ISBB
FFFO FFF1 SCI (RORF+ORFE+TDRE)'
It IS tYPical to power both VCC and VCC Standby from the
same source dUring normal operation A diode must be used "IRQ2 Interrupt

4-100
 FIGURE 19 - INTERRUPT FLOWCHART
s:
~.....
s:•
~
s:•
~
Z
::tI

~
~
o
~

SCI = TIEoTDRE+ RIEoIRDRF+ ORFEI

Condlhon Code Register

Vector . . PC

NMI FFFC FFFO Non-Maskable Interrupt

SWI FFFA FFFB Software Interrupt
IROl FFFB FFF9 Maskable Interrupt Request 1
ICF FFF6 FFF7 Input Capture Interrupt
OCF FFF4 FFF5 Output Compare Interrupt
TOF FFF2 FFF3 Timer Overflow Interrupt
SCI FFFO FFFl SCllnterrupt (TORE -I- RDRF + ORFE)

•
 • s:
~......
FIGURE 20 - INTERRUPT SEQUENCE

I Cycle
Last Instructron-j #1 #2 #3 #4 I #5 I #6 #7 #8 #9 I #10 I #11 #12
s:•
~•
E

Internal
Address Bus
s:
~
IRQl

NMI or IRQ2
\. Z
~ !--tpcs :II

Internal
Data Bus
Op Code Op Code PC 0-7 PC8-15 X 0-7 X 8-15 ACCA ACCB CCR Irrelevant Vector Vector First Inst of
_ _ _ _ _ _ _ _ _ _ _ _~+...l1_'"\ Data MSB LSB Interrupt Routine
Internal R/W \ /
f'
-"'
oI\)
FIGURE 21 - RESET TIMING

&\\\\\\\\\\\\~ %\~m~~~\\\\ LJLf1 f1JLflJ

525 V 1I ' I ~ I1 ~
VCC
7f..:475 V tRC ' - L i : = t Pcs ~ i:="tPCS

RESET _ _ _----,11 I ~40V 08\~1=-

_ _ _ __

Internal \\\\\\'S\\\\\\\\\s' \\\\\\\\\\\\\\\\\\\\\\\\\ \\~ ------.JL~"'-_.A.._...J\_ _"-_./I...._.../\._...../I_....J'I__=

Address Bus ' ----- ~~ FFFE FFFE FFFE FFFE FFFF New PC

Internal R/W S\\\\\\\\\\\\\\\~ ~\\\\\\\\\\\\\\\\\\\\\\\\\\\l -------------~~

&\\\\\\\\\\\\\\\\~ /hl\\\\\\\\\ \\\\\\\\\\\\\\\\\Nq ~

Internal
Data Bus
PC 8-15 PC 0-7 First
InstructIon
~ NotVahd
MC6801- MC6803- MC6803N R

XTAL1 AND EXTAl2 SCl and SC2 In Single-Chip Mode

These two Input pins Interface either a crystal or TTL com- In Single-Chip Mode, SC1 and SC2 are configured as an
patible clock to the MCU Internal clock generator Dlvlde-by- Input and output, respectively, and both function as Port 3
four circuitry IS Included which allows use of the inexpensive control lines SC1 functions as TS3 and can be used to In-
358 MHz or 44336 MHz Color Burst TV crystals A 20 pF dicate that Port 3 Input data IS ready or output data has been
capacitor should be tied from each crystal pin to ground to accepted Three options associated With TS3 are controlled
ensure reliable startup and operation Alternatively, EXT AL2 by Port 3 Control and Status Register and are discussed In
may be driven by an external TTL compatible clock at 4fo the Port 3 descnptlon If unused, IS3 can remain uncon-
with a duty cycle of 50% I ± 5%) with XT AL 1 connected to nected
ground SC2 IS configured as OS3 and can be used to strobe out-
The Internal OSCillator IS deSigned to Interface With an AT- put data or acknowledge Input data It IS controlled by Out-
cut quartz crystal resonator operated In parallel resonance put Strobe Select 10SSI In the Port 3 Control and Status
mode In the frequency range specified for fXT AL The Register The strobe IS generated by a read lOSS = 01 or
crystal should be mounted as close as possible to the Input wnte lOSS = 11 to the Port 3 Data Register OS3 timing IS
pins to minimize output distortion and startup stabilization shown In Figure 5
time· The MCU IS compatible With most commercially
SCl And SC2 In Expanded Non-Multiplexed Mode
available crystals Nominal crystal parameters are shown In
Figure 22. In the Expanded Non-Multiplexed Mode, both SC1 and
SC2 are configured as outputs SC1 functions as Input/Out-
RESET put Select IIOSI and IS asserted only when $0100 through
$01 FF IS sensed on the Internal address bus
ThiS Input IS used to reset the Internal state of the deVice
SC2 IS configured as Read/Wnte and IS used to control
and proVide an orderly startup procedure DUring powerup,
the direction of data bus transfers An MPU read IS enabled
RESET must be held below 08 volts 111 at least tRC after
when Read/Wnte and E are high

•
V CC reaches 4 75 volts In order to proVide suffiCient time for
the clock generator to stabilize, and 121 until V CC Standby SCl And SC2 In Expanded Multiplexed Mode
reaches 475 volts RESET must be held low at least three
In the Expanded Multiplexed Modes, both SC1 and SC2
E-cycles If asserted dunng powerup operation
are configured as outputs SC1 functions as Address Strobe
and can be used to demultiplex the eight least significant ad-
E (ENABLE)
dresses and the data bus A latch controlled by Address
ThiS IS an output clock used pnmanly for bus synchroniza- Strobe captures address on the negative edge, as shown In
tion It IS TTL compatible and IS the slightly skewed dlvlde- Figure 15
by-four result of the deVice Input clock frequency It Will SC2 IS configured as Read/Wnte and IS used to control
drive one Schottky TTL load and 90 pF, and all data given In the direction of data bus transfers An M PU read IS enabled
cycles IS referenced to thiS clock unless otherWise noted when Read/Wnte and E are high

NMI (NON-MASKABLE INTERRUPT) Pl0-P17 (PORT 1)

An NMI negative edge requests an MCU Interrupt se- Port 1 IS a mode Independent 8-blt I/O port With each line
quence, but the current Instruction will be completed before an Input or output as defined by the Port 1 Data Direction
It responds to the request The MCU Will then begin an inter- Register The TTL compatible three-state output buffers can
rupt sequence Finally, a vector IS fetched from $FFFC and dnve one Schottky TTL load and 30 pF, Darlington tran-
$FFFD, transferred to the Program Counter and Instruction Sistors, or CMOS deVices uSing external pullup resistors It IS
execution IS resumed NMI tYPically requires a 33 kO configured as a data Input port by RESET Unused lines can
Inomlnal~lstor to VCC There IS no Internal NMI pullup remain unconnected
resistor NM I must be held low for at least one E-cycle to be
P20-P24 (PORT 2)
recognized under all conditions
Port 2 IS a mode-Independent, 5-blt, multipurpose 1/ a port
IRQ1 (MASKABLE INTERRUPT REOUEST 1) The voltage levels present on P20, P21, and P22 on the nSlng
edge of RESET determine the operating mode of the MCU
IR01IS a level-senSitive Input which can be used to re-
The entire port IS then configured as a data Input port The
quest an Interrupt sequence The M PU will complete the cur-
Port 2 lines can be selectively configured as data output lines
rent instruction before It responds to the request If the inter-
by setting the appropnate bits In the Port 2 Data Direction
rupt mask bit II-bit) In the Condition Code Register IS clear,
Register The Port 2 Data Register IS used to move data
the MCU will begin an Interrupt sequence A vector IS fetch-
through the port However, If P21 IS configured as an out-
ed from $FFF8 and $FFF9, transferred to the Program
put, It Will be tied to the timer Output Compare function and
Counter, and instruction execution IS resumed
cannot be used to prOVide output from the Port 2 Data
iR51 tYPically requires an external 3 3 kO Inomlnal! Register
resistor to VCC for wire-OR applications IRQ1 has no inter-
Port 2 can also be used to proVide an Interface for the
nal pullup resistor
Senal Communications Interface and the timer Input Edge
function These configurations are descnbed In the ap-
SCl AND SC2 (STROBE CONTROL 1 AND 2)
propnate SCI and Timer sections of thiS publication
The function of SC1 and SC2 depends on the operating The Port 2 three-state, TTL-compatible output buffers are
mode. SC1 IS configured as an output In all modes except capable of dnvlng one Schottky TTL load and 30 pF, or
Single chip mode, whereas SC2 IS always an output SC1 CMOS deVices uSing external pull up resistors
and SC2 can dnve one Schottky load and 90 pF
PORT 2 DATA REGISTER

'"DeVices made With masks subsequent to M5G, M8D and T5P in-
7 6 543 2 1 o
corporate an advanced clock With Improved startup charac-
teristics
IPC21 PC1 I I
PCO P241 P231 P221 P21 I I
P20 $0003

4-103
 MC6801-MC6803- MC6803NR

FIGURE 22 - M6801 FAMILY OSCILLATOR CHARACTERISTICS

lal Nominal Recommended Crystal Parameters

Nominal Crystal Parameters·

3.58 MHz 4.00 MHz 5.0 MHz 6.0 MHz B.O MHz
RS 6011 5011 30-50 11 30-5011 20-40 11
Co 35 pF 65 pF 4-6 pF 4-6 pF 4·6 pF
C, 0015 pF 0025 pF 001·002 pF 001-002 pF 001·002 pF
0 >40 K >30 K >20 K >20 K >20 K

*NOTE These are representative AT-cut crystal parameters only Crystals of other
types of cut may also be used

MC6S01

1.1 3

•
• CL ~ 20 pF (tYPlcall
2
Ll
Cl

Co
RS

EqUivalent CircUIt

NOTE
TTL -compatible oscillators may be
obtained from
Motorola Component Products
Attn Data Clock Sales
2553 N Edgington St
Franklin Park, IL 60131
Tel 312·451-1000
Telex 433·0067

Ib) Oscillator Stabilization Time ItRC)

~4~7~5~V~-----------f~f----------------------------------
Vee

I. tAC
Oscillator
J

Stabilization
Time. tRC

4·104
MC6801- MC6803- MC6803N R

P30-P37 (PORT 3) Port 3 In Expanded Multiplexed Mode

Port 3 can be configured as an I/O port, a bidirectional Port 3 IS conflgur8d as a time multiplexed address (AO-A7I
8-blt data bus, or a multiplexed address/ data bus depending and data bus (o7-DOI In the Expanded Multiplexed Modes,
on the operating mode The TTL compatible three-state out- where Address Strobe (AS) can be used to demultiplex the
put buffers can drive one Schottky TTL load and 90 pF two buses Port 3 IS held In a high Impedance state between
Unused lines can remain unconnected valid address and data to prevent bus conflicts

Port 3 In Single-Chip Mode P40-P47 (PORT 4)

Port 3 IS an 8-blt I/O port In the Single-Chip Mode, with Port 4 IS configured as an S-blt I/O port, as address out-
each line configured by the Port 3 Data Direction Register puts, or as data Inputs depending on the operating mode
There are also two lines, IS3 and OS3, which can be used to Port 4 can drive one Schottky TTL load and 90 pF and IS the
control Port 3 data transfers only port with Internal pullup resistors Unused lines can re-
Three Port 3 options are controlled by the Port 3 Control main unconnected
and Status Register and are available only In Single-Chip
Mode (1) Port 3 Input data can be latched uSing IS3 as a
control signal, (2) OS3 can be generated by either an MPU Port 4 In Single-Chip Mode
read or write to the Port 3 Data Register, and (3) an IRQ1 In- In Single-Chip Mode, Port 4 functions as an 8-blt I/O port
terrupt can be enabled by an iS3negative edge Port 3 latch with each line configured by the Port 4 Data Direction
timing IS shown In Figure 6 Register Internal pullup resistors allow the port to directly In-
terface with CMOS at 5 volt levels External pullup resistors
to more than 5 volts, however, cannot be used

153
Flag
PORT 3 CONTROL AND STATUS REGISTER

IS3
IRQ1
6

Enable
X
5 4

OSS
3

Latch
Enable
2

X X
o

X $OOOF
Port 4 In Expanded Non-Multiplexed Mode
Port 4 IS configured from reset as an S-blt Input port,
where the Port 4 Data Direction Register can be written to
provide any or all of eight address lines, AO to A7 Internal
I
pullup resistors pull the lines high until the Port 4 Data Direc-
tion Register IS configured
Bit 0-2 Not used
Bit 3 LATCH ENABLE This bit controls the Port 4 In Expanded Multiplexed Mode
Input latch for Port 3 If set, Input data In all Expanded Multiplexed modes except Mode 6, Port 4
IS latched by an iS3 negative edge The functions as half of the address bus and provides AS to A 15
latch IS transparent after a read of the In Mode 6, the port IS configured from reset as an 8-blt
Port 3 Data Register LATCH ENAL- parallel Input port, where the Port 4 Data Direction Register
BLE IS cleared dUring reset can be wlllten to provide any or all of upper address lines AS
Bit 4 OSS (Output Strobe Select) This bit to A 15 Internal pullup resistors pull the lines high until the
determines whether OS3 will be Port 4 Data Direction Register IS configured, where bit 0 con-
generated by a read or write of the Port trols AS
3 Data Register When clear, the
strobe IS generated by a read, when
set, It IS generated by a write OSS IS
cleared dUring reset RESIDENT MEMORY
Bit 5 Not used
The MC6801 provides 2048 bvtes of on-board ROM and
Bit 6 IS3 IRQ1 ENABLE When set, an iROT
128 bytes of on-board RAM
Interrupt will be enabled whenever 153
One half of the RAM IS powered through the VCC standby
FLAG IS set, when clear, the Interrupt
pin and IS maintainable dUring V CC powerdown ThiS stand-
IS inhibited This bit IS cleared dUring
by portion of the RAM consists of 64 bytes located from $SO
reset
through $BF
Bit 7 IS3 FLAG This read-only status bit IS Power must be supplied to V CC standby If the Internal
set by an I S3 negative edge It IS RAM IS to be used regardless of whether standby power
cleared by a read of the Port 3 Control operation IS anticipated
and Status Register (with IS3 FLAG The RAM IS controlled by the RAM Control Register
set) followed by a read or write to the
Port 3 Data Register or dUring reset
RAM CONTROL REGISTER ($14)
Port 3 In Expanded Non-Multiplexed Mode The RAM Control Register Includes two bits which can be
Port 3 IS configured as a bidirectional data bus (07-00) In used to control RAM accesses and determine the adequacy
the Expanded Non-Multiplexed Mode The direction of data of the standby power source dUring powerdown operation
transfers IS controlled by Read/Write (SC2) Data IS clocked It IS rntended that RAME be cleared and STBY PWR be set
by E (Enable) as part of a powerdown procedure

4-105
 MC6801·MC6803·MC6803NR

RAM CONTROL REGISTER PROGRAMMABLE TIMER

7 6 5 4 3 2 o
STBY RAME x x x x x x The Programmable Timer can be used to perform Input
PWR waveform measurements while Independently generating an
output waveform Pulse Widths can vary from several
Bit 0-5 Not Used microseconds to many seconds A block diagram of the
Timer IS shown In Figure 23
Sit 6 RAME RAM Enable This Read/Write bit can
be used to remove the entire RAM
from the Internal memory map RAME COUNTER ($09:0A)
IS set (enabled) dUring Reset provided The key timer element IS a 16-blt free-running counter
standby power IS available on the which IS Incremented by E (Enable) It IS cleared dUring reset
positive edge of RESET If RAME IS and IS read-only With one exception a write to the counter
clear, any access to a RAM address IS ($09) Will preset It to $FFF8 ThiS feature, Intended for
external If RAME IS set and not In testing, can disturb serial operations because the counter
Mode 3, the RAM IS Included In the in- proVides the SCI Internal bit rate clock TOF IS set whenever
ternal map the counter contains all l's
Sit 7 STBY PWR Standby Power This bit IS a
Read/Write status bit which IS cleared OUTPUT COMPARE REGISTER ($OB:OC)
whenever VCC Standby decreases The Output Compare Register IS a 16-blt Read/Write
below VSBB (min) It can be set only register used to control an output waveform or proVide an ar-

•
by software and IS not affected dUring bitrary timeout flag It IS compared With the free-running
reset counter on each E-cycle When a match occurs, OCF IS set

FIGURE 23 - BLOCK DIAGRAM OF PROGRAMMABLE TIMER

MC6801/MC6803/MC6803NR Internal Bus

Status Register
Register
$OB Bit 1
Port 2
DDR

,...-
I
Output Compare Pulse ___ J Output Input
Level Edge
Bit 1 Bit 0
Port 2 Port 2

4·106
MC6801-MC6803-MC6803NR

and OLVL IS clocked to an output level register If Port 2, bit Sit 4 EICI Enable Input Capture Interrupt When
1, IS configured as an output, OLVL Will appear at P21 and set, an IRQ2 mterrupt IS enabled for an
the Output Compare Register and OLVL can then be Input capture, when clear, the Inter-
changed for the next compdre The function IS mhlblted for rupt IS mhlblted It IS cleared dUring
one cycle after a write to ItS high byte ($OBI to ensure a valid reset
compare The Output Compare Register IS set to $FFFF at Bit 5 TOF Timer Overflow Flag rOF IS set when
RESET the counter contains all 1's It IS
cleared by reading the TCSR (with
INPUT CAPTURE REGISTER ($OD:OE) TOF set) then reading the counter high
The Input Capture Register IS a 16-blt read-only register byte ($OO), or dUring reset
used to store the free-runnmg counter when a "proper" In- Bit 6 OCF Output Compare Flag OCF IS set
put transition occurs as defmed by IEDG Port 2, bit 0 should when the Output Compare Register
be configured as an mput, but the edge detect CirCUit always matches the free-runnmg counter It IS
senses P20 even when configured as an output An Input cleared by readmg the TCSR (with
capture can occur Independently of ICF the register always OCF setl and then wrltmg to the Out-
contains the most current value Counter transfer IS In- put Compare Register ($OB or $OCI, or
hibited, however, between accesses of a double byte MPU dUring reset
read The mput pulse Width must be at least two E-cycles to
Bit 7 ICF Input Capture Flag ICF IS set to m-
ensure an mput capture under all conditions
dlcate a proper level transition, It IS
cleared by reading the TCSR (with ICF
TIMER CONTROL AND STATUS REGISTER ($OB)

•
setl and then the Input Capture
The Timer Control and Status Register (TCSR) IS an 8-blt Register High Byte ($001, or dUring
register of which all bits are readable, while only bits 0-4 can reset
be written The three most significant bits provide the timer
status and md,cate If'
• a proper level transition has been detected,
• a match has occured between the free-running SERIAL COMMUNICATIONS INTERFACE (SCI)
counter and the output compare register, and
A full-duplex asynchronous Serial Communications Inter-
• the free-running counter has overflowed
face (SClils provided With two data formats and a variety of
Each of the three events can generate an IRQ2 Interrupt
rates The SCI transmitter and receiver are functionally m-
and IS controlled by an md,v,dual enable bit In the TCSR
dependent, but use the same data format and bit rate Serial
data formats Include standard mark/space (NRZI and BI-
TIMER CONTROL AND STATUS REGISTER (TCSR) phase and both provide one start bit, eight data bitS, and one
stop bit "Baud" and "bit rate" are used synonymously In
7 6 5 432 1 0 the follOWing deSCription

WAKE-UP FEATURE
In a typical serial loop mUlti-processor configuration, the
Bit OOLVL Output level OLVL IS clocked to the
software protocol Will usually Identify the addressee(s) at the
output level register by a successful
beglnnmg of the message In order to permit uninterested
output compare and Will appear at P21
MPU's to Ignore the remainder of the message, a wake-up
If Bit 1 of the Port 2 Data Direction
feature IS Included whereby all further SCI receiver flag (and
Register IS set It IS cleared dUring
Interrupti processing can be mhlblted until ItS data line goes
reset
Idle An SCI receiver IS re-enabled by an Idle string of ten
Bit 1 EIDG Input Edge IEDG IS cleared dUring consecutive 1's or dUring reset Software must provide for
reset and controls which level transI- the required Idle string between consecutive messages and
tion Will trigger a counter transfer to prevent It Within messages
the Input Capture Register
IEDG = 0 Transfer on a negative-edge PROGRAMMABLE OPTIONS
IEDG= 1 Transfer on a posItive-edge The followmg features of the SCI are programmable
Bit 2 ETOI Enable Timer Overflow Interrupt • format standard mark/space (NRZI or BI-phase
When set, an IRQ2 Interrupt IS enabled • clock external or Internal bit rate clock
for a timer overflow, when clear, the
• Baud one of 4 per E-clock frequency, or external
Interrupt IS mhlblted It IS cleared dur-
clock ( x 8 deSired baud)
Ing reset
• wake-up feature enabled or disabled
Sit 3 EOCI Enable Output Compare Interrupt
When set. an IRQ2 Interrupt IS enabled • Interrupt requests enabled Individually for trans-
for an output compare, when clear, mitter and receiver
the Interrupt IS mhlblted It IS cleared • clock output Internal bit rate clock enabled or diS-
dUring reset abled to P22

4-107
 MC6801- MC6803-MC6803NR

SERIAL COMMUNICATIONS REGISTERS Bit 1 Bit 0 S S 1 SSO S peed Select These two
The Serial Communications Interface Includes four ad- bits select the Baud when uSing the in-
dressable registers as depicted In Figure 24 It IS controlled ternal clock Four rates may be
by the Rate and Mode Control Register and the selected which are a function of the
Transmlt/ Receive Control and Status Register Data IS MCU Input frequency Table 6 lists bit
transmitted and received utilizing a write-only Transmit time and rates for three selected M CU
Register and a read-only Receive Register The shift registers frequencies
are not accessible to software Bit 3 Bit 2 CCl CCO Clock Control and Format
Select These two bits control the for-
mat and select the serial clock source
Rate and Mode Control Register IRMCR) 1$10) If CCl IS set, the DDR value for P22 IS
The Rate and Mode Control Register controls the SCI bit forced to the complement of CCO and
rate, format, clock source, and under certain conditions, the cannot be altered until CCl IS cleared
configuration of P22 The register consists of four write-only If CCl IS cleared after haVing been set,
bits which are cleared dUring reset The two least Significant ItS DDR value IS unchanged Table 7
bits control the bit rate of the Internal clock and the remain- defines the formats, clock source, and
Ing two bits control the format and clock source use of P22
If both CCl and CCO are set, an external TTL compatible
clock must be connected to P22 at eight times 18XI the
deSired bit rate, but not greater than E, With a duty cycle of
50% I ± 10%1 If CCl CCO= 10, the Internal bit rate clock IS

•
RATE AND MODE CONTROL REGISTER IRMCR) provided at P22 regardless of the values for TE or RE
NOTE: The source of SCI internal bit rate clock is the timer
7 6 5 43210
free running counter. An MPU write to the counter
x x x x 1 CCl 1 CCO 1 SSll SSO 1 $0010 can disturb serial operations.

FIGURE 24 - SCI REGISTERS

alt 7 Rate and Mode Control Register alt 0

I Ieel I ceo 155115501 $10

Transmit/Receive Control and Status Register

Port 2

Receive Shift Reqlster

10

12

4·108
MC6801 e MC6803e MC6803NR

Transmit/ Receive Control And Status Register Sit 5 TDRE Transmit Data Register Empty TDRE
ITRCSR) 1$11) IS set when the Transmit Data Register
The Transmit/Receive Control and Status Register con- IS transferred to the output serial shift
trols the transmitter, receiver, wake-up feature, and two in- register or dUring reset It IS cleared by
dividual Interrupts and mOnitors the status of serial opera- reading the TRCSR IWlth TDRE set)
tions All eight bits are readable while bits 0 to 4 are also and then writing to the Transmit Data
writable The register IS initialized to $20 by RESET Regrster Additional data will be
transmitted only If TDR E has been
TRANSMIT/RECEIVE CONTROL AND STATUS cleared
REGISTER ITRCSR) Sit 6 ORFE Overrun Framing Error If set, ORFE In-
dicates either an overrun or framing er-
6 5 4 3 2 o ror An overrun IS a new byte ready to
transfer to the Receiver Data Register
With RDRF stili set A receiver framing
error has occurred when the byte
S,tOWU "Wake-up" on Idle Line When set, boundaries of the bit stream are not
WU enables the wake-up function, It IS synchronized to the bit counter An
cleared by ten consecutive 1'5 or dur- overrun can be distinguished from a
Ing reset WU will not set If the line IS framing error by the state of RDRF If
Idle RDRF IS set, then an overrun has oc-

•
Sit 1 TE T ransmt Enable When set, P24 DDR curred, otherWise a framing error has
bit IS set, cannot be changed, and will been detected Data IS not transferred
remain set If TE IS subsequently to the Receive Data Register In an
cleared When TE IS changed from overrun condition Unframed data
clear to set, the transmitter IS con- causing a framing error IS transferred
nected to P24 and a preamble of nine to the Receive Data Register
consecutive 1'5 IS transmitted TE IS However, subsequent data transfer IS
cleared dUring reset blocked until the framing error flag IS
Sit 2 TIE Transmit Interrupt Enable When set, cleared' ORFE IS cleared by reading
an IR02 Interrupt IS enabled when the TRCSR IWlth ORFE set) then the
TDRE IS set, when clear, the Interrupt Receive Data Register, or dUring reset
IS inhibited TE IS cleared dUring reset Sit 7 RDRF Receive Data Register Full RDRF IS
Sit 3 RE Receive Enable When set, the P23 set when the Input serial shift register
DDR bit IS cleared, cannot be chang- IS transferred to the Receive Data
ed, and will remain clear If RE IS subse- Register It IS cleared by readmg the
quently cleared While RE IS set, the TRCSR IWlth RDRF set), and then the
SCI receiver IS enabled RE IS cleared Receive Data Register, or dUring reset
dUring reset
Sit 4 RIE Receiver Interrupt Enable When set, "Oevlces made With mask numbers M5G, M8D, and TbP do not
an IR02 Interrupt IS enabled when transfer unframed data to the Receive Data Register
RDRF and/or ORFE IS set, when clear,
the Interrupt IS Inhibited RIE IS cleared
dUring reset

TABLE 6 - SCI BIT TIMES AND RATES

410 _ 2.4576 MHz 4.0 Mhz 4.9152 MHz
SSI:SS0
E 614.4 kHz 1.0 MHz 1.2288 MHz
0 0 -16 26 ~s/38,400 Baud 16 ~s/62,500 Baud 13 0 ~s!76,800 Baud
0 1 -128 208 ~s/4,800 baud 128 ~s!7812 5 Baud 104 2 l,s/9,600 Baud
1 0 -1024 1 67 ms/600 Baud$ 1 024 ms/976 6 Baud 833 3 ~s/l ,200 Baud
1 1 -4096 6 67 ms/150 Baud 4 096 ms/244 1 Baud 333 ms/300 Baud
'ExternallP221 13 a ~sI76,800 Baud 8 0 ~s/125,000 Baud 6 5 ~s/153,600 Baud
"Using maximum clock rate

TABLE 7 - SCI FORMAT AND CLOCK SOURCE CONTROL

CC1:CCO Clock Port 2

Format
Source B~ 2
00 BI-Phase Internal Not Used
01 NRZ Internal Not Used
10 NRZ Internal Output
11 NRZ External Input

4·109
 SERIAL OPERATIONS executable Instruction IS suffiCient to Identify the Instruction
The SCI IS Inttlalized by wntlng control bytes first to the and the addreSSing mode The hexadeCimal eqUivalents of
Rate and Mode Control Register and then to the the binary codes, which result from the translation of the 82
Transmltl Receive Control and Status Register When TE IS Instructions In all valid modes of addreSSing, are shown In
set, the output of the transmit senal shift register IS con- Table 8 There are 220 valid machine codes, 34 unassigned
nected to P24 and senal output IS Initiated by transmitting a codes, and 2 codes reserved for test purposes
9-blt preamble of l's
At this pOint one of two situations eXist lllf the Transmit PROGRAMMING MODEL
Data Register IS empty (TDRE= 11, a continuous stnng of l's A programming model for the MC6801/03/03NR IS shown
will be sent indicating an Idle line, or 21 If a byte has been In Figure 11 Accumulator A can be concatenated with ac-
wntten to the Transmit-Data Register (TDRE=Q), It Will be cumulator B and JOintly referred to as accumulator D where
transferred to the output senal shift register (synchronized A IS the most significant byte Any operation which modifies
with the bit rate clockl, TDRE Will be set, and transmission the double accumulator Will also modify accumulator A
Will begin and I or B Other registers are defined as follows
The start bit (01, eight data bits Ibeglnnlng with bit 01 and a Program Counter - The program counter IS a 16-blt
stop bit (11, Will be transmitted If TDRE IS stili set when the register which always pOints to the next Instruction
next byte transfer should occur, l's Will be sent until more
Stack Pointer - The stack pOinter IS a 16-blt register
data IS provided In BI-phase format, the output toggles at
which contams the address of the next available location In a
the start of each bit and at half-bit time when a "1" IS sent.
pushdown/pullup (L1FOI queue The stack reSides In ran-
Receive operation IS controlled by RE which configures P23
dom access memory at a location defined by the program-
as an Input and enables the receiver SCI data formats are Il-
mer.
lustrated In Figure 25

I
Index Register - The Index Register IS a 16-blt register
INSTRUCTION SET which can be used to store data or provide an address for the
Indexed mode of addreSSing
The MC6801/03/03NR IS upward source and object code Accumulators - The M PU contains two 8-b" ac-
compatible with the MC6800 Execution times of key Instruc- cumulators, A and B, which are used to store operands and
tions have been reduced and several new Instructions have results from the anthmetlc logiC unit IALUI They can also be
been added, Including a hardware multiply A list of new concatenated and referred to as the D Idoublel accumulator
operations added to the MC6800 instruction set IS shown In Condition Code Registers - The condition code register
Table 1 Indicates the results of an Instruction and Includes the
In addition, two new speCial opcodes, 4E and 5E, are pro- following five condition bits Negative I NI , Zero IZI,
Vided for test purposes These opcodes force the Program Overflow (VI, Carry/Borrow from MSB ICI, and Half Carry
Counter to Increment like a 16-blt counter, causing address from bit 3 I HI These bits are testable by the conditional
lines used In the expanded modes to Increment until the branch instructions Bit 4 IS the Interrupt mask (I-bltl and In-
deVice IS reset. These opcodes have no mnemoniCS hibits all maskable Interrupts when set The two unused bitS,
The coding uf the first (or onlyl byte corresponding to an B6 and B7, are read as ones

FIGURE 25 - SCI DATA FORMATS

Output
Clock

NRZ
Format

BI-Phase
J=ormat
Bit Bit
Idle Start a 3 4 5 6 7 Stop
Data 01001101 1$401

4·110
MC6801-MC6803-MC6803NR

ADDRESSING MODES tlons, the 256-byte area IS reserved for frequently referenced
S'X addressing modes can be used to reference memory data
A summary of addressing modes for all Instructions IS Extended Addressing - The second and third bytes of the
presented In Tables 9, 10, 11, and 12, where execution times Instruction contain the absolute address of the operand
are proVided In E-cycles Instruction execution times are These are three byte Instrutlons
summarized In Table 13 With an Input frequency of 4 MHz, Indexed Addressing - The unSigned offset contained In
E-cycles are eqUivalent to microseconds A cycle-by-cycle the second byte of the instruction IS added With carry to the
deSCription of bus activity for each instruction IS provided In Index Register and used to reference memory Without
Table 14 and a deSCription of selected Instructions IS shown changing the Index Register These are two byte Instruc-
In Figure 26 tions
Immediate Addressing - The operand or "Immediate Inherent Addressing - The operand(s) are registers and
byte(s)" IS contained In the following byte(s) of the Instruc- no memory reference IS reqUired These are Single byte In-
tion where the number of bytes matches the size of the structions
register These are two or three byte instructIOns Relative Addressing - Relative addreSSing IS used only for
Direct Addressing - The least Significant byte of the branch instructions If the branch conditIOn IS true, the Pro-
operand address IS contained In the second byte of the in- gram Counter IS overwritten With the sum of a Signed Single
struction and the most Significant byte IS assumed to be $00 byte displacement In the second byte of the Instruction and
Direct addreSSing allows the user to access $00 through $FF the current Program Counter ThiS proVides a branch range
uSing two byte Instructions and execution time IS reduced by of - 126 to 129 bytes from the fllst byte of the Instruction
eliminating the additional memory access In most applica- These are two byte instructIOns

.
TABLE 8 - CPU INSTRUCTION MAP

-. -. . .
t-
•
OP
00
MNEM MODE
- OP
14
MNEM
DES
MODE
INHfR 3 I
OP
68
MNEM
ASL
M DE
INDXD 6 2
OP
9C
MNEM
CPx Dl
---
MODE
5 2
OP
DO
MNEM
SUB8
MODE
DIR
-
3 2

I
01 NOP IN ER 2 I 35 TXS 3 I 69 ROL 6 2 90 JSR 5 2 01 (MPS 3 2
02 36 PSHA 3 I 6A DEC 6 2 9E LOS 4 2 02 S~CB 3 2
03 37 PSHB 3 I 6B 9f STS DIR 4 2 03 ADDD 5 2
04 LSAD 3 I 38 PULX 5 I 6C INC 6 2 40 SUBA INDXD 4 2 04 ANOS 3 2
Db ASLD 3 I 39 ATS 5 I 60 TST 6 2 AI CMPA 4 2 OS BITS 3 2
06 TAP 2 I 3A ABX 3 I fiE JMP 3 2 A2 seCA 4 2 06 LDAS 3 2
07 TPA 2 I 3B RTI 10 I 6F CLR INDXD 6 2 A3 SUBD 6 2 07 STAB 3 2
DB INX 3 I 3C PSHX 4 I 70 NEG fXTND 6 3 A4 ANDA 4 2 DB EORB 3 2

,,
09 DEX 3 I 3D MUL 10 I 71 A5 BITA 4 2 09 AceS 3 2
OA
DB
CLV
SEV ,
2 I
1
3E
3F
WAI
SWI
9
12
1
1
72
73 rOM 6 3
A6
A7
LOAA
STAA
4
4
2
2
OA
DB
ORAB
ADDs
3
I
DC CLC 2 1 40 NEGA 2 1 74 LSR 6 3 AB EORA 4 2 Dr I DO 4 I
00 SEC 2 1 41 75 A9 ADCA 4 2 DO "0 4
DE CLI 2 1 42 76 ROR 6 3 AA DRAA 4 2 DE lOX 4
,1
OF
10
SEI
SBA
2
2
1

,
1
43
44
COMA
LSRA ,
2 1
1
77
7B
ASR
ASL
6
6
3
3
AB
AC
ADDA
(PX
4
b
2
2
OF
ED
',IX
'>lJHII
( MPH
[JlIi
IMPH) ,1
., i
11 CBA 2 45 79 ROL 6 3 AD JSR b 2 F1 I
12
13
46
47
RORA
ASRA
2
2
I 17A
1 78
DEC 6 3 AE
M
LOS
STS INDXO ,
5 2
2
E2
E3
~B( B

AODD
4
b
I
)
\4 48 ASLA 2 1 7C INC 6 3 80 SUBA fXTND 4 7 E4 ANDB 4 2
15 49 ROLA 2 1 70 TS7 6 3 B1 ('MPA 4 3 E5 81T8 4 2
16 TAB ) 1 4A OECA 2 1 7[ JMP 3 3 82 SBCA 4 3 E6 LDAB 4 2
17 TBA 2 1 48 7F CLR I::XTND 6 3 B3 SUBD 6 3 E7 STAB 4 2
1B 4C INCA 2 1 80 SU8A IMMED 2 2 84 ANOA 4 3 E8 EORS 4 2
19 OAA tNHER 2 1 40 TSlA 2 1 81 CMPA 2 2 B5 elTA 4 3 E9 ADCB 4 2
1A 4E T 82 seCA 2 2 86 lOAA 4 3 EA DRAB 4 2
1B ABA INHER 2 I 4F ClRA 2 1 83 SUBD 4 3 87 51AA 4 3 EB ADDS 4 2
1C 50 NEGB 2 1 84 ANDA 7 2 88 EORA 4 3 EC LaD 5 2
10 51 85 BllA 7 2 B9 AO(A 4 3 EO STD 5 2
1E 52 86 LDAA 7 2 8A DRAA 4 3 EF LOX 5 2
1F 53 COMB 2 1 87 6B ADOA 4 3 EF ST> INoxa 5 2
20 ORA REL 3 2 54 LSRB 7 1 B8 tORA } 2 8e epx 6 3 EO SUBS fXTND 4 3
21 8RN 3 2 55 89 ADCA } 2 BO JSA 6 3 E1 CMPB 4 3
22 8HI 3 2 56 RaRB 2 I 8A ORAA 2 2 8E LOS 5 3 E2 sece 4 3
23 BLS 3 2 57 ASRB 2 1 8B ADOA 2 2 RF SIS EXl'ND 5 3 r3 ADDO 6 3
24 8CC 3 2 58 ASLB 2 1 8C (rx IMMH) 4 3 CO SUBS IMMED 2 2 F4 ANOS 4 3
c5 BITS 4

.
25 BCS 3 2 59 ROLS 2 1 80 BSR REL b 2 ('1 (MPB 2 2 3
26 8NE 3 2 5A OECB 2 I I BE LOS IMMED 3 3 ('2 sees 2 2 F6 LOAS 4 3
27 8EQ 3 2 58 C3 ADOO 4 3 F7 STAB 4 3
2B 8VC 3 2 5C INCB 2 I 90 SUBA 0" 3 2 e4 ANoe 2 7 f8 fORB 4 1
29 BVS 3 2 SO T516 2 I 91 CMPA 3 2 co BITS 2 2 F9 AOCB 4 3
2A 8PL 3 2 1 2 ('6 LOAS ) 2 FA aRAB 4 3
50 I 92 seCA
28
2C
8MI
BGE
3
3
2
2
5f
60
(LRB
NEG
INHEA
INoxa
2
b
1
2 ,.
93 sueD
ANDA
5
3
2
2
C7
C8
C9
EORB
ADCB
7
7
2
2
FB
FC
FD
ADDe
LaD
STO
4
5
5
3
3
3

I
20 8CT 3 2 61 95 elTA 3 2
2E 8GT 3 2 62 96 LOAA 3 2 eA DRAB 7 2 fE LOX 5 3
2F 8LE REL 3 2 63 COM 6 2 97 SlAA 1 2 C8 ADDS 7 2 FE STX EXTND 5 3
30 TSX INHER 3 1 64 LSR 6 2 98 fORA 3 2 ce WD 1 3

t
31 INS 3 1 AOCA 3 2 (0
65 99 UNDEFINfD OP (ODE
32 PULA 4 I 66 ROR 6 2 9A DRAA 3 2 C~ LOX IMMEO 3 3
33 PULB 4 1 67 ASR INDXD 6 2 98 ADDA 3 2 Cf
----- --------
NOTES
1 AddreSSing Modes
INHER '" Inherent INDXD", Indexed IMMED", Immediate
REL", Relative EXTND", Extended DIR",Dlfect
Unassigned opcodes are IndIcated by "*,, and should not be executed
Codes marked by "T" force the PC to functIon as a 16-blt counter

4-111
 MC6801· MC6803· MC6803N R

TABLE 9 - INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS

Immed Direct Index Extnd Inherent

Condition Codes
5 4 3 2 0 ,
Pointer Operations

Compare Index Reg

Mnemonic OP- # OP- # OP- # OP- # OP- #

CPX 8C 4 3 9C 5 2 AC 6 2 BC 6 3 M +1
Boolean/
Anthmetic Operation
!< - M
H I N Z V C

• • ·11
II I i
,
Decrement Index Reg DEX 09 3 1 X -1 -X
•• I ••
Decrement Stack Pntr DES 34 3 1 sp - 1 -SP
• • ·It
••••
Increment Index Reg INX 08 3 1 X + 1 -X
•• ••
Increment Stack Pntr INS 31 3 1 1 SP + 1 SP
••••••
Load Index Reg LDX CE 3 3 DE 4 2 EE 5 2 FE 5 3 M -XH, 1M + 1)--XL
•• R • R
Load Stack Pntr LDS 8E 3 3 9E 4 2 AE 5 2 BE 5 3 M -SPH, 1M + 1) --SPL
•• •
Store Index Reg STX DF 4 2 EF 5 2 FF 5 3 XH -M, XL -1M + 11
•• R •
Store Stack Pntr STS 9F 4 2 AF 5 2 BF 5 3 SPH -M, SPL -1M + 1)
•• • R
Index Reg - Stack Pntr TXS 35 3 1 X - 1 -SP
••••••
Stack Pntr - Index Reg TSX 30 3 1 SP + 1 -X
•• •• • • • •
• • •• • " •
Add
Push Data
ABX
PSHX
3A 3
3C 4
1 B +X-X
1 XL -MSp, SP - 1 -SP
•••
XH -MSR SP - 1~SP

••••••
II
Pull Data PULX 38 5 1 SP + 1 -SP, MSp -XH
SP + 1 -SP, MSp --XL

TABLE 10 - ACCUMULATOR AND MEMORY INSTRUCTIONS

Accumulator and Immed Direct Index Extend '"her Boolean Condition Codes
Memory Operations MNE Op # Op # Op - # Op # Op # Expression H I N Z V C

• •• • • • •
Add Acmltrs ABA 18 2 1 A +8-A I I
AddBtoX ABX 3A 3 1 OOB+X-X

•••
Add with Carry ADCA 89 2 2 99 3 2 A9 4 2 89 4 3 A+M+C-A
ADCB C9 2 2 D9 3 2 E9 4 2 F9 4 3 B+M+C-B
Add ADDA 88 2 2 9B 3 2 AB 4 2 BB 4 3 A +M -A

• •••
ADOB CB 2 2 OB 3 2 EB 4 2 FB 4 3 B + M-A
Add Double ADDD C3 4 3 D3 5 2 E3 6 2 F3 6 3 D + M M + 1-D

••• •• ••
And ANDA 84 2 2 94 3 2 A4 4 2 B4 4 3 A·M-A R

--
ANDB C4 2 2 D4 3 2 E4 4 2 F4 4 3 B' M --8 R
Shift Left, ASL 68 6 2 78 6 3 J j
Arithmetic ASLA
ASLB
48 2 1
58 2 1
&)-...IIIIIIIII+-o
b7 bO •• •• I
~ Contmued-

4·112
MC6801·MC6803·MC6803NR

TABLE 10 - ACCUMULATOR AND MEMORY INSTRUCTIONS (CONTINUED)

Accumulator and Immed Diract Index Extend Inher Boolean Condition Cod••
Memory Operations MNE
Op - # Op # Op - # Op -
# Op - # Expression H N Z V C
Shift Left Dbl ASLD 05 3 1
Shift Right, ASR 67 6 2 77 6 3
Arithmetic ASRA 47 2 1 qlllli III+El
b7 bO
ASRB 57 2 1
Bit Test BITA
BITB
85 2 2 95 3 2 A5 4 2 B5 4 3
C5 2 2 D5 3 2 E5 4 2 F5 4 3
A'M
B'M
R
R
••
Compare Acmltrs CBA 11 2 1 A-B I I
Clear CLR 6F 6 2 7F 6 3 OO-M R S R R
CLRA 4F 2 1 OO-A R S R R
CLRB 5F 2 1 OO-B R S R R
Compare CMPA B1 2 2 91 3 2 A1 4 2 B1 4 3 A-M I
CMPB C1 2 2 D1 3 2 E1 4 2 F1 4 3 B-M I
"s Complement COM 63 6 2 73 6 3 IM-M R S
COMA 43 2 11A"-A R S
COMB 53 2 1 'IJ-B R S
Decimal Adj, A DAA 19 2 1 Adj binary sum to BCD

•••
Decrement DEC 6A 6 2 7A 6 3 M-1-M
DECA 4A 2 1 A-1-A
DECB 5A 2 1 B-1 -B
Exclusive OR EORA BB 2 2 98 3 2 AB 4 2 BB 4 3 A @ M-A R
•
•••
EORB CB 2 2 DB 3 2 E8 4 2 FB 4 3 B @ M-B f R
Increment INC 6C 6 2 7C 6 3 M+ 1-M II

Load Acmltrs

Load Double
INCA
INCB
LDAA
LDAB
LDD
B6 2 2 96 3 2 A6 4 2 B6 4 3
C6 2 2 D6 3 2 E6 4 2 F6 4 3
CC 3 3 DC 4 2 EC 5 2 FC 5 3
4C 2 1 A + 1-A
5C 2 1 B + 1-B
M-A
M-B
M M+ 1-D
R
R
R
••
•• I
logical Shift,
Left
LSL
LSLA
LSLB
LSLD
6B 6 2 7B 6 3
4B 2 1
5B 2 1
05 3 1
--
0 ...... 11111111'-0
b7 bO

Shift Right, LSR 64 6 2 74 6 3 -+ R

logical LSRA 44 2 1 0"1111 II II J.+EJ R
b7 bO
LSRB 54 2 1 R
LSRD 04 3 1 R
Multiply
2'5 Complement
MUL
NEG 60 6 2 70 6 3
3D 10 1 AXB-D
00- M-M
•••Ii
(Negate) NEGA 40 2 1 00 - A-A I
NEGB 50 2 1 00 - B-B I I
No Operation
InclUSIVe OR
NOP
ORAA 8A 2 2 9A 3 2 AA 4 2 BA 4 3
01 2 1 PC + 1 -PC
A+M-A
• • • ••
I R

•• •• •• •••
ORAB CA 2 2 DA 3 2 EA 4 2 FA 4 3 B+ M-B I R
Push Data PSHA 36 3 1 A -Stack
PSH8 37 3 1 B --Stack
Pull Data PULA 32 4 1 Stack -A
•• • • ••
Rotate Left
PULa
ROL
ROLA
69 6 2 79 6 3
33 4 1 Stack -B

-
49 2 1 g..H Ii " i II H-m
I I
I
•• I
I

-
b7 bO
ROLB 59 2 1 I
Rotate Right ROR 66 6 2 76 6 3 I
RORA 46 2 1 ~11i1!11~
RORB 56 2 1 b7 bO

Subtract Acmltr SBA 10 2 1 A-B-A

Subtract With SBCA 8212 2 92 3 A2 4 2 B2 4 3 A-M-C-A
Carry SBCB C2 2 2 D2 3 2 E2 4 2 F2 4 3 B-M C-B
Store Acmltrs STAA
STAB
97 3 2 A7 4 2 B7 4 3
D7 3 2 E7 4 2 F7 4 3
A-M
B-M
R
R
••
Subtract
STD
SUBA
DD 4 2 ED 5 2 FD 5 3
80 2 2 90 3 2 AO 4 2 BO 4 3
D -MM + 1
A-M-A
R
I II
•
SUBB CO 2 2 DO 3 2 EO 4 2 FO 4 3 B-M-B 'j
Subtract Double SUBD 83 4 3 93 5 2 A3 6 2 83 6 3 D - MM + 1-D t I
Transfer Acmltr TAB
TBA
1b ~
17 2 1 B-A
A-8 R
R ••
Test, Zero or TST 6D 6 2 7D 6 3 M -00 R R
MinUS TSTA 4D 2 1 A-OO R R
TSTB 5D 2 1 B - 00 I R R
The Condition Code Register notes are listed after Table 10

4·113
 MC6801·MC6803·MC6803NR

TABLE 11 - JUMP AND BRANCH INSTRUCTIONS

R.lative
Direct Index Extnd Inheren
Condo Code Reg.
Ii 4 3 2 0 ,
Operations Mnemonic OP -# OP- # OP- # OP - # OPr- Branch Test H I N Z V C

•••• •
• • • • •• •
Branch Alwavs BRA 203 2 None
Branch Never BRN 21 3 2 None

•• •
•• • •• •• • ••
Branch If Carry Clear BCC 24 3 2 C=O
Branch If Carry Set BCS 25 3 2 C=1
Branch If = Zero BEQ 27 3 2 Z=1
•••••
Branch If "" Zero BGE 2C 3 2 N$V=O
••••••
•••••
• • • • • ••
Branch If > Zero BGT 2E 3 2 Z+(N$V)=O
Branch If Higher BHI 22 3 2 C+Z=O
Branch If Higher or Same BHS 24 3 2 C=G
• •••• •
•••••
•• • • • • ••
Branch If < Zero BlE 2F 3 2 Z+(N$V)= 1
Branch If Carry Set BLO 25 3 2 C- 1
Branch If lower Or Same
Branch If < Zero
BlS
BlT
23 3 2
203 2
C+Z =1
N$V= 1
•••••
••••••
•••••
• • • • • ••
Branch If Minus BMI 2B 3 2 N -1
Branch If Not Equal Zero BNE 26 3 2 Z-O

• ••••••
Branch If Overflow Clear BVC 2B 3 2 V=O
Br anch If Overflow Set BVS 29 3 2 V=1
••••••
Branch If Plus BPl 2A 3 2 N=O
••••••
Branch To Subroutme BSR 806 2
} See Special ••••••
•••• •
• • • • •• •
Jump JMP 6E 3 2 7E 3 3 Operations ~

Jump To Subroutine JSR 905 2 lAD 6 2 BD 6 3 Figure 26

No OperallOn NOP 01 2 1
• • • •I • •
Return From Interrupt RTI 3B 0 1
I II il II II
!
Return From Subroutme RTS 39 5 1 } See Special
1 Operations· ••••••
Software Interrupt SWI 3F 2 Figure 26 • ••••
S
Walt For Interrupt WAI 3E 9 1
• •• • • •
TABLE 12 - CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS

Inherent
Cond Code Reg
5 4 3 2 0 ,
Operattons Mnemonic OP - # Boolean Operation H I N Z V C
Clear Carry ClC OC 2 1 O-C
••••• R
Clear Interrupt Mask CLI OE 2 1 0-1
• ••••
R
••• •
• • • •• •
Clear Overflow ClV OA 2 1 O-V R
Set Carry SEC 002 1 1-C S
Set Interrupt Mask SEI OF 2 1 ,1-1
• ••••
S
Set Overflow
Accumulator A -CCR
SEV
TAP
OB 2
06 2
1
1
1 -V
A -CCR
•I II• •, •I I I
S •

CCR -Accumulator A TPA 07 2 1 CCR -A

••••••
LEGEND CONDITION CODE SYMBOLS
OPOperatlon Code (Hexadecimal) H Half·carrv'from bit 3
- Number of MPU Cvcles I Interrupt mask
MSp Contents of memory locallon pOinted to bV Stack POinter N Negative (sign bit)
# Number of Program Bytes Z Zero (byte)
+ ArithmetiC Plus V Overflow, 2's complement
- ArithmetIC MinUS C Carry/Borrow from M&B
• Boolean AND R Reset Alwavs
X ArithmetiC MultlplV S Set Alwavs
+ Boolean InclUSive OR I Affected
$ Boolean ExclUSive OR • Not Affected
!iii Complement of M
-- Transfer Into
OBit = Zero
00 Byte = Zero

4·114
MC6801· MC6803· MC6803N R

TABLE 13 - INSTRUCTION EXECUTION TIMES IN E-CYCLES

ADDRESSING MODE ADDRESSING MODE

! .
'ii
."
"c ." ;:
..,".>
$
.
.,
'ii
.,
."
." .,
."
~
C
"
.~
E"
~

"f
."
"
)( f
E
lJ c
$)(
.,
)(
~ .!!
.E 0 ~
w
"
."
E E
"
.r:: a;
a: .E 0
f
w
."
E
.r::
E "
ABA
• •• •• • 2
•• INX
••• •• • • 3
•2 • •••
ABX 3 JMP 3 3
ADC 3 4 4
•• • JSR 5 6 6

•••
ADD 2 3 4 4 LOA 2 3 4 4
ADDD
AND
4
2
5
3
6
4
6
4
•
•2
LDD
LOS
3
3
4
4
5
5
5
5
••
••• ••• •• •2
ASL 6 6 LOX 3 4 5 5
ASLD •6 •6 3 LSL
•
•
•• 6
•6 •
6
ASR
•• •• ••
2
•3 LSLD
•
3
• ••
BCC LSR 6 2
••
••• ••• ••6
BCS 3 LSRD 3
BEQ
•• •• •••
3 MUL
•• 10

•••
BGE 3 NEG 6 2

•
BGT
•• •• •••
3 NOP
•2 •3 • • 2
•
••
BHI 3 QRA 4 4
BHS
•2 • •
3 PSH
•• • •• •
••
3
•••
••
BIT 3 4 4 PSHX 4
•• •• •• •
••• ••
BLE 3 PUL 4
BLO 3 PULX
•• •6 • 5
••
•• • •• ••
BLS 3 ROL 6 2
BLT
• • 3 ROR
•••
6 6 2
••
•• ••• ••• •• ••• ••• •• ••
BMI 3 RTI 10
BNE 3 RTS 5
BPL
•• •••
3 SBA
•3 • • 2

•• •• • •• •
BRA 3 SBC 2 4 4
BRN
•• • • ••
3 SEC
••• •• ••
2

•••
BSR 6 SEI 2
BVC
• ••• •• ••2
3 SEV
• • • • 2

••• •••
BVS 3 STA 3 4 4

••• •• •• •••
CBA STD 4 5 5

•••
CLC 2 STS 4 5 5
CLI
CLR
•• 6
•6 2
2
STX
SUB
•
2
4
3
5
4
5
4
•
CLV
• • • • 2 SUBD 4 5 6
•• •• •
6
•2 • •••
CMP 2 3 4 4 SWI 12
COM
• •5 6 6 TAB
•• •• ••
2
CPX 4
•• ••
6
•
6
•2 TAP 2
•6 ••• •••
DAA TBA 2
DEC
DES
• ••
6
•• •
2
3
TPA
TST
•6 •6 2
2
DEX
• • 3 TSX
••
••• •• • 3
•• ••
EOR 2 3 4 4 TXS 3
INC
INS
•• •• 6
•
6
• 3
WAI
• • 9

4-115
 MC6801·MC6803-MC6803NR

SUMMARY OF CYCLE-BY-CYCLE OPERATION

Table 14 provides a detailed description of the information per instruction In general, instructions with the same ad-
present on the Address Bus, Data Bus, and the Read/Write dressing mode and number of cycles execute In the same
(R/W) line dUring each cycle of each Instruction manner Exceptions are indicated In the table
The Information IS useful In comparing actual with ex- Note that dUring MPU reads of Internal locations, the
pected results dUring debug of both software and hardware resultant value will not appear on the external Data Bus ex-
as the program IS executed. The information IS categorized In cept In Mode a "High order" byte refers to the most signifi-
groups according to addressing mode and number of cycles cant byte of a 16·blt value

TABLE 14 - CYCLE·BY·CYCLE OPERATION

Address Mode & R/W

Address Bus Data Bus
Instructions line
IMMEDIATE
ADC EOR 2 1 Op Code Address 1 Dp Code
ADD LDA 2 Op Code Address + 1 1 Operand Data
AND ORA
BIT SBC
CMP SUB

•
LOS 3 1 Op Code Address 1 Op Code
LOX 2 Op Code Address + 1 1 Operand Data (High Order Byte)
LDD 3 Op Code Address + 2 1 Operant.: Data (Low Order Byte)
CPX 4 1 Op Code Address 1 Op Code
SUBD 2 Op Code Address + 1 1 Operand Data (High Order Byte)
ADDD 3 Op Code Address + 2 1 Operand Data (Low Order Byte)
4 Address Bus FFFF 1 Low BytE' of Restart Vector
DIRECT
ADC EOR 3 1 Op Code Address 1 Op Code
ADD LOA 2 Op Code Address + 1 1 Address of Operand
AND ORA 3 Address of Operand 1 Operand Data
BIT SBC
CMP SUB
STA 3 1 Op Code Address 1 Op Code
2 Op Code Address + 1 1 Destination Address
3 Destination Address 0 Data from Accumulator
LOS 4 1 Op Code Address 1 Op Code
LOX 2 Op Code Address + 1 1 Address of Operand
LDD 3 Address of Operand 1 Operand Data (High Order Byte)
4 Operand Address + 1 1 Operand Data (Low Order Byte)
STS 4 1 Op Code Address 1 Op Code
STX 2 Op Code Address + 1 1 Address of Operand
STD 3 Address of Operand 0 Register Data (High Order Byte)
4 Address of Operand + 1 0 Register Data (Low Order Byte)
CPX 5 1 Op Code Address 1 Op Code
SUBD 2 Op Code Address + 1 1 Address of Operand
ADDD 3 Operand Address 1 Operand Data (High Order Byte)
4 Operand Address + 1 1 Operand Data (Low Order Byte)
5 Address Bus 'FFFF 1 Low Byte of Restart Vector
JSR. 5 1 Op Code Address 1 Op Code
2 Op Code Address + 1 1 Irrelevant Data
3 Subroutine Address 1 Fn st Subroutine Op Code
4 Stack POinter 0 Return Address (Low Order Byte)
5 Stack Pomter + 1 0 Return Address(Hlgh Order Byte)

- Contmued-

4-116
MC6801-MC6803- MC6803N R

TABLE 14 - CYCLE-BY-CYCLE OPERATION (CONTINUED)

Address Mode & R/W

Instructions Address Bus line Data Bus

EXTENDED
JMP 3 1 Op Code Address 1 Op Code
2 Op Code Address + 1 1 Jump Address (High Order Byte)
3 Op Code Address + 2 1 Jump Address (Low Order Byte)
ADC EOR 4 1 Op Code Address 1 Op Code
ADD LOA 2 Op Code Address + 1 1 Address of Operand
AND ORA 3 Op Code Address + 2 1 Address of Operand
(Low Order Byte)
BIT SBC 4 Address of Operand 1 Operand Data
CMP SUB
STA 4 1 Op Code Address 1 Op Code
2 Op Code Address + 1 1 Destination Address
(High Order Byte)
3 Op Code Address + 2 1 Destmatlon Address
(Low Order Byte)
4 Operand Destmatlon Address 0 Data from Accumulator

•
LOS 5 1 Op Code Address 1 Op Code
LOX 2 Op Code Address + 1 1 Address of Operand
(High Order Byte)
LDD 3 Op Code Address + 2 1 Address of Operand
(Low Order Byte)
4 Address of Operand 1 Operand Data (High Order Byte)
5 Address of Operand + 1 1 Operand Data (Low Ortier Byte)
STS 5 1 Op Code Address 1 Op Code
STX 2 Op Code Address + 1 1 Address of Operand
(High Order Byte)
STD 3 Op Code Address + 2 1 Address of Operand
(Low Order Byte)
4 Address of Operand 0 Operand Data (High Order Byte)
5 Address of Operand + 1 0 Operand Data (Low Order Byte)
ASL LSR 6 1 Op Code Address 1 Op Code
ASR NEG 2 Op Code Address + 1 1 Address of Operand
(High Order Byte)
CLR ROL 3 Op Code Address + 2 1 Address of Operand
(Low Order Byte)
COM ROR 4 Address of Operand 1 Current Operand Data
DEC TST 5 Address Bus FFFF 1 Low Byte of Restart Vector
INC 6 Address of Operand 0 New Operand Data
CPX 6 1 Op Code Address 1 Op Code
SUBD 2 Op Code Address + 1 1 Operand Address
(High Order Byte)
ADDD 3 Op code Address + 2 1 Operand Address
(Low Order Byte)
4 Operand Address 1 Operand Data (High Order Byte)
5 Operand Address + 1 1 Operand Data (Low Order Byte)
6 Address Bus FFFF 1 Low Byte of Restart Vector
JSR 6 1 Op Code Address 1 00 Code
2 Op Code Address + 1 1 Address of Subroutine
(High Order Byte)
3 Op Code Address + 2 1 Address of Subroutine
(Low Order Byte)
4 Subroutine Starting Address 1 Op Code of Next InstructIon
5 Stack POInter 0 Return Address
(Low Order Byte)
6 Stack POInter - 1 0 Return Address
High Order Byte)

- Contmued-

4·117
 MC6801- MC6803- MC6803NR

TABLE 14 - CYCLE-BY-CYCLE OPERATION (CONTINUED)

Address Mode &

Address Bus
RIW Data Bus
Instructions line
INDEXED
JMP 3 1 Op Code Address 1 Op Code
2 Op Code Address + 1 1 Offset
3 Address Bus FFFF 1 Low Byte of Restart Vector
ADC EOI'! 4 1 Op Code Address 1 Op Code
ADD LDA 2 Op Code Address + 1 1 Offset
AND OAA 3 Address Bus FFFF 1 Low Byte of Restart Vector
BIT SBC 4 Index Aeglster Plus Offset 1 Operand Data
CMP SUB
STA 4 1 Op Code Address 1 Op Code
2 Op Code Address + 1 1 Offset
3 Address Bus FFFF 1 Low Byte of Restart Vector
4 Index RegIster Plus Offset 0 Operand Data
LDS 5 1 Op Code Address 1 Op Code
LDX 2 Op Code Address + 1 1 Offset
LDD 3 Address Bus FFFF 1 Low Byte of Restart Vector
4 Index Regls!er Plus Offset 1 Operand Data (H Igh Order Byte)

•
5 Index Register Plus Offset + 1 1 Operand Dat .. (Low Order Byte)
STS 5 1 Op Code Address 1 Op Code
STX 2 Op Code Address + 1 1 Offset
STD 3 Address Bus FFFF 1 Low Byte of Restart Vector
4 Index Aeglster Plus Offset 0 Operand Data (HIgh Order Byte)
5 Index Aeglster Plus Offset + 1 0 Operand Data (Low Order Byte)
ASL LSR 6 1 Op Code Address 1 Op Code
ASA NEG 2 Op Code Address + 1 1 Offset
CLA AOL 3 Address Bus FFFF 1 Low Byte of Restart Vector
COM ROA 4 Index RegIster Plus Offset 1 Current Operand Data
DEC TST (I) 5 Address Bus FFFF 1 Low Byte of Restart Vector
INC 6 Index Aeglster Plus Offset 0 New Operand Data
CPX 6 1 Op Code Address 1 Op Code
SUBD 2 Op Code Address + 1 1 Offset
ADDD 3 Address Bus FFFF 1 Low Byte of Restart Vector
4 Index Register + Offset 1 Operand Data (HIgh Order Byte)
5 Index Aeglster + Offset + 1 1 Operand Data (Low Order Byte)
6 Address Bus FFFF Low Byte of Restart Vector
JSR 6 1 Op Code Address 1 Op Code
2 Op Code Address + 1 1 Offset
3 Address Bus FFFF 1 Low Byte of Aestart Vector
4 Index Aeglster + Offset 1 First Subroutme Op Code
5 Sta ck POinter 0 Return Address (Low Order Byte)
6 Stack POInter - 1 0 Aeturn Address (HIgh Order Byte)

- Contlnued-

4-118
MC6801-MC6803-MC6803NR

TABLE 14 - CYCLE-BY-CYCLE OPERATION (CONTINUED)

Addres. Mode 80 R/W

Address Bus Data Bus
Instructions Line
INHERENT
ABA DAASEC 2 1 Op Code Address 1 Op Code
ASL DEC SEI 2 Op Code Address +1 1 Op Code of Next Instruction
ASR INC SEV
CBA LSR TAB
CLC NEG TAP
CLI NOP TBA
CLR ROL TPA
CLV ROR TST
COM SBA
ABX 3 1 Op Code Address 1 Op Code
2 Op Code Address +1 1 Irrelevent Data
3 Address Bus FFFF 1 Low Byte of Restart Vector
ASLD 3 1 Op Code Address 1 Op Code
LSRD 2 Op Code Address +1 1 Irrelevant Data
3 Address Bus FFFF 1 Low Byte of Restart Vector
DES 3 1 Op Code Address 1 Op Code
INS 2 Op Code Address +1 1 Op Code of Next Instruction

INX
DEX

PSHA
PSHB
3

3
3
1
2
3
1
2
PrevIous Register Contents
Op Code Address
Op Code Address +1
Address Bus FFFF
Op Code Address
Op Code Address +1
1
1
1
1
1
1
Irrelevant Data
Op Code
Op Code of Next Instrucllon
Low Byte of Restart Vector
Op Code
Op Code of Next Instruction
II
3 Stack POinter 0 Accumulator Data
TSX 3 1 Op Code Address 1 Op Code
2 Op Code Address +1 1 Op Code of Next Instruction
3 Stack POinter 1 Irrelevant Data
TXS 3 1 Op Code Address 1 Op Code
2 Op Code Address +1 1 Op Code of Next InstrUClion
3 Address Bus FFFF 1 Low Byte of Restart Vector
PULA 4 1 Op Code Address 1 Op Code
PULB 2 Op Code Address +1 1 Op Code of Next Instruction
3 Stack POinter 1 Irrelevant Data
4 Stack POinter +1 1 Operand Data from Stack
PSHX 4 1 Op Code Address 1 Op Code
2 Op Code Address +1 1 Irrelevant Data
3 Stack Pomter 0 Index Register (Low Order Byte)
4 Stack POinter - 1 0 Index Register (High Order Byte)
PULX 5 1 Op Code Address 1 Op Code
2 Op Code Address +1 1 Irrelevant Data
3 Stack POinter 1 Irrelevant Data
4 Stack POinter +1 1 Index Register (High Order Byte)
5 Stack POinter +2 1 Index Register (Low Order Ih'!e)
- Continued -

4·119
 MC6801-MC6803-MC6803NR

TABLE 14 - CYCLE-BY-CYCLE OPERATION (CONTINUED)

Address Mode 80 R/W

Address Bus Line Data Bus
Instructions
INHEElENT
RTS 5 1 Op Code Address 1 Op Code
2 Op Code Address +1 1 Irrelevant Data
3 Stack POinter 1 Irrelevant Data
4 Stack POinter +1 1 Address of Next Instruction
(High Order Byte)
5 Stack POinter +2 1 Address of Next Instruction
(Low Order Byte)
WAI 9 1 Op Code Address 1 Op Code
2 Op Code Address +' 1 Op Code of Next Instruction
3 Stack POinter 0 Return Address (Low Order Byte)
4 Stack POinter -1 0 Return Address
(High Order Byte)
5 Stack POinter -2 0 Index Register (Low Order Byte)
6 Stack POinter -3 0 Index Register (High Order Byte)
7 Stack POinter -4 0 Contents of Accumulator A
8 Stack POinter -5 0 Contents of Accumulator B
9 Stack POinter -6 0 Contents of Cond Code Register
MUL ,0 1 Op Code Address 1 Op Code

II 2
3
4
5
6
7
8
Op Code Address +,
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
1
1
1
1
,,
1
Irrelevant Data
Low Byte of Restart Vector
Low
Low
Low
Low
Byte
Byte
Byte
Byte
of
of
of
of
Restart
Restart
Restart
Restart
Low Byte of Restart Vector
Vector
Vector
Vector
Vector

9 Address Bus FFFF 1 Low Byte of Restart Vector

10 Address Bus FFFF 1 Low Byte of Restart Vector
RTI 10 1 Op Code Address 1 Op Code
2
3
Op Code Address +1
Stack POinter ,
1 Irrelevant Data
Irrelevant Data
4 Stack POinter +' 1 Contents of Cond Code Reg
from Stack
5 Stack POinter +2 1 Contents of Accumulator B

6 Stack POinter +3 , from Stack

Contents of Accumulator A
from Stack
7 Stack POinter +4 1 Index Register from Stack
(High Order Byte)
8 Stack POinter +5 1 Index Register from Stack
(Low Order Byte)
9 Stack POinter +6 1 Next Instruction Address from
Stack (High Order Byte)
10 Stack POinter +7 1 Next Instruction Address from
Stack (Low Order Byte)
SWI 12 1 Op Code Address 1 Op Code
2 Op Code Address +1 1 Irrelevant Data
3 Stack POinter 0 Return Address (Low Order Byte)
4 Stack POinter -1 0 Return Address
(High Order Byte)
5 Stack POinter -2 0 Index Register (Low Order Byte)
6 Stack POinter -3 0 Index Register (High Order Byte)
7 Stack POinter -4 0 Contents of Accumulator A
8 Stack POinter :5 0 Contf.:nts of Accumulator B
9 Stack POinter -6 0 Contents of Cond Code Register
10 Stack POinter -7 1 Irrelevant Data
11 Vector Address FFFA (Hex) 1 Address of Subroutine
(High Order Byte)
12 Vector Address FFFB (Hex) 1 Address of Subroutine
(Low Order Byte)
- Continued -

4-120
MC6801- MC6803- MC6803N R

TABLE 14 - CYClE-BY-CYClE OPERATION (CONCLUDED)

Address Mode & R/W

Address Bus Data Bus
Instructions Line
RELATIVE
BCC BHT BNE BlO 3 1 Op Code Address 1 Op Code
BCS BlE BPl BHS 2 Op Code Address + 1 1 Branch Offset
BEQ BlS BRA BRN 3 Address Bus FFFF I Low Byte of Restart Vector
BGE BlT BVC
BGT BMT BVS
BSR 6 1 Op Code Address 1 Op Code
2 Op Code Address + 1 1 Branch Offset
3 Address Bus FFFF I Low Byte of Restart Vector
4 Subroutine Starting Address 1 Op Code of Next Instruction
5 Stack POinter a Return Address (Low Order Byte)
6 Stack Pomter -1 0 Return Address (High Order Byte)

4-121
 MC6801- MC6803- MC6803NR

FIGURE 26 - SPECIAL OPERATIONS

JSR Jume to Subroutine

!'(;

Direct
{ RTN

SE Stack

{ ~SP-2~
~

c:=>
lNDXO SP _ 1 RTNH

RTN SP RTNL

Main Program
EC sao - J$R

EXTND
{ RTN
SH == Subr Addr

SL - Subr Addr

Next Mam Instr

eSR Branch To Subroutme

~Sp~~S"Ck

• SWI. Software Interrupt

RTN

RTS, Return from Subroutine

!'(;
Subroutine

"-';""'3:-9-'0'::R:::Ts'-'1 c>
~ SP + 2
SP - 1

SP + 1
SP

;~Stack
ATNH

RTNL

RTNH

RTNl

IT
RTN
Main Program

~--t
$3F;;;SWI I L-y'~ -"SP-7
SP - 6
S,P Slack

Condition Code

SP - 5 Acmltr B

SP - 4 Acmltr A
SP 3 lndex Register (X H)

c:=>
WAI. Wall for Interrupt
Main Program Index Register (XL)

--II
SP - 2

f-'_3_Eo_W_A_' SP - 1 RTNH
RTN SP RTNL

Rn Returl"' from Interrupt

Stack
Sf'
ff SP
SP + 1 Condition Code

SP + 2 Acmllr B

SP + 3 Acmltr A

SP t 4 Index Reglstel (XH)

SP + 5 ~ndex Register (XU

SP + 6 RTNH
-)I... SP ... 7 RTNL

JMP. Jump

{~b":-:::-::-::::::::::-1
ff

INOXD { '''ended

X +K Next InstructIOn I
K I Next InstructIOn
Legend
RTN = Address of next ,nstructlOn In Main Program to be executed upon rpturn from subroutine
RTNH = Most SIgnIfIcant byte of Return Address
RTNl ;;:; least slgmflcant byte of Return Address
--= Stack POlOter After ExecutIon
K = 8·1>11 UnSIgned Value

4-122
MC6801-MC6803-MC6803NR

APPENDIX
CUSTOM MC6801 ORDERING INFORMATION

A.O CUSTOM MC6801 ORDERING INFORMATION data}, may be submitted for pattern generation The
The custom MC6801 specifications may be transmitted to MC2708s must be clearly marked to ,nd,cate which PROM
Motorola In any of the follOWing media corresponds to which address space ($X800-$XFFF) See
1} PROM(s} Figure A-1 for recommended marking procedure
After the PROM(s} are marked, they should be placed In
2} MOOS diskette
conductive I C carners and securely packed 00 not use
styrofoam
The specificatIOn should be formatted and packed, as in-
dicated In the appropnate paragraph below, and mailed
prepaid and Insured with a cover letter (see Figure A-2) to'

Motorola Inc ~ ~
6d ~
3501 Ed Bluestein Blvd
AUStin, Texas 7B721

FIGURE A-1 XXX= Customer 10

A copy of the cover letter should also be mailed separately
A.2 DISKETTE (MOOS)
A.1 PROMs

II
The start/end location should be written on the label EX-
MCM270B and MCM2716 type PROMs, programmed With
ORclsor format
the custom program (positive logiC sense for address and

FIGURE A-2

CUSTOMER NAME
ADDRESS ___________________________________________________________________

STATE ___________________________ CITY _______________________ ZIP _________

PHONE ( _ _ ) _____________________________ EXTENSION ___________________________

CONTACT MS/MR

CUSTOMERPART# _________________________________________________________________

ROM START ADDRESS OPTION TEMPERATURE RANGE

oSCBOO 00° to 70°C
o $DBOO
o SEBOO
o $F800
o A12 and A13 don't care PACKAGE TYPE
o Geramlc
o PlastiC

MARKING
PATTERN MEDIA o Standard
02708 PROM o Special
02716 PROM
o Diskette (MOOS)
(Note 1) _______________________________________________________________

NOTE: (1) Other Media ReqUire Prior Factory Approval

SIGNATURE ___________________________________________________________________
TITLE _______________________________________________________________________

4-123
 MC6801. MC6803· MC6803N R

r-----MC6801 L 1 -. LlL8ug ™ Monitor _ _ _ _...

An MC6801 may be purchased without specifYing the

ROM pattern This standard part IS labeled as MC6801 L 1
and contains a 2K monitor In the ROM The monitor,
LlLbug, may be used to evaluate and debug a program
under development Details and a source listing are
specified In the "LlLbug Manual"

• IMPORTANT NOTICE
Devices made with mask #T5P may generate multiple framing error
flags In response to unframed data These devices will eventually syn·
chronlze correctly after a framing error, but valid, framed data following
an unframed data byte may generate false framing error flags

4-124
 ® MOTOROL.A
MC6S02
MC6S0S
MC6S02NS
MICROPROCESSOR WITH CLOCK AND OPTIONAL RAM

The MC6802 IS a monolithic 8-blt microprocessor that contains all the

MOS
registers and accumulators of the present MC6800 plus an Internal clock
OSCillator and dnver on the same chip In additIOn, the MC6802 has 128 IN-CHANNEL, SILICON-GATE,
bytes of on-board RAM located at hex addresses $0000 to $007F The DEPLETION LOAD)
first 32 bytes of RAM, at hex addresses $0000 to $001 F, may be retained
In a low power mode by utiliZing VCC standby, thus, faCIlitating MICROPROCESSOR
memory retention dunng a power-down situation WITH CLOCK AND OPTIONAL RAM
The MC6802 IS completely software compatible With the MC6800 as
well as the entire M6800 family of parts Hence, the MC6802 IS expand-
able to 64K words
The MC6802NS IS Identical to the MC6802 Without standby RAM
feature The MC6808 IS Identical to the MC6802 Without on-board
RAM
• On-Chip Clock Circuit
• 128x8 Bit On-Chip RAM
• 32 Bytes of RAM are Retalnable
• Software-Compatible With the MC6800

•
• Expandable to 64K Words
• Standard TTL-Compatible Inputs and Outputs
• 8-Blt Word Size
• 16-Blt Memory AddreSSing
• Interrupt Capability
PART NUMBER DESIGI'!ATION BY SPEED
MC6802 MC6808 MC6802NS
(10 MHzl (10 MHzl (10 MHzl
PIN ASSIGNMENT
MC68A02 MC68A08
(15 MHzl (15 MHzl VSS RESET
MC68B02 MC68B08 HALT EX TAL
(20 MHzl (20 MHzl '.1R XTAL

TYPICAL MICROCOMPUTER VMA RE"

Vec VCC Vce Vec NMI V CC Standby'
R,W
Vec DO

iiiQ AD DI
Counter/ ~
Timer 1/0 MR Al D2
REsTI VMA VMA A2 D3
Clock E RE A3 D4

..
Riw
RiwMC6802 NMI

, ," \
A4 D5
MPU
A5 D6
1/0 DO-D7 DO-D7
EXTAL D7
A6
CJ A7 A15
Control { AO-A15 AO-AI5 XTAL
A8 AlA
A9 AI3
AlO 19 AI2
ThiS block diagram shows a typical cost effective microcomputer The MPU 15
the center of the mlcrocoputer system and IS shown In a minimum system Inter- All VSS
faCing With a ROM combination chip It IS not Intended that thiS system be
limited to thiS function but that It be expandable With other parts In the M6800 'P,n 35 must be tied to 5 V on the 6802NS
Microcomputer family .. Pin 36 must be tied to ground for the 6808

4·125
 MAXIMUM RATINGS
ThiS Input contains circUitry to protect the
Rating Symbol Value Unit
Inputs agamst damage due to hIgh statIc
Supply Voltage Vee -03 to + 70 V voltages or electnc fields, however, It IS ad~
Input Voltage Vin -03 to + 70 V vised that normal precautions be taken to
Operatmg Temperature Range TA o to + 70 °e aVOid apphcatlon of any voltage higher than
maximum rated voltages to thIS hlgh-
Storage Temperature Range Tstg -55 to + 150 °e
Impedance CircUit Reliability of operatIon IS
enhanced If unused Inputs are tied to an ap-
propriate logiC voltage level (e 9 , either VSS
THERMAL CHARACTERISTICS
or VeeJ
Characteristic Symbol Value Unit
Average Thermal ResIstance (Junction to Ambient)
PlastiC 100
8JA °e/w
Ceramic 50

POWER CONSIDERATIONS

The average Chip-Junction temperature, TJ, In °C can be obtained from

•
TJ=TA+(PO"OJA) (1)
Where
T A'" Ambient Temperature, °c
OJA= Package ThermaJ ReSistance, Junctlon-to-Amblent, °C/W
PO'" PINT+ PPORT
PINT'"' ICC x VCC, Watts - Chip Internal Power
PPORT= Port Power OISSlpatlOn, Watts - User Oetermlned
For most applications PPORT<IIi PINT and can be neglected PPORT may become significant If tl'8 deVice IS configured to
drive Oarlington bases or sink LEO loads
An approximate relationship between Po and T J (,f PPORT IS neglected) IS
Po = K - IT J + 273°C) (2)
SolVing equations 1 and 2 for K gives
K = PO"IT A + 273°C) + OJA"P 0 2 (3)
Where K IS a constant pertaining to the particular part K can be determined from equation 3 by measuring Po lat equilibrium)
for a known T A USing thiS value of K the values of Po and T J can be obtained by solVing equations (1) and (2) Iteratively for 3ny
value of T A

4-126
OPERATING TEMPERATURE RANGE

Device Speed Symbol Value Unit

MC6802P,L (10 MHzl
TA
o to + 70
°C
MC6802CP ,CL (10 MHzl -40 to +85
MC68A02P,L (15 MHzl
TA
o to + 70
°C
MC68A02CP ,CL (15 MHzl -40 to +85
MC68B02P,L (20 MHzl Oto +70
TA °C
MC68B02CP ,CL (20 MHzl -40 to +85
MC6802NSP ,L (10 MHzl TA Oto +70 °C
MC6808P,L (10 MHzl
MC68A08P,L (15 MHzl TA o to + 70 °C
MC68B08P,L (20 MHzl

-
DC ELECTRICAL CHARACTERISTICS (VCC-50 Vdc ±5% Vss-O -
- to 70°C unless otherwise noted I
TA-O
Charactenstic Symbol Min Typ Max Unit

Input High Voltage Logic, EXT AL, RES'IT VSS + 20 - VCC V

VIH -
VSS+40 VCC

•
Input Low Voltage Logic, EXTAL, RESET VIL VSS-03 - VSS + 08 V
Input Leakage Current (V ,n =Oto 525 V, VCC= maxi Logic lin - 10 25 ~A
Output High Voltage
(ILoad= -205~A, Vcc=mlnl 00-07 VSS + 24 -- -
VOH V
ilLoad= -145~A, VCC = mini AO-A15, Riw, VMA, E VSS+24 - -
(ILoad= -100~A, Vcc=mlnl BA VSS + 24 - -
Output Low Voltage ilLoad = 1 6 rnA, VCC = mini VOL - - VSS+O 4 V
Internal Power DISSipation (Measured at T A = QOC) PINT - 0600 10 W

VCC Standby
Power Down VSBB 40 - 525
V
Power Up VSB 475 - 525
Standby Current ISBB - 80 mA
Capacitance #
(V,n=O, TA=25°C,f=1 OMHzl 00-07 C,n 10 125 pF
LogiC Inputs, EXT AL 65 10
AO-AI5, Riw, VMA Cout 12 pF

-In power-down mode. maximum power diSSipation IS less than 42 mW

'Capacitances are periodically sampled rather than 100% teMed

CONTROL TIMING (Vcc=50 V +5%

- VSS=O TA=TL 10 TH unless otherwise noledl
MC6802NS. MC68A02 MC68B02
Characteristics Symbol MC6808 MC68A08 MC68B08 Unit
Min Max Min Max Min Max
Frequency of Operation 10 01 10 01 15 01 20 M~!z

Crystal Frequency IXTAL 10 40 10 60 10 80 MHz

External Oscillator Frequency 4xlo 04 40 04 60 04 80 MHz
Crystal OSCillator Start Up Time trc 100 - 100 - 100 - ms
Processor Controls (HALT, MR, RE, RESET, lffQ NMII
Processor Control Setup Time IpCS 200 - 140 - 110 - ns
Processor Control Rise and Fall Time IPCr, - 100 - 100 - 100 ns
(Does Not Apply to RESETI IPCI

4·127
 MC6802· MC6808. MC6802NS

BUS TIMING CHARACTERISTICS

MC6802NS
MC68A02 MC68B02
Ident. MC6802
Characteristic Symbol MC68AOB MC68BOB Unit
Number MC680B
Min Max Min Max Min Max
1 Cycle Time tCYC 10 10 0667 10 05 10 ~s

2 Pulse Width, E Low PWEL 450 5000 280 5000 210 5000 ns
3 Pulse Width, E High PWEH 450 9500 280 9700 220 9700 ns
4 Clock Rise and Fall Time tr,q - 25 - 25 - 20 ns
9 Address Hold Time tAH 20 - 20 - 20 - os
tAVl 160 - 100 - 50 -
12 Non-Muxed Address Valid Time to E ISee Note 51 ns
tAV2 - 270 - - - -
17 Read Data Setup Time tDSR 100 - 70 - 60 - ns
18 Read Data Hold Time tDHR 10 - 10 - 10 - ns
19 Wnte Data Delay Time tDDW - 225 - 170 - 150 ns
21 Wnte Data Hold Time tDHW 30 - 20 - 20 - ns
29 Usable Access Time (See Note 4) tACC 605 - 310 - 235 - ns

FIGURE 2 - BUS TIMING

II
R/VV, Address----_r~~~](~~jf~t_-=~~~__t----_tt_--------------------------------_r~~~7
INon-Muxedl

Read Data MPU Read Data Non-Muxed

Non·Muxed ___-+__-'1"

Write Data
Non-Muxed ____ -+__~

NOTES
Voltage levels shown are VL;5; 0 4 V, V H 2: 2 4 V, unless otherwise specified
Measurement POints shown are 0 8 V and 20 V, unless otherwise noted
All electllcals shown for the MC6802 apply to the MC6802NS and MC6808, unless otherwise noted
Usable access time IS computed by 12+3+4-17
If programs are not executed from on-board RAM, TAV1 applies If programs are to be stored and executed from on-board RAM, T AV2 ap-
plies For normal data storage In the on-board RAM, this extended delay does not apply Programs cannot be executed from on-board
RAM when uSing A and B parts IMC68A02, MC68A08, MC68B02, MC68B081 On-board RAM can be used for data storage with all parts

4-128
MC6802- MC6808- MC6802NS

FIGURE 3 - BUS TIMING TEST LOAD

475 V

RL = 22 kD

MMD6150
C= 130 pF for 00-07, E Test POlnto-.....-1r--t..- . or Equlv
=90 pF for AO-AI5, R/iN, and VMA
=30 pF for SA C R
R= 117 kD for 00-07, E MMD7000
= 16 5 kD for AO-AI5, R/iN, and VMA or EqUlv
=24 kD for SA

FIGURE 4 - TYPICAL DATA BUS OUTPUT DELAY FIGURE 5 - TYPICAL READ/WRITE, VMA AND
versus CAPACITIVE LOADING ADDRESS OUTPUT DELAY versus CAPACITIVE LOADING
600 600
IOH =-205JJA max@24V 10H I _145 1"A rna> .'2 4 V
10 l = 1 6 rnA max @ 0 4 V tOl:: 1 6 rnA max@O 4 V
500
VCC'50V 500 VCC' 5 av
TA' 25'C TA' 25 C

]
400
:g 400
Address, VMA

-
w w

'>-"
~ 300 '>-"
~
300
I---- I--"
l-
g I-- --- g Vf-" ...... f--: r- RIW
200

-- I---- 200
r-

•
~
100
100
i
CL tncludesstray capacitance CL tncludesstray capacitance
100 200 300 400 500 600 100 200 300 400 500 600
Cl,lOAD CAPACITANCE (pfl Cl,lOAO CAPACITANCE (pfl

FIGURE 6 - EXPANDED BLOCK DIAGRAM

A15 A14 A13 A12 All AlO A9 A8 A7 A6 A5 A4 A3 A2 Al AD
25 24 23 22 20 19 18 17 16 15 14 13 12 11 10 g

Memory Ready 3
Enable 37
RESET 40
Non-Maskable Interrupt (NMI)
i=iiii:T 2
Interrupt Request IIRQ) 4
EXTAl 39
XTAl 38
Bus Available 7
Valid Memory Address 5
Read/Write {R/WI 34

Vee= P,n 8
Vee'" Pm 35 for MC6802NS
VSS=Plns 1, 21
VSS = Pm 36 for MC6808

26 27 28 29 30 31 32 33
D7 D6 D5 D4 D3 D2 D1 DO

4·129
 MPU REGISTERS

A general block diagram of the MC6802 IS shown In Figure read/wnte memory that may have any location laddress)
6. As shown, the number and configuration of the registers that IS convenient. In those applications that require storage
are the same as for the MC6800 The 126 x 8-blt RAM" has of Information In the stack when power IS lost, the stack
been added to the basIc MPU. The first 32 bytes can be re- must be non-volatile.
tained during power-up and power-down conditions via the
RE signal. INDEX REGISTER
The MC6802NS IS identical to the MC6802 except for the The index register IS a two byte register that IS used to
standby feature on the first 32 bytes of RAM. The standby store data or a 16-blt memory address for the Indexed mode
feature does not eXist on the MC6802NS and thus pin 35 of memory addressing
must be tied to 5 V.
The MC6808 IS identical to the MC6802 except for on- ACCUMULATORS
board RAM. Since the MC6808 does not have on-board The MPU contains two 8-blt accumulators that are used to
RAM Pin 36 must be tied to ground allOWing the processor to hold operands and results from an arithmetic logic Unit
utilize up to 64K bytes of external memory IALU)
The MPU has three 16-blt registers and three 8-bit
registers available for use by the programmer IFlgure 7) CONDITION CODE REGISTER
PROGRAM COUNTER The condition' code register indicates the results of an
Anthmetlc Logic Unit operation: Negative IN), Zero IZ),
The program counter IS a two byte 116-blt) register that Overflow IV), Carry from bit 7 IC), and Half Carry from bit 3

•
POints to the current program address IHI. These bits of the Condition Code Register are used as
testable conditions for the conditional branch Instructions.
STACK POINTER Bit 41s the interrupt mask bit II) The unused bits of the Con-
The stack pOinter IS a two byte register that contains the dition Code Register Ib6 and b7) are ones.
address of the next available location In an external push- Figure 8 shows the order of saving the microprocessor
down/pop-up stack ThiS stack IS normally a random access status Within the stack.

'If programs are not executed from on-board RAM, TAV1 applies. If programs are to be stored and executed from on-board RAM, TAV2 ap-
plies. For normal data storage In the on-board RAM, thiS extended delay does not apply Programs cannot be executed from on-board RAM
when uSing A and B parts IMC68A02, MC68AOB, MC68B02, and MC68BOBI On-board RAM can be used for data storage with all parts.

FIGURE 7 - PROGRAMMING MODEL OF THE MICROPROCESSING UNIT

I Accumulator A
':-------'0

15
'-_____-'1 Accumulator B

LI_ _ _ _ _ _ _ _ _ _ _ _ _ -'I Stack POinter

Condition Codes
,....."..,r'-r.,..,..
L...J....... Register

Carry (From alt 7)

Overflow

z •.-o
Negative

Interrupt

' - - - - - - Half Carry (From Sit 3)

4·130
 FIGURE 8 - SAVING THE STATUS OF THE MICROPROCESSOR IN THE STACK

m - 9
m - 8
m - 7 SP
SP = Stack POinter
CC:: Condition Codes (Also called the Processor Status Byte) m- 6 CC
ACeS = Accumulator B
m - 5 ACeS
ACCA = Accumulator A
IXH:: Index RegISter, Higher Order 8 Bits m - 4 ACCA
I XL = Index Register, Lower Order 8 Bits m - 3 IXH
PCH = Program Counter, Higher Order 8 Sits
PC L = Program Counter, Lower Order 8 Bits m - 2
m -1
m - 2

m - 1
IXL
PCH .
"u
en

--l
_ _ SP
PCL
m + 1 m + 1
m + 2 m + 2

Before After

MPU SIGNAL DESCRIPTION

Proper operation of the MPU requires that certain control

and timing signals be provided to accomplish specific func-
tions and that other signal lines be monitored to determine
the state of the processor These control and timing signals
are similar to those of the MC6800 except that TSC, DBE,
4>1, 4>2 Input, and two unused pins have been eliminated,
and the following signal and timing lines have been added
tlon, bus available will be at a high state, valid memory ad-
dress will be at a low state The address bus will display the
address of the next Instruction
To ensure single Instruction operation, transition of the
HALT line must occur tpcs before the failing edge of E and
the HALT line must go high for one clock cycle.
HALT should be tied high If not used ThiS IS good
•
RAM Enable (RE) engineering deSign practice In general and necessary to en-
Crystal Connections EXT AL and XT AL sure proper operation of the part
Memory Ready (MR)
VCC Standby READ/WRITE (RiW)
Enable 4>2 Output (E) ThiS TTL-compatible output signals the peripherals and
The following IS a summary of the MPU signals memory deVices whether the MPU IS In a read (high) or write
(low) state The normal standby state of thiS signal IS read
ADDRESS BUS (AO-A15) (high) When the processor IS halted, It will be In the read
Sixteen pins are used for the address bus The outputs are state ThiS output IS capable of driVing one standard TTL
capable of driVing one standard TTL load and 90 pF These load and 90 pF.
lines do not have three-state capability
VALID MEMORY ADDRESS (VMA)
DATA BUS (00-07) ThiS output indicates to peripheral deVices that there IS a
Eight PinS are used for the data bus. It IS bidirectional, valid address on the address bus In normal operation, thiS
transferring data to and from the memory and peripheral signal should be utilized for enabling peripheral Interfaces
deVices It also has three-state output buffers capable of such as the PIA and ACIA ThiS signal IS not three-state One
driVing one standard TTL load and 130 pF standard TTL load and 90 pF may be directly driven by thiS
Data bus will be In the output mode when the Internal active high signal
RAM IS accessed and RE will be high ThiS prohibits external
data entering the MPU It should be noted that the Internal BUS AVAILABLE (BA) - The bus available signal Will nor-
RAM IS fully decoded from $0000 to $OO7F External RAM at mally be In the low state, when activated, It Will go to the
$0000 to $OO7F must be disabled when Internal RAM IS ac- high state Indicating that the microprocessor has stopped
cessed and that the address bus IS available (but not In a three-state
condition). ThiS Will occur If the HALT line IS In the low state
HALT or the processor IS In the WAIT state as a result of the execu-
When thiS Input IS In the low state, all activity In the tion of a WAIT Instruction. At such time, all three-state out-
machine will be halted. ThiS Input IS level sensitive. In the put drivers Will go to their off-state and other outputs to their
HALT mode, the machine will stop at the end of an Instruc- normally Inactive level. The processor IS removed from the

4-131
 WAIT state by the occurrence of a maskable (mask bit 1=0) tlon of a routine to Inttlallze the processor from ItS reset con-
or nonmaskable Interrupt. This output IS capable of driving ditIOn All the higher order address lines will be forced high
one standard TTL load and 30 pF. For the restart, the last two ($FFFE, $FFFFI locations In
memory will be used to load the program that IS addressed
INTERRUPT REQUEST (IRQ) by the program counter Dunng the restart routine, the inter-
A low level on this Input requests that an Interrupt se- rupt mask bit IS set and must be reset before the MPU can be
quence be generated within the machine The processor will Interrupted by IRO Power-up and reset timing and power-
wait until It completes the current instruction that IS being down sequences are shown In Figures 9 and 10, respectively
excuted before It recogntzes the request At that time, If the RESET, when brought low, must be held low at least three
Interrupt mask bit In the condition code register IS not set, clock cycles ThiS allows adequate time to respond Internally
the machine will begin an Interrupt sequence. The Index to the reset ThiS IS Independent of the trc power-up reset
register, program counter, accumulators, and condition that IS reqUired.
code register are stored away on the stack Next the MPU When RES ET IS released It must go through the low-to-
will respond to the Interrupt request by setting the Interrupt high threshold Without bounCing, oscillating, or otherwise
mask bit high so that no further Interrupts may occur At the causing an erroneous reset (less than three clock cyclesl
end of the cycle, a lS-bIt vectoring address which IS located ThiS may cause Improper M PU operation until the ~ext valid
In memory locations $FFF8 and $FFF9 IS loaded which reset
causes the M PU to branch to an Interrupt routine In memory
The HALT line must be In the high state for Interrupts to NON-MASKABLE I~TERRUPT (NMI)
be serviced Interrupts will be latched Internally while HALT A low-gOing edge on thiS Input requests that a non-
IS low. maskable Interrupt sequence be generated Within the pro-
A nominal 3 kD pullup resistor to Vee should be used for cessor. As With the Interrupt request Signal, the processor
Wire-OR and optimum control of Interrupts IRO may be tied Will complete the current Instruction that IS being executed
directly to Vee If not used before It recogmzes the NMi Signal The Interrupt mask bit In
the condition code register has no effect on NMi

II RESET
ThiS Input IS used to reset and start the M PU from a
power-down condition, resulting from a power failure or an
Inttlal start-up of the processor When thiS line IS low, the
MPU IS inactive and the Information In the registers will be
The Index register, program counter, accumulators, and
condition code registers are stored away on the stack At the
end of the cycle, a 16-blt vectonng address which IS located
In memory locations $FFFe and $FFFD IS loaded causing the
M PU to branch to an Interrupt service routine In memory
lost If a high level IS detected on the Input, thiS will Signal A nominal 3 kD pullup resistor to Vee should be used for
the MPU to begin the restart sequence ThiS will start execu- wire-OR and optimum control of Interrupts NMI may be tied

FIGURE 9 - POWER-UP AND RESET TIMING

Vcc

trc

~--------------------~~--------~VIH
d !.-t
VIL
pcs

Option 1
(See Note Below)

trc
RESET ______

RE _ _ _ _
~-

j[,~,
fI
---------- Option 2
(See Figure 10 for
Power-down Condition)

NOTE If option 1 IS chosen, i'i"ESEi' and RE PinS can be tied together

4-132
MC6802-MC6808-MC6802NS

directly to V CC If not used FIGURE 10 - POWER-DOWN SE~UENCE

Inputs IRQ and NMI are hardware Interrupt lines that are
sampled when E IS high and will start the Interrupt routine on
VCC
a low E following the completion of an Instruction
Figure 11 IS a flowchart describing the major decIsion
paths and Interrupt vectors of the microprocessor Table 1
gives the memory map for Interrupt vectors

TABLE 1 - MEMORY MAP FOR E

INTERRUPT VECTORS

Vector
Description
MS LS
$FFFE $FFFF Restart RE
$FFFC $FFFD Non-Maskable Interrupt
$FFFA $FFFB Software Interrupt
$FFFB $FFF9 Interrupt Request

FIGURE 11 - MPU FLOWCHART

•
No

Yes
NMI

No No

Yes
TAli

No
Yes
On

4-133
 MC6802-MC6808-MC6802NS

FIGURE 12 - CRYSTAL SPECIFICATIONS

Y1 Cin Cout
358 MHz 27 pF 27 pF
4 MHz 27 pF 27 pF
6 MHz 20 pF 20 pF
8 MHz 18 pF 18 pF

Crystal Loading

----;101--1- - -
Yl

• RS
CO
Cl
Q
3.58 MHz
60 Il
35 pF
0015 pF
>40K
Nominal Crystal Parameters*

4.0 MHz
501l
65 pF
0025 pF
>30K
6.0 MHz
3O-501l
4-6 pF
001-002 pF
>20K
8.0 MHz
20-40 [)
4-6 pF
001-002 pF
>20K

-These are representative AT -cut parallel resonance crystal parameters only

Crystals of other types of cuts may also be used

Figure 13 - SUGGESTED PC BOARD LAYOUT

Example of Board Design USing the Crystal Oscillator

~Other Signals are Not Wired In this Area

/ E Signal IS Wired Apart from 38 Pm

/ and 39 Pin
o.::----'E

4·134
MC6802- MC6808- MC6802NS

FIGURE 14 - MEMORY READY SYNCHRONIZATION

4xfo
OSCillator

EXTALf~~--------------------------.
XTAL 38
MC6802
MR~----------------1Q
Memory Ready
D Generated from
CS Logic
SN74LS74

FIGURE 15 - MR NEGATIVE SETUP TIME REQUIREMENT

e=t''''
E Clock Stretch •
\I...O_B_V___ .JJ

The E clock Will be stretched at end of E high of the cycle dUring which MR negative meets the tpcs setup time The tpcs setup time IS
referenced to the fall of E If the tpcs setup lime IS not met, E Will be stretched at the end of the next E-hlgh II cycle E Will be stretched In in-
tegral multiples of II cycles

Resuming E ClOCking

~tPcs ~tPcs

L
I
I I
Stretched E I

MR
HUff
The E clock Will resume normal operallOn at the end of the II cycle dUring which M R asserllOn meets the tpcs setup time The tpcs setup time
IS referenced to transitions of E were It not stretched If tpcs setup time IS not met, E Will fall at the second possible tranSItion time after MR IS
asserted There IS no dIrect means of determlOing when the tpcs references occur, unless the synchroniZing CirCUit of Figure 14 IS used

4-135
 RAM ENABLE (RE - MC6802+MC6802NS ONLY) MPU INSTRUCTION SET
A TTL-compatible RAM enable Input controls the on-chip
RAM of the MC6802 When placed In the high state, the on- The Instruction set has 72 different Instructions Included
chip memory IS enabled to respond to the MPU controls In are binary and deCimal anthmetlc, logical, Shift, rotate, load,
the low state, RAM IS disabled This Pin may also be utilized store, conditional or unconditional branch, Interrupt and
to disable reading and wntlng the on-chip RAM dunng a stack manipulation Instructions (Tables 2 through 6) The in-
power-down situation RAM Enable must be low three struction set IS the same as that for the MC6800
cycles before VCC goes below 4 75 V dunng power-down
RAM enable must be tied low on the MC6808 RE should be
tied to the correct high or low state If not used
MPU ADDRESSING MODES
EXTAL AND XTAL
These Inputs are used for the Internal oscillator that may There are seven address modes that can be used by a pro-
be crystal controlled These connections are for a parallel grammer, With the addreSSing mode a function of both the
resonant fundamental crystal (see Figure 12) (AT-cut) A type of instruction and the coding Within the instruction A
dlvlde-by-four CirCUit has been added so a 4 MHz crystal may summary of the addreSSing modes for a particular instruction
be used In lieu of a 1 MHz crystal for a more cost-effective can be found In Table 7 along With the associated Instruction
system An example of the crystal circuit layout IS shown In execution time that IS given In machine cycles With a bus
FigurE:> 13 Pin 39 may be dnven externally by a TTL Input frequency of 1 MHz, these times would be microseconds
signal four times the required E clock frequency Pin 38 IS to
be grounded ACCUMULATOR (ACCX) ADDRESSING

II
An RC network IS not directly usable as a frequency In accumulator only addreSSing, either accumulator A or
source on PinS 38 and 39 An RC network type TTL or CMOS accumulator B IS specified These are one-byte Instructions
OSCillator will work well as long as the TTL or CMOS output
dnves the on-Chip OSCillator IMMEDIATE ADDRESSING
LC networks are not recommended to be used In place of
In Immediate addreSSing, the operand IS contained In the
the crystal
second byte of the Instruction except LOS and LOX which
If an external clock IS used, It may not be halted for more
have the operand In the second and third bytes of the in-
than tPW4>L The MC6802, MC6808 and MC6802NS are
struction The MPU addresses thiS location when It fetches
dynamiC parts except for the Internal RAM, and require the the Immediate instruction for execution These are two- or
external clock to retain information three-byte instructions

MEMORY READY (MR) DIRECT ADDRESSING

MR IS a TTL-compatible Input signal controlling the stret- In direct addreSSing, the address of the operand IS contain-
ching of E Use of MR requires synchronization With the 4xfo ed In the second byte of the Instruction Direct addreSSing
signal, as shown In Figure 14 When MR IS high, E will be In allows the user to directly address the lowest 256 bytes In the
normal operation When M R IS low, E Will be stretched in- machine, Ie, locations zero through 255 Enhanced execu-
tegral numbers of half penods, thus allOWing Interface to tion times are achieved by stonng data In these locations In
slow memones Memory Ready timing IS shown In Figure 15 most configurations, It should be a random-access memory
MR should be !led high (connected directly to VCC) If not These are two-byte Instructions
used ThiS IS necessary to ensure proper operation of the
part A maximum stretch IS tcyc EXTENDED ADDRESSING
In extended addreSSing, the address contained In the se-
ENABLE (E) cond byte of the instruction IS used as the higher eight bits of
ThiS pin supplies the clock for the M PU and the rest of the the address of the operand The third byte of the instruction
system ThiS IS a Single-phase, TTL-compatible clock ThiS IS used as the lower eight bits of the address for the operand
clock may be conditioned by a memory read signal ThiS IS ThiS IS an absolute address In memory These are three-byte
eqUivalent to 4>2 on the MC6800 ThiS output IS capable of instructions
dnvlng one standard TTL load and 130 pF
INDEXED ADDRESSING
VCC STANDBY (MC6802 ONLY) In Indexed addreSSing, the address contained In the se-
ThiS pin supplies the dc voltage to the first 32 bytes of cond byte of the instruction IS added to the Index register's
RAM as well as the RAM Enable (RE) control logiC Thus, lowest eight bits In the M PU The carry IS then added to the
retention of data In thiS portion of the RAM on a power-up, higher order eight bits of the Index register ThiS result IS
power-down, or standby condition IS guaranteed MaXimum then used to address memory The modified address IS held
current drain at VSB maximum IS ISBB For the MC6802NS In a temporary address register so there IS no change to the
thiS Pin must be connected to V CC Index register These are two-byte instructions

4-136
MC6802- MC68Q8- MC6802NS

IMPLIED ADDRESSING byte of the Instruction IS added to the program counter's

In the Implied addressing mode, the instruction gives the lowest eight bits plus two The carry or borrow IS then added
address (I.e, stack pOinter, Index register, etc) These are to the high eight bits This allows the user to address data
one-byte Instructions Within a range of - 125 to + 129 bytes of the present Instruc-
tion These are two-byte Instructions
RELATIVE ADDRESSING
In relative addressing, the address contained In the second

TABLE 2 - MICROPROCESSOR INSTRUCTION SET - ALPHABETIC SEQUENCE

ABA Add Accumulators CLR Clear PUL Pull Data

ADC Add With Carry CLV Clear Overflow ROL Rotate LeN
ADD Add CMP Compare ROR Rotate Right
AND logical And COM Complement RTI Return from Interrupt
ASl AnthmetlC Shift leh CPX Compare Index Register RTS Return from Subroutine
ASR AnthmetlC Shift Right
DAA Decimal Adlust SBA Subtract Accumulators
BCC Branch rt Carry Clear DEC Decrement
SBC Subtract With Carry

II
BCS Branch rt Carry Set DES Decrement Stack POinter SEC Set Carry
BEQ Branch If Equal to Zero DEX Decrement Index Register SEI Set Interrupt Mask
BGE Branch If Greater or Equal Zero
EOR ExclUSive OR SEV Set Overflow
BGT Branch rt Greater than Zero
STA Store Accumulator
BHI Branch If Higher INC Increment
STS Store Stack Register
BIT Bit Test INS Increment Stack POinter STX Store Index Register
BlE Branch rt Less or Equal INX Increment Index Register SUB Subtract
BLS Branch If Lower or Same
JMP Jump SWI Software Interrupt
BLT Branch If less than Zero
BMI Branch rt MinUS JSR Jump to Subroutine TAB Transfer Accumulators
BNE Branch rt Not Equal to Zero LDA Load Accumulator TAP Transfer Accumulators to Condition Code Reg
BPL Branch rt Plus lDS Load Stack POinter TBA Transfer Accumulators
BRA Branch Always lDX Load Index Register TPA Transfer Condition Code Reg to Accumulator
BSR Branch to Subrouline LSR LogICal Shift Right TST Test
BVC Branch rt Overflow Clear TSX Transfer Stack POinter to Index Register
NEG Negate TXS Transfer Index Register to Stack POinter
BVS Branch If Overflow Set
NOP No Operation
CBA Compare Accumulators WAI Wail for Interrupt
ORA InclUSive OR Accumulator
ClC Clear Carry
CLI Clear Interrupt Mask PSH Push Data

4-137
 TABLE 3 - ACCUMULATOR AND MEMORY INSTRUCTIONS

ADDRESSING MODES BOOLUN/ARITHMETIC OPERATION CDND CODE REG

IMMED DIRECT INDEX EXTNO IMPLIED IAllrlllsterlabel, 5 " 3 Z 1 0
OPfRATIONS MNEMONIC OP - 0. o. o. 0 .. - = refft10 conttflUl HINZVC
Add AQDA 3B 9B 2 AB 5 2 SB 4 J A + M ·A
ADOB CB OB 2 EB 5 2 F8 4 3 S + M ·B I • I
Add Acmltrs A.A lB 2 I A + B ·A ! • I
AddWIthCa,rv AOCA B9 99 2 A9 5 B!I 4 J A. M. C A I • I
AOCB C9 09 2 E9 5 F9 4 B+M +C B I • I I J
A"

BltTesl
ANOA
ANDB
BITA
81TS
84
C4
85
C5
94
04
95
05 3
A4
E4
AS
E5
5
5
B4
F4
B5
F5
4

4
A
8
A M
B
M ·A
M B

M
I

I ••
,.

,•• .
Clear CLA 6F 1 2 IF 6 3 00 ·M • • R S R R
ClRA 00 A

Compare
ClRS
CMPA 81 2 2 91 2 Al 5 2 Bl 4 3
"
5f 00.
•
•
•
•
R S R R
R S
A M I I
CMPS CI 2 201 2 EI 5 2 Fl 4 3 • M • • ! I
Compare Acmllf! CBA 11 2 I A B 11
Complement,l's co. 63 , 2 73 6 J
• • I I'S
COMA 43 2
" ·AM
A • • I l' S
COMB 53 2 8·. I, S
i

!'~i
Complement,2s NEG 60 , 10 6 J 00 M M
!Negatel NEGA 40 2 00 A·A • • I
NEGB 50 2 00 B B • • I
Decimal AdlUSI A OAA 19 2 , Cunverts Bilidry Add 01 BCD Chdrd~ters

Inllo BCD form"l

;~ :
Decrement DEC 6A ,
21'A 6 3
M I M

•
OECA 4A 2 1 A I A • • I
DECB SA 2 I BIB ! t':' •
ExclUSive OR fORA B8 2 9B 3 A. , 2 B8 4 AffiM ·A I , •
EOAB CB 2 08 3 E8 , 2 F8 4 B0M B

·: .:1:..iI' :.
Illcremenl INC 6C , 2 7C 6 1 M" ·M
INCA 4C '} 1 A. 1 ~
INCB 5C 2 , Bfl Il
LoadALmlu lOAA 86 2 1 96 3 A6 2 B6 4 M A • • : : R •
LDAS C6 2 06 3 E6 2 f-6 4 M • • • : : R •

···....
Or InchlslYI! OAAA 8A 2 9A 3 2 AA ') 2 I SA 4 3 A+ M A

.... ..
• •• : R •
DRAB CA 2 2 OA 3 2 EA !i 2 FA 4 3 B+M B • • : : A •

.... .
Pu~h Data PSHA 36 4 1 A MSp SP 1 SP
PSHS 31 4 1 B MSp SP 1 SP
Pun Odld PULA 32 SP liSP MSp A

ROldleLeit
PULS
ROl
ROLA
69 2 19 6 3
33

49 2 1
SP. 1 SP MSp e

=}L{]-~
· .. ~If

;I~:
ROlS !i9 2 , B C b7 - bO
'0' ~} CO
66 1 2 76 6 J
RORA 46 l. - b1o:r:rn:o:;:::J
i~
1
RORS 56 2 I B C - bO
ASl
ASLA
ASLB
68 1 2 18 6 3
4B
" ,
2
n ~- ~-O • .!
:~
1(6
ASR
ASRA
ASAI!
6f I 2 11 6 3
47
!i7
'}
'}
1
1
:}ctrnlliD -
B b1 bO
0
C : :~:
lSR 64 1 2 14 6 J • • A :@ !

::;I it
lSRA 44 2 1 A
M, } o- rn::r::rII1J - 0
LSRB 54 2 1 bl bD C
STAA 91 4 2 AI 6 2 61 A M
STAB , M

··...
01 2 E1 6 2 FI • • : : R •
SublfdLt SUBA 80 2 2 90 2 AD 5 2 BO 4 • A • • : : I
SUBS
SBA
CO 2 2 00 3 2 EO !i 2 fO 4
• ,

·.,
SubtrdLl Atmltrs 10 2 1 A • : :

..,
Subtr With Cdf1~ SBCA B2 2 92 2 A2 !J '} B2 4 3 A MeA
SBCB C2 2 02 '} E2 5 2 F2 4 3 B M (. B
TrdllsferAcmllf$ TA. 16 2 A • I , •
TBA
, ,,
, A
" 2
TeSl, ZPfO or MlIlu$ TST 60 7 2 10 6 3 • 00
TSlA 40 2 , 00
TSIB 50 2 1 00 I, ,
H I N Z V C

LEGEND CONDITION CODE SYMBOLS

OP Operation Code I HexadewnalJ Boolean InduSlVe OR
Number of MPU Cycles o Boolean E~duslve OR Hdll cdrry hom bit 3,
Number of Program Bytes I COlnplemenlof M Illterruptmask
Aflthmetlc Plus TrdnsferlnlO Negallve hlgnblt)
Aflthmetlc Mmus o alt Zero, Zero (byte)
BooieanANO, 00 Byte"lero Owrflow 2's complpment
MSp Contents of memory location pOinted to be Statk Pomler Carrylrombl17
ResetAlwa~s
Note - Accumulator addressmg mode instructions arf Included m Ihe column for IMPLIED addreSSIng SeIAlways
TeSl and set If true,claared olhifwise
NOIAffemd

4·138
 TABLE 4 - INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS

CONO CODE REG

IMMEO DIRECT INDEX UTNO IMPLIED S 4 3 2 I 0

- -= -= -
····....... ·..·.
POINTER OPERATIONS MNEMONIC OP = OP OP OP = OP I- = BOOLEAN/ARITHMETIC OPERATION H I N Z V C
Compare Index lIeg CPX 8C 3 3 9C 4 2 AC 6 2 BC S 3 XH M, XL- 1M .1) CD: 8 •
Decrement Index Reg DEX I X I ,X I

··.... ··..
Decrement Stal;k Pntr DES I SP I 'SP
Increment Index Reg
Increment Slack Pntr
INX
INS
=1 :
08
31
4
4
I
1
Xt 1 •X
SP + 1 'SP
;

··• ..-r- ·..'

Load Index Req LOX CE 3 3 DE 4 2 EE 6 2 FE S 3 M • XH. 1M t l) • Xl ®! R •
Load Stack Pntr LOS 8E 3 3 9E 4 2 AE 6 2 BE 5 3 M ·SPH. 1M t 11 'SPl ®: R .1
Store Index Reg STX OF 5 2 EF I 2 FF 6 3 XH ·M.XL '(M+1I ®: R ,
Store Slack Pntr STS 9F 5 2 AF I 2 I BF 6 3 SPH • M, SPl • 1M
X 1 -SP
i 11 • .® : R •

· ··
Ind. Reg • Stack Potr TXS 35 4 1
Slack Pllir 'Inch. Reg TSX I 30 4 1 Spq ·X ·i· : 1

TABLE 5 - JUMP AND BRANCH INSTRUCTIONS

C~ND CODE REG

•
RELATIVE INDEX EXTNO IMPLIED 543210
OPERATIONS MNEMONIC OP - = OP - OP - OP - BRANCH TEST HINZVC

• .• .• .
• .• .
" " "
Branch Always BRA 20 4 2 None
·.,. •

. .. .. .. ..
Branch If Carry Clear BCC 24 4 2 CoO
Branch If Carry Set Bts 25 4 2 C- 1
Branch It = Zero BEQ 27 4 2 Z- I • i· • • • •
Bunch It :<tZero BGE 2C 4 2 NG)V-O :.
a
.' ·1·. .
• .• .
It > Zero

.'.
Branch BGT 2E 4 2 Z' IN $VI-
Branch It Higher
Branch If <; Zero
BHI
BLE
22
2F
4
4
2
2
C+Z"O
Z + IN (t) VI" 1
• i· •
•
• • •

· ., ....
Branch If lower Or Same BLS 23 4 2 C+Z=l • i • !. • • •
Branch If < Zero BLT 2D 4 2 N (£I V:.l
Branch If MinUS BMI 2B 4 2 N-l .' • i· • • •
Branch If Not Equal Zero BNE 26 4 2 Z-B • • I. • ••
Branch It Overflow Clear BVC 28 4 2 v-a • • • I. • •
Branch If Overflow Set
Branch If Plus
Branch To Subroutine
Jump
Jump To Subroutme
BVS
BPl
BSR
JMP
JSR
29
2A
80
4
4
8
2
2
2
6E
AD
4
8
2
2
IE
BD
3
9
3
3
I(
,
V-I
N-O

See Special OperatIOns

(Figure 16)
:::i:::
· . .'. . .
• • .1. • •
No Operation NOP 01 2 1 Advances Prog Cntr Onlv .;.I.! •••
Return From Interrupt RT! 3B 10 1 --@---
Return From Subfoutme RTS 39 5 1
~ :1 :1:1 :1:1 1

~l@! ·1· · ·
Softwar. Interrupt SWI 3F 12 1 See Special Operations :
W'lt tor Interrupt WAI 3E 9 1 I (Figure 16)

4-139
 FIGURE 16 - SPECIAL OPERATIONS
SPECIAL OPERATIONS
JSR, JUMP TO SUBROUTINE,

INOXD
PC
-;;
{ n+ 1
Main Program
Ao-JSR
K = Offset-
SP-2
SP-l
Ii!' Stack
INX + K
eli
I Subroutme
hI Sub. I.m

n+ 2 Next Main Instr SP

·K =8 Sit Unsigned Value (0+21 Hand In+ 21 L form 0+2

Io+~
MltnProgram ~ Stack ~ Subroutme
l£
Bo· JSR 5P-2 S ht Subr Instr

EXTNo
.+2
.+3
SH Subr Addr
It

Sl = Subr Addr
Next Mam Instr
c::::> SP-l
SP '-"'-";"':;'_--' (S Formed From SH and SLI
-+ = Stack Pomter After Execution

BSR, BRANCH TO SUBROUTINE

~ Main Program
SP~ ,---=:S::"'::::k,--. ~ Subroutine
Bo· BSR n+2.± K htSubr Instr
SP-l 1-"==--1
SP L..!,;;:":":;':"::-_..J
n+2 Formed from In+2! H and In t 21l

JMP, JUMP

[~:
Main Program

•
1E = JMP
,'1 KH = Next Address
INOXO EXTENDED Kl = Next Address
".
Next In:truCllon I
RTS, RETURN FROM SUBROUTINE
~ MamProgram
~§St"k
PC Subroutme
S 1 39 • RTS 1 c:::> SP + 1 NH
SP + 2 NL

ATI, RETURN FROM INTERRUPT

f& Interrupt Program ~ Stack

c::::>
PC
SP
S 1 38· RTI 1
SP + 1 Con dillOn Code
SP + 2 AcmltrB
SP + 3 AcmltrA
SP + 4 lodele Reqlster (X H)
SP + 5 Index Register (XLI
SP + 6 PCH
-+ SP + 7 pel

TABLE 6 - CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS

CoNo CODE REG
'iMP-LIEiJ 5 4 3 2 1 0
OPERATIONS MNEMONIC OP - = BOOLEAN OPERATION H , N Z V C
Clear Carry
Clear Interrupt Mask
CLC
CLI
OC
OE
2
2 ,
1 o 'C
0'1
0
0
0
R
0
0
0
0
0
0
R
0
Clear Overflow CLV OA 2 1 o 'V 0 0 0 0 R 0
Set Carry
Set Interrupt Mask
SEC
SE'
00
OF
2
2
I
1 ,
1 'C
"
0
0
0
S
0
0
0
0
0
0
S
0
Set Overtlow SEV DB 2 1 1 'V 0 0 0 0 S 0
Acmltr A -CCR TAP 06 2 1 A 'CCR --@--
CCR -+Acmltr A TPA 07 2 1 CCR ~'A 0101 0 10 1010

CONDITION CODE REGISTER NOTES (Bit set It test IS true and cleared otherWise!

(Bit VI Test Result" 10000000' (Bit N! Test Stgn bit of most slgmflcant (MSI byte" 1?
IBlt C! Test Result # 00000000' (Bit V! Test 2's complement overtlow from subtraction of MS bytes'
IBlt Cl Test DeCimal value at most slgAlficant BCD Character greater than mne' (8tt N) Test Result less than zero? (Btt lS = 1)
(Not cleared If prevtously set I 10 IAIII load ConditIOn Code Register from Stack (See SpeCial Operations)
(Bit VI Test Operand" 10000000 pnor to executIOn' 11 IBII il Set when mterrupt occurs It pr,evlously set, a Non Maskabh!
(Bit V! Test Operand'" 01111111 prior to execution' Interrupt IS reqUired to Ult the Wilt state
(Bit V! Test Set equal to result of N(f)C after shift has occurre" 12 IAII! Set accordmg to the contents of Accumulator A

4-140
 TABLE 7 - INSTRUCTION ADDRESSING MODES AND ASSOCIATED EXECUTION TIMES
(Times in Machine Cycle)

;; :;;
c .5
c

l = !I

. "-!c
. ".e
1c
! 0- !
11x "-a! .!!i 11
: "!
0
0
OJ
)(
u i! ~ . . OJ
)(
U
to
!I
! 0= w= !
ABA
ADC
e u
"
2
6
3
..
x
w

4
.:" !
5
2
a:
INC
INS
9 ~
2
x
"E
6
4
ADD
AND
ASl
ASR
2
2
2
2
3
3
6
6
4
4
5
5
7
7 .
INX
JMP
JSR
lDA 2 3
3
9
4
·
4
8
5
4

BCC 4 lDS 3 4 5 6
BCS 4 LDX 3 4 5 6
BEA 4 lSR 6 7
BGE 4 NEG 6 7
BGT Nap

·
4
BHI 4 ORA 2 3
BIT PSH 4
BlE
BLS
BLT
BMI
4
4
4
PUL
ROL
ROR
RTI
0
6
·
7
7
4

.
4 10
BNE 4 RTS 5
BPL 4 SBA 2
BRA 4 SBC 2 3 4
BSR SEC
.
8 2
BVC SEI 2

·
4
BVS 4 SEV 2
CBA 2 STA 4 5 6
CLC 2 STS 5 6 7
CLI STX
..·
2 6 7

·
5
CLR 2 6 SUB 3 4 5
CLV 2 SWI 12
CMP 3 4 5 TAB 2
COM TAP
. .·
6 7 2
CPX 5 6 TBA 2
DAA 2 TPA 2
DEC
DES
DEX
EaR
2

2 3
6

4
·
4
4
TST
TSX
TSX
WAI
2 6 7
·
4
4
9

NOTE I nterrupt time IS 12 cycles from thf' end of

the Instruction being executeci, except following
a WA I InstructIOn Then It IS 4 cycles

4·141
 MC6802·MC6808·MC6802NS

SUMMARY OF CYCLE-BY-CYCLE OPERATION

Table 8 provides a detailed descnptlon of the Information as the control program IS executed The Information IS
present on the address bus, data bus, valid memory address categonzed In groups according to addressing modes and
line IVMA), and the read/wnte line IR/W) dunng each cycle number of cycles per instruction. lin general, instructions
for each instruction. with the same addreSSing mode and number of cycles ex-
This Information IS useful In companng actual with ex- ecute In the same manner, exceptions are indicated In the
pected results dunng debug of both software and hardware table.)

TABLE 8 - OPERATIONS SUMMARY

Address Mode R/W

and Instructions Address Bus Line Data Bus
IMMEDIATE
ADC EOR 1 1 Op Code Address 1 Op Code
ADO LOA
2 1 Op Code Address +1 1 Operand Data
AND ORA 2
BIT SBC
CMP SUB
CPX 1 1 Op Code Address 1 Op Code
LOS
LOX
3 2 1 Op Code Address + 1 1 Operand Data (HIgh Order Bvte)

•
3 1 Op Code Address + 2 1 Operand Data (Low Order Byte)
DIRECT
ADC EOR 1 1 Op Code Address 1 Op Code
AOD LOA
AND ORA 3 2 1 Op Code Address +1 1 Address of Operand
BIT SBC 3 1 Address of Operand 1 Operand Data
CMP SUB
CPX 1 1 Op Code Address 1 Op Code
LOS 1
LOX 4 2 Op Code Address + 1 1 Address of Operand
3 1 Address of Operand 1 Operand Data (High Order Byte)
4 1 Operand Address + 1 1 Operand Data (Low Order Byte)
STA 1 1 Op Code Address 1 Op Code
4 2 1 Op Code Address + 1 1 Destination Address
3 0 De!.ttnation Address 1 Irrelevant Data (Note 1)
4 1 DestIOatlon Address 0 Data from Accumulator
STS 1 1 Op Code Address 1 Op Code
STX 2 1 Op Code Address + 1 1 Address of Operand
5 3 0 Address of Operand 1 Irrelevant Data (Note 1)
4 1 Address of Operand 0 Register Data (High Order Byte)
5 1 Address of Operand + 1 0 Register Data (Low Order Byte)
INDEXED
JMP 1 1 Op Code Address 1 Op Code
2 1 Op Code Address + 1 1 Offset
4
3 0 Index Register 1 Irrelevant Data (Note 1)
4 0 Index Register Plus Offset (w/o Carry) 1 Irrelevant Data (Note 1)
ADC EDR 1 1 Op Code Address 1 Op Code
ADO LOA 1
AND 2 1 Op Code Address + 1 Offset
ORA
BIT SBC 5 3 0 Index Register 1 Irrelevant Data (Note 1)
CMP SUB 1
4 0 Index Register Plus Offset (w/o Carry) Irrelevant Data (Note 1)
5 1 Index Register Plus Offset 1 Operand Data
CPX 1 1 Op Code Address 1 Op Code
LOS
LOX 2 1 Op Code Address + 1 1 Offset
3 0 I ndex Register 1 Irrelevant Data (Note 1)
6
4 0 Index Register Plus Offset (w/o Carry) 1 Irrelevant Data (Note 1)
5 1 Index Register Plus Offset 1 Operand Data (High Order By tel
6 1 Index Register Plus Offset + 1 1 Operand Data ILow Order Byte)

4-142
MC6802-MC68Q8-MC6802NS

TABLE 8 - OPERATIONS SUMMARY ICONTINUED)

Address Mode RIW

and Instructions Address Sus Line Data Bus
INDEXED IContlnued)
STA 1 1 Op Code Address 1 Op Code
2 1 Op Code Address + 1 1 Offset

6 3 0 Index Register 1 Irrelevant Data (Note 1)

4 0 Index Register Plus Offset (w/o Carry) 1 Irrelevant Data (Note 1)
5 0 Index Register Plus Offset 1 Irrelevant Data (Note 1)
6 1 Index Register Plus Offset 0 Operand Data
ASL LSR 1 1 Op Code Address 1 Op Code
ASR NEG 2 1 Op Code Address + 1 1 Offset
CLR ROL
COM ROR 3 0 Index Register 1 Irrelevant Data (Note 1)
TST
7
DEC 4 0 Index Register Plus Offset (w/o Carry) 1
INC
Irrelevant Data (Note 1)
5 1 Index Register Plus Offset 1 Current Operand Data
6 0 Index Register Plus Offset 1 Irrelevant Data (Note 1 )
7 1/0 Index Register Plus Offset 0 New Operand Data (Note 3)
(Note
3)
STS , 1 Op Code Address 1 Op Code
STX
2 1 Op Code Address + 1 1 Offset
3 0 Index Register 1 Irrelevant Data (Note 1)

•
7
4 0 Index Register Plus Offset (w/o Carry) 1 Irrelevant Data (Note 1)
5 0 Index Register Plus Offset 1 Irrelevant Data (Note 1)
6 1 Index Register Plus Offset 0 Operand Data (High Order Byte)
7 1 Index Register PILI'S Offset + 1 0 Operand Data (Low Order Byte)
JSR 1 1 Op Code Address 1 Op Code
2 1 Op Code Address + 1 1 Offset
3
,
0 Index Register 1 Irrelevant Dat03 (Note 1)
8 4
5 , Stack Pomter
Stack POinter -- 1
0
0
Return Address (Low Order Byte)
Return Address (High Order Byte)
6
7
0
0
Stack POinter - 2
Index Register ,
1 Irrelevant Data (Note 1)
Irrelevant Data (Note 1)
8 0 Index Register Plus Offset (w/o Carry) 1 Irrelevant Data (Note 1)
EXTENDED
, 1
JMP
3 2 1
Op Code Address
Op Code Address + 1 ,
1 Op Code
Jump Address {High Order Byte)
3
,
1 Op Code Address + 2 1 Jump Address (Low Order Byte)
ADC
ADD
EOR
LOA
1
, Op Code Address
Op Code Address + 1
1 Op Code

AND ORA 4
2
Op Code Address + 2 ,
1 Address of Operand (HIgh Order Byte)
BIT
CMP
SBC
SUB
3
4 ,
1
Address of Operand , Address of Operand (Low Order Byte)
Operand Data
CPX 1 1 Op Code Address 1 Op Code
LOS
LOX
2 1 Op Code Address + 1 1 Address of Operand (HIgh Order Byte)
1 Op Code Address + 2
5 3
,
1 Address of Operand (Low Order Byte)
4
5
1
1
Address of Operand
Address of Operand + 1 , Operand Data (High Order Byte)
Operand Data (Low Order Byte)
STA A 1 1 Op Code Address 1 Op Code
STA B
2 1 Op Code Address + 1 1 DestinatIon Address (High Order Byte)
5 3 1 Op Code Address + 2 1 Destination Address (Low Order Byte)
4
5 ,
0 Operand Destination Address
Operand Destination Address 0
1 Irrelevant Data (Note 1)
Data from Accumulator
ASL
ASR
CLR
LSR
NEG
ROL
1
2
1
1
Op Code Address
Op Code Address +,
1
, Op Code
Address of Operand (High Order Byte)
Op Code Address + 2
COM
DEC
INC
ROR
TST 6
3
4
1
1 Address of Operand ,
1 Address of Operand (Low Order Etyte)
Current Operand Data
5 0 Address of Operand 1 Irrelevant Data (Note 1)
6 1/0 Address of Operand 0 New Operand Data INote 3)
INote
3)

4-143
 TABLE 8 - OPERATIONS SUMMARY ICONTINUED)

Address Mode RIW

and Instructions Address BUI Line Data Bus
EXTENDED (Continued)
STS 1 1 Op Code Address 1 Op Code
STX Op Code Address + 1 1 Address of Operand (High Order Byte)
2 1
3 1 Op Code Address + 2 1 Address of Operand (Low Order Byte)
6
4 0 Address of Operand 1 Irrelevant Data (Note 11
5 1 Address of Operand 0 Operand Data (High Order Byte)
6 1 Address of Operand + 1 0 Operand Data (Low Order Byte)
JSR 1 1 Op Code Address 1 Op Code
2 1 Op Code Address + 1 1 Address of Subroutine (High Order Byte)
3 1 Op Code Address + 2 1 Address of Subroutine (Low Order Byte)
4 1 Subroutine Starting Address 1 Op Code of Next Instruction
9 5 1 Stack Pomter 0 Return Address (Low Order Byte)
6 1 Stack Pomter - 1 0 Return Address (High Order Byte)
7 0 Stack POinter - 2 1 Irrelevant Data (Note 1)
8 0 Op Code Address + 2 1 Irrelevant Data (Note 1)
9 1 Op Code Address + 2 1 Address of Subroutine (Low Order Byte)
INHERENT
ABA DAA SEC 1 1 Op Code Address 1 Op Code
ASL DEC SEI 2
2 1 Op Code Address + 1 1 Op Code of Next Instruction

I
ASR INC SEV
CBA LSR TAB
CLC NEG TAP
CLI NOP TBA
CLR ROL TPA
CLV ROR TST
COM SBA
DES 1 1 o p Code Address 1 Op Code
DEX 1 Op Code Address + 1 1 Cp Code of Next InstructIon
INS 2
4
INX 3 0 PrevIous Register Contents 1 Irrelevant Data (Note 1)
4 0 New Register Contents 1 Irrelevant Data (Note 1)
PSH 1 1 Op Code Address 1 Op Code
2 1 Op Code Address + 1 1 Op Code of Next Instruction
4
3 1 Stack POinter 0 Accumulator Data
4 0 Stack POinter - 1 1 Accumulator Data
PUL 1 1 ap Code Address 1 ap Code
2 1 Op Code Address + 1 1 Op Code of Next Instruction
4
3 0 Stack POinter 1 Irrelevant Data (Note 1)
4 1 Stack POinter + 1 1 Operand Data from Stack
TSX 1 1 Op Code Address 1 Op Code
2 1 Op Code Address + 1 1 Op Code of Next Instruction
4
3 0 Stack POinter 1 Irrelevant Data (Note 1)
4 0 New Index Register 1 Irrelevant Data (Note 1)
TXS 1 1 Op Code Address 1 Op Code
2 1 Op Code Address + 1 1 ap Code of Next Instruction
4
3 0 Index Register 1 Irrelevant Data
4 0 New Stack POinter 1 Irrelevant Data
RTS 1 1 Op Code Address 1 Op Code
2 1 Op Code Address + 1 1 Irrelevant Data (Note 2)
5 3 0 Stack Pointer 1 Irrelevant Data (Note 1)
4 1 Stack Pointer + 1 1 Address of Next Instruction (High
Order Byte)
5 1 Stack POinter + 2 1 Address of Next Instruction (Low
Order Byte)

4-144
MC6802. MC680a. MC6802NS

TABLE 8 - OPERATIONS SUMMARY (CONCLUDED)

Address Mode R/W

and Instructions Address Bus Line Data Bus
INHERENT (Contonued)
WAI 1 1 Op Code Address 1 Op Code
2 1 Op Code Address +1 1 Op Code of Next Instruction
3 1 Stack POinter 0 Return Address (Low Order Byte)
4 1 Stack POinter - 1 0 Return Address (High Order Byte)
9 5 1 Stack Pointer - 2 0 Index Register (Low Order Byte)
6 1 Stack Pointer - 3 0 Index Register (H,gh Order Byte)
7 1 Stack Po inter - 4 0 Contents of Accumulator A
B 1 Stack POinter - 5 0 Contents of Accumulator B
9 1 Stack Pointer - 6 1 Contents of Condo Code Register
RTI 1 1 Op Code Address 1 Op Code
2 1 Op Code Address +1 1 Irrelevant Data (Note?)
3 0 Stack POinter 1 Irrelevant Data (Note 1)
4 1 Stack POinter + 1 1 Contents of Condo Code Register from
Stack
10 1 Stack POinter + 2 1 Contents of Accumulator B from Stack
5
6 1 Stack POinter + 3 1 Contents of Accumulator A from Stack

•
7 1 Stack POinter + 4 1 Index Register from Stack (High Order
Byte)
S 1 Stack POinter + 5 1 Index Register from Stack (Low Order
Byte)
9 1 Stack POinter + 6 1 Next Instruction Address from Stack
(H Igh Order Byte)
10 1 Stack POinter + 7 1 Next Instruction Address from Stack
(low Order Byte)
SWI 1 1 Op Code Address 1 Op Code
2 1 Op Code Address + 1 1 Irrelevant Data (Note 1)
3 1 Stack Pointer 0 Return Address (Low Order Byte)
4 1 Stack POinter - 1 0 Return Address (High Order Byte)
5 1 Stack Po Inter - 2 0 Index Register (Low Order Byte)
6 1 Stack POinter - 3 0 Index Register (High Order By tel
12
7 1 Stack POinter - 4 0 Contents of Accumulator A
B 1 Stack POinter - 5 0 Contents of Accumulator B
9 1 Stack POinter - 6 0 Contents of Condo Code Re'Jlster
10 0 Stack POinter - 7 1 Irrelevant Data (Note 1)
11 1 Vector Address FFFA (Hex) 1 Address of Subroutine (High Order
Byte)
12 1 Vector Address FFFB (Hex) 1 Address of Subroutine (Low Order
Byte)
RELATIVE
BCC BHI BNE 1 1 Op Code Address 1 Op Code
BCS BlE BPl 1 Op Code Address + 1 1 Branch Offset
2
SEQ BlS BRA 4
BGE BlT BVC 3 0 Op Code Address + 2 1 Irrelevant Data (Note 1)
BGT BMI BVS 1 Irrelevant Data (Note 1)
4 0 Branch Address
BSR 1 1 Op Code Address 1 Op Code
2 1 Op Code Address + 1 1 Branch Offset
3 0 Return Address of Main Program 1 Irrelevant Data (Note 1)
4 1 Stack POinter 0 Return Address (Low Order Byte)
B
5 1 Stack POinter - 1 0 Return Address (High Order Byte)
6 0 Stack Pointer - 2 1 Irrelevant Data (Note 1)
7 0 Return Address of MaIn Program 1 I rrelevant Data (Note 1)
B 0 Subroutine Address (Note 4) 1 Irrelevant Data (Note 1)

NOTES
If device which is addressed dunng thiS cycle uses VMA, then the Data Bus will go to the high-Impedance three-state condition
Depending on bus capacitance, data from the prevIous cycle may be retained on the Data Bus
2 Data IS Ignored by the MPU
3 For TST, VMA=Q and Operand data does not change
4 MS Byte of Address Bus= MS Byte of Address of BSR InstructIOn and LS Byte of Address Bus= LS Byte of Sub-Routine Address

4-145
 ® MOTOROLA MC680SP2

Advance Infor:rnation
HMOS
(HIGH DENSITY
N·CHANNEl, SILICON-GATE
a-BIT MICROCOMPUTER UNIT DEPLETION LOADI

The MC6805P2 Microcomputer Unit (MPU) IS a member of the 8-BIT

M6805 Family of low-cost single-chip microcomputers This 8-blt
microcomputer contains a CPU, on-chip CLOCK, ROM, RAM, 110, and
MICROCOMPUTER
TIMER. It IS designed for the user who needs an economical microcom-
puter with the proven capabilities of the M6800-based instruction set A
comparison of the key features of several members of the M6805 Family
IS shown on the last page of this data sheet The follOWing are some of
the hardware and software highlights of the MC6805P2 MCU

HARDWARE FEATURES:
•8-Blt Architecture

•64 Bytes of RAM l SUFFIX

•Memory Mapped 110 CERAMIC PACKAGE

•
CASE 719
•1100 Bytes of User ROM
•20 TTLICMOS Compatible 81dlrectlonal 110 Lines 18 Lines are
LED Compatlblel

• On-Chip Clock Generator

• Zero
Self-Check Mode
•• MasterCrossing
Reset
Detection
P SUFFIX
PLASTIC PACKAGE
• Complete Development System Support on EXORciser'" CASE 710

• 5 V Single Supply
SOFTWARE FEATURES:
•Similar to M6800 Family
•Byte EffiCient Instruction Set
•Easy to Program

•True Bit Manipulation

•Bit Test !lnd Branch Instruction
•Versatile Interrupt Handling
•Versatile Index Register
FIGURE 1 - PIN ASSIGNMENTS
•Powerful Indexed AddreSSing for Tables
•Full Set of Conditional Branches Vss R'ESEi'
•Memory Usable as ReglsterlFlags
• Single Instruction Memory ExamlnelChange
INT PA7
VCC PA6
• 10 Powerful AddreSSing Modes
EXTAL 4 PA5
• All AddreSSing Modes Apply to ROM, RAM, and 1/0
USER SELECTABLE OPTIONS: XTAL PA4

• Internal8-Blt Timer With Selectable Clock Source (External Tlrner NUM PA3
Input or Internal Machine Clock) TIMER PA2
• Timer Prescaler Option 17 Bits 2NI PCO PAl
• 8 Bidirectional 110 Lines With TTL or TTLICMOS Interface Option
PCl PAO
• Crystal or Low-Cost Resistor OSCillator Option
PC2 PS7
• Low Voltage Inhibit Option
• 4 Vectored Interrupts; Timer, Software, and 2 External PC3 PS6
PSO PS5
PSl PS4
PS2 PS3

4-146
MC6805P2

FIGURE 2 - MC6S05P2 HMOS MICROCOMPUTER SLOCK DIAGRAM

TIMER

PBO
Accumulator PBI
a A CPU Data Pon PB2 Pon
Index Control Dir. a PB3 a
PB4 I/O
Register Reg. Reg. PB5 Lines
PAO a x
PB6
PAl Condition
Pon PA2 PB7
Pon Data Code
A PA3 Re ister cc
A Dir.
I/O PA4 CPU
PA5 Reg. Reg. Stack
Lines
PA6 Pointer
PA7 SP PCO Pon
Program Data Pon
PCI C
Counter Dir. C
PC2 I/O
Hi h PCH Reg. Reg PC3 Lines
ALU
1100 X 8 Program
User ROM Counter

•
116 X 8 Self- a Low PCl
Check ROM

MAXIMUM RATINGS
This device contains circuitry to protect the
Rating Symbol Value Unit Inputs against damage due to high static
Supply Vollage Vee -0:310 +70 V voltages or electric fields, however, It IS ad-
Inpul Vollage {Excepl Pin 61 V," -0310 +70 V vised that normal precautions be taken to
avoid appllcatlon of any voltage higher than
Operating Temperature Range TA 010 70 'e
maximum rated voltages to this hlgh-
Storage Temperature Range Tslg -5510 +150 'e Impedance Circuit For proper operation It IS
Junction Temperature recommended that V In and Vout be con-
Plasllc 150 strained to the range VSS:S (V in or V out )
::5Vee Reliability of operation IS enhanced If
Ceramic TJ 175 'e
unused Inputs are tied to an appropriate logic
Cerdlp 175 voltage level (e g , either VSS or Vee)

THERMAL CHARACTERISTICS
Characteristic Symbol Value Unit
Thermal Resistance
Plastic 120
Ceramic 8JA 50 'c/w
eerdlp 60

POWER CONSIDERATIONS
The average chip-junction temperature. T J, In °c can be obtained from
TJ=TA+(PD-8JA) (1)
Where:
T A. Ambient Temperature, °c
8JA" Package Thermal ReSistance, Junctlon-to-Amblent, °C/W
PD- PINT+ PPORT
PINT-ICCxVCC, Watts - Chip Internal Power
PPORT- Port Power DISSipation, Watts - User Determined
For most appliCationS PPORT <C PINT and can be neglected PPORT may become significant If the deVice IS configured to
drive Darlington bases or sink LED loads
An approximate relationship between PD and T J (,f PPORT IS neglected) IS
Po = K ... IT J + 273°C) (2)
SolVing equations 1 and 2 for K gives.
K = PO-(T A + 273°C) + 8JA-PD 2 (3)
Where K IS a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at eqUllibnum)
for a known T A. USing this value of K Ihe values of Po and T J can be obtained by solVing equations (1) and (2) Iteratively for any
value of T A.

4·147
 MC6805P2

ELECTRICAL CHARACTERISTICS IVCC~ +525 Vdc±O 5 Vdc, VSS ~ GND, TA ~O" to 70"C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

Input High Voltage
RESET 14 75SVCCs5 75) 40 - VCC
IVCC<475) VCC-O 5 - VCC
iNT 14 75sVCCs5 75) VIH 40
* VCC V
IVCC<475) VCC-O 5
All Other 20
*- VCC
VCC
Input High Voltage Timer
Timer Mode VIH 20 - VCC V
Self-Check Mode - 90 150
Input Low Voltage
RESEi' -03 - 08
-03
INT VIL
-03
* 15 V
All Other - 08
RESET HysteresIs Voltage ISee Figures 11, 12, and 13)
"Out of Reset" VIRES + 21 - 40 V
"I nto Reset" VIRES- 08 - 20
INT Zero Crossing Input Voltage, Through a Capacitor VI NT 20 - 40 Va-c p-p

•
Internal Power DlsslpatlOn- No Port Loading V CC ~ 5 75 V, T A ~ O"C PINT - 400 690 mW
Input Capacitance
EXTAL Cin - 25 - pF
All Other - 10 -
Low Voltage Recover VLVR - - 475 V
Low Voltage Inhibit VLVI - 35 - V
Input Current
TIMER IV,n~O 4 V) - - 20
INT IVIn~2 4 V to VCC) - 20 50
EXTAL IV,n~2 4 V to VCC, crystal OptIOn I lin - - 10 ~A
IVIn~O 4 V, Crystal OptlOnl - - -1600
RESEi' IVIn~O 8 VI -40 - -50
(External Capacitor Chargmg Current)
* Due to Internal biaSing, this Input (when unused) floats to approximately 2 0 Vdc
PORT DC ELECTRICAL CHARACTERISTICS IVCC~ +5 25 Vdc±O 5 Vdc, VSS~GND, TA~O" to 70"C unless othenwlse noted I
Characteristic I Symbol I Min I Typ I Max I Unit
Port A with CMOS Drive Enabled
Output Low Voltage, ILoad~ 1 6 mA VOL - - 04 V
Output High Voltage, ILoad_~ -100 ~A VOH 24 - - V
Output High Voltage, ILoad= -10 ~A VOH 35 - - V
Input High Voltage, ILoad= -300 ~A Imax) VIH 20 - VCC V
Input Low Voltate, ILoad= -500 ~A Imax ) VIL 03 - 08 V
HI-Z State Input Current IV In =2 0 V to VCC) IIH - - -300 ~A
HI-Z State Input Current IVIn=O 4 V) IlL - - -500 ~A
Port B
Output Low Voltage, ILoad = 32 mA VOL - - 04 V
Output Low Voltage, ILoad= 10 mA ISlnk) VOL - - 10 V
Output High Voltage, ILoad= -200 ~A VOH 24 - - V
Darlington Current Drive ISource), VO= 15 V 10H -10 - 710 rnA
Input High Voltage VIH 20 - VCC V
Input Low Voltage VIL -03 - 08 V
HI-Z State Input Current ITS I - 2 20 ~A
Port C and Port A with CMOS Drive Disabled
Output Low Voltage, ILoad =1 6 mA VOL - - 04 V
Output High Voltage, ILoad- -100 ~A VOH 24 - V
Input High Voltage VIH 20 - VCC V
Input Low Voltage VIL -03 - 08 V
HI-Z State Input Current ITSI - 2 20 ~A

4-148
MC6805P2

SWITCHING CHARACTERISTICS IVec ~ + 025 Vde ± 05 Vde, VSS ~ GND, TA ~ 0" 10 70"C unle" olherWlse noledl

Characteristic Symbol M,n Typ Max Unit

Oscillator Frequency IOSC 04 42 MHz
Cycle Time 141 losel tcyc 095 10 ~s

INT and TIMER Pulse W,dlh IWL,IWH leye + 250 - - ns

RESET Pulse Width IRWL leye+ 250 - - ns
RESET Delay Time IExternal Capaeltanee= 1 0 ~FI tRHL - 100 ms
INT Zero Crossing Detection Input Frequency (+ 5° Accuracy) tiNT 003 -
10 kHz
External Clock Input Duty Cycle IEXTALI - 40 50 60 %

FIGURE3 - TIL EQUIVALENT TEST LOAD FIGURE4 - CMOS EQUIVALENT TEST LOAD FIGURE5 - TIL EQUIVALENT TEST LOAD
(PORT BI (PORT AI (PORTS A AND CI

VCC=575V VCC=575V
Test Test
POint Pomt

40 pF
TestPolnt~

I 30 pF IT otall 30 pF

•
1T0tali ITotali

C = 40 pF 1T0tali

SIGNAL DESCRIPTION 4-blt port ICI All lines are prograrnmable as either Inputs or
The tnput and output signals for the M CU, shown tn outputs under software control of the data direction
F'gure 1, are descnbed tn the followtng paragraphs registers Refer to INPUTS/OUTPUTS for add,ttonal tnfor-
matlon
VCC AND VSS - Power IS supplted to the MCU us,ng
these two pins Vec IS power and VSS 's the ground con- MEMORY
nection As shown ,n Figure 6, the MCU IS capable of addressing
INT - ThiS pin provides the capablltty for asynchronously 2048 bytes of memory and I/O registers with ItS program
applYing an external tnterrupt to the MCU Refer to INTER- counter The MC6805P2 MCU has Implemented 128 of these
RUPTS for additional tnformatlon locations ThiS consists of 1100 bytes of user ROM, 116
XTAL AND EXTAL - These ptnS provide connections to bytes of self-check ROM, 64 bytes of user RAM, 6 bytes of
the on-chip clock OSCillator circuit A crystal, a resistor, or an port 1/0, and 2 timer registers
external signal dependtng on the user selectable manufactur- The stack area IS used dunng the processing of Interrupt
tng mask option, can be connected to these ptnS to provide a and subroutine calls to save the processor state The register
system clock source with vanous stability/ cost tradeoffs contents are pushed onto the stack tn the order shown ,n
lead lengths and stray capacitance on these two pins should Figure 7 Because the stack potnter decrements dunng
be minimized Refer to INTERNAL CLOCK GENERATOR pushes, the low order byte IPCU of the program counter 's
OPTIONS for recommendations about these Inputs stacked first, then the high order three bits I PCHI are
stacked ThiS ensures that the program counter IS loaded
TIMER - ThiS ptn allows an external Input to be used to correctly, dunng pulls from the stack, stnce the stack potnter
decrement the Internal timer circuitry Refer to TIMER for Increments dunng pulls A subroutine call results In only the
additional tnformatlon about the timer circUitry program counter IPCl, PCHI contents betng pushed onto
REsET - ThiS ptn allows resetting of the MCU at times the stack The rematntng CPU registers are not pushed
other than the automat,c resetttng capablltty already tn the
MCU Refer to RESETS for additional tnformatlon CENTRAL PROCESSING UNIT
The CPU of the M6805 Family IS Implemented In
NUM - ThiS pin IS not for user appltcatlon and must be
dependently from the 1/0 or memory configuration Conse-
connected to V S S
quently, ,t can be treated as an tndependent central pro-
INPUT/OUTPUT LINES {AO-A7, Bo-B7, CO-C31 - These cessor commUnication w,th I/O and memory via Internal ad-
20 Itnes are arranged Into two 8-blt ports IA and BI and one dress, data, and control buses

4·149
 MC6805P2

FIGURE 6 - MC6605P2 MCU ADDRESS MAP

o 76543210
()()() I/O Ports $()()() $()()()
0 PortA
Timer
1 PortB $001
Page Zero RAM
Access with 127 1128 Bytes! $07F 2 11 1 1 I Port C $002
Short 128 $080 3 Not Used $003
Instructions Page Zero
User ROM 4 PortA DDR $004"
1128 Bytes!
255 \FF 5 Port BOOR $005"
256
Not Used
$100 6 I
Not Used Port C DDR $006"

1704 Bytes! 7 Not Used $007

959 $3BF 8 Timer Data Reg $008

960 $3CO 9 Timer Control Reg $009
Main User
10 $OOA
ROM Not Used
1964 Bytes! 154 Bytes!
1923 $783 63 $03F
1924 $784 64 $040
Self Check RAM

•
ROM 164 Bytes!
1116 Bytes!
2039 $7F7
2040 Interrupt $7F8 Stack
Vectors 131 Bytes
ROM Maximum)
2047 18 Bytes! $7FF 127 1 $07F
"Caution IDDRs! are write-only, they read as $FF

FIGURE 7 - INTERRUPT STACKING ORDER FIGURE 8 - PROGRAMMING MODEl

7 6 5 4 o Pull o
n 4 1 1 1
I COND1T10N
CODE REGISTER n .1
7
I
~--------------~
A I Accumulator
o
n -3 ACCUMULATOR n .2
L..-_ _ _ _ _ _--'
X I Index Register
n -2 INDEX REGISTER n '3 10 o
I'-___
PCH -'-__________
PCl -'1 Program Counter
n -1 1 1 1 1
1 I PCH* n '4
10 5 4

PCL* n '5 10 10I 0 1011 111 SP Stack POinter

Push
Condition Code Register
*For subroutine calis, only PCl and PCH are stacked
Carry/Borrow
REGISTERS
The M6805 Family CPU has five registers available to the Zero
programmer They are shown In Figure 8 and are explained In L -_ _ _ _ Negative
the follOWing paragraphs.
~----- Inlerrupt Mask

ACCUMULATOR (A) - The accumulator IS a general pur- ' - - - - - - - - Half Carry

pose 8-blt register used to hold operands and results of
arithmetiC calculations or data manipulations

4-150
MC6805P2

INDEX REGISTER (X) - The Index register IS an 8-bIt bit IS set the Interrupt :s latched and IS processed as soon as
register used for the Indexed addressing mode. It contains the Interrupt bit IS cleared
an 8-blt value that may be added to an Instruction value to Negative (N) - Used to indicate that the result of the last
create an effective address The Index register can also be arithmetic, logical or data manipulation was negative (bit 7 In
used for data manipulations uSing the read/modify/write in- result equal to a logical one)
structions The Index register may also be used as a tem- Zero (Z) - Used to ,nd,cate that the result of the last
porary storage area arithmetiC, logical or data manipulation was zero
Carry/Borrow (C) - Used to indicate that a carry or bor-
row out of the arithmetic logiC unit (ALU! occurred dUring
PROGRAM COUNTER (PC) - The program counter IS an the last arithmetic operation ThiS bit IS also affected dUring
11-blt register that contains the address of the next instruc- bit test and branch instructions plus shifts and rotates
tion to be executed
TIMER
STACK POINTER (SP) - The stack pOinter IS an 11-blt The MC6805P2 MCU timer circuitry IS shown In Figure 9
register that contains the address of the next free location on The 8-bIt counter may be loaded under program control and
the stack. Initially, the stack pOinter IS set to location $07F IS decremented toward zero by the clock Input (prescaler
and IS decremented as data IS being pushed onto the stack output!. When the timer reaches zero, the timer Interrupt re-
and Incremented as data IS being pulled from the stack The quest bit (bit 7) In the Timer Control Register (TCR) IS set
SIX most significant bits of the stack pOinter are permanently The timer Interrupt can be masked (disabled) by setting the
set to000011 DUring a MCU reset orthe Reset Stack POinter timer Interrupt mask bit (bit 6) In the TCR The Interrupt bit

•
(ASP) InstrUction, the stack pOinter IS set to location $07F ii-bit) In the Condition Code Register also prevents a timer
Subroutines and Interrupts may be nested down to location Interrupt from being processed The MCU responds to thiS
$06+.(31 bytes maximum! which allows the programmer to Interrupt by saving the present CPU state In the stack,
use up to 15 levels of subroutine calls fetching the timer Interrupt vector from locations $7F8 and
$7F9 and executing the Interrupt routine, see the INTER-
RUPTS section The TIMER INTERRUPT REQUEST BIT
CONDITION CODE REGISTER (CC) - The condition MUST BE CLEARED BY SOFTWARE
code register IS a 5-blt register In which four bits are used to
Indicate the results of the instruction Just executed These
bits can be indiVidually tested by a program and speCifiC ac- The clock Input to the timer can be from an external
tion taken as a result of their state Each indiVidual condition source (decrementing of Timer Counter occurs on a positive
code register bit IS explained In the follOWing paragraphs tranSition of the external source! applied to the TIMER Input
pin or It can be the Internal <1>2 Signal When the <1>2 Signal IS
Half Carry (H) - Set dUring ADD and ADC instructions to used as the source, It can be gated by an Input applied to the
Indicate that a carry occurred between bits 3 and 4 TIMER Input pin allOWing the user to easily perform pulse-
Interrupt (I) - Thls..!2!!..!s set to mask (disable) the timer Width measurements. (Note' For ungated <1>2 clock Inputs to
and external Interrupt (lNT) If an Interrupt occurs while thiS the timer prescaler, the TIMER pin should be tied to VCC).

FIGURE 9 - TIMER BLOCK DIAGRAM

"'2
(Internal)

Timer
Interrupt
TIMER
Mask
Input
Pin
r------,
!
I
I
I
L_____ J
Manufacturing
Mask Options

Internal Data Bus

4-151
 MC6805P2

The source of the clock mput IS one of the mask options that RESETS
IS specified before manufacture of the MCU The MCU can be reset three ways by mltlal power-up, by
A prescaler option can be applied to the clock mput that the external reset Input d'iESEi\ and by an optional Internal
extends the timing mterval up to a maximum of 128 counts low voltage detect CirCUit, see Figure 11 The mternal circuit
before decrementmg the counter This prescallng mask op- connected to the RESET pin consists of a Schmitt trigger
tion IS also specified before manufacture which senses the RESET line logiC level The Schmitt trigger
The timer contmues to count past zero, fallmg through to prOVides an Internal reset voltage If It senses a logiC 0 on the
$FF from zero and then continUing the count Thus, the RESET pin DUring power-up, the Schmitt trigger SWitches
counter can be read at any time by readmg the Timer Data on (removes reset) when the RES ET pm voltage rises to
Register (TOR) ThiS allows a program to determme the VIRES + When the RESET pin voltage falls to a logical 0 for
length of time smce a timer Interrupt has occurred, and not a period longer than one tcyc, the Schmitt trigger SWitches
disturb the counting process off to proVide an mternal reset voltage The "switch off"
At Power-up or Reset. the prescaler and counter are voltage occurs at VIRES _ A tYPical reset Schmitt trigger
Inillalized With all logical ones, the timer mterrupt request bit hysteresIs curve IS shown m Figure 12
(bit 7) IS cleared, and the timer mterrupt mask bit (bit 6) IS Upon power-up, a delay of tRHL IS needed before allowmg
set the RESET mput to go high ThiS time allows the Internal
clock generator to stabilize Connectmg a capacitor to the
SELF-CHECK Rt'm Input as shown In Figure 13, tYPically proVides suffi-
The self-check capability of the MC6805P2 MCU proVides cient delay See Figure 17 for the complete reset sequence
an mternal check to determine If the part IS functional Con-
nect the MCU as shown m Figure 10 and monitor the output INTERNAL CLOCK GENERATOR OPTIONS

•
of Port C bit 3 for an OSCillation of approximately 7 Hz A 9 The mternal clock generator CirCUit IS deSigned to require a
volt level on the Timer Input, Pm 7, energizes the ROM- minimum of external components A crystal, a reSistor, a
based self-check feature The self-check program exerCises Jumper Wire, or an external Signal may be used to generate a
the RAM, ROM, timer, mterrupts, and 1/0 ports system clock With various stabilityl cost tradeoffs A

FIGURE 10 - SELF-CHECK CONNECTIONS

-
2 INT MC6805P2 PA7 27
PA6 26
28 RESET PA5 25
~ 10"F PA4 ~
--

~
XTAL PA3 23
PA2 22
EXTAL PAl 21

PAD 20
-
..A12~
'9V
.... 7 TIMER

PB7 19
-
6 NUM PB6 18
vcc
-::r-
-
PB5 17
PB4 16
3300
-"'=!~ 8
PCO PB3
15
-
_'!:
l.~~ ~ ~9 PC1 PB2 14
3300 .h.:; ~1O PC2 PB1 13
'Cl ~11
JlOJ2
v
'PC3 PBO 12
0'
VCC= Pin 3
Vss= Pin 1
*Thls connection depends on the clock OSCillator user selectable mask option
Use crystal If that optIOn IS selected

4-152
MC6805P2

manufacturing mask option IS required to select either the The crystal oscillator startup time IS a function of many
crystal oscillator or the RC oscillator CIrCUit The oscillator variables crystal parameters (especially Rsl, oscillator load
frequency IS Internally divided by four to produce the Internal capacitance, IC parameters, ambient temperature, and
system clocks supply voltage To ensure rapid oscillator startup, neither the
The different connection methods are shown In Figure 14 crystal characteristics nor the load capacitance should ex-
The crystal specifications are given In Figure 15 A resistor ceed recommendations
selection graph IS given In Figure 16

FIGURE 11 - POWER AND RESET TIMING

5V
VCC
OV _ _ _ _ _ _- J

RESET
Pin
-------1'
Internal
Reset
----------~

Out
Of
Reset
FIGURE 12 - TYPICAL RESET SCHMITT
TRIGGER HYSTERESIS FIGURE 13 - POWER UP RESET DELAY CIRCUIT

--.1.-
v CC _1\,/I/\.--+2:::;S'-----,
II
RESET I' O~F
I~
Part Of
MC6805P2
MCU
In
Reset
OSV 2V 4V
FIGURE 14 - CLOCK GENERATOR OPTIONS

5 XTAL XTAL

ISee Note) c::J MC6805P2 MC6S05P2

4 EXTAL MCU EXTAL MCU
I Crystal Mask (Resistor Mask
CL
:c Option) Optlonl

-
Crystal ApprOXimately 25% Accuracy
TYPical tCYC= 1 25 ~s
External Jumper

+5V
XTAL XTAL
R MC6S05P2
External MC6S05P2
4 I See Figure 16} 4 EXTAL MCU
Clock EXTAL MCU
(Resistor Mask
Input ICrystal Mask No
Optloni
Option) Connection

External Clock ApprOXimately 10% Accuracy

External ReSistor
(Excludes ReSistor Tolerance)
NOTE The recommended CL value with a 4 0 MHz crystal IS 27 pF, maXimum, including system distributed capacitance There IS an Internal
capacitance of approximately 25 pF on the XTAL pin For crystal frequencies other than 4 MHz, the total capacitance on each Pin
should be scalled as the Inverse of the frequency ratio For example, with a 2 MHz crystal, use approximately 50 pF on EXTAL and
approximately 25 pF on XTAL The exact value depends on the Motional-Arm parameters of the crystal used

4-153
 MC6805P2

FIGURE 15 - CRYSTAL MOTIONAL ARM PARAMETERS FIGURE 16 - TYPICAL FREQUENCY SELECTION FOR
AND SUGGESTED PC BOARD LAYOUT RESISTOR OSCILLATOR OPTION
50
I I
Crysldl P,IItllllt'tt->r<.,

\ VCC=5 V
f--
EXTAL~~XTAL
40
TA=25'C
N

'"
I
::;;

4·~W
;: 30
u
5
zw "",
i5w 20
AT - Cut Parallel Resonance Crystal a: .........
Co = 7 pF Max u.. r-..... r--...
FREQ=40 MHz @ CL =24 pF 10
RS = 50 ohms Max ......

o 5 10 15 20 25 30 35 40 45 50 55 60
lal RESISTANCE Ik OHMSI
INTERRUPTS

•
The MC6805P2 MCU can be Interrupted three different
ways through the external Interrupt (lNT) mput pin, the
mternal timer Interrupt request, or the software Interrupt m-
structlon (SWII When any Interrupt occurs, processmg IS
suspended, the present CPU state IS pushed onto the stack,
the mterrupt bit (I) m the condition code register IS set, the
address of the mterrupt routme IS obtamed from the
appropriate Interrupt vector address, and the mterrupt
routme IS executed Stackmg the CPU register, settmg the
I-bit. and vector fetchmg requires a total of 11 tcyc periods
for completion
A flowchart of the Interrupt sequence IS shown m Figure
17 The Interrupt service routme must end with a return from
mterrupt (RTII Instruction which allows the MCU to resume
processmg of the program prior to the mterrupt (by unstack-
mg the prevIous CPU state) Table 1 provides a IIstmg of the
mterrupts, their PriOrity, and the address of the vector which
Ibl contams the starting address of the appropriate mterrupt ser-
vice routme The mterrupt PriOrity applies to those pending
when the CPU IS ready to accept a new mterrupt RESET IS
listed In Table 1 because It IS treated as an mterrupt
However, It IS not normally used as an Interrupt. When the
mterrupt mask bit m the Condition Code Register IS set the
mterrupt IS latched for later mterrupt execution
The external mterrupt IS mternally synchrOnized and then
latched on the failing edge of INT A smusoldal mput signal
(fINT maximum) can be used to generate an external mter-
rupt, as shown In Figure 18a, for use as a Zero Crossing
Detector For digital applications the INT can be driven by a
digital signal at a maximum period of tlWL ThiS allows ap-
plications such as servIcing tlme-of-day routmes and engag-
Ing/ dlsengagmg AC power control deVices Off-chip full
wave rectification provides an mterrupt at every zero cross-
mg of the AC signal and thereby proVides a 2f clock
A software mterrupt (SWII IS an executable mstructlon
which IS executed regardless of the state of the I-bit m the
Note Keep crystal leads and CirCUit
Condition Code Register SWl's are usually used as break-
connections as short as possible
pOints for debuggmg or as system calls

4-154
MC6805P2

FIGURE 17 - RESET AND INTERRUPT PROCESSING FLOWCHART

,------.1. N

1-llln CCR)
07F- SP
O-OOR's Stack
CLR INT Logic PC, X,A, CC
FF- Timer
7 F-Prescaler
7F- TCR
N

TCR 6=0
And

•
Put on 7FE TCR 7= 1 Load PC From
SWI 7FC17FD
Address Bus
INT 7FA /7FB
N
Timer 7F8 I7F9

Fetch
Instruction

N{ PIn=
iiESEf
High
PC _ PC + 1 I--,S:..;W-,,-I- '

Load PC
from
7FE17FF
Execute
Instruction

FIGURE 18 - TYPICAL INTERRUPT CIRCUITS

a - Zero Crossing Interrupt b - Digital Signal Interrupt

VCC

AC
Input (Currel'lt TTL 47 k
IflNT Max) Limiting) MC6805P2 Level iNT MC6805P2
Rs 1 Mil ~----;Q~---;~~ MCU Dlgltal------4~_"_t
MCU
Input
AC Input~ 01 IlF
10 Vpp (tIWL Maximum
Period)

lJ

4-155
 MC6805P2

TABLE 1 - INTERRUPT PRIORITIES grammed for outputs, It IS capable of Sinking 10 mA and

sourcing almA on each pin
Interrupt
~ ,
Priority Vector Address
S7FE and S7FF
All Input! output lines are TTL compatible as both Inputs
and outputs Ports Band C are CMOS compatible as Inputs
SWI 2* S7FC and S7FD
Port A may be made CMOS compatible as outputs With a
iNT 3 S7FA and S7FB
mask option The address map In Figure 6 gives the address
Timer 4 S7F8 and S7F9
of data registers and DDRs The register configuration IS pro-
*Pnonty 2 applies when the I-bit In the CondltlOn Code Register IS
Vided In Figure 20 and Figure 21 proVides some examples of
set When 1=0, SWI has a prtOrity of 4, like any other instruction, port connections
the pnorlty of fNT thus becomes 2 and the timer becomes 3 Caution
The corresponding DDRs for ports A, B, and Care
INPUT/OUTPUT write-only registers Ireglsters at $004, $005, and $0061 A
There are 20 Input/ output pins The INT pin may also be read operation on these registers IS undefined. Since
pulled with branch instructions to provide an additional Input BSET and BCLR are read/modify/write functions, they
pin All pins IPort A, B, and CI are programmable as either cannot be used to set or clear a DDR bltlall "unaffected"
Inputs or outputs under software control of the corres- bits would be set I It IS recommended that all DDR bits In
ponding Data Direction Register IDDRI The port I/O a port be written uSing a Single store instruction
programming IS accomplished by writing the corresponding The latched output data bit Isee Figure 191 may always be
bit In the port DDR to a logiC "1" for output or a logiC "0" for written Therefore, any wllte to a port writes all of ItS data
Input On Reset, all the DDRs are initialized to a logiC "0" bits even though the port DDR IS set to Input ThiS may be
state to put the ports In the Input mode The port output used to initialize the data registers and aVOid undefined out-

II registers are not Initialized on Reset but may be written to

before setting the DDR bits to avoid undefined levels When
programmed as outputs, the latched output data IS readable
as Input data, regardless of the logiC levels at the output pin
due to output loading, see Figure 19 When Port B IS pro-
puts, however, care must be exercised when uSing
read/modify/write instructions since the data read cor-
responds to the pin level of the DDR IS an Input 101 and cor-
responds to the latched output data when the DDR IS an out-
put 111

FIGURE 19 - TYPICAL PORT I/O CIRCUITRY

Data
Direction Register
Blt*

~
c
<5 0 Latched
EU Output
-"c ccw Data
- 0 Bit
u

Data
Direction Output Input
Register Data Output To

,,
Sit Sit
0
State
0
MCU
0
1 1 1
0 X 3-State** Pin

*OOR IS a write-only register and reads as all "s

**Ports A (With CMOS dnve disabled), B, and C are three state ports Port A has opllonal Internal pullup deVices
to provide CMOS drive capability Sef~ Eleclflcal Characteristics tables for complete in/ormation

4·156
MC6805P2

FIGURE 20 - MCU REGISTER CONFIGURATION

PORT DATA REGISTER PORT DATA DIRECTION REGISTER IDDRI

a o

Port A Addr= $000 III Write Only, reads as alil's

Port B Addr= $001 12) 1 = Output, a = Input Cleared to a by Reset
Port C Addr= $002 IB,ts 0-31 13) Port A Addr= $004
Port B Addr= $005
Port C Addr= $006 IB,ts 0-31

TIMER CONTROL REGISTER ITCR) TIMER DATA REGISTER ITOR)

6 5 4 3 2 a 7 a
MSB LSB I $008

TCR7- Timer Interrupt Status Bit Set when TDR goes

to zero, must be cleared by software Cleared to
a by Reset
TCR6 Bit 6- Timer Interrupt Mask Bit 1 = timer inter-
rupt masked Idlsabled) Set to 1 by Reset
TCR Bits 5, 4, 3, 2,1,0 read l's-unused bits

FIGURE 21 - TYPICAL PORT CONNECTIONS

8_ Output Modes
II
PA7 27 ICMOS Loads)
PB7 19
PA6 26 ~IO= HFE.lb

-
PA5 25 PB6 18

PM 24 11 TTL Load) PB5 17

-Ib
PA3 23 PB4 16
16mA lamA
PA2 22 PB3 15 2N6386ITYPlcall
PAl 21 PB2 14

PAO 20 PBl 13
PBO 12
-
Port A, Bit 7 Programmed as Output, DriVing
CMOS Loads and Bit 4 DriVing one TTL Load Port B, Bit 5 Programmed as Output, DriVing
Directly luslng_CMOS output option) Darlington-Base Directly
+v +V
PB7 19
PB6 18
PB5 17
PB4 16

-
PC3 11 CMOS
PB3 15
PC2 10 Inverters
PB2 14 MC14049/MCl4069
PBl 13
PCl 9 f - - - -....-+-- ITYPlcall
PBO PCO 8
_lamA

Port B, Bit a and Bit 1 Programmed as Output, Port C, Bits 0-3 Programmed as Output, DriV-
DriVing LEOs Directly Ing CMOS Loads, USing External Pullup
ReSIstors

4·157
 MC6805P2

FIGURE 21 - TYPICAL PORT CONNECTIONS (CONTINUED)

. b. Input Modes

PA7 PB7
PA6 PB6
25 PA5 17 PB5
MC74LS04
MC74LS04 24 PA4 or 16 PB4
!TYPical! MC14069
23 PA3 15 PB3
iTYPlcal!
22 PA2 14 PB2
PA1 PB1
PAO PBO

TTL DriVing Port A Directly CMOS or TTL DriVing Port B Directly

II
PC3
PC2
PC1
PCO

CMOS and TTL Driving Port C Directly

BIT MANIPULATION
The MC6805P2 MCU has the ability to set or clear any. have Individual flags In RAM or to handle 1/0 bits as control
single random access memory or Input/output bit (except lines
the Data Direction Register, see Caution under INPUT/OUT- The coding example In Figure 22 Illustrates the usefulness
PUT paragraph), with a single instruction (BSET, BCLR) of the bit manipulation and test Instructions Assume that
Any bit In page zero Including ROM, except the DDRs, can the MCU IS to communicate with an external senal deVice
be tested, uSing the BRSET and BRCLR Instructions, and The external deVice has a data ready signal, a data output
the program branches as a result of ItS state The Carry bit line, and a clock line to clock data one bit at a time, LBS first,
equals the value of the bit referenced by BRSET or BRCLR out of the deVice The MCU walts until the data IS ready,
A Rotate Instruction may then be used to accumulate serial clocks the external deVice, picks up the data In the Carry Flag
Input data In a RAM location or register The capability to (C-blt), clears the clock line, and finally accumulates the data
work with any bit In RAM, ROM, or 1/0 allows the user to bit In a RAM location

FIGURE 22 - BIT MANIPULATION EXAMPLE

MCU SELF BRSET 2, PORTA, SELF

Ready -2 P
Senal
Clock 0
DeVice
1 R
BSET 1, PORTA
T
Data BRCLR 0, PORTA, CONT
OA
- CONT BCLR 1, PORTA
ASR RAMLOC

4·158
MC6805P2

ADDRESSING MODES INDEXED, 16-BIT OFFSET - In the Indexed, 16-blt offset

The MC6805P2 MCU has 10 addressing modes which are addreSSing mode, the effective address IS the sum of the
explained briefly In the following paragraphs For additional contents of the unsigned 8-blt Index register and the two un-
details and graphical Illustrations, refer to the M6805 Family signed bytes follOWing the opcode ThiS addreSSing mode
User's Manual can be used In a manner Similar to Indexed, 8-blt offset, ex-
The term "effective address" (EAlls used In descrlbmg the cept that thiS 3-byte instruction allows tables to be anywhere
address modes EA IS defined as the address from which the In memory
argument for an instruction IS fectched or stored
BIT SET/CLEAR - In the bit set/clear addreSSing mode,
IMMEDIATE - In the Immediate addreSSing mode, the the bit to be set or cleared IS part of the opcode, and the
operand IS contained In the byte Immediately follOWing the byte follOWing the opcode specifies the address of the byte
opcode The Immediate addreSSing mode IS used to access In which the specified bit IS to be set direct or cleared Thus,
constants which do not change dUring program execution any read/Write bit In the first 256 locations of memory, In-
(e g , a constant used to InitialIZe a loop counterl cluding I/O, can be selectively set or cleared With a Single
2-byte instruction See Caution under the INPUT/OUTPUT
DIRECT - In the direct addreSSing mode, the effective paragraph
address of the argument IS contained In a single byte follow-
Ing the opcode byte Direct addreSSing allows the user to BIT TEST AND BRANCH - The bit test and branch ad-
directly address the lowest 256 bytes In memory with a single dreSSing mode IS a combination of direct addreSSing and
2-byte instruction ThiS Includes the on-chip RAM and I/O relative addreSSing The bit and condition (set or clearl which
registers and 128 bytes of ROM Direct addreSSing IS an ef- IS to be tested IS Included In the opcode, and the address of
fective use of both memory and lime the byte to be tested IS In the Single byte Immediately follow-
Ing the opcode byte The signed relative 8-blt offset IS In the
EXTENDED - In the extended addreSSing mode, the ef- third byte and IS added to the value of the PC If the branch
fective address of the argument IS contained In the two bytes condition IS true ThiS Single 3-byte Instruction allows the
following the opcode Instructions uSing extended address- program to branch based on the condition of any readable
Ing are capable of referenCing arguments anywhere In bit In the first 256 locations of memory The span of
memory with a single 3-byte instruction When uSing the branching IS from + 130 to -125 from the opcode address
Motorola assembler, the programmer need not specify The state of th'Ol tested bit IS also transferred to the Carry bit
whether an Instruction uses direct or extended addreSSing of the Condll,on Code Register See Caution under the
The assembler automatically selects the shortest form of the INPUT/OUTPUT paragraph
Instruction
INHERENT - In the Inherent addreSSing mode, all the In-
RELATIVE - The relative addreSSing mode IS only used In formation necessary to execute the instruction IS contained
branch Instructions In relative addreSSing, the contents of In the opcode Operations speCifYing only the Index register
the8-blt signed byte follOWing the opcode (the offset I IS add- or accumulator, as well as control instruction With no other
ed to the PC If and only If the branch condition IS true Other- arguments, are Included In thiS mode These instructions are
Wise, control proceeds to the next instruction The span of one byte long
relative addreSSing IS from - 126 to + 129 from the opcode
address The programmer need not worry about calculating INSTRUCTION SET
the correct offset when uSing the Motorola assembler, since The MC6805P2 MCU has a set of 59 baSIC instructions,
It calculates the proper offset and checks to see If It IS within which when combined With the 10 addreSSing modes pro-
the span of the branch duce 207 usable opcodes They can be diVided Into five dif-
ferent types register/memory, read/modify/write, branch,
INDEXED, NO OFFSET - In the Indexed, no offset ad- bit manipulation, and control The follOWing paragraphs
dreSSing mode, the effective address of the argument IS con- briefly explain each type All the instructions Within a given
tained In the 8-blt Index register Thus, thiS addreSSing mode type are presented In IndiVidual tables
can access the first 256 memory locations These Instruc-
tions are only one byte long ThiS mode IS often used to REGISTER/MEMORY INSTRUCTIONS - Most of these
move a pOinter through a table or to hold the address of a Instructions use two operands One operand IS either the ac-
frequently referenced RAM or I/O location cumulator or the Index register The other operand IS obtain-
ed from memory uSing one of the addreSSing modes The
INDEXED, 8-BIT OFFSET - In the Indexed, 8-blt offset Jump unconditional (JMPI and Jump to subroutine (JSRI in-
addreSSing mode, the effective address IS the sum of the structions have no register operands Refer to Table 2
contents of the unsigned 8-blt Index register and the unsign-
ed byte follOWing the opcode ThiS addreSSing mode IS READ/MODIFY/WRITE INSTRUCTIONS - These in-
useful In selecting the kth element In an n element table structions read a memorv location or a register, modify or
With thiS 2-byte instruction, k would tYPically be In X With test ItS contents, and write the modified value back to
the address of the beginning of the table In the instruction memory or to the register (see Caution under INPUT/OUT-
As such tables may begin anywhere Within the first 256 PUT paragraphl The test for negative or zero (TSTI Instruc-
addressable locations and could extend as far as location 511 tion IS Included In read/modify/write instructions though It
($lFEI does not perform the write Refer to Table 3

4-159
 MC6805P2

BRANCH INSTRUCTIONS - The branch instructIOns CONTROL INSTRUCTIONS - The control InstructIOns
cause a branch from the program when a certain condition IS control the MCU operatIOns dUring program execution
met Refer to Table 4 Refer to Table 6

BIT MANIPULATION INSTRUCTIONS - These Instruc- ALPHABETICAL LISTING - The complete Instruction set
tions are used on any bit In the first 256 bytes of the memory IS given In alphabetical order ,n Table 7
(see Caution under INPUT/OUTPUT paragraph) One group
either sets or clears The other group performs the bit test OPCODE MAP SUMMARY - Table 8 IS an opcode map
branch operations Refer to Table 5 for the instructions used on the MCU

II

4·160
 TABLE 2 - REGISTER/MEMORY INSTRUCTIONS
s:
n
~
Addressing Modes
Indexed Indexed Indexed
Immediate Direct
Extended (No Offset) (8-Blt Offset) (16-8It Offset)

Function
Op # # Op # # Op # #
MnemoOiC Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles
Op # # Op # #
Code Bytes Cycles Code Bytes Cycles
OP # #
Code Bytes Cycles
;3
Load A from Memory LDA A6 2 2 B6 2 4 C6 3 5 F6 1 4 E6 2 5 D6 3 6
Load X from Memory LDX AE 2 2 BE 2 4 CE 3 5 FE 1 4 EE 2 5 DE 3 6
Store A In Memory STA B7 2 5 C7 3 6 F7 1 5 E7 2 6 D7 3 7
Store X In Memory STX BF 2 5 CF 3 6 FF 1 5 EF 2 6 DF 3 7
Add Memory to A ADD AB 2 2 BB 2 4 CB 3 5 FB 1 4 EB 2 5 DB 3 6
Add Memory and
Carry to A ADC A9 2 2 B9 2 4 C9 3 5 F9 1 4 E9 2 5 09 3 6 I
Subtract Memory SUB AO 2 2 80 2 4 CO 3 5 FO 1 4 EO 2 5 DO 3 6
Subtract Memory from I
A with Borrow SBC A2 2 2 B2 2 4 C2 3 5 F2 1 4 E2 2 5 02 3 6
AND Memory 10 A AND A4 2 2 B4 2 4 C4 3 5 F4 1 4 E4 2 5 D4 3 6
OR Memory with A ORA AA 2 2 BA 2 4 CA 3 5 FA 1 4 EA 2 5 DA 3 6
ExcluSive OR Memory
wllhA EOR A8 2 2 B8 2 4 C8 3 5 F8 1 4 E8 2 5 D8 3 6
Anthmetlc Compare A
with Memory CMP A1 2 2 B1 2 4 C1 3 5 F1 1 4 El 2 5 D1 3 6
Arithmetic Compare X
with Memory CPX A3 2 2 B3 2 4 C3 3 5 F3 1 4 E3 2 5 D3 3 6
~ Test Memory wllh
...... 811
A (Logical Compare) BIT A5 2 2 B5 2 4 C5 3 5 F5 1 4 E5 2 5 05 3 6
0)
...... Jump Unconditional JMP - - BC 2 3 CC 3 4 FC 1 3 EC 2 4 DC 3 5
- FD 1 7 ED 2
2_~~J
Jump to Subroutine JSR - - BD 2 7 CD 3 B 8 DD
- - - - _ . _ ... - -- ---

TABLE 3 - READ/MODIFY/WRITE INSTRUCTIONS

AddreSSing Modes
Indexed Indexed
Inherent (A) Inherent (X) Direct (No Offset) (B Bit Offset)
Op # # Op # # Op # # Op # # Op # #
Function Mnemonic Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles
Incremenl INC 4C 1 4 5C 1 4 3C 2 6 7C 1 6 6e 2 7
Decrement DEC 4A 1 4 5A 1 4 3A 2 6 7A 1 6 6A 2 7
Clear CLR 4F 1 4 5F 1 4 3F 2 6 7F 1 6 6F 2 7
Complement COM 43 1 4 53 1 4 33 2 6 73 1 6 63 2 7
Negate
(2's Complemen1) NEG 40 1 4 50 , 4 30 2 6 70 , 6 60 2 7
Rotate Left Thru Carry ROL 49
,
1 4 59 1 4 39 2 6 79
,
1 6 69 2 7
Rotate Right Thru Carry ROR 46
, 4 56
,
1 4 36 2 6 76
, 6 66 2 7
Logical ShIft Left LSL 4B 4 58
, 4 38 2 6 78 6 68 2 7
Logical Shift Right
Arithmetic Shift Right
LSR
ASR
44
47
1
1
4
4
54
57 , 4
4
34
37
2
2
6
6
74
77
1
1
6
6
64
67
2
2
7
7
Test for Negative
or Zero TST 4D 1 4 50 , --
4 3D 2 6 70 1 6 60 2 7

II _ _ _ _ _ _ _~ ~ 0_ _ _ _ _
- __ _
 MC6805P2

TABLE 4 - BRANCH INSTRUCTIONS

Relative Addressing Mode

Op # #
function Mnemonic Code Byte. Cycles
Branch Always BRA 20 2 4
Branch Never BRN 21 2 4
Branch IFFHlgher BHI 22 2 4
Branch IFF Lower or Same BLS 23 2 4
Branch IFF Carry Clear BCC 24 2 4
(BranchlFFHlgher or Same) (BHS) 24 2 4
Branch IFF Carry Set BCS 25 2 4
(Branch IFF Lower) (BLD) 25 2 4
BranchlFFNot Equal BNE 26 2 4
Branch IFF Equal BEQ 27 2 4
Branch Half Carry Clear BHCC 28 2 4
BranchiFFHaif Carry Set BHCS 29 2 4

..
BranchlFF Plus BPL 2A 2 4
BranchlFF Minus BMI 2B 2 4
Branch IFFlnterupt Mask
BIt IS Clear BMC 2C 2 4
Branch IFF Interrupt Mask
Bit IS Set BMS 20 2 4
Branch IFF Interrupt Line
IS Low BIL 2E 2 4
Branch IFF Interrupt Lme
IS HIgh BIH 2F 2 4
Branch to Subroutme BSR AO 2 8

TABLE 5 - BIT MANIPULATION INSTRUCTIONS

Addressong Modes
Bit SellClear BIt Test and Branch
Op # # Dp # #
Function Mnemonic Code Bytes Cycles Code Bytes Cycles
Branch IFF BIt n IS set BRSET n (n =0 71 - - - 20n 3 10
Branch IFF BIt n IS clear BRCLR n (n =0 71 - - - 01 + 2 • n 3 10
Set BII n BSET n (n - 0 71 10 + 20 n 2 7 - - -
Clear bit n BCLR n (n - 0 71 11 + 2 en 2 7 - - -

TABLE 6 - CONTROL INSTRUCTIONS

Inherent
Op # #
Function Mnemonic Code Bytes Cycles
Transfer A to X TAX 97 1 2
Transfer X to A TXA 9F 1 2
Set Carry BIt SEC 99 1 2
Clear Carry Bit CLC 9B 1 2
Set Interrupt Mask BII SEI 9a 1 2
Clear Interrupt Mask BIt CLI 9A 1 2
Software Interrupt SWI 83 1 11
Return from Subroutine RTS 81 1 6
Return from Interrupt RTI 80 1 9
Reset Stack POinter RSP 9C 1 2
No-Operation NDP 90 1 2

4-162
MC6805P2

TABLE 7 - INSTRUCTION SET

Addressing Modes Condition Code

Bit
Bit
Indexed Indexed Indexed Setl Test &
Mnemonic Inherent Immediate Direct Extended Relative (No Offset) (B Bits) (16 Bits) Clear Branch H I N Z C
ADC X X X X X X
"•"" "
ADD X X
X
X
X
X
X
X
X
X
"• •• " " •"
• • "" ""
AND X X
ASL X X X X
"
X X X
••
• • •" •"
ASR X
BCC X
•"
BClR X
•••• •
BCS X
•••• •
BEQ X
•••• •
BHCC X
•••• •
BHCS X
•••• •
BHI X
•••• •
BHS X
•••• •
BIH X
•••• •
BIL X
•••• •
BIT X X X X X X
••"" •

•
BLO X
•••• •
BLS X
•••• •
BMC X
•••• •
BMI
•••• •
BMS
•••• •
BNE
•••• •
BPL
•••• •
BRA
•••• •
BRN
•••• •
BRCLR X
•••• "
••••
•"
BRSET X
BSET X
••••
BSR X
•••• •0
CLL X
••••
CLI X
• 0 0• •, •
CLR X X X X
•• •
CMP X X X X X X
•• /\ /\
,
/\
COM X X X X
•• /\ /\
CPX X X X X X X
•• /\ /\ /\
DEC X X X X
•• /\ /\
•
EOR X X X X X X
•• /\ /\
•
INC X X X X
•• /\ /\
•
JMP X X X X X
•••• •
JSR X X X X X
•••• •
LDA X X X X X X
••" /\
•
LDX X X X X X X
•• /\ /\
•
LSL X X X X
• • 0" /\ /\
LSR X X X X
•• /\ /\
NEQ X X X X
•• /\ /\ /\
NOP X
•••• •
ORA X X X X X X
•• " /\
•
ROL X X X X
•• /\ /\ /\
RSP X
•••• •
Condition Code Symbols
H Half Carry (From Bit 31 C Carry/Borrow
Interrupt Mask A Test and Set If T rue, Cleared Otherwise
N Negative (Sign Bltl • Not Affected
Z Zero

4·163
 MC6805P2

TABLE 7 - INSTRUCTION SET (CONTINUED)

Addressing Modes Condition Code

Bit Bit
Indexed Indexed Indexed Set! Test &
Mnemonic Inherent Immediate Direct Extended Relative (No Offset) (8 Bits) (16 Bots) Clear Branch H I N Z C
RTI X ? ? ? ? ?
RTS X
•• •• •
SBC X X X X X X
•• A A A
SEC X
•••• 1
SEI X
• ••1
•
STA X X X X X
•• A A
•
STX X X X X X
•• A A
•
SUB X X X X X X
•• A A A
SWI X
• ••1
•
TAX X
•• • • •
TST X X X X
•• A A
•
TXA X
•••• •

•
Condition Code Symbols
H Half Carry (From Bit 3) C Carry! Borrow
I Interrupt Mask A Test and Set If True, Cleared Otherwise
N Negat,ve (S'gn B,tl • Not Affected
Z Zero ? Load CC Register From Stack

4-164
 s:
(')
TABLE 8 - M6805 FAMILY OPCODE MAP

~j:3
L~t

~
'0
Bit Manipulation
BTB
cx'ix,
BRSEJ~A
5 7
.ri"
BSE1~c
5 4
Branch
REL
00'\.
2 BRARFL
3 6

2
DIR
~,
NEG
DIA
5 4
.
INH A
,':,.
, NEGAINH
Read! Modify /Wnte

3
INHIXI

4
.~,
NEGX
3
INH
IX,

2
.
.~
NEG
6 6
IX
.~,
NEG
5
IX
9

1
INH
,~
RTI
Control

INH
INH
.~~
2
IMM
"~n
SUB
IMM
2 4

2
DIR
,~,
SUB
3
DIR
5
3 SUB
Register I Memory
EXT
,~
4 6
I
'~1
XT 13 SUB IX2
5 5
X,
,,~n
2 SUB
4

IXl
4

1
I
,i"
SUB
3
IX
HI....----C;-W
0
lIDO
1 IX' 1
10 5 7 5 4 3 6 6 2 2 4 3 5 4 6 5 5 4 4 3
CMP CMP CMP 1
1 2 BCL~~e 12 BRNAEL
BRCLRO RTS CMP CMP CMP
CXXll 3 STS 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IXl I IX eml
'0 5 7 5 4 3 2 2 4 3 5 4 6 5 5 4 4 3
2 BASETI BSETI BHI SBC SBC SBC SBC SBC SBC 2
00'0 3 STS 2 sse 2 AE 2 IMM 2 OIR 3 EXT 3 IX2 2 IXl 1 IX 0010
'0 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 11 10 2 2 4 3 5 4 6 5 5 4 4 3
COMA CPX CPX CPX CPX 3
2 BCL~~e 2 BLSAEL
3 BRCLRI COM COMX COM COM SWI CPX CPX
0011 3 STS 2 DIR 1 INH 1 INH 2 IXl 1 IX 1 INH 2 IMM 2 DIA 3 EXT 3 IX2 2 IXl 1 IX 0011
'0 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 2 2 4 3 5 4 6 5 5 4 4 3
4 BRSET2 BSET2 17 BCC LSR LSRA LSRX LSR LSR AND AND AND AND AND AND 4
0100 3 STS sse AEL 2 DIR 1 INH 1 INH 2 IXl 1 IX 2 IMM 2 DIR 3 EXT 3 IX2 2 IXl 1 IX 0100
10 5 7 5 4 3 2 2 4 3 5 4 6 5 5 4 4 3
BIT
2 BCL~~e
BIT BIT BIT BIT 5
5
0101 3
BACLA2
STS
I, BCSAE BI~MM IR 3 EXT 3 IX2 2 IXl 1 IX 0101
10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 2 2 4 3 5 4 6 5 5 4 4 3
6
0110 3
BRSET3
STS BSE~~c 12 BNEAEL 2 ROR
DIR 1
RORA
INH 1
RORX
INH
ROR
IXl 1
ROR
IX 2
LOA
IMM 2
LOA
DIR 3
LOA
EXT 3
LOA
IX2 2
LOA
IXl 1
LOA
IX
6
0110
10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 2 2 5 4 5 7 6 6 5 5 4
7 BACLA3 BCLR3 BEQ ASRA ASRX ASR ASR TAX STA , STA STA STA STA 7
7 ASR
0111 3 STS 2 asc 2 AE DIR 1 INH 1 INH 2 IXl 1 IX 1 INH 2 DIA 3 EXT 3 IX2 2 IXl 1 IX 0111
10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 2 2 2 2 4 3 5 4 6 5 5 4 4 3
8 BASET4 BSET4 BHCC 2 LSL LSLA LSLX LSL LSL CLC I, EORIMM EOR EOR EOR EOR EOR 8
lem 3 TS 2 sse 2 AE DIA 1 INH 1 INH 2 IXl 1 IX H 2 DIR 3 EXT 3 IX2 2 IXl 1 IX 1000
10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 2 2 2 2 4 3 5 4 6 5 5 4 4 3
2 BCL~~c
9 BRCLR4 BHCS AOL AOLA ROLX ROL AOL SEC ADC ADC ADC ADC ADC ADC 9
1001 3 STS 2 REl 2 DIA 1 INH 1 INH 2 IXl 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IXl 1 IX 1001
10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 2 2 2 2 4 4 5 4
~
...... A
1010 3BASEJis 2 BSE~~c 2
BPL
REL
2 DEC
DIR 1
DECA
INH 1
DECX
INH 2
DEC
IXl 1
DEC
IX 1
CLI
INH 2
ORA
IMM 2
ORA 4
DIR
.0 ORA
3 EXT 3
ORA
IX2
5 OAA 4
2 IXl 1
ORA
IX
A
1010
3 3
m B
10
BRCLA5
5 7
BCLR5
5 4
BMI
2
SEI
2 2
ADO
2
4 ADO 3
5
ADD
4 6
ADO' , ADO
4 4
ADD B I
01 1011 3 STS 2 ssc 2 AEL 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IXl 1 IX 1011
10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 2 2 3 2 4 3 5 4 4 3 3 2
C BRSET6 BSET6 BMC INCA INCX INC RSP JMP JMP JMP JMP JMP C I
2 INC DIA .2 INC IXl IX
1100 STS 2 ssc 2 AEL 1 INH 1 INH IXl 1 IX 1 INH 2 DIA 3 EXT 3 IX2 2 1 1100
10 5 7 5 4 3 , 4 4 3 4 3 7 5 6 4 2 2 S 6 7 5 6 9 7 S 6 7
'6 JSR JSR '
0 BACL~~A , BCL~~r BMS
REL , TS~mA TSTA TSTX
INH
'2 TST
IXl
TST NOP BSR JSR
EXT
JSR
IX2 2
JSR
IXl IX
0
111
10 5 7 5 4 3
, INH 1 1 IX
2
1 INH 2
2
REL
2
2
4
DIA 3 3
5 5 , 1
4 3
'101
LOX 4 " LOX 4 , LOX
2 BSE~Ic
E BRSET7 BIL STOP LOX LOX LOX E
1110 3 BTB 2 AEL 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IXl 1 IX 1110
10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 2 2 2 5 4 6 5 7 6 6 5 5 4
F BACLA7 BCLA7 BIH CLR CLAA CLAX CLA CLR WAIT TXA STX STX STX STX STX F
1111 3 STS 2 __ B,~C 2 AEL 2 DIR 1 INH 1 INH -' IXl 1 IX 1 INH 1 INH 2 DIR 3 EXT 3 IX2 2 IXl 1 IX 1111

Abbreviations for Address Modes LEGEND

INH
IMM
Inherent
Immediate
'-'F:::;...E=+----------::::;;>,.. Opcode In Hexadecimal
DIR
EXT
REL
Direct
Extended
Relative
# of Cycles IHMOS VersIons)
Mnemonic
j.4··· ~
.. SUB
~
0
Opcode In Binary

BSC Bit Setl Clear Bytes , IX 0000

)
BTB Bit Test and Branch
IX Indexed (No Offset! # of Cycles (CMOS Verslonsl--------' " Address Mode
IX, Indexed, , Byte IS-Bltl Offset
IX2 Indexed, 2 Byte ('6-BIt! Offset
CMOS Versions Only

•
 MC6805P2

ORDERING INFORMATION

The Information reqUired when ordenng a custom MCU IS signed, and returned to Motorola The signed venf,cat,on
listed below The ROM program may be transmitted to form constitutes the contractual agreement for creation of
Motorola on EPROM(s) or a MOOS disk file the customer mask If deSired, Motorola Will program on
To Initiate a ROM pattern for the MCU It IS necessary to blank EPROM from the data file used to create the custom
first contact your local Motorola representative or Motorola mask and aId In the Verification process
dlstnbutor
ROM VERIFICATION UNITS (RVUs!
EPROMs - The MCM2716 or MCM2532 type EPROMs, pro- Ten MCUs containing the customer's ROM pattern Will be
grammed with the customer program (positive logiC sense sent for program venf,cat,on These units Will have been
for address and data), may be submitted for pattern genera- made uSing the custom mask but are for the purpose of
tion The EPROM must be clearly marked to indicate which ROM venf,cat,on only For expediency they are usually un-
EPROM corresponds to which address space The recom- marked, packaged In ceramiC, and tested only at room
mended marking procedure IS Illustrated below temperature and 5 volts These RVUs are Included In the
mask charge and are not production parts The RVUs are
thus not guaranteed by Motorola Quality Assurance,and
xxx should be discarded after venf,cat,on IS completed

FLEXIBLE DISKS
The disk media submitted must be Single-sided, slngle-

II 000

xxx = Customer ID
400
denSity, 8-lnch, MOOS compatible flOPPies The customer
must wnte the binary file name and company name on the
disk With a felt-tip pen The minimum MOOS system files as
well as the absolute binary object file (filename LO type of
file) from the M6805 cross assembler must be on the disk An
object file made from a memory dump uSing the ROLLOUT
After the EPROM(s) are marked they should be placed In command IS also acceptable Consider submitting a Source
conductive IC carners and securely packed Do not use Iisling as well as the follOWing files filename, LX (EXOR-
styrofoam ciser'" loadable format! and filename, SA (ASCII Source
Code! These files will of course be kept confidential and are
VERIFICATION MEDIA used 11 to speed up the process In-house If any problems
All onglnal pattern media (EPROMs or Floppy Disk! are fil- anse, and 2) to speed up the user-to-factor Interface If the
ed for contractual purposes and are not returned A com- user finds any software errors and needs assistance qUickly
puter listing of the ROM code Will be generated and returned from Motorola factory representatives
along With a lisling venficatlon form The listing should be MOOS IS Motorola's Disk Operating system available on
thoroughly checked and the venf,cat,on form completed, development systems such as EXORCisers, EXORsets, etc

4·166
MC6805P2

MC6805P2 MCU ORDERING INFORMATION

Date _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Customer PO Number _ _ _ _ _ _ _ _ _ _ __

Customer Company _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Motorola Part Numbers

MC ______________
Address _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
SC ______________
City _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ State _ _ _ _ _ _ _ _ _ _ _ _ _ _ Z,p __________

Country _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Phone _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Extenslon _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___

Customer Contact Person _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Customer Part Number

OPTION LIST
Select the options for you r M CU from the following list A
manufacturing mask will be generated from this Information

Timer Clock Source

o
o
Internal </>2 clock
TIMER Input pin

Timer Prescaler
II
o2' (divide by 1) o 2' (divide by 16)
o2' (divide by 2) o 2' (divide by 32)
o2' (divide by 4) o 2' (divide by 64)
o2' (divide by 8) o 2' (divide by 128)

Internal Oscillator Input Port A Output Drive

o Crystal o CMOS and TTL
o ReSistor o TTL Only

Low Voltage Inhibit

oDisable
oEnable

Pattern Media (All other media reqUIres pnor factory approval)

o EPROMs (MCM2716 or MCM2532 o Floppy Disk
o Other

Clock Freq _ _ _ _ _ _ _ _ _ _ _ _ __

Temp Range _ _ _ _ _ _ _ _ _ _ _ _ _ _ DO' to + 70'C IStandardl o _40' to +85°C*

*Requlres pnor factory approval

Marking Information (12 Characters MaXimum)

Title ________________________________________________________________________________

S,gnature _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

4·167
 @ MOTOROLA MC680SP4

Advance InforD1ation
HMOS
(HIGH DENSITY
N·CHANNEL, SILICON-GATE.
DEPLETION LOADI
8-81T MICROCOMPUTER UNIT
8-BIT
The MC6805P4 Microcomputer Unit IMCUI IS a member of the MICROCOMPUTER
M6805 Family of low-cost single-chip microcomputers This 8-bIt
microcomputer contains a CPU, on-chip CLOCK, ROM, RAM, I/O, and
TIMER. It IS designed for the user who needs an economical microcom-
puter with the proven capabilities of the M6800-based instruction set. A
comparison of the key features of several members of the M6805 Family
IS shown on the last page of this data sheet The following are some of
the hardware and software highlights of the MC6805P4 MCU
HARDWARE FEATURES:
• S-Blt Architecture
• 112 Bytes of Standby RAM
• Standby RAM Power Pin

•
• Memory Mapped I/O
• 1100 Bytes of User ROM
• 20 TTL/CMOS Compatible Bidirectional I/O Lines (S Lines are
LED Compatlblel
• On-Chip Clock Generator
• Self-Check Mode
• Zero Crossing Detection PLASTIC PACKAGE
CASE 710
• Master Reset
• Complete Development System Support on EXORCiser'"
• 5 V Single Supply
SOFTWARE FEATURES:
• Similar to M6800 Family
• Byte Efficient Instruction Set
CERDIP PACKAGE
• Easy to Program CASE 733
• True Bit Manipulation
• Bit Test and Branch Instructions
• Versatile Interrupt Handling FIGURE 1 - PIN ASSIGNMENTS
• Versatile Index Register
• Powerful Indexed Addressing for Tables Vss ~
• Full Set of Conditional Branches INT PA7
• Memory Usable as Register/Flags VCC PA6
• Single Instruction Memory Examine/Change EXTAL PA5
• 10 Powerful Addressing Modes XTAL PA4
• All Addressing Modes Apply to ROM, RAM, and I/O
VSB PA3
USER SELECTABLE OPTIONS:
TIMER' PA2
• Internal8-Blt Timer With Selectable Clock Source IExternal Timer
Input or Internal Machine Clockl PCO/NUM PAl
• Timer Prescaler Opllon 17 Bits 2NI PCl PAO
• S Bidirectional I/O Lines With TTL or TTL/CMOS Interface Opllon PC2 PB7
• Crystal or Low-Cost Resistor OSCillator Option PC3 PB6
• Low Voltage Inhibit Opllon PBO PB5
• 4 Vectored Interrupts, Timer, Software, and 2 External PBl PB4
PB2 PB3

4-168
MC6805P4

FIGURE 2 - MC6805P4 HMOS MICROCOMPUTER BLOCK DIAGRAM

RESET 1m

)
TIMER

NUM PBO
Accumulator PBt
A CPU PB2 Port
Data Port
Control PB3 B
Index Dir B PB4 110
Register Reg Reg PB5
x Lines
PAO PBS
PAl Condition PB7
Port PA2 Code
Port Data
A PA3 Register ec
A Oir.
liD PA4 CPU
Reg. Reg. Stack
Lmes PA5
PAS POinter
PA7 SP PCO/NUM Pon
Program Data Port
PCt C
Counter Dir C PC2 I/O
Hi h peH Reg Reg PC3 Ltnes
ALU
1100 X 8 Program
User ROM Counter
116 X 8 Self- Low pel
Check ROM VSB

MAXIMUM RATINGS

Supply Voltage
Ratlno

Input Voltage IExcept PCO/NUMI

Operating Temperature Range
Storage Temperature Range
Junction Temperature
PlastiC
Symbol
Vce
VIO
TA
Tstg
Value
-03 to + 70
-03to +70
o to 70
-55 to + 150

150
Unit
V
V
'(
O(
ThiS device contains circuitry to protect the in-
puts against damage due to high static voltages
or electncal fields, however, It IS adVised that
normal precautions be taken to avoid application
of any voltage higher than maximum rated
voltages to thiS high-Impedance circuit For pro-
per operation It IS recommended that Vin and
Vout be constrained to the range VSS~(VIn or
V out) ~ V CC Reliability of operation IS enchanc-
•
ed If unused Inputs except EXTAL are tied to an
Ceramic TJ 175 '(
appropnate logiC voltage level (e 9 , either VSS
Cerdlp 175
or Vee!
THERMAL CHARACTERISTICS
Characteristic Symbol Value Unit
Thermal Resistance
PlastiC 120
8JA 'C/W
Ceramic 50
Cerdlp 60

POWER CONSIDERATIONS
The average Chip-Junction temperature, T J, In 'C can be obtained from'
T J=TA + (PO"8JAI (1)
Where'
TA-Amblent Temperature, 'C
8JA-Package Thermal Resistance, Junctlon-to-Amblent, °C/W
Po - PINT + PPORT
PINT -ICC x V CC, Watts - Chip Internal Power
PPORT - Port Power DiSSipation, Watts - User Determined
For most applications PPORT<C PINT and can be neglected. PPORT may become significant If the deVice IS configured to
drive Darlington bases or Sink LED loads.
An approximate relationship between Po and T J (If PPORT IS neglected) IS:
PO=K+(TJ+273°C) (2)
SolVing equations 1 and 2 for K gives:
K = PO"(T A + 273°C) +8JA"P 0 2 (31
Where K IS a constant pertaining to the particular part. K can be determined from equation 3 by measuring Po (at equllibrluml
for a known T A. USing this value of K the values of Po and T J can be obtained by solVing equations (1) and (2) Iteratively for any
value of TA.

4-169
 MC6805P4

SWITCHING CHARACTERISTICS IVCC= + 525 Vdc ± 05 Vdc. VSS = GND. TA =0° to 50° unless otherwise notedl
Characteristic Symbol Min Typ Max Unit
Oscillator Frequency 10SC 04 - 42 MHz
Cycle Time (4/ fascl tcyc 095 - 10 ~s

INT and TIMER Pulse Width tWL.tWH t cyc + 250 - - ns

RESET Pulse Width tRWL t cyc + 250 - - ns

RESET Delay Time (External Capacitance:::: 1 a ttFI 'RHL - 100 - ms

INT Zero Crossing Detection Input Frequency (± 5° Accuracy) liNT 003 - 10 kHz

External Clock Input Duty Cycle IEXTALI - 40 50 60 %

ELECTRICAL CHARACTERISTICS IVCC= + 525 Vdc±O 5 Vdc. VSS= GND. TA=O' to 70 c C unless otherwise notedl

Characteristic Symbol Min Typ Max Unit

Input High Voltage
RESET 14 75:5VCC:55 751 40 - VCC

II
IVCC<4751 VCC-O 5 - Vce
INT 14 75:5VCC:55 751 VIH 40 * VCC V
VCC-O 5
IVCC<4751
* Vce
All Other 20 - VCC
Input High Voltage Timer
Timer Mode V,H 20 -
Vee V
Self-Check Mode -- 90 150
Input Low Voltage
RESET -03 - 08
-03
INT Vil * 15 V
All Other -03 - 08
RESET HysteresIs Voltage ISee Figures 11. 12. and 131
"Out of Reset" VIRES ~ 21 - 4C V
"Into Reset" VIRES - 08 - 20
INT Zero Crossing Input Voltage, Through a Capacitor VI NT 20 - 40 Va-c p-p
Internal Power DISSipation - No Port Loading Vee == 5 75 V ITA = aoe PINT - 400 TBD mW
Input Capacitance
EXTAL C,n - 25 - pF
All Other - 10 -

Low Voltage Recover VLVR - - 475 V

Low Voltage Inhibit VLVI - 35 - V
Input Current
TIMER IV,n=O 4 VI - - 20
TNT IV tn =24 V to VCC. Crystal OptiOnl - 20 50
EXTAL IV,n=O 4 V. Crystal OptiOnl lin - - 10 ~A
IV ,n =04VI - - --1600
RESET IV ,n = 08 VI -40 - -50
(External Capacitor Charging Current)
* Due to Internal braslng, thiS Input (when unused) floats to approximately 2 a Vdc

4-170
MC6805P4

PORT DC ELECTRICAL CHARACTERISTICS IVCC= + 525 Vdc -+ 05 Vdc, VSS = GND, T A = 0° to 70'C unless otherwise noted}
Characteristic Symbol Min Typ Max Unit I I
Port A with CMOS Drive Enabled
Output Low Voltage, ILoad= 1 6 rnA VOL - - 04 V
Output High Voltage, ILoad= -100 ~A Vm 24 - - V
Output High Voltage, ILoad= -10 ~A VOH 35 - - V
Input High Voltage, ILoad= -300 ~A Imax) VIH 20 - VCC V
Input Low Voltate, ILoad= -500 ~A Imax) VIL -30 - 08 V
HI-Z State Input Current IV,n = 2 0 V to VCC) IIH - - -300 ~A
HI-Z State Input Current IV In = 04 V) IlL - - -500 ~A
Port B
Output Low Voltage, ILoad=3 2 rnA VOL - - 04 V
Output Low Voltage, ILoad= 10 rnA ISlnk) VOL - - 10 V
Output High Voltage, ILoad= -200 ~A VOH 24 - - V
Darlington Current Drive (Source), VO= 15 V IOH -10 - -10 rnA
Input High Voltage VIH 20 - VCC V
Input Low Voltage VIL -03 - 08 V
HI-Z State Input Current ITSI - 2 20 ~A

•
Port C and Port A with CMOS Drive Disabled
Output Low Voltage, ILoad = 1 6 rnA VOL - - 04 V
Output High Voltage, ILoad - -100 ~A VOH 24 - - V
Input High Voltage VIH 20 - VCC V
Input Low Voltage VIL -03 - 08 V
HI-Z State Input Current ITSI - 2 20 ~A

STANDBY RAM CHARACTERISTICS ITernperature=O°C, VSB= Maxi

Characteristic Symbol Min Typ Max Unit

Standby Current
16 Bytes - 16 TBD
64 Bytes ISB - 34 TBD ~A
112 Bytes - 52 TBD
RAM Standby Volt"fLe VSB TBD 525 TBD V
VCC Turn-off Rate VCCTO - - 1/100 V/~s

FIGURE3 - TTL EQUIVALENT TEST LOAD FIGURE4 - CMOS EQUIVALENT TEST LOAD FIGURE5 - TTL EQUIVALENT TEST LOAD
(PORT B) (PORT AI (PORTS A AND C)

VCC=5 75 V
Test MMD6150
POint or Equlv 297 kW
TestPolnt~

130 pF ITotall 30
pF 24 kO MMD7000
or Equlv
I Totall

C = 40 pF 1T0tail

4-171
 MC6805P4

INPUT/OUTPUT LINES (AO-A7, BO-B7, CO-eJ) - These

SIGNAL DESCRIPTION 20 lines are arranged Into two 8-blt ports IA and B) and one
The Input and output signals for the MCU, shown In 4-blt port (C) All lines are programmable as either Inputs or
Figure 1, are described In the follOWing paragraphs outputs under software control of the data direction
VSB, VCC, VSS - Power IS supplied to the MCU uSing registers Refer to INPUTS/OUTPUTS for additional Infor-
these two pinS VCC IS power and VSS IS the ground con- mation
nection MEMORY
VSB IS the standby RAM voltage In order to allow orderly As shown In Figure 6, the MCU IS capable of addreSSing
transition Into the standby mode, the turn-off rate of VCC 2048 bytes of memory and I/O registers With ItS program
must not exceed 1 volt per 100 ns counter The MC6805P4 MCU has Implemented 1336 of
these locations ThiS conSists of 1100 bytes of user ROM,
TNT - ThiS pin provides the capability for asynchronously
116 bytes of self-check ROM, 112 bytes of user RAM, 6
applYing an external Interrupt to the MCU Refer to INTER-
bytes of port 1/0, and 2 timer registers
RUPTS for additional Information
The stack area IS used dUring the processing of Interrupt
XTAl AND EXTAl - These pins provide connections to and subroutine calls to save the processor state The register
the on-chip clock OSCillator CirCUit A crystal, a resistor, or an contents are pushed onto the stack In the order shown In
external signal depending on the user selectable manufactur- Figure 7 Because the stack pOinter decrements dUring
Ing mask option, can be connected to these pins to provide a pushes, the low order byte I PCL! of the program counter IS
system clock source with various stability/cost tradeoffs stacked flrsl, then the high order three bits I PCH) are
Lead lengths and stray capacitance on these two pins should stacked ThiS ensures that the program counter IS loaded
be minimized Refer to INTERNAL CLOCK GENERA TOR correctly, dUring pulls from the stack, since the stack pOinter
OPTIONS for recommendations about these Inputs Increments dUring pulls A subroutine call results In only the

II TIMER - ThiS pin allows an external Input to be used to

decrement the Internal timer circuitry Refer to TIMER for
additional Information about the timer CIrcuitry
RESET - ThiS pin allows resetting of the MCU at times
other than the automatic resetting capability already In the
program counter (PCl, PCH) contents being pushed onto
the stack The remaining CPU registers are not pushed

CENTRAL PROCESSING UNIT

The CPU of the M6805 Family IS Inplemented in-
dependently from the I/O or memory configuration Conse-
MCl! Refer to RESETS for additional Information quently, It can be treated as an Independent central pro-
NUM - ThiS pin IS not for user application and must be cessor communication With 1/0 and memory via Internal
connected to VSS address, data, and control buses

4-172
MC6805P4

FIGURE 6 - MC6805P4 MCU ADDRESS MAP

o 76543210
000 SOOO
I 0 Ports 0 Port A SOOO
Timer
1 Port B SOOl
Page Zero RAM
(128 Byles) 2 1 1 1 Port C S002
Access with 127 $07F 11
Short

~::
128 3 Not Used SOO3
Instructions Page Zero
User ROM 4 Port A DDR S004*
1128 Bytes)
255 5 Port BOOR S005*
256 S100
6 Not Used I Port C DDR S006*
Not Used
7 Not Used S007
1704 Bytes)
8 Timer Data Reg S008
959 S3BF
960 S3CO 9 Timer Control Reg S009
Main User
10 SOOA
ROM Not Used
1964 Bytes) 16 Bytes)
1923 s783
15 $oaF
1924 S784
Self Check 16 RAM $010

•
ROM (112 Bytes)
{1 1 6 Bytes}
2039 s7F7 Stack
2040 S7F8
Interrupt 131 Bytes
Vectors Maximum)
ROM

2047
(8 Bytes)
s7FF 127 t S07F
*Cautlon (DORs) are write-only, they read as $FF

FIGURE 7 - INTERRUPT STACKING ORDER FIGURE 8 - PROGRAMMING MODEl

I
0 Pull

CONDITION A Accumulator
n 4 1 1 1 CODE REGISTER n'l

n -3 ACCUMULATOR n '2 Index Register

n -2 INDEX REGISTER 10 a
n '3
L.'-'P_C=-H_-'-_ _ _ _ _ _P-'C.::L_ _ _ _...JI Program Counter
n -1 1 1 1 1
II PCH:* n '4 10 5 4
SP Stack POinter
PCL* n '5

Push
Condition Code Register
*For subroutine calls, only peL and PCH are stacked
Carry/Borrow
REGISTERS
The M6805 Family CPU has five registers available to the Zero
programmer They are shown In Figure 8 and are explained In ' - - - - - Negalive
the following paragraphs ' - - - - - - Interrupt Mask

ACCUMULATOR (A) - The accumulator IS a general pur- ' - - - - - - - Half Carry

pose 8-blt register used to hold operands and results of
arithmetic calculations or data manipulations.

4-173
 MC6805P4

INDEX REGISTER (X) - The Index register IS an 8-bIt bit IS set the Interrupt IS latched and IS processed as soon as
register used for the Indexed addressing mode It contains the Interrupt bit IS cleared
an 8-blt value that may be added to an instruction value to Negative (Nl - Used to ,nd,cate that the result of the last
create an effective address The Index register can also be arithmetic, (oglcal or data manipulation was negative (bit 7 In
used for data manipulations uSing the read/modify/write In- result equal to a logical one)
structions. The Index register may also be used as a tem- Zero (Zl - Used to indicate that the result of the last
porary storage area arithmetic, logical or data manipulation was zero
Carry/Borrow (Cl - Used to Indicate that a carry or bor-
PROGRAM COUNTER (PC) - The program counter IS an row out of the arithmetic logiC Unit (ALU) occurred dUring
tt-blt register that contains the address of the next instruc- the last arithmetic operation. ThiS bit is also affected dUring
tion to be executed bit test and branch instructions plus shifts and rotates

STACK POINTER (SP) - The stack pOinter IS an tt-bit TIMER

register that contains the address of the next free location on The MC6805P4 MCU timer circuitry IS shown In Figure 9.
the stack Initially, the stack pOinter IS set to location $07F The 8-blt counter may be loaded under program control and
and IS decremented as data IS being pushed onto the stack IS decremented toward zero by the clock Input Iprescaler
and Incremented as data IS being pulled from the stack. The output) When the timer reaches zero, the timer Interrupt re-
SIX most significant bits of the stack pOinter are permanently quest bit (bit 7) In the Timer Control Register (TCR) IS set
set to 000011 DUring a MCU reset or the Reset Stack POinter The timer Interrupt can be masked (disabled) by setting the
(RSPI instruction, the stack pOinter IS set to location $07F timer Interrupt mask bit Iblt 6) In the TCR The Interrupt bit
Subroutines and Interrupts may be nested down to location II-bit) In the Condition Code Register also prevents a timer
$061 (31 bytes maxlmuml which allows the programmer to

•
Interrupt from being processed The MCU responds to thiS
use up to 31 levels of subroutine calls Interrupt by saving the present CPU state In the stack,
fetching the timer Interrupt vector from locations $7F8 and
CONDITION CODE REGISTER (CCI - The condition $7F9 and executing the Interrupt routine, see the INTER-
code register IS a 5-blt register In which four bits are used to RUPTS section The TIMER INTERRUPT REQUEST BIT
,nd,cate the results of the instruction lust executed These MUST BE CLEARED BY SOFTWARE
bits can be Individually tested by a program and specific ac- The clock Input to the timer can be from an external
tion taken as a result of their state. Each individual condition source (decrementmg of TImer Counter occurs on a POSItive
code register bit IS explained In the follOWing paragraphs transition of the external source) applied to the TIMER Input
pin or It can be Internal <1>2 signal. When the <1>2 signal IS used
Half Carry (HI - Set dUring ADD and ADC instructions to as the source, It can be gated by an Input applied to the
Indicate that a carry occurred between bits 3 and 4 TIM ER Input pin allOWing the user to eaSily perform pulse-
Interrupt (IJ - Thls!!!.L!s set to mask (disable) the timer Width measurements. (Note for ungated <1>2 clock Inputs to
and external Interrupt (INT) If an Interrupt occurs While thiS the timer prescaler, the TIMER pin should be tied to CCC.)

FIGURE 9 - TIMER BLOCK DIAGRAM

Timer
Interrupt
TIMER
Mask
Input
Pin
,..-------.
I I
I I
I I
I I
IL. ______ I
~

ManufacturIng
Mask Options
Write Read Write Read

Internal Data Bus

4·174
MC6805P4

FIGURE 10 - SELF-CHECK CONNECTIONS

iNT MC6805P4 PAJ 27

PA6 26
28 RESEr PA5 25

1 0 ~f PA4 24

XTAL PA3 23

PA2 22
~
EXTAL PAl 21

27pf ~ PAO 20

-9 V 10 kll TIMER

VCC 3 Vee
PBJ 19

18
VSB PB6
17
PB5

II
PB4 16
470 [) 15
PCO PB3
470 [) 14
PCl PB2
470 [) 13
PC2 PBt
470 [) 12
PBO

VCC Pin 3 GND

VSS Pill 1 .".1
* NOTE For RC user selectable mask option, omit the crystal and the 27 pF
capacitor and connect pin 4 and 5 together with a Jumper

The source of the clock Input IS one of the mask options that RESETS
IS specified before manufacture of the MCU The MCU can be reset three ways by Initial power-up, by
A prescaler option, divided by 2 n , can be applied to the the external reset Input (RESETI, and by an optional Internal
clock Input that extends the timing Interval up to a maximum low voltage detect CirCUit, see Figure 11 The Internal CirCUit
of 128 counts before decrementing the counter This prescal- connected to the RESET pin consists of a Schmitt tngger
Ing mask option IS also specified before manufacture which senses the RESET line logiC level The Schmitt tngger
The timer continues to count past zero, failing through to proVides an Internal reset voltage If It senses a logiC 0 on the
$FF from zero and then continuing the count Thus, the RESET Pin Dunng power-up, the Schmitt tngger SWitches
counter can be read at any time by reading the Timer Data on (removes reset I when the RESET pin voltage nses to
Register (TORI This allows a program to determine the VIRES + When the RESET pin voltage falls to a logical 0 for
length of time since a timer Interrupt has occurred, and not a penod longer than one tcyc, the Schmitt tngger SWitches
disturb the counting process off to p'ovlde an Internal reset voltage The "switch off"
At Power-up or Reset, the prescaler and counter are- voltage occurs at VIRES _ A tYPical reset Schmitt tngger
Ir"tlallzed With all logical ones, the timer Interrupt request bit ,hysteresIs curve IS shown In Figure 12
(bit 71 IS cleared, and the timer Interrupt mask bit (bit 61 IS Upon power-up, a delay of tRHL IS needed before allOWing
set the RESET Input to go high ThiS time allows the Internal
clock generator to stabilize Connectmg a capacitor to the
SELF-CHECK i'iIm Input as shown In Figure 13, tYPically prOVides suffi-
The self-check capability of the MC6805P4 MCU provides cient delay See Figure 17 for the complete reset sequence
an Internal check to determine If the part IS functional Con-
nect the MCU as shown In Figure 10 and mOnitor the output INTERNAL CLOCK GENERATOR OPTIONS
of Port C bit 3 for an OSCillation of approximately 7 Hz A 9 The Internal clock generator CirCUit IS deSigned to reqUire a
volt level on the TIMER Input, Pin 7, energizes the ROM- minimum of external components A crystal, a reSistor, a
based self-check feature The self-check program exerCises Jumper Wire, or an external Signal may be used to generate a
the RAM, ROM, timer, Interrupts, and I/O ports system clock With vanous stability/cost tradeoffs A

4-175
 MC6805P4

manufacturing mask option IS required to select either the The crystal oscillator startup lime IS a function of many
crystal oscillator or the RC oscillator CirCUit The oscillator vanables crystal parameters (especially Rsl, OSCillator load
frequency IS Internally diVided by four to produce the Internal capacitance, IC parameters, ambient temperature, and
system clocks supply voltage To ensure rapid OSCillator startup, neither the
The different connection methods are shown In Figure 14 crystal characteristics nor the load capacitance should ex~
The crystal specifications are given In Figure 15 A res stor ceed recommendations
selection graph IS given In Figure 16

FIGURE 11 - POWER AND RESET TIMING

5V
VCC
OV _ _ _ _ _ _- J

RESeT
Pin
------1'"
Internal
Reset
---------~

•
FIGURE 12 - TYPICAL RESET SCHMITT
TRIGGER HYSTERESIS FIGURE 13 - POWER UP RESET DELAY CIRCUIT

Out
Of
Reset ..-1-
VCc--AVV\r--r2~-B~,
RESET

Part Of
MC6805P4
MCU
In I
Reset
08V 2V 4V

FIGURE 14 - CLOCK GENERATOR OPTIONS

XTAL XTAL

(See Notel Cl MC6805P4 MC6805P4

4 EXTAL MCU EXTAL MCU
ICrystal Mask (ReSistor Mask
CL ::::c Option I Option)

Approximately 25% Accuracy

Crystal
TYPical tCYC ~ 1 25 ~s
External Jumper

+5V
XTAL ~\AI\r---i XT AL
MC6805P4 MC6805P4
External (See Figure 16)
EXTAL MCU EXTAL MCU
Clock (Resistor Mask
Input (Crystal Mask No
Option)
Option) Connection

External Clock Approximately 10 % Accuracy

External Resistor
(Excludes Resistor Tolerance)
NOTE a
The recommended CL value with a 4 MHz crystal IS 27 pF, maXimum, including system distributed capacitance There IS an Internal
capacitance of approximately 25 pF on the XTAL Pin For crystal frequencies other than 4 MHz, the total capacitance on each pin
should be sea lied as the Inverse of the frequency ratio For example, with a 2 MHz crystal, use approximately 50 pF on EXTAL and
approximately 25 pF on XTAL The exact value depends on the Motional-Arm parameters of the crystal used

4-176
MC6805P4

FIGURE 15 - CRYSTAL MOTIONAL ARM PARAMETERS FIGURE 16 - TYPICAL FREQUENCY SELECTION FOR
AND SUGGESTED PC BOARD LAYOUT RESISTOR OSCILLATOR OPTION
50
I I
40
\ v CC ~ 5 v
r--
EXTAL~~XTAL
TA~25°C
!i'
~
~
~
30
>-
"~
4 5 u
z
UJ
:::J
aUJ 20
AT - Cut Parallel Resonance Crystal
s: i'---
I'-- ~
-
Co~ 7 pF Max
FREO~4 0 MHz@ CL ~24 pF 10
RS ~ 50 ohms Max

0
o 10 15 20 25 30 35 40 45 50 55 60
lal RESISTANCE Ik OHMS I
INTERRUPTS
The MC6805P2 MCU can be Interrupted three different
ways through the external Interrupt IINTI Input pin, the
Internal timer Interrupt request, or the software Interrupt in-
struction (SWII When any Interrupt occurs, processing IS
suspended, the present CPU state IS pushed onto the stack,
the Interrupt bit III In the condition code register IS set, the
address of the Interrupt routine IS obtained from the
I
appropriate Interrupt vector address, and the Interrupt
routine IS executed Stacking the CPU register, setting the
I-bit, and vector fetching requlles a total of 11 tcyc periods
for completion
A flowchart of the Interrupt sequence IS shown In Figure
17 The Interrupt service routine must end with a return from
Interrupt (RTII Instruction which allows the MCU to resume
processing of the program prior to the Interrupt (by unstack-
Ing the prevIous CPU statel Table 1 provides a listing of the
Interrupts, thell PriOrity, and the address of the vector which
Ibl contains the starting address of the appropriate Interrupt ser-
vice roullne The Interrupt PriOrtly applies to those pending
when the CPU IS ready to accept a new Interrupt RESET IS
listed In Table 1 because It IS treated as an Interrupt
However, It IS not normally used as an Interrupt When the
Interrupt mask bit In the Condition Code Register IS set the
Interrupt IS latched for later Interrupt execution
The external Interrupt IS Internally synchronized and then
latched on the failing edge of INT A SinUSOidal Input Signal
(fINT maxlmuml can be used to generate an external Inter-
rupt, as shown In Figure 18a, for use as a Zero Crossing
Detector For digital applications the INT can be driven by a
digital Signal at a maximum period of tlWL ThiS allows ap-
plications such as servIcing tlme-of-day routines and engag-
Ing/ disengaging AC power control deVices Off-chip full
wave rectification provides an Interrupt at every zero cross-
Ing of the AC Signal and thereby prOVides a 2f clock
A software Interrupt (SWt) IS an executable instruction
which IS executed regardless of the state of the I-bit In the
Note. Keep crystal leads and Circuit
Condition Code Register SWI's are usually used as break-
connections as short as possible
POints for debugging or as system calls

4-177
MC6805P4

FIGURE 17 - RESET AND INTERRUPT PROCESSING FLOWCHART

..-----iN

FIGURE 18 - TYPICAL INTERRUPT CIRCUITS

a ~ Zero Crossing Interrupt b - Digital Signal Interrupt

Vcc
AC TTl 47k
Input {Current
If M ) Limiting)
2m MC6805P4 Level iNT MC6805P4
1~~1 ~~ ~~-g""-""----101 Dlgltal---4....~
MCU MCU
Input
AC Input::2! pF
ItlWL Maximum
10 Vpp
Period)

lJ

4-178
MC6805P4

TABLE 1 - INTERRUPT PRIORITIES grammed for outputs, It IS capable of Sinking 10 mA and

sourcing almA on each pin
Interrupt Priority Vector Address All Input/output Imes are TTL compatible as both Inputs
R!rn 1 $7FE and $7FF and outputs Ports Band C are CMOS compatible as Inputs
SWI 2* $7FC and $7FD Port A may be made CMOS compatible as outputs With a
INT 3 $7FA and $7FB mask option The address map In Figure 6 gives the address
Timer 4 $7FB and $7F9 of data registers and DDRs The register configuration IS pro-
Vided m Figure 20 and Figure 21 proVides some examples of
"'Priority 2 applies when the I-bit In the ConditIOn Code Register IS
port connections.
set When I = 0, SWI has a Priority 014, like any other Instruction,
the priority of INT thus becomes 2 and the timer becomes 3

Caution: The corresponding DDRs for ports A, B, and C

are wnte-only registers (registers at $004, $005, and $(06) A
INPUT/OUTPUT
There are 20 Input/ output pinS The iNT pin may also be read operation on these registers IS undefined Since BSET
pulled With branch instructions to provide an additional Input and BCLR are read/modify/write lunctlons, they cannot be
pin. All pinS (Port A, B, and C) are programmable as either used to set or clear a DDR bit lall"unaffected" bits would be
Inputs or outputs under software control of the corres- setl It IS recommended that all DDR bits In a port be written
ponding Data Direction Register (DDR) The port I/O usmg a Single store instruction
programming IS accomplished by wntlng the corresponding The latched output data bit Isee Figure 191 may always be
bit In the port DDR to a logic "1" for output or a logic "a" for written Therefore, any wnte to a port wntes all of ItS data
Input On Reset, all the DDRs are Initialized to a logic "a" bits even though the port DDR IS set to Input ThiS may be

•
state to put the ports In the Input mode The port output used to Initialize the data registers and aVOid undefined out-
registers are not initialized on Reset but may be wntten to puts, however, care must be exerCised when uSing
before setting the DDR bits to avoid undefined levels When read/modlfy/wnte instructions smce the data read cor-
programmed as outputs, the latched output data IS readable responds to the pin level of the DDR IS an Input (01 and cor-
as Input data, regardless of the logic levels at the output pin responds to the latched output data when the DDR IS an out-
due to output loading, see Figure 19 When Port B IS pro- put (11

FIGURE 19 - TYPICAL PORT I/O CIRCUITRY

Data
Direction Register
81t*

co "'cQ Latched
Output
c<;; "w
Data
E §
o Bit
U

Data
Direction Output Input
Register Data Output To
Bit Bit State MCU
I
I ,
a
,
a a
,
a x 3-State** Pin

.OOR IS a Write-only register and reads as all 1'5

.*Ports A (With CMOS drive disabled), S, and C are three-state ports Port A has optlonalmternal pullup deVices
to proVide CMOS drive capability See Electncal Characteristics tables for complete Information

4-179
 MC6805P4

FIGURE 20 - MCU REGISTER CONFIGURATION

PORT DATA REGISTER PORT DATA DIRECTION REGISTER IDDRI

o

Port A Addr = $000 111 Wllte Only, reads as alil's

Port B Addr= $001 121 1 = Output, 0= Input Cleared to 0 by Reset
Port C Addr= $002 IB,ts 0-31 131 Port A Addr = $004
Port B Addr = $005
Port C Addr = $006 I Bits 0-31

TIMER CONTROL REGISTER ITCRI TIMER DATA REGISTER ITORI

432 o o
~~~I_l-Ll_l~l_l~l_l~l~l~~I$~ MSB LSB 1$008
TCR7 - Timer Interrupt Status Request Bit Set when
TOR goes to zero, must be cleared by software
Cleared to 0 by Reset
TCR6 Bit 6- Timer Interrupt Mask Bit 1 = timer Inter-

•
rupt masked (disabled) Set to 1 by Reset
TCR Bits 5, 4, 3, 2, 1, 0 read 1's- unused bits

FIGURE 21 - TYPICAL PORT CONNECTIONS

a. Output Modes

PA7 27 ICMOS Loadsl

PA6 26 PB7 19

-
PA5 25 PB6 18

PA4 24 11 TTL Loadl PB5 17

-Ib
PA3 23 PB4 16
16mA 10mA
PA2 22 Pfi~ 15 2N6386 11 YPlcali
PAl 21 PB2 14

PAD 20 PBl 13
PBO 12

Port A, Bit 7 Programmed as Output, DriVing

CMOS Loads and Bit 4 DIIVllig one TTL Load Port B, Bit 5 Programmed as Output, DriVing
Directly I USlll9 CMOS output optlonl Darlington-Base Directly
+V
+v

PC3 11 CMOS
PC2 10 Inverters
MC14049/MCl4069
PCl 9 ITYPlcali
PCO 8

Port C, Bits 0, 3 Programmed as Output, Dllv-

Ing CMOS Loads, USing External Pullup
ReSistors

4-180
MC6805P4

FIGURE 21 - TYPICAL PORT CONNECTIONS (CONTINUED)

b. Input Modes

PA7 PB7
PA6 PB6

MC74LS04
. 25
24
PA5
PA4
MC74LS04
or
17
16
PB5
PB4
(TYPlcali MCl4069
23 PA3 15 PB3
(TYPlcall
22 PA2 PB2
PAl PB1
PAO PBO

TTL Driving Port A Directly CMOS or TTL DriVing Port B Directly

•
PC3
PC2
PC1
PCO

CMOS and TTL DriVing Port C Directly

BIT MANIPULATION
The MC6805P4 MCU has the abilltity to set or clear any have ,nd,v,dual flags In RAM or to handle I/O bits as control
single random access memory or input/ output bit (except lines
the Data Dlrecllon Register, see Caution under INPUT /OUT- The coding example In Figure 22 Illustrates the usefulness
PUT paragraph), with a single instruction (BSET, BClR) of the bit manipulation and test Instrucllons Assume that
Any bit In page zero including ROM, except the DDRs, can the MCU IS to communicate with an external senal deVice
be tested, uSing the BRSET and BRClR Instrucllons, and The external deVice has a data ready signal, a data output
the program branches as a result of Its state. The Carry bit line, and clock line to clock data one bit at a time, lBS first,
equals the value of the bit referenced by BRSET or BRClR out of the deVice The MCU walts until the data IS ready.
A Rotate Instruction may then be used to accumulate senal clocks the external deVice, picks up the data In the Carry Flag
Input data In a RAM location or register The capability to (C-bltl, clears the clock line, and finally accumulates the data
work with any bit In RAM, ROM, or I/O allows the user to bit In a RAM location

FIGUR€ 22 - BIT MANIPULATION EXAMPLE

MCU SELF BRSET 2, PORTA, SELF

Ready r-
2 P
Senal
DeVice Clock a
1 R
T
BSET 1- PORTA
Data BRCLR 0, PORTA, CONT
OA
r- CONT BCLR 1, PORTA
ASR RAMLOC

4·181
 MC6805P4

ADDRESSING MODES INDEXED, 16-BIT OFFSET - In the Indexed, 16-blt offset

The MC6805P4 MCU has 10 addressing modes which are addreSSing mode, the effective address IS the sum of the
explained briefly In the following paragraphs For additional contents of the unSigned 8-blt Index register and the two un-
details and graphical Illustrations, refer to the M6805 Family signed bytes follOWing the opcode ThiS addreSSing mode
User's Manual can be used In a manner Similar to Indexed, 8-blt offset, ex-
The term "effective address" lEAl IS used In describing the cept that thiS 3-byte instruction allows tables to be anywhere
address modes EA IS defined as the address from which the In memory
argulTlent for an Instruction IS fectched or stored
BIT SET/CLEAR - In the bit set/clear addreSSing mode,
IMMEDIATE - In the Immediate addreSSing mode, the the bit to be set or cleared IS part of the cpcode, and the
operand IS contained In the byte Immediately following the byte follOWing the opcode speCifies the address of the byte
opcode The Immediate addreSSing mode IS used to access In which the speCified bit IS to be set direct or cleared Thus,
constants which do not change during program execution any read/write bit In the first 256 locations of memory, in-
Ie 9 , a constant used to initialize a loop counterl cluding I/O, can be selectively set or cleared With a Single
2-byte InstrucllOn See CaullOn under the INPUT/OUTPUT
DIRECT - In the direct addreSSing mode, the effective paragraph
address of the argument IS contained In a Single byte follow-
Ing the opcode byte Direct addreSSing allows the user to BIT TEST AND BRANCH - The bit test and branch ad-
directly address the lowest 256 bytes In memory with a Single dreSSing mode IS a combination of direct addreSSing and
2-byte instruction ThiS Includes the on-chip RAM and I/O relative addreSSing The bit and condition Iset or clearl which
registers and 128 bytes of ROM Direct addreSSing IS an ef- IS to be tested IS Included In the opcode, and the address of
fective use of both memory and time the byte to be tested IS In the Single byte Immediately follow-

•
Ing the opcode byte The Signed relative 8-blt offset IS In the
EXTENDED - I n the extended addreSSing mode, the ef- third byte and IS added to the value of the PC If the branch
fective address of the argument IS contained In the two bytes condlllOn IS true ThiS Single 3-byte Instruction allows the
follOWing the opcode Instructions uSing extended address- program to branch based on the condition of any readable
Ing are capable of referenCing arguments anywhere In bit In the first 256 locations of memory The span of
memory with a single 3-byte Instruction When uSing the branching IS from + 130 to -125 from the opcodeaddress
Motorola assembler, the programmer need not specify The state of the tested bit IS also transfered to the Carry bit
whether an Instruction uses direct or extended addreSSing of the Condition Code Register See Caution under the
The assembler automatically selects the shortest form of the INPUT /OUTPUT paragraph
instruction
INHERENT - In the Inherent addreSSing mode, all the in-
RELATIVE - The relative addreSSing mode IS only used In formation necessary to execute the instruction IS contained
branch Instructions In relative addreSSing, the contents of In the opcode Operations speCifYing only the Index register
the 8-bIt signed byte follOWing the opcode Ithe offsetlls add- or accumulator, as well as controllnstrucllOn With no other
ed to the PC If and only If the branch conditIOn IS true Other- arguments, are Included In thiS mode These InstrucllOns are
Wise, control proceeds te the next instruction rhe span of one byte long
relative addreSSing IS from -126 to + 129 from the opcode
address. The programmer need not worry about calculating INSTRUCTION SET
the correct offset when uSing the Motorola assembler, since The MC6805P4 MCU has a set of 59 baSIC InstrucliOns,
It calculates the proper offset and checks to see If It IS within which when combined With the 10 addreSSing modes pro-
the span of the branch duce 207 usable opcodes. They can be diVided Into five dif-
ferent types. register/memory, read/modifY/Write, branch,
INDEXED, NO OFFSET - In the Indexed, no offset ad- bit manipulation, and control. The follOWing paragraphs
dreSSing mode, the effective address of the argument IS con- briefly explain each type. All the instructions Within a given
tained In the 8-bIt Index register Thus, thiS addreSSing mode type are presented In indiVidual tables
can access the first 256 memory locations These instruc-
tions are only one byte long ThiS mode IS often used to REGISTER/MEMORY INSTRUCTIONS - Most of these
move a pOinter through a table or to hold the address of a instructions use two operands One operand IS either the ac-
frequently referenced RAM or I/O location cumulator or the Index register The other operand IS obtain-
ed from memory uSing one of the addreSSing modes The
INDEXED, 8-BIT OFFSET - In the Indexed, 8-blt offset Jump uncondltlonallJMP) and Jump to subroutine IJSRIIn-
addreSSing mode, the effective address IS the sum of the structlons have no register operands Refer to Table 2
contents of the unSigned 8-blt Index register and the unsign-
ed byte follOWing the opcode ThiS addreSSing mode IS READ/MODIFY/WRITE INSTRUCTIONS - These In-
useful In selecting the kth element In an n element table structions read a memory location or a register, modify or
With thiS 2-byte InstrucliOn, k would tYPically be In X with test ItS contents, and write the modified value back to
the address of the beginning of the table In the instruction. memory or to the register Isee Caution under INPUT /OUT-
As such tables may begin anywhere within the first 256 ad- PUT paragraphl The test for negative or zero (TSTI Instruc-
dressable locations and could extend as far as location 511 tion IS Included In read/modifY/Write instructions though It
1$1FE) does not perform the write Refer to Table 3

4-182
MC6805P4

BRANCH INSTRUCTIONS - The branch instructions CONTROL INSTRUCTIONS - The control instructions
cause a branch from the program when a certain condition IS control the MCU operations dUring program execution
met Refer to Table 4 Refer to Table 6

BIT MANIPULATION INSTRUCTIONS - These Instruc- ALPHABETICAL LISTING - The complete Instruction set
tions are used on any bit In the first 256 bytes of the memory IS given In alphabetical order In Table 7
(see Caution under INPUT/OUTPUT paragraph) One group
either sets or clears The other group performs the bit test OPCODE MAP SUMMARY - Table 8 IS an opcode map
branch operations Refer to Table 5 for the instructions used on the MCU

4·183
 •
TABLE 2 - REGISTER/MEMORY INSTRUCTIONS
s:
~~
AddresslOq Modes
Indexed Indexed Indexed
Immediate Direct Extended (No Offset) f8 a,t Offset) (16 Bit Offset)

Function
Op # # Op # Op
MnemOnic Code Bytes Cycles Code Bvtes Cycles Code Bytes Cycles
• • • Op •
Code Bytes Cycles
• Op • OP •
Code Bytes Cycles Code Bytes Cycles
• •
Load A from Memory LDA A6 2 2 B6 2 4 (6 3 5 F6 1 4 ,6 2 5 D6 1 6
Load X from Memory LDX AE 2 2 BE 2 4 Cf 3 5 FE 1 4 EO 2 5 Df 3 6
Store A In Memory STA B7 2 5 C7 3 6 F7 1 5 EO 2 6 D7 3 7
Store X In Memory STX BF 2 5 CF 3 6 FF 1 5 EF 2 6 DF 3 7
Add Memory to A ADD AB 2 2 BB 2 4 CB 3 5 FB 1 4 EB 2 5 DB 3 6
Add Memory and
Carry to A ADC A9 2 2 B9 2 4 C9 3 5 f9 1 4 ,9 2 5 D9 3 6
Subtract Memory SUB AO 2 2 BO 2 4 CO 3 5 Fa 1 4 EO 2 5 DO 3 6
Subtract Memory from
A with Borrow SBC A2 2 2 B2 2 4 C2 3 5 F2 1 4 E2 2 5 02 3 6
AND Memory to A AND A4 2 2 B4 2 4 C4 3 5 F4 1 4 f4 2 5 04 3 6
OR Memory With A ORA AA 2 2 BA 2 4 CA 3 5 FA 1 4 EA 2 5 DA 3 6
ExcluSIve OR Memory
with A EaR A8 2 2 B8 2 4 C8 3 5 F8 1 4 E8 2 5 08 3 6
ArithmetIC Compare A
With Memory CMP A1 2 2 B1 2 4 C1 3 5 F1 1 4 El 2 5 D1 3 6
Aflthmetlc Compare X
With Memory CPX A3 2 2 83 2 4 C3 3 5 F3 1 4 E3 2 5 03 3 6
f"
...... a,tTest Memory With
1
A (logical Compare) 81T A5 2 2 B5 2 4 C5 3 5 F5 4 E5 2 5 D5 3 6
CD JMP FC 1 3 EC 2
-I:>- Jump UnconditIOnal 8C 2 3 CC 3 4 4 DC 3 5
Jump to Subroutine JSR BO 2 7 CO 3 8 FD 1 7 ED 2 8 DD 3 9

TABLE 3 - READ/MODIFY/WRITE INSTRUCTIONS

Addressing Modes
Indexed Indexed
Inherent (A) Inherent (X) Direct (No Offset) (8 Bit Offset}

Function
Op # #
Mnemonic Code Bytes Cycles
Op # # Op #
Code Bytes Cycles Code Bytes Cycles
• Op
•
Code Bytes Cycles
• Op #
Code Bytes Cycles
•
increment INC 4C 1 4 5C 1 4 3C 2 6 7C 1 6 6C 2 7
Decrement DEC 4A 1 4 5A 1 4 3A 2 6 7A 1 6 6A 2 7
Clear CLR 4F 1 4 5F 1 4 3F 2 6 7F 1 6 6F 2 7
Complement COM 43 1 4 53 1 4 33 2 6 73 1 6 63 2 7
Negate
r---
(2 5 Complement} NEG 40 1 4 50 1 4 30 2 6 70 1 6 60 2 7
Rotate Left Thru Carry ROL 49 1 4 59 1 4 39 _ 2 6 79 1 6 69 2 7
Rotate Right Thru Carry ROR 46 1 4 56 1 4 36 2 6 76 1 6 66 2 7 I
Logical ShIft Left LSL 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7
Logical Shift Right LSR 44 1 4 54 1 4 34 2 6 74 1 6 64 2 7
Arithmetic Shift Right ASR 47 1 4 57 1 4 37 2 6 77 1 6 67 2 7
Test for Negative
or Zero TST 4D 1 4 5D 1 4 3D 2 6 7D 1 6 6D 2 7
--- - - -
MC6805P4

TABLE 4 - BRANCH INSTRUCTIONS

Relative Addressing Mode

Op # #
Function Mnemonic Code Bytes Cycles
Branch Always BRA 20 2 4
Branch Never BRN 21 2 4
Branch IFFHlgher BHI 22 2 4
BranchlFFLower or Same BlS 23 2 4
Branch IFFCarry Clear BCC 24 2 4
IBranchlFFHlgher or Same) IBHS) 24 2 4
Branch IFF Carry Set BCS 25 2 4
IBranchlFFlower) IBlOI 25 2 4
Branch IFF Not Equal BNE 26 2 4
Branch IFF Equal BEQ 27 2 4
Branch Half Carry Clear BHCC 28 2 4
Branch IFF Half Carry Set BHCS 29 2 4
Branch IFF Plus BPl 2A 2 4
BranchlFF Minus BMI 2B 2 4

•
Branch IFF Interupt Mask
Bit IS CI~ar BMC 2C 2 4
Branch IFF Interrupt Mask
Bit IS Set BMS 2D 2 4
Branch IFF Interrupt Line
IS Low Bil 2E 2 4
Branch IfF Interrupt Line
IS High BIH 2F 2 4
Branch to Subroutine BSR AD 2 8

TABLE 5 - BIT MANIPULATION INSTRUCTIONS

Addressmg Modes
Bit Set/Clear Bit Test and Branch
Op # # Op # I ~

Function Mnemonic Code Bytes Cycles Code Bytes Cycles

Branch IFF Bit n IS set BRSET n In = 0 71 - - - 2.n 3 10
Branch IFF Bit n IS clear BRClR n In - 0 71 - - - 01 ~ 2. n 3 10
Set Bit n BSET n In = 0 71 10+2en 2 7 - - -
Clear bit n BClR n In = 0 71 11 + 2. n 2 7 - - -

TABLE 6 - CONTROL INSTRUCTIONS

Inherent
Op # #
Function Mnemonic Code Bytes Cycles
Transfer A to X TAX 97 1 2
Transfer X to A TXA 9F 1 2
Set Carry Bit SEC 99 1 2
Clear Carry Bit ClC 98 1 2
Set Interrupt Mask Bit SEI 9B 1 2
Clear Interrupt Mask Bit CLI 9A 1 2
Software Interrupt SWI 83 1 11
Return from Subroutine RTS 81 1 6
Return from Interrupt RT! 80 1 9
Reset Stack POinter RSP 9C 1 2
No-Operation NOP 9D 1 2

4-185
 MC6805P4

TABLE 7 - INSTRUCTION SET

Addressing Modes Condition Code

Bit Bit
Indexed Indexed Indexed Setl Test &
MnemoOic Inherent Immediate Direct Extended Relative (1110 Offset) (8 Bits) (16 Bots) Clear Branch H I N Z C
ADC X X X X X X /\
• /\ /\ /\
ADD X X X X X X /\
• /\ /\ /\
AND X X X X X X
•• /\ /\
•
ASl X X X X
•• /\ /\ /\
ASR X X X X
•• /\ /\ /\
BCC X
•••• •
BClR X
•••• •
BCS X
•••• •
BEQ X
•••• •
BHCC X
"••• •
BHCS X
•••• •
BHI X
•••• •
BHS X
•••• •
BIH X
•••• •
Bil X
•••• •

•
BIT X X X X X X
•• /\ /\
•
BlO X
•••• •
BlS X
•••• •
BMC X
•••• •
BMI
•••• •
BMS
•••• •
BNE
•••• •
BPl
•••• •
BRA
•••• •
BRN
•••• •
BRClR X
•••• /\
BRSET X
•••• /\
BSET X
•••• •
BSR X
•••• •0
Cll X
••••
CLI X
• 0 0• • •
ClR X X X X
•• 1
•
CMP X X X X X X
•• /\ /\ /\
COM X X X X
•• /\ /\ 1
CPX X X X X X X
•• /\ /\ /\
DEC X X X X
•• /\ /\
•
EOR X X X X X X
•• /\ /\
•
INC X X X X
•• /\ /\
•
JMP X X X X X
•••• •
JSR X X X X X
•••• •
lDA X X X X X X
•• /\ /\
•
lDX X X X X X X
•• /\ /\
•
lSl X X X X
•• /\ /\ /\
lSR X X X X
••0 /\ /\
NEO X X X X
•• /\ /\ /\
NOP X
•••• •
ORA X X X X X X
•• /\ /\
•
ROl X X X X
•• /\ /\ /\
RSP X
•••• •
Condition Code Symbols
H Half Carry (From Bit 31 C Carry/Borrow
Interrupt Mask A Test and Set If T rue, Cleared OtherwIse
N Negative (Sign Bigi • Not Affected
Z Zero

4-186
MC6805P4

TABLE 7 - INSTRUCTION SET ICONTINUED)

Addressing Modes Condition Code

BitBit
Indexed Indexed Indexed Set! Test &

, , N, Z, C,
Mnemonic Inherent Immediate Direct Extended Relative INo Offsetl IB Bltsl 116 Bltsl Clear Branch H I
RTI X
RTS X
•• • • •
SBC X X X X X X
••"" "
SEC X
•••• 1
SEI X
• ••1
•
STA X X X X X
••"" •
STX X X X X X
• • " "t, •
SUB X X X X X X
••"
SWI X
• ••1
•"
TAX X
•• • • •
TST X X X X
••"" •
TXA X
•••• •

•
Condition Code Symbols
H Half Carry I From Bit 3) C Carry/Borrow
I Interrupt Mask /I Test and Set If True, Cleared Otherwise
N Negative I Sign Bigi • Not Affected
Z Zero 7 Load CC Register From Stack

4-187
 • s:
~
TABLE B - M6805 FAMILY OPCODE MAP

,
. .
Bk MIIllpulotion Brlnch Road/Modlfv/Wnte Control Reaester/Memory
I HX IX 1NIf 1NIf IMM DR E I JX I
~i .:., .J"
4
~.
3 6
.l.,
5 4
.~
3 4
,~,
3 7
.~
6 6
.["
5 9
,:" ,£,
2
,tt. 2 4 3
,!" 4
foo ,g, 11~0 ·,it, H~
~
'~RSETO' 12 BSE~~c
7
NEGA NEG X NEG NEG ATI " SUB SUB SUB I ' SUB 4 I' SUB 3
k -JiiiL 12 BA-";,EL NEGm• , I I INH IXI I IX I INH 1M
, SUB
OIR 3 EXT I IX ril.,
,
3 IX2 12 IXl
,0 ,~. 4 , 6 6 2 2 4 3 5 4 6 5 5 4 4 1 1
J,
7 .'
BRCLr,'l, 12 BCL~~r I, BANR" I
ATS
INH
CMP
IMM 2
CMP
01.3
CMP
EXT 3
CMP
IX2 , CMP
IXI I
CMP
0001
"
.t.Q -.i. ,BSE~l;
T~ASET1· I I,
4

4
BHI."
3

3 6 5 4 3 4 3 7 6 6 5 11 10
2

2
SBC
2 4
IMM 2
,
4
SBC
3
OIR
, SBC
3
4

,XT 3
4
SBC
5
IX2
5
2
SBC
4
IXI I
SBC
IX
2
0010
1'~RCL~i: 1 7,BCL~lc " 5 CPX 6 CPX 5 5 CPX 4 4 CPX 3
COMOIR COM~H I COM~H I, COMIXI I COM IX SWI CPX CPX
J" "
5 4
BLSREL
3 6 5 4 3 4 3 7 6 6 5
I INH 2
2
IMM 2
2 4
01.
3
3 'XT 3
4
IX2 2 IXI ,
4
IX
3
0011

o:to I'SRSET2'
-Bfa I, BSE1~c ,2 BCCREL I, LSAOIR ,
LSAA
INH , LSAX 12 LSA
INH IX'
LSA
IX , ,
2
AND
IMM 2
AND
01.
, AND
3 XT 3
AND'
IX2 .2
5 AND 4
, AND 01~
1'~RCLR2·
5 4 3 • 2 , BIT 3 5 4 6 5 ' ,
IXI
4 4 "3
o~, -BTB 12 BCL~~c
BCSREL
,
BIT
1M ,
, DIA
, BIT
'XT
BIT IX? , BIT 'XI , BIT IX 11~1
5 6 5 4 3 4 3 7 6 6 5 4 35 4 6 5 5 4 4 3
1'~ASEJJ: 4 BNE '
, LOA o~o
LOA LOA
n~n I, BS~~c , AOA~H "
AOAA LOA LOA , LOA
-."
I, ADAm.
6 5 4
I
3 4 3 7
ADA X,
6
, ROA IX
6 5 , , IMM 2
5
OIR
4
3 EXT 3 IXl IXI >X

o,~, 'SRCL~J: BCL~~: BEaR'~ ASA~H ASAX ASA

, ASA
, TAXINH, , STA • STA 5 STA • 6 STA ' , STA 4 7
,
1 I, ASR IR
I, 1 INH i 2 IX1 IX 2 DIR 3 XT >X, • 2 IXI , IX alII
4 3 4 3 7 6 6 5 2 4 3 5 4 6 5 5 4 4 3
BHC~,~
.5 6
,:., 1 'SRSEJ:: 12 BS~~c I, LSL lIR , LSLAN LSL~NH " LSL , LSL
IX
, ,,CLS NH EOA
I M
, EOA
OIR
3 EOA
EXT 3 EOA>x,
" EOA
IX' , EOA
IX
8
1000

..
4 3 6 5 4 3 4 3 7 " 6 6 2 4 4 6 4 4 3
'~RCLA4'
5 3 5 5 5
,£, -BT8
7 .'
I, BCL~~c , BHC~EL I, AOLOIA AOL~H , AOLX :, AOL
INH IX' , ROL
IX , SECINH, ADC
IMM 2
ADC
OIR 3
ADC
EXT 3
ADC
IX'
ADC
IX' , ,ADC
IX
9
'00'
~
..
4 3 6 5 4 3 4 3 7 6 6 5 4
......' ,tto I'SRSrn5
-BTB I, BSE~c , BPLREL I, DECOlA , DEC~H
4 3
, DECX
INH ,
DEC
IX' , DEC
IX , CLI
INH , OAA
IMM ,
OAA ' , OAA
OIR 3 'XT 3
OAA 5
IX'
OAA
>X,
4
, , OAA ox
4
A
101(.

I" ,!" '~RCLR5'

-BTB 12 BCL~~c 2 BM~EL
,, ,
SEI '
INH
ADD
IMM 2
4 ADD 3 5 ADD 4 • ADD 5
OIR 3 EXT 3 IXl
ADD
IXI , , ADD >X
B
1011
I. 5 4 3 4 3 7 6 6 5
1T~RSEJ~: BSE1~; BM~<~ 3 JMP , 4 JMP , JMP 4 14 JMP ,
,lin I, 4 I, INC lIR , INC~"H 1
INCX
INH
, INC
IX'
INC
IX , ,, INH,
ASP
, OIR 3 ExT 3 IX2 2 IXI ,
JMP
IX
C
1100
4 3 4 6 4 8 6 7
,g, 'SRCLRS'
-.To I, BCL~~:
4 BMS ' I"
IIFI I, TSTmR TST~NH
TSTX' 7 1ST •
·INH'
TST
IXI , IX , NOPINH , BSA
REL 2
JSA ' • JSA
OIR 3
• JSA
EXT 3 IX'
JSA b
IXI , , JSA IX
0
1101
'0,' 7 5 4 3 , LOX • , LOX 4
11~0 BRSEJIB 12 BSEVsc BILREL
6 4 3 4 3 7 6 6
, STOP
INH
,
LOX
IMM ,
OIR 3
• LOX
EXT 3 >X,
LOX
IXI , LOX
IX
E
l11C

, '~ACLA76
F
1111 3 BTO , BCLA,' 4 BIH 3
BSC 2 - REL 2
CLR
OIA ,
CLAA
INH , CLAX
~-I:! '-,
CLR
~X}
, CLA IX• , WAITINH , TXAINH ,
, STX 4
• STX
OIR 3 EXT 3
STX •
1 6 STX '
IXI
IX' , , STX
IX
F
1111

LEGEND
AbbcevIationI for AddNM Modea

INH Inherent r-iF:4==l--------:7

F oC Opcode in Hexadecllnal

j
;>'
IMM Immed,ate
DIR
EXT
Direct
Extended # of Cycles (HMOS Versions! 4 "'~ ~ Opcode In Binary
REL Relative MnemonIC .. SUB 0
BSC Bit Set! Clear Bytes 1 IX 0000
J
BTB Bit Teat and Branch
IX Indexed INo Offsetl # of Cycles (CMOS Verslonsl------~ " Address Mode
IXl Indexed, 1 Byte (8-Blt) Offset
1X2 Indexed, 2 Byte (18-Blt) Offset
CMOS Venoions Onlv
MC6805P4

ORDERING INFORMATION

The Information required when ordenng a custom MCU IS signed, and returned to Motorola. The signed venficatlon
listed below. The ROM program may be transmitted to form constitutes the contractual agreement for creation of
Motorola on EPROM(s) or a MDOS disk file. the customer mask If desired, Motorola will program on
To Inillate a ROM pattern for the MCU It IS necessary to blank EPROM from the data file used to create the custom
first contact your local Motorola representative or Motorola mask and aid In the venflcallon process.
dlstnbutor
ROM VERIFICATION UNITS (RVUs)
EPROMs - The MCM2716 or MCM2532 type EPROMs, pro- Ten MCUs containing the customer's ROM pattern will be
grammed with the customer program (positive logic sense sent for program venflcatlon. These Units will have been
for address and data), may be submitted for pattern genera- made uSing the custom mask but are for the purpose of
tion The EPROM must be clearly marked to Indicate which ROM venflcatlon only For expediency they are usually un-
EPROM corresponds to which address space. The recom- marked, packaged In ceramiC, and tested only at room
mended marking procedure IS Illustrated below temperature and 5 volts These RVUs are Included In the
mask charge and are not production parts The RVUs are
thus not guaranteed by Motorola Quality Assurance,and
xxx xxx should be discarded after venflcatlon IS completed

FLEXIBLE DISKS

•
The disk media submitted must be Single-sided, slngle-
denSity, 8-lnch, MDOS compatible flOPPies. The customer
must wnte the binary file name and company name on the
disk With a felt-tip pen The minimum MDOS system files as
000 400 well as the absolute binary object file (filename LO type of
file) from the M6805 cross assembler must be on the disk. An
xxx = Customer ID object file made from a memory dump uSing the ROLLOUT
After the EPROM(s) are marked they should be placed In command IS also acceptable. Consider submitting a source
conductive IC carners and securely packed. Do not use listing as well as the follOWing files filename, LX (EXOR-
styrofoam ciser" loadable format) and filename, SA (ASCII Source
Code) These files Will of course be kept confidential and are
VERIFICATION MEDIA used 1) to speed up the process In-house If any problems
All onglnal pattern media (EPROMs or Floppy Disk) are fil- anse, and 2) to speed up the user-to-factor Interface If the
ed for contractual purposes and are not returned A com- user finds any software errors and needs assistance qUickly
puter listing of the ROM code will be generated and returned from Motorola factory representatives.
along with a listing venflcatlon form The listing should be M DOS IS Motorola's Disk Operating system available on
thoroughly checked and the venflcatlon form completed, development systems such as EXORCisers, EXORsets, etc

4·189
 MC6805P4

MC6806P4 MCU ORDERING INFORMATION

Date _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Customer PO Number _ _ _ _ _ _ _ _ _ __

Customer Company _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Motorola Part Numbers

Address MC _ _ _ _ _ __
-----------------------------SC
Clty _ _ _ _ _--'_ _ _ _ _ _ _ _ _ _ State _ _ _ _ _ _ _ _ _ _ _ _ _ Zlp _ _ _ _ __ ------
Count~ __________________________________________

Phone ____________________ Extension _____________________________

CustomerCon~ctPemon ______________________________________

Customer Part Number _____________________________________

OPTION LIST
Select the options for your MCU from the followmg list A
manufacturing mask Will be generated from this mformatlon

•
Timer Clock Source
o Internal <1>2 clock
o TIMER Input pm

Timer Prescaler
o 2" (divide by 1) o 24 (divide by 16)
o 2' (diVide by 2) o 2' (divide by 32)
o 22 (divide by 4) o 2" (divide by 64)
o 2' (diVide by 8) o 2' (divide by 128)

Internal OSCillator Input Port A Output Drive

o Crystal o CMOS and TTL
o Resistor o TTL Only

Low Voltage Inhibit Standby RAM

oDisable o 16 Bytes
oEnable o 64 Bytes
o 112 Bytes

Pattern ,Media (All other m~la reqUires prIOr factory approval)

o EPROMs (MCM2716 or MCM2532 o Floppy Disk
o Other

Clock Freq, ________________

Temp, Range _________________ 0 O· to + 70·C IStandard)

*ReqUires pnor facto~ approval

Marking Information (12 Charactem MaXimum)

Tltle _______________________________________________

S,gnature _______________________________________________

4-190
!
® MOTOROLA MC680SR2

Advance InforIDation HMOS

(HIGH DENSITY
a-BIT MICROCOMPUTER UNIT WITH AID N-CHANNEL, SILICON-GATE
DEPLETION LOAD)
The MC6805R2 Microcomputer Unit IMCUI IS a member of the M6805
Family of low-cost single-chip Microcomputers The B-blt microcomputer
8-BIT
contains a CPU, on-chip CLOCK, ROM, RAM, I/O, 4-channeI8-blt A/D,
and TIMER It IS designed for the user who needs an economical MICROCOMPUTER
microcomputer with the proven capabilities of the M6800-based Instruction WITH AID
set A companson of the key features of several members of the M6805
Family of microcomputers IS shown on the last page of thiS data sheet The
following are some of the hardware and software highlights of the
MC6805R2 MCU
HARDWARE FEATURES:
• 8-81t Architecture
• 64 8ytes of RAM
• Memory Mapped I/O

~PSUFFIX
• 2048 8ytes of User ROM
• 24 TTL/CMOS Compatible 81dlrectlOnaii/0 Lines 18 lines are LED
Compatlblel

•
• 2 to 5 Digital Input Lines ~!;rrt I'·· PLASTIC PACKAGE
• A/D Converter . CASE 711
8-81t Conversion, Monotonic

~SSUFFIX
1 to 4 Multiplexed Analog Inputs
± 1/2 LS8 Quantizing Error
± 1/2 LS8 All Other Errors ~1{ [[l L I " • CERDIP PACKAGE
± 1 LSB Total Error Imaxl
Ratlometnc Conversion CASE 734
• Zero-Crossing Detection
• On-Chip Clock Generator
FIGURE 1 - PIN ASSIGNMENTS
• Self-Check Mode
• Master Reset
• Complete Development System Support On EXORCiser" PA7
• 5 V Single Supply
PA6
SOFTWARE FEATURES: PA5
Similar to M6800 Family
PA4
Byte EffiCient Instruction Set
Easy to Program PA3
T rue Bit Manipulation PA2
Bit Test and Branch Instructions
PAl
Versatile Interrupt Handling
Versatile Index Register PAO
Powerful Indexed AddreSSing for Tables PB7
Full Set of ConditIOnal Branches
Memory Usable as Register/Flags PB6
Single Instruction Memory Examlne/ Change PB5
10 Powerful AddresSing Modes PB4
All AddreSSing Modes
User Callable Self-Check Subroutines PB3
PB2
USER SELECTABLE OPTIONS:
PBl
• InternalS-Bit Timer With Selectable Clock Source IExternal Timer
Input or Internal Machine Clockl PBO
• Timer Prescaler Option 17 Bits 2N) PDO/ANO
• 8 BidirectionalI/O Lines With TTL or TTLI CMOS Interface Option
PD1/ANl
• Crystal or Low-Cost Resistor OSCillator Option
• Low Voltage Inhibit Option PD2/AN2
• 4 Vectored Interrupts, Timer, Software, and 2 External PD3/AN3

4-191
 MC6805R2

,,- 7
Prescaler J
FIGURE 2 -

Tlmerl
8 Counter

Timer Control
MC8806R2 HMOS MICROCOMPUTER BLOCK DIAGRAM

H
Xl
l

Oscillator
EJl

~
RESET NUM

T
I •
PA0 ' "
PA1 _ Accumulator AID !\
J:...J
a: a:
Analog
MUX
1
Port PA 8 ~ »
~::
Port Data CPU
A PA A 0" t- Index Control
110
lines
PA. 4 ' "
PA
Reg Reg Register 10- IINT2 ~ PDQ/ANO

~=
8 X t- PD1/AN1
PA r- PD2/AN2 Port
Condition
PA. 7 _
Code PD3/AN3 o

.
Input
5 Register CC VRl
CPU Lines
VRH_
Stack PD6I1NT2

•
POinter PD7
PB0 _ 5 SP
PB 1..... Program
~ .~
Port PB 2 _

1
Port Data

•
Counter Port 0
B
110
lines
PB3 _
PB
PB
PB 6
~:::
7_.....
_
B
Reg
0"
Reg
r-< 4 High
Program
Counter
PCH AlU Input
J
PB 8 low PCl
1
::: PCO
PC1

1 T Data Port
C
:: PC2
PC3
Port
C
204B x 8
User ROM
64x8
RAM
0"
Reg Reg
::: PC4
PC5
110
lines
Self-Check
ROM
::: PC6
PC7

MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage VCC -03 to + 70 V
Input Voltage V in -03 to + 70 V
Stresses above those listed under "MaXimum
Operating Temperature Range TA o to 70 ·C
Ratings" may cause permanent damage to the
Storage Temperature Range T~ -55 to +150 ·C
device ThiS IS a stress rating only and functional
Junction Temperature operation of the device at these or any other con-
Plastic Package 150 ditIOns above those indicated In the operational
Ceramic Package TJ 175 ·C sections of thiS specification IS not Implied Ex-
Cerdlp 175 posure to absolute maximum rating conditions
for extended penods may affect device reliability
THERMAL CHARACTERISTICS Reliability of operation IS enhanced If unused in-
puts are tied to an appropnate logic voltage level
Characteristic Symbol Value Unit
(e g • either VSS or VCC)
Thermal Resistance
PlastiC 100
8JA ·C/W
Ceramic 50
Cerdlp 60

4-192
MC6805R2

POWER CONSIDERATIONS

The average chip-Junction temperature, T J, In °c can be obtained from'

Tj=TA+I PO·8JAI 111
Where
TA-Amblent Temperature, °c
8JA- Package Thermal ReSistance, junctlon-to-Amblent, °C/W
PO- PINT+ PPORT
PINT-ICC x VCe. Watts - Chip Internal Power
PPORT - Port Power O,ss,pat,on, Watts - User Oetermlned
For most applicallOns PPORT <C PINT and can be neglected PPORT may become Significant If the deVice IS configured to
drive Oarlington bases or Sink LEO loads
An approximate relallOnshlp between Po and T j (,f PPORT IS neglectedl IS'
Po = K -IT J + 273°CI 121
SolVing equations 1 and 2 for K gives.
K = PO.(T A + 273°CI + 8JA.P 0 2 131
Where K IS a constant pertaining to the particular part K can be determined from equation 3 by measuring Po lat eqUilibrluml
for a known T A USing thiS value of K the values of Po and T J can be obtained by solVing equations (11 and 121 Iteratively for any
value of T A

ELECTRICAL CHARACTERISTICS (VCC = + 525 Vdc ± 05 Vdc VSS = GND TA = 0° to 70°C Unless Otherwise Noted)

Input High Voltage

REm (4 75SVCCs5 75)
IVCC<475)
INT 14 75sVCCs5 75)
Characteristic Symbol

V,H
Min

40
VCC-O 5
40
Typ

-
-
*
Max

VCC
VCC
VCC
Unit

V
•
IVCC<475) VCC-O 5 * VCC
AI) Other 20 - VCC
Input High Voltage Timer
Timer Mode V,H 20 - VCC V
Self-Check Mode - 90 150
Input Low Voltage
RESET -03 - 08
INT V,L -03 * 15 V
All Other (Except AID Inputs) -03 - 08
RESET HysteresIs Voltages (See Figures 11, 12, and 13)
"Out of Reset" V'RES+ 21 - 40 V
"Into Reset" V,RES- 08 - 20
INT Zero Crossing Input Voltage, Through a Capacitor V,NT 2 - 4 Vac pop
Power DISSipation - No Port Loadrng V CC = 5 75 V, T A = O'C Po - 600 - mW
Input Capacitance
EXTAL Crn - 25 - pF
All Other Except Analog Inputs - 10 -
Low Voltage Recover VLVR - - 475 V
Low Voltage Inhibit VLVR - 35 V
Input Current
- - 20
TIMER (V rn = 0.4 V)
- 20 50
INT (V rn = 2 4 V to VCC)
Irn - - 10 ~A
EXTAL (V rn =2 4 V to VCC Crystal OptlOnl
(V,n=O 4 V Crystal OptIOn)
- - -1600
-40 - -50
RESET (V ,n = 08 VI
I External Capacitor Charging Current)

NOTE Port 0 Analog Inputs, when selected, C,n = 25 pF for the first 5 out or 30 cycles
*Due to rnternal biaSing thiS Input (when unusedl floats to approximately 2 0 V

4·193
 MC6805R2

AID CONVERTER CHARACTERISTICS IVCC= +525 Vdc ±O 5 Vdc, VSS=GND, TA=O' to 70°C Unless Otherwise Notedl
Characteristic Min Typ Max Un~ Comments
Resolution 8 8 8 Bits
Non-Linearity - - ± 1/2 LSB For VRH-4.0 to 5 0 V and VRL OV
Quantizing Error - - ± 1/2 LSB For VRH - 4.0 to 5.0 V and VRL OV
Conversion Range VRL - VRH V
VRH - - 50 V AID Accuracy may decrease proportionately as
VRL - 0.2 V VRH IS reduced below 4 0 V The sum of VAH and
VSS
VRL must not exceed 5 0 V
Conversion Time 30 30 30 tcyc Includes sampling time
MonotontClty Inherent {Within total error!
Zero Input Reading 00 00 01 hexadeCimal V,n-O
Ratlometnc Reading FF FF FF hexadeCimal V,n - VRH
Sample Time 5 5 5 tcyc
Sample I Hold Capacitance, Input - - 25 pF
Analog Input Voltage VRL - VRH V Negative tranSients on VAL are not
allowed at any time dUring converSion

SWITCHING CHARACTERISTICS IVCC= +5 25 Vdc ±O 5 Vdc, VSS'=GND, TA=O° to 70°C Unless Otherwise Notedl

•
Characteristic Symbol Min Typ Max Unit
OSCillator Frequency losc 04 - 42 MHz
Cycle Time 14/1osc l tCYC 095 - 10 ~s

INT, INT2, and TIMER Pulse Width tWL,tWH tcvc+ 250 - - ns

RESET Pulse Width tRWL tcvc + 250 - - ns
RESET Delay Time I External Cap= 1 ~FI tRHL - 100 - ms
INT Zero-Crossing Detection Input Frequency (for ± 5° Accuracy) flNT 003 - 1 kHz
External Clock Input Duty Cycle IEXTALI - 40 50 50 %

PORT ELECTRICAL CHARACTERISTICS IVCC= + 525 Vdc ± 05 Vdc, VSS = GND, TA = 0° to 70°C Unless Otherwise Notedl
Characteristic Symbol I Min I Typ I Max Unit
Port A with CMOS Drive Enabled
Output Low Voltage ILoad= 1 6 mA V_OJ. - - 04 V
Output High Voltage ILoad = -100 I'A VOH 24 - - V
Output High Voltage ILoad lO~A VOH 35 - - V
Input High Voltage ILoad 300 I'A Imaxi VH 20 - Vce V
Input Low Voltag~ ILoad- 500 I'A Imaxl VIL -0.3 - 08 V
H,-Z-State Input Current IV In 2 U V to VCO IIH - - -300 ~A
H,-Z State Input Current IV In = 0 4 VI IlL - - -500 I'A
Port B
Output Low Voltage ILoad=3 2 mA VOL - - 04 V
Output Low Voltage ILoad-10 mA ISlnkl VOL - - 10 V
Output High Voltage ILoad= -200 I'A VOH 24 - - V
Darlington Current Dnve ISourcel VO= 1 5 V IOH -10 - -10 mA
Input High Voltage VIH 20 - VCC v
Input Low Voltage VIL -03 - 08 V
HI-Z-State Input Current ITSI - 2 20 I'A
Port C and Port A with CMOS Device Disabled
Ouput Low Voltage ILoad= 1 6 mA VOL - - 04 V
Output High Voltage ILoad- -100 I'A VOH 24 - - V
Input High Voltage VIH 20 - VCC V
Input Low Voltage VIL -0.3 - 0.8 V
H,-Z-State Input Current ITS I - 2 20 ~A
Port D (Dig~llnputs Only)
Input High Voltage J Vlt:L 2.0 - Vce I V
Input Low Voltage I VIL -03 - 08 I V
Input Current* I", - - 20 I'A

*VRL/PD4- VRH/PD5 The AID conversIon resistor (11.6 k nomlnall IS connected internally between these two lines, Impacting the" use as
digital Inputs In some applications.

4-194
MC6805R2

FIGURE3 - TTL EQUIVALENT TEST LOAD FIGURE4 - CMOS EQUIVALENT TEST LOAD FIGURE 5 - TTL EQUIVALENT TEST LOAD
{PORT BI {PORT AI {PORTS A AND CI

VCC~575V VCC~575V
Test MMD6150 Test
POint or Equlv POint
15kll
TestPOtnt~

40 pF 12 kll MMD7000 130 pF ITotal1 30 pF

11 Olall or Equlv 1T0tal!

SIGNAL DESCRIPTION five digital Inputs All port D lines can also be directly read
The Input and output signals for the MCU, shown In and used as binary Inputs The voltage reference pinS (VRH
Figure 1, are described In the following paragraphs and VRll for the A/D converter are also read as a part of
port D Refer to INPUT/OUTPUT, A/D CONVERTER, and
Vee AND VSS - Power IS supplied to the MCU uSing

•
INTERRUPTS for additional Information
these two pinS VCC IS power and VSS IS the ground con-
nection MEMORY - The MCU IS capable of addreSSing 4096
INT - This pin provides the capability for asynchronously bytes of memory and I/O registers with ItS program counter
applYing an external Interrupt to the MCU Refer to INTER- The MC6805R2 MCU has implemented 2316 of these bytes.
RUPTS for addltonal Information ThiS consists at- 2048 user ROM bytes, 192 self-check ROM
bytes, 64 user RAM bytes, 7 port I/O bytes, 2 timer registers,
XTAL AND EXTAL - These PinS provide control Input 2 A/ D registers and a miscellaneous register, see Figure 6 for
for the on-chip clock oscillator CIrCUit. A crystal, a resistor, or the Address Map The user ROM has been split Into three
an external signal depending on user selectable manufactur- areas. The first area IS memory locations $080 to $OFF, and
Ing mask opllon, can be connected to these pinS to provide a allows the user to access these ROM locations utilizing the
system clock with various degrees of stability/cost tradeoffs direct and table look-up Indexed addreSSing modes The
lead length and stray capacitance on these two pins should main user ROM area IS from $7CO to $F37. The last 8 user
be minimized Refer to INTERNAL CLOCK GENERATOR ROM locations at the top of memory are for the Interrupt
OPTIONS for recommendations about these Inputs vectors
The MCU reserves the first 16 memory locations for I/O
TIMER - The pin allows an external Input to be used to features, of which 12 have been Implemented These loca-
decrement the Internal timer CIrcuitry Refer to TI M ER for tions are used for the ports, the port DDRs, the timer, the
additional information about the timer circuitry INT2 miscellaneous register, and the A/D Of the 64 RAM
bytes, 31 bytes are shared With the stack area The stack
RESET - ThiS Pin allows resetting of the MCU at times
must be used With care when data shares the stack area
other than the automatic resetting capability already In the
The shared stack area IS used dUring the processing of an
MCU The MCU can be reset by pulling RESET low Refer to
Interrupt or subroutine calls to save the contents of the CPU
RESETS for additional Information
state The register contents are pushed onto the stack In
NUM (Non-User Model - ThiS pin IS not for user applica- order shown In Figure 7. Since the Stack pOinter decrements
tion and must be connected to VSS dUring pushes, the low order byte (PCL) of the Program
Counter IS stacked first. then the high order four bits (PCHI
INPUT/OUTPUT LINES (PAO-PA7, PBO-PB7, PCO-PC7, are stacked. ThiS ensures that the program counter IS loaded
PDO-PD7) - These 30 lines are arranged Into three 8-blt correctly dUring pulls from the stack Since the stack pOinter
ports {A, B, and CI plus port D with 6 Inputs Ports A, B, and Increments when It pulls data from the stack. A subroutine
C are programmable as either Inputs or outputs, under soft- call results In only the Program Counter (PCl, PCHI con-
ware control of the data direction registers Port D has from tents bing pushed onto the stack, the remaining CPU
one to four analog Inputs, an INT2 Input, and from one to registers are not pushed

4-195
 MC6805R2

FIGURE 6 - MC6805R2 MCU ADDRESS MAP

7 o 76543210
000 $000
1/0 Ports 0 Port A Data $000
Timer
Page Zero 1 Port 8 Data $001
RAM
Access with 1128 Bytes) 2 Port C Data $002
Short 127 $07F
Instructions
128 $080 3 Port 0 Data $003
Page Zero

I~FF
User ROM 4 Port A DDR* $004*
1128 Bytes)
255 5 Port B DDR* $005*
256 $100 6 Port C DDR* $006*
Not Used
11728 Bytes) 7 Not Used $007

$7BF 8 Timer Data Reg $008

1963
1984 $7CO 9 Timer Control Reg $009
Mam User
ROM 10 Mise Reg $ooA
11912 Bytes)
3895 $F37 11 Not Used $008
3896 $F38 13 Bytes)
Self Check 13 $000

•
ROM 14 AID Control/Status $ooE
1192 Bytes)
4087 $FF7 15 AID Result $ooF
4088 $FF8 16
Interrupt Not Used
Vectors 63 148 Bytesl $03F
ROM 64 $040
18 Bytes) RAM
4095 $FFF
164 Bytes)

Stack
131 Bytes Maximum)
*Caution. Data 0 frectiOn Registers IDDRs) are
wnte-o nly, they read as $FF 127 t $07F

CENTRAL PROCESSING UNIT

The CPU of the M6805 Family IS Implemented In-
dependently from the I/O or memory configuration Conse-
FIGURE 7 - INTERRUPT STACKING ORDER
quently, It can be treated as an Independent central pro-
6 5 4 3 o Pull cessor communicating with I/O and memory via Internal ad-

n-4 11 1 I Condition
Code Register n+l
dress, data, and control buses

REGISTERS
n-3 Accumulator n+2
The M6805 Family CPU has five registers available to the
programmer. They are shown In Figure a and are explained In
n-2 Index Register n+3
the following paragraphs.

n- 1 1 11 lJ PCH* n+4 ACCUMULATOR (A) - The Accumulator IS a general

purpose 8-blt register used to hold operands and results of
PCl* n+5 arithmetic calculations or data manipulations
Push
INDEX REGISTER (X) - The Index Register IS an a-bit
"'For subroutine calls, only PCH and PCl are stacked
register used for the Indexed addreSSing mode. It contains an
a-bit value that may be added to an Instruction value to
create an effective address. The Index register can also be
used for data manipulations uSing the read/ modifY/Write In-
structions. The Index Register may also be used as a tem-
porary storage area.

4·196
MC6805R2

FIGURE 8 - PROGRAMMING MOOEL

7 a
I...______A_ _ _ _-'I Accumulator
a
x I Index Register
11 a
PCH PCl I Program Counter
11 54 a
10101010101 SP I Stack POinter
Condition Code Register

arry/Borrow

L----INegat've
'-------llnterrupt Mask

II
' - - - - - - - - H a l f Carry

PROGRAM COUNTER (PC) - The Program Counter IS a Half Carry (H) - Set dUring ADD and ADC opera lions to
12-blt register that contains the address of the next instruc- indicate that a carry occurred between bits 3 and 4
tion to be executed
STACK POINTER (SP) - The Stack POinter IS a 12-blt Interrupt (I) - When thiS bit IS set, the timer and external
register that contains the address of the next free location on Interrupts liNT and INT21 are masked (disabled). If an inter-
the stack DUring an MCU reset or the Reset Stack POinter rupt occurs While thiS bit IS set the Interrupt IS latched and IS
(RSPI Instrucllon, the Stack POinter IS set to locallon $07F processed as soon as the Interrupt bit IS cleared.
The Stack POinter IS then decremented as data IS pushed on-
to the stack and Incremented as data IS then pulled from the Negative (N) - When set, thiS bit Indicates that the result
stack. The seven most-Significant bits of the Stack POinter of the last arithmetiC, logical, or data manipulation was
are permanently set to 0000011 Subroutines and Interrupts negative (bit 7 In the result IS a logical onel
may be nested down to location $061 (31 bytes maxlmuml
which allows the programmer to use up to 15 levels of
Zero (Z) - When set, thiS bit Indicates that the result of
subroutine calls lIess If Interrupts are allowed)
the last arithmetiC, logical, or data manipulation was zero.
CONDITION CODE REGISTERS (CC) - The Condilion
Code Register IS a 5-blt register In which four bits are used to Carry/Borrow (C) - When set, this bit Indicates that a
indicate the results of the Instruction Just executed. These carry or borrow out of the ArithmetiC LogiC Unit (ALU)
bits can be IndiVidually tested by a program and specific ac- occurred dUring the last arithmetiC operation ThiS bit IS also
tion taken as a result of their state Each bit IS explained In affected dUring bit test and branch Instructions plus shifts
the follOWing paragraphs and rotates.

4·197
 MC6805R2

TIMER TIMER Input pin allOWing the user to eaSily perform pulse-
The MC6805R2 MCU timer circuitry IS shown In Figure 9. Width measurements. (NOTE· For ungated </>2 clock Input to
The 8-blt counter may be loaded under program control and the timer prescaler, the TIMER Pin should be tied to VCC'
is decremented toward zero by the clock Input (or prescaler The source of the clock Input IS one of the mask options that
output). When the timer reaches zero, the tlmar Interrupt re- IS specified before manufacture of the MCU
quest bit (bit 7) In the Timer Control Register (TCR) IS set.
A prescaler optiOn can be apphed to the clock Input that
The timer Interrupt can be masked (disabled) by setting the
extends the timing Interval up to a maximum of 128 counts
timer interrupt mask bit (bit 6) In the TCR The Interrupt bit
before decrementing the counter ThiS prescahng mask op-
(I-bit) In the Condition Code Register also prevents a timer
tion IS also speCified before manufacture To aVOid trunca-
Interrupt from being processed. The MCU responds to thiS
tion errors, the prescaler IS cleared when bit 3 of Timer Con-
interrupt by saving the present CPU state In the stack,
trol Register IS written to a logiC 1 (thiS bit always reads as a
fetching the timer Interrupt vector from locatiOns $FF8 and logiC 01. .
$FF9 and executing the Interrupt routine (see the INTER-
The timer continues to count past zero, falhng through to
RUPT section). THE TIMER INTERRUPT REQUEST 81T
$FF from zero and then continUing the count. Thus, the
MUST BE CLEARED BY SOFTWARE. The timer and iiiiT2
counter can be read at any time by reading the Timer Data
share the same Interrupt vector THE INTERRUPT ROUTINE
Register (TOR) ThiS allows a program to determine the
MUST CHECK THE REQUEST BITS TO DETERMINE THE
length of time since a timer Interrupt has occurred, and not
SOURCE OF THE INTERRUPT
disturb the counting process.
The clock Input to the timer can be from an external
At power-up or reset, the prescaler and counter are In-
source (decrementing of Timer Counter occurs on a POSitive
Itialized With all logical ones; the timer Interrupt request bit
transItiOn of the external source) apphed to the TIMER Input
(bit 7) IS cleared and the timer Interrupt request mask bit (bit
Pin, or It can be the Internal </>2 signal. When the </>2 signal IS

II
6) IS set.
used as the source, It can be gated by an Input applied to the

FIGURE 9 - TIMER BLOCK DIAGRAM

Timer
Interrupt Not
TIMER Mask
Input
Pin
,..------,
I I
:L______!I
Manufactunng
Mask Options
Wrtte Read Write Read

ln_te_r_na_I_D_a_ta_B_u_s________________
L-_______________ ~I·

SELF-CHECK
The self-check capability of the MC6805R2 MCU prOVides clear If any error IS detected; otherwise the Z-blt IS set The
an internal check to determine If the part is functional. Con- walking diagnostic pattern method IS used.
nect the MCU as shown in Figure 10 and moMor the output The RAM test must be called With the stack pOinter at
of Port C bit 3 for an oscillatiOn of approxlmaty 7 Hz. A 9 volt $07F.When run, the test checks every RAM cell except for
level on the T(MER Input, pin 8, energizes the ROM-based $07F and $07E which are assumed to contain the return
self-check feature. The self-check program exercises the address.
RAM, ROM, timer, AID, interrupts, and (f0 ports. The A and X registers and all RAM locations except the
Several of the self-check subroutines can be called by a top two are modified
user program with a JSR or BSR instruction. They are the ROM CHECKSUM SUBROUTINE - The ROM self-check
RAM, ROM, and 4-channel AID tests. The timer routine IS called at location $F8A and returns with the Z-blt cleared If
may also be called if the timer input IS the Internal </>2 clock. any error was found; otherwise Z = 1. X = 0 on return, and A
RAM SELF-CHECK SUBROUTINE - The RAM self- IS zero If the test passed. RAM locations $040-$043 are over-
check is called at location $F6F and returns With the Z-bit written.

4·198
MC6805R2

FIGURE 10 - SELF-CHECK CONNECTIONS

- -
RESET r-:l.
-
1-
r
I 40
VSS PA7
10-.... 39
MC6805R2 PA6
I'FT
2 RESET
PA5 1L-
3 INT
PA4 JL.
4 VCC
- ' - 10)'F PA3 36
+ 525 5
:r: ....1....'5.
*25
tXTAL
PA2 35
- :r:~ 4~ PAl 34
-- MHz
XTAL
7 NUM PAO
33
10k
8 TIMER
+ 9V LED tl. 510 9 PCO PS7 32
LEDb. ... 510·
10 PCl PS6 31
.. LED~' "'512-
II PC2 R-

•
PB5
LED~ 51
... " ... 0 " 12 PC3 PS4 ~
c...1l PC4 PS3 28
~ PC5 PS2 27

15 PC6 PB1 12- t--

16 PC7 PSO 12...
--1l PD7

~ PD6/1iNT21 24
PDD/AND
19 VRH

T
PD1/AN1 23
01 22
PD2/AN2
20 VRL PD3/AN3 21

J:.
-
*Thls connection depends on clock oscillator user selectable mask option Use Jumper If the RC mask option IS selected

LED Meanings
CO C1 C2 C3 Remarks [1:LED ON; O:LED OFF]
I 0 1 0 Sad 110
0 0 I 0 Bad Timer
I I 0 0 Sad RAM
0 I 0 0 Bad ROM
I
0
0
0
0
0
All Flashing
I
0 Sad AID
0 Bad Interrupts or Request Flag
Good Part
Anything else bad Part, Sad Port 3, Sad ISP, etc

A-TO-D CONVERTER SELF-CHECK - The AID self- In order to work correctly as a user subroutme, the Internal
check IS called at location SFA4 and returns with the l-blt <1>2 clock must be the clocking source and mterrupts must be
cleared If any error was found, otherwise l = 1. disabled. Also, on eXit, the clock IS runnmg and the mterrupt
The A and X register contents are lost. The X register must mask not set so the caller must pr6tect from mterrupts If
be set to 4 before the call. On return X = 8 and AI D channel 7 necessary.
IS selected. The AI D test uses the mternal voltage references The A and X register contents are lost The timer self-
and confirms port connections check routme counts how many times the clock counts 10
128 cycles. The number of counts should be a power of two
TIMER SELF-CHECK SUBROUTINE - The timer self- Since the prescaler IS a power of two If not, the timer
check IS called at location SFCF and returns with the l-blt probably IS not countmg correctly. The routme also detects a
cleared If any error was found; otherwise l= 1. timer which IS not running.

4·199
 MC6805R2

RESETS INTERNAL CLOCK GENERATOR OPTIONS

The MCU can be reset three ways: by Intllal power-up, by The Internal clock generator CirCUit IS designed to reqUire a
the external reset Input (RESET), and by an Icyc Internal low minimum of external components A crystal, a resistor, a
voltage detect circUit, see Figure 11 The Internal CircUit con- lumper Wire, or an external signal may be used to control the
nected to the RESET Pin consists of a Schmitt trigger which Internal clock generator with various stability/ cost tradeoffs
senses the RESET line logic level. The Schmitt trigger pro- A manufactUring mask option IS used to select the crystal or
vides an Internal reset voltage If It senses a logical 0 on the resistor option The OSCillator frequency IS Internally diVided
RESET pin. DUring power-up, the Schmitt trigger switches by four to produce the Internal system clocks
on (removes reset) when the RESET pin voltage rises to The different connection methods are shown In Figure 14
VIRES + When the RESET pin voltage falls to a logical 0 for The Crystal specifications are given In Figure 15 A resistor
a period longer than one tcyc, the Schmitt trigger sWitches selection graph IS shown In Figure 16
off to provide an Internal reset voltage. The "switch off" The crystal OSCillator start-up time IS a function of many
voltage occurs at VIRES- A typical reset Schmitt trigger variables crystal parameters (especially Rs) OSCillator load
hysteresIs curve IS shown In Figure 12 capaCitances, IC parameters, ambient temperatures, supply
Upon power-up, a delay of TRHL milliseconds IS needed voltage, and supply voltage turn-on time To ensure rapid
before allowing the RESET Input to go high This time allows OSCillator start-up, neither the crystal charactenstlcs nor the
the Internal clock generator to stabilize Connecting a load capacitances should exceed recommendations
capacitor to the RESET Input as shown In Figure 13 tYPically
proVides sufficient delay

• 5V
ov
vee _______.J
FIGURE 1t - POWER AND RESET TIMING

RESET
Pin
-------~

Internal
Reset _ _ _ _ _ _ _ _ _ _--J

FIGURE 12 - TYPICAL RESET SCHMITI

TRIGGER HYSTERESIS FIGURE 13 - POWER UP RESET DELAY CIRCUIT

Out
Of
Reset --.!-
Vce_~~r-~2~a~-,
REsET
I
Part Of
MC8805R2
MCU
In
Reset L--i-~-~~-+-------
oav 2V 4V

4·200
MC6805R2

FIGURE 14 - CLOCK GENERATOR OPTIONS

XTAL XTAL

ISee Note) CJ MC6805R2 MC6805R2

4 EXTAL MCU 4 EXTAL MCU
{Crystal Mask (Resistor Mask
CL
::::r: Option) Option)

Crystal Approximately 25 % Accu racy

TYPical tCYC = 1 251's
External Jumper

+5V
XTAL XTAL
MC6805R2
External MC6805R2
4 ISee Figure 16) 4 EXTAL MCU
Clock EXTAL MCU
(Resistor Mask
Input ICrystal Mask No
OptlOnl
OptlOnl Connection

NOTE
External Clock Approximately 10% Accuracy
External Resistor
(Excludes Resistor Tolerance)

The recommended CL value with a 4 0 MHz cry tal IS 27 pF, maXimum, Inlcudlng system dlstnbuted capacitance There IS an Internal
II
capacitance of approximately 25 pF on the XTAL pin For crystal frequencies other than 4 MHz, the total capacitance on each Pin
should be scaled as the Inverse of the frequency ratio For example, with a 2 MHz crystal, use approximately 50 pF on EXTAL and ap-
proximately 25 pF on XTAL The exact value depends on the Motional-Arm parameters of the crystal used

FIGURE 15 - CRYSTAL MOTIONAL ARM PARAMETERS

AND SUGGESTED PC BOARD LAYOUT
Crystal Motional Arm

EqUlv:~:~:a~~ XTAL

5 ~E---J 6

AT - Cut Parallel Resonance Crystal

Ca =7 pF Max
FREQ=40 MHz@ CL=24pF
RS = 50 ohms Max
lal
Ibl

Note Keep crystal leads and circuit connections as short as possible

4-201
 MC6805R2

FIGURE 16 - TYPICAL FREQUENCY SELECTION FOR INTERRUPTS

RESISTOR OSCILLATOR OPTION The MC6805R2 MCU can be interrupted four different
50 ways: through the external Interrupt (I NTI Input Pin, the

1'\ I 1
VCC=5 V
Internal timer Interrupt request, the external port D bit 6
(lNT21 Input pin, and a software Interrupt instruction ISWII
N 40 TA=25'C - When any Interrupt occurs, processing IS suspended, the
I
~
>- 30
~ present CPU state IS pushed onto the stack, the Interrupt bit
II-bltl in the Condition Code Register IS set, the address of
u the Interrupt routine IS obtained from the appropriate inter-
zw "",- rupt vector address, and the Interrupt routine IS executed
::J
~ 20
Stacking the CPU registers, setllng the I-bit, and vector
c: .......... fetching reqUires a total of 11 tcyc periods for completion
u.
i'-- r--.. Refer to Figure 17 for a flowchart The Interrupt service
10 routine must end With a Return from Interrupt IRTII,nstruc-
' ..... tlon which allows the MCU to resume processing of the pro-
gram prior to the Interrupt Table 1 proVides a listing of the
o Interrupts, their PriOrity, and the address of the vector which
o 5 10 15 20 25 30 35 40 45 50 55 60
RESISTANCE (k OHMSI

FIGURE 17 - RESET AND INTERRUPT PROCESSING FLOWCHART

• 1-1110 CCRI Clpar

07F- SP
O-DDR's Stack
CLR INT LogiC INT PC, X, A, CC
FF- Timer
7 F-Prescaler
7F- TCR
7F-MR
O-CSR

TlJnt-'f

Put on FFE
Address Bus
N
Timer
or INT2 FF8/FF9
Fetch
Instruction

PC-PC+ 1 I--'S"W.:.':.....,.J

Load PC
from
FFE/FFF
Execute
Instruction

4-202
MC6805R2

contains the starting address of the appropriate Interrupt ser- Miscellaneous Register (MR), refer to Figure 18 The INT2
vice routine. The Interrupt Priority applies to those pending Interrupt IS Inhabited when the mask bit IS set The INT2 IS
when the CPU IS ready to accept a new Interrupt RESET IS always readable as a digital Input of Port D The INT2 and
listed in Table 1 because It IS processed similar to an Inter- timer Interrupt request bitS, If set, causes the MCU to pro-
rupt. However, It IS not normally used as an Interrupt. When cess an Interrupt when the condition code I-bit IS clear
the Interrupt mask bit In the Condition Code Register IS set
the Interrupt IS latched for later Interrupt execution TABLE 1 - INTERRUPT PRIORITIES
NOTE
The timer and INT2 share the same vector address. Interrupt Priority Vector Address
The Interrupt routine must determine the source by RESET 1 $FFE and $FFF
SWI 2* $FFC and $FFD
examining the Interrupt request bits ITCR7 and MR7)
INT 3 $FFA and $FFB
Both TCR7 and M R7 can only be written to 0 by soft- TIMER/OO2 4 $FF8 and $FF9
ware.
The external Interrupts, INT and INT2, are set on the fail- * Pnorlty 2 applies when the I-bit
In the Condition Code Register IS
Ing edge of the Input signal The INT2 has an Interrupt re- set When 1=0, SWI has a pnorlty of 4, Irkeany other Instruction,
quest bit (bit 7) and a mask bit (bit 6) located In the the PriOrity of iN"f thus becomes 2 and the timer becomes 3

FIGURE 18 - MCU REGISTER CONFIGURATION

PORT DATA DIRECTION REGISTER IDDR) PORT DATA REGISTER
o

•
a

(1) Write Only, reads as aliI's Port A Addr = $000

(2) 1 = Output. 0= Input Cleared to a by Reset Port B Addr = $001
(3) Port A Addr = $004 Port C Addr = $002
Port B Addr = $005 Port D Addr = $003
Po,t C Addr = $006

TIMER CONTROL REG)STER ITCR) TIMER DATA REGISTER ITDR)

a
654321 a
MSB LSB 1$008
$009

TCR7 - Timer Interrupt Request Status Bit Set when

TOR goes to zero, must be cleared by software
Cleared to a by Reset
TCR6- Timer Interrupt Mask Bit 1 = trmer inter-
rupt masked (disabled) Set to 1 by Reset
TCR3- Clear prescaler always reads as a 0, clears pre-
scaler when wntten to a logiC 1
TCR Bits 5. 4. 2. 1. a reads I's - unused bits
MISCELLANEOUS REGISTER IMR)
6 a
L-~ __ ~ ________________ ~ I $ooA

MR7 Bit 7 -INT2 Interrupt Request Bit Set when fail-

Ing edge detected on INT2 Pin. must be
cleared by software Cleared to 0 by Reset
MR6 Bit 6-INT2 Interrupt Mask Bit 1 = INT2 Interrupt
masked (disabled)' Set to 1 by Reset
MR B)ts5, 4, 3. 2.1. a-Read as l's - unused bits

AID CONTROL REGISTER (ACR) AID RESULT REGISTER (ARR)

6 5 4 3 a 7 a
MSB LSB I $ooF

Bit 7 - Conversion Complete Status Flag Set when

converSion IS complete. Cleared only on a write
to ACR

Readable, not wntable

Bits 2.1.0 - AID Input Mux Selection (See Table 2)

Bits 6,5.4,3 read as l's - unused bits

4·203
 MC6805R2

A sinusoidal Input signal (fINT maxlmuml can be used to responding bit In the port DDR to a logic "1" for output or a
operate an external Interrupt IINTI, as shown In Figure 19, logic "0" for input. On reset all the DDRs are initialized to a
for use as a Zero-Crossing Detector with hysteresIs Included. logic "0" state, plaCing the ports In the Input mode. The port
An Interrupt request IS generated for each negative-slope, output registers are not Inilialized on reset and should be
zero crossing of the AC signal. For digital applications, the Initialized by software before changing the DDRs from Input
INT can be driven directly by a digital Signal at a maximum to output When programmed as outputs, all I/O pinS read
period of tIWL. This allows applications such as servIcing latched output data, regardless of the logic levels at the out-
tlme-of-day routines and engaglng/ disengaging AC power put pin due to output loading, refer to Figure 20
control devices Off-chip full wave rectification prOVides an All Input/output lines are TTL compatible as both Inputs
Interrupt at every zero crossing of the AC Signal and thereby and outputs Port A lines are CMOS compatible as outputs
provide a 2f clock uSing a mask option. Port B, C, and D lines are CMOS com-
A software Interrupt (SWII IS an executable instruction patible as Inputs. Port D lines are Input only, thus, there IS no
which IS executed regardless of the state of the I-bit In the corresponding DDR When programmed as outputs, Port B
Condition Code Register SWI's are usually used as break- IS capable of Sinking 10 milliamperes and sourcing 1 0
pOints for debugging or as system calls milliampere on each pin
INPUT/OUTPUT Port D prOVides the multiplexed analog Inputs, reference
There are 30 Input or Input/ output pins The INT pin may voltages, and INT2 All of these lines are shared With the Port
also be polled With branch Instructions to provide an addi- D digital Inputs Port D may always be used as digital Inputs
tional Input pin All pins on ports A, B, and C are program- and may also be used as analog Inputs The VRL to VRH
mable as either Inputs or outputs under software control of lines (PD4 and PD51 are Internally connected by the A/D
the corresponding Data Direction Registers !DDRsl The resistor Analog Inputs may be pre-scaled to attain the V RL

•
port I/O programming IS accomplished by setting the cor- to VRH recommended Input voltage range

FIGURE 19 - TYPICAL INTERRUPT CIRCUITS

a - Zero Crossing Interrupt b - Digital Signal Interrupt

Vce
AC
Input (Currer,t TTL 47 K:
IflNT Max) Limiting) 3 iNi MC6805R2 Level ~ 3 iNT
MC6805R2

-rr
DI9,tal---4'--I
R,; 1 MU ~~---;1+~-"""-\ MCU MCU
Input
AC Input", 10 Vpp 01 p.F (1IWL Maximum
Period)

FIGURE 20 - TYPICAL PORT 110 CIRCUITRY

Data
Direction Register
Blt*

Latched
Output
Data
Bit

Data
Direction Output Input
Register Data Output To ~DDR IS a write-only register and reads as all 1's
Bit Bit State MCU ··Ports A (With CMOS dnve disabled), 8, and C are three-state
1 a 0 a ports Port A has optional Internal puHup devices to proVide CMOS
1 1 drive capability See Electrical Characteristics tabies for complete
a X 3-5tat.** Pin Information

4-204
MC6805R2

Figure 21 provides some examples of port connections. write-only registers (locallOns $004, $005, and $0061 A
The Address Map In Figure 6 gives the addresses of data read operation on these registers IS undefined Since
registers and DDRs The Register Configuration IS provided BSET and BCLR are read/modify/write funcllons, they
In Figure 18 cannot be used to set or clear a DDR bit lall "unaffected"
CAUTION bits would be setl It IS recommended that all DDR bits In
The corresponding DDRs for Ports A, B, and Care a port be written uSing a single-store Instruction

FIGURE 21 - TYPICAL PORT CONNECTIONS

a. Output Modes

PA7 40 ICMOS Loadsl PB7 32

PA6 39 PB6 31

-
PA5 38 PB5 30
(1 TTL Loadl _Ib
PM 37 PB4 29 10 mA
PA3 36 16 mA PB3 2B
PA2 35 PB2 27
PAl 34 PBl 26
Port A, Bit 7 Programmed as Output. DriVing
PAO 33 CMOS Loads and Bit 4 one TTL Load Directly PBO 25
(Using CMOS Output Openon)
Port B, Bit 5 Programmed as Output, Dnvlng
Darhngton·Base Directly

PB7

PB6
PB5
PB4
32

31

30
29
+ V
PC7

PC6

PC5
PC4
16

15

14
13
+ V
II
PB3

PB2
28

27
1 f PC3

PC2
12

"
CMOS Inverter
MCI4049/14089
PCl 10 ITYPlcail
PBl 26
PCO
PBO 25
4--10mA
Port B, Bit 0 and Bit 1 Programmed as Output, Dnv" Port C, Bits 0·3 Programmed as Output. DriVing
tng LEOs Directly CMOS Loads, USing External Pullup ReSIstors

b. Input Modes

30 P85
38 PA5 MC74LS04 or MC14069 29 PB4
(TYPical)
MC74LS04 (TYPical) 37 PA4
28 PB3
36 PA3
27 PB2
35 PA2
PBl
PBO

CMOS or TTL Dnvmg Port B Directly

TTL Dnvlng Port A Directly

PC7

15 PC6

14 PC5

13 PC4

12 PC3

11 PC2 POO/iNT2
10 PCl PD7
(TYPical)

CMOS and TTL DriVing Port C Directly Port 0 used as 4-Channel AID Input with Bit 7 used
as CMOS Digital Input

4-205
 MC6805R2

The latched output data bit (see Figure 181 may always be The converter operates contlnously uSing 30 machine
wntten Therefore, any write to a port writes all of Its data cycles to complete a converSion of the sampled analog Input
bits even though the port DDR IS set to input. This may be When conversion IS complete, the digitized sample or digital
used to Initialize the data registers and aVOid undefined out- value is placed In the AID Result Register (ARR), the conver-
puts However, care must be exercised when uSing sion complete flag IS set, the selected Input IS sampled again,
read/modlfy/wnte instructions since the data read cor- and a new converSion IS started
responds to the pin level If the DDR IS an Input (0) and cor- The AID IS ratlometric Two reference voltage (VRH and
responds to the latched output data when the DDr IS an out- VRLI are supplied to the converter via Port D pinS An, Input
put (11 voltage equal to VRH converts to $FF (fuli'scale) and an in-
put voltage equal to VRL converts $00 An Input voltage
ANALOG-TO-DIGITAL CONVERTER (AID) The greater than VRH converts to FF16 and no overflow Indica-
MC6805R2 MCU has an 8-blt AID converter Implemented on tion IS proVided For ratlometnc converSions, the source of
the chip uSing a successive approximation technique, as each analog Input should use VRH as the supply voltage and
shown In Figure 22 Up to four external analog Inputs, via be referenced to VRL.
port D, are connected to the AID through a multiplexer
Four Internal analog signals may be selected for calibration
purposes (VRH, VRHf2. VRH/4, VRLI CAUTION
The multiplexer selection IS controlled by the AID Control ThiS device contains circUitry to protect the Inputs
Register (ACR) bits 0, 1, and 2, see Table 2. ThiS register IS against damage due to high static voltages or electnc
cleared dunng any Reset condition. Refer to Figure 18 for field, however, the deSign of the Input circuitry for the
Register Configuration analog reference voltage pinS (19 and 20) does not of-

•
Whenever the ACR IS Written, the conversion In progress fer the SAME level of protection Precautions should
IS aborted, the conversion complete flag (ACR bit 7) is be taken to aVOid applications of any voltage higher
cleared, and the selected Input is sampled and held inter- than maximum-rated voltage or handled In any en-
nally. vironment prodUCing high-static voltages

FIGURE 22 - AID BLOCK DIAGRAM

8

D/A
Control
10 k ITyp I Count
LogiC

PDO/ANO
PD1/ANl Select
PD2/AN2 Multiplexer
PD3/AN3
8

AID AID
Result
Register

TABLE 2 - AID INPUT MUX SELECTION

-
AID Control Register Input Selected
CR2 CRl CRD
a a a ANa
a a 1 ANI
a I 0 AN2
0 I I AN3
I 0 a VRH*
I a I VRL*
I I a VRH/4*
I I I VRH/2*
*lnternal (Calibration) levelS

4·206
MC6805R2

BIT MANIPULATION
The MC6805R2 MCU has the ability to set or clear any 1/0 bits as control lines
single RAM or Inputloutput bit lexcept the Data Direction The coding example In Figure 23 Illustrates the usefulness
Registers, see Caution under INPUT 10UTPUT paragraphl of the bit manipulation and test InstructIOns Assume that
with a single instruction IBRSET, BCLR) Any bit In page the MCU IS to communicate with an external serial deVice
zero Including ROM, except the DDRs, can be tested uSing The external deVice has a data ready signal. a data output
the BRSET and BRCLR Instructions and the program line, and a clock line to clock data one bit at a time, LBS first,
branches as a result of Its state The carry bit ICI equals the out of the deVice The MCU walts until the data IS ready,
value of the bit referenced by BRSET or BRCLR. The clocks the external deVice, picks up the data In the Carry Flag
capability of work with any bit In RAM, ROM, or 1/0 allows I C-bltl, clears the clock line and finally accumulates the data
the user to have ,nd,v,dual flags In RAM or to handle single bits In a RAM location

FIGURE 23 - BIT MANIPULATION EXAM PlE

MCU
BRSET 2,PORTA, " WAIT FOR READY Ready I--
2P
" BSET 1, PORTA CLOCK NEXT BIT IN
Senal
Clock
0
BRClR
DeVice 1 R
0, PORTA, NEXT PICKUP BIT IN C-BIT
NEXT BClR 1, PORTA RETURN CLOCK LINE HIGH T
ASR RAMlOC MOVE C-BIT INTO RAM Data
°A
-

ADDRESSING MODES
The MC6805R2 MCU has ten addressing modes aVailable
for use by the programmer They are explained briefly In the
follOWing paragraphs For additional details and graphical
Illustrations, refer to the M6805 Family Users Manual
The term "effective address" lEA) IS used In describing the
addreSSing modes EA IS defined as the address from which
the argument for an Instruction IS fetched or stored
IMMEDIATE - In the Immediate addreSSing mode, the
INDEXED, NO OFFSET - In the ,ndexed, no offset
addreSSing mode, the effective address of the argument IS
contained In the S-blt Index register Thus, thiS addreSSing
mode can access the first 256 memory locations These in-
structions are only one byte long ThiS mode IS often used to
move a pOinter through a table or to hold the address of a
frequently referenced RAM or 1/0 location
INDEXED, 8-BIT OFFSET - In the Indexed, S-blt offset
addreSSing mode, the effective address IS the sum of the
•
operand IS contained In the byte Immediately follOWing the contents of the unSigned S-blt Index register and the unsign-
opcode The Immediate addreSSing mode IS used to access ed byte follOWing the opcode ThiS addreSSing mode IS
constants which do not change dUring program execution useful In selecling the kth element In an n element table
Ie g , a constant used to Initialize a loop counterl With thiS 2-byte InstructIOn, k would tYPically be In X With
DIRECT - In the direct addreSSing mode, the effective the address of the beginning of the table In the instruction
address of the argument IS contained In a Single byte follow- As such tables may begin anywhere Within the first 256
Ing the opcode byte Direct addreSSing allows the user to addressable locations and could extend as far as location 511
directly address the lowest 256 bytes In memory With a single ($lFEI
2-byte instruction ThiS address area Includes all on-chip INDEXED, 16-BIT OFFSET - In the Indexed, 16-bit offset
RAM and 1/0 registers and 12S bytes of ROM Direct addreSSing mode, the effective address IS the sum of the
addreSSing IS an effective use of both memory and time contents of the unSigned S-blt Index register and the two un-
EXTENDED - In the extended addreSSing mode, the ef- Signed bytes follOWing the opcode ThiS addreSSing mode
fective address of the argument IS contained In the two bytes can be used In a manner Similar to Indexed, S-blt offset ex-
follOWing the opcode Instructions With extended addreSSing cept that thiS 3-byte Instruction allows tables to be anywhere
mode are capable of referenCing arguments anywhere In In memory As With direct and extended, the Motorola
memory With a Single 3-byte instruction When uSing the assembler determines the shortest form of Indexed address-
Motorola assembler, the user need not speCify whether an Ing
instruction uses direct or extended addreSSing The BIT SET/CLEAR - In the bit setlclear addreSSing mode,
assembler automatically selects the shortest form of the in- the bit to be set or cleared IS part of the opcode, and the byte
struction follOWing the opcode speCifies the direct address of the byte
RELATIVE - The relative addreSSing mode IS only used In In which the speCified bit IS to be set or cleared Thus, any
branch instructions In relative addreSSing, the contents of readlwrlte bit In the first 256 locations of memory, including
1/0, can be selectively set or cleared With a Single 2-byte in-
the B-blt Signed byte follOWing the opcode Ithe offsetl IS
added to the PC If, and only If, the branch condition IS true struction See Caution under INPUT IOUTPUT paragraph
Otherwise, control proceeds to the next instruction The BIT TEST AND BRANCH - The bit test and branch
span of relative addreSSing IS from + 129 to -126 from the addreSSing mode IS a combination of direct addreSSing and
opcode address. The programmer need not worry about relative addreSSing The bit which IS to be tested and condi-
calculating the correct offset If he uses the Motorola tion (set or clear) Included In the opcode, and the address of
assembler, Since It calculates the proper offset and checks to the byte to be tested IS In the Single byte Immediately follow-
see If It IS Within the span of the branch. Ing the opcode byte. The Signed relative S-blt offset In the

4·207
 MC6805R2

third byte IS added to the PC If the specified bit IS set or clear ed from memory uSing one of the addreSSing modes The
in the specified memory location. This single 3-byte Instruc- Jump uncondltlonallJMP) and Jump to subroutine IJSR) in-
lion allows the program to branch based on the condition of structions have no register operand Refer to Table 3
any readable bit In the first 256 location of memory The span READ/MODIFY/WRITE INSTRUCTIONS - These in-
of branching IS from + 130 to - 125 from the opcode structions read a memory location or a register, modify or
address The state of the tested bit IS also transferred to the test ItS contents, and write the modified value back to
Carry bit of the Condition Code Registers. See Caution memory or to the register, see Caution under INPUT/OUT-
under INPUT/OUTPUT paragraph. PUT paragraph The test for negative or zero ITST) instruc-
INHERENT - In the Inherent addressing mode, all the in- tion IS Included in the read/modify/write instruction though
formallon necessary to execute the instruction IS contained It does not perform the write. Refer to Table 4
In the opcode Operations specifYing only the Index register BRANCH INSTRUCTIONS - The branch instructions
or accumulator, as well as control Instructions with no other cause a branch from the program when a certain condition IS
arguments, are Included In thiS mode These instructions are met Refer to Table 5
one byte long.
BIT MANIPULATION INSTRUCTIONS - The Instruc-
INSTRUCTION SET tions are used on any bit In the first 256 bytes of the memory,
The MC6805R2 MCU has a set of 59 baSIC instrucllons, see Caution under INPUT (OUTPUT paragraph One group
which when combined with the 10 addressing modes pro- either sets or clears The other group performs the bit test
duce 207 usable opcodes They can be diVided Into five dif- and branch operations Refer to Table 6
ferent types register/memory, read/modlfy/wnte, branch, CONTROL INSTRUCTION - The control Instructions
bit manipulation, and control The following paragraphs control the MCU operations dUring program execution
briefly explain each type. All the instructions within a given Refer to Table 7

•
type are presented In indiVidual tables ALPHABETICAL LISTING - The complete instruction set
REGISTER/MEMORY INSTRUCTIONS - Most of these IS given In alphabetical order In Table 8
instructions use two operands One operand IS 8Ither the ac- OPCODE MAP - Table 9 IS an opcode map for the in-
cumulator or the Index register The other operand IS obtaln- struction used on the MCU

4-208
 TABLE 3 - REGISTER/MEMORY INSTRUCTIONS s:
n
~
Addressmq Modes
Indeked Indexed Indelled
Immediate Direct Extended (No Offset) (8 Sit Offset) (' 6 alt Offset)

Function
Op # # Op Op
•
MnemOniC Code Bytes Cycles Code Bytes Cycles Code Bytes Cycles
• • • Op # Op # # #
Code Bytes Cycles Code Bytes Cycles
OP #•
Code Bytes Cycles
:JJ
N
Load A from Memory lDA A6 2 2 B6 2 4 C6 3 5 F6 1 4 E6 2 5 D6 3 6
Load X from Memory lDX AE 2 2 8E 2 4 CE 3 5 FE 1 4 EE 2 5 Df 3 6
Store A 10 Memory STA - 87 2 5 C7 3 6 F7 1 5 E7 2 6 D7 3 7
Store X 10 Memory STX - - 8F 2 5 CF 3 6 FF 1 5 EF 2 6 DF 3 7
Add Memory 10 A ADD A8 2 2 88 2 4 C8 3 5 F8 1 4 E8 2 5 D8 3 6
Add Memory and
Carry to A ADC A9 2 2 89 2 4 C9 3 5 F9 1 4 E9 2 5 D9 3 6
Subtract Memory SUB AD 2 2 80 2 4 CO 3 5 FO 1 4 EO 2 5 DO 3 6
Subtract Memory from
A with Borrow SBC A2 2 2 82 2 4 C2 3 5 F2 1 4 E2 2 5 D2 3 6
AND Memory to A AND A4 2 2 84 2 4 C4 3 5 F4 1 4 E4 2 5 04 3 6
O~ Memory with A ORA AA 2 2 BA 2 4 CA 3 5 FA 1 4 EA 2 5 DA 3 6
EKclusl've OR Memory
with A EOR AB 2 2 BB 2 4 CB 3 5 F8 1 4 EB 2 5 D8 3 6
Arithmetic Compare A
with Memory CMP A1 2 2 B1 2 4 C1 3 5 F1 1 4 El 2 5 D1 3 6
Arithmetic Compare X
with Memory CPX A3 2 2 83 2 4 C3 3 5 F3 1 4 E3 2 5 D3 3 6
~
BIt Test Memory with
i\) A (Logical Compare) 81T A5 2 2 85 2 4 C5 3 5 F5 1 4 E5 2 5 D5 3 6
o Jump Unconditional JMP BC 2 3 CC 3 4 FC 1 3 EC 2 4 DC 3 5
CO - - -

Jump to Subroutine JSR - - BD 2 7 CD 3 8 FD 1 7 ED 2 8 DD 3 9

TABLE 4 - READ/MODIFY/WRITE INSTRUCTIONS

Addressing Modes
Indexed Indexed
Inherent tAl Inherent (Xl Direct (No Offset) (8 Bit Offset)

Function
Op # #
MnemOniC Code Bytes Cycles
Op #
•
Op
Code Bytes Cycles Code Bytes Cycles
• • Op #
Code Bytes Cycles
• Op
•
Code Bytes Cycles
•
Increment INC 4C 1 4 5C 1 4 3C 2 6 7C 1 6 6C 2 7
Decrement DEC 4A 1 4 5A 1 4 3A 2 6 7A 1 6 6A 2 7
Clear ClR 4F 1 4 5F 1 4 3F 2 6 7F 1 6 6F 2 7

Complement COM 43 1 4 53 1 4 33 2 6 73 1 6 63 2 7
Negate
(2's Complement) NEG 40 1 4 50 1 4 30 2 6 70 1 6 60 2 7
Rotate Left Thru Carry ROl 49 1 4 59 1 4 39 2 6 79 1 6 69 2 7
Rotate RIght Thru Carry ROR 46 1 4 56 1 4 36 2 6 76 1 6 66 2 7
LogIcal ShIft Left lSl 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7
LogIcal ShIft RIght lSR 44 1 4 54 1 4 34 2 6 74 1 6 64 2 7
ArithmetIc ShIft RIght ASR 47 1 4 57 1 4 37 2 6 77 1 6 67 2 7
Test for Negative
I or Zero TST 4D 1 4 5D 1 4 3D 2 6 7D 1 6 6D 2 7

II
 MC6805R2

TABLE 5 - BRANCH INSTRUCTIONS

Relative Addressing Mode

Op # #
Function Mnemonic Code Bytes Cycles
Branch Always BRA 20 2 4
Branch Never BRN 21 2 4
Branch IFF HIgher BHI 22 2 4
Branch IFF Lower or Same BLS 23 2 4
Branch IFF Carry Clear BCC 24 2 4
(BranchlFFHlgher or Samel (BHSI 24 2 4
Branch IFFCarry Set BCS 25 2 4
(Branch IFF Lowerl (BlOI 25 2 4
Branch IFF Not Equal BNE 26 2 4
Branch IFFEqual BEQ 27 2 4
Branch IFF Half Carry Clear BHCC 28 2 4
Branch IFF Half Carry Set BHCS 29 2 4
BranchlFF Plus BPl 2A 2 4
BranchlFF Minus BMI 2B 2 4
Branch IFFlnterupl Mask

I
BIt IS Clear BMC 2C 2 4
Branch IFF Interrupt Mask
Btt IS Set BMS 20 2 4
Branch IFF Interrupt Line
IS Low Bil 2E 2 4
Branch IFF Interrupt Line
IS HIgh BIH 2F 2 4
Branch to Subroutme BSR AD 2 8

TABLE 6 - BIT MANIPULATION INSTRUCTIONS

Addressing Modes
Bit SetlClear Bit Test and Branch
Op # # Op # /:
Function Mnemonic Code Bytes Cycles Code Byles Cycles
Branch IFF BIt n IS set BRSET n (n = 0 71 - - - 2 on 3 10
Branch IFF BIt n IS clear BRClR n (n = 0 71 - - - 01 + 2 en 3 10
Set Bit n BSET n (n - 0 71 10+2.n 2 7 - - -
Clear bIt n BClR n (n = 0 71 11 + 2 en 2 7 - - -

TABLE 7 - CONTROL INSTRUCTIONS

Inherent
Op # #
Function Mnemonic Code Bytes Cycles
Transfer A to X TAX 97 1 2
Transfer X to A TXA 9F 1 2
Set Carry a,t SEC 99 1 2
Clear Carry B.t ClC 98 1 2
Set Interrupt Mask Bit SEI 9B 1 2
Clear Interrupt Mask Bit CLI 9A 1 2
Software Interrupt SWI 83 1 11
Return from Subroutine RTS 81 1 6
Return from Interrupt RTI 80 1 9
Reset Stack POinter RSP 9C 1 2
No-Operatton NOP 9D 1 2

4-210
MC6805R2

TABLE 8 - INSTRUCTION SET

Addressing Modes Condition Code

Bit Bit
Indexed Indexed Indexed Setl Test a.
Mnemonic Inherent Immediate Direct Extended Relative INo Offset) 18 Bits) 116 Bits) Clear Branch H I N Z C
ADC X X X X X X II
• II II II
ADD X X X X X X II
• II II II
AND X X X X X X
•• II II
•
ASl X X X X
•• II II II
ASR X X X X
•• II II II
BCC X
•••• •
BClR X
•••• •
BCS X
•••• •
BEO X
•••• •
BHCC X
•••• •
BHCS X
•••• •
BHI X
•••• •
BHS X
•••• •
BIH X
••••
••••
•
•

•
Bil X
BIT X X X X X X
•• II II
•
BlO X
•••• •
BlS X
•••• •
BMC X
•••• •
BMI
•••• •
BMS
• • • •• •
BNE
••• •
BPl
•••• •
BRA
•••• •
BRN
•••• •
BRClR X
•••• II
BRSET X
•••• II
BSET X
•••• •
BSR X
•••• •0
Cll X
••••
Cli X
• 0 •0 •1 •
ClR X X X X
•• •
CMP X X X X X X
•• II II II
COM X X X X
•• II II 1
CPX X X X X X X
•• II II II
DEC X X X X
•• II II
•
EOR X X X X X X
•• II II
•
INC X X X X
•• II II
•
JMP X X X X X
•••• •
JSR x X X X X
•••• •
lOA X x X X X X
•• II II
•
lOX X X X X X X
•• II II
•
lSl X X X X
••0 II II II
lSR X X X X
•• II II
NEO X X X X
•• II II II
NOP X
•••• •
ORA X X X X X X
•• II II
•
ROl X X X X
•• II II II
RSP X
CondItIOn Code Symbols
•••• •
H Half Carry (From BIt 3) C Carry I Borrow
I Interrupt Mask /I Test and Set If True, Cleared OtherwIse
N NegatIVe (SIgn BIll • Not Affected
Z Zero

4·211
 MC6805R2

TABLE 8 - INSTRUCTION SET (CONTINUED)

Addressing Modes Condition Code

Bit Bit
Indexed Indexed Indexed Set! Test 80
Mnemonic Inherent Immediate Direct Extended Relative (No Offset) (8 Bits) (16 Bits) Clear Branch H I N Z C
RTI X ? ? ? ? ?
RTS X
•• • • •
SBC X X X X X X
•• 1\ 1\ 1\
SEC X
•••• 1
SEI X
• ••
1
•
STA X X X X X
•• 1\ 1\
•
STX X X X X X
•• 1\ 1\
•
SUB X X X X X X
•• 1\ 1\ 1\
SWI X
• ••
1
•
TAX X
•• • • •
TST X X X X
•• 1\ 1\
•
TXA X
•••• •

•
ConditIOn Code Symbols
H Half Carry I From Bit 3) C Carry/Borrow
I Interrupt Mask fI Test and Set If True, Cleared Otherwise
N Negative (Sign Bill • Not Affected
Z Zero ? Load CC Register From Stack

4-212
 s:

Bit Meni ulation Branch

TABLE 8 -

Read/Modify/Write
M6805 FAMILY OPCODE MAP

Control Register JMemory

i
::c
r-.J
L~I
I.
BTB
~ , 7
..., ,
C

4
R
rJi.
BRA'
6
01
001,
, 4
INH A
4
01 ..
3 4
INHIXI
5
0101
3 7
IXl
o,~o
6 6
IX
7
0111
, 9
INH
8
'''' 9
.
I H
,,
9
2
IMM
A
1010
2 4 3 I'
OIR
B
1011
4
EXT
C
11 . .
1X2
0
6
1101

SUB ,x,
, I'
11
E
1110
SUB 4
4
IX
F
1111
SUB 3
H~t:a:
0
~ BRSEl~B I 2 BSE~~e NEGX RTI SUB SUB
DIR I 3 SUBEXT
NEGA
10 , 7 , 4
Rl
3
12 NEG
DIR I INH 1 INH
2 NEG 1X1 1 NEG IX
1
6
INH
6 2
IMM
2 4 3
CMP
4 , 6
CMP
5 ,
12
CMP
IXl
4
1
4
CMP
IX
3
0000

1
1 BRClRO BClRO BRN ATS CMP CMP
0001 3 BTB
'SASET1'
2
7
BSe
,
2
4
REl
3
1 INH 2
2
IMM 2
7 , DIR 3
3
EXT
4 , 3
6 5,
IX2 2
,
IXI I
4
IX
3
rool
2
I 2 BSE~le SBC SBC SBC SBC SBC SBC 2
0010 3
10
BTB
5 7 5 ,
BHIREL
3 6 5 4 3 4 3 7 6 6 , 11 10 ,
2 IMM 2
2 4
DIR 3
3 5
EXT
, 3
6 ,,
IX2 2
,
IXI 1
4
IX 0010

3
3 BRClRl BClRl BlSREL COMA COM~H COMJX1 COM SWI CPX CPx CPX CPX CPX CPX
0011 3
10
BTB
5
2
7
Bse
5 , 3
.. .2. COM IR
6 , 1
4
I
3
1
4 3 7 6
1
6
IX
, 1 INH
,
2 IMM 2
2 4
DIR 3
3
EXT
4 , 3
6
IX2
5
2
5
IXI
4
1
4
AND
IX
3
0011

4
4 BRSET2 I , BSE~~c BCC lSRA lSRX lSR lSR AND AND AND AND
.'00 3
10
BlB
5 7 5
2
4
Rl
3
2 LSR01R
1 INH 1 INH IXI 1 IX
,
2 IMM 2
2 4
DIR
13 AND
3 5
EXT
4
3
6
IX2
5
2
5
IXI
4
1
4
BIT
IX
3
0100

3BRCl:1B ! 2 BCl~!c
5 BCS BIT BIT BIT BIT 5
0101
10 , 7 , 2
4
Rl
3 6 , 4 3 , 3 7 6 6 5 , IMM
2 4
DIR I 3
3 5
EXT
, 6 ,
IX2
2 BIT
5
IXI
4
1
4
IX
3
0101

0110
6
3
BRSET3
10 ,
BTS 2
7
BSE~~e
, 2
4
BNE
Rl
3
,
6
ROR
,
IR 1
4
RORA
INH 1
3
RORX
,
INH
3 7
ROR IX1
6
1
6
ROA
IX
, 2 2
, lOA
IMM 2
lOA
, DIR 3
lOA
EXT
4 6 , 3
7
lOA
IX2
6
2
6
lOA
,,
IXI 1
LOA
IX
4
6
0110

7 3BRCl~,3s ,BCl~~c BEQ ASR ASAA ASRX ASR ASR TAX STA STA STA STA STA 7
0111
10 , 7 , 2
4
Rl
3
2
6
DIR
, 1
4
INH 1
3 4
INH
3 7
IXI
6
1
6
IX
5 ,
1 INH
2 2 2
2 , DIR
3 ,3 EXT, 3
6
IX2
5 ,
2 ,
'Xl 1
4
IX
3
0111

, , 8HC~Fl
8SE~~c
,,
8 lSl lSlA lSlX lSl lSl ClC EaR EOR EaR EaR EaR EaR 8
~
1000
10 ,
3 8RSEl1 ! ,
7 3
2
6
DIR
5 ,
1 INH 1
3 4
INH
3 7
IXI
6
1
6
I
, 2
INH
2 2
IMM 2
2 4
DIR
3 ,
3 EXT
4
3
6 , IX3
IX2
5
IXI
4
1 1000

N
9 BRClR4 2 BCl~ic BHCS ROl
,
AOlA AOlX
,
ROl ROl SEC
, ADC ADC ADC
,
ADC ADC
, , IX
ADC 9
.... 1001

1{~0
3
10
STS
5 7

13BRSEl.? I ,BSE~~e
5 ,
2

BPl
REL
3
2
6
, DEC
DIR
5
1 INH 1
DECA
3
INH
DECX
3
2
7
DEC
IXI
6
1
6
DEC
IX
5
1
2
CLI
INH
2 2
ORA
IMM 2
2 4
ORA'
DIR 3

ORA
EXT
ORA
3
6
ORA
IX2
ORA
5
2
5
IXI 1 1001

A
(.)
10 5 7 5 , REl
3
DIR 1 INH 1 INH 2 IXI 1 IX 1 INH
2
2 IMM 2
2
DIR
3
3
, ADDIX2 2 IXI , IX
EXT 3
5 5 4
1 1010

B BRClR5 BClR5 BMI SEI

, ADD ADD ADD 6 ADD ADD B !
1011 3 STS
'~RSET6'
2
7
sse
, ,
2 REL
3 6 , 4 3 , 3 7 6 6 , 1
2
INH
2
IMM 2
3
DIR
, ,3 EXT 3 , , IXI
IX2 2
3
5
IX
2 3
1
3
lOll

C 2 BSE~~e BM~EL INC INCA INCX INC INC RSP JMP JMP JMP JMP JMP C
1100 3
1~. '
BTB
7 ,
2
4 3
2
6
DIR
, ,
1 INH
3 ,
1 INH
3
2
7 ,
IXI 1
6
IX
4 ,
1 INH
2 S
2
6 7
DIR
, 3
S
EXT
6
3
9
IX2
7
2 IXI
6
1 IX 1100

0 13BRCl~~ I ,BCl~~c BM~Fl TSTA TSTX TST TST NOP BSR JSR JSR JSR JSR JSR D
,,01
10 , 7 , 4 3
, TST
IR 1 INH 1 INH IXI 1 IX
2
1 INH 2
2
REl 2
2
DIR
4 lOX 3
3
,
EXT
4
3
lOX
IX2 2 IXI
4
1
4
IX
3
1101

E I 2 BSE~~e Bil STOP LOX lOX b lOX lOX E

1110 3 BRSElJs
10 , 7 ,, 2 REl
3 6 , 4 3 , 3 7 6 6 , 1 INH
2 2 2
2 IMM 2 DIR
, 3 EXT
, 3
7
IX2
6
2
6 ,
IXI 1
5
IX
4
111C

1111
F
3
BRClR7
STB 2
BClR7
__~~C;_ -'--
81H
REl 2
ClR
DIR 1
ClRA
INH 1
ClRX
INH , ClR
IXI 1
ClR
IX 1
WAIT
INH 1
TXA
INH
, STX
2 DIR 3
STX
EXT 3
STX
IX2 2
STX
IXI 1
STX
IX
F
1111

Abbreviations for Add...... Modes

INH Inherent LEGEND

IMM Immediate

l(
DIR Direct
r-IF::;...t=+----------::;77' Opcode In Hexadecimal

j
EXT Extended
AEL Relative
BSC Bit Set! Clear ."' ,~,. «MO",,,""", 4 ... ~ Opcode In Binary
BTB Bit Test and Branch MnemOniC .. SUB 0
IX Indexed INa Offsetl Bytes 1 IX 0000
IX1 Indexed, 1 Byte 18-Bnl Offset
IX2 Indexed, 2 Byte 116-B,tI Offset # of Cycles (CMOS Versions I 7 " Address Mode

"'CMOS Versions only

II
 MC6805R2

ORDERING INFORMATION thoroughly checked and the verification form completed,

The information reqUired when ordering a custom MCU IS signed, and returned to Motorola The signed verification
listed below The ROM program may be transmitted to form constitutes the contractual agreement for creation of
Motorola on EPROM(s) or an MOOS disk file the customer mask If desired, Motorola Will program one
To initiate a ROM pattern for the MCU It IS necessary to blank EPROM from the data file used to create the custom
first contact you local Motorola representative or Motorola mask to aid In the verification process
distributor
EPROMs - The MCM2716 or MCM2532 type EPROMs, ROM VERIFICATION UNITS (RVUs)
Ten MCUs containing the customer's ROM pattem Will be
programmed with the customer program (positive logic
sent for program verification These units Will have been
sense for address and data), may be submitted for pattern
made uSing the custom mask but are for the purpose of
generation The EPROM must be clearly marked to indicate
ROM verification only For expediency they are usually un-
which EPROM corresponds to which address space The
marked, packaged In ceramiC, and tested only at room
recommended marking procedure IS Illustrated below
temperature and 5 volts These RVUs are Included In the
mask charge and are not production parts The RVUs are
thus not guaranteed by Motorola Quality Assurance, and
xxx should be discarded after Verification IS completed

FLEXIBLE DISKS
The disk media submitted must be Single-sided, slngle-
denSity, 8-lnch, MOOS compatible flOPPies The customer

I
must write the binary file name and company name on the
disk With a felt-tip pen The minimum MOOS system files as
000 400 well as the absolute binary object file Ifilename LO type of
file) from the M6805 cross assembler must be on the disk An
xxx ~ Customer 10 object file made from a memory dump uSing the ROLLOUT
After the EPROM(s) are marked they should be placed In command IS also acceptable Consider submitting a source
conductive IC carners and securely packed Do not use listing as well as the follOWing files filename LX (EXOR-
styroforam ciser'" loadable format) and filename SA (ASCII Source
Code) These files will of course be kept confidential and are
VERIFICATION MEDIA used 1) to speed up the process In-house If any problems
arise, and 2) to speed up the user-to-factory mterface If the
All original pattern media (EPROMs or Floppy Disk) are user finds any software errOrs and needs assistance qUickly
filed for contractual purposes and are not returned A com- from Motorola factory representatives
puter listing of the ROM code will be generated and returned MOOS IS Motorola's Disk Operating System available on
along with a listing verification form The listing should be development systems such as EXORCisers, EXORsets, etc

4·214
MC6805R2

MC6805R2 MCU ORDERING INFORMATION

Date _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Customer PO Number _ _ _ _ _ _ _ _ _ _ __

Customer Company _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Motorola Part Numbers

Address MC _ _ _ _ _ __
---------------------------------SC
City _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ State _ _ _ _ _ _ _ _ _ _ _ _ _ Z,p _ _ _ __ -----
Country _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Phone _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Extenslon _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Customer Contact Person _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Customer Part Number _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

OPTION LIST
Select the options for your MCU from the followtng itst A
manufacturing mask will be generated from this tnformatlon

II
Timer Clock Source
o Internal ",2 clock
o TIMER Input pm

Timer Prescaler
o 2° (divide by 11 o 2' (divide by 16)
o 2' (divide by 2) o 2' (divide by 32)
o 2' (divide by 4) o 2' (divide by 64)
o 2' (divide by 8) o 2' (divide by 128)

Internal Oscillator Input Port A Output Drive

o Crystal o CMOS and TTL
o Resistor o TTL Only

Low Voltage Inhibit

o Disable
o Enable

Pattern Media IAII other media requlfes pflor factory approval I

o EPROMs (MCM2716 or MCM2532 o Floppy Disk
o Other

Clock Freq _ _ _ _ _ _ _ _ _ _ _ _ __

Temp Range _ _ _ _ _ _ _ _ _ _ _ _ _ DO' to +70'C IStandardl o _40' to +85'C· 0 _40' to + 125'C·

*ReqUires prior factory approval

Marking Information 112 Characters Maxlmuml

Tllle _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

S,gnature _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

4·215
 ® MOTOROLA MC680ST2

Advance Information
HMOS
8-BIT MICROCOMPUTER UNIT WITH PLL LOGIC IHIGH DENSITY
N"CHANNEL. SILICON-GATE
The MC6805T2 Microcomputer Unit I MCU) with PLL logic IS a DEPLETION LOAD)
member of the M6805 Family of low-cost single-chip microcomputers 8-BIT
This 8-bit microcomputer contams a CPU, on-chip CLOCK, ROM,
RAM, 1/0, TIMER, and the PLL logic for an RF synthesizer It IS design- MICROCOMPUTER
ed for the user who needs an economical microcomputer with the WITH PLL LOGIC
proven capabilities of the M6800-based mstructlon set, as well as the
necessary logic reqUired for frequency synthesIs applications A com-
panson of the key features of several members of the M6805 Family of
microcomputers is shown on the last page of this data sheet The
following are some of the hardware and software highlights of the
MC6805T2 MCU

HARDWARE FEATURES:
• 8-Blt Architecture
• 64 Bytes of RAM

II • Memory Mapped 1/0

• 2508 Bytes of User ROM
• Timer StartlStop and Source Select
• 19 TTLICMOS Compatible BidirectIOnal 1/0 Lines 18 Lines
are LED Compatible)
• On-Chip Clock Generator P SUFFIX
• Zero-Crossing Detection PLASTIC PACKAGE
• Self-Check Mode CASE 710
• Master Reset
• Complete Development System Support on EXORciser'"
• 5 V Single Supply
• 14-Blt Binary Vanable D,v,der
• 10-Stage Mask-Programmable Reference D,v,der
• Three-State Phase and Frequency Comparator FIGURE 1 - PIN ASSIGNMENTS
• SUitable for TV Frequency Synthesizers
SOFTWARE FEATURES:
Similar to M6800
"
Byte EffiCient Instruction Set
Vss RESET
Easy to Program
True Bit Manipulation INT PAl
Bit Test and Branch Instructions PA6
VCC
Versatile Interrupt Handling
EXTAL PA5
Versatile Index Register
Powerful "indexed Addressing for Tables XTAL PA4
Full Set of Conditional Branches NUM PA3
Memory Usable as Reglstersl Flags
q,COMP 22 PA2
Single Instruction Memory ExamlnelChange
10 Powerful Addressing Modes P-CO/TIMEA 21 PAl
All Addressing Modes Apply to ROM, RAM, and 1/0 PCl PAO
USER SELECTABLE OPTIONS:
PC2 10 PBl
• Internal8-Blt Timer with Selectable Clock Source IExternal Timer
Input or Internal Machine Clock) fin 11 18 PB6
• Timer Prescaler OptIOn 17 Bits 2N) PBO 12 17 PB5
• 8 Bidirectional 1/0 Lines with TTL or TTL/CMOS Interface OptIOn PBl 13 PB4
• 4 Vectored Interrupts; Timer, Software, and 2 External
PB2 14 PB3

4-216
MC6805T2

FIGURE 2 - MC6805T2 HMOS MICROCOMPUTER BLOCK DIAGRAM

PAO PCO TIMER

PAl Accumulator PCI
Port PA2 Data Data Port
A PC2 Pan
A PAJ Olr Otr C
1/0 PA4 C
Reg Index Reg Reg
1/0
Lmes PA5
PAS Register Lines
PA7 X
Condition
Code
Register
CC
CPU
Stack
POinter
SP
PBO Program Frequency
Port PBI Counter r~:;;;;;;;;:;;;:-l--------c Input
B
PB2 Port Data High PCH fin
PB3 B Olr ALU
1/0 PB4 Reg Reg Phase
Lines PB5

•
PBS Comparator
PB7 ",CaMP

Self-Check
ROM

MAXIMUM RATINGS
Rating Symbol Value Unit This device contains circuitry to protect the
Inputs against damage due to high 'italic
Supply Voltage VCC -03to +70 V
voltages or electnc fields, however, It IS ad~
Input Voltage V ln -03to +70 V Vised that normal precautions be taken to
Operating Temperature Range TA o to + 70 'c aVOid application of any voltage higher than
maximum rated voltages to this hlgh-
Storage Temperature Range Tstg -55 to + 150 'c Impedance circuit For proper operation It IS
recommended that V In and Vout be con~
THERMAL CHARACTERISTICS strained to the range VSSS(V In or V out )
Characteristic Symbol Value Unit sVCC Reliability of operation IS enhanced If
Thermal Resistance unused Inputs are tied to an appropriate logiC
Plastic 120 voltage level Ie 9 • eltner VSS or VCCI
Ceramic 9JA 50 'C/W
Cerdlp 60

POWER CONSIDERATIONS
The average chip-Junction temperature. T J. In 'c can be obtained from
T J=TA+ (PO-BJA) (1)
Where
TA-Amblent Temperature. °c
BJA- Package Thermal ReSistance. JunctlOn-to-Amblent. °C/W
PO- PINT + PPORT
PINT-ICC x VCC. Watts - Chip Internal Power
PPORT-Port Power DISSipation. Watts - User Determined
For most applicatIOns PPORT~ PINT and can be neglected PPORT may become Significant If the deVice IS configured to
drive Darlington bases or sink LED loads
An approximate relationship between Po and TJ Ilf PPORT IS neglected) IS
PO= K+ (T J + 273°C) (2)
SolVing equations 1 and 2 for K gives.
K = PO-IT A + 273°C) + BJAoP 0 2 (3)
Where K IS a constant pertaining to the particular part K can be determined from equation 3 by measunng Po (at eqUilibrium)
for a known T A USing thiS value of K the values of Po and T J can be obtained by solVing equations (1) and (2) Iteratively for any
value of TA

4·217
 MC6805T2

SWITCHING CHARACTERISTICS (VCC= 525 Vdc -+ 05 Vdc VSS = GND TA = 0 to 70·C unless otherwise notedl
Characteristics Symbol Min Typ Max Unit
Oscillator Frequency fosc 04 - 42 MHz
Cycle Time (4lfoscl tcyc 095 - 10 ~A
INT and TIMER Pulse Width tWH,tWL t cyc +250 - - ns
RESET Pulse Width tRWL t cyc +250 ns
f1E:SE~ Delay Time (External Capacllance-l 0 ~Fl tRHL 100 ms
Input Frequency fin 1 - 16 MHz
Input Frequency Rise Time at fin tlNR - - 20 ns
Input Frequency Fall Time at fin tlNF - 20 ns
Duty Cycle of fin and External Input on EXTAL - 40 - 60 %
Injection Pulse Active Time tarr 70 ns
TIQj Zero-Crossing Detection Input Frequency (for ± 5° Accuracy flNT 003 10 kHz

ELECTRICAL CHARACTERISTICS (VCC=5 25 Vdc ±O 5 Vdc, VSS=GND, TA=O to 70·C unless otherwise notedl

•
Characteristic Symbol Min Typ Max Unit
Input High Voltage
RESET (4 75sVCC,s5 751 40 - VCC
(VCC<4751 VCC-O 5 -, VCC
INT (4 75,sVCC,s5 751 VIH 40 VCC V
,
(VCC<4751 VCC-O 5 VCC
All Other Except fin 20 - VCC
Input High Voltage <l>COMP
Normal Mode - - VCC
VIH
Self-Check Mode - 90 150 V
Input Low Voltage
RESET -03 -, 08
INT VIL -03 15 V
All Other Except fin -03 - 08
iiiiT Zero-Crossing Input Voltage, through a Capacitor VINT 20 - 40 Vac p-p
Internal Power DIssipation - No Port Loading,
VCC=575 V, TA=O·C PINT - 400 - mW
Input CapaCItance
EXTAL - 25 -
All Others Cin - 10 - pF
AC Coupled Input Voltage SWing VFIP 05 12 - Vac p-p
Input Current (VIH = VCCI IFH - - 40 ~A
Ouput Low Current (VOL = 1 0 V) ICML - 300 - ~A
Output High Current (VOH- VCC-l V) ICMH - 200 - y.A
Leakage Current (V ,n - VCC) IOFF - 2 - nA
RESET HysteresIs Voltage (See Figures 11 and 121
"Out of Reset" VIRES+ 21 - 40 V
"Into Reset" VIRES- 08 - 20
Input Current
TIMER (V,n=O 4 VI - - 20
INT (VIn=O 4 VI - 20 50
EXTAL (V In =2 4 V to VCC Crystal Option I 1m - - 10 ~A
_ _ (V ,n = 0 4 V Crystal OptIOn) - - -1600
RESET (VIn=O 8 V) -40 - -50
(External Capacttor Charging Current!

'Due to Internal biaSing, thiS Input (when unusedl floats to approximately 2 0 V

4-218
MC6805T2

PORT ELECTRICAL CHARACTERISTICS IVCC= +525 Vdc ±O 5 Vdc, VSS= GND, TA=O' to 70'C unless otherwise noted I

Characteristic Symbol Min Typ Max Unit

Port A with CMOS Drive Enabled
Output Low Voltage, ILoad= 16 mA VOL - - 04 V
Output High Voltage, ILnad- -100 ~A '!illi 24 - - V
Output High Voltage, ILoad= -10 ~A VOH 35 - - V
Input High Voltage, ILoad= -300 ~A Imaxl VIH 20 - VCC V
Input Low Voltate, ILoad= -500 ~A Imaxl VIL 03 - 08 V
HI-Z State Input Current IV",=2 0 V to VCCI IIH -- - -300 ~A
HI-Z State Input Current IV", = 0 4 VI II - - -500 ~A
Port B
Output Low Voltage, ILoad=3 2 rnA VOL - - 04 V
Output Low Voltage, ILoad = 10 mA ISlnkl VOL - - 10 V
Output High Voltage, ILoad- -200 ~A VOH 24 - - V
Darlington Current Drive (Source), VO= 1 5 V IOH -10 - -10 mA
Input High Voltage VIH 20 -
VCC V
I nput Low Voltage VIL 03 - 08 V
HI-Z State Input Current ITSI - 2 20 ~A

•
Port C and Port A with CMOS Drive Disabled
Output Low Voltage, ILoad= 16 rnA VOL - - 04 V
Output High Voltage, ILoad- -100 ~A VOH 24 - V
Input High Voltage VIH 20 -
VCC V
Input Low Voltage VIL 03 - 08 V
HI-Z State Input Current ITS I - 2 20 ~A

FIGURE 3 - TTL EQUIVALENT TEST LOAD FIGURE 4 - CMOS EQUIVALENT TEST LOAD FIGURE 5 - TTL EQUIVALENT TeST LOAD
(PORT BI (PORT AI (PORTS A AND CI

VCC=575V
Test MMD6150
POint or Equlv 297 kll
TestPolnt~

I 30 pF IT otal1 30 pF
1T0tail
24 kll MMD7000
or Equlv

C = 40 pF !Totall

SIGNAL DESCRIPTION oscillator Lead length and stray capacitance on these two
The Input and output signals for the MCU, shown In pinS should be minimized Refer to INTERNAL
Figure 1, are described In the following paragraphs OSCILLATOR for recommendations about these pinS

VCC AND VSS - Power IS supplied to the MCU uSing fin - The high frequency digital Input to the variable
these two pins VCC IS power and VSS IS the ground con- divider portion of the on-chip frequency synthesizer IS on the
nection fin pin The reference frequency for the phase lock loop IS
divided down from the crystal oscillator. Refer to the PHASE
INT - ThiS pin provides the capability for asynchronously LOCK LOOP section for details on the frequency synthesizer
applYing an external Interrupt to the MCU Refer to INTER- features
RUPTS for additional information.
cj>COMP - ThiS three-state output IS the result of compar-
XTAL AND EXTAL - These PinS provide control Input for 109 the mternal reference frequency to the vanable divider
the on-chip clock oscillator CirCUit A crystal or an external signal Refer to PLL for details In Self-Check, cj>COMP IS
signal can be connected to these pins to provide the Internal raised to .. 9 V

4-219
 MC6805T2

Rem - This Pin allows resetting of the MCU at times The MCU reserves the first 16 memory locations for I/O
other than the automatic resetting capability already In the features, of which 10 have been Implemented. These loca-
MCU. Refer to RESETS for additional information tions are used for the ports, the port DDRs, the timer, and
the PLL registers.
NUM - ThiS Pin IS not for user application and must be Sixty-four bytes of user RAM are provided Of the 64
connected to VSS. bytes, 31 bytes are shared With the stack area The stack
must be used With care when data shares the stack area
INPUT/OUTPUT LINES (PAo-PAl, PBo-PBl, PCO-PC21 The shared stack area IS used dUring the processing of
- These 19 lines are arranged Into two 8-bIt ports (A and BI Interrupt and subroutine calls to save the processor state
and one 3-blt port (CI All lines are programmable as either The register contents are pushed onto the stack In the
Inputs or outputs under software control of the data direc- order shown In Figure 7 Since the stack pOinter decrements
tion registers. Refer to INPUT/OUTPUTS for additional in- dUring pushes, the low order byte (PCL) of the program
formation The PCO/TIMER pin also serves as an external in- counter IS stacked first, then the high order four bits (PCH)
put to the Internal timer Refer to the TIMER section for in- are stacked ThiS ensures that the program counter IS loaded
formation on the timer modes correctly follOWing pulls from the stack, since the stack
pOinter Increments when It pulls data from the stack A
MEMORY subroutine call results In only the program counter (PCH,
The MCU memory IS configured as shown In Figure 6 The PCL) contents being pushed onto the stack, the remaining
MCU IS capable of addreSSing 4096 bytes of memory and 1/0 CPU registers are not pushed.
registers With ItS program counter The MCU has Im-
plemented 2698 of these memory locations ThiS consists of.

II
2508 bytes user ROM, 116 bytes self-check ROM, 64 bytes of REGISTERS
user RAM, 6 bytes of port I/O, 2 timer registers, and 2 PLL The MCU has five registers available to the programmer
registers The user ROM IS split Into four areas. The first area They are shown In Figure 8 and are explained In the follOWing
beginS at memory location $080, which allows the user to paragraphs
access ROM locations utiliZing the direct and table look-up
Indexed addreSSing modes The second user ROM area ACCUMULATOR (AI - The accumulator IS a general pur-
begins at memory location $100 The last eight user ROM pose 8-blt register used to hold operands and results of
locations, at the top of memory, are for the Interrupt vectors arithmetiC calculations or data manipulations

FIGURE 6 - MC6806T2 MCU ADDRESS MAP

7 o 7 6 5 4 3 2 o
0 PortA $000
1/0 Ports, RAM $000
PLL, Timer
1 Port 8 $001
$07F
Page Zero
User ROM
$080 2 1 1 1 1 1 I PortC $002

(128 bytes) 3 NOT USED $003

\OFF
$100
User ROM
4 PortA ODR $004'

2047
(1792 bytes) \
$7FF
5 Port B DDR $006'
2048 $800
6 NOT USED I Port C DDR $006'

7 NOT USED $007

Not Used
8 Timer Data Register $008
(1344 bytes)

9 Timer Control Register $009

10 Vanable D,v,der LSB $OOA

3391 $D3F
3392
ROM
$040 11 1 1 I Vanable D,v,der M S B $OOB
1580 bytes) 12 NOT USED $OOC
3971 $F83
(52 bytes)
3972 Self-Check $F84 83 $03F
$040

\
ROM User RAM
(116 bytes) (84 bytes)
4087 $FF7
4al8 $FFS
Stack
Interrupt Vectors (S bytes)
(31 bytes ;aXlmum)
4096 $FFF
127 $07F

'Caullon Data Dlfectlon Register !DORs) are wnte-only, they read as $FF

4·220
MC6805T2

FIGURE 7 - INTERRUPT STACKING ORDER FIGURE 8 - PROGRAMMING MODel

5 4 Pull o
I
0
CONOITION A Accumulator
n 4 1 1 1 CODE REGISTER n ·1
o
n ·3 ACCUMULATOR n -2 L.._ _ _ _ _x_ _ _ _...I1 Index Register

r1 -2 INDEX REGISTER n -3 11 0
---I1
.:..p.;:C:.;H_...L_ _ _ _-:...PC::L=-_ _ Program Counter
I
LI_ _

n ·1 1 1 1 1 PCW n -4
1 11 5 4
SP Stack Pomter
PCL" n -5

Push
Condilion Code Register
• For subroutme calls only PCH and pel are stacked
Carry I Barrow

Zero
' - - - - Negative
' - - - - - - Interrupt Mask

INDEX REGISTER (X) - The mdex register IS an B-blt

register used for the mdexed addressmg mode It contams an
' - - - - - - - Half Carry

bit IS set, the mterrupt IS latched and IS processed as soon as

the mterrupt bit IS reset
II
B-blt value that may be added to an Instruction value to
create an effective address The Index register can also be Negative (N) - Used to Indicate that the result of the
used for data manipulations uSing the read/ modify/write In- LAST arithmetiC, logical, or data manipulation was negative
structions The Index register may also be used as a tem- I bit 7 m result equal to a logical one)
porary storage area
Zero IZ) - Used to indicate that the result of the LAST
PROGRAM COUNTER (PC) - The program counter IS a arithmetiC, logical, or data manipulation was zero
12-blt register that contains the address of the NEXT Instruc-
tion to be executed Carry/Borrow (C) - Used to indicate that a carry or bor-
row out of the arithmetiC logiC Unit (ALU) occurred dUring
STACK POINTER (SP) - The stack pomt IS a 12-bit the LAST arithmetiC operatIOn This bit IS also affected dur-
register that contams the address of the next free location on Ing bit test and branch instructions plus shifts and rotates
the stack Initially, the stack pomter IS set to location $07F
and IS decremented as data IS bemg pushed onto the stack TIMER
and mcremented as data IS bemg pulled from the stack The The MCU timer CirCUitry IS shown In Figure 9. The 8-blt
seven most-significant bits of the stack pOinter are per- counter may be loaded under program control and IS
manently set to 0000011 DUring a MCU reset or the Reset decremented toward zero by the clock Input (prescaler out-
Stack POinter (RSP) InstructIOn, the stack pOinter IS set to put) When the timer reaches zero the timer interrupt request
locatIOn $07F Subroutmes and mterrupts may be nested bit Iblt 7) In the Timer Control Register ITCR) IS set. The
down to locatIOn $061 (31 bytes maximum) which allows the timer mterrupt can be masked (disabled) by settmg the timer
programmer to use up to 15 levels of subroutme calls interrupt mask bit (bit 6) In the TCR The mterrupt bit (I-bit)
m the Condition Code Register also prevents a timer inter-
CONDITION CODE REGISTER (CC) - The condition rupt from being processed The MCU responds to thiS Inter-
code register IS a 5-blt register In which four bits are used to rupt by saving the present CPU state m the stack, fetchmg
indicate the results of the mstructlon Just executed. These the timer Interrupt vector from locations $FFB and $FF9 and
bits can be Individually tested by a program and specific ac- executmg the mterrupt routme, see INTERRUPT section
tion taken as a result of their state Each mdlvldual condition The timer clock mput IS established via bit 5 ITCR5) In the
code register bit IS explamed In the followmg paragraphs Timer Control Register When thiS bit IS set high, logical one
I external mode), the timer clock source IS the PCO/TIMER
Half Carry I H) - Set dUring ADD and ADC instructIOns to pm. In thiS mode a mask optIOn IS used to select either. a) the
mdlcate that a carry occurred between bits 3 and 4 gated 4>2 With PCO or b) the positive transition on
PCOITIMER as timer clock source ThiS allows eaSily per-
Interrupt (I) - ThiS bit IS set to mask (disable) the timer formed pulse Width or pulse count measurements. When
and external Interrupt (lNT). If an Interrupt occurs while thiS TCR5 IS low, logical zero, the timer clock source IS the mter-
nal4>2.

4-221
 MC6805T2

FIGURE 9 - TIMER BLOCK DIAGRAM

q,2
I l n t e m a nr-
B -,
I I
I
I I
Pm ~_.J
PCG/TiMER
TCR5
TImer
TCR4 Interrupt
Mask

r---,
I I
I I
I I Clock
L. ___ J
Manufacturing
Input
Mask OptIOn

Internal Data Bus

• Bit 4 In the Timer Control Register (TCR41 disables the

timer clock source when set to logical one
Tt\e timer continues to count past zero, failing through to
$FF from zero, and then continuing to count Thus, the
counter can be read at any time by reading the Timer Data
Register ITDRI. ThiS allows a program to determine the
length of time since a timer Interrupt has occurred, and not
disturb the counting process
Input, as shown In Figure 12, will proVide suffiCient delay.
See Figure 17 for the complete reset sequence.

INTERNAL OSCILLATOR
The Internal OSCillator CirCUit has been deSigned to require
a minimum of external components The use of a crystal or
an external signal may be used to drive the Internal OSCillator
The different connection methods are shown In Figures 13
At Powerup or Reset, the prescaler and counter are and 14 The crystal specifications are given In Figure 15.
Initialized with all logical ones; the timer Interrupt request bit The crystal OSCillator startup time IS a function of many
Iblt 71 IS cleared; the timer Interrupt mask bit Iblt 61 IS set; the variables crystal parameters (especially RsI, OSCillator load
external timer source bit Iblt 51 IS cleared and the timer capaCItances, IC parameters, ambient temperature, and sup-
disable bit Iblt 41 IS cleared ply voltage To ensure rapid OSCillator startup, neither the
crystal characteristics nor the load capacitance should ex-
SELF-CHECK ceed recommendallons.
The self-check capability of the MCU provides an Internal
check to determine If the port IS functional. Connect the INTERRUPTS
MCU as shown In Figure 10 and mOnitor the output of Port C The MCU can be Interrupted three different ways through
bit 3 for an OSCillation of approximately 7 Hz A 9-volt level on the external Interrupt I INTI Input pin, the Internal timer inter-
the ",COMP input, pin 7, energizes the ROM-based self- rupt request, or the software Interrupt Instruction (SWII.
check feature The self-check program exercises the RAM, When any Interrupt occurs, processing is suspended, the
ROM, timer, Interrupts, and 1/0 ports present CPU state IS pushed onto the stack, the Interrupt bit
III In the ConditIOn Code Register IS set, the address of the
RESETS Interrupt routine is obtained from the appropriate Interrupt
The MCU can be reset two ways' by the external reset In- vector address, and the Interrupt routine is executed. Stack-
put IRESETI and dUring power up time. See Figure 11 Ing the CPU registers, setting the I-bit, and vector fetching
The Internal CirCUit connected to the ~ pin consists requires a total of 11 tcyc periods for completion
of a Schmitt trigger which senses the RESET line logiC level A flowchart of the Interrupt sequence IS shown In Figure
The Schmitt trigger proVides an Internal reset voltage If It 16 The Interrupt service routine must end With a return from
senses a logical 0 on the RESET pin. DUring power up, the Interrupt (RTII Instruction which allows the MCU to resume
Schmitt trigger sWitches on (removes resetl when the processing of the program prior to the interrupt (by unstack-
RESET pin voltage rises to VIRES +. When the RESET Pin Ing the prevIous CPU statel. Table 1 proVides a listing of the
voltage falls to a logical 0 for a period longer than one t cyc , Interrupts, their PriOrity, and the address of the vector which
the Schmitt trigger sWitches off to provide an Internal reset contains the starling address of the appropriate Interrupt ser-
voltage The "switch off" voltage occurs at VIRES _. A vice routine The Interrupt priOrity applies to those pending
typical reset Schmitt trigger hysteresIs curve IS shown In when the CPU IS ready to accept a new Interrupt. RESET is
Figure 12. listed In Table 1 because It IS treated as an Interrupt.
Upon power up, a delay of tRHL IS needed before allOWing However, It IS not normally used as an Interrupt When the
the reset Input to go high. This time allows the Internal clock Interrupt mask bit In the Condition Code Register IS set the
generator to stabilize. Connecting a capacitor to the RES ET Interrupt IS latched for later Interrupt execution

4-222
MC6805T2

FIGURE 10 - SELF·CHECK CONNECTIONS

.2.. iNT PAl

21

MC6805T2 26
PA6
10"F 28 25
r-1 CL
R'E'SEi' PA5

PA4 1!..-
4 23
~
-- ~
EXTAL PA3
PA2
22

T 5
XTAL PAl 21

PAO ~
7
+9V ",COMP
PBl .l2....-.
6 18
NUM PB6
'CC
~ 17
- PB5

II
16
PB4
J.72D 8
PCO/TIMER PB3 .!L-.
J.7..iX;. 9
PCl PB2
14

.
J.7..00 10
PC2 PBl
13

VCC= Pin 3
- 11
fin PBO
12

VSS= Pin 1

FIGURE 11 - POWER AND R'E'SEi'TIMING

5V
VCC
OV _ _ _ _ _ _- J

RESET
Pin
-------r'

Internal
Reset _ _ _ _ _ _ _ _ _ _....

FIGURE 12 - POWERUP RESET DELAY CIRCUIT

TYPical RESET Schmllt Trigger Hysteresis

Out

VCC - :::r:: 1 O"F

of Reset

Part Of
MC6805T2
MCU
InReset L-~~~~I_~-+--- ___
O.BV 2V 4V

4·223
 MC6805T2

FIGURE 13 - CRYSTAL OSCILLATOR FIGURE 14 - EXTERNAL OSCILLATOR

~ 4 EXTAL
External
4 EXTAL
Clock
(See Note) c:J MC6805T2 Input MC6805T2
5 XTAL MCU 5 XTAL MCU

Crystal
External Clock

NOTE. The recommended CL value with a 40 MHz crystal IS 27 pF,

maXimum, Including system distributed capacitance There
IS an Internal capacitance of approximately 25 pF on the
XT AL pin For crystal frequencies other than 4 M Hz, the
total capacitance on each pin should be scaled as the in-
verse of the frequency ratio For example, with a 2 MHz
crystal, use approximately 50 pF on EXTAL and approxl+

•
mately 25 pF on XT Al. The exact value depends on the
MotIOnal-Arm parameters of the crystal used

FIGURE 15 - CRYSTAL MOTIONAL ARM PARAMETERS

AND SUGGESTED PC BOARD LAYOUT

Recommended
Crystal MotIOnal Arm Parameters Cl

n:'C,;3-":.c
AT - Cut Parallel Resonance Crystal
Co~ 7 pF Max
FREO~4 0 MHz @ CL ~24 pF
RS = 50 ohms Max.

(a) (bl

Note Keep crystal leads and CirCUit

connectIOns as short as possible

4·224
MC6805T2

FIGURE 16 - RESET AND INTERRUPT PROCESSING FLOWCHART

l-ll,n CCA)
07F- SP
O-DDA's Stack
CLA INT Logic PC, X, A, CC
FF-Tlmer
7F-Prescaler
7F- TCA

Put FFE on Load PC From

Address Bus SWI FFC/FFD

•
iNT FFA/FFB
Timer FFB/FF9

Fetch
Instruction

Load PC
from
FFE/FFF
Execute
Instruction

TABLE 1 - INTERRUPT PRIORITIES

Interrupt Priority Vector Address INPUT/OUTPUT

mET 1 $FFE and $FFF There are 19 input/outpul pins (The INT pm may also be
SWI 2" $FFC and $FFD polled with branch mstructions to provide an additional Input
INi' 3 $FFA and $FFB pin.! All pins (Ports A, B, and C) are programmable as either
Timer 4 $FF8 and $FF9 Inputs or outputs under software control of the correspond-
mg Data Direction Registers (DDRI. The port I/O program-
*PrlOrity 2 applies when the I-bit In the Condition Code Aeglster IS mmg IS accomplished by writing the corresponding bit In the
set When 1=0, SWI has a Priority of 4, like any other Instruction, port DDR to a logiC "1" for output or a logic "0" for mput.
the Priority of iNi' thus becomes 2 and the timer becomes 3 On Reset all DDRs are Initialized to a logiC "0" state to put
the ports in the Input mode, The port oulput registers are not
mitlallzed on Reset but may be written to before setting the
The external Interrupt IS mternally synchronized and then DDR bits to avoid undefined levels. When programmed as
latched on the falhng edge of INT. A smusoidal input signal outputs, lhe latched output data IS readable as input data,
(fINT maximum) can be used to generate an external mter- regardless of the logiC levels at the output pm due to output
rupt, as shown In Figure 17, for use as a Zero-Crossing loadmg; see Figure 18. When Port 8 IS programmed for out-
Detector. For digital applicatIOns the INT can be driven by a puts, It IS capable of slnkmg 10 mA and sourcmg 1 mA on
digital signal at a maximum period of tlWL each pin.

4-225
 MC6805T2

FIGURE 17 - TYPICAL INTERRUPT CIRCUITS

a- Zero Crossing Interrupt b - Digital SI9nai Interrupt

VCC
AC TTL 47 k
Input (Current
IfINT Max I Limiting) MC6805T2 Level 2 TIiIT MC6805T2
Rs 1 Mil ~---<Q,.--t--I MCU DI9Ital---4t--I
Input
MCU
AC Input~ O.lI'F
(tlWL MaXimum
10 Vpp
Penod)

lJ

I Data
FIGURE 18 - TYPICAL PORT 1/0 CIRCUITRY

Direction Register
Bit-

Latched
Output
Data
Sit

To Timer
for PCO/TIMER Pin
Data
Direction Output Input
Register Data Output To
Bit B~ State MCU
1 0 0 0
1 1 1 1
0 X 3-State"" Pin

-DDR IS a write-only register and reads as all "s

""Ports A (with CMOS drive disabled), S, and C are three-state ports Port A has opllOnal Internal pullup deVices
to provide CMOS dnve capability See Electncal CharacterIStics tables for complete Information

4·226
MC6805T2

All Inputloutput lines are TTL compatible as both Inputs used to Initialize the data registers and avoid undefined out-
and outputs Ports Band C are CMOS compatible as Inputs puts, however, care must be exercised when usmg readl
Port A may be made CMOS compatible as outputs with a modlfy/wnte Instructions smce the data read corresponds to
mask option Figure 19 provides some examples of port con- the pin level If the DDR IS an Input (0) and corresponds to the
nections The address map In Figure 6 gives the address of latched output data when the DDR IS an output (1)
the data registers and DDRs The register configuration IS
shown m Table 2
Caution PHASE LOCK lOOP (PLL)
The corresponding DDRs for ports A, B, and Care wnte-
only registers (registers at $004, $005, and $006) A read The Pll section consists of a 14-bIt bmary vanable
operation on these registers IS undefined Smce BSET and divider, a fixed 10-stage divider, ~ digital phase and fre-
BClR are read/modlfy/wnte functions, they cannot be used quency comparator with a three-state output, and circUitry
to set or clear a DDR bit (all "unaffected" bits would be set) to aVOid "backlash" effects In phase lock conditions
It IS recommended that all DDR bits m a port be wntten uSing With a sUitable high-frequency prescaler and an active
a smgle-store Instruction mtegrator the user can easily establish a frequency syn-
The latched output data bit (see Figure 18) may always be theSizer system dnvmg a voltage controlled OSCillator, as
wntten Therefore, any wnte to a port wntes all of ItS data shown m Figure 20 The equations governmg the Pll are
bits even though the port DDR IS set to mput ThiS may be given In Figure 21

TABLE 2 - MCU REGISTER CONFIGURATION

111 Wnte Only, reads as all 1's

PORT DATA DIRECTION REGISTER IDDRI

o II
121 1= Output, 0= Input Cleared to 0 by Reset
131 Port A Addr= $004
Port B Addr= $005
Port C Addr=$006

PORT DATA REGISTER

7 o
Port A Addr= $000
Port B Addr = $001
Port C Addr = $002

TIMER CeNTROL REGISTER ITCRI

$009 7 6 5 4 3 o
TCR7 - Timer Interrupt Request Status Bit Set when
TOR goes to zero, must be cleared by software
Cleared to 0 by Reset
TCR6- Timer Interrupt Mask Bit 1 = timer Interrupt
masked Idlsabledl Set to 1 by Reset
TCR5- External Timer Source 1 = External, 0= Inter-
nal Cleared to 0 by Reset
TCR4- Disable Timer 1 = Timer Source Disconnected,
0= Timer Input Enabled Cleared to 0 by Reset
TCR Bits 3,2, 1, and 0 read as 1's Inot usedl

TIMER DATA REGISTER ITORI

$OIl8 7 o
~----------------------~
MSB LSB

4-227
 MC6805T2

FIGURE 19 - TYPICAL PORT CONNECTIONS

a. Output Modes

PA7 27 ICMOS Loadsl

PB7 19
PA6 26 ~ IO=HFE"lb

-
PA5 25 PB6 18
PA4 24 II TTL Loadl PB5 17
-Ib
PA3 23 PB4 16
16mA 10mA
PA2 PB3 15 2N8386 ITYPlcal!
22
PAl 21 PB2 14
PAO PBl 13
20
PBO 12
-
Port A, Bit 7 Programmed as Output, OrlYlng
CMOS Loads and Bit 4 Orlvlng one TTL Load Port B, Bit 6 Programmed as Output, DrlYlng
Directly luslng CMOS output optlonl Darlington-Base Directly.
+V + V
PB7 19
PB6 18

•
PB5 17
PB4 16

- If If
PB3 15 lamA CMOS
lmaxl PC2 10 Inverters
PB2 14 MCI4049/MCI4069
PBl 13
PCl 9 (TYPical)
PBO 12 PCO 8
_10mAlmaxl

Port B, Bit a and Bit 1 Programmed as Output, Port C, Bits 0·3 Programmed as Output, DnY'
DrlYlng LEDs Directly Ing CMOS Loads, USing External Pullup
ReSistors

b. Input Modes

PA7 PB7
PA6 PB6

MC74LS04
. 25
24
PA5
PA4
MC74LS04
or
17
16
PB5
PB4
ITYPlcal! MCI4069
23 PA3 15 PB3
ITYPlcall
22 PA2 PB2
PAl PBI
PAO PBO

TTL DrlYlng Port A Directly CMOS or TTL Dnvlng Port B Dlrectl\

MCI4069

PCI
peo/riMER

CMOS and TTL DrlYlng Port C Directly

4·228
MC6805T2

VARIABLE DIVIDER The use of the 14-blt latch synchronizes the data transfer
The variable divider IS a 14-blt binary down counter which between two asynchronous systems, namely, the CPU and
communicates with the CPU via two read/write registers the variable divider
located at address $OOA, for the LS byte, and $OOB, for the At power up reset both the variable divider and the con-
M S byte The upper two bits In register $OOB, always read tents of the PLL registers are set to logical "l's"
as logical "l's" When the variable divider count has reached The variable frequency Input pin, fin, IS self biased requir-
zero a preset pulse, fVAR, IS generated. This IS used to Ing an ac coupled signal with a normal sWing of a 5 V The
reload the variable divider with the contents of the 14-blt Input frequency range of fin allows the device, together with
latch as shown In Figure 22 a SUitable prescaler, to cover the enttre TV frequency spec-
Data transfers from registers $OOA and $OOB to the latch trum
occur outside the preset time and only dUring a write opera- REFERENCE DIVIDER
tion performed on register $OOA For example, a 6-blt data ThiS la-stage binary counter generates a reference fre-
transfer to register $OOB IS only transferred to the variable quency, fREF, which IS compared with the output of the
divider If followed by a write operation to register $OOA variable diVider The reference diVider IS mask program-
Figure 23 shows a tYPical error free manipulation of the mable, thus, allOWing the user a chOice of reference fre-
14-blt data In the fine tuning operations quency, see Figure 22.

FIGURE 20 - PHASE LOCK LOOP AN AN RF FREQUENCY SYNTHESIZER

fVCO

•
""COMP
Vancap
.-- ,-----------------
I I
I I

Band
Information

MC6805T2 I
___________ ...1

FIGURE 21 - PRINCIPAL PLL EQUATIONS

For a system In lock.

fVAR = fREF

where P = prescaler diVIsion ration

fVCO = fREF· p. N

Minimum frequency step =

b.fVCO = fREF· P
b.N

e.g.' fCL = 400 MHz

R = 2'0
where R = the reference diVider ratio
P =64
~ = 62.5 kHz
b.N
fREF = 9765Hz

4-229
 MC6805T2

FIGURE 22 - MC6806T2 PLL BLOCK DIAGRAM

CPU Data Bus

~--------- READ PLLLOW

~-----.....- - - WRITE PLLLOW

Variable D,v,der

• ",COMP o-ot_-----I Comparator

r--,
I I Manufacturing
L _ .J Mask Option

tCL
tREF = 4,12', 2',
'---y--J
lout of 10 Mask Option

FIGURE 23 - TYPICAL FINE TUNE EXAMPLE

FTUP LDA PLLLOW

INCA =
check If LS byte $FF IReg $OOAI
BNE TTl If not Increment only LS byte
INC PLLLOW Increment MSB IReg $OOBI before LSB
TTl INC PLLLOW

FTDWN TST PLLLOW =

check If LS byte $00
BNE TT2 If not decrement only LS byte
DEC PLLHI decrement MSB before LSB
TT2 DEC PLLLOW

4-230
MC6805T2

PHASE COMPARATOR delays. Thus, phase comparators exhIbIt non-hnear

The phase comparator compares the frequency and phase characteristIcs and for systems whIch lock In phase, th,s
of fVAR and fREF, and according to their phase relatIonshIp results In a 'backlash' effect - creatIng sIdebands and FM
generates a three-level output, </lCOMP, as shown in FIgures dIstortIon. To aVOId thIs effect a very short pulse IS Inlected
24 and 25. The output waveform IS then Integrated, periodically Into the system. The loop, In turn, attempts to
amphfled, and the resultant dc voltage IS apphed to the cancel thIs Interference. and In dOing so brings the phase
voltage controlled OSCIllator comparator to ItS hnear zone, as shown In FIgures 26 and 27.
In practIce a hnear characteristIc around the steady-state A tYPIcal apphcatlon, for a TV frequency syntheSIzer, is Il-
regIon can not be achIeved due to Internal propagatIon lustrated In FIgure 28

FIGURE 24 - PHASE COMPARATOR STATE DIAGRAM

'VAR 'REF
II
",COMP 3-State
Output
o HIgh-Impedance

FIGURE 25 - PHASE COMPARATOR OUTPUT WAVEFORM

'VAR

'REF--+-........

1-
",COMPIST
0-

.. Phaselead
.. II
Phaselag
.. Stable State

4-231
 MC6805T2

FIGURE 28 - PHASE COMPARATOR CHARACTERISTICS

r-
ldeal
y /
/
/
/
-"""T'"------7'hoIF--f-----..--- WLLOtREF
-2..

•
FIGURE '0 - PHASE COMPARATOR WITH PULSE INJECTION

Ideal
y /
/
/
/
/
--.--------,jC---+~+---r_ ... WLLOtREF
-2..

/
/ No Backlash Zone

/
/
----./

4·232
MC6805T2

FIGURE 28 - A TYPICAL 1V SYNTHESIZER APPLICATION

4MHz

MCl4497
Remote
Control
Transmitter
MCS805T2
000
CE
000
KEYBOARD

V'Vaneap

Band

or ~CMl44102-CMOS Memory
SMA 2901/MCM 2801 NMOS 18x16
Non-Volatile
II
BIT MANIPULATION
The MCU has the ability to set or clear any single random- have individual flags In RAM or to handle I/O bits as control
access memory or Input/ output bit (except the Data Direc- lines
tIOn Registers, see Caution under INPUT/OUTPUT The coding example In Figure 29 Illustrates the usefulness
paragraph), with a single instruction (BSET, BCLR) Any bit of the bit manipulation and test instructions Assume that
In page zero including ROM, except the DDRs, can be the MCU IS to communicate With an external senal device
tested, uSing the BRSEl and BRCLR instructions, and the The external device has a data ready signal, a data output
program branches as a result of ItS state The Carry bit line, and a clock line to clock data one bit at a time, LSB first,
equals the value of the bit referenced by BRSEl and BRCLR out of the device The MCU walts until the data IS ready,
A Rotate instruction may then be used to accumulate senal clocks the external device, picks up the data In the Carry Flag
Input data In a RAM location or register The capability to (C-blll, clears the clock line and finally accumulates the data
work with any bit In RAM, ROM, or I/O allows the user to bits In a RAM location

FIGURE 29 - BIT MANIPULATION EXAMPLE

MCU SELF BRSET 2, PORTA, SELF

-- Ready r-
2p
Senal
Clock 0
Device 1R
BSET 1, PORTA
T
Data BRCLR 0, PORTA, CONT
OA
r- CONT BCLR 1, PORTA
ASR RAMLOC

4-233
 MC6805T2

ADDRESSING MODES INDEXED, 16-BIT OFFSET - In the Indexed, 16-blt offset

The MCU has 10 addressing modes which are explained addreSSing mode, the effective address IS the sum of the
briefly In the following paragraphs For additional details and contents of the unsigned 8-blt Index register and the two un-
graphical illustrations, refer to the M6805 Family Users Signed bytes follOWing the opcode ThiS addreSSing mode
Manual can be used In a manner Similar to Indexed, 8-blt offset, ex-
The term "effective address" lEAl IS used In describing the cept that this 3-byte Instruction allows tables to be anywhere
address modes EA IS defined as the address from which the In memory
argument for an Instruction IS fectched or stored
BIT SET/CLEAR - In the bit set/clear addreSSing mode,
IMMEDIATE - In the Immediate addressing mode, the the bit to be set or cleared IS part of the opcode, and the byte
operand IS contained In the byte Immediately following the follOWing the opcode speCifies the page-zero address of the
opcode The Immediate addressing mode IS used to access byte In which the speCified bit IS to be set or cleared Thus,
constants which do not change dUring program execution any read/write bit In the first 256 locations of memory, in-
Ie g , a constant used to InitialIZe a loop counterl cluding I/O, can be selectively set or cleared with a single
2-byte instruction See Caution under the INPUT/OUTPUT
DIRECT - In the direct addreSSing mode, the effective paragraph
address of the argument IS contained In a single byte follow-
Ing the opcode byte Direct addreSSing allows the user to BIT TEST AND BRANCH - The bit test and branch
directly address the lowest 256 bytes In memory with a Single addreSSing mode IS a combination of direct addreSSing and
2-byte instruction ThiS Includes the on-chip RAM and I/O relative addreSSing. The bit and condition Iset OJ clear) IS In-
registers and 128 bytes of ROM Direct addreSSing IS an ef- cluded In the opcode, which IS to be tested and the address

•
fective use of both memory and time of the byte to be tested IS In the single byte Immediately
follOWing the opcode byte The Signed relative 8-blt offset In
EXTENDED - In the extended addreSSing mode, the ef- the third byte IS added to the value of the PC If the branch
fective address of the argument IS contained In the two bytes condition is true. ThiS single 3-byte instruction allows the
follOWing the opcode Instructions uSing extended address- program to branch based on the condition of any readable
Ing are capable of referenCing arguments anywhere In bit In the first 256 locations of memory The span of branch-
memory with a single 3-byte Instruction When uSing the Ing IS from + 130 to -125 from the opcode address The
Motorola assembler, the programmer need not specify state of the tested bit IS also transferred to the Carry bit of
whether an instruction uses direct or extended addreSSing the Condition Code Register See Caution under the IN-
The assembler automatically selects the shortest form of the PUT /OUTPUT paragraph
Instruction
INHERENT - In the Inherent addreSSing mode, all the in-
RELATIVE - The relative addreSSing mode IS only used In formation necessary to execute the instruction IS contained
branch Instructions In relative addreSSing, the contents of In the opcode Operations speCifYing only the Index register
the 8-blt signed byte follOWing the opcode Ithe offsetl IS add- or accumulator, as well as control instruction with no other
ed to the PC If and only If the branch condition IS true. Oth8f- arguments, are Included In thiS mode These instructions are
Wise, control proceeds to the next Instruction The span of one byte long
relative addreSSing IS from - 126 to + 129 from the opcode
address. The programmer need not worry about calculating INSTRUCTION SET
the correct offset when uSing the Motorola assembler, since The MCU has a set of 59 baSIC instructions, which when
It calculates the proper offset and checks to see If It IS within combined with the 10 addreSSing modes produce 207 usable
the span of the branch. opcodes. They can be diVided Into five different types
register/memory, read/modify/write, branch, bit manipula-
INDEXED, NO OFFSET - In the Indexed, no offset ad- tion, and control The follOWing paragraphs briefly explain
dressing mode, the effective address of the argument IS con- each type. All the instructions within a given type are
tained In the 8-blt Index register. Thus, thiS addreSSing mode presented In indiVidual tables
can access the first 256 memory locations. These instruc-
tions are only one byte long ThiS mode IS often used to REGISTER/MEMORY INSTRUCTIONS - Most of these
move a pOinter through a table or to hold the address of a instructions use two operands. One operand IS either the ac-
frequently referenced RAM or I/O location cumulator or the Index register The other operand IS obtain-
ed from memory uSing one of the addreSSing modes The
INDEXED, 8-BIT OFFSET - In the Indexed, 8-blt offset Jump uncondltlonallJMP) and Jump to subroutine IJSR) in-
addreSSing mode the effective address IS the sum of the con- structions have no register operand. Refer to Table 3.
tents of the unsigned 8-blt Index register IXI and the unsign-
ed byte follOWing the opcode. ThiS addreSSing mode IS READ/MODIFY/WRITE INSTRUCTIONS - These in-
useful In selecting the kth element In an n element table. structions read a memory location or a register, modify or
With this 2-byte instruction, k would tYPically be In X with test ItS contents, and write the modified value back to
the address of the beginning of the table In the Instruction. memory or to the register Isee Cautions under INPUT/OUT-
As such tables may begin anywhere within the first 256 ad- PUT paragraph). The test for negative or zero ITST) instruc-
dressable locations and could extend as far as location 511 tion IS Included In the read/modlfy/wnte instructions though
1$1FEI. It does not perform the write. Refer to Table 4.

2·234
 TABLE 3 - REGISTER/MEMORY INSTRUCTIONS s:
~
Addressmg Modes
Indexed Indexed Indexed
Immediate Direct Extended (No Offset! (8 elt Offset) (16-8It Offset)

Function Mnemonic Code

Op # # Op #
Bytes Cycles Code Bytes Cycles
• Op
•
Code Bytes Cycles
• Op
• Op •
Code Bytes Cycles Code Bytes Cycles
• • OP
Code Bytes
• •
Cycles
;j
Load A from Memory LDA A6 2 2 86 2 4 C6 3 5 F6 1 4 E6 2 5 D6 3 6
load X from Memory LDX AE 2 2 BE 2 4 CE 3 5 FE 1 4 EE 2 5 DE 3 6
Store A In Memory STA B7 2 5 C7 3 6 F7 1 5 E7 2 6 D7 3 7
Store X 10 Memory STX BF 2 5 CF 3 6 FF 1 5 EF 2 6 DF 3 7
Add Memory 10 A ADD AB 2 2 BB 2 4 CB 3 5 FB 1 4 EB 2 5 DB 3 6
Add Memory and
Carry to A ADC A9 2 2 B9 2 4 C9 3 5 F9 1 4 E9 2 5 D9 3 6
Subtract Memory SU8 AD 2 2 80 2 4 CO 3 5 FO 1 4 EO 2 5 DO 3 6
Subtract Memory from
AWllh Borrow S8C A2 2 2 82 2 4 C2 3 5 F2 1 4 E2 2 5 D2 3 6
AND Memory to A AND A4 2 2 B4 2 4 C4 3 5 F4 1 4 E4 2 5 D4 3 6
OR Memory with A OAA AA 2 2 8A 2 4 CA 3 5 FA 1 4 EA 2 5 DA 3 6
E)(clu5lVe OR Memory
with A EOA AB 2 2 88 2 4 C8 3 5 F8 1 4 E8 2 5 D8 3 6
Anthmetlc Compare A
with Memory CMP A1 2 2 B1 2 4 C1 3 5 F1 1 4 El 2 5 D1 3 6
Arlthmellc Compare X
with Memory CPX A3 2 2 B3 2 4 C3 3 5 F3 1 4 E3 2 5 D3 3 6
~
elt Test Memory with
i\) A (logical Compare) BIT A5 2 2 B5 2 4 F5 1 4 E5 2 5 D5
U) C5 3 5 3 6
0'1 Jump Unconditional JMP - - - BC 2 3 CC 3 4 FC 1 3 EC 2 4 DC 3 5
Jump to Subroutine JSA BD 2 7 CD 3 8 FD 1 7 ED 2 B DD 3 9

TABLE 4 - READ/ MODIFY/WRITE/ INSTRUCTIONS

Addressing Modes
Indelled Indexed
Inherent (A) Inherent (Xl Direct (No Offsetl (8 Bit Offset)

Function
Op #
Mnemonic Code Bytes Cycles
• Op
• # Op
•
Code Bytes Cycles Code Bytes Cycles
• Op
•
Code Bytes Cycles
• Op #
Code Bytes Cycles
•
Increment 1NC 4C 1 4 5C 1 4 3C 2 6 7C 1 6 6C 2 7
Decrement DEC 4A 1 4 5A 1 4 3A 2 6 7A 1 6 6A 2 7
Clear CLA 4F 1 4 5F 1 4 3F 2 6 7F 1 6 6F 2 7
Complement COM 43 1 4 53 1 4 33 2 6 73 1 6 63 2 7 I

Negate I
(2'5 Complement) NEG 40 1 4 50 1 4 30 2 6 10 1 6 60 2 7
Rotate Left Thru Carry AOL 49 1 4 59 1 4 39 2 6 79 1 6 69 2 7
Rotate Right Thru Carry AOR 46 1 4 56 1 4 36 2 6 76 1 6 66 2 7
logical Shift Left LSL 48 1 4 58 1 4 3B 2 6 78 1 6 68 2 7
Logical ShIft RIght LSA 44 1 4 54 1 4 34 2 6 74 1 6 64 2 7
Anthmetlc Shift Right ASA 47 1 4 57 1 4 37 2 6 77 1 6 67 2 7
Test for NegatIve
or Zero TST 4D 1 4 5D 1 4 3D 2 6 7D 1 6 6D 2 7

II
 MC6805T2

BRANCH INSTRUCTIONS - The branch instructions CONTROL INSTRUCTIONS - The control Instructions
cause a branch from the program when a certain condition is control the MCU operations dUring program execution
met. Refer to Table 5. Refer to Table 7.

BIT MANIPULATION INSTRUCTIONS - These instruc- ALPHABETICAL LISTING - The complete instruction set
tions are used on any bit In the first 256 bytes of the memory IS given In alphabetical order In Table 8
Isee Cautions under INPUT/OUTPUT paragraph). One
group either sets or clears. The other group performs the bit OPCODE MAP SUMMARY - Table 9 IS an opcode map
test branch operations Refer to Table 6. for the instructions used on the MCU.

4·236
MC6805T2

TABLE 5 - BRANCH INSTRUCTIONS

Relative Addressing Mode

Op # #
Function Mnemonic Code Bytes Cycles
Branch Always BRA 20 2 4
Branch Never BRN 21 2 4
Branch IFF Higher BHI 22 2 4
Branch IFFLower or Same BLS 23 2 4
Branch IFFCarry Clear BCC 24 2 4
(BranchlFFHlgher or Same) (BHS) 24 2 4
Branch IFF Carry Set BCS 25 2 4
(Branch IFF Lower) (BLO) 25 2 4
BranchlFF Not Equal BNE 26 2 4
Branch IFF Equal BED 27 2 4
Branch IFF Half Carry Clear BHCC 28 2 4
Branch IFF Half Carry Set BHCS 29 2 4
Branch IFF Plus BPL 2A 2 4
BranchlFF MinUS BMI 2B 2 4

II
Branch IFF Interupt Mask
alt IS Clear BMC 2C 2 4
Branch IFF Interrupt Mask
Bit IS Set aMS 20 2 4
Branch IFF Interrupt Lme
IS Low BIL 2E 2 4
BranchlFFlnterrupt Line
IS High BIH 2F 2 4
Branch to Subroutine aSR AO 2 8

TABLE 6 - BIT MANIPULATION INSTRUCTIONS

Addressing Modes
Bit Set/Clear ait Test and Branch
Op # # Op # #
Function Mnemonic Code Bytes Cycles Code Bytes Cycles
Branch IFF Bit n IS set BRSEl n (n = 0 71 - - - 20n 3 10
Branch IFF a,t n IS clear aRCLR n (n = 0 71 - - - 01 + 2 en 3 10
Set a,t n aSEl n (n - 0 71 10 + 20 n 2 7 - - -
Clear bit n BCLR n (n = 0 7) 11 + 2 on 2 7 - - -

TABLE 7 - CONTROL INSTRUCTIONS

Inherent
Op # #
Function Mnemonic Code Bytes Cycles
Transfer A to X TAX 97 1 2
Transfer X to A TXA 9F 1 2
Set Carry a,t SEC 99 1 2
Clear Carry Bit CLC 98 1 2
Set Interrupt Mask a,t SEI 9B 1 2
Clear Interrupt Mask Bit CLI 9A 1 2
Software Interrupt SWI 83 1 11
Return from Subroutine RTS 81 1 6
Return from Interrupt RTI 80 1 9
Reset Stack Pomter RSP 9C 1 2
No-Operation NOP 90 1 2

4-237
 MC6805T2

TABLE 8 - INSTRUCTION SET

Addressing Modes Condition Code

Bit Bit
Indexed Indexed Indexed Set! Test &
Mnemonic Inherent Immediate Direct Extended Relative (No Offset) (S Sits) (16 Sits) Clear Sranch H I N Z C

"•""
ADC X X X X X X
ADD X X X X X X
"•""
"
AND X X X X X X
•• •"
ASl X X X X
• • "" "" "
ASR X X X X
••
BeC X
• • •" •" •"
BelR X
•••• •
BeS X
•••• •
BEQ X
•••• •
BHCC X
•••• •
BHCS X
•••• •
BHI X
•••• •
BHS X
•••• •
BIH X
•••• •
Bil X
•••• •
X X
••"" •
I
BIT X X X X
BlO X
•••• •
BlS X
•••• •
BMC X
•••• •
BMI
•••• •
BMS
•••• •
BNE
•••• •
BPl
•••• •
BRA
•••• •
BRN
•••• •
BRClR X
•••• "
BRSET X
••••
BSEl X
•••• •"
BSR X
•••• •
ClL X
•••• a
CLI X
• ••a
•
ClR X X X X
•• a 1
•
CMP X X X X X X
••
COM X X X X
• • "" "" 1"
CPX X X X X X X
• .'" "
DEC X X X X
••"" •"
EaR X X X X X X
•• •
INC X X X X
• • "" "" •
JMP X X X X X
•••• •
JSR X X X X X
•••• •
X X X X X
•• •
• • "" ""
LOA X
lOX X X X X X X
•
X X X X
••
• • " ""
lSl
LSR X X X X
"
X X
••""
a
"
NEG
Nap X
X X

•••• "•
ORA X X X X X X
••"" •
X x
••
• • •" •" •"
ROl X X
RSP X
Condition Code Symbols
H Half Carry IFrom Bit 31 C Carry/Borrow
I Interrupt Mask 1\ Test and Set If True, Cleared Otherwise
N Negative ISlgn Bltl • Not Affected
Z Zero

4·238
MC6805T2

TABLE 8 - INSTRUCTION SET (CONTINUEDI

Addressin Modes Cond,tion Code

B,tB,t
Indexed Indexed Indexed Setl Test.
Mnemonic Inherent Immediate Direct Extended Relat,ve (No Offsetl (B B,tsl (16 B'tsl Clear Branch H I N Z C
ATI X ? , ? ? ?
ATS X
•• • • •
SBC X X X X X X
•• A A A
SEC X
•••• 1
SEI X
• ••1
•
STA X X X X X
•• A A
•
STX X X X X X
•• A A
•
SUB X X X X X X
•• A A A
SWI X
• ••1
•
TAX X
•• • • •
TST X X X X
•• • A A

•••• •

.,
TXA X

Condition Code Symbols

H Half Carry 1From Bit 31 C Carryi Borrow
I Interrupt Mask fI Test and Set If True, Cleared Otherwise
N Negative ISlgn BIt! • Not Affected
Z Zero , Load CC Register From Stack

4-239
 TABLE 9 - M6805 FAMILY INSTRUCTION OPCODE MAP
• ~
("')

Bit Manipulation
T
Branch
RL R AI
Read/Modify/Write
INH(X Xl IX INH
Control
I IMM DIR
Register I Memory
EXT 1X2 11 IX
~jj
6
~ ~, 8 9 A 8 0 E F
.i" o,~ o,~, C
Low ,J" oo'io 0110 0111 '000 '00' 1010 1011 1100 1101 1110 1111 ~w
'0 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 9 9 2 2 4 3 5 4
SUB' , SUB
DIR 13 SU~XT
BRSE:~B BRA NEGA NEGX RTI SUB '
rk 10 5
2
7
BSETO
B e
5
2
4
RE
3
2
NEG
DIR 1 INH I INH
2 NEG
IXI 1
NEG
IX 1
6
INH
6 2
SUB
IMM
2 4
SUB
3 5 4
3
6
IX2
5 5
IXl
4
1
4
IX
3
40.
1 BRClRO BClRO BRN RTS CMP CMP CMP CMP CMP CMP 1
0001 3 BTB Bse 2 RE 1 INH 2 IMM 2 OIR 3 EXT 3 IX2 2 IXI I IX 0001
10 5 7 5 4 3 2 2 4 3 5 4 6 5 5 4 4 3
2 BRSETl 2 BSETlc ,? BHIRFI SBC SBC SBC SBC SBC SBC 2
0010 3 BTB 2 IMM 2 DIR 3 EXT 3 IX2 2 IXI 1 IX 0010
10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 11 10 2 2 4 3 5 4 6 5 5 4 4 3
2 BCl~le 12
3 BRClRl BlSREl COM COMA COMX 2 COM COM SWI CPX CPX CPX CPX CPX CPX 3
0011 3 BTB DIR 1 INH 1 INH lXl I IX 1 INH 2 IMM 2 D1R 3 EXT 3 IX2 2 IXl 1 IX 0011
3 3 4 3 5 2 2 4 3 5 4 3
'~RSET25
7 5 4 6 5 4 7 6 6 4 6 5 5 4
4 BSET2 BCC lSR LSRA lSRX 2 lSR lSR AND MJO AND AND AND AND 4
0100 3 BTB B e 2 REl 2 DiR 1 INH 1 INH IXl I IX 2 IMM 2 DIR 3 EXT 3 IX2 2 IXl 1 IX 0100
10 5 7 5 4 3 2 2 4 3 5 4 6 5 5 4 4 3
5 BRClR2 BClR2 BCS BIT BIT BIT BIT BIT BIT 5
0101 3 BTB 2 B e 2 REL IMM 2 DIR 3 EXT IX2 2 IXl 1 IX 0101
10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 2 2 4 3 5 4 6 5 5 4 4 3

0110
6 BRSEJiB 2 BSE~~c 2
BNE
REl 2
ROR
DIR I
RORA
lNH 1
RORX
INH 2
ROR
IXI 1
ROR
IX 2
LDA
IMM 2
LOA
DIR 3
lOA
EXT 3
LOA
IX2 2
LOA
IXl I
LOA
IX
",-

10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 2 2 5 4 6 5 7 6 6 5 5 4
2 BCl~~e
7 BRClR3 12 BEGREl ASR ASRA ASRX ASR ASR TAX STA STA STA STA STA 7
0111 3 BTB 2 DIR I INH 1 INH 2 IXl 1 IX 1 INH 2 DIR 3 EXT 3 IX2 2 'Xl 1 IX 0111
10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 2 2 2 2 4 3 5 4 6 5 5 4 4 3

1£. 3BRSE
10
:ie 5 7
BSET1c.
5
12. BHC:ful
4 3 6
LSl
DIR
5
1
4
lSLA
INH
3
1
4
lSlX
INH
3 7
LSL
IXl
6
1
6
LSl
IX
5 2
ClC
INH
2 2
EOR
IMM 2
2 4
EOR
OIR
3
3
5
EOR
EXT
4
3
6
EOR
1X2
5
2
5
EOR
IXl
4
1
4
EOR
IX
3
8
1000

~ 1001
9 3BRCl~~ 2
BClR4
BS
,? BHCS
REl 2
ROl
DIR 1
ROlA
INH 1
ROlX
lNH 2
ROl
IXI 1
ROl
IX 1
SEC
INH 2
ADC
IMM 2
ADC
DIR 3
ADC
EXT 3
ADC
IX2 2
ADC
IXI 1
ADC
IX
9
1(1()1
r\) 10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 2 2 2 2 4 4 6 5 5 4 4
ORA 4
~ 110
A BRSEJ-PB BSE~~e I, BPL
REl 2
DEC
DIR 1
DECA
INH 1
DECX
INH 2
DEC
IXl 1
DEC
IX 1
CLI
INH 2
ORA
IMM 2 DIR 3
ORA
EXT 3
ORA
IX2 2
ORA
IXI 1
ORA
IX
A
1010
o B
10
BRClR5
5 7
BClR5
5 4
BMI
3 2
SEI
2 2
ADD
4
ADD
3 5
ADD
4 6
ADD
5 5
ADD
4 4
ADD B
1011 3 8TB 2 Bse 2 REl I INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IXl 1 IX 1011
10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 2 2 3 2 4 3 5 4 4 3 3 2
C BRSET6
BTB 2 BSE~~e BMC
2
INC
DIR
INCA
INH
INCX
INH 2
INC
IXl
INC
IX 1
RSP
INH 2
JMP
DIR
JMP
EXT
JMP
IX2 2
JMP
IXl
JMP
IX
C
"""0 10
3BRCl:~B
5 7 5
2
4
2 BClR~e ,2 BMSRE
REL
3 6
TST
4
1
4
TSTA
3
1
4
TSTX
3 7
TST
5
1
6
TST
4 2
NOP
2 8
BSR
6 7
JSR
5
3
I' JSR
6
3
9
JSR
7 8
JSR
6
1

JSR
5
1100

D
1101 iR 1 INH 1 INH 2 IXl 1 IX 1 INH 2 REL 2 DIR 3 EXT 3 IX2 2 IXl I IX 1101 .
10 5 7 5 4 3 2 2 2 4 4 6 5 5 4 4 3
lDX 3
11~
BRSET7 BSET7 Bil STOP lOX LDX lOX lDX LDX E
BTB 2 BS 2 REL 1 INH 2 IMM 2 DIR 3 EX, 3 IX2 2 IXl 1 IX 111L: i
10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 2 2 2 5 4 6 5 7 6 6 5 5 4
F BRClR7 BClR7 BIH ClR ClRA ClRX ClR (lR WAIT TXA STX STX STX STX STX F
1111 3 BTB 2 sse 2 REl 2 DIR 1 INH 1 INH 2 IXl 1 IX 1 INH 1 INH 2 DIR 3 EXT 3 IX2 2 IXI 1 IX 1111 I
AbbnIviations for Add .... Modes LEGEND

INH Inherent
r--F--:;;:::+---------::7'
F ... Opcode Hexadecimal

j
IMM Immediate In

DIR Direct
EXT Extended # of Cycles (HMOS Versions) 4 ... ~ ~
REL Relallve MnemOniC .. SUB 0 Opcode In Binary
BSC Bit Setl Clear Bytes 1 IX <XXX>
BTB Bit Test and Branch 7
IX Indexed (No Offset) # of Cycles (CMOS VerSionsl / " Address Mode
IXI Indexed, 1 Byte (8-BIIl Offset
IX2 Indexed,2 Byte (I6-Blt) Offset
CMOS Versions Only
MC6805T2

ORDERING INFORMATION thoroughly checked and the venficatlon form completed,

The information required when ordering a custom MCU IS signed, and returned to Motorola The signed venf,cat,on
listed below The ROM program may be transmitted to form constitutes the contractual agreement for creation of
Motorola on EPROMls) or on MOOS disk file. the customer mask If desired, Motorola Will program one
To Initiate a ROM pattern for the MCU It IS necessary to blank EPROM from the data file used to create the custom
first contact your local Motorola representative or mask to aid In the venf,cat,on process
d,stnbutor
ROM VERIFICATION UNITS (RVUs)
EPROMs - The MCM2716 or MCM2532 type EPROMs, Ten MCUs containing the customer's ROM pattern Will be
programmed with the customer program Iposltlve logiC sent for program venficatlon. These Units Will have been
sense for address and data), may be submitted for pattern made uSing the custom mask but are for the purpose of
generation The EPROM must be clearly marked to Indicate ROM venficatlon only For expediency they are usually un-
which EPROM corresponds to which address space The marked, packaged In ceramiC, and tested only at room
recommended marking procedure IS Illustrated below temperature and 5 volts These RVUs are Included In the
mask charge and are not production parts. The RVUs thus
are not guaranteed by Motorola Quality Assurance, and
xxx xxx should be discarded after venf,catlon IS completed

FLEXIBLE DISKS
The disk media submitted must be Single-sided, Single-
denSity, 8-Inch, MOOS-compatible flOPPies The customer

•
must wnte the binary file name and company name on the
disk With a felt-tip pen The minimum MOOS system files as
000 400 well as the absolute binary oblect file Ifllename, .LO type of
file) from the M6805 cross assembler must be on the disk An
xxx = Customer 10 object file made from a memory dump using the ROLLOUT
command IS also acceptable Consider submitting a source
After the EPROM Is) are marked they should be placed In
listing as well as the follOWing files. filename, . LXI EXOR-
conductive IC carners and securely packed Do not use
ciser- loadable format) and filename, .SA IASCII Source
styrofoam
Code). These files will of course be kept confidential and are
used 1) to speed up the process In-house If any problems
VERIFICATION MEDIA anse, and 2) to speed up the user-te-factory Interface If the
All onglnal pattern media IEPROMs or Floppy Disk) are user finds any software errors and needs assistance qUickly
filed for contractual purposes and are not returned. A com- from Motorola factory representatives
puter listing of the ROM code will be generated and returned MOOS IS Motorola's Disk Operating' System available on
along With a listing venf,cat,on form The listing should be development systems such as EXORCiser, EXORsets, etc.

4-241
 MC6805T2

MC6806T2 MCU ORDERING INFORMATION

Date _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Customer PO Number _ _ _ _ _ _ _ _ _ __

Customer Company _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Motorola Part Numbers

Address MC _ _ _ _ _ __
------------------------SC
City _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ State _ _ _ _ _ _ _ _ _ _ _ _ _ Z,p _ _ _ _ __ -------
Count~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Phone _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Extenslon _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Customer Contact Person _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Customer Part Number

OPTION LIST
Select the options for your MCU from the followmg list. A
manufacturing mask will be generated from this information.

II
Timer Clock Source
o Internal ",2 clock
o TIMER Input pin
Timer Prescaler
o 2" (divide by 1) o 24 (divide by 16)
o 2' (divide by 2) o 2' (divide by 32)
o 2' (divide by 4) o 2' (divide by 64)
o 2' (divide by 8) o 2' (divide by 128)
Internal Oscillator Input Low Voltage Inhibit Port A Output Drive
o Crystal oDisable o CMOS and TTL
o Resistor o Enable o TTL Only

Pattern Media fAil other media requires prior factory approval)

o EPROMs (MCM2716 or MCM2532 o Floppy Disk
o Other

Clock Freq. _ _ _ _ _ _ _ _ _ _ _ __

Temp. Range _ _ _ _ _ _ _ _ _ _ _ _ 0 O· to + 70·C IStandard)

*ReqUires prior factory approval

Marking Information 112 Characters MaXimum)

Title _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Signature _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

4·242
® MOTOROLA MC680SU2

Advance InforIllation
HMOS
8-BIT MICROCOMPUTER UNIT WITH AID IHIGH DENSITY
N-CHANNEL, SILICON-GATE
The MC6805R2 Microcomputer Unit IMCU) IS a member of the M6805
DEPLETION LOAD)
Family of low-cost single-chip Microcomputers The 8-blt microcomputer
contains a CPU, on-chip CLOCK, ROM, RAM, 1/0, 4-channeI8-bit AID,
and TIMER It IS designed for the user who needs an economical 8-BIT
microcomputer with the proven capabilities of the M6800-based Instruction MICROCOMPUTER
set A comparison of the key features of several members of the M6805
Family of microcomputers IS shown on the last page of this data sheet The
following are some of the hardware and software highlights of the
MC6805R2 MCU
HARDWARE FEATURES:
• 8-Blt Architecture
• 64 Bytes of RAM
• Memory Mapped 1/0 CASE 715

~PSUFFIX
• 2048 Bytes of User ROM
• 24 TTL! CMOS Compatible Bidirectional 1/0 Lines 18 lines are LED

•
Compatlblel
• 2 to 5 Digital Input Lines ~-{" - ;,' PLASTIC PACKAGE
• AI D Converter CASE 711

~SSUFFIX
8- Bit ConverSion, Monotonic
1 to 4 Multiplexed Analog Inputs
± 1/2 LSB Quantizing Error
± 1/2 LSB All Other Errors ~lllllill ' 'CERDIP PACKAGE
± 1 LSB Total Error Imax)
CASE 734
Ratlometrlc Conversion
• Zero-Crossing Detection
• On-Chip Clock Generator
FIGURE 1 - PIN ASSIGNMENTS
• Self-Check Mode
• Master Reset
• Complete Development System Support On EXORciser'" Vss PA7
• 5 V Single Supply REID PA6

SOFTWARE FEATURES: INT PA5

Similar to M6800 Family VCC PA4
Byte EffiCient Instruction Set
EXTAL PA3
Easy to Program
True Bit Manipulation XTAL PA2
Bit Test and Branch Instructions PA1
NUM
Versatile Interrup Handling
Versatile Index Register TIMER PAD
Powerful Indexed Addressing for Tables PCD PB7
Full Set of Conditional Branches
PC1 PB6
Memory Usable as Register I Flags
Single Instruction Memory ExamlnelChange PC2 PB5
10 Powerful Addressing Modes PC3 PB4
All Addressing Modes
PC4 PB3
User Callable Self-Check Subroutines
PC5 PB2
USER SELECTABLE OPTIONS: PC6 PB1
• Internal8-Blt Timer with Selectable Clock Source IExternal Timer
Input or Internal Machine Clock) PC7 PBD
• Timer Prescaler Option 17 Bits 2N) P07 POD
• 8 Bidirectional 1/0 Lines with TTL or TTL!CMOS Interface Option
P0611NT2 P01
• Crystal or Low-Cost ReSistor OSCillator Option
• Low Voltage Inhibit Option, P05 P02
• 4 Vectored Interrupts, Timer, Software, and 2 External P04 P03

4-243
 MC6805U2

FIGURE 2 - MC6806U2 HMOS MICROCOMPUTER BLOCK DIAGRAM

Timer

,--__ t
PAO
PAl Accumulator
Port PA2 Data a A
CPU iN'f2
A PA3 D" Inde, Control
110 PA4 Reg Register PD~
Lines PA5 a x PDl
PA6
Condition PD2
PA7 Port D
Code PD3
Register Input
CC
CPU PD4 Lines
Stack PD5 _
POinter PD6i1NT2
PBO 5 SP PD7
PBl Program
Port PB2 Port Data Counter

•
B PB3 B D" 4 High PCH
I/O PB4 ALU
Reg Reg
Lines PB5 Program
PB6 Counter
PB7 8 Low PCO
PCl
PC2 Port
Data POlt
PC3 C
D" C 1,0
Reg Reg PC4
PC5 lines
PC6
PC7

MAXIMUM RATINGS
ThiS deVice contains CircUItry to protect the
Rating Symbol Value Unit
mputs against damage due to high static
Supply Voltage VCC -03to +70 V voltages or electnc fields, however, It IS ad-
Input Voltage (Except Pin 61 V in -03to +70 V ViSed that normal precautions be taken to

Operating Temperature Range TA o to 70 °c avord application of any voltage hIgher than

maxImum rated voltages to thiS hlgh-
Storage Temperature Range Tstg -55 to + 150 °c Impedance CirCUit For proper operatIon It IS
Junction Temperature recommended that Vin and V out be con-
PlastiC 150 strained to the range V SS::S I V,n or
Ceramic 1J 175 °c VoutlSVCC Rehability of operation IS
Cerdlp 175 enhanced If unused Inputs are tJed to an ap-
propriate logiC voltage level ,e 9 . either VSS
or VCC I

THERMAL CHARACTERISTICS
Characteristic Symbol Value Unit
Thermal Resistance
PlastiC 100
Ceramic 9JA 50 °C/W
Cerdlp 60

4-244
MC6805U2

POWER CONSIDERATIONS

The average chlp-Iunctlon temperature. T J. In DC can be obtained from'

T J = T A + (Poo8JA) (1)
Where'
TA- Ambient Temperature. DC
8JA - Package Thermal Resistance. Junction-to-Ambient, DC/W
PO- PINT+ PPORT
PINT-ICC x VCC. Watts - Chip Internal Power
PPORT- Port Power DIssipation. Watts - User Determined
For most applications PPORT<C PINT and can be neglected. PPORT may become Significant If the device IS configured to
drive Darlington bases or sink LED loads.
An approximate relationship between Po and T J Ilf PPORT IS neglected) IS'
PO= K~ IT J + 273 D C) (2)
Solving equations 1 and 2 for K gives
K = PoolT A + 273 DC) + 8JAoP0 2 (3)
Where K IS a constant pertaining to the particular part K can be determined from equation 3 by measuring Po lat eqUilibrium)
for a known T A USing this value of K the values of Po and T J can be obtained by solving equations (1) and (2) Iteratively for any
value of T A.

ELECTRICAL CHARACTERISTICS IV CC =

Input High Voltage

RESET 14 75sVCCs5 751
IVCC<4751
INT 14 75sVCCs5 751
IVCC<4751
All Other
+ 525 Vdc +
Characteristic
- 05 Vdc VSS = GND T A = 0° to 70°C Unless Otherwise Notedl
Symbol

V,H
Min

40
VCC-O 5
40
VCC-O 5
20
Typ

-
-
*
*-
Max

VCC
VCC
VCC
VCC
Unit

V
•
VCC
Input High Voltage Timer
Timer Mode VIH 20 - VCC V
Self-Check Mode - 90 150
Input Low Voltage
RESET -03 - 08
INT
All Other
VIL -03
-03
'"
-
15
08
V

RESET HysteresIs Voltages ISee Figures 11. 12. and 131

"Out of Reset" VIRES + 21 - 40 V
"Into Reset" VIRFS 08 - 20
INT Zero Crossing Voltage, Through a Capacitor VINT 2 - 4 Vac p-p
Internal Power DISSipation. No Port Loading VCC-5 75 V. TA-O°C PINT 600 mW
Input Capacitance
EXTAL Cin - 25 - pF
All Other - 10 -
Low Voltage Recover VLVR - - 475 V
Low Voltage Inhibit VLVI - 35 - V
Input Current
TIMER IV in = 04 VI - - 20
INT IV In =2 4 V to VCCI - 20 50
EXTAL IVIn=2 4 V to VCC Crystal OptlOnl lin - - 10 ,.A
_ _ IVIn = 0 4 V Crystal Optlonl - - -1600
RESET IVIn=O 8 VI -40 - -50
(External Capacitor Charging Current)

'" Due to Internal biaSing. thiS Input Iwhen unusedl floats to approximately 20 V

4·245
 MC6805U2

SWITCHING CHARACTERISTICS IV cc= + 525 Vdc +

- 05 Vdc, VSS = GND, TA = 0' to 70'C Unless Otherwise Notedl
Characteristic Symbol Min Typ Max Unit
Oscillator frequency tosc 04 - 42 MHz
Cycle Time 14!foscl tcyc 095 - 10 ~s

INI and TIMER Pulse Width tWL, tWH tcyc + 250 - - ns

~ Pulse Width tRWL tcyc+ 25O - - ns
RESET Delay Time IExternal Cap-l ~FI tRHL - 100 - ms
iNT Zero Crossing Detection Input Frequency (for ± 5° Accuracy) tiNT 003 - 10 kHz
External Clock Input Duty Cycle IEXTALI - 40 50 60 %

PORT ELECTRICAL CHARACTERISTICS IVCC= + 525 Vdc ±O 5 Vdc, VSS = GND, TA = 0' to 70'C Unless Otherwise Notedl
Characteristic I Symbol. L Min J Typ I Max I Unit
Pon A with CMOS drive enabled
Output Low Voltage ILoad= 16 mA VOL - - 04 V
Output High Voltage ILoad= -100 ~A VOH 24 - - V
Output High Voltage ILoad - -10 ~A VOH 35 - - V
Input High Voltage ILoad= -300 ~A Imaxl VIH 20 - VCC V

•
Input Low Voltage ILoad- -500 ~A Imaxl VI -03 - 08 V
H,-Z State Input Current IV In =2 0 V to VCCI IIH - - -300 ~A
HI-Z State Input Current IV,n = 04 VI IlL - - -500 ~A
Pon B
Output Low Voltage ILoad = 32 mA VOL - - 04 V
Output Low Voltage ILoad= 10 mA ISlnk) VOL - - 10 V
Output High Voltage ILoad= -200 ~A VOH 24 - - V
Darlington Current Dnve ISourcel VO-1 5 V IOH -10 - -10 mA
Input High Voltage VIH 20 - Vrr V
Input Low Voltage VIL -03 - 08 V
H,-Z State Input Current ITSI - 2 20 ~A
Pon C and Pon A with CMOS drive disabled
Output Low Voltage ILoad= 16 mA VOL - - 04 V
Output High Voltage ILoad = -100 ~A VOH 24 - - V
Input High Voltage VIH 20 - VCC V
Input Low Voltage VIL -03 - 08 V
HI-Z State Input Current ITSI - 2 20 ~A
Pon D (Inputs)
Input High Voltage I VIH I 20 I - VCC I V
Input Low Voltage I VI I -03 I - I 08 I V
Input Current I lin I - I - I 20 I ~A

FIGURE 3 - TTL EQUIVALENT TEST LOAD FIGURE 4 - CMOS EQUIVALENT TEST LOAD FIGURE 5 - TTL EQUIVALENT TEST LOAD
IPORT BI IPORT AI IPORTS A AND C)

VCC=575V VCC=5.75 V
MMD6150 Test MMD6150
V

t
Test
POint or Equlv POint or Equlv ...-:
1 5 k!l 2.97 kO
Test Paint ~
40 pF
11 olall
12 kO MMD7000
or Equlv
130 pF ITotall 30 pF
ITotall
~ 24 kO MMD7000
or Equlv.

4·246
MC6805U2

SIGNAL DESCRIPTION INPUT/OUTPUT LINES (PAO-PA7, PBO-PB7, PCO-PC7.

The Input and output signals for the MCU, shown In PDO-PD7) - These 32 lines are arranged Into four 8-bIt ports
Figure 1, are described In the follOWing paragraphs lA, 8, C, and DI Ports A, 8, and C are programmable as
either Inputs or outputs, under software control of the data
Vcc AND VSS - Power IS supplied to the MCU uSing direction registers Port D IS for digital Input only and bit 6
these two pins VCC IS power and VSS IS the ground con- may be used for a second Interrupt INT2 Refer to
nection INPUT/OUTPUT and INTERRUPTS for additional Informa-
INT - This pin provides the capability for asynchronously tion.
applYing an external Interrupt to the MCU Refer to INTER-
RUPTS for addltonal InformatIOn MEMORY - The MCU IS capable of addreSSing 4096
bytes of memory and I/O registers With Its program counter
XTAL AND EXTAL - These pins provide control Input The MC6805U2 MCU has Implemented 2314 of these bytes
for the on-chip clock OSCillator circuit. A crystal, a resistor, or ThiS consists of 2048 user ROM bytes, 192 self-check ROM
an external signal depending on user selectable manufactur- bytes, 64 user RAM bytes, 7 port I/O bytes, 2 timer registers,
Ing mask option, can be connected to these pinS to provide a and a miscellaneous register, see Figure 6 for the Address
system clock with various degrees of stability/cost tradeoffs Map. The user ROM has been split Into three areas The first
Lead length and stray capacitance on these two pinS should area IS memory locations $080 to $OFF, and allows the user
be minimized. Refer to INTERNAL CLOCK GENERATOR to access the ROM locations utiliZing the direct and table
OPTIONS for recommendations about these Inputs look-up Indexed addreSSing modes The main user ROM area
TIMER - This Pin allows an external Input to be used to IS from $7CO to $F37 The last 8 user ROM locations at the
decrement the Internal timer cirCUitry Refer to TIMER for top of memory are for the Interrupt vectors

•
additional information about the timer circuitry. The MCU reserves the first 16 memory locations for 1/0
features, of which 10 have been Implemented These loca-
RESET - ThiS pin allows resetllng of the M CU at times
tions are used for the ports, the port DDRs, the timer, and
other than the automatic resetting capability already In the
the INT2 miscellaneous register Of the 64 RAM bytes, 31
MCU. The MCU can be reset by pul"ng RESET low Refer to
bytes are shared With the stack area The stack must be used
RESETS for additional Informallon
With care when data shares the stack area
NUM (Non-User Mode) - ThiS pin IS not for user applica- The shared stack area IS used during the processing of
tion and must be connected to VSS Interrupt and subroutine calls to save the processor state

FIGURE 6 - MC6805U2 MCU ADDRESS MAP

7 o 76543210
000 SOOO
110 Ports 0 Port A Data sOOO
Timer
Page Zero 1 Port B Data SOOI
RAM
Access With 1128 Bytes) 2 Port C Data S002
Short 127 S07F
Instructions
128 ~080 3 Port 0 Data S003
Page-Zero

I~F
User ROM 4 Port A DDR*' SOO4*
1128 Bytesl
255 5 Port B DDR*' s005*
256 $100 Port C DDR* $006*
6
Not Used
11728 Bytesl 7 Not Used s007
8 Timer Data Reg s008
1983 S7BF
1984 S7CO
9 Timer Control Reg SOO9
Mam User
ROM 10 M,sc Reg SOOA
11912 Bytes)
3895 SF37 11 SOOB
3896 SF38 Not Used
Self-Check (53 Bytes)
ROM 63 $03F
1192 Bytes) 64 $040
4087 $FF7
4088 SFF8 RAM
Interrupt
(64 Bytes)
Vectors
ROM Stack
(8 Bytes) (31 Bytes
4095 $FFF
MaXimum)

127 t S07F
*CaullOn Data Dlfecllon Registers (DDRs) are wnte-only, they read as $FF

4-247
 MC6805U2

The register contents are pushed onto the stack In the order ACCUMULATOR (AI - The Accumulator IS a general
shown In Figure 7 Since the Stack POinter decrements dur- purpose 8-blt reglstAr used to hold operands and results of
Ing pushes, the low order byte (PCL) of the Program Counter arithmetiC calculations or data manipulations.
IS stacked first, then the high order four bits (PCHI are stack-
ed This ensures that the program counter IS loaded correctly
INDEX REGISTER (XI - The Index Register IS an 8-bIt
dUring pulls from the stack Since the stack pOinter in-
register used for the Indexed addreSSing mode It contains an
crements when It pulls data from the stack A subroutine call
8-blt value that may be added to an Instruction value to
results In only the Program Counter (PCl, PCHI contents be-
create an effective address The Index register can also be
Ing pushed onto the stack, the remaining CPU registers are
used for data manipulations uSing the read/modify/write in-
not pushed
structIOns The Index Register may also be used as a tem-
porary storage area
FIGURE 7 INTERRUPT STACKING ORDER
a PROGRAM COUNTER (PCI - The Program Counter IS a

n-4
7 6
t t t
5
I4 3
Condition
Code Register
2 1

n+1
Pull
12-blt register that contains the address of the next instruc-
tion to be executed

n- 3 Accumulator n+2
STACK POINTER (SPI - The Stack POinter IS a 12-blt
n- 2 Index Register n+3 register that contains the address of the next free location on
the stack DUring an MCU reset, or the Reset Stack POinter

I (RSPI instruction, the Stack POinter IS set to location $07F

•
n- t 1 1 t 1 PCH* n+4 The Stack POinter IS then decremented as data IS pushed on-
to the stack and Incremented as data IS then pulled from the
n PCl* n+5
stack The seven most-Significant bits of the Stack POinter
PUSh are permanently set to 0000011 Subroutines and Interrupts
*For subroutine calls, only PCH and pel are stacked
may be nested down to location $061 (31 bytes maxlmuml
which allows the programmer to use up to 15 levels of
CENTRAL PROCESSING UNIT subroutine calls (less If Interrupts are allowed I
The CPU of the M6805 Family IS Implemented In-
dependently from the I/O or memory configuration Conse-
quently, It can be treated as an Independent central pro- CONDITION CODE REGISTERS (CCI - The Condition
cessor communicating With I/O and memory via Internal ad- Code Register IS a 5-blt register In which four bits are used to
dress, data, and control buses indicate the results of the instruction Just executed These
bits can be indiVidually tested by a program and speCifiC ac-
REGISTERS tion taken as a result of the" state Each bit IS explained In
The M6805 Family CPU has five registers available to the the follOWing paragraphs
programmer They are shown In Figure 8 and are explained In
the follOWing paragraphs.
Half Carry (HI - Set dUring ADD and ADC operations to
FIGURE 8 - PROGRAMMING MODEL indicate that a carry occurred between bits 3 and 4
a
' -_ _ _ _ _ _A_ _ _ _ -'I Accumulator Interrupt (I) - When thiS bit IS set. the timer and external
Interrupts (lNT and INT21 are masked (dlsabledl If an Inter-
a rupt occurs while thiS bit IS set, the Interrupt IS latched and IS
x I Index Register processed as soon as the Interrupt bit IS cleared
11 a
I PCH PCl I Program Counter
Negative (NI - When set, thiS Olt Indicates that the result
11 54 a of the last arithmetiC, logical, or data manipulation was
10101010101 I SP I Stack POinter negative (bit 7 In the result IS a logical onel

Condition Code
Zero (ZI - When set, thiS bit indicates that the result of
Register
the last arithmetiC, logical, or data manipulation was zero
Carry I Borrow

Zero Carry/Borrow (CI - When set, thiS bit indicates that a

Negative
carry or borrow out of the ArithmetiC logiC Unit (AlUI
occurred dUring the last arithmetiC operation ThiS bit IS also
Interrupt Mask
affected dUring bit test and branch InstructionS plus shifts
Half Carry and rotates

4-248
MC6805U2

TIMER used as the source, It can be gated by an Input applied to the

The MC6805U2 MCU timer circuitry IS shown tn Figure 9 TIMER tnput pin allOWing the user to eaSily perform pulse-
The 8-btt counter may be loaded under program control and Width measurements (NOTE For ungated ",2 clock Input to
IS decremented toward zero by the clock Input (or prescaler the timer prescaler, the TIMER ptn should be tied to VCC I
output) When the timer reaches zero, the timer Interrupt re- The source of the clock tnput IS one of the mask options that
quest bit (bit 7) tn the Timer Control Register nCR) IS set IS specified before manufacture of the MCU
The timer tnterrupt can be masked (disabled) by setting the A prescaler option can be applied to the clock Input that
timer tnterrupt mask bit Iblt 6) In the TCR The tnterrupt bit extends the timing Interval up to a maximum of 128 counts
II-bit) tn the Condition Code Register also prevents a timer before decrementing the counter ThiS prescallng mask op-
tnterrupt from betng processed The MCU responds to thiS tion IS also specified before manufacture To aVOid trunca-
Interrupt by saving the present CPU state In the stack, tion errors, the prescaler IS cleared when bit 3 of Timer Con-
fetching the timer tnterrupt vector from locations $FF8 and trol Register IS written to a logiC 1 I thiS bit always reads as a
$FF9 and executtng the Interrupt routtne (see the INTER- logiC Q)
RUPT section) THE TIMER INTERRUPT REQUEST BIT The timer continues to count past zero, failing through to
MUST BE CLEARED BY SOFTWARE The timer and INT2 $FF from zero and then continuing the count Thus, the
share the same Interrupt vector THE INTERRUPT ROUTINE counter can be read at any time by reading the Timer Data
MUST CHECK THE REQUEST BITS TO DETERMINE THE Register ITDRI ThiS allows a program to determine the
SOURCE OF THE INTERRUPT length of lime Since a timer Interrupt has occurred, and not
The clock tnput to the timer can be from an external disturb the counting process
source (decrementing of Timer Counter occurs on a POSitive At power-up or reset, the prescaler and counter are
transition of the external source) applied to the TIMER Input Inttlallzed With all logical ones, the timer Interrupt request bit

•
pin, or It can be the tnternal ",2 signal When the ",2 signal IS Iblt 7) IS cleared and the timer Interrupt mask bit Iblt611S set

FIGURE 9 - TIMER BLOCK DIAGRAM

Timer
Interrupt Not
TIMER Mask
Input
Pin
r------,
I I
IL______ I!
Manufacturing
Mask Options
Write Read Wnte Read

Internal Data Bus

SELF-CHECK clear If any error IS detected, otherWise the l-blt IS set The
The self-check capability of the MC6805U2 MCU proVides walktng diagnostic pattern method IS used
an tnternal check to determtne If the part If functional Con- The RAM test must be called With the stack pOinter at
nect the MCU as shown In Figure 10 and monttor the output $07F When run, the test checks every RAM cell except for
of Port C bit 3 for an OSCillation of approximately 7 Hz A 9 $07F and $07E which are assumed to contain the return
volt level on the TIMER tnput, ptn 8, energIZes the ROM- address
based self-check feature. The self-check program exercises The A and X registers and all RAM locations except the
the RAM, ROM, timer, interrupts, and 110 ports top two are modified
Two of the self-check subroutines (the RAM and ROM ROM CHECKSUM SUBROUTINE - The ROM self-check
tests) can be called by a user program With a JSR or BSR In- IS called at location $F8A and returns With the l-blt cleared If
struction. The timer routine may also be called If the timer In- any error was found, otherwise l= 1 X= 0 on return, and A
put IS the Internal ",2 clock. IS zero If the test passed RAM locations $040-$043 are over-
RAM SELF-CHECK SUBROUTINE - The RAM self- wrttten. The checksum IS the compliment of the exclUSive
check IS called at location $F6F and returns with the l-blt OR of the contents of the user ROM

4·249
 MC6805U2

TIMER SELF-CHECK SUBROUTINE - The timer self- necessary

check IS called at location $FCF and returns with the Z-blt The A and X register contents are lost The timer self-
cleared If any error was found, otherwise Z = 1 check routine counts how many times the clock counts In
In order to work correctly as a user subroutine, the Internal 128 cycles The number of counts should be a power of two
</>2 clock must be the clocking source and Interrupts must be since the prescaler IS a power of two If not, the timer
disabled Also, on eXIt, the clock IS running and the Interrupt probably IS not counting correctly The routine also detects a
mask not set so the caller must protect from Interrupts If timer which IS not running

FIGURE 10 - SELF-CHECK CONNECTIONS

RESET r-:l.
-
.1
r
1 40
VSS PA7
10-"- 39
MC6805U2 PA6
I'F'T"
2 RESET
PA5 ~
3 INT

4 VCC
PA4 PL

•
525 -L 1O I'F PA3 36
5
:r: ..L '5 .4:,
EXTAL
PA2 35
- If::;
- 4~ XTAL
MHz
PAl 34
33
7 NUM PAO
10 k
8 TIMER
+ 9V LED :tJ. 510
9 PCO PB7
32
LEDl!. 5~ll" " 10 PCl PB6 31
510
"1ED.l!." 11 PC2 PB5 ~
LEDL!. • ~10;""
...-. -"""
12 PC3 PB4 ~
c.l,;l PC4 PB3 28
'----.l.1 PC5 PB2 27
15 PC6 PBl ~ f--
16 PC7 PBO
F
,----l1 PD7
.1§ PD6111NT21 POO
24

19 PD5 23

T
POl
01 22
PD2
20 PD4 PD3 21

.J-
• ThiS connection depends on clock oscillator user selectable mask. option Use Jumper If the RC mask option IS selected
LED Meamnas
CO Cl C2 C3 Ramarl<s [1:LED ON; O:LED OFF[
1 0 1 0 Sad 110
0 0 1 0 Bad Timer
1 1 0 0 Sad RAM
0 1 0 0 Sad ROM
1 0 0 0 Sad AID
0 0 0 0 Bad Interrupts or Request Flag
All Flashlnn Good Part
Anything else bad Part, Sad Port 3, Sad ISP, etc

4-250
MC6805U2

RESETS prOVides sufficient delay See Figure 17 for the complete

reset sequence
The MCU can be reset three ways by Initial power-up, by
INTERNAL CLOCK GENERATOR OPTIONS
the external reset Input IRESET), and by an optional Internal
low-voltage detect CIrCUit, see Figure 11 The Internal CIrCUit The Internal clock generator CIrCUit IS deSigned to reqUire a
connected to the RESET pin consists of a Schmitt trigger minimum of external components A crystal, a resistor, a
which senses the RESET line logiC level The Schmitt trigger lumper Wile, or an external Signal may be used to cootrol the
Internal clock generator with vanous stabll,tyl cost tradeoffs
provl~ Internal reset voltage It If senses a logical 0 on
the RESET pin DUring power-up, the Schmitt trigger A manufactUring mask option IS used to select the crystal or
sWitches on Iremoves reset) when the RESET pin voltage resistor option The oscillator frequency IS Internally diVided
by four to produce the Internal system clocks
rises to VIRES + When the RESET pin voltage falls to a
logical 0 for a period longer than one tcyc, the Schmitt trig- The different connection methods are shown In Figure 14
ger sWitches off to provide an Internal reset voltage The The Crystal speCifications are given In F,gu,e 15 A resistor
"switch off" voltage occurs at VIRES- A tYPical reset selection graph IS shown In Figure 16
Schmllt trigger hysteresIs curve IS shown In Figure 12 The crystal OSCillator start-up time IS a function of many
variables crystal parameters (espeCially Rs) OSCillator load
Upon power-up, a delay of tRHL milliseconds IS needed capaCitances, IC parameters, ambient temperatures, supply
before allOWing the RESET Input to go high ThiS time allows voltage, and supply voltage turn-on time To ensure rapid
the Internal clock generator to stabilIZe Connecting a OSCillator start-up, neither the crystal characteristics nor the
capacitor to the RESET Input as shown In Figure 13 tYPically load capacitances should exceed recommendations

5V
VCC
OV-------J

RESET
FIGURE tl - POWER AND RESET TIMING

•
Pin
---------------¥
Internal
Reset _ _ _ _ _ _ _ _ _ _ _....J

FIGURE 12 - TYPICAL RESET SCHMID

TRIGGER HYSTERESIS FIGURE 13 - POWER UP RESET DELAY CIRCUIT

Out
Of I
Reset
VCC _-"-V\.I\r_+=2=a_~
:::r: 1.0 ~F

Part Of
MC6805U2
MCU
In
Reset
oav 2V 4V

4-251
 MC6805U2

FIGURE 14 - CLOCK GENERATOR OPTIONS

5 XTAL XTAL

ISeeNotel c:::J MC6805U2 MC6805U2

4 MCU 4 EXTAL MCU
EXTAL
I Crystal Mask (Resistor Mask
CL ::r: OptIOn I Option)

Crystal Approximately 25 % Accuracy

TYPical tCYC~ 1 25 ~s
External Jumper

+5V
5 XTAL XTAL
R MC6805U2
External MC6805U2
4 ISee Figure 161 4 EXTAL MCU
Clock EXTAL MCU
(Resistor Mask
Input I Crystal Mask No
Option I
Optlonl Connection

II External Clock

a
Approximately 10% Accuracy
External Resistor
(Excludes Resistor Tolerance)
NOTE The recommended CL value with a 4 MHz crystal IS 27 pf, maXImum, including system distributed capacitance There IS an rnternal
capacitance of approXimately 25 pf on the XTAL Pin For crystal frequencies other than 4 MHz, the total capacitance on each, prn
should be scalled as the Inverse of the frequency ratto For example, with a 2 MHz crystal, use approXimately 50 pF on EXTAL and
approXimately 25 pF on XTAL The exact value depends on the Motional-Arm parameters of the crystal used

FIGURE 15 - CRYSTAL MOTIONAL ARM PARAMETERS

AND SUGGESTED PC BOARD LAYOUT
Crystal Motional Arm

EqUIVEa:~~:~~ XTAL

5 ~E---J 6

AT - Cut Parallel Resonance Crystal

Co~7 pF Max
lal FREQ~4 0 MHz @ CL ~24 pF
RS ~ 50 ohms Max Ibl

Note Keep crystal leads and Circuit connectIons as short as possIble

4-252
MC6805U2

FIGURE 16 - TYPICAL FREQUENCY SELECTION FOR INTERRUPTS

RESISTOR OSCILLATOR OPTION The MC6805U2 MCU can be Interr~ed four different
50 ways through the external mterrupt (lNT) mput pm, the

\ VCC=5 V
I 1 mternal timer mterrupt request, the external port D bit 6
(lNT2) Input pin, and a software Interrupt Instruction (SWIl.
40 f-- When any mterrupt occurs, processmg IS suspended, the
TA=25'C
N
present CPU state IS pushed onto the stack, the mterrupt bit

'"
J:
::; (I-bit) m the Condition Code Register IS set, the address of
;: 30 the mterrupt routme IS obtained from the appropriate Inter-
u "-
z
UJ

is 20
I'-..r--, rupt vector address, and the Interrupt routine IS executed
Stacking the CPU registers, settmg the I-bit and vector
.......... fetchmg reqUIres a total of 11 tcyc periods for completion
...
UJ
a:
.........
.........
10
..... Refer to Figure 17 for a flowchart The Interrupt service
routmes must end With a Return from Interrupt (RTIl mstruc-
tIon which allows the MCU to resume processmg of the pro-
10 15 20 25 30 35 40 45 50 55 60 gram prior to the mterrupt Table 1 provides a listmg of the
mterrupts,thelr PriOrity, and the address of the vector which
RESISTANCE Ik OHMS)

FIGURE 17 - RESET AND INTERRUPT PROCESSING FLOWCHART

•
Slack
CLR INT LogiC PC, X, A, CC
FF- Timer
7 F-Prescaler
7F- TCR
7F-MR

Tont'r

Pul on FFE
Address Bus

Timer
or iiii'l1 FF8/FF9
Felch
Instruction

PC_PC+ll-...:S",W.:.;I.-J

Load PC
from
FFE/FFF
Execute
Instruction

4-253
 MC6805U2

contains the starting address of the appropriate Interrupt ser- quest bit (bit 71 and a mask bit (bit 61 located In the
vice routine The Interrupt PriOrity applies to those pending Miscellaneous Register (MRI, refer to Figure 18 The INT2
when the CPU IS ready to 'accept an Interrupt or a new inter- Interrupt IS inhibited when the mask bit IS set The I'/iITI IS
rupt RESET IS listed In Table 1 because It IS processed always readable as a digital Input of Port D The INT2 and
slmlliar to an Interrupt However, It IS not normally used as timer Interrupt request bitS, It set, causes the M CU to pro-
an Interrupt When the Interrupt mask bit In the Condition cess an Interrupt when the condition code I-bit IS clear
Code Register IS set the Interrupt IS latched for later Interrupt
execution

NOTE TABLE I - INTERRUPT PRIORITIES

The timer and INT2 share the same vector address Interrupt Prior~y Vector Address
The Interrupt routine must determine the source by RESE'f 1 SFFE and SFFF
examining the I~terrupt request bits (TCR7 and MR71 SWI 2" SFFC and SFFD
Both TCR7 and MR7 can only be written to 0 by soft- INT 3 SF FA and SFFB
ware TlMERIINT2 4 SFF8 and $FF9

* Prlonty 2 applies when the I-bit In the Condition Code Register IS

The external Interrupts, INT and INT2, are set on the fail- set When 1=0, SWI has a Priority of 4, like any other tnstructlo:-;,
Ing edge of the Input signal The iIiITI has an Interrupt ra- the Priority of iNT thus becomes ~ and the timer becomes 3

• III Write Only, reads as aliI's

FIGURE 18 - MCU REGISTER CONFIGURATION
PORT DATA DIRECTION REGISTER IDDRI

121 1 = Output, 0= Input Cleared to 0 by Reset

o
TIMER CONTROL REGISTER ITCRI

6 5 4 3

TCR7 - Timer Interrupt Request Status Bit Set when

TDR goes to zero, must be cleared by software
o

131 Port A Addr = $004

Cleared to 0 by Reset
Port B Addr = $005
TCR6- Timer Interrupt Mask Bit I = timer inter-
Po·t C Addr = $006
Port D Addr= None, Port D IS Input only rupt masked Idlsabledl Set to 1 by Reset
TCR3- Clear Prescaler Always reads as a 0, clears pre-
scaler when wntten to a logiC 1
TCR Bits 5,4,2, 1,0 reads l's - unused bits
PORT DATA REGISTER
7 o
TIMER DATA REGISTER ITORI

Port A Addr = Sooo

Port B Addr= SOOI
MSB LSB IS008
Port C Addr = S002

MISCELLANEOUS REGISTER IMRI

6543210

1 I I I
1 1 1 1 I I SOOA

MR7 Bit 7-iNi'2 Interrupt Request Bit Set when fail-

Ing edge detected on iiiiTI pin, must be
cleared by software Cleared to 0 by Reset
M R6 Bit 6 - iNTI: Interrupt Mask Bit 1 = iliiT:2 Interrupt
masked Idlsabledl Set to 1 by Reset
MR B;ts 5,4,3,7,1 0- Read as 1's - unused bits

4·254
MC6805U2

A sinusoidal Input signal IflNT maXimum) can be used to tlonallnput pin All pins on ports A. B, and C are program-
operate an external Interrupt liNT), as shown In Figure 19, mable as either Inputs or outputs under software control of
for use as a Zero-Crossing Detector with hysteresIs Included the corresponding Data Direction Registers IDDRsl The
An Interrupt request IS gAnerated for each negative-slope, port 1/0 programming IS accomplished by setting the cor-
zero crossing of the AC signal For digital applications, the responding bit In the port DDR to a logiC "1" for output or a
TNT can be driven directly by a digital signal at a maXimum lOgiC "0" for Input On reset all the DDRs are Initialized to a
period of trWL This allows applications such as servIcing logiC "0" state, plaCing the ports In the Input mode The port
tlme-of-day routines and engaging! disengaging AC power output registers are not Initialized on reset and should be
control deVices Off-chip full wave rectificatIOn provides an Initialized by software before changing the DDRs from Input
Interrupt at every zero crossing of the AC signal and thereby to output When programmed as outputs, all 1/0 pinS read
provide a 2f clock latched output data, regardless of the logiC levels at the out-
A software Interrupt ISWI) IS an executable Instruction put Pin due to output loading, refer to Figure 20
which ,s executed regardless of the state of the I-bit In the All Inputloutput lines are TTL compatible as both Inputs
ConditIOn Code Register SWI s are usually used as break- and outputs Port A lines are CMOS compatible as outputs
pOints for debugging or as system calls uSing a mask option Port B, C, and D lines are CMOS com-
patible as Inputs Port D lines are Input only, thus, there IS no
INPUTIOUTPUT corresponding DDR When programmed as outputs, Port B
There are 32 Input or Input/output pinS The INT pin may IS capable of Sinking 10 milliamperes and SOurcing 1 0
also be polled with branch instructIOns to provide an add 1- milliampere on each pin

FIGURE 19 - TYPICAL INTERRUPT CIRCUITS

AC
AC
Inpui
(tiNT Max)
R", 1 Mn
Inpur", 10 Vpp
a -

Limiting)
Zero Crossing Interrupt

iCurreflt

--'\III'v~-r;"'----'--l
~ 011'F
MC6805U2
MCU
TTL
b -

Level
Digital Signal Interrupt

47 K

Dlglral---4"'~
Input
ItlWL MaXimum
VCC

iN'f
MC6805U2
MCU
•
Period)

FIGURE 20 - TYPICAL PORT 110 CIRCUITRY

Dara
DireCtion Register
Bll*

Latched
Output
Data
Sir

Data
Direction Output Input
Register Data Output To * DOR a write-only register and reads as all "s
IS
Brt Brt State MCU ** Ports A (With CMOS drive disabled), 8, and C are three-state
1 0 0 o ports Port A has optional Internal pull up deVices 10 proVide CMOS
1 1 dllve capability See Electncal CharacterIstIcs tables for complete
o X 3-5ta1.** informatIon

4-255
 MC6805U2

Figure 21 provides some examples of port connections. bits would be setl. It IS recommended that all
The Address Map In Figure 6 gives the addresses of data DDR bits In a port be written usong a single-store
registers and DDRs. The Register Configuration IS provided instruction.
in Figure 18 The latched output data bit (see Figure 181 may always be
wrotten Therefore, any wrote to a port wrotes all of ItS data
CAUTION bits even though the port DDR IS set to Input ThiS may be
The corresponding DDRs for Ports A, B, and C used to initialize the data registers and aVOid undefined out-
are wrote-only registers (iocatlons $004, $005, and puts However, care must be exercised when uSing
$0061. A read operation on these registers is read/modify/wrote Instructions sonce the data read cor-
undefined. Since BSET and BClR are responds to the pon level If the DDR IS an onput (01 and cor-
read/modify/wrote functions, they cannot be responds to the latched output data when the DDr IS an out-
used to set or clear a DDR bit (all "unaffected" put (1)

FIGURE 21 - TYPICAL PORT CONNECTIONS

a. Output Modes

PA7 40 ICMOS Loadsl PB7 32

PA6 39 PB6 31
PA5
PM
38
37

- 11 TTL Loadl
PB5
PB4
30
29
_Ib
10 rnA

•
PA3 36 1 6mA PB3 28
'-"\A""+-'V\A~. 2N6386 !TYPIcal)
PA2 35 PB2 27
PAl 34 PBl 26
Port A. BIt 7 Programmed as Output, DriVIng
PAO 33 CMOS Loads and Bit 4 one TTL Load DIrectly PBO 25
(Using CMOS Output OptIon)
Port S, BII 5 Programmed as Output. Dnvlr'9
Darlington-Base Directly

PCl 16
PB7 32
+ V
PC6 15
PB6 31
PB5 30 PC5 14

PB4 29 PC4 13

PC3 12
PB3 28 CMOS Inverter
PC2 11 MC14049 14069
PB2 P ,TYPical)
PCl 10
PBl 28
PBO 25 PCO

Port B, BIt 0 and Bit 1 Programmed as Output, Dnv- Port C. Blis 0-3 Programmed as Output DriVing
Ing LEOs DIrectly CMOS Loads. Usmg External Puliup ReSistors

b. Input Modes
PA7
PBl
PA6
PB6
38 PA5
30 PB5
37 PA4
29 PB4
MC74LS04 nYPlcall • MCl4lS04 oc MC14069
36 PA3
(TYPIcal! 2B PB3
35 PA2
27 PB2

PB1
PBO
PC?

TTL Dnvmg Port A Directly PC6

14 PC5

13 PC4

12 PC3

11 "C2

10 PC1

PCO

i-:-YPlcall CMOS and TTL Drtvlng Port C Directly

4-256
MC6805U2

BIT MANIPULATION
The MC6805U2 MCU has the ability to set or clear any control lines
single RAM or Input/output bit (except the Data Direction The coding example In Figure 22 illustrates the usefulness
Registers, see Caution under INPUT/OUTPUT paragraph! of the bit manipulation and test instructions Assume that
with a single instruction (BSET, BCLR! Any bit In page zero the MCU IS to communicate with an external serial device
including ROM, except the DDRs, can be tested uSing the The external device has a data ready signal, a data output
BRSET and BRCLR instructions and the program branches line, and a clock line to clock data one bit at a time, LBS first,
as a result of ItS state The carry bit (C! equals the value of out of the device The MCU walls until the data IS ready,
the bit referenced by BRSET and BRCLR The capability to clocks the external device, picks up the data In the Carry Flag
work with any bit In RAM, ROM, or I/O allows the user to IC-bltl, clears the clock line and finally accumulates the data
have individual flags In RAM or to handle single I/O bits as bits In a RAM location
FIGURE 22 - BIT MANIPULATION EXA MPLE
MCU
BRSET 2,PORTA~ WAIT FOR READY Ready I--
2P
Serial 0
* BSET 1, PORTA CLOCK NEXT BIT IN
DeVice Clock
1 R
BRClR 0, PORTA, NEXT PICKUP BIT IN C-BIT
NEXT BClR 1, PORTA RETURN CLOCK LINE HIGH T
ASR RAMlOC MOVE C-BIT INTO RAM Data
°A
~

ADDRESSING MODES
The MC6805U2 MCU has 10 addreSSing modes available
for use by the programmer They are explained briefly In the
follOWing paragraphs For additional details and graphical Il-
lustrations, refer to the M6805 Family User Manual
The term "effective address" (EA!ls used In describing the
addreSSing modes EA IS defined as the address from which
the argument for an instruction IS fetched or stored
IMMEDIATE - In the Immediate addreSSing mode, the
INDEXED, NO OFFSET - In the Indexed, no offset
addreSSing mode, the effective address of the argument IS
contained In the 8-blt Index register Thus, thiS addreSSing
mode can access the first 256 memory locations These in-
structions are only one byte long ThiS mode IS often used to
move a pOinter through a table or to hold the address of a
frequently referenced RAM or I/O location
INDEXED, 8-BIT OFFSET - In the Indexed, 8-blt offset
addreSSing mode, the effective address IS the sum of the
•
operand IS contained In the byte Immediately following the contents of the unsigned 8-blt Index register and the unsign-
opcode The Immediate addreSSing mode IS used to access ed byte follOWing the opcode ThiS addreSSing mode IS
constants which do not change dUring program execution useful In selecting the kth element In an n element table
Ie g , a constant used to initialIZe a loop counter! With thiS 2-byte InstructIOn, k would tYPically be In X With
DIRECT - In the direct addreSSing mode, the effective the address of the beginning of the table In the instruction
address of the argument IS contained In a single byte follow- As such tables may begin anywhere Within the first 256
Ing the opcode byte Direct addreSSing allows the user to addressable locations and could extend as far as location 511
directly address the lowest 256 bytes In memory with a single ($1 FE!
2-byte instructIOn ThiS address area Includes all on-chip INDEXED, 16-BIT OFFSET - In the Indexed, 16-blt offset
RAM and I/O registers and 128 bytes of ROM Direct addreSSing mode, the effective address IS the sum of the
addreSSing IS an effecllve use of both memory and time contents of the unsigned 8-blt Index register and the two un-
EXTENDED - In the extended addreSSing mode, the ef- signed bytes follOWing the opcode ThiS addreSSing mode
fective address of the argument IS contained In the two bytes can be used In a manner Similar to Indexed, 8-blt offset ex-
following the opcode Instructions with extended addreSSing cept that thiS 3-byte Instruction allows tables to be anywhere
mode are capable of referenCing arguments anywhere In In memory As With direct and extended, the Motorola
memory With a Single 3-byte InstructIOn When uSing the assembler determines the shortest form of Indexed address-
Motorola assembler, the user need not specify whether an Ing
Instruction uses direct or extended addreSSing The BIT SET/CLEAR - In the bit setlclear addreSSing mode,
assembler automatically selects the shortest form of the in- the bit to be set or cleared IS part of the opcode, and the byte
struction follOWing the opcode specifies the direct address of the byte
In which the specified bit IS to be set or cleared Thus, any
RELATIVE - The relative addreSSing mode IS only used In
read/Write bit In the first 256 locations of memory, including
branch Instructions In relative addreSSing, the contents of
I/O, can be selectively set or cleared With a Single 2-byte in-
the 8-blt signed byte follOWing the opcode (the offset! IS
struction See Caution under INPUT IOUTPUT paragraph
added to the PC If, and only if, the branch condition IS true
OtherWise, control proceeds to the next InstructIOn The BIT TEST AND BRANCH - The bit test and branch
span of relative addreSSing IS from + 129 to - 126 from the addreSSing mode IS a combination of direct addreSSing and
opcode address, The programmer need not worry about relative addreSSing The bit which IS to be tested and condi-
calculating the correct offset If he uses the Motorola tion (set or clear) Included In the opcode, and the address of
assembler, since It calculates the proper offset and checks to the byte to be tested IS In the Single byte Immediately follow-
see If It IS Within the span of the branch Ing the opcode byte The signed relative 8-bll offset In the

4-257
 MC6805U2

third byte IS added to the PC If the specified bit IS set or clear ed .from memory uSing one of the addressing modes The
In the specified memory location This single 3-byte instruc- lump uncondltlonallJMP) and jump to'subroutlne IJSR) in-
tion allows the program to branch based on the condition of structions have no register operand Refer to Table 2
any readable bit In the first 256 location of memory The span READ/MODIFY/WRITE INSTRUCTIONS - These in-
of branching IS from + 130 to -125 from the opcode structions read a memory location or a register, modify or
address The state of the tested bit IS also transferred to the test Its contents, and wnte the modified value back to
Carry bit of the CondlllOn Code Registers See Caution memory or to the register; see Caution under INPUT /OUT-
Linder INPUT/OUTPUT paragraph PUT paragraph The test for negative or zero (TST) Instruc-
INHERENT - In the Inherent addressing mode, all the in- lion IS Included In the read/modlfy/wnte instruction though
formation necessary to execute the Instruction IS contained It does not perform the write Refer to Table 3
In the opcode Operations specifYing only the Index register BRANCH INSTRUCTIONS - The branch InstrucllOns
or accumulator, as well as control instructions with no other cause a branch from the program when a certain condition IS
arguments, are Included In this mode These instructions are met Refer to Table 4
one byte long BIT MANIPULATION INSTRUCTIONS - The instruc-
INSTRUCTION SET tions are used on any bit In the first 256 bytes of the memory,
see Caution under INPUT/OUTPUT paragraph One group
The MC6805U2 MCU has a set of 59 baSIC InstrucllOns,
which when combined with the 10 addressing modes pro- either sets or clears The other group performs the bit test
and branch operations Refer to Table 5
duce 207 usable opcodes They can be diVided Into five dif-
ferent types register/memory, read/modlfy/wnte, branch, CONTROL INSTRUCTION - The control Instructions
bit manipulation, and control The following paragraphs control the M CU operations dunng program execution

•
briefly explain each type All the instructions within a given Refer to Table 6
type are presented In individual tables ALPHABETICAL LISTING - The complete instruction set
REGISTER/MEMORY INSTRUCTIONS - Most of these IS given In alphabetical order In Table 7
instructions use two operands One operand IS either the ac- OPCODE MAP - Table 8 IS an opcode map for the In-
cumulator or the Index register The other operand IS obtaln- strucllOn used on the MCU

4-258
 TABLE 2 - REGISTER/MEMORY INSTRUCTIONS
3::

Function
00
Mnemonic Code Bytes
Immediate

• •
Cycles
00
Direct

Code Bytes
• •
Cycles
Op •
Addressing Modes

Extended

Code Bytes Cycles

• Op
Indexed
(No Offset)

•
Code Bytes Cycles
• Op
Indexed
(8 SIt Offset)

•
Code Bytes Cycles
• OP
Code Bytes
Indexed
(16 B,t Offset)

• •
Cycles
i
cN
Load A from Memory LOA A6 2 2 B6 2 4 C6 3 5 F6 1 4 E6 2 5 D6 3 6
load X from Memory LOX AE 2 2 BE 2 4 CE 3 5 FE 1 4 EE 2 5 Df 3 6
Store A In Memory STA B7 2 5 C7 3 6 F7 1 5 E7 2 6 D7 3 7
Store X In Memory STX BF 2 5 CF 3 6 FF 1 5 EF 2 6 OF 3 7
Add Memory to A ADD AB 2 2 BB 2 4 CB 3 5 FB 1 4 EB 2 5 DB 3 6
Add Memory and
Carry to A ADC A9 2 2 B9 2 4 C9 3 5 F9 1 4 E9 2 5 D9 3 6
Subtract Memory SUB AO 2 2 BO 2 4 CO 3 5 FO 1 4 EO 2 5 DO 3 6
Subtract Memory from
A With Borrow SBC A2 2 2 B2 2 4 C2 3 5 F2 1 4 E2 2 5 02 3 6
AND Memory to A AND A4 2 2 B4 2 4 C4 3 5 F4 1 4 E4 2 5 04 3 6
O~ Memory With A ORA AA 2 2 BA 2 4 CA 3 5 FA 1 4 EA 2 5 DA 3 6
Exclusrve OR Memory
With A

ArithmetiC Compare A
EOA A8 2 2 BB 2 4 CB 3 5 F8 1 4 EB 2 5 DB 3 6 I
With Memory
Anthmellc Compare X
CMP Al 2 2 Bl 2 4 Cl 3 5 F1 1 4 El 2 5 Dl 3 6 I
~ With Memory CPX A3 2 2 B3 2 4 C3 3 5 F3 1 4 E3 2 5 D3 3 6 I
r\l BII Test Memory With I
C1I
<0
A (Logical Compare) BIT A5 2 2 B5 2 4 C5 3 5 F5 1 4 E5 2 5 05 3 6 I
Jump Unconditional JMP BC 2 3 CC 3 4 FC 1 3 EC 2 4 DC 3 5
Jump to Subroutine JSR - BD 2 7 CD 3 8 FD 1 7 ED 2 8 DD 3 9J
TABLE 3 - READ/MODIFY/WRITE INSTRUCTIONS

AddreSSing Modes
Indexed Indexed
Inherent (A) Inherent (X) Direct (No Offset) (8 Bit Offset)

Function
00
Mnemonic Code Bytes
• •
Cycles
Op
Code Bytes
• • Op •
Cycles Code Bytes Cycles
• Op
Code Bytes
• •
Cycles
Op
Code Bytes
• •
Cycles
Increment INC 4C 1 ·4 5C 1 4 3C 2 6 7C 1 6 6C 2 7
Decrement DEC ·4A 1 4 5A 1 4 3A 2 6 7A 1 6 6A 2 7
Clear CLR 4F 1 4 5F 1 4 3F 2 6 7F 1 6 6F 2 7
Complement COM 43 1 4 53 1 4 33 2 6 73 1 6 63 2 7
Negate
(2 s Complement) NEG 40 1 4 50 1 4 30 2 6 70 1 6 60 2 7
Rotate Left 1 hru Carry ROL 49 1 4 59 1 4 39 2 6 79 1 6 69 2 7
Rotale RIght Thru Carry ROA 46 1 4 56 1 4 36 2 6 76 1 6 66 2 7
LogIcal ShIft Left LSL 4B 1 4 58 1 4 38 2 6 78 1 6 6B 2 7
LogICal Shift RIght LSR 44 1 4 54 1 4 34 2 6 74 1 6 64 2 7
AnthmetlC Shdt R!ght ASR 47 1 4 57 1 4 37 2 6 77 1 6 67 2 7
Test for Negat!ve
TST 4D 1 4 5D 1 4 1 6D
or Zero
.- - }~- 2 6 70 6
---- -
2
~--

II
 MC6805U2

TABLE 4 - BRANCH INSTRUCTIONS

Relative Addressing Mode

Op # #
Function Mnemonic Code Bytes Cycles
Branch Always BRA 20 2 4
Branch Never BRN 21 2 4
Branch IFFHrgher BHI 22 2 4
Branch IFF Lower or Same BlS 23 2 4
Branch IFFCarry Clear BCC 24 2 4
(BranchlFFHlgher or Samel (BHSI 24 2 4
Branch IFF Carry Set BCS 25 2 4
(Branch IFF lower) (BLOI 25 2 4
Branch IFF Not Equal BNE 26 2 4
Branch IFF Equal BEG 27 2 4
Branch IFF Half Carry Clear BHCC 28 2 4
Branch IFF Half Carry Set BHCS 29 2 4
BranchlFF Plus BPl 2A 2 4
Branch IFF Minus BMI 2B 2 4
Branch IFF Interupt Mask

•
Bit IS CI~ar BMC 2C 2 4
Branch IFF Interrupt Mask
Bit IS Set BMS 20 2 4
Branch IFF Interrupt Line
IS Low Bil 2E 2 4
Branch IFF Interrupt Line
15 High BIH 2F 2 4
Branch to SubroLltlne BSA AD 2 8

TABLE 5 - BIT MANIPULATION INSTRUCTIONS

AddreSSing Modes
Bit SeliC lear Bit Test and Branch
Op # # Op # t
FunctIon MnemOniC Code Bytes Cycles Code Bytes Cycles
Branch IFF BIt n IS set BRSET n (n 00 71 -- - - 2.n 3 10
Branch IFF Bit n IS clear BRClR n (n 0 0 71 - - - 01 . 2. n 3 10
Set Bit n BSET n (n 00 71 10 + 2. n 2 7 - - -
Clear bit n BClR n (n 00 71 11 + 2. n 2 7 - - -

TABLE 6 - CONTROL JNSTRUCTIONS

Inherent
Op # #
Function MnemOniC Code Bytes Cycles
Transfer A to X TAX 97 1 2
Transfer X to A TXA 9F 1 2
Set Carry Bit SEC 99 1 2
Clear Carry Bit ClC 98 1 2
Set Interrupt Mask 81t SEI 9B 1 2
Clear Interrupt Mask 81t CLI 9A 1 2
Software Interrupt SWI 83 '1 11
Return from Subroutine RTS 81 1 6
Return from Interrupt RTI 80 1 9
Reset Stack POinter RSP 9C 1 2
No-Operaflon NOP 90 1 2

4·260
MC6805U2

TABLE 7 - INSTRUCTION SET

Addressing Modes Condition Code

Bit Bit
Indexed Indexed Indexed Set I Test &
Mnemonic Inherent Immediate Direct Extended Relative (No Offset) (B Bits) (16 Bits) Clear Branch H I N Z C
ADC X X X X X X
"•"" "
"• •• " "
ADD X X X X X X
AND X X X X X X
•"
ASl X X X X
• • "" "" "
ASR X X X X
•• ""
BCC X
•••• •"
BClR X
•••• •
BCS X
•••• •
BEQ X
•••• •
BHCC X
•••• •
BHCS X
•••• •
BHI X
•••• •
BHS X
•••• •
BIH X
•••• •
•••• •

•
BIL X
BIT X X X X X X
••"" •
BLO X
•••• •
BLS X
•••• •
BMC X
•••• •
BMI
•••• •
BMS
•••• •
BNE
•••• •
BPL
•••• •
BRA
•••• •
BAN
•••• •
BACLR X
•••• "
BRSET X
••••
BSET X
• • • • •"
BSR X
• • • • 0•
CLL X
••••
CLI X
• ••0 •
CLR X X X X
•• 0 1
•
CMP X X X X X X
••"" "
COM X X X X
••"" 1
CPX X X X X X X
••
DEC X X X X
• • "" "" •"
EOR X X X X X X
•• •
INC X X X X
• • "" "" •
JMP X X X X X
•••• •
JSR X X X X X
•••• •
X X X X X
•• •
• • "" ""
LDA X
LDX X X X X X X
•
LSL X X X X
••"" "
LSR X X X X
•• " 0
"
NEQ X X X X
••""
NOP X
•••• •"
X X X X X
•• •
• • "" ""
ORA X
ROL X X X X
RSP X
Condition Code Symbols
•••• •"
H Half Carry (From Bit 31 C Carry/Borrow
I Interrupt Mask A Test and Set If T rue, Cleared Otherwise
N Negative (Sign B,t) • Not Affected
Z Zero

4·261
 MC6805U2

TABLE 7 - INSTRUCTION SET (CONTINUED)

Addressong Modes CondItIon Code

BIt BIt
Indexed Indexed Indexed Set! Test &
Mnemonic Inherent Immediate Direct Extended Relative (No Offset) (8 Bits) (16 BIts) Clear Branch H I N Z C
RTI X ? ? ? ? ?
RTS X
•••• •
SBC X X X X X X
••"" "
SEC X
•••• 1
SEI X
• ••
1
•
STA X X X X X
••"" •
STX X X X X X
•• •
SUB X X X X X X
• • "" ""
SWI X
• ••
1
•"
TAX X
•• •• •
TST X X X X
••"" •
TXA X
•••• •
Condition Code Symbols

•
H Half Carry (From Bit 3) C Carry! Borrow
I Interrupt Mask 1\ Test and Set If True, Cleared Otherwise
N NegatIve ISlgn Bltl • Not Affected
Z Zero , Load CC RegIster From Stack

4-262
 3:
(')
TABLE 8 - M6805 FAMilY OPCOOE MAP

Bit Manioulation
T8
Branch
R 01 I HA
Read/Modifv/Write
I HI 11 ~. INH
Control
H 1M OIR
RegISter/Memory
EX 1X2 1 IX
~
C
~' rk 0001 ooio ";', 01"00
5
0101 01~O
7
01"
8
1000
9
1001
A
1010
8
lOll
C
1100
0
1101
E
1110 ,,,,
F Hl ___ U;W
N
4 4 3 7 6 6 5 2 4 3 4 5 4 4

J:" 'l'lRSETO'
-BTB 12 BSE1~: BR"",, 2
o NEG '
-DIR 1
NEGA
INH
4 NEGX '
1 INH
12 NEG
IXl 1
NEG
IX
i' RTI
1 IN
SUB
IMM
2 SUB
OIR 3
SUB
EXT
"
3
SUB
IX
SUB
1X1 1
SUB j
IX cJo·
10 5 7 5 4 3 6 6 2 2 4 3 5 4 6 5 5 4 4 3
1 BRCLAO BCLAO RTS CMP CMP CMP CMP CMP CMP 1
0001 3
10
BTB 2
5 7
BSe
5
2
4
BANREL
3
1 INH 2
2
IMM 2
4, DIR
3
3
5
EXT
4
3
6
1X2
5
2
5
IXl
4
I
4
'x3 OOJl

2 BRSET1 BHIREL SBC SBC SBC SBC SBC SBC 2

0010 3 BTB I 2 BSE11e 2 'MM 2 DIR 3 EXT 3 IX2 2 IXI 1 'x 0010
10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 11 10 2 2 4 3 5 4 6 5 5 4 4 3
3 BRCLR1 BCLR1 BLSRfL 2 COMa!R COMA COMX 12 COM COM SWI CPX CPX CPX CPX CPX CPX 3
0011 3 BTB 2 Bse 1 INH 1 I H JX1 1 IX 1 INH 2 IMM 2 D,R 3 EXT 3 1X2 2 'Xl 1 'X 0011
1 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 2 2 4 3 5 4 6 5 5 4 4 3
4 BRSET2 2 BSE1~e LSRA LSRX LSR AND AND AND AND AND AND 4
0100 BTB BCC"L 7 LSRDIR 1 INH 1 INH 2 LSR IXl
1 IX 2 DIR EXT 3 IX2 2 IXl 1 IX 0100
'MM 2 3
10 5 7 5 4 3 2 2 4 3 5 4 6 5 5 4 4 3
5 BRCL~lB , BCL~~c BCSRFL
BI~"M 2 BIT DIR 3
BIT
EXT 3
BIT BIT
IXl 1
BIT
IX
5
0101
0101
4 6
'x 5 3
10 5 7 5 4 3 6 5 4 3 3 7 6 6 5 2 2 4 3 5 4 5 4 4
6 BRSET3 2 BSE1~e BNEREL 2 RORDIR 1 RORA RORX '2 ROR ROR LDA LOA LDA LDA LDA LDA 6
0110 3 BTB INH 1 INH IXl 1 IX 'MM 2 DIR 3 EXT 3 ,X2 2 'Xl 1 IX 0110
1~. 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 2 2 5 4 6 5 7 6 6 5 5 4
STA STA 7
2BCL~~r
7 BRCLR.,J,,- ASR ASRA ASRX ASR ASR TAX STA STA STA ,
0111 3 BT , BEGR" DIR 1 INH 1 INH 2 IXl 1 IX 1 INH 2 DIR 3 EXT 3 'X2 2 ,Xl 1 IX 0111
10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 2 2 2 2 4 3 5 4 6 5 5 4 4 3
1~ 3
BRSET4
BTB 2 BSE11e BHC~EL
2
LSL
DIR 1
LSLA
INH 1
LSLX
INH 2
LSL
IXl 1
LSL
IX
CLC EOR
IMM 2
EOR
DIR 3
EOR
EXT 3
EOR
IX2 2
EOR
IXl , EOR
IX
B
l00J
10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 2 2 2 2 4 3 5 4 6 5 5 4 4 3
9
1001 3
BRCLR4
BTB
, 2 BCL~1e BHC~EL 2 ROLDIR 1
ROLA
INH 1
ROLX
INH 2
ROL
IXl 1
ROL
1
SEC
INH 2
ADC
IMM 2
ADC
DIR 3
ADC
EXT 3
ADC
2
ADC
IXl 1
ADC
IX
9
1001
'X IX'
10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 2 2 2 2 4 5 4
~ ORA' , ORA 5 ORA 4
2 BSE1~e
BRSET5 2 BPLREL 2 DEC DECA DECX DEC DEC CLI ORA ORA ORA A

~
1&;0 BTB DIR 1 INH 1 INH 2 IXl 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 ,X2 2 1 1010 I

B
10
BRCLR5
5 7
BCLR5
5 4
BMI
3
SEI < ADD < 4 ADD 3 5 ADD
4 6
ADD , ADD
'Xl
4 4
ADD
" B I
(,.) 1011 3
10
BTB
5
2
7
BSC
5
2
4
REL
3 6 5 4 3 4 3 7 6 6 5
1
2
INH
2
2 IMM 2
3
DIR 3
4, EXT
3
3
5
IX2
4 4
2 IXl
3
1
3 ,
IX 1011

,~ 3BRSEl~B !2BSEj;~c BMC

REL 2
INC
DIR 1
INCA
INH 1
INCX
INH 2
INC
IXl 1
INC
1
RSP
INH 2
JMP
DIR 3
JMP
EXT 3
JMP
IX' 2
JMP
IXl 1
JMP
IX
C
1100 I
10 _, 7
BRCL~~ I , BCL~~r
5 4 3 6 4 4 3 4 3 7 5 6 "
4 2 2 B 6 7 5 B 6 9 7
, JSR 6
7
D
1101 BM~" TST
2 DIR 1
TSTA
INH 1
TSTX
INH 2
TST
IXl 1
TST
IX 1
NOP
INH 2
BSR
REL 2
JSR
DIR 3
JSR
EXT 3
JSR
1X2 2 IXl 1
JSR '
IX
0
1101
10 5 7 5 4 3 2 2 4 4 4 3
E BIL STOP I' LOX LOX j , LOX LOX , LOX 4 LOX E
1 10 BRSEJIB I 2 BSET7 REL 1 IX
BSe 2 1 INH 2 IMM 2 DIR 3 EXT 3 IXl ') IXl 1110
10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 2 2 2 7 6 6 5 5 4
F BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR WAIT TXA STX o STX STX STX STX F
1111 3 BT~ 2 Bse 2 REL 2 DIR 1 INH 1 INH 2 IXI 1 IX 1 INH 1 INH 2 DIR 3 EXT 3 IX2 2 IXI 1 IX 1111

Abbreviations for Address Modes lEGEND

INH Inherent F Opcode In Hexadecimal

IMM Immediate
1111
# of Cycles (HMOS VerslonSI----l~44--'-:..:..:....::s31-~==:=:;;:f:::::::::-_
DIR Direct
EXT Extended Opcode In Binary
REl Relative MnemOniC ----H~
BSC Bit Setl Clear Bytes -----,l"l~ _ _jL.!~k_-~~~::...J
BTB Bit Test and Branch
IX Indexed (No Offsetl # of Cycles ICMOS Verslonsl------~ " Address Mnrl.p
IXl Indexed. 1 Byte (8-Bltl Offset
IX2 Indexed, 2 Byte (16-B,tl Offset
CMOS Versions Only

•
 MC6805U2

ORDERING INFORM~TION thoroughly checked and the verification form completed,

The Information reqUired when ordering a custom MCU IS Signed, and returned to Motorola The Signed verification
listed below The ROM program may be transmitted to form constitutes the contractual agreement for creation of
Motorola on EPROMls) or an MDOS disk file the customer mask If deSired, Motorola will program one
To Initiate a ROM pattern for the MCU It IS necessary to blank EPROM from the data file used to create the custom
first contact you local Motorola representative or Motorola mask to aid In the verification process
distributor
EPROMs - The MCM2716 or MCM2532 type EPROMs, ROM VERIFICATION UNITS (RVUs)
Ten MCUs containing the customer's ROM pattern will be
programmed with the customer program I positive logiC
sent for program verification These units will have been
sense for address and datal, may be submitted for pattern
ma'de uSing the custom mask but are for the purpose of
generation The EPROM must be clearly marked to Ind;cate
which EPROM corresponds to which address space The ROM verification only For expediency they are usually un-
recommended marking procedure IS Illustrated below marked, packaged In ceramiC, and tested only at room
temperature and 5 volts These RVUs are Included In the
mask charge and are not production parts The RVUs are
xxx thus not guaranteed by Motorola Quality Assurance, and
should be discarded after verification IS completed

FLEXIBLE DISKS
The disk media submitted must be Single-Sided, Single-
denSity, 8-lnch, MDOS compatible floppies The customer

•
must write the binary file name and company name on the
000 400 disk With a felt-tip pen The minimum MDOS system flies as
well as the absolute binary object file I filename LO type of
XXx. = Customer 10 fllel from the M6805 cross assembler must be on the disk An
object file made from a memory dump uSing the ROLLOUT
command IS also acceptable ConSider submitting a source
After the EPROMlsl are marked they should be placed In
listing as well as the follOWing flies filename LX I EXOR-
conductive IC camers and securely packed Do not use
ciser'" loadable format! and filename SA IASCII Source
styrofoam
Codel These flies Will of course be kept confidential and are
VERIFICATION MEDIA used 11 to speed up the process In-house If any problems
arise, and 21 to speed up the user-to-factory Interface If the
All Original pattern media IEPROMs or Floppy Disk) are user finds any software errors and needs assistance qUickly
filed for contractual purposes and are not returned A com- from Motorola factory representatives
puter listing of the ROM code will be generated and returned MDOS IS Motorola's Disk Operating System available on
along With a listing verification form The listing should be development systems such as EXORCisers, EXORsets, etc

4·264
MC6805U2

MC6805U2 MCU ORDERING INFORMATION

Date _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Customer PO Number _ _ _ _ _ _ _ _ _ _ __

Customer Company _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Motorola Part Numbers

Address MC _ _ _ _ _ __
-----------------------------------------------SC
City _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ State _ _ _ _ _ _ _ _ _ _ _ _ _ ZIP _________ -------
Country _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Phone _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Extenslon _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Customer Contact Person _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Customer Part Number

OPTION LIST
Select the options for your MCU from the following list A
manufacturing mask will be generated from this Information

•
Timer Clock Source
o Internal q,2 clock
o TIMER Input pin

Timer Prescaler
o 2° (divide by 11 o 2' (divide by 161
o 2' (divide by 21 o 2' (divide by 321
o 2' (divide by 41 o 2' (divide by 641
o 2' (divide by 81 o 2' (divide by 1281

Internal Oscillator Input Port A Output Drive

o Crystal o CMOS and TTL
o ReSistor o TTL Only

Low Voltage Inhibit

oDisable
oEnable

Pattern Media (All other media requires Prior factory approval)

o EPROMs (MCM2716 or MCM2532 o Floppy Disk
o Other

Clock Freq _ _ _ _ _ _ _ _ _ _ _ _ __

Temp Range _ _ _ _ _ _ _ _ _ _ _ _ _ _ 00° to + 70°C IStandardl o _40° to +85°C~ 0 _40° to + 125°C~

*Requlres prior factory approval

Marking Information (12 Characters MaXimum)

Title _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Slgnature _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

4-265
 MC6809
(1.0 MHz)

@ MOTOROLA MC68A09
(1.5 MHz)

MC68B09
(2.0 MHz)

8-BIT MICROPROCESSING UNIT HMOS

The MC6809 IS a revolutionary high-performance 8-blt microprocessor
which supports modern programming techniques such as position in- (HIGH DENSITY N-CHANNEL. SILICON-GATEI
dependence, reentrancy, and modular programming
This third-generation addition to the M6800 family has major architectural 8-BIT
Improvements which Include additional registers, instructions, and addressing MICROPROCESSING
modes
UNIT
The basIc instructions of any computer are greatly enhanced by the
presence of powerful addressing modes The MC6809 has the most complete
set of addressing modes available on any 8-blt microprocessor today
The MC6809 has hardware and software features which make It an Ideal
processor for higher level language execution or standard controller appllca-
lions

L SUFFIX
CERAMIC PACKAGE
MC6800 COMPATIBLE CASE 715
• Hardware - Interfaces with All M6800 Peripherals
• Software - Upward Source Code Compatible Instruction Set and
Addressing Modes ~
~~ ••• ~
PSUFFIX

•
PLASTIC PACKAGE
ARCHITECTURAL FEATURES , ' ' CASE 711
• Two 16-blt Index Registers

~
• Two 16-blt Indexable Stack POinters
• Two 8-blt Accumulators can be Concatenated to Form One 16-81t
Accumulator SSUFFIX
, I .' • I • CERDIP PACKAGE
• Direct Paqe Reqlster Allows Direct Addressing Throughout Memory , I • CASE 734
HARDVVAREFEATURES
• On-Chip Oscillator (Crystal Frequency=4XEI
• DMA/BREQ Allows DMA Operation on Memory Refresh
• Fast Interrupt Request Input Stacks Only Condllion Code Register FIGURE 1 - PIN ASSIGNMENT
and Program Counter
.MRDY Input Extends Data Access Times for Use with Slow Memory
• Interrupt Acknowledge Output Allows Vectoring 8y Devices Vss
• SYNC Acknowledge Output Allows for Synchronization to External NMi XTAL
Event
TIm EXTAL
• Single Bus-Cycle RESET
• ~Ie 5-Volt SUPPIYR~~Eitlon Fiim mIT
• IIIliilT Inhibited After Until After First Load of Stack POinter BS MROY
• Early Address Valid Allows Use VV,th Slower Memories
• Early VVnte-Data for Dynamic Memories BA

SOFTVVARE FEATURES Vee

• 10 Addressing Modes OMA/BREO
• 6800 Upward Compatible Addres~lng Modes Al R/W
• Direct Addressing Anywhere In Memory Map
• Long Relalive Branches A2
• Program Counter Relative A3
• True Indirect Addressing
A4
• Expanded Indexed Addressing
0-,5-,8-, or 16-blt Constant Offsets
6-, or 16-bIt Accumulator Offsets
D4
Auto-Increment/Decrement by 1 or 2
• Improved Stack Manipulation 05
• 1464 Instructions with Unique Addressing Modes AS 06
• 8 x 8 Unsigned Multiply
07
• 16-bIt Arithmetic
• Transfer/Exchange All Registers A15
• Push/ Pull Any Registers or Any Set of Registers A14
All
• Load Effective Address
A13

4-266
MC6809· MC68A09. MC68B09

MAXIMUM RATINGS
Rating Symbol Value Unit
This deVice contains circuitry to protect the
Supply Voltage Vcc - 03 to + 70 V
Inputs against damage due to high static
Input Voltage V ,n - 03 to + 70 V voltages or electnc fields. however, It IS ad-
Operating Temperature Range TL to TH vised that normal precautions be taken to
MC6809. MC68A09. MC68809 TA o to + 70 'c avoid application of any voltage higher than
MC6809C. MC68A09C. MC68809C - 40 to + 85 maximum rated voltages to thiS high Irn*
Storage Temperature Range T5tg -55 to + 150 DC pedance Circuit Reliability of operation IS
enhanced If unused Inputs are tied to an ap-
THERMAL CHARACTERISTICS propriate logiC voltage levels Ie g, either
VSS or VCCI
Characteristic Symbol Value Unit
Thermal ReSistance
Ceramic 50
8JA 'C/W
Cerdlp 60
Plastic 100

POWER CONSIDERATIONS

The average chlp-lunCtiOn temperature, TJ, In 'c can be obtained from

T J ~ T A + IPO·OJA) III

•
Where
T A'" Ambient Temperature, 'c
OJA'" Package Thermal ReSistance, Junctlon-to-Amblent, °C/W
PO'" PINT+ PPORT
PINT'" ICC x VCe. Watts - Chip Internal Power
PPORT'" Port Power OISSlpatlon, Watts - User Oetermlned
For most applicatIOns PPORT<Ii PINT and can be neglected PPORT may become significant If the deVice IS configured to
drive Oarllngton bases or sink LEO loads.
An approximate relationship between Po and T J Ilf PPORT IS neglected) IS
PO~K-ITJ+273°C) 121
Solving equations 1 and 2 for K gives
K ~ PO·IT A + 273°C) + OJA·P 0 2 (3)
Where K IS a constant pertaining to the particular part K can be determined from equation 3 by measuring Po lat eqUIlibrium)
for a known T A USing thiS value of K the values of Po and TJ can be obtained by solving equations (1) and (2) iteratively for any
value of T A

ELECTRICAL CHARACTERISTICS IVcc~ 5 0 V ± 5% VSS ~ 0 TA ~O to 70'C unless otherwise noted I

Characteristic Symbol Min Typ Max Unit
LogiC, EXTAL VIH VS5 + 20 - VCC
Input High Voltage V
RESET VIHR VSS +4 0 - VCC
Input Low Voltage LogiC. EXT AL, RESET VIL VSS 03 VSS +08 V
Input Leakage Current
IV,n~O to 5 25 V, Vcc~maxl
LogiC lin - - 25 ~A

DC Dutput High Voltage

IILoad~ - 205 ~A, VCC ~ mini DO-D7
VOH
VSS + 24 - - V
IILoad~ -145~A, Vcc~mlnl AO-A15, R/Vi, Q, E VSS + 2 4 - -
"Load~ -100 ~A, VCC~ mini 8A, 85 VSS + 24 - -
DC Output Low Voltage
VOL - - VSS+05 V
IILoad~20 rnA. Vcc~mlnl
Internal Power DISSipation {measured at TA = aoc In steady state operation} PINT - - 10 W
Capacitance #
IVIn~O, TA~25'C. f~1 0 MHzI DO-D7, RESET Cin - 10 15 pF
LogiC Inputs, EXT AL, XT AL - 10 15
AO-A15. R/W. 8A. 8S Cout - - 15 pF
Frequency ~f Operation MC6809 04 - 4
MC68A09 fXTAL 04 - 6 MHz
(Crystal or External Input) MC68809 04 - 8
Three-State IOff Statel Input Current DO-D7 - 20 10
ITSI ~A
IVIn~O 4 to 2 4 V, Vcc~maxi AO-A15, R/W - - 100

# capacitances are penodlcally tested rather than 100% tested

4-267
 MC6809- MC68A09- MC68B09

FIGURE 2 - BUS TIMING

R/VV,Address----t~~~~J\.~~~t_-=~----------_i_r--------------------~------------rt~~~
SA, SS

Read Data ----+--,l MPU Read Data

1}-------4--+------------~~~~--------------~1

~-+----------__ ~~L---~N~0~t~e~3------------~

•
Write Data

--@)----..t

BUS TIMING CHARACTERISTICS ISee Notes 1 and 21

Ident, MC6809 MC68A09 MC68B09
Characteristics Symbol Unit
Number Min Max Min Max Min Max
1 Cycle Time I See Note 51 tcyc 10 10 0667 10 05 10 ~s

2 Pulse Width, E Low PWEL 430 5000 280 5000 210 5000 ns
3 Pulse Width, E High PWEH 450 15500 280 15700 220 15700 ns
4 Clock Rise and Fall Time tr, tf - 25 - 25 - 20 ns
5 Pulse Width, Q High PWQH 430 5000 280 5000 210 5000 ns
6 Pulse Width, a Low PWOL 450 15500 280 15700 220 15700 ns
7 Delay Time, E to Q Rise tAvs 200 250 130 165 80 125 ns
9 Address Hold Time' ISee Note 41 tAH 20 - 20 - 20 - ns
10 SA, 8S, R/W, and Address Valid Time to a Rise tAO 50 - 25 - 15 - ns
17 Read Data Setup Time tDSR 80 - 60 - 40 - ns
18 Read Data Hold Tlme* tDHR 10 10 10 ns
20 Data Delay Time from Q tDDO - 200 - 140 - 110 ns
21 Write Data Hold Time· tDHW 30 - 30 - 30 - ns
29 Usable Access Time ISee Note 31 tACC 695 - 440 - 330 - ns
Processor Control Setup Time IMRDY, Interrupts, DMA/BREO, - - - ns
tpcs 200 140 110
HALT, RESETllFlgures 7,9,10,11,13, and 141
Crystal OSCillator Start Time I Figures 7 and 81 tRC - 100 - 100 - 100 ms
Processor Control Rise and Fall TIme iFlgures 7 and 9) IpCr, tpCf - 100 - 100 - 100 ns

'Address and data hold times are periodically tested rather than 100% tested

NOTES.
1 Voltage levels shown are VL:SO 4 V, VH",2 4 V, unless otherWise specified,
2 Measurement POints shown are 0 8 V and 2 0 V, unless otherWise specified
3 Usable acce~me IS computed by 1-4- 7 max + 10-17
4 Hold time I \211
for SA and SS IS not specified.
5 MaXimum tcyc dUring MRDY or DMA/BREQ IS 16 p.S

4·268
MC6809- MC68A09- MC68B09

FIGURE 3 - MC6809 EXPANDED BLOCK DIAGRAM

<4--Vee
<4--VSS

Instruction
Register

OMA/BREO
R/W

RAC'f
BA

BS
XTAL
•
EXTAL
MROY

L-_-.E
' - - - -... 0
* Internal Three-State Control
FIGURE 4 - BUS TIMING TEST LOAD PROGRAMMING MODEL
As shown In Figure 5, the MC6809 adds three registers to
the set available In the MC6800, The added registers Include
50V a Direct Page Register, the User Stack pOinter and a second
Index Register

ACCUMULATORS (A, S, D)
The A and B registers are general purpose accumulators
which are used for arithmetic calculations and manipulation
of data
e Certain Instructions concatenate the A and B registers to
MMD7000 form a single 16-blt accumulator ThiS IS referred to as the D
or EqUiv Register, and IS formed with the A Register as the most
significant byte

DIRECT PAGE REGISTER (DP)

The Direct Page Register of the MC6809 serves to enhance
C = 30 pF for BA, BS R = 11.7 kll for 00-07 the Direct AddreSSing Mode. The content of thIS register ap-
130 pF for 00-07, E, 0 16.5 kll for AO-A 15, E, 0, R/IN pears at the higher address outputs IA8-A 15) dUring direct
90 pf for AO-A 15, R/IN 24 kll for SA, SS AddreSSing Instruction execution ThiS allows the direct
mode to be used at any place In memory, under program
control To ensure 6800 compatibility, all bits of thiS register
are cleared dUring Processor Reset.

4-269
 MC68Q9-MC68A09-MC68B09

FIGURE 5 - PROGRAMMING MODEL OF THE MICROPROCESSING UNIT

15 o

}~,"",
x- Index Register
Y - Index Register
U - User Stack POinter ",""""
S - Hardware Stack POinter
PC Program Counter

,
A
I B
,
Accumulators
v
D

DP Direct Page Register

7 a
I ElF I I, I I z I v I c I
H N CC - Condition Code Register

• INDEX REGISTERS (X, VI

The Index Registers are used In Indexed mode of address-
Ing. The 16-blt address In this register takes parl In the
calculation of effective addresses This address may be used
to pOlnl to dala directly or may be modlfed by an optional
FIGURE 6 - CONDITION CODE REGISTER FORMAT

Carry
constant or register offset. DUring some Indexed modes, the Overflow
contents of the Index register are Incremented or L.~--Zero
L-_ _ _ _ Negative
decremented to pOint to the next Item of tabular type data
L--_ _ _ _ _ _ IRO Mask
All four pOinter registers IX, Y, U, SI may be used as Index L--_ _ _ _ _ _ _ Half Carry
registers.
L - - - - - - - - - F I R O Mask
STACK POINTER (U, SI L - - - - - - - - - - - E n t l r e Flag
The Hardware Stack POinter (S) is used automatically by
the processor dUring subroutine calls and interrupts. The
stack pOinters of the M C6809 point to the top of the stack, In
contrast to the MC6800 stack pOinter, which pOinted to the
next free location on the stack The User Stack POinter lUl,s
controlled exclusively by the programmer thus allowing CONDITION CODE REGISTER
arguments to be passed to and from subroutines with ease. DESCRIPTION
Both Stack Pointers have the same Indexed mode address- BITO (C)
.ing capabilities as the X and Y registers, but also support
Bit 0 IS the carry flag, and IS usually the carry from the
Push and Pull instructions. ThiS allows the MC6809 to· be us-
binary ALU C IS also used to represent a 'borrow' from sub-
ed efficiently as a stack processor, greatly enhancing ItS abili-
tract like instructions ICMP, NEG, SUB, SBCI and IS the
ty to support higher level languages and modular programm-
complement of the carry from the binary ALU
Ing.

PROGRAM COUNTER BIT 1 (V)

The Program Counter IS used by the processor to POint to Bit 1 IS the overflow flag, and IS set to a one by an opera-
the address of the next instruction to be executed by the pro- tion which causes a signed two's complement arithmetic
cessor. Relative Addressing is provided allOWing the Pro- overflow ThiS overflow IS detected In an operation In which
gram Counter to be used like an index register in some situa- the carry from the MSB In the ALU does not match the carry
tions. from the MSB-l

CONDITION CODE REGISTER BIT2 (Z)

The Condition Code Register defines the State of the Pro- Bit 2 IS the zero flag, and IS set to a one If the result of the
cessor at any given time. See Figure 6. prevIous operation was Identically zero

4·270
MC6809· MC68A09· MC68B09

BIT 3 (N) READ/WRITE (R/W)

Bit 3 IS the negative flag, which contains exactly the value ThiS Signal indicates the direction of data transfer on the
of the MSB of the result of the preceding operation Thus, data bus. A low Indicates that the MPU IS Writing data onto
a negative two's-complement result will leave N set to a one the data bus R/Vii is made high Impedance when BA IS
high. R/Vii IS valid on the r~,ng edge of 0
BIT 4 (I)
Bit 4,s the IRO mask bit The processor will not recognize
Interru~ from the IRO line If thiS bit IS set to a one NMI, RESET
F~RO, IRO, RESET, and SWI are set I to a one, SWI2 and A low level on thiS Schmitt-trigger Input for greater than
SWI3 do not affect I one bus cycle will reset the MPU, as shown In Figure 7 The
Reset vectors are fetched from locations FFFE16 and FFFF16
BIT 5 (H) IT able 1) when Interrupt Acknowledge IS true,
Bit 5 IS the half-carry bit, and IS used to Indicate a carry (BA 0 BS = 11 DUring Initial power-on, the RESET line
from bit 3 In the ALU as a 'result of an 8-blt addition only should be held low until the clock OSCillator IS fully opera-
IADC or ADDI ThiS bit IS used by the DAA instruction to tional. See Figure 8.
perform a BCD decimal add adjust operation The state of Because the MC6809 RESET pin has a Schmitt-trigger in-
thiS flag IS undefined In all subtract-like Instructions put With a threshold voltage higher than that of standard
peripherals, a Simple RIC network may be used to reset the
BIT 6 (FI entire system. ThiS higher threshold voltage ensures that all
peripherals are out of the reset state before the Processor
Bit 6 IS the FIRO mask bit The processor will not
recognIZe Interrupts from the FIRO line If thiS bit IS a one
NMI, FIRO, SWI, and RESET all set F to a one IRO, SWI2
and SWI3 do not affect F

BIT 7 (E)
Bit 7 IS the entire flag, and when set to a one indicates that
HALT
A low level on thiS Input pin will cause the MPU to stop
running at the end of the present Instruction and remain
halted indefinitely Without loss of data. When halted, the BA
output IS driven high indicating the buses are high Im-
I
the complete machine state lall the reglstersl was stacked, pedance. BS IS also high which indicates the processor IS In
as opposed to the subset state (PC and CCI The E bit of the the Halt or Bus Grant state. While halted, the MPU will not
stacked CC IS used on a return from Interrupt (RT!) to deter- respond to external real-time requests (FIRO, iRa) although
mine the extent of the unstacklng Therefore, the current E DMA/BREO will always be accepted, and NMI or RESET will
left In the Condition Code Register represents past action be latched for later response. DUring the Halt state 0 and E
continue to run normally If the MPU IS not running (REm,
DMA/BREO), a halted state (BAoBS = 1) can be achieved
by pulling HALT low while RESET IS still low. If DMA/BREO
and HALT are both pulled low, the processor Will reach the
PIN DESCRIPTIONS
last cycle of the instruction (by reverse cycle stealing) where
the machine Will then become halted See Figure 9.
POWER (VSS, Veel
Two pinS are used to supply power to the part VSS IS BUS AVAILABLE, BUS STATUS (BA, BS)
ground or 0 volts, while VCC IS + 50 V ± 5%
The Bus Available output IS an Indication of an Internal
ADDRESS BUS (AO-A15) control Signal which makes the MOS buses of the MPU high
Sixteen pins are used to output address Information from Impedance. ThiS Signal does not Imply that the bus Will be
the MPU onto the Address Bus When the processor does available for more than one cycle When BA goes low, a
not reqUire the bus for a data transfer, It will output address dead cycle Will elapse before the MPU acqUires the bus
ft!i16, R/Vii = 1, and BS = 0; thiS IS a "dummy access" or
VMA cycle Addresses are valid on the riSing edge of 0 Isee The Bus Status output Signal, when decoded With BA,
Figure 21 All address bus drivers are made high-Impedance represents the M PU state (valid With leading edge of 0)
when output Bus Available (BA) IS high. Each Pin will
drive one Schottky TTL load or four LS TTL loads, and MPU State
MPU State Definition
90 pF BA BS
0 0 Normal IRunnlng)
DATA BUS (00-07)
0 1 Interrupt or Reset Acknowledge
These eight pins prOVide commUnication with the system
1 0 Sync Acknowledge
bi-directlonal data bus. Each pin will drive one Schottky TTL
1 1 Halt or Bus Grant Acknowledge
load or four LS TTL loads, and 130 pF

4-271
 • s:
n
~•
s:

FIGURE 7 - RESET TIMING

I
s:•
VCC
~
OJ
~
Q f~PCS ~~----------------------------~~\
'~~tPCS I
tPCfnT.rynn7~nn~~~~~----------------------____________
RESET f 08 V VIHR VIHA Y S V ~a£.ii'y~lHRtPcs
tRC -I tPCr
NewPC+l
.J>.. Address~~~~~~~~r_--,r-- __ r---,r--_;r_--,r--__ r---;r--__ r_--;r~~~r---\r--~r---\r--__ r_-->r--~r---\r--__ ,r_-->r--__ r--_;r_--'r-
N
....., Bus
FFFE FF .. E FFFE FFFE FFFE FFFF FFFF 'leN PC
I\)
R/iN M\\\\\W;~ New PC __ ~ New PC --
Data HI Byte VMA H, Byte VMA

Bus New PC First New PC First

SA \\\\\'L~~ La Byte Instruction ss La Byte Instruction

BS \\\\\\~ ! \ if ! \'--______
'NOTE: Pans with dat.. codes prefixed by 7F or 5A will come out of RESEi' one cycle sooner than shown
MC6809. MC68A09· MC68B09

FIGURE 8 - CRYSTAL CONNECTIONS AND OSCILLATOR START UP

~ ~
)
( 101
VCC

~CD~
Co

MC6809

•
38 Y1 39
Y1 C,~ Cout
8 MHz
6 MHz
4 MHz
18 pF
20 pF
24 pF
18 pF
20 pF
24 pF
D
Cout

Nominal Crystal Parameters"

3.68 MHz 4.00 MHz 6.0 MHz B.O MHz
RS 600 500 30-500 20-400

Co 35 pF 65 pF 4-6 pF 4-6 pF
C1 0015 pF 0025 pF 001-002 pF 001·002 pF
Q >40K >30K >20 K >20 K
All parameters are 10%
·NOTE These are representative AT-cut crystal parameters only Crystals of other
types of cut may also be used

NOTE Waveform measurements for all Inputs and outputs are specIfied
at logiC high 2 0 V and logiC low 0 8 V unless otherwise specIfied

Other Signals
Not Wifed In
This Area
~

4-273
 MC6809- MC68A09-MC68B09

FIGURE 9 - iiAL'f AND SINGLE INSTRUCTION

EXECUTION FOR SYSTEM DEBUG
2nd To Last
Last Cycle
Cycle Of Of
Current Current Dead Dead Inst Instruction Dead
I..
Inst I
Inst
... I
...Cycle.J
~ .. H
Halted
• •I • •
~CYCle~etch Execute~CYCIP
••I Halted
Q

FiAIT

~--4~---------------~~---­
Address
Bus
Fetch Execute
I ,
R/W
(S
BA 1 \'--____-'1

•
H~--------------~\ I~-------
BS 1
Data
Bus _ _~"L_---1 }---4~-----------<~--­
Instruction
Opcode
NOTE' Waveform measurements for all Inputs and outputs are specified at logiC high 2.0 V and logiC low 0 8 V unless otherwise specified

Interrupt Acknowledge IS Indlca~ur~ot~cles of a Interrupt cannot be Inhibited by the program, and also has a
hardware-vector-fetch (RESET, NMI, FIRO, IRO, SWI, higher Priority than FIRO, iRCi or software Interrupts. DUring
SWI2, SWI3) ThiS signal, plus decoding of the lower four recognition of an NMI, the entire machine state IS saved on
address hnes, can provide the user With an Indication of the hardware stack After reset, an NMI Will not be recogniz-
which Interrupt level IS being serviced and allow vectoring by ed until the first program load of the Hardware Stack POinter
deVice See Table 1 (S) The pulse Width of NMIIow must be at least one E cycle.
Sync Acknowledge IS indicated while the MPU IS waiting If the NMI Input does not meet the minimum set up With
for external synchrOnization on an Interrupt hne. respect to 0, the Interrupt Will not be recognized until the
next cycle See Figure 10
HaitI Bus Grant IS true when the M C6809 IS In a Halt or Bus
Grant condition .

TABLE I: MEMORY MAP FOR INTERRUPT VECTORS FAST-INTERRUPT REQUEST (FIRQI*

Memory Mep For A low level on thiS Input pin Will Initiate a fast Interrupt se-
Vector Locations Interrupt Vector quence, provided ItS mask bit (F) In the CC IS clear. ThiS se-
Description ~ce has Prlonty over the standard Interrupt Request
MS LS (IRQ), and IS fast In the sense that It stacks only the contents
FFFE FFFF REStT of the condition code register and the program counter The
Interrupt service routine should clear the source of the inter-
FFFC FFFD Nf:Al
rupt before dOing an RTI. See Figure 11.
FFFA FFFB SWI
FFF8 FFF9 iRa
FFF6 FFF7 'FiiiQ INTERRUPT REQUEST (iRQ)*
FFF4 FFF5 SWI2 A low level Input on thiS pin w~1 IMiate an Interrupt Re-
FFF2 FFF3 SWI3 quest ~ence provided the mask bit (I) In the CC IS clear.
FFFO FFFI Reserved Since IRO stacks the entire machine state It provides a
slower response to Interrupts than FIRO. IRO also has a
NON MASKABLE INTERRUPT (NMiI* lower prionty than FIRO. Again, the Interrupt service routine
A negative transition on thiS Input requests that a non- should clear the source of the Interrupt before doing an RTI
maskable Interrupt sequence be generated. A non-maskable See Figure 10

"NMt FIRQ, and TAO requests are sampled on the falhng edge of Q One cycle IS reqUired for synchronization before these Interrupts are recog-
nized. The pending Interruptls) Will not be serviced until completion of the current Instruction unless a SYNC or CWAI condition IS present If rna
and J!iJm'do not remain low until completion of the current Instruction they may not be recognized However, NMlls latched and need only re-
maIO low for one cycle No Interrupts are recognized or latched between the falhng edge of mrr and the rising edge of BS Indicating
REm acknowledge.

4-274
 s::

FIGURE 10 - IRQ AND iiiMi .INTERRUPT TIMING

i
s::
last cycle
of Current
Instruction
1-

1 m-2 1 m-l 1 m
Interrupt Stacking and Vector Fetch Sequence

1m+ 1 1 m+21 m+31 m+41 m+51 m+61 m+ 71 m+SI m+9Im+ 10Im+lllm+ 121m+ 131m+ 141m+ 15Im+16Im+ 171m+1SI
Instruction

• J
Fetch

n 1 n+ 1 1
!
s::
~OJ
~;;~~;t;;;t~~~~~~~;;~;;~~~~~;':~~~~~~~~~~~~~~~~~
E'

Q
~
Address
Bus

~r ~rpcs .
~~~~~ti''''_'\lnu~'
Daw
---A--~~--JL---A----~V~M~AJL~P~Cl~~P~C~H~-U~S-l~~U~SH~~IY~l-A~I~Y~H~-I-Xl~~IX~H~--D-P~A-C-C~BJLA-C~C-AA-C~C~A~~~==~~N-ew~-N-ew--A:V=M=A~--~~~
-f'" PCH PCl
N
......
U'I BA~
A/W~ \~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ /r----------------

NOTE Waveform measurements for all onputs and outputs are specified at logiC high =2 0 V and logiC low =0 S V unless otherwise specified
E clock shown for reference only

•
 • ~

Last Cycle
lof Current I....
Instruction
FIGURE 11 - FIRQ INTERRUPT TIMING

Interrupt Stacking and Vector Fetch Sequence -I

Instruction
Fetch
I
i•
~

E"

Q
I m-2 I m-l m I m+l m+2 I m+3 I m+4 I m+5 I m+6 I m+7 I m+8 I m+9 n+ 1 n+

I
•
~

-4 r
Address
Bus
m
txJ

tpcs PC PC ~
FiRQ

Data
.j:o.
N
-...I
m
R/W~ \ I
BA~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _

NOTE Waveform measurements for all Inputs and outputs are specified at logiC high = 20 V and logiC low= 08 V unless otherwise specified
E clock shown for reference only
MC6809-MC68A09-MC68B09

XTAL,EXTAL the MPU Into a Halt mode to three-state the machine, but
These Inputs are used to connect the on-chip oscillator to MRDY Will not stretch the clocks
an external parallel-resonant crystal. Alternately, the pin The mask set for a particular part may be determined by
EXT AL may be used as a TTL level Input for external timing examining the markings on top of the part Below the part
by grounding XT AL The crystal or external frequency IS four number IS a string of characters The first two characters are
times the bus frequency See Figure 8 Proper RF layout the last two characters of the mask set code If there are only
techniques should be observed In the layout of printed C"CUlt four digitS the part IS the G7F mask set The last four digits.
boards the date code, show when the part was manufactured
These four dlgtts represent year and week For example a
ceramic part marked
E,O
E IS Similar to the M C6800 bus timing signal <1>2, Q IS a

/~-.
quadrature clock signal which leads E Q has no parallel on
the MC6800 Addresses frorn the MPU will be valid with the
leading edge of Q Data IS latched on the falling edge of E
Timing for E and Q IS shown In Figure 12

IS a T5A mask set made the twelveth week of 1980.

MRDY'
ThiS Input control signal allows stretching of E and Q to
extend data-access time E and Q operate normally while
MRDY IS high When MRDY IS low, E and Q may be stretch- DMA/BREO'

•
ed In Integral multiples of quarter ( Y. I bus cycles, thus allow- The DMA/BREQ Input prOVides a method of suspending
Ing Interface to slow memOries, as shown In Figure 13(A) execution and acquiring the MPU bus for another use. as
DUring non-valid memory access (VMA cyclesl MRDY has shown In Figure 14 TYPical uses Include DMA and dynamiC
no effect on stretching E and Q, thiS Inhibits slOWing the pro-
cessor dunng "don't care" bus accesses MRDY may also be
memory refresh =-:-::-==;::-
TranSitions of DMAJ BREQ should occur dUring Q A low
used to stretch clocks (for slow memory) when bus control level on thiS pin Will stop Instruction execution at the end of
has been transferred to an external deVice (through the use the current cycle unless pre-empted by self· refresh The
of HALT and DMA/BREQ) MPU Will acknowledge DMA/BREQ by setting BA and BS to
NOTE Four of the early production mask sets (G7F, T5A, a one The requesting deVice Will now have up to 15 bus
P6F, T6M) require synchrOnization of the MRDY Input With cycles before the MPU retrieves the bus for self-refresh Self-
the 4f clock The synchronization necessitates an external refresh reqUires one bus cycle With a leading and trailing
OSCillator as shown In Figure 13(B) The negative transition dead cycle See Figure 15 The self-refresh counter IS only
of the MRDY signal, normally denved from the chip select cleared If DMA/BREQ IS Inactive for two or more MPU
decoding, must meet the tpcs timing. With these four cycles
mask sets, MRDY's POSitive transItion must occur With the TYPically. the DMA controller Will request to use the bus
nSlng edge of 4f by asserting DMAI BREQ pin Iowan the leading edge of E
In addition, on these same mask sets, MRDY Will not When the MPU replies by setting BA and BS to a one. that
stretch the E and Q signals If the machine IS executing either cycle Will be a dead cycle used to transfer bus mastership to
a TFR or EXG instruction dunng the HALT hlgh-to-Iow tran- the DMA controller
Sition If the MPU executes a CWAllnstructlon, the machine False memory accesses may be prevented dUrlcg any dead
pushes the Internal registers onto the stack and then awaits cycles by developing a system DMAVMA Signal which IS
an Interrupt DUring thiS waiting penod, It IS pOSSible to place LOW In any cycle when BA has changed

FIGURE 12 - E/Q RELATIONSHIP

Start of Cycle End of Cycle (Latch Datal

I
I I
E~~9~5~V________~/ '{I~--

I
\'--~:-­
rtAVSy
Q

I Address Valid I
NOTE Waveform iT.easurements for all Inputs and outputs are speCified at logiC high 20 V and logiC low 0 8 V unless otherwise speCified

-The on-board clock generator furnishes E and 0 to both the system and the MPU When MRDY IS pulled low, both the system clocks and the
Internal MPU clocks are stretched Assertion of OM AI BREQ Input stops the Internal MPU clocks while allOWing the external system clocks
to RUN (I e , release the bus to a DMA controller) The Internal MPU clocks resume operation after DMAI BREQ IS released or after 16 bus
cycles (14 DMA, 2 dead), whichever occurs first While DMA7iiRECi IS asserted It IS sometimes necessary to pull MRDY low to allow DMA to/
from sloW' menory/penpherals As both MADY and OMA/BREQ control the Internal MPU clocks, care must be exercised not to Violate the
maximum tcyc speclf,caliOn for MRDY or OMA/BRrn (See Note 5 In Bus Timing)

4·277
 MC6809.MC68AOO. MC68BOO

When BA goes low (either as a result of DMA/BREQ = This sequence begins after RESET and IS repeated Indefinite-
HIGH or MPU self-refresh), the DMA deVice should be taken ly unless altered by a special instruction or hardware occur-
off the bus Another dead cycle will elapse before the MPU rence. software instructions that alter normal MPU operation
accesses memory, 10 allow transfer of bus mastership are: SWI. SWI2, SWI3, CWAI, RTI and SYNC. An Interrupt,
without contention HALT, or DMA/BREQ can also alter the normal execution of
Instructions. Figure 16 illustrates the flowchart for the
MC6B09.
MPU OPERATION

DUring normal operation, the MPU fetches an instruction

from memory and then executes the requested function.

FIGURE 13(AI - MRDY TIMING

\ / \ / 'Ie~
t,- ____
I
I
0
/ \ / \
, )~
I "'I'} /

•
I t<.
tpcs
MRDY
",\\\\i I
I l

FIGURE 13(81 - MRDY SYNCHRONIZATION

XTAL 39

EXTAL~~~ ______________________________~____-,

Part of
MC6809 MRDY~36~__~M~R~D~Y~S~tffi~t=C~h__ +-__________~
MRDY
12 Synchronization
7474
D

ActIve La
Chip Select
For Slow
Memory or
Peripheral

MRDY Stretch
L--"S-"tre",tc",h~=:::....::O,-,7,-,R"C,-_____________ To Memory

4-278
MC6809·MC68A09· MC68B09

FIGURE 14 - TYPICAL DMA TIMING t< 14 CYCLES)

MPU DEAD DMA DEAD MPU

DMAIBREO

BA, BS

I \ I "-
•
DMAVMA-

AD DR ) C
(MPU)

ADDR
(DMAC) ( >

FIGURE 15 - AUTO-REFRESH DMA TIMING (> 14 CYCLES)

(REVERSE CYCLE STEALING)

IDfADI.IoIt--------14 DMA CyCles--------t.~'ooJMPulrud.--DMA~

I I I I I 1
I I I I I
E
I
o I
1 I
DMA/BREO'I I 1 I
I I 1 1
BA,BS--4'r-rI--------------------------------~~~)r--------

~.~
1 I
~--------
1I 1 I

.~ IS a signal whIch is developed externally, but IS a system requIrement for DMA. Refer to Apphcatlon Note AN-8.

NOTE: Waveform measurements for all Inputs and outputs are specIfIed at I~glc hIgh 2 0 V an~ logIC low O.B V unless otherwIse speCIfIed

4-279
 •
FIGURE 16 - FLOWCHART FOR MC8II09 INSTRUCTIONS s::
is::•
n
l_F-
l-R!W
ClrNMI
Logic
I

Disarm NMI
-r--
~s:•
n
~
CD
~

~
N
Q)
o

SYNC

CWAI

Bua State BA BS
Normal (Running) 0 0
Interrupt or Reset Acknowledge 0 1
Sync Acknowledge 0
Halt or Bus Grant Acknowledge

~OTE: Asserting RESET will result in entering the reset sequence from any point In the flow chan.
MC6809-MC68A09- MC68B09

ADDRESSING MODES

The basIc instructions of any computer are greatly EXTENDED INDIRECT

enhanced by the presence of powerful addressing modes As a speCial case of Indexed addressing (discussed
The MC6809 has the most complete set of addressing modes below), one level of Indirection may be added to Extended
available on any microcomputer today For example, the Addressing. In Extended Indirect, the two bytes following
MC6809 has 59 basIc instructions; however, It recognizes the postbyte of an Indexed Instruction contain the address of
1464 different variations of instructions and addressing the data.
modes The addressing modes support modern programm- LDA [CATl
Ing techmques The following addressing modes are LDX [$FFFEl
available on the M C6809:
STU [DOGl
Inherent (Includes Accumulator)
Immediate
Extended DIRECT ADDRESSING
Extended Indirect Direct addressing IS similar to extended addressing except
Direct that only one byte of address follows the opcode ThiS byte
Register specifies the lower 8 bits of the address to be used The up-
per 8 bits of the address are supplied by the direct page
Indexed
register Since only one byte of address IS reqUired In direct
Zero-Offset addressing, thiS mode reqUires less memory and executes
Constant Offset

II
faster than extended addressing Of course, only 256 loca-
Accumulator Offset tions (one page) can be accessed Without redef,mng the con-
Auto Increment/Decrement tents of the DP register Since the DP register IS set to $00 on
Indexed Indirect Reset. direct addressing on the MC6809 IS compatible With
Relative direct addressing on the M6800 Indirection IS not allowed In
Short/Long Relative Branching direct addressing Some examples of direct addressing are
Program Counter Relative Addressing
LDA $30
INHERENT (INCLUDES ACCUMULATOR) SETDP $10 (Assembler dlrectlvel
In thiS addressing mode, the opcode of the instruction LDB $1030
contains all the address Information necessary Examples of LDD < CAT
Inherent Addressing are ABX, DAA, SWI, ASRA, and
CLRB NOTE: < IS an assembler directive which forces direct
addreSSing
IMMEDIATE ADDRESSING
In Immediate Addressing, the effective address of the data
IS the location Immediately following the opcode (, e., the REGISTER ADDRESSING
data to be used In the instruction Immediately follows the op- Some opcodes are followed by a byte that defines a
code of the instruction). The MC6809 uses both Band 16-bIt register or set of registers to be used by the Instruction ThiS
Immediate values depending on the size of argument IS called a postbyte Some examples of register addreSSing
specified by the opcode. Examples of instructions With Im- are'
mediate Addressing are' TFR X, Y Transfers X Into Y
LDA #$20 EXG A, 8 Exchanges A With B
LOX #$FOOO PSHS A, B, X, Y Push y, X, B and A onto S
LDY #CAT PULU X, Y, D Pull D, X, and Y from U
NOTE: # slgmfles Immediate addressing, $ s,gmf,es hexa-
decimal value.
INDEXED ADDRESSING
EXTENDED ADDRESSING
In all Indexed addreSSing, one of the pOinter registers (X,
In Extended Addressing, the contents of the two bytes Im-
Y, U, S, and sometimes PCI,s used In a calculation of the ef-
mediately following the opcode fully specify the 16-blt effec-
fective address of the operand to be used by the instruction
tive address used by the Instruction. Note that the address
Five baSIC types of indeXing are available and are discussed
generated by an extended instruction defines an absolute ad-
below The postbyte of an Indexed instruction specifies the
dress and IS not posItIOn Independent. Examples of Extended
baSIC type and variation of the addreSSing mode as well as
Addressing Include
the pOinter register to be used Figure 17 lists the legal for-
LDA CAT mats for the postbyte Table 2 gives the assembler form and
STX MOUSE the number of cycles and bytes added to the baSIC values for
LDD $2000 Indexed addresSing for each variation

4·281
 MC6809·MC68A09· MC68B09

FIGURE 17 - INDEXED ADDRESSING POSTBYTE Zero-Offset Indexed - In thiS mode, the selected pOinter
REGISTER BIT ASSIGNMENTS register contains the effective address of the data to be used
Indexed by the Instruction, ThiS IS the fastest IndeXing mode,
Post-Byte RegIster Bit
Addressing Examples are
7 6 5 4 3 2 1 0
Mode
LOO Q,X
0 R R d d d d d EA ~ ,R + 5 BIt Offset
LOA S
1 R R 0 0 0 0 0 ,R+
1 R R I 0 0 0 1 ,R+ + Constant Offset Indexed In thiS mode, a
1 R R 0 0 0 1 0 ,- R two's-complement offset and the contents of one of the
1 R R , 0 0 1 1 ,- - R pOinter registers are added to form the effective address of
1 R R , 0 1 0 0 EA ~ ,R +0 Offset the operand The pOinter register's lnillal content IS un-
1 R R , 0 1 0 I EA ~ ,R + ACCB Offset changed by the addition
1 R R , 0 1 1 0 EA ~ ,R + ACCA Offset Three sizes of offsets are available,
1 R R , 1 0 0 0 EA ~ ,R +8 B't Offset 5 -bit (- 16 to + 151
1 R R , 1 0 0 1 EA ~ ,R + 16 Bit Offset 8 -bit (- 128 to + 1271
1 R R , 1 0 1 1 EA - ,R + 0 Offset 16-blt (- 32768 to + 327671
1 x x , 1 1 0 0 EA - ,PC + 8 B't Offset The two's complement 5-blt offset IS Included In the
1 x x , 1 1 0 1 EA ~ ,PC + 16 B,t Offset post byte and, therefore, IS most effiCient In use of bytes and
,
1
- A R
-~
1 1 1 1 EA

'-----Addressmg Moae Field

~ l,Addressl cycles The two's complement 8-blt offset IS contained In a
single byte following the postbyte The two's complement

I
16-blt offset IS In the two bytes follOWing the post byte In
most cases the programmer need not be concerned with the
' - - - - - - - - I n d l r e c t Field
size of thiS offset Since the assembler Will select the optimal
IS'gn b,t when b7 ~ 01
sIze automatically,
Examples of constant-offset IndeXing are
' - - - - - - - - - - - - R e g ' s t e r F,eld RR LOA 23,X
00 ~ X
LOX -2,S
01 ~ Y
10 ~ U LOY 3OO,X
11 ~ S LOU CAT,Y
x = Don't Care
d ~ Offset BI1
0= Not Indirect
1 = Indirect

TABLE 2 - INDEXED ADDRESSING MODE

Non Indirect Indirect
Type Forms Assembler Postbyte + + Assembler Postbyte + +

Constant Offset From R No Offset

Form
,R
OP Code
lRR00100
-
0 0
# Form
[,RI
OP Code
1RR10l00
- #
3 0
12's Complement Offsetsl 5 B,t Offset n, R ORRnnnnn 1 0 defaults to 8-blt
8 BIt Offset n, R lRR01000 1 1 In, RI 1RR11000 4 1
16 BIt Offset n, R lRR01001 4 2 In, RI lRRll001 7 2
Accumulator Offset From R A RegIster Offset A, R lRR00110 1 0 [A, RI lRR10110 4 0
12's Complement Offsetsl B Reg,ster Offset B, R 1RR0010l 1 0 [B, Al lRR1010t 4 0
° RegIster Offset 0, R lRR01011 4 0 [0, RI lRR11011 7 0
Auto Increment/ Decrement R Increment By 1 ,R+ lRROOOOO 2 0 not allowed
Increment By 2 ,R+ + lRROOOOl 3 0 l,R+ +1 lRR10001 6 0
Decrement By 1 ,- R lRROOO10 2 0 not allowed
Decrement By 2 ,- -R lRROOO11 3 0 l,- - RI lRR100l1 6 0
Constant Offset From PC 8 B,t Offset n, PCR lxxOl100 1 1 In, PCRI lxxl1100 4 1
12's Complement Offsets I 16 B,t Offset n, PCR lxx01101 5 2 In, PCRI lxxl1101 8 2
Extended Indirect 16 B,t Address - - - - [nl 10011111 5 2
R ~ X, Y, U or S
x = Don't Care RR
OO=X
01=Y
10=U
11 =S

:and +# Indicate the number of additional cycles and bytes for the particular vanatlon

4-282
MC6809-MC68AOS-MC68BOS

Accumulator-Offset Indexed - This mode IS similar to Before Execution

constant offset indexed except that the two's-complement A=XX Idon't care)
value in one of the accumulators lA, B or D) and the con- X= $Fooo
tents of one of the pOinter registers are added to form the ef- $0100 LOA [$10,X] EA IS now $F010
fective address of the operand. The contents of both the ac-
cumulator and the pOinter register are unchanged by the ad- $F010 $F1 $Fl50 IS now the
dition. The postbyte specifies which accumulator to use as $FOll $50 new EA
an offset and no additional bytes are required. The advan- $Fl50 $AA
tage of an accumulator offset is that the value of the offset
After Execution
can be calculated by a program at run-time.
A = $AA Actual Data Loaded
Some examples are:
X=$Fooo
LOA B,Y
LOX D,Y All modes of Indexed indirect are Included except those
LEAX B,X which are meaningless Ie g , auto Increment/decrement by
Auto Increment!Decrement Indexed - In the auto incre- 1 ,nd,rect) Some examples of Indexed Indirect are
ment addressing mode, the pOinter register contains the ad- LOA [,X] LOA [B,Y]
dress of the operand. Then, after the pOinter register IS used
LOO [10,5] LOO [,X++]
It IS Incremented by one or two. ThiS addressing mode IS
useful In stepping through tables, moving data, or for the
creation of software stacks. In auto decrement, the pOinter RELATIVE ADDRESSING

•
register IS decremented prior to use as the address of the The bytels) follOWing the branch opcode IS lare) treated as
data. The use of auto decrement IS similar to that of auto in- a Signed offset which may be added to the program counter
crement; but the tables, etc., are scanned from the high to If the branch condition IS true then the ca)culated address
low addresses. The size of the increment! decrement can be IPC + Signed offsell IS loaded Into the program counter
either one or two to allow for tables of either a or 16-bIt data Program execution pontlnues at the new location as In-
to be accessed and IS selectable by the programmer. The dicated by the PC, short 11 byte offset) and long 12 bvtes off-
pre-decrement, post-Increment nature of these modes allow set) relative addreSSing modes are available All of memory
them to be used to create additional software stacks that can be reached In long relative addreSSing as an effective ad-
behave Identically to the U and 5 stacks. dress IS Interpreted modulo 216 Some examples of relative
Some examples of the auto Increment! decrement ad- addreSSing are:
dressing modes are: BEQ CAT Ishort)
LOA ,X+ BGT DOG (shorll
STD ,Y++ CAT LBEQ RAT (long)
LOa ,-Y DOG LBGT RABBIT liang)
LOX ,- -5

Care should be taken in performing operations on 16-blt •

pOinter registers IX, Y, U, 5) where the same register IS used •
to calculate the effective address. RAT NOP
Consider the follOWing instruction: RABBIT NOP
STX O,X+ + IX initialized to 01
PROGRAM COUNTER RELATIVE
The desired result IS to store a 0 In locations $0000 and $0001
then Increment X to point to $0002. In reality, the follOWing a
The PC can be used as the pOinter register With or 16-bIt
occurs: signed offsets. As In relative addressing, the offset IS added
to the current PC to create the effective address. The effec-
O-temp calculate the EA, temp IS a holding register
tive address is then used as the address of the operand or
X+2-X perform autolncrement
data. Program Counter RelatIVe Addressing IS used for
X-Itemp) do store operation
writing position Independent programs. Tables related to a
particular routine will maintain the same relationship after
INDEXED INDIRECT the routine is moved, If referenced relatIVe to the Program
All of the indeXing modes With the exception of auto In- Counter. Examples are:
crement! decrement by one, or a ± 4-bit offset may have an LOA CAT, PCR
additional level of indirection specified. In Indirect adddress- LEAX TABLE, PCR
ing, the effective address IS contained at the location
Since program counter relative IS a type of IndeXing, an
specified by the contents of the Index register plus any off-
additional level of indirection IS available
set. In the example below, the A accumulator is loaded in-
directly using an effective address calculated from the Index LOA [CAT, PCR]
register and an offset. LOU [DOG, PCR]

4-283
 MC680ge MC68A0ge MC68B09

MC6809 INSTRUCTION SET

The instruction set of the MC6809 IS similar to that of the register, while bits 0-3 represent the destination register
MC6800 and IS upward compatible at the source code level. These are denoted as follows.
The number of opcodes has been reduced from 72 to 59, but
TRANSFER/EXCHANGE POST BYTE
because of the expanded architecture and additional ad-
dressing modes, the number of available opcodes (with dif- [}OtIRC~ I o~sTI~ATloN I
ferent addressing modes) has risen from 197 to 1464
Some of the new Instructions are described In detail REGISTER FIELD
below 0000 OIAS) 1000 - A
0001 ~ X 1001 S
0010 ~ Y 1010 CCR
PSHU/PSHS 0011 . U 1011 OPR
The push Instructions have the capability of pushing onto 0100 5
0101 pc
either the hardware stack (S) or user stack (U) any Single
register, or set of registers with a single instruction. NOTE: All other combinations are undefined and INVALID

PULU/PULS LEAX/LEAY/LEAU/LEAS
The LEA (Load Effective Address) works by calculating
The pull Instructions have the same capability of the push
the effectIVe address used In an Indexed instruction and
Instruction, In reverse order The bYte Immediately following
stores that address value, rather than the data at that ad-
the push or pull opcode determines which register or
dress, In a pOinter register This makes all the features of the
registers are to be pushed or pulled The actual PUSH/PULL

•
Internal addreSSing hardware available to the programmer
sequence 15 fixed, each bit defines a unique register to push
Some of the Implications of this Instruction are Illustrated In
or pull, as shown below.
Table 3
The LEA instruction also allows the user to access data
and tables In a posItion Independent manner. For example.
PUSH/PULL POST BYTE STACKING ORDER
LEAX MSG1, PCR
PULL ORDER
LBSR PDATA (Print message routine)
CCR Jc •
A
L-_ _ _ 'S
A
B
•
'--_ _ _ _ OPR MSG1 FCC 'MESSAGE'
OP
' -_ _ _ _ _ x X H, This sample program prints 'MESSAGE' By writing
'-------y
' - _ _ _ _ _ _ _ S/U
X Lo M SG 1, PCR, the assembler computes the distance between
YH,
' -_________ pc YLo the present address and MSG 1 This result 15 placed as a
U/SHI constant Into the LEAX Instruction which will be Indexed
U/S Lo from the PC value at the time of execution No matter wherf3
PC HI
PC La
the code 15 located, when It 15 executed, the computed offset
+ from the PC Will put the absolute address of MSG11nto the X
PUSH ORDER pOinter register. This code 15 totally position Independent
INCREASING The LEA Instructions are very powerful and use an Internal
MEMORY holding register (temp), Care must be exercised when uSing
~ the LEA instructions With the autOincrement and autodecre-
ment addreSSing modes due to the sequence of Internal
operations The LEA Internal sequence 15 outlined as follows:

LEAa ,b+ (any of the 16-blt pOinter registers X, Y, U,

or S may be substituted for a and b I
TFR/EXG
Within the MC6809, any register may be transferred to or 1 b-temp (calculate the EA)
exchanged With another of like-size, I e., B-blt to B-blt or 2.b+1-b (modify b, postlncrement)
16-blt to 16-blt. Bits 4-7 of postbyte define the source 3 temp-a (load a)

TABLE 3 - LEA EXAMPLES

Instruction Operation Comment
LEAX 10,X X + 10 -X Adds 5-blt constant 10 to X
LEAX 5OO,X X+5OO-X Adds 16-blt constant 500 to X
LEAY A,Y Y+A -Y Adds 8-bit A accumulator to Y
LEAY D,Y Y+D -Y Adds 16-blt D accumulator to Y
LEAU -10, U U - 10 -U Subtracts 10 from U
LEAS -10, S S - 10 -S Used to reserve area on stack
LEAS 10,5 5 + 10 -5 Used to 'clean up' stack
LEAX 5,5 5+5 -X Transfers as well as adds

4·284
MC68Q9- MC68A09- MC68B09

LEAa ,- b next byte, so thiS technique considerably speeds

throughput) Next, the operation of each opcode will follow
b-1-temp (calculate EA with predecrement) the flowchart VMA IS an Indication of FFFF16 on the ad-
2 b-1-b (modify b, predecrement) dress bus, R /W = 1 and B S = 0 The follOWing examples il-
3 temp-a (load a) lustrate the use of the chart, see Figure 19

Example 1: LBSR (Branch Taken)

AutOincrement-by-two and autodecrement-by-two Instruc- Before Execution SP == FOOO
tions work similarly Note that LEAX ,X + does not change
X, however LEAX, - X does decrement LEAX 1, X should
be used to Increment X by one
$8000 LBSR CAT
MUL
Multiplies the unsigned binary numbers In the A and B ac-
cumulator and places the unsigned result Into the 16-blt 0
accumulator ThiS unsigned multiply also allows multlple- $AOOO CAT
precIsion multiplications
CYCLE-BY-CYCLE FLOW
Long And Short Relative Branches Cycle # Address Data Rfw DeSCription
The MC6809E has the capability of program counter 1 8000 17 1 Opcode FetCh
relative branching throughout the entire memory map In BOO 1 20 Offset High Byte
thiS mode, If the branch IS to be taken, the 8- or 16-blt signed 8002 00 Offset Low Byte

II
offset IS added to the value of the program counter to be us- FFFF VMA Cycle
ed as the effective address ThiS allows the program to FFFF VMA Cycle
AOOO Computed Branch Address
branch anywhere In the 64K memory map Posltlon-
FFFF 1 VMA Cycle
Independent code can be easily generated through the use of EFFF 80 0 Stack High Order Byte of
relative branching Both short (8-blt) and long (16-blt) bran- Return Address
ches are available EFFE 03 Stack Low Order Byte of
Return Address
SYNC
After encountering a Sync Instruction, the MPU enters a Example 2: DEC {Extendedl
Sync state, stops processing Instructions and walts for an In-
$8000 DEC $AOOO
terrupt If the pending Interrupt IS non-maskable (NMI) or
maskable (FIRO, IRQ) With ItS mask bit (F or I) clear, the pro-
••
cessor Will clear the Sync state and perform the normal Inter- $ABOOO $80
•
rupt stacking and serVice routine Since FIRO and IRO are
not edge-triggered, a low level With a minimum duration of CYCLE-BY-CYCLE FLOW
three bus cycles IS reqUired to assure that the Interrupt Will Cycle # Address Data Rl'iN Description
be taken If the pending Interrupt IS maskable (FIRO, IRO) 1 8000 7A 1 Opcode Fetch
With ItS mask bit (F or I) set, the processor Will clear the Sync 2 8001 AO Operand Address, High Byte
state and continue processing by executing the next Inllne 3 8002 00 Operand Address, Low Byte
Instruction Figure 18 depicts Sync timing 4 FFFF VMA Cycle
5 AOOO 80 Read the Data
Software Interrupts 6 FFFF VMA Cycle
A Software Interrupt IS an instruction which Will cause an 7 AOOO 7F Store the Decremented Data
Interrupt, and ItS associated vector fetch These Software In-
"The data bus has the data at that particular address
terrupts are useful In operating system calls, software
debugging, trace operations, memory mapping, and soft-
MC6809 INSTRUCTION SET TABLES
ware development systems Three levels of SWI are available
on the MC6809, and are prioritIZed In the follOWing order
SWI, SWI2, SWI3 The Instructions of the MC6809 have been broken down
Into five different categories They are as follows '
16-Bit Operation 8-Blt operation (Table 4)
The M C6809 has the capability of processing 16-blt data 16-Bll operation (Table 51
These instructions Include loads, stores, compares, adds, Index register/stack pOinter Instructions ITable 6)
subtracts, transfers, exchanges, pushes and pulls Relative branches Iiong or short I (Table 7)
Miscellaneous Instructions ITable 81
CYCLE-BY-CYCLE OPERATION HexadeCimal values for the Instructions are given In
Table 9
The address bus cycle-by-cycle performance chart Il-
lustrates the memory-access sequence corresponding to
each possible instruction and addreSSing mode In the
MC6809 Each Instruction begins With an opcode fetch PROGRAMMING AID
While that opcode IS being Internally decoded, the next pro- Figure 21 contaills a compilation of data that Will assist In
gram byte IS always fetched (Most Instructions Will use the programmlllg the MC6809

4·285
 .' 3:

i
3:

!
FIGURE 18 - SYNC TIMING

Sync Last Cycle

3:
~OJ
a

f6
Address

~
N
Data r-x;
(Xl
0)
R/W '------<d~)~~------+----------------J~---------------------
( I
-v---\ )
BA~ I t
BS

~{
Fi'RLi
~ See Note 2
NMI tpcs

NOTES
1 If the associated mask bit IS set when the Interrupt IS requested, this cycle will be an Instruction fetch from address location PC+ 1 However, If the in-
terrupt IS accepted (NMI or an unmasked FIRG or TAO) mterrupt processing contmues with this cycle as (m) on Figures 10 and 11 (Interrupt Timing)
2 If mask bits are clear, IRQ and FlAG must be held low for three cycles to guarantee Interrupt to be taken, although only one cycle IS necessary to bnng
the processor out of SYNC

NOTE Waveform measurements for all Inputs and outputs are speclfred at logiC high 2 0 V and logiC low 0 8 V unless otherwise specified
 (
FIGURE 19 - ADDRESS BUS CYCLE-BY-CYCLE PERFORMANCE

fetch)
i
ADDR-Addressof Opcode IFetch)

~
Addr-Addr+ 1
,
~

Long

Brar-T-Inhe.ent
Short Immediate and

--.-- I ,
Indexed
I
~

~DJ
Auto Aut

Addr-:Addr + 1 I VMA Add'-Addr+ 1

I
InclDec Inc/Dec
by 1 by 2
No
Offset
VMA Offset ~
ACCA

I 1
ACCS
R + 5 Brt
R+B Bit
ADDR- ADDR-
ADDR+l ADDR+l
ADDR- ADDR-l
ADDR+ 1 ADDR+ 1
VMA PC -t 8 Bit ADDR- ADDR- ADLlR- ADDR-
ADDR+ 1 ADDR+ 1 ADDi'I+ 1- ADDR+ 1
I I
~
I\) VilA ilfTA VIh
(Xl
...... VliilA vffA vk ~

Addr - Address of Operand

--I
l I !, !

N ADDR-New Opcode ADDR

I
VMA
I
Stack Write
I
Stack Write

NOTES
1 All subsequent Page 2 and Page 3 pre-bytes will be'lgnomd dftel 111I1Itii Opf odo Illt{ h
2 Write operation dunng store Instruction
3 ADDR refers to the state of the address bu,

•
 FIGURE 2O(a) -
•
OPERATION: ADDRESS BUS CYCLE-BY-CYCLE PERFORMANCE s:
Inherent Page From Figure 19

Continued
~•
ASLA
ASLB
ABX RTS ·TFR EXG MUL PSHU
PSHS
PULU
PULS
SWI
SWI2
CWAI
RT'l on Next
Page
s:

!
SWI3
ASRA
ASRB ADDR-ADDR+1 STACK IRI
CLRA
CLRB VMA VMA VMA VMA VMA vk
s:•
COMA VMA I I
COMB VMA VMA VMA
DAA VMA

~tIl
DECA
DECB
INCA STACK IRI VMA VMA
I
ADDR-SP
STACKIW: STACKIWI
STACKIWI STACKiWI Y
~
INCB STACKIRI VMA VMA I E~l
STACK IWI STACK IWI >--
LSLA
LSLB
VMA VMA
VMlI
VMA
VMA
Note 3
g
! Stack IWl1 1 STACKIWI
STACKIWi
STACKIWI
STACKIWI
STACK
STACK
IRI
IRI
LSRA \ilViA VMA N
IStack IRI162 STACK IWi STACK IWI STACK IRI
LSRB
NEGA
VMA VMA
VMA
I Note 3 ST ACK IWI
ST ACK IWI
STACK IWI
STACK IWI
STACK
STACK
IRI
IR'
NEGB VMA STACKIWI STACKIWI STACK IRI STACK IRI
NOP VMA
-1=>0 ST ACK IWI STACK IWI S1 ACK IRI STACK IRI
ROLA
r\) STACKIWI STACKIWI STACK IRI
ROLB
(X) STACKIWI STACKIWI STACK IRI
RORA
(X)
RORB
SEX ADDR-SP

VMA
I
IVMAI""
I . STACK

,....----
STACK
IRI
IRI

I Note4
VECTOR IHI. VeCTOR IHI.
BUSY-I BUSY-1 Addr-SP
VECTOR Ill. VECTOR IL~'
BUSY -0 BUSY-O
I I
VMA VM-'I

, , J J J r 1 1
To Figure 19
NOTES
1 Stack IWI refers to the following sequence SP- SP -1, then ADDR- SP "lth R/W = 0
Stack IRI refers to the following sequence ADDR-SP with RiW= 1, then SP-SP+ 1
PSHU, PULU instructions use the user stack pOInter (! e, SPi!IE'U) and PSHS PULS use ttle hClrdware stack pOinter (I e. SP15S)
Vector refers to the address of an Interrupt or reset vector (see Table 1)
The number of stack accesses will vary according to the number of bytes saved
VMA cycles will occur until an Interrupt occurs
 ~
FIGURE 20(bl - OPERATION: ADDRESS BUS CYCLE-BY-CYCLE PERFORMANCE (")

~•
(CONTINUED)

Non-\nherents From Figure 19

~
(")
~
~•
ADCA
ADCB
AOOA
AOOB
ANOA
LOO
LOS
ASL
ASR
TST AODO
CMPO
JSR STD
STS s::
(")
LOU CLR CMPS STU
ANOB
BITA
LOX
LOU
COM
DEC
CMPU
CMPX
STX
STU
~
BITB
INC
OJ
CMPY
CMPA
LSL SUBO
@
CMPB ANOCC LSR
EORA ORCC NEG
EORB
ROL
LOA
ROR
LOB
ORA
ORB
"'~"
())
SBCA
SBCB
<0 STA
STB
SUBA
SUBB
TSTA
TSTB
AOOR-AOOR+1 VMA VMA AOOR-AOOR+1 VMA AOOR - AOOR + 1
AOOR VMA VMA STACKIW) IWrlte)
STACKIWI

To Figure 19

•
 MC680ge MC68AOSe MC68BOS

TABLE 4 - 8-BIT ACCUMULATOR AND MEMORY INSTRUCTIONS

Mnemonic(s) Operation
ADCA,ADCB Add memory to accumulator with carry
ADDA,ADDB Add memory to accumulator
ANDA,ANDB And memory with accumulator
ASL, ASLA, ASLB Arithmetic shift of accumulator or memory left
ASR,ASRA,ASRB Anthmetlc shift of accumulator or memq~y nght
BITA, BITB Bit test memory with accumulator
CLR, CLAA, CLAB Clear accumulator or memory location
CMPA, CMPB Compare memory from accumulator
COM, COMA, COMB Complement accumulator or memory locatIon
DAA Decimal adjust A accumulator
DEC,DECA,DECB Decrement accumulator or memory location
EOAA, EORB Exclusive or memory with accumulator
EXG Al, A2 Exchange Al with R2 IR1, R2 - A, B, CC, DPI
INC, INCA, INCB Increment accumulator or memory location
LiJA, LDB Load accumulator from memory
LSL,LSLA, LSLB LogIcal shift left accumulator or memory location
LSA, LSAA, LSAB Logical shift nght accumulator or memory location

•
MUL Unsigned multiply IA x B - DI
NEG, NEGA, NEGB Negate accumulator or memory
OAA,ORB Or memory with accumulator
ROL, AOLA, ROLB Rotate accumulator or memory left
AOA,AOAA,AORB Rotate accumulator or memory right
SBCA,SBCB Subtract memory from accumulator with bouow
STA, STB Store accumulator to memory
SUBA,SUBB Subtract memory from accumulator
TST, TSTA, TSTB Test accumulator or memory location
TFA Al, A2 Transfer Al to A2 IA1, A2 ~ A, B, CC, DPI

NOTE A, B, CC or DP may be pushed to Ipulled froml either stack with PSHS, PSHU IPULS,
PULUI Instructions

TABLE 5 - 16-BIT ACCUMULATOR AND MEMORY INSTRUCTIONS

Mnemonic!s) Operation
ADDD Add memory to 0 accumulator
CMPD Compare memory from D accumulator
EXG D, A Exchange D With X, Y. S, U or PC
LDD Load D accumulator from memory
SEX Sign Extend B accumulator Into A accumulator
STD Store D accumulator to memory
SUBD Subtract memory from D accumulator
TFA D, R Transfer D to X, Y, S, U or PC
TFA A, D
- Transfer X, Y, S, U or PC to D

NOTE D may be pushed Ipulledl to either stack With PSHS, PSHU (PULS,
PULUI Instructions

4-290
MC6809. MC68A09· MC68B09

TABLE 6 - INDEX REGISTER/STACK POINTER INSTRUCTIONS

Instruction Descnptlon
CMPS, CMPU Compare memory from stack pOinter
CMPX, CMPY Compare memory from Index register
EXGR1,R2 Exchange D, X, Y. S. U or PC with D, X,Y,S,UorPC
LEAS, LEAU Load effective address Into stack pOinter
LEAX, LEAY Load effective address Into Index register
LDS, LDU Load stack pOinter from memory
LDX, LDY Load Index register from memory
PSHS Push A, B, ce, DP, D, X, Y, U, or PC onto hardware stack
PSHU Push A, S, ce, DP, D, X, y, S, or PC onto user stack
PULS Pull A, B, ce, DP. D, X, Y, U or PC from hardware stack
PULU Pull A, B, ce, DP, D, X, y, S or PC from hardware stack
STS, STU Store stack pOinter to memory
STX, STY Store Index register to memory
TFR Rl, R2 Transfer D. X. Y. S, U or PC to 0, X, Y, S, U or PC
ABX Add B accumulator to X (unsigned)

TABLE 7 - BRANCH INSTRUCTIONS

Instruction Descnptlon
SIMPLE BRANCHES
BEQ, LBEQ Branch If equal

•
BNE, LBNE Branch If nOt equal
BMI, LBMI Branch If minus
BPL, LBPL Branch If plus
BCS, LBCS Branch If carry set
BCC, LBCC Branch If carry clear
BVS, LBVS Branch If overflow set
BVC, LBVC Branch If overflow clear
SIGNED BRANCHES
SGT, LBGT Branch If greater (signed)
BVS, LBVS Branch If invalid 2's complement result
BGE, LBGE Branch If greater than or equal (signed)
BEQ, LBEQ Branch If equal
BNE, LBNE Branch If not equal
BLE, LBLE Branch If less than or equal (signed)
BVC, LBVC Branch If valid 2'~ complement result
BLT, LBLT Branch If less than (signed)
UNSIGNED BRANCHES
BHI, LBHI Branch If higher (unsigned)
BCC, LBCC Branch Ii higher or same (unsigned)
BHS, LBHS Branch If higher or same (unsigned)
BEQ, LBEQ Branch If equal
BNE, LBNE Branch If not equal
BLS, LBLS Branch If lower or same (unsigned)
BCS, LBCS Branch If lower (unsigned)
BLO, LBLO Br8r>ch If lower (unsIgned)
OTHER BRANCHES
BSR, LBSR I Branch to subroutine
BRA, LBRA Branch always
BRN, LBRN I Branch never
TABLE B - MISCELLANEOUS INSTRUCTIONS
InstructIon Descnption
ANDCC AN[' condition code register
CWAI AN;) condition code register, then walt for Interrupt
NQP No operation
ORCC OR condition code register
JMP Jump
JSR Jump to subroutine
RTI Return from Interrupt
RTS Return from subroutine
SWI, SWI2, SWI3 Software Interrupt (absolute Indirect)
SYNC Synchronize with Interrupt line

4-291
 MC680ge MC68AOOe MC68BOO

TABLE 9 - HEXADECIMAL VALUES OF MACHINE CODES

OP Mr.em Mode OP Mnem Mode OP Mnem Mode

00 NEG Direct 30 LEAX Indexed 4+ 2+ 60 NEG Indexed 6+ 2+
01
02
03
04
COM
LSR
31
32
33
34
LEAY
LEAS
LEAU
PSHS
t 4+
4+
Indexed 4+
Inherent 5+
2+
2+
2+
2
61
62
63
64
COM
LSR
6+
6+
2+
2+
05
06 ROR 6
35
36
PULS
PSHU t 5+
5+
2
2
65
66 ROR 6+ 2+
07 ASR 6 37 PULU 5+ 2 67 ASR
1 6+ 2+

I
00 ASL, LSL 6 38 68 ASL, LSL 6+ 2+
09 ROL 6 39 RTS 5 69 ROL 6+ 2+
OA OEC 3A ABX 3 6A OEC i 6+ 2+
08
OC
00
OE
OF
INC
TST
JMP
CLR Direct
6
6
3
6
2
2
2
2
3B
3C
30
3E
3F
RTI
CWAI
MUL

SWI Inherent
6/15
;;,20
11

19
6B
6C
60
6E
6F
INC
TST
JMP
CLR
j
Indexed
6+
6+
3+
6+
2+
2+
2+
2+

10 Page 2 40 NE:GA Inherent 70 NEG Extended

•
11 Page 3 41 71
12 NDP Inherent 42 72
13 SYNC Inherent ;;,4 43 COMA 73 COM
14 44 LSRA 74 LSR
15 45 75
16 LBRA Relative 5 46 RORA 76 ROR 3
17 LBSR Relative 9 47 ASRA 77 ASR 3
18 48 ASLA, LSLA 78 ASL, LSL 3
19 DAA Inherent 49 ROLA 79 ROL 3
1A ORCC Immed 4A DECA 7A DEC 3
1B 4B 7B
1C ANDCC Immed 4C INCA 7C INC 3
10
1E
1F
SEX
EXG
TFR
Inherent

•
Inherent
2
2
40
4E
4F
TSTA

CLRA Inherent
70
7E
7F
TST
JMP
CLR
1
Extended
3
3
3

20 BRA Relative 50 NEGB Inherent 80 SUBA Immed

21 BRN 51 81 CMPA
22 BHI 3 52 82 SBCA
23 BLS 3 53 COMB 83 SUBD 4
24 BHS, BCC 3 54 LSRB 84 ANOA 2
25 BLO, BCS 3 55 B5 BITA 2
26 BNE 3 56 RORB 86 LOA 2
27 BEG 3 57 ASRB B7
28 BVC 3 56 ASLB, LSLB 68 EORA
29 BVS 3 59 ROLB B9 AOCA
2A BPL 3 5A DECB 8A ORA
2B BMI 3 58 B8 ADOA
2C BGE 3 5C INCB BC CMPX Immed
2D BLT 3 50 T5TB BD BSR Relative 7
2E BGT 3 5E 8E LOX Immed 3
2F BLE Relative 3 5F CLRB Inherent 8F

LEGEND
- Number of MPU cycles (less possible push puB or mdexed-mode cycles)
# Number of program bytes
.. Denotes unused opcode

4·292
MC6809- MC68AOO- MC68BOO

TABLE 9 - HEXADECIMAL VALUES OF MACHINE CODES (CONTINUED)

OP Mnem Mode # OP Mnem Mode OP Mnem Mode

90 SUBA Olr ct 2

T
CO SUBB
91 CMPA 4 2 Cl CMPB Page 2 and 3 Machine
92 SBCA 4 C2 SBCB Codes
93 SUBO 6 C3 ADOO
94 ANOA C4 ANDB 1021 LBRN Relative 5 4
95 BITA C5 BITB Immed 1022 LBHI 4
5161
96 LOA C6 LOB Immed 1023 LBLS 5161 4
97 ST~ C7 1024 LBHS, LBCC 516) 4
EORA

1
98 C8 EORB 1025 LBCS, LBLO 5161 4
99 AOCA 4 C9 ADCB 1026 LBNE 5161 4
9A ORA 4 CA ORB 1027 LBEO 5161 4
9B AOOA 4 CB AODB 1028 LBVC 5161 4
9C
90
9E
9F
CMPX
JSR
LOX
STX
6
7
5
5
CC
CD
CE
CF
LDD

LDU
1
Imrr,ed 3
1029
102A
102B
102C
LBVS
LBPL
LBMI
LBGE
5161
5161
5161
5161
4
4
4
4
Direct 4 1020 LBLT 5161 4
AO SUBA' Indexed 4+ 2+ DO SUBB
Dl CMPB
102E LBGT 5161 4
Al CMPA 4+ 2+ Relative 5161 4
D2 4 102F LBLE
A2 SBCA 4+ 2+ SBCB

•
ADDD 103F SWI2 Inherent 20 2
A3 SUBO 6+ 2+ 03 6
D4 ANOB 4 1083 CMPO Immed 5 4
A4 ANOA 4+ 2+
A5 BITA 4+ 2+ D5 BIT8 4 108C CMPY I 5 4
lOBE LOY Immed 4 4
06 LDB 4
A6
A7
A8
A9
LOA
STA
EORA
AOCA
4+
4+
4+
4+
2+
2+
2+
2+
D7
08
09
STB
EORB
AOCB
4
4
4
1093
109C
109E
CMPO
CMPY
LOY
Dr 7
7
6
3
3
3
OA ORB 4 109F STY Direct 6 3
AA ORA 4+ 2+ lOA3 CMPO 3+
AB AOOA 4+ 2+ DB ADDB Ind.xed ; :
DC LDD
lOAC CMPY 3+
AC
AD
CMPX
JSR
6+
7+
2+
2+ DO STD 5 10AE LOY t 6+ 3+
DE LDU 5 lOAF STY Indexed 6+ 3+
AE LOX 5+ 2+
AF STX Indexed 5+ 2+ OF STU Direct 5 lOB3 CMPO Extefded 8 4
10BC CMPY 4
EO SUBB Indexed 4+ 2+ lOBE LOY 4
BO SUBA Extended El CMPB 4+ 2+ 10BF STY Extended 4
Bl CMPA 3 E2 SBCB 4+ 2+ Immed 4
lOCE LOS 4
B2 SBCA 3 E3 AODD 6+ 2+ lODE LOS Direct 6 3
B3 SUBO 3 E4 ANDB 4+ 2+ 100F STS Direct 6 3
B4 ANOA 5 3 E5 BITB 4+ 2+ lOEE LOS Indexed 6+ 3+
B5 BITA 5 3 E6 LDB 4+ 2+ lOEF STS Indexed 6+ 3+
B6 LOA 5 3 E7 STB 4+ 2+ 10FE LDS Extended 7 4
B7 STA 5 3 E8 EORB 4+ 2+ 10FF STS Extended 7 4
B8 EORA 5 3 E9 AOCB 4+ 2+ 113F SWI3 Inherent 20 2
B9 ADCA 5 3 EA ORB 4+ 2+ 1183 CMPU Immed 4
BA ORA 3 EB ADOB 4+ 2+ 118C CMPS Immed 5 4
BB ADDA 3 EC LOO 5+ 2+

1j
1193 CMPU Direct 7 3
BC CMPX 3 ED STD 5+ 2+ 119C CMPS Direct 7 3
BO JSR 3 EE 2+
LDU 5+ 11A3 CMPU Indexed 7+ 3+
BE LDX 3 EF STU Indexed 5+ 2+ 11AC CMPS Indexed 7+ 3+
BF STX Extended 6 3 llB3 CMPU Extended 8 4
FO SUBB Extended 5 3
llBC CMPS Extended 8 4
Fl CMPB 5 3
F2 SBCB 5 3
F3 AOOO 7 3
F4 ANOB 5 3
F5 BITB 5 3
F6 LOB 5 3
F7 STB 5 3
NOTE All unused opcodes are both undefined F8 EORB 5 3
and Illegal F9 ADCB 5 3
FA ORB 5 3
FB AODB Extended 5 3
FC LDD Extended 6 3
FO
FE
FF
STD
LDU
STU
t
Extended 6
~
3
3
3

4-293
 MC6809-MC68A09-MC68B09

FIGURE 21 - PROGRAMMING AID

Addressing Mod..

Instruction Forms
Immediate
Op - # Op
Direct
- #
Indexed
OJ! - # Op
Extended
- , Op
Inherent
- I Description
5 3 2 1 0
H N Z V C
ABX
ADC ADCA
ADCB
89
C9
2
2
2
2
99
D9
4
4
2
2
A9
E9
4+
4+
2+
2+
B9
F9
5
5
3
3
3A 3 1 B+X-X (Unsigned)
A+M+C-A
B+M+C-B
···· ·
I
I
I
I
I
I
I
I
I
I
ADD AOOA 88 2 2 9B 4 2 A8 4+ 2+ 88 5 3 A+M-A I I I I I
AOOB CB 2 2 DB 4 2 EB 4+ 2+ FB 5 3 8+ M-8 I I I I I

AND
AOOO
ANDA
C3
84
4
2
3
2
03
94
6
4
2
2
E3 6+
A4 4+
2+
2+
F3
B4
7
5
3
3
D+M M+ 1-D
AA M-A ·· I
I
I
I
I
0
I

··
AN DB
ANOCC
C4
1C
2
3
2
2
D4 4 2 E4 4+ 2+ F4 5 3 B A M-B
CC A IMM-CC · I I a
7

~I[H
ASL ASLA 48 2 1 8 I I I I
ASLB
ASL 08 6 2 68 6+ 2+ 78 7 3
58 2 1
M c
Ililllll-o
b7 bO
8
8
I
I
I
I
I
I
I
I

~lqlmTIlHJ ···
ASR ASRA 47 2 1 8 I I I
ASR8 57 2 1 8 I I I
ASR 07 6 2 67 6+ 2+ 77 7 3 b7 60 c 8 I I I
BIT BITA
BITB
85
C5
2
2
2
2
95
D5
4
4
2
2
A5
E5
4+
4+
2+
2+
85
F5
5
S
3
3
Bit Test A (M A A)
Bll Test B (M A BJ ·· ··
I
I
I
I
a
a

···
CLR CLRA 41 2 1 a-A a 1 a a
CLRB 5F 2 1 O-B a 1 a a

•
CLR OF 6 2 6F 6+ 2+ 7F 7 3 O-M a 1 a 0
CMP CMPA 81 2 2 91 4 2 A1 4+ 2+ B1 5 3 Compare M from A 8 I I I I
CMPB C1 2 2 D1 4 2 E1 4+ 2+ F1 5 3 Compare M from B 8 I I I I
CMPO 10
83
5 4 10
93
7 3 10
A3
7+ 3+ 10
B3
8 4 Compare M M + 1 from 0
·I I I I

CMPS 11
8C
5 4 11
9C
7 3 11
AC
7+ 3+ 11
BC
8 4 Compare M M + 1 from S
· I I I I

CMPU 11
83
5 4 11
93
7 3 11
A3
7,
" 11
B3
8 4 Compare M M + 1 from U
· I I I I

··
CMPX BC 4 3 9C 6 2 AC 6+ 2+ BC 7 3 Compare M M + 1 from X I I I I
CMPY 10 5 4 10 7 3 10 7+ 3+ 10 8 4 Compare M M + 1 from Y I I I I
8C 9C AC 8C
COM COMA 43 2 1 A-A
·t I a 1

··
COM8 53 2 1 B-B I I a 1
COM 03 6 2 63 6+ 2+ 73 7 3 M-M I I 0 1
CWAI 3C "2( 2 CC A IMM-CC Walt for Interrupt 7
DAA
DEC OECA
19
4A
2
2
1 DeCimal Adju,,\ A
1 A-1 A ·· ·
I
I
I
I
0 I

·· ··
I
OECB 5A 2 1 B-1-B I I I
DEC OA 6 2 bA 6+ 2+ 7A 7 3 M-1-M I I I
EOR EORA
EOR8
88
C8
2
2
2
2
98
08
4
4
2
2
A8 4+
E8 4+
2+
2+
B8
F8
5
5
3
3
A¥M-A
B¥ M-B ·· ··
I
I
I
I
a
0
EXG
INC
R1, R2
INCA
1E
4C
8
2
2 nJ- R22
1 A+ 1-A ·· · · · ··
I I I

··· · · · ···
INCB 5C 2 1 B + 1-8 t I I
INC OC 6 2 6C 6+ 2t 7C 7 3 M+ l-M I I I
JMP OE 3 2 6E 3+ 2+ 7E 4 3 EA3_ PC
JSR
LD LOA 86 2 2
90
96
7
4
2
2
AD
A6
7+
4+
2+
2+
BD
B6
8
5
3
3
Jurnp to Subroutine
M-A I
·· · · · ··
I 0

··· ···
LOB C6 2 2 06 4 2 E6 4+ 2+ F6 5 3 M-B I I 0
LOD cC 3 3 DC 5 2 EC 5+ 2+ FC 6 3 MM+l-D I I a
LOS 10 4 4 10 6 3 10 6+ 3+ 10 1 4 MM+l-S I I a
CE DE EE FE
LOU
LOX
CE
8E
3
3
3
3
DE
9E
5
5
2
2
EE
AE
5+
5+
2+
2+
FE
BE
6
6
3
3
MM+l-U
M M -+ l-X
I
I ··I
I
0
0 ··
LOY 10
8E
4 4 10
9E
6 3 10
AE
6+ 3+ 10
BE
7 4 M M-+ l-Y I I
· a
·
LEA LEAS
LEAU
32
33
4+
4+
2+
2+
EA3_. S
EA3_ U ·· ·· ·· ·· ··
·· ·· ·· ··
LEAX 30 4+ 2+ EA3_X I
LEAY 31 4+ 2+ EA3_ y I

Legend M Complement of M Test and set If true, cleared otherWise

OP Operation Code (Hexadecimal) Transfer Into Not Affected
Number of MPU Cycles H Half-carry (from bit 31 CC Condition Code Register
Number of Program Bytes N Negative (sign bit) Concatenation
+ Arithmetic Plus Z Zero result V Logical or
Anthmetlc Minus V Overflow, 2' 5 complement A Logical and
Multiply C Carry from ALU 'f Logical ExclUSive or

4·294
MC6809-MC68AOO-MC68BOO

FIGURE 21 - PROGRAMMING AID (CONTINUED)

Addr...ing Mod"

Inltruction Forma Op
Immediate
- , Op
Direct
- , Op
Indexed
- , Extended
Op - , Op
Inherent
- , Description
5 3 2 1 0
H N Z VI"
LSL LSLA
·
··· ·
48 2 1 I I I I
LSLB
tSL 08 6 2 58 6+ 2+ 78 7 3
58 2 1 ~I[H
A

c b7
-
11111111-
bO
0 I I I I
I I I I
a
~Io ~ 1t t t t t t HJ
LSR LSRA 44

·· ··
2 1 I I
LSRB 54 2 1 a I I
LSR 04 6 2 64 G+ 2+ 74 7 3 M b7 bO c a I I
MUL
NEG NEGA
NEGB
3D
40
50
11
2
2
1 Ax B-O IUnslgnedl
1 A+ I-A
1 B+ l-B
8
B
·· ·
I
I
I
I
I
I
I
9
I
I
NEG 00 6 2 60 6+ 2+ 70 7 3 M+l-M 8 I I I I

··· · · · ···
NOP 12 2 1 No Operatloll
OR ORA 8A 2 2 9A 4 2 AA 4+ 2+ BA 5 3 A V M-A I I a
ORB CA 2 2 DA 4 2 EA 4+ 2+ FA 5 3 B V M-B I I 0
ORCC lA 3 2 CC V IMM-CC 7
PSH PSHS
PSHU
34 5+
36 5+ 4
2
2
PUS!I Registers on S Stack
Push Reqlsters on U Stack ·· ·· ·· ·· ··
PUL PULS
PULU
35 5+
37 5+ 4
2
2
Pull ReglstPfs irorn S Stack
Pull Registers !rom U Stack ·· ·· ·· ·· ··
ROL ROLA 49 2 1
~1L{Ht ·
I I I I

··· ·
t t t t t tP
II
ROLB £,g 2 1 I I I I
ROL 09 6 2 69 6+ 2+ 79 7 3 c b7 50 I I I I

~l qJ:Oj t t t t t t tP
ROR RORA 46 2 1 I I I

RTI
RORB
ROR 06 6 2 66 6+ 2+ 76 7 3
56

3B 6/lt
2 1
c b7
1 Return From Interrupt
bO ·· ··
I
I
I
I
I
I
7
RTS
SBC S8CA
SBCB
82
C2
2
2
2
2
92
D2
4
4
2
2
A2
E2
4+
4+
2+
2+
82
F2
5
5
3
3
39 5 1 Return trOni Subroutine
A M C-A
8 - M"- C- 8
8 I
8 1
·····
I
I
I
I
I
I

··· a ···
SEX lD 2 1 Sign Extend B ,nlO A I I 0
ST STA 97 4 2 A7 4+ 2+ B7 5 3 A-M I I a
STB D7 4 2 E7 4+ 2+ F7 5 3 B-M I I

·· ··
STD DD 5 2 ED 5+ 2+ FD 6 3 D-MM+l I I a
STS 10 6 3 10 6+ 3+ 10 7 4 S-M M t 1 I I 0
DF EF FF
STU
STX
DF
9F
5
5
2
2
EF
AF
5+
5+
2+
2+
FF
BF
6
6
3
3
U-MM+l
X-M M + 1
I
I·· a ··
I
I
a
0

SUB
STY

SUBA 60 2 2
10
9F
90 4
6 3

2
10
AF
AO
6+
4+
3+
2+
10
BF
BO
7

5
4

3
Y-MM+l

A-M-A 8
I

I
· ·
I

I I I
SUB8 CO 2 2 DO 4 2 EO 4+ 2+ Fa 5 3 B- M-B 8 I I I I

SWI
SU8D
SWI 6
83 4 3 93 6 2 A3 6+ 2+ B3 7 3 D-M M+l-D
·· · · · ·
I I I I

· ·· · ·
3F 19 1 Software Interrupt 1
SWI6 10 20 2 Software Interrupt 2
3F
SWI6 11
3F
20 1 Software If"1terrupt 3
·····
SYNC
TFR Rl, R2
13
IF
2:4
6
1 Synchronize to Interrupt
2 Rl-Ril
·· ·· ·· ·· ··
··· ···
TST TSTA 4D 2 1 Test A I I a
TSTB 5D 2 1 Test B I I a
TST aD 6 2 6D 6+ 2+ 7D 7 3 Test M I I a

Notes
ThiS column gives a base cycle and byte count To obtam total count, add the values obtamed from the INDEXED ADDRESSING MODE table,
Table 2
Rl and R2 may be any pair of 8 bit or any pair of 16 bit registers
The 8 bit registers are A, B. CC. DP
The 16 bit registers are X. Y. U. S. D. PC
EA IS the effective address
4 The PSH and PUL Instructions require 5 cycles plus 1 cycle for each byte pushed or pulled
5(61 means 5 cycles If branch not taken, 6 cycles If taken (Branch instructions)
6 SWI sets I and F bits SWI2 and SWI3 do not affect I and F
Conditions Codes set as a direct result of the Instruction
8 Vaue of half-carry flag IS undefined
9 SpeCial Case - Carry set If b7 IS SET

4·295
 MC6809- MC68A09-MC68B09

FIGURE 21 - PROGRAMMING AID

(CONCLUDED)

Branch Instructions

Addl8lling Addressmg
Mode Mode

InatruCbon Fonno OP
u·
-9 , DeacrlptlOn
S 3 2 1 0
H N Z V C Instruction Forms OP - I Description
5 3 2 1 0
H N Z V C
BCC BCC
lBCC
24
10
3
5161
2 Branch C-O
4 Long Branch ·· ·· ·· ·· ·· BlS BlS 23 3 2 Branch Lower
·····
·····
Of Same
24 c=o lBlS 10 5161 4 Long Branch Lower
BCS BCS
lBCS
25
10
25
3
5161
2 Branch C= 1
4 long Branch
C=1
·· ·· ·· ·· ·· BlT BLT
lBlT
23
;c--
or Same
2D 3" 2 Branch < Zero
10 516} 4 Long Branch<Zero ·· ·· ·· ·· ··
BEQ BEQ 27 3 2 Branch Z=l
·· ·· ·· ·· ·· 2D

·· ·· ·· ·· ··
lBEQ 10 5161 4 long Branch BMI BMI 2B 3 2 Branch Mmus
27 z=o LBMI 10 5161 4 Long Branch Mmus
BGE BGE
lBGE
2C
10
2C
3
5161
2 Branch~Zero
4 long Branch~Zero ·· ·· ·· ·· ·· BNE BNE
lBNE
2B
26 3 2 Branch Z=O
10 5161 4 Long Branch ·· ·· ·· ·· ··
·· ·· ·· ·· ··
BGT BGT 2E 3 2 Branch>lero 26 Z.. O

·· ·· ·· ·· ··
lBGT 10 5161 4 long 8ranch>Zero BPl BPl 2A 3 2 Branch Plus
2E lBPl 10 5161 4 Long Branch Plus

·· ·· ·· ·· ··
CaiiI 2A

··· ··· ··· ··· ···

BHI 22 3 2 Branch Higher -

•
lBHI 10 5161 4 Long Branch Higher BRA BRA 20 3 2 Branch Always
22 LBRA 16 5 3 Long Branch Always
BHS BHS 24 3 2 Branch Higher
·· · ·· BRN BRN
LBRN
21 3
5
2 Branch Never
4 Long Branch Never
·····
·····
or Same 10
lBHS 10 5161 4 Long Branch Higher 21

· ·· ·· ·· ··
24 or Same BSR BSR BD 7 2 Branch to Subroutine -
BlE BlE
lBlE
2F 3
10 5161
2 Branch:s Zero
4 Long BranchsZero ·· ·· ·· ·· ·· lBS" 17 9 3 Long Branch to
Subroutine

··...·· ·· ·· ··
2F BVC BVC 28 3 2 Branch V-O

·· ·· ·· ·· ··
-.-
fsi:o' BlO 25 3 2 Branch lower lBVC 10 5161 4 Long Branch
lBlO 10 I 5(6) 4 Long Branch Lower 2B v=o

-:- ·· ·· ··
BVS BVS 2B 3 2 Branch V-1
25 lBVS 10 5161 4 Long Branch
1 2B V~1

SIMPLE BRANCHES
OP SIMPLE CONDITIONAL BRANCHES (Notes 1-4)
BRA 20 3 Test True OP Fal.e OP
lBRA 16 5 N=l BMI 2B BPl 2A
BRN 21 2 Z=1 BEa 27 BNE 26
lBRN 1021 4 V=l BVS 29 BVC 28
BSR 80 7 2 C=l BCS 25 BCC 24
lBSR 17 9 3

SIGNED CONDITIONAL BRANCHES (Note. 1·4) UNSIGNED CONDITIONAL BRANCHES (Notos H)

Test True OP False OP Test True OP Fal.e OP
r>m BGT 2E BlE 2F r>m BHI 22 BlS 23
r"'m BGE 2C BlT 20 r2::;m BHS 24 BlO 25
r=m BEa 27 BNE 26 r=m BEQ 27 BNE 26
rsm BlE 2F BGT 2E rsm BlS 23 BHI 22
r<m BlT 20 BGE 2C r<m BlO 25 BHS 24

Notes
1 All condItIonal branches have both short and long vanatlons
2 All short branches are 2 bytes and require 3 cycles
3 All condItional long branches are tormed by prefixing the short branch opcode with $10 and uSing a 16 blt destination offset H

4 All conditional long branches require 4 bytes and 6 cycles If the branch IS taken or 5 cycles If the branch IS not taken

4-296
MC6809. MC68A09. MC68B09

ORDERING INFORMATION

MC68A09C P

Motorola Integrated CirCUit

M6800 Family -
""TTfJ
Blanks~ 10 MHz
A~l 5 MHz
B~20 MHz
Device Designation
In M6800 Family
Temperature Range _ _ _ _ _ _ _ _ _.J
Blank = 0°_ + 70°C
C~ -40'- +85'C
Package _ _ _ _ _ _ _ _ _ _ _ _ _--.J
P = Plastic
S ~ Cerdlp
L = Ceramic

BEITER PROGRAM

Better program proceSSing IS available on all types listed Add

suffix letters to part number

Levell add "S"

Levell "S'~
Level 2 add "D" Level 3 add "DS"

10 Temp Cycles - 1-25 to 150'CI,

HI Temp testing at T A max
Level 2 "0 '= 168 Hour Burn-In at 125°C
Level 3 "OS" = Combination of Levelland 2
•

4·297
 MC6809E
(1.0 MHz)

@ MOTOROLA MC68A09E
(1.5 MHz)
MC68B09E
(2.0 MHz)

8-BIT MICROPROCESSING UNIT

The MC6809E IS a revolutionary high performance 8-blt microprocessor HMOS
which supports modern programming techniques such as position in- (HIGH-DENSITY N-CHANNEL, SILICON-GATE)
dependence, reentrancy, and modular programming.
This third-generation addition to the M6800 family has major architectural 8-BIT
Improvements which Include additional registers, Instructions and addreSSing MICROPROCESSING
modes.
UNIT
The basIc instructions of any computer are greatly enhanced by the
presence of powerful addreSSing modes The M C6809E has the most com-
plete set of addreSSing modes available on any 8-blt microprocessor today.
The MC6809E has hardware and software features which make It an Ideal
processor for higher level language execution or standard controller applica-
tions. External clock Inputs are proVided to allow synchronization With
peripherals, systems or other MPUs.
MC6800 COMPATIBLE L SUFFIX
• Hardware - Interfaces With All M6800 Peripherals CERAMIC PACKAGE
• Software - Upward Source Code Compatible Instruction Set and CASE 715

~
AddreSSing Modes
ARCHITECTURAL FEATURES
PSUFFIX
~"':; ...

•
• Two 16-blt Index Registers PLASTIC PACKAGE
• Two 16-blt Indexable Stack POinters
• Two 8-blt Accumulators can be Concatenated to Form One 16-Bit
f,.;' <.f CASE 711

~
Accumulator
• Direct Page Register Allows Direct AddreSSing Throughout Memory ........... SSUFFIX
HARDWARE FEATURES . . . . . . . . CERDIP PACKAGE
• External Clock Inputs, E and Q, Allow SynchronizatIOn CASE 734
• TSC Input Controls Internal Bus Buffers
• L1C Indicates Opcode Fetch
• AVMA Allows EffiCient Use of Common Resources In
A Multiprocessor System
• BUSY IS a Status Line for Multiprocessing FIGURE 1 - PIN ASSIGNMENT
• Fast Interrupt Request Input Stacks Only Condition Code Register
and Program Counter Vss
• Interrupt Acknowledge Output Allows Vectoring By DeVices
• SYNC Acknowledge Output Allows for SynchronizatIOn to External NMi
Event iRa
• Single Bus-Cycle RESET
• ~Ie 5-Volt Supply Operation
Fi1i1l
• NMI Inhibited After REStT Until After First Load of Stack POinter SS'
• Early AddreSil Valid Allows Use With Slower MemOries SA
• Early Write-Data for DynamiC MemOries
SOFTWARE FEATURES Vee
• 10 AddreSSing Modes AO
• M6800 Upward Compatible AddreSSing Modes
AI'
• Direct AddreSSing Anywhere In Memory Map
• Long Relative Branches A2
• Program Counter Relative A3
• True Indirect AddreSSing
• Expanded Indexed AddreSSing: A4
0, 5, 8, or 16-blt Constant Offsets A5
8, or 16-blt Accumulator Offsets
Auto-Increment/ Decrement by 1 or 2 A6 14
• Improved Stack Manipulation A7 15
• 1464 Instructions With Unique AddreSSing Modes AB 16
• 8 x 8 Unsigned Multiply
• 16-blt ArithmetiC A9 17
• Transfer/Exchange All Registers Al0 18
• Push/Pull Any Registers or Any Set of Registers
• Load Effective Address All 19

A12 20

4-298
MC6809EeMC68A09EeMC68B09E

MAXIMUM RATINGS
Rating Symbol Value Unit ThiS device contains circuitry to protect the
Supply Voltage -03to+70 V Inputs against damage due to high static
Vcc
voltages or electriC fields, however, It IS ad-
Input Voltage Vin -03to+70 V
vised that normal precautions be taken to
Operating Temperature Range TL to TH avoid application 01 any voltage higher than
MC6809E, MC68A09E, MC68B09E TA o to + 70 °c maximum rated voltages to thiS high Im-
Storage Temperature Range Tstg -55to+150 pedance CirCUit.
°c
Reliability of operation IS enhanced If unus-
ed Inputs are tied to an appropriate logic
voltage level le.g., either VSS or VCC!.
THERMAL CHARACTERISTICS
Characteristic Symbol Value Unit
Thermal Resistance
Ceramic 50
Cerdlp 8JA 60 °C/W
Plastic 100

POWER CONSIDERATIONS

The average chip-Junction temperature, TJ, In °c can be obtained from

TJ=TA+I POo8JAI 111
Where
TA-Amblent Temperature, °c

•
8JA. Package Thermal Resistance, Junctlon-to-Amblent, °C/W
PO- PINT+ PPORT
PINT-ICCxVCC, Watts - Chip Internal Power
PPORT- Port Power OISSlpatlon, Watts - User Oetermlned
For most applications PPORT<C PINT and can be neglected. PPORT may become Significant If the device IS configured to
drive Oarllngton bases or sink LEO loads.
An approximate relationship between Po and T J Ilf PPORT IS neglectedl IS'
PO= K - IT J+273°CI 121
SolVing equations 1 and 2 for K gives.
K = PoolT A + 273°CI +8JAo P0 2 131
Where K IS a constant pertaining to the particular part K can be determined from equation 3 by measuring Po lat equllibrluml
for a known T A USing thiS value of K the values of Po and TJ can be obtained by solVing equations 111 and 121 iteratively for any
value of T A

DC ELECTRICAL CHARACTERISTICS IVCC=5 0 V ±5%, VSS=O, TA=TL to TH unless otherWise noted)

Characteristic Symbol Min Typ Max Unit
Logic, G, V,H VSS + 20 VCC
Input High Voltage -
RtStT V,HR VSS + 40 VCC V
E V,HC VCC-O 75 - VCC+O 3
Input Low Voltage Logic, G, HEt;E I V,L VSS 03 VSS + 08 V
E V'LC VSS-03 - VSS+O.4
Input Leakage Current Logic, G, RESEI 2.5
lin ~A
IV In = Ot0525V,VCC = max} E - - 100
DC Output High Voltage
IILoad = -205~A, VCC = mini 00-07 VSS + 24 - - V
VOH - -
IILoad = - 145 ~A, VCC = mini AO-A15, R/W VSS + 24
IILoad = - 100 ~A, VCC = mini BA, BS, L1C, AVMA, BUSY VSS + 24 - -
DC Output Low Voltage
IILoad = 20 mA, VCC = min)
VOL - - VSS + 05 V

Internal Power DISSipation (Measured at T A - T L In Steady State OperatlOn) P,NT 1.0 W

Capacitance· CIn
IV In = 0, 1 A = 25°C, 1 = I 0 MHz) 00-07, Logic Inputs, G, RESET - 10 15
pF
E - 30 50
AO-A15, R/W, BA, BS
Cout - 10 IS pF
L1C, AVMA, BUSY
Frequency of Operation MC6809E 01 - 1.0
MC68A09E 1 01 - 1.5 MHz
(E and G Inputsl MC68B09E 01 - 2.0
Three-State 10ff State) Input Current 00-07 - 20 10
~A
IV In = 0 4 to 2 4 V, VCC = maxi AO-A1S, R/W ITSI - - 100

• Capacitances are periodically tested rather than 100% tested

4-299
 MC6809Ee MC68A09Ee MC68B09E

BUS TIMING CHARACTERISTICS (See Notes 1 2 3 and 41

ldent. MC6809E MC68A09E MC68B09E
Characteristics Symbol Unit
Number Min Max Min Max Min Max
1 Cycle Time tcyc 10 10 0667 10 05 10 ~s

2 Pulse Width. E Low PWEL 450 9500 295 9500 210 9500 ns
3 Pulse Width. E High PWEH 450 9500 280 9500 220 9500 ns
4 Clock Rise and Fall Time t r , tf - 25 - 25 - 20 ns
5 Pulse Width, 0 High PWOH 450 9500 280 9500 220 9500 ns
7 Delay Time, E to 0 Rise tEO 1 200 - 130 100 ns
7A Delay Time, 0 High to E Rise tE02 200 - 130 - 100 - ns
7S Delay Time, E High to 0 Fall tE03 200 - 130 - 100 - ns
7C Delay Time, 0 High to E Fall tE04 200 - 130 - 100 - ns
9 Address Hold Time tAH 20 - 20 - 20 - ns
11 Address Delay Time from E Low (SA. BS, R/WI tAD - 200 - 140 .- 110 ns
17 Read Data Setup Time tDSR 80 - 80 40 ns
18 Read Data Hold Time tDHR 10 - 10 - 10 - ns
20 Data Delay Time from 0 tDDO - 200 - 140 - 110 ns
21 Wrrte Data Hold Time tDHW 30 - 30 - 30 - ns
29 Usable Access Time tACC 695 - 440 - 330 - ns

•
Control Delay Time (Figure 21 tCD - 300 - 250 .- 200 ns
Interrupts, HALT, RESET, and TSC Setup Time tpcs 200 - 140 - 110 - ns
(Figures 7, 8, 9, 10, 13, and 141
TSC Drrve to Valid LogiC Level (Figure 141 tTSV - 210 - 150 - 120 ns
TSC Release MaS Buffers to High Impedance I Figure 141 tTSR - 200 - 140 - 110 ns
TSC Three·State Delay Time (Figure 141 tTSC - 120 85 - 80 ns
tPCr, - 100 100 - 100 ns
Processor Control Rise and Fall Time (Figure 8) -
tPCf

FIGURE 2 - READ/WRITE DATA TO MEMORY OR PERIPHERALS

R/W, Address--n7V6i:x;1O(xlr-t--------t---------"~----__ttt'1\ii7
8A, BS

Read Data
Non-Muxed ---t--'t----t-t--------::::------------~-----_+-~

Write Data

Busy, LlC, -------t-~t"7:"AT'V"rT"':"IT'ITv+------------­

AVMA

NOTES:
~-----tCD------~
P<X')(XX)4
Not Valid

1. Voltage levels shown are VLSO 4 V, VIH",2 4 V, unless otherwise specified' 3 Hold time ( ®
I for SA and as IS not specified
2. Measurement pOints shown are 0.8 V and 2 0 V, unless otherwise specified 4 Usable access time IS computed by. 1 - 4 - 11 max - 17

4-300
MC6809E- MC68A09E-MC68B09E

FIGURE 3 - MC6809E EXPANDED BLOCK DIAGRAM

+--VCC
+--VSS

Instruction
Register

FiAO

•
IRO
'--.rr=::::!'-. LlC
. . - - - - l.. AVMA
R/iN
TSC

HALT
BA

BS
BUSY

* Internal Three-State Control

PROGRAMMING MODEL
FIGURE 4 - BUS TIMING TEST LOAD As shown In Figure 5, the MC6809E adds three registers to
the set available In the MC6800. The added registers Include
a Direct Page Register, the User Stack pOinter and a second
50V Index Register.

ACCUMULATORS (A, B, D)
The A and B registers are general purpose accumulators
which are used for arithmetic calculations and manipulation
Test POint o-..--.~ ..........
~ of data.
Certain instructions concatenate the A and B registers to
c form a single 16-blt accumulator. ThiS is referred to as the D
MM07000
Register, and IS formed with the A Register as the most
or EqUlv
significant byte

DIRECT PAGE REGISTER (DP)

C=3O pF for BA, BS, L1C, AVMA, BUSY The Direct Page Register of the MC6809E serves to
130 pF for 00-07 enhance the Direct AddreSSing Mode. The content of thiS
90 pF for AO·A 15, R/W register appears at the higher address outputs (AB-A 15) dur-
R = 11 7 kll for 00-07 Ing direct addreSSing instruction execution. ThiS allows the
165 kll for AO-A15, R/W direct mode to be used at any place In memory, under pro-
24 kll for BA, BS gram control To ensure M6800 compatibility, all bits of thiS
LlC, AVMA, BUSY register are cleared dUring Processor Reset.

4-301
 MC6809E-MC68A09E-MC68B09E

FIGURE 5 - PROGRAMMING MODEL OF THE MICROPROCESSING UNIT

15 o

,~,,~
x- Index Register
Y - Index Register

U - User Stack Pomter } ''''W

S - Hardware Stack POinter

PC Program Counter

, A I B
/
Accumulators
v
D

7 0
LI_____D_P_ _ _ _-'I Direct Page Register

7 0
I ElF I I I Iz I I I
H I N V C cc - Condition Code Register

• INDEX REGISTERS (X, YI

The Index Registers are used In Indexed mode of address-
Ing The 16-blt address In this register takes part In the
calculation of effective addresses This address may be used
to pOint to data directly or may be modlfed by an optional
constant or register offset. DUring some Indexed modes, the
contents of the Index register are Incremented
decremented to pOint to the next Item of tabular type data
All four pOinter register IX, Y, U, SI may be used as Index
or
FIGURE 6 - CONDITION CODE REGISTER FORMAT

'-----Zero
Carry
Overflow

' - - - - - - Negative
' - - - - - - - IRQ Mask
registers ' - - - - - - - - Half Carry
' - - - - - - - - - - FIRO Mask
STACK POINTER (U, 51 ' - - - - - - - - - - - - E n t l r e Flag

The Hardware Stack POinter lSI IS used automatically by

the processor dUring subroutine calls and Interrupts The
User Stack POinter lUI IS controlled exclUSively by the pro-
grammer thus allOWing arguments to be passed to and from
subroutines With ease. The U-reglster IS frequently used as a
stack marker Both Stack POinters have the same Indexed
mode addreSSing capabilities as the X and Y registers, but
also support Push and Pull instructions. ThiS allows the
MC6B09E to be used efficiently as a stack processor, greatly
enhanCing ItS ability to support higher level languages and CONDITION CODE REGISTER
modular programming. DESCRIPTION
BITO (el
NOTE Bita IS the carry flag, and IS usually the carry from the
The stack pOinters of the MC6B09E pOint to the top of binary ALU e IS also used to represent a 'borrow' from sub-
the stack, In contrast to the Me6800 stack pOinter, tract like Instructions (eMP, NEG, SUB, SBCI and IS the
which pOinted to the next free location on stack. complement of the carry from the binary ALU.

PROGRAM COUNTER BIT 1 (V)

The Program Counter IS used by the processor to pOint to Bit 1 IS the overflow flag, and IS set to a one by an opera-
the address of the next instruction to be executed by the pro- tion which causes a Signed two's complement arithmetiC
cessor. Relative AddreSSing IS provided allOWing the Pro- overflow. ThiS overflow IS detected In an operation In which
gram Counter to be used like an Index register In some situa- the carry from the MSB In the ALU does not match the carry
tions. from the MSB-l.

CONDITION CODE REGISTER BIT2 (ZI

The Condition Code Register defines the state of the pro- Bit 2 IS the zero flag, and IS set to a one If the result of the
cessor at any given time See Figure 6 prevIous operation was Identically zero

4-302
MC6809E-MC68A09E-MC68B09E

BIT3(N) Reset vectors are fetched from locations FFFE16 and FFFF16
Bit 31s the negative flag, which contains exactly the value (Table 1) when Interrupt Acknowledge IS true,
of the MSB of the result of the preceding operation Thus, a (BA - BS = 11 DUring Initial power-on, the Reset line should
negative two's-complement result will leave N set to a one. be held low until the clock Input signals are fully operational
Because the MC6809E Reset pin has a Schmitt-trigger in-
BIT 4 (I) put With a threshold voltage higher than that of' standard
Bit 4 IS the TRTI mask bit. The processor will not recognize peripherals, a simple R/ C network may be used to reset the
Interrupts from the mIT line If this bit IS set to a one NMI, entire system ThiS higher threshold voltage ensures that all
FTRQ, f!il1, m:sTI, and SWI all set I to a one, SWI2 and peripherals are out of the reset state before the Processor
SWI3 do not affect I
HALT
BITS (H) A low level on thiS Input pin Will cause the MPU to stop
Bit 5 IS the half-carry bit, and IS used to indicate a carry running at the end of the present Instruction and remain
from bit 3 In the ALU as a result of an 8-blt addition only halted indefinitely Without loss of data When halted, the BA
(ADC or ADD), This bit IS used by the DAA instruction to output IS driven high Indicating the buses are high Im-
perform a BCD decimal add adjust operation. The state of pedance BS IS also high which Indicates the processor IS In
this flag IS undefined In all subtract-like instructions the Halt state While halted, the MPU Will not respond to ex-
ternal real-time requests (FIRO, IROi although NMI or
BIT 6 IF) RESET Will be latched for later response DUring the Halt
Bit 6 IS the FIRO mask bit. The processor Will not °
state and E should continue to run normally A halted state

•
recognize Interrupts from the FIRO line If this bit IS a one (BA-BS= 11 can be achieved by pulling HALT low while
NMI, FIRO, SWI, and RESET all set F to a one. IRO, SWI2 RESET IS stili low See Figure 8
and SWI3 do not affect F.
BUS AVAILABLE, BUS STATUS (BA, BS)
BIT7 (E) The Bus Available output IS an Indication of an Internal
Bit 71s the entire flag, and when set to a one Indicates that control signal which makes the MOS buses of the MPU high
the complete machine state (all the registers) was stacked, Impedance When BA goes low, a dead cycle will elapse
as opposed to the subset state (PC and CC) The E bit of the before the MPU acqultes the bus BA Will not be asserted
stacked CC IS used on a return from Interrupt (RTIl to deter- when TSC IS actIVe, thus allOWing dead cycle consistency
mine the extent of the unstacklng. Therefore, the current E
left In the Condition Code Register represents past action. The Bus Status output signal, when decoded With BA,
represents the MPU state (valid With leading edge of 01

PIN DESCRIPTIONS MPU State

MPU State Definition
BA BS
POWER (Vss, Vee)
0 0 Normal (Running)
Two PinS are used to supply power to the part· VSS IS
0 1 Interrupt or RESET Acknowledge
ground or 0 volts, while V CC IS + 5 0 V ± 5%
1 0 SYNC Acknowledge
ADDRESS BUS (AO-A15) 1 1 HALT Acknowledge
Sixteen pins are used to output address Information from
-
the MPU onto the Address Bus When the processor does
not reqUire the bus for a data transfer, It will output address Interrupt Acknowledge IS Indicated dUring both cycles of a
hardware-vector-fetch (RESET, 'NMi", FIRO, 'lRG. SWI,
FFFF16, R/W = 1, and BS = 0, thiS IS a "dummy access" or
SWI2, SWI31 ThiS signal, plus decoding of the lower four
VMA cycle All address bus drivers are made hlgh-
Impedance when output Bus Available (BA) IS high or when address lines, can proVide the user With an indication of
TSC IS asserted. Each pin Will drive one Schottky TTL load or which Interrupt level IS being serViced and allow vectoring by
four LS TTL loads, and 90 pF deVice. See Table 1

DATA BUS (00-07)

TABLE 1 - MEMORY MAP FOR INTERRUPT VECTORS
These eight pins provide commUnication With the system Memory Map For
bl-dlrectlonal data bus. Each pin Will drive one Schottky TTL Vector Locations
lnterrupt Vector
load or four LS TTL loads, and 130 pF Description
MS LS
FFFE FFFF RESET
READ/WRITE (R/W)
FFFC FFFD NMI
ThiS signal indicates the direction of data transfer on the
FFFA FFFB SWI
data bus. A low indicates that the MPU IS writing data onto
the data bus. R/IN IS made high Impedance when BA IS high FFFB FFF9 IRO
or when TSC IS asserted FFF6 FFF7 FIRO
FFF4 FFF5 SWI2
RESET
FFF2 FFF3 SWI3
A low level on thiS Schmitt-trigger Input for greater than
FFFO FFFI Reserved
one bus cycle Will reset the MPU, as shown In Figure 7. The

4-303
 • s:
~
m
s:•

I m
FIGURE 7 - RESET TIMING

I m + 1 I m + 2 I m + 3 I m + 4 I m + 5 I m + 6 Im + 7 I I n I n + 1 I n + 2 I n + 3 I n + 4 I n + 5 I n + 6 I n + 7 I n + 8 I n + 9 I n + 10 I
I
m
s:•
~CD
~
m
Address -'-'-'",-,-UJl,==".J'==J'-,==J'-,-==-,''-,-,==-,,==,,.J'==J'-,_-=c! . ____ . ____ . ____ • ____ • ____ • ____ • ____ .,

~
Daw~Ul~~~_-1L-_-A__Jl_~~~~~~>r!.~~~~~~~_~L-_-J'~_~
~

Lie ..\,.\\l..lI..\,.I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- f

NOTE Tlmmg measurements are referenced to and from a low voltage of a8 volts and a high voltage of 2 0 volts, unless otherwise noted
 s:
(')

FIGURE 8 - HALT AND SINGLE INSTRUCTION EXECUTION TIMING FOR SYSTEM DEBUG ~
m
s:•
(')

~
Dead lnstructlon!lnstructlon! Dead
Cycle ! Fetch Execute Cycle Halted

m
Q
s:•
E
m
OJ
~
m

.J>. Bus
W Fetch Execute
0
01 R/W

BA _ _ _ _ _-----JI... \ I
BS ---------'/... \ I~---
Data
Bus
Instruction
Opcode

AVMA ~ ry I ,'-___
UC /
~----~ ~

NOTE Timing measurements are referenced to and from a low voltage of a 8 volts and a nigh voltage of 20 volts, unless otherwise noted

II
 MC6809Ee MC68A09Ee MC68B09E

Sync Acknowtedge is indicated while the MPU IS waiting defer the rearbitration of the next bus cycle to Insure the In-
for external synchronization on an interrupt line. tegrity of the above operations. ThiS difference prOVides the
HaitI Acknowledge is indicated when the MC6809E IS In a indivisible memory access required for a "test-and-set"
Halt condition. primitive, uSing anyone of several read-modify-wrlte instruc-
tions.
NON MASKABL.E INTERRUPT INMII" Busy does not become active dUring PSH or PUL opera-
A negative transition on this input requests that a non- tions. A typical read-modify-wrlte instruction (ASL) IS shown
maskable interrupt sequence be generated. A non-maskable In Figure 12. Timing information is given In Figure 13. Busy IS
interrupt cannot be inhibited by the program, and also has a valid tCD after the rising edge of O.
higher priority than Fiim, iRO or software interrupts. During
recognition of an NMi, the entire machine state is saved on AVMA
the hardware stack. After resat, an NMI will not be racog- AVMA is the Advanced VMA signal and Indicates that the
nized until the first program load of the Hardware Stack MPU will use the bus In the follOWing bus cycle The predic-
Pointer lSI. The pulse width of NMi low must be at least one tive nature of the AVMA Signal allows effiCient shared-bus
E cycle. If the Nfiifl input does not meet the minimum set up multiprocessor systems. AVMA IS LOW when the MPU IS In
with respect to 0, the interrupt will not be racognlzed until either a HALT or SYNC state AVMA IS valid tCD after the
the next cycle. See Figure 9. rising edge of O.

FAST-INTERRUPT REQUEST 1"FIIml*

A low level on thiS input pin will initiate a fast interrupt se- LIC
quence, provided ItS mask bit (F) In the CC IS clear. ThiS se- L1C (Last Instruction Cycle) IS HIGH dUring the last cycle

I
quence has PriOrity over the standard Interrupt Request of every instruction, and ItS tranSition from HIGH to LOW
(iRO), and is fast in the sense that it stacks only the contents will Indicate that the first byte of an opcode Will be latched at
of the condition code register and the program counter. The the end of the present bus c'{cle. L1C will be HIGH when the
interrupt service routine should clear the source of the inter- MPU is Halted at the end of an instruction, h.e., not In CWAI
rupt before dOing an RT!. See Figure 10. or RESET) In SYNC state or while stacking dUring Interrupts
L1C is valid tCD after th\l riSing edge of O.
INTERRUPT REQUEST liRO)*
A low level input on thiS pin will Initiate an Interrupt Re-
quest ~ence provided the mask bit (I) in the CC is clear. TSC
Since IRO stacks the entire machine state it provides a TSC (Three-State Controll will cause MOS address, data,
slower response to interrupts than FiRO. IRO also has a and R/iN buffers to assume a high-Impedance state. The
lower priOrity than FIRO. Again, the interrupt service routine control Signals (BA, BS, BUSY, AVMA and L1CI Will not go
should clear the source of the interrupt before dOing an RT!. to the high-impedance state. TSC IS Intended to allow a
See Figure 9. Single bus to be shared With other bus masters (processors
or DMA controllersl.
CLOCK INPUTS E, 0 While E is low, TSC controls the address buffers and R/W
directly. The data bus buffers dUring a write operation are In
E and 0 are the clock signals reqUIred by the MC6809E. 0
a high-impedance state until 0 rises at which time, If TSC IS
must lead E; that is, a transition on 0 must be followed by a
true, they will remain in a high-Impedance state. If TSC IS
similar tranSition on E after a minimum delay. Addresses will
held beyond the rising edge of E, then it will be Internally lat-
be valid from the MPU, tAD after the falling edge of E, and
ched, keeping the bus drivers in a high-Impedance state for
data will be latched from the bus by the falling edge of E.
the remainder of the bus cycle. See Figure 14.
While the 0 input is fully TIL compatible, the E input diractly
drives internal MOS circuitry and, thus, requires a high level
above normal TTL levels. This approach minimizes clock
skew Inherent With an Internal buffer. Timing and waveforms
for E and 0 are shown In Figure 2 while Figure 11 shows a MPU OPERATION
Simple clock generator for the MC6809E.
During normal operation, the MPU fetches an Instruction
BUSY from memory and then executes the requested function
Busy will be high for the read and modify cycles of a read- This sequence begins after RESET and IS repeated indefinite-
modify-write instruction and dUring the access of the first ly unless altered by a special Instruction or hardware occur-
byte of a double-byte operation (e.g., LOX, STD, ADDDI. rence. Software instructions that alter normal MPU opera-
Busy is also high during the first byte of any indirect or other tion are: SWI, SWI2, SWI3, CWAI, RTI and SYNC. An in-
vector fetch le.g., jump extended, SWI indirect etc.l. terrupt or HALT input can also alter the normal execution of
In a multi-processor system, busy indicates the need to instructions Figure 15 IS the flow chart for the MC6809E

'iiiMi, Film, and iiiO requests are sampled on the failing edge of O. One cycle IS reqUired for synchrOnization before these Interrupts are rec.st
nlzad. The pending interrupt(sl will not be serviced until completion of the current Instruction unless a SYNC or CWAI oondlllon IS present. If IRO
and FIRO do not remain low until completion of the current Instruction they may not be recognized. However, iiiMi IS latched and need only re-
!!!!!!!..!.ow for one cycle. No Interrupts are reoognlzed or latched between the failing edge of ifESEf and the roSlng edge of BS Indicating
RESET acknowledge. See REID sequence in the MPU flowchart In Figure 15.

4·306
 s:
i
~
FIGURE 9 - IRQ AND NMi INTERRUPT TIMING s:
last cycle
of Current
Instruction

I m-2 I m-l I
I·
m
Interrupt Stacking and Vector Fetch Sequence

I m+ 1 I m+2 I m+3 I m+4 I m+5 I m+6 I m+ 7 I m+S I m+9 Im+ 101 m+ 11 Im+ 12 Im+ 13 Im+ 14 Im+ 151m+ 161m+ 17 Im+ lSi
InstructIOn

•
Fetch
I
n n+ 1 I
I
m
s:•
~OJ
E·

~
Address ~~~>r----~--~---->r---'~---v----cr---'r----v----cr---'r---,r----v----'r---,,----\,---'r---,,----v----,r---.r----v---~~
B~
m
IRQ or
NMI
.j::>.

~
Data
VMA PCl PCH USl USH IYl IYH IXl IXH ~~~~

"'" R/W~ ,'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___

BA~'____________________________________

BS~ /
~

AVMA~===~A~:'==~~~======================================~~~~~~~~~~~~
==>.
BUSY
L1C / , 1\ c=..
L--_ _ __

"E clock shown for reference only

NOTE Timing measurements are referenced to and from a low voltage of 0 8 volts and a high voltage of 2 0 volts, unless otherwise noted

•
 • s::
~m
FIGURE 10 -FIRQ INTERRUPT TIMING

I
s::•
Last Cycle Iinstruction
lof Current ,- Interrupt Stacking and Vector Fetch Sequence • Fetch
InstructIon

!
I m-2 I m-1 m I m+1 m+2 I m+3 I m+4 I m+5 I m+6 I m+7 I m+B I m+9 n+1 n+

E'

Q '1'
s::
A~~:SS~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
-1 i..-tpcs PC PC FFFF SP - 1 SP - 2 SP - 3 $FFFF $FFF6 $FFF7 $FFFF New PC New PC+ 1 ~aI
~
~~~_I----------------------------------------------------------------------------------------- m

Data

i R/W~ \
PCH CCR New PCH

" - - - - - - - - -
New PCl

BA~
BS~~-------=------

~=-----------------~I \~___________
AVMA

BUSV:=J 1\ ~
LIC , - ---
\
E

• E clock shown for reference only

NOTE Timing measurements are referenced to and from a low voltage of 0 B volts and a high voltage of 2 0 volts. unless otherwise noted.
MC6809E-MC68A09E-MC68B09E

FIGURE 11 - MC6809E CLOCK GENERATOR

r ------------------,
I I
I I
I I
I I
I I
Optional
IMADY
MRDY(lrcUlt
I
I I
I I
I
!...----- ___ ..J

r--+----------(~Q to System and Processor

3
4 CLA
J OHf!."f.....'" P ....- - - - - : - = " D E to System
1 74~~76

><:H~-{:>E to Processor

4X

Q
+5V

NOTE If optional CirCUit IS not Included the CLR and PRE

Inputs 01 U2 and U3 must be tied high
•
MRDY

S'i'REi"Ci=i -----------111

FIGURE 12 - READ-MODIFY-WRITE INSTRUCTION EXAMPLE IASL EXTENDED INDIRECT)

Memory Memory
Location Contents Contents Descnptlon

PC- $0200 $68 ASL Indexed Opcode

$0201 $9F Extended Indirect Postbyte
$0202 $63 Indirect Address H,-Byte

--
$0203 $00 Indirect Address La-Byte

$0204 Next Main Instruction

--
$6300~ Effective Address HI-Byte

$6301~ Effective Address Lo-Byte

Target Data

4-309
 Last Cycle of
• 3:

~'1'
FIGURE 13 - BUSY TIMINC,
Current Instr

m-1 m I m+1 m+2 m+3 m+4 m+5 m+6 m+7 m+B m+9 I m+10 I n

Q 3:

!
m
•
3:
BUSY

LlC _ _ _-'
A~ ________________________________________________~

i
AVMA _ _ _-' ~
m
E

~
(,.)
.....
o
FIGURE 14 - TSC TIMING

Q\ 1 1 f_t pcs _

, ",Jk \ ~~
'"
R/W. AOOR
I77Jj f""
-
"''"1 t: "'"~ f -1
I

--l !---tDow ~
r\...-tT_sV_ _

;.;:..1-....:..;tTS,-,-V_ _

MPU DATA
-------,> c:J '-see
<'--r--
Note~
NOTE Data will be asserted by the MPU only dUring the Interval while R/W IS low and IE or OJ IS high
A composite bus cycle IS shown to give most cases of timing
Timing measurements are referenced to and from a low voltage of 0 B volts and a high voltage of 2 0 volts. unltess otherwise noted
 s:
~
FIGURE 15 - FLOWCHART FOR MC6809E INSTRUCTIONS

m
•
s:
(')

~
~
s:
~OJ
~
m

~
~
.....
.....

CWAI

Bus State BA I BS
Running 010
Interrupt or Reset Acknowledge o I 1
Sync Acknowledge o
Halt Acknowledge

Notes 1 Asserting RES"Ef will result In entering the reset

sequence from any pOint In the flow chart
BU S Y IS hIgh during first vector fetCh cycle

•
 MC6809E-MC68A09E- MC68B09E

ADDRESSING MODES

The basIc Instructions of any computer are greatly EXTENDED INDIRECT

enhanced by the presence of powerful addressing modes As a speCial case of Indexed addreSSing Id,scussed
The MC6809E has the most complete set of addressing below!, one level of Indirection may be added to Extended
modes available on any microcomputer today. For example, AddreSSing In Extended Indirect, the two bytes following
the MC6809E has 59 basIc Instructions, however, It the postbyte of an Indexed Instruction contain the address of
recognizes 1464 different vanatlons of instructions and ad- the data
dressing modes. The addressing modes support modern pro- LDA [CAT]
gramming techniques The following addressing modes are LDX [$FFFE]
available on the MC6809E'
STU [DOG]
Inherent Iinciudes Accumulator!
Immediate
Extended DIRECT ADDRESSING
Extended Indirect Direct addreSSing IS Similar to extended addreSSing except
that only one byte of address follows the opcode. ThiS byte
Direct
specifies the lower 8 bits of the address to be used The up-
Register per 8 bits of the address are supplied by the direct page
Indexed register. Since only one byte of address IS required In direct
Zero-Offset addreSSing, thiS mode requires less memory and executes

•
Constant Offset faster than extended addreSSing Of course, only 256 loca-
Accumulator Offset tions lone page! can be accessed without redefining the con-
Auto Incrementl Decrement tents of the DP register. Since the DP register IS set to $00 on
Indexed Indirect Reset, direct addreSSing on the MC6809E IS upward compati-
Relative ble with direct addreSSing on the M6800 Indirection IS not
Short/Long Relative Branching allowed In direct addreSSing. Some examples of direct ad-
Program Counter RelatIVe Addressing dreSSing are'
LDA where DP = $00
INHERENT (INCLUDES ACCUMULATOR! LDB where DP=$10
In this addressing mode, the opcode of the instruction LDD <CAT
contains all the address Information necessary Examples of
NOTE: < IS an assembler directive which forces direct
Inherent AddreSSing are ABX, DAA, SWI, ASRA, and
addreSSing
CLRB

IMMEDIATE ADDRESSING
REGISTER ADDRESSING
In Immediate AddreSSing, the effective address of the data
Some opcodes are followed by a byte that defines a
IS the location Immediately following the opcode II e., the
register or set of registers to be used by the instruction ThiS
data to be used In the instruction Immediately follows the op-
IS called a post byte Some examples of register addreSSing
code of the Instruction! The MC6809E uses both 8 and
are
16-blt Immediate values depending on the size of argument
TFR X, Y Tra~sfers X Into Y
specified by the opcode Examples of instructions with Im-
mediate AddreSSing are EXG A, B Exchanges A with B
LDA #$20 PSHS A, B, X, Y Push Y, X, B and A onto S
stack
LDX #$FOOO
PULU X, Y, D Pull D, X, and Y from U stack
LDY #CAT
NOTE: # signifies Immediate addreSSing, $ Signifies hexa-
decimal value to the MC6809 assembler.
INDEXED ADDRESSING
EXTENDED ADDRESSING
In all Indexed addreSSing, one of the pOinter registers IX,
In Extended AddreSSing, the contents of the two bytes Im-
Y, U, S, and sometimes PC! IS used In a calculation of the ef-
mediately following the opcode fully specify the 16-blt effec-
fective address of the operand to be used by the instructIOn
tive address used by the Instruction Note that the address
Five baSIC types of IndeXing are available and are discussed
generated by an extended instruction defines an absolute ad-
below The postbyte of an Indexed instruction specifies the
dress and IS not posItIOn Independent Examples of Extended
baSIC type and vanatlon of the addreSSing mode as well as
AddreSSing Include'
the pOinter register to be used. Figure 16 lists the legal for-
LDA CAT mats for the post byte Table 2 gives the assembler form and
STX MOUSE the number of cycles and bytes added to the baSIC values for
LDD $2000 Indexed addreSSing for each vanatlon

4·312
MC6809E-MC68A09E-MC68B09E

FIGURE 16 - INDEXED ADDRESSING PDSTBYTE

REGISTER BIT ASSIGNMENTS Zero-Offset Indexed - In thiS mode, the selected pOinter
Indexed register contains the effective address of the data to be used
Post-Byte Reaister B" by the Instruction ThiS IS the fastest Indexing mode
Addressing
7 6 5 4 3 2 1 0 Mode Examples are
a R R d d d d d EA = ,R + 5 Bit Offset LOO 0, X
1 R R a a a a a ,R+ LOA ,8
1 R R I a a a 1 ,R+ +
1 R R a a a 1 a ,-R Constant Offset Indexed - In thiS mode, a
1 R R I a a 1 1 ,- -R two's-complement offset and the contents of one of the
pOinter registers are added to form the effective address of
1 R R I a 1 a a EA = ,R +0 Offset
the operand The pOinter register's Initial content IS un-
1 R R I a 1 a 1 EA -, R + ACCB Offset
changed by the additIOn
1 R R I a 1 1 0 EA - .R + ACCA Offset
1 R R I 1 a a a EA = ,R +B Bit Offset Three sizes of offsets are available
1 R R I 1 a a 1 EA = ,R + 16 Bit Offset 5 -bit (-16 to + 151
1 R R I 1 a 1 1 EA - .R +0 Offset 8 -bit (-128 to + 127)
1 x x I 1 1 a a EA - ,PC +B Bit Offset 16-blt (- 32768 to + 32767)

-----
1 x x I 1 1 a 1 EA - ,PC + 16 Bit Offset
1 R R I 1 1 1 1 EA = [,Addressl The two's complement 5-blt offset IS Included In the
postbyte and, therefore, IS most efficient In use of bytes and
'----Addressing Mode Field cycles. The two's complement 8-blt offset IS contained In a

'--------Indtrect Field
ISlgn bit when b7 = Ol

' - - - - - - - - - - - - R e g l s t e r Field RR
00 = X
single byte following the postbyte The two's complement
16-bIt offset IS In the two bytes following the postbyte In
most cases the programmer need not be concerned with the
size of thiS offset since the assembler will select the optimal
size automatically
II
01 = Y Examples of constant-offset indeXing are'
10 = U LOA 23,X
11 = S LOX -2,8
x = Don't Care
LDY 3OO,X
d=Offset Bit
LOU CAT,Y
0= Not Indtrec!
1=
1 = Indtrect

TABLE 2 - INDEXED ADDRESSING MODE

Non Indirect Indirect
Type Forms Assembler Postbyte + + Assembler Postbyte + +

Constant Offset From R No Offset

Form
R
OP Code
lRRoolOO
-a #
a
Form
[ Rl
OP Code
lRR10100
-a
3
#

12's Complement Offsets) 5 Bit Offset n, R ORRnnnnn 1 a defaults to 8-bit

8 Bit Offset n, R lRR01000 1 1 tn, Rl lRRll000 4 1
16 8n Offset n, R lRROlOOl 4 2 tn, Rl lRRllool 7 2
Accumulator Offset From R A Register Offset A, R lRRooll0 1 a [A, Rl lRR10ll0 4 a
12's Complement Offsets) B Register Offset B, R lRRool0l 1 a [B, Rl lRR10l0l 4 a
o Register Offset D, R lRR01011 4 a [0, Rl lRRll011 7 a
Auto Increment/Decrement R Increment By 1 ,R+ lRROOOOO 2 a not allowed
Increment By 2 ,R+ + lRROOOOl 3 a l,R+ +1 ~ lRR1000l 6 a
Decrement By 1 ,-R lRROOO10 2 a not allowed
Decrement By 2 ,- -R lRROOOll 3 a l,- -Rl lRRl0011 6 a
Constant Offset From PC 8 Bit Offset n, PCR lxxOlloo 1 1 tn, PCRl lxxllloo 4 1
12's Complement Offsets) 16 Bit Offset n, PCR lxxOll0l 5 2 tn, PCRl lxxlll0l B 2
Extended Indtrect 16 Bit Address - - - - [nl 10011111 5 2
R - X, Y, U or S RR
x = Don't Care 00= X
01=Y
10=U
11 =S
::"'and ~ indicate the number of additional cycles and bytes respectively for the particular Indexing vanatlon

4·313
 MC6809E-MC68A09E-MC68B09E

Accumulator-Offset Indexed - This mode IS similar to $0100 LDA [$10,Xl EA IS now $F010
constant offset Indexed except that the two's-complement
value In one of the accumulators (A, B or D) and the con- $F010 $F1 $F150 IS now the
tents of one of the pOinter registers are added to form the ef- $F011 $50 new EA
fective address of the operand The contents of both the ac-
cumulator and the pOinter register are unchanged by the ad- $F150 $AA
dition. The postbyte specifies which accumulator to use as
an offset and no additional bytes are reqUired. The advan- After Execution
tage of an accumulator offset IS that the value of the offset A=$AA (Actual Data Loaded)
can be calculated by a program at run-time X=$FOOO
Some examples are:
All modes of Indexed indirect are Included except those
LDA B,Y
which are meaningless (e.g., auto Increment!decrement by
LDX D,Y
1 Indirect!. Some examples of Indexed indirect are
LEAX B,X
LDA LXJ
Auto Increment!Decrement Indexed - In the auto incre-
LDD [10,SJ
ment addreSSing mode, the pOinter register contains the ad-
LDA [B,YJ
dress of the operand. Then, after the pOinter register IS used
LDD LX+ +J
It IS Incremented by one or two. This addreSSing mode IS
useful In stepping through tables, moving data, or for the
creation of software stacks In auto decrement, the pOinter
register IS decremented prior to use as the address of the

•
RELATIVE ADDRESSING
data The use of auto decrement IS Similar to that of auto in- The byte(s) follOWing the branch opcode IS (are) treated as
crement, but the tables, etc, are scanned from the high to a Signed offset which (!lay be added to the program counter.
low addresses. The size of the Increment! decrement can be If the branch condition IS true then the calculated address
either one or two to allow for tables of either 8- or 16-blt data (PC + Signed offsetl IS loaded Into the program counter
to be accessed and IS selectable by the programmer The Program execution continues at the new location as In-
pre-decrement, post-Increment nature of these modes allow dicated by the PC; short (1 byte offset) and long (2 bytes off-
them to be used to create additional software stacks that set) relative addreSSing modes are available All of memory
behave Identically to the U and S stacks can be reached. In long relative addreSSing as an effective ad-
Some examples of the auto Increment! decrement ad- dress Interpreted modulo 216 Some examples of relative ad-
dressing modes are: dreSSing are:
LDA ,X+
STD ,Y+ +
BEG CAT (shortl
LDB ,-V BGT DOG (short)
LDX ,--S CAT LBEQ RAT (long)
Care should be taken In performing operations on 16-blt DOG LBGT RABBIT (long)
pOinter registers (X, Y, U, S) where the same register IS used
to calculate the effective address
ConSider the follOWing Instruction
STX O,X + + (X Initialized to 0) RAT NOP
The deSired result IS to store a 0 In locations $0000 and $0001 RABBIT NOP
then Increment X to pOint to $0002 In reahty, the follOWing
occurs
O-temp calculate the EA, temp IS a holding register
X+2-X perform autOincrement PROGRAM COUNTER RELATIVE
X-Itemp) do store operation The PC can be used as the pOinter register With B or 16-blt
signed offsets As In relative addreSSing, the offset IS added
to the current PC to create the effective address The effec-
INDEXED INDIRECT tive address IS then used as the address of the operand or
All of the indeXing modes With the exception of auto In- data Program Counter Relative AddreSSing IS used for
crement! decrement by one, or a ± 5-blt offset may have an wntlng position Independent programs Tables related to a
additional level of Indirection specified In indirect address- particular routine Will maintain the same relationship after
Ing, the effective address IS contained at the locatIOn the routine IS moved, If referenced relative to the Program
speCIfied by the contents of the Index Register plus any off- Counter Examples are
set In the example below, the A accumulator IS loaded in- LOA CAT, PCR
directly uSing an effective address calculated from the Index
LEAX TABLE, PCR
Register and an offset.
Before Execution Since program counter relative IS a type of IndeXing, an
A=XX (don't additional level of indirection IS available
care) LDA [CAT, PCRJ
X=$FOOO LDU [DOG, PCR1

4·314
MC6809E-MC68A09E-MC68B09E

MC6809E INSTRUCTION SET

The instruction set of the MC6809E IS similar to that of the TRANSFER/EXCHANGE POST BYTE
MC6800 and IS upward compatible at the source code level.
The number of opcodes has been reduced from 72 to 59, but
C@RC"f [ D~STl~AT(ON I
because of the expanded architecture and additional ad- REGISTER FIELD
dressing modes, the number of available opcodes (with dif- 0000 0 fA BJ 1000 A
ferent addreSSing modes) has nsen from 197 to 1464. 0001 X 1001 B
Some of the new instructions are descnbed In detail 0010 Y 1010 eCR
0011 U lOll DPR
below:
0100 S
0101 PC
PSHU/PSHS NOTE: All other combinations are undeftned and INVALID
The push Instructtons have the capability of pushing onto LEAX/ LEAY / LEAU/LEAS
either the hardware stack (S) or user stack (U) any single The LEA (Load Effective Address) works by calculating
register, or set of registers with a single instruction the effective address used In an Indexed instruction and
stores that address value, rather than the data at that ad-
dress, In a pOinter register ThiS makes all the features of the
PULU/PULS Internal addreSSing hardware available to the programmer
The pull instructions have the same capability of the push Some of the Implications of thiS Instruction are Illustrated In
Instruction, In reverse order. The byte Immediately follOWing Table 3
the push or pull opcode determines which register or The LEA Instruction also allows the user to access data
registers are to be pushed or pulled. The actual PUSH/PULL and tables In a position Independent manner For example'

•
sequence is fixed; each bit defines a umque register to push LEAX MSG1, PCR
or pull, as shown below LBSR PDATA (Pnnt message routine)

MSG1 FCC 'MESSAGE'

ThiS sample program prtnts 'MESSAGE' By wntlng
PUSH/PULL POST BYTE STACKING ORDER
MSG1, PCR, the assembler computes the distance between
PUlLOADEA
the present address and MSG1 ThiS result IS placed as a
CGR c'c constant Into the LEAX instruction which Will be Indexed
A A from the PC value at the time of execution No matter where
" -_ _ _ 8 8
DP
the code IS located, when It IS executed, the computed offset
X H, from the PC Will put the absolute address of M SG 1 Into the X
" - _ _ _ _ _ _ _ S/U
X Lo pOinter register ThiS code IS totally position Independent
YH,
"-_ _ _ _ _ _ _ _ _ PC
Y Lo
The LEA instructions are very powerful and use an Internal
U/S HI holding register (tempI. Care must be exerCised when uSing
U/S Lo the LEA Instructions With the autolncrement and autodecre-
PC HI
ment addreSSing modes due to the sequence of Internal
PC Lo
•
PUSH ORDER
operations. The LEA Internal sequence IS outlined as follows
LEAa ,b+ (any of the 16-blt pOinter registers X, Y, U
INCREASING or S may be substituted for a and b )
MEMORY 1 b-temp (calculate the EA)
~ 2 b+1-b (modify b, postlncrementl
3 temp-a (load a)
TFR/EXG
Within the MC6809E, any register may be transferred to or LEAa ,-b
exchanged With another of like-Size; i.e., B-bit to B-blt or
16-blt to 16-blt. Bits 4-7 of postbyte define the source 1 b-1-temp lcalculate EA With predecrement)
register, while bits 0-3 represent the destination register. 2. b-1-b (modify b, predecrementl
These are denoted as follows: 3 temp-a (load a)

TABLE 3 - LEA EXAMPLES

Instruction Operation Comment
LEAX 10,X X + 10 -X Adds 5-bit constant 10 to X
LEAX 5OO,X X+500-X Adds 16-blt constant 500 to X
LEAY A,Y Y+A -Y Adds S-blt A accumulator to Y
LEAY D,Y Y+D -Y Adds 16-blt D accumulator to Y
LEAU -10, U U - 10 -U Subtracts 10 from U
LEAS -10, S S - 10 -S Used to reserve area on stack
LEAS 10, S S + 10 -S Used to 'clean up' stack
LEAX 5, S S+5 -X Transfers as well as adds

4-315
 MC6809E·MC68AOSE·MC68BOSE

Autolncrement-by-two and autodecrement-by-two Instruc- dress bus, R/Vii = 1 and BS = O. The follOWing examples Il-
tions work similarly Note that LEAX ,X + does not change lustrate the use of the chart; see Figure 18.
X, however LEAX ,- X does decrement X LEAX 1,X should
be used to Increment X by one Example 1: LBSR (Branch Takenl
Before Execution SP = FOOO
MUL
Multiplies the unsigned binary numbers In the A and B ac-
cumulator and places the unsigned result Into the 16-blt D
accumulator. This unsigned multiply also allows multlple- $9000 LBSR CAT
preCISion multiplications

Long And Short Relative Branches

The MC6B09E has the capability of program counter $AOOO CAT
relative branching throughout the entire memory map In
CYCLE-BY-CYCLE FLOW
this mode, If the branch IS to be taken, the 8 or 16-blt signed
offset IS added to the value of the program counter to be us- Cycle # Address Data R/W Description
ed as the effective address This allows the program to 1 9000 17 1 Opcode Fetch
2 8001 20 1 Offset High Byte
branch anywhere In the 64K memory map. Position indepen-
3 8002 00 1 Offset Low Byte
dent code can be easily generated through the use of rei aWe 4 FFFF 1 VMA Cycle
branching Both short (8-blt) and long (16-blt) branches are 5 FFFF 1 VMA Cycle
available 6 AOOO 1 Computed Branch Address

•
7 FFFF 1 VMA Cycle
8 EFFF 80 0 Stack High Order Byte of
SYNC Return Address
After encountenng a Sync instruction, the MPU enters a 9 EFFE 03 0 Stack Low Order Byte of
Return Address
Sync state, stops processing Instructions and walts for an In-
terrupt If the pending Interrupt IS non-maskable (NMII or Example 2: DEC (Extended)
maskable (FIRO, IRO) With ItS mask bit (F or I) clear, the pro-
cessor will clear the Sync state and perform the normal Inter- $8000 DEC $AOOO
rupt stacking and service routine Since FIRO and IRO are $AOOO FCB $80
not edge-tnggered, a low level With a minimum duration of
three bus cycles IS required to assure that the Interrupt will CYCLE-BY-CYCLE FLOW
be taken If the pending Interrupt IS maskable (FIRO, IRO) Cycle # Address Data R/W Description
With ItS mask bit (F or II set, the processor will clear the Sync 1 9000 7A 1 Opcode Fetch
state and continue processing by execullng the next Inllne 2 8001 AO Operand Address, High Byte
instruction Figure 17 depicts Sync timing 3 8002 00 ~and Address, Low Byte
4 FFFF VMA Cycle
Software Interrupts 5 AOOO BO Read the Data
6 FFFF 1 VMA Cycle
A Software Interrupt IS an Instruction which will cause an 7 AOOO 7F 0 Store the Decremented Data
Interrupt, and ItS associated vector fetch. These Software In-
terrupts are useful In operating system calls, software "The data bus has the data at that particular address
debugging, trace operations, memory mapping, and soft-
ware development systems. Three levels of SWI are available
on thiS MC6B09E, and are pnontlZed In the following order MC6809E INSTRUCTION SET TABLES
SWI, SWI2, SWI3

16-Bit Operation The instructions of the MC6B09E have been broken down
IntO five different categones. They are as follows.
The MC6B09E has the capability of processing 16-blt data.
These instructions Include loads, stores, compares, adds, 8-Blt operation (Table 4)
subtracts, transfers, exchanges, pushes and pulls 16-Blt operation (Table 5)
Index register/stack pOinter Instructions (Table 61
Relative branches Iiong or short) (Table 7)
CYCLE-BY-CYCLE OPERATION Miscellaneous instructions !Table 8)
The address bus cycle-by-cycle performance chart Il- HexadeCimal values for the instructions are given In
lustrates the memory-access sequence corresponding to Table 9.
each possible Instruction and addressing mode In the
MC6B09E Each instruction begins With an opcode fetch.
While that opcode IS being Internally decoded, the next pro-
gram byte IS always fetched (Most instructions will use the
next byte, so thiS technique considerably speeds PROGRAMMING AID
throughput.) Next, the operation of each opcode will follow Figure 18 contains a compilation of data that will assist
the flow chart. VMA is an Indication of FFFF16 on the ad- you In programming the M C6B09E

4·316
 s:
FIGURE 17 - SYNC TIMING ~'1'
s:

~
Last Cycle Sync Last Cycle
of PrevIous Opcode Sync Acknowledge of Sync
IInstructIOn! Fetch ! Execute !- ... -!lnstructlOn!

'1'
o
s:
n
~
Address OJ
~
m
Data~J '" ~
-~
A/W~ ~~----~----------~
•

~
W
......
BA ===:A I '" \'-_________
-..,j

BS~ "'~----~---------------------------
AVMA~ \ ~. I
LlC ~ ·~~--~-~-l.h!t-PC-f----------;X See Note 1

lAO 'lL~il_~S=ee~N~0~te~2 _ _ _ _ _ _ _ _ _ _ _ _ ___

NMI
FIAO
VIL 1"-
r-tpcs
Notes 1 If the associated mask bit IS set when the Interrupt IS requested, Lie will go low and this cycle will be an instruction fetch from address
locatlOn PC+ 1 However, If the Interrupt IS accepted (NMI or an unmasked FTRO. or IRQ) Lie will remain high and Interrupt processing
will start with this cycle as Iml on Figures 9 and 10 Iinterrupt Tlmlngl
2 If mask bits are clear, IRQ andFi"RTI must be held low for three cycles to guarantee that Interrupt will be taken, although only one cycle
IS necessary to bring the processor out of SYNC

NOTE Timing measurements are referenced to and from a low voltage of a 8 volts and a high voltage of 2 0 volts, unless otherwIse noted

..
 FIGURE 18 - ADDRESS BUS CYCLE-BY-CYCLE PERFORMANCE
• 3:

i
ADDR= STATE OF ADDRESS BUS
C Fetch)
ADDR-Address of Opcode (Fetchl

'1'
3:

Long
Branch
Short
Branch
ImmedIate and
Inherent

Auto Aut
Indexed
Addr-Addr+ 1
I
PC + Extended No
I
m
•
3:
Inc/Dec Inc/Dec
VID.
Addr-Addr+l
Addr-Addr+ 1

vt
by 1 by2 R+16 B,ts R+D 16 BIts Indlfect Offset
i
Offset
ACCA
ACCB
R+5 BII
2m
Addr- Addr- Addr- Addr-
VF.;fA R+8 BIt
Addr+l Addr+l Addr+l
PC+8 BII I
VMA V~A
~ I I
(0)
.....
CO vw.
"ilf<1A
I
"ilf<1A
VMA
vw.
I
VMA
I
"ilf<1A
w.rA
I
VF.;fA
I
VF.;fA

N VMA
I
VMA
I
Stack Wnte
I
Stack Write

NOTES:
1 Busy = 1 dUring access of f,rst byte of double byte ,mmed,ate load.
2. All subsequent Page 2 and Page 3 prebytes WIll be Ignored after IOltlal opcode fetch
3 Write operation dUring store Instruction. ~ = 1 dunng flfst two cycles of a double-byte access and the flfst cycle of read-modlfy-wrlte access
4. AVMA is asserted on the cycle before a VMA cycle
 s::
~
FIGURE 191al - OPERATIONS. ADDRESS BUS CYCLE· BY-CYCLE PERFORMANCE

Inherent Page
SWI
From Figure 18 PSHU
PULU SWI2
ABX RTS TFR EXG MUL ~ PSHS SWI3 CWAI m
s::•
PULS RT.!

ASLA

I
ASLB
ASRA
ASRB ADDR
I
STACK IRI
CLRA
--.L
CLRB I VMA VMA VMA VMA VMA VMA
COMA VMA I I m
COMB
DAA
VMA
VMA
VMA VMA
s::•
~
DECA
DECB
INCA STACK IRI VMA VMA
I
ADDR-SP
STACKIW: STACKIWI
INCB STACKIWI STACKIWI
E~
OJ
LSLA
STACK IRI VMA VMA
I STACKIWI STACKIWI
~
VMA VMA VMA I Stack IWII ~ STACKIWI STACKIWI STACK IRI
LSLB VMA VMA Note 3 STACKIWi STACKIWI STACK IRI m
LSRA VlVfA VMA
IStack IRilb2STACKIWI STACKIWI STACK IRI
LSRB VMA VMA Note 3 STACK IWI STACKIWI STACK IRI
NEGA \iiV1A STACKIWI STACKIWI ST ACK IRI
NEGB VMA
~ STACKIWI STACKIWI STACK IRI STACK IRI
NOP
~
...... ROLA
VMA STACKIWI STACKIWI STACK IRI STACK IRI
STACKIWI STACKIWI STACK IRI
<0 ROLB
STACKIWI STACK IRI
RORA STICKIWI
STACK IRI
RORB
SEX
ADDR-SP I ~
STACK IRI

VMA IVMAI""
I I Note4
VECTOR IHI. VECTOR IHI.
BUSY-l BUSY-l Addr- SP
VECTOR Ill. VECTOR Ill.
BUSY-O BUSY-O
_I I
VMA VMA

~ ~
To Figure 18
NOTES
Stack IWI refers to the following sequence SP-SP-l. then ADDR-SP with Riw~o
Stack IRI refers to the follOWing sequence ADDR-SP with Riw~l. then SP-SP+ I
PSHU, PULU instructions use the user stack pOinter (I e, SP2EUl and PSHS, PULS use the hardware stack pOinter (I e, SPES)
Vector refers to the address of an Interrupt or reset vector (see Table 1)
The number of stack accesses Will vary according to the number of bytes saved
4 VMA cycles Will occur until an Interrupt occurs

II
 • ~

i
FIGURE 19(b) - OPERATIONS: ADDRESS BUS CYCLE-BY-CYCLE PERFORMANCE

Non-Inherents From Figure 18

'1'
ADCA LDD ASL TST ADDD JSR STD ~
ADCB

I
LOS ASR CMPD STS
ADDA LDU CLR CMPS STU
ADDB LDX COM CMPU STX
ANDA LDY DEC CMPX STY
ANDB INC CMPY
BITA LSL SUBD m
BITB
CMPA
ANDCC
ORCC
LSR
NEG
•
~
CMPB

~
ROL VMA
EORA ROR STACK IWI
EORB STACK IWI
LDA aJ
LDB
ORA f6
m
ORB
SBCA
SBCB
STA

"""
CN
I\)
STB
SUBA VMA, BUSY-1
SUBB ADDR-ADDR+1, ADDR-ADDR+1
0
TSTA
TSTB
BUSY-O

VMA
I
VMA
ADDR-ADDR + 1 VMA ADDR-A DR+1IWI

To Figure 18
NOTES
Stack IWI refers to the following sequence SP-SP-1, then ADDR-SP with R/W=O
Stack IRI refers to the following sequence, ADDR-SP with R/W= 1, then SP-SP + 1
PSHU, PULCI Instructions use the user stack pOinter lie, SP= UI and PSHS, PULS use the hardware stack pOinter II e , SP= SI
2 Vector refers to the address of an Interrupt or reset vector (see Table 1)
3 The number of stack accesses will vary according to the number of bytes saved
4 VMA cycles will occur until an Interrupt occurs
MC6809EeMC68A09EeMC68B09E

TABLE 4 - 8-BIT ACCUMULATOR AND MEMORY INSTRUCTIONS

---- ----- -- "----~---------

Mnemonlc(s) Operation
ADCA, ADCB Add memory to accumulator with carry
ADDA, ADDB Add memory to accumulator
ANDA, AN DB And memory with accumulator
ASL, ASLA, ASLB Anthmetlc shift of ac.cumulator or memory left
ASR,ASRA, ASRB Arithmetic shift of accumulator or memory nght
BITA, BITB Bit test memory with accumulator
CLR,CLRA,CLRB Clear accumulator or memory location
CMPA, CMPB Compare memory from accumulator
COM, COMA, COMB Complement accumulator or memory location
DAA Decimal adjust A accumulator
DEC, DECA, DECB Decrement accumulator or memory location
EORA, EORB Exclusive or memory with accumulator
EXG Rl, R2 Exchange Rl with R2 IR1, R2 ~ A, B, CC, DPI
INC, INCA, INCB Increment accumulator or memory location
LDA, LDB Load accumulator from memory
LSL, LSLA, LSLB Logical shift left accumulator or memory location
LSR, LSRA, LSRB Logical shift nght accumulator or memory location

•
MUL Unsigned multiply IA x B - DI
NEG, NEGA, NEGB Negate accumulator or memory
ORA,ORB Or memory with accumulator
ROL, ROLA, ROLB Rotate accumulator or memory left
ROR, RORA, RORB Rotate accumulator or memory right
SBCA, SBCB Subtract memory from accumulator with borrow
STA, STB Store accumulator to memory
SUBA, SUBS Subtract memory from accumulator
TST, TSTA, TSTB Test accumulator or memory location
TFR Rl, R2 Transfer Rl ta R2 (Rl, R2 ~ A, B, CC, DPI

NOTE A, B, CC ar DP may be pushed ta (pulled framl 8Ither stack with PSHS, PSHU IPULS,
PULU) Instructions

TABLE 5 - 16-BIT ACCUMULATOR AND MEMORY INSTRUCTIONS

Mnemonlc(s) OperatIon
ADDD Add memory to 0 accumulator
CMPD Compare memory from 0 accumulator
EXG D, R Exchange D with X, Y, S, U ar PC
LDD Load 0 accumulator from memory
SEX Sign Extend 8 accumulator Into A accumulator
STD Store 0 accumulator to memory
SUBD Subtract memory from 0 accumulator
TFR D, R Transfer D ta X, Y, S, U ar PC
TFR R, D Transfer X, Y, S, U or PC to 0

NOTE D may be pushed (pulledl ta either stack with PSHS, PSHU IPULS,
PULU) Instructions

4-321
 MC6809EeMC68A09EeMC68B09E

TABLE 6 - INDEX REGISTER/STACK POINTER INSTRUCTIONS

Instructton DeacripttOn
CMPS, CMPU Compare memory from stack pOinter
CMPX, CMPY Compare memory from Index register
EXG Rl, R2 Exchange 0, X, Y, S, U or PC with D. X, V, S, U or PC
lEAS, lEAU Load effective address Into stack pOinter
lEAX, lEAY Load effective address Into Index register
lDS, lDU Load stack pOinter from memory
lDX, lDY Load Index register from memory
PSHS Push A, B. ee, DP, D, X, V, U. or PC onto hardware stack
PSHU Push A, at ee, DP, D. X, Y, 5, or PC onto user stack
PUlS Pull A. B. ce. DP. D, X. Y, U or PC from hardware stack
PUlU Pull A, 8, ee, DP, 0, X, Y, S or PC from hardware stack
STS, STU Store stack pOinter to memory
STX, STY Store Index register to memory
TFR Rl, R2 Transfer 0, X, Y, 5, U or PC to D, X, Y, $, U or PC
ABX Add B accumulator to X (unsigned)

TABLE 7 - BRANCH INSTRUCTIONS

InstructIOn J DescriptIOn
SIMPLE BRANCHES
BEO, lBEO Branch .f equal

I
BNE, lBNE Branch If not equal
BMI, lBMI Branch If minus
BPl, lBPl Branch If plus
BCS, lBCS Branch If carry set
BCC, lBCC Branch If carry clear
BVS, lBVS Branch It overflow set
BVC, lBVC Branch If overflow clear
SIGNED BRANCHES
BGT, lBGT Branch If greater (signed)
BVS, lBVS Branch If Invalid 2's complement result
BGE, lBGE Branch If greater than or equal (signed)
BEC, lBEO Branch If equal
BNE, lBNE Branch If not equal
BlE, LBlE Branch If less than or equal (signed)
BVC, lBVC Branch If valid 2's complement result
BlT, lBlT Branch If less than (signed)
UNSIGNED BRANCHES
BHI, lBHI Branch If higher (unSigned)
BCC, lBCC Branch If higher or same (unSigned)
BHS, lBHS Branch If higher or same (unSigned)
BEC, lBEC Branch If equal
BNE, lBNE Branch If not equal
BlS, lBlS Branch If lower or same (unSigned)
BCS, lBCS Branch If lower (unsigned)
BlD, lBlD Branch If lower (unSigned)
OTHER BRANCHES
BSR, lBSR 1Branch to subroutine
BRA, lBRA I Branch always
BRN, lBRN I Branch never

TABLE 8 - MISCELLANEOUS INSTRUCTIONS

InstructIOn Description
ANDCC AND condition code register
CWAI AND condition code register, then walt for Interrupt
NOP No operation
DRCC OR condition code register
JMP Jump
JSR Jump to subroutine
RTI Return from Interrupt
RTS Return from subroutine
SWI, SWI2, SWI3 Software Interrupt (absolute mdlrect!
SYNC Synchronize with Interrupt line

4-322
MC6809E- MC68A09E- MC68B09E

TABLE 9 - HEXADECIMAL VALUES OF MACHINE CODES

OP Mnem Mode OP Mnem Mode OP Mnem Mode

00 NEG Direct 6 30 LEAX Indexed 4+ 2+ 60 NEG Indexed 6+ 2+
01
02
03
04
COM
LSR
31
32
33
34
LEAY
LEAS
LEAU
PSHS
t 4+
4+
Indexed 4+
Inherent 5+
2+
2+
2+
2
61
62
63
64
COM
LSR
6+
6+
2+
2+
05 35 PULS 5+ 2 65
06 ROR 36 PSHU 5+ 2 66 RO,A 6+ 2+
07 ASR 37 PULU 5+ 67 ASR 6+ 2+
08 ASL, LSL 3B 68 ASL, LSL 6+ 2+
09 ROL 39 RTS 69 ROL 6+ 2+
OA DEC 3A ABX 6A DEC 6+ 2+
OB 3B RTI 6/15 6B
OC INC 6 3C CWAI 2020 6C INC 6+ 2+
OD TST 6 3D MUL 11 6D TST 6+ 2+
OE JMP 3 3E 6E JMP 3+ 2+
OF CLR Direct 6 3F SWI Inherent 19 6F CLR Indexed 6+ 2+

•
10 Page 2 40 NEGA Inherent 70 NEG Extended
11 Page 3 41 71
12 NOP Inherent 42 72
13 SYNC Inherent 204 43 COMA 73 COM
14 44 LSRA 74 LSR
15 45 75
16 LBRA Relative 5 46 RORA 76 ROR
17 LBSR Relative 9 47 ASRA 77 ASR
18 48 ASLA, LSLA 78 ASL, LSL
19 DAA Inherent 49 ROLA 79 ROL
1A ORCC Immed 4A DECA 7A DEC
1B 4B 7B
1C ANDCC lmmed 4C INCA 7C INC 3
1D SEX Inherent 4D TSTA 7D TST 3
1E
1F

20
21
EXG
TFR

BRA
BRN
•
Inherent

Relative 3
3
4E
4F

50
51
CLRA

NEGB
Inherent

Inherent
7E
7F

80
81
JMP
CLR

SU8A
CMPA
Extended

lmmed
4 3
3

22 BHI 3 52 82 SBCA
23 BLS 3 53 COMB 83 SUBD
24 BHS, BCC 3 54 LSRB 84 ANDA
25 BLO, BCS 3 55 85 BITA
26 BNE 3 56 RORB 86 LDA
27 BEQ 3 57 ASRB 87
28 BVC 3 58 ASLB, LSLB 88 EORA
29 BVS 3 59 ROLB 89 ADCA
2A BPL 3 5A DECB 8A ORA
28 8MI 3 5B 8B ADDA
2C 8GE 5C INCB 8C CMPX Immed
2D BLT 5D TSTB 8D BSR Relative
2E BGT 5E 8E LOX Immed
2F BLE Relative 5F CLRB Inherent 8F

LEGEND
- Number of MPU cycles (less possible push pull or Indexed-mode cycles)
# Number of program bytes
• Denotes unused opcode

4·323
 MC6809E· MC68A09E. MC68B09E

TABLE 9 - HEXADECIMAL VALUES OF MACHINE CODES ICONTINUED)

OP Mnem Mode # OP Mnem Mode # OP Mnem Mode

90 SUBA Direct 4 2 CO SUBB Immed
CMPA 4 2

I
91 Cl CMPB 2 2 Page 2 and 3 Machine
92 SBCA 4 2 C2 SBCB 2 2 Codes
93 SUBD 6 2 C3 ADDD 4 3
94 ANDA 4 2 C4 AN DB 2 2 1021 LBRN Relative 5 4
95 BITA 4 2 C5 BITB Immed 2 2 1022 LBHI 5161 4
96 LDA 4 2 C6 LDB Immed 2 2 1023 LBLS 5161 4
97 STA 4 2 C7

I
1024 LBHS, LBCC 5161 4
98 EORA 4 2 C8 EORB 2 2 1025 LBCS, LBLO 5161 4
99 ADCA 4 2 C9 ADCB 2 2 1026 LBNE 5161 4
9A ORA 4 2 CA ORB 2 2 1027 LBEO 5161 4
9B ADDA 4 2 CB ADDB 2 2 1028 LBVC 5161 4
9C CMPX 6 2 CC LDD 3 3 1029 LBVS 5161 4
9D JSR 7 2 CD 102A LBPL 5161 4
9E LDX 5 2 CE LDU Immed 102B LBMI 5161 4
9F STX Direct 5 2 CF 102C LBGE 5161 4
4 102D LBLT 5161 4
AO SUBA Indexed 4+ 2+ DO SUBB Direct 2
102E LBGT bl61 4
Al CMPA 4+ 2+ Dl CMPB 4 2
4 2
102F LBLE Relative 5161 4
A2 SBCA 4+ 2+ D2 SBCB
103F SWI2 Inherent 20 2

•
A3 SUBD 6+ 2+ D3 ADDD 6
1083 CMPD Immed 5 4
A4 ANDA 4+ 2+ D4 AN DB 4
A5 BITA 4+ 2+ D5 BITB 4
lOBC CMPY I 5 4
lOBE LDY Immed 4 4
A6 LDA 4+ 2+ D6 LDB 4
1093 CMPD Direct 7 3
D7 STB 4

~
A7 STA 4+ 2+ l09C CMPY 7 3
A8 EORA 4+ 2+ D8 EORB 4
l09E LDY 6 3
A9 ADCA A+ 2+ D9 ADCB 4 2
l09F STY Direct 6 3
AA ORA 4+ 2+ DA ORB 4 2
4 2 10A3 CMPD Indexed 7+ 3+
DB ADDB

~
AB ADDA 4+ 2+ lOAC CMPY 7+ 3+
AC CMPX 2+ DC LDD 5 2
6+ 10AE LDY 6+ 3+
AD JSR 7+ 2+ DD STD 5 2
5 2 lOAF STY Indexed 6+ 3+
AE LOX 5+ 2+ DE LDU
10B3 CMPD Extended 8 4
OF STU Direct 5 2

~ ~
AF STX Indexed 5+ 2+ lOBC CMPY 4
EO SUBB Indexed 4+ 2+ lOBE LDY 4
BO SUBA Extended 5 3 El CMPB 4+ 2+ 10BF STY Extended 7 4
Bl CMPA 5 3 E2 SBCB 4+ 2+ 10CE LOS Immed 4 4
B2 SBCA 5 3 E3 ADDD 6+ 2+ lODE LOS Direct 6 3
B3 SUBD 7 3 E4 ANDB 4+ 2+ 10DF STS Direct 6 3
B4 ANDA 5 3 E5 BITB 4+ 2+ lOEE LOS Indexed 6+ 3+
B5 BITA 5 3 E6 LDB 4+ 2+ lOEF STS Indexed 6+ 3+
B6 LOA 5 3 E7 STB 4+ 2+ 10FE LOS Extended 7 4
B7 STA 5 3 E8 EORB 4+ 2+ 10FF STS Extended 7 4
B8 EORA 5 E9 ADCB 4+ 2+ 113F SWI3 Inherent 20 2
B9 ADCA 5 EA ORB 4+ 2+ 1183 CMPU Immed 5 4
BA ORA 5 3 EB ADDB 4+ 2+ 118C CMPS Immed 5 4
BB ADDA 5 3 EC LDD 5+ 2+ 1193 CMPU Direct 7 3
BC CMPX 7 3 ED STD 5+ 2+ 119C CMPS Direct 3
BD JSR 8 3 EE LOU 5+ 2+ llA3 CMPU Indexed 7+ 3+
BE LOX 6 3 EF STU Indexed 5+ 2+ 11AC CMPS Indexed 7+ 3+
BF STX Extended 6 3 llB3 CMPU Extended 8 4
FO SUBB Extended 5 3
llBC CMPS Extended 8 4
F1 CMPB 5 3
F2 SBCB 5 3
F3 ADDD 7 3
F4 ANDB 5 3
F5 BITB 5 3
F6 LDB 5 3
F7 STB 5 3
NOTE All unused opcodes are both undellned F8 EORB 5 3
and Illegal F9 ADCB 5 3
FA ORB 3
FB ADDB Extended 5 3
FC LDD Extended 6 3
FD
FE
FF
STD
LOU
STU
t 6
6
Extended 6
3

4·324
MC6809E-MC68A09E-MC68B09E

FIGURE 20 - PROGRAMMING AID

Addr.sslng Modes
Immediate Direct Indexed Extended Inherent 5 3 2 1 0
Instruction Forms Op - # Op # Op - # Op - # Op - I Description H N Z V C
ABX
ADC ADCA
ADCB
89
C9
2
2
2
2
99
09
4
4
2
2
A9
E9
4+
4+
2+
2+
B9
F9
5
5
3
3
3A 3 1 B+X-X (Unsigned)
A+M+C-A
B+M+C-B
·····
I
I
I
I
I
I
I
I
I
I
ADD ADDA 8B 2 2 9B 4 2 AB 4+ 2+ BB 5 3 A+M-A I I I I I
ADOB CB 2 2 DB 4 2 EB 4+ 2+ FB 5 3 B+M-B I I I I I

···
ADDD C3 4 3 03 6 2 E3 6+ 2+ F3 7 3 D+M M+l-D I I I I

··
AND ANDA 84 2 2 94 4 2 A4 4~ 2+ B4 5 3 AAM-A I I 0
ANDa C4 2 2 D4 4 2 E4 4+ 2+ F4 5 3 B A M-B I I 0
ANDCC lC 3 2 CC A IMM-CC 7

~lcHb7I lim IbOf-o

ASL ASLA 48 2 1 8 I I I I
ASLB 58 2 1 8 I I I I
ASL 08 6 2 66 6+ 2+ 78 7 3 M c 8 I I I I
ASR ASRA
ASRB
47
57
2
2
1
I
~!IIIIIII
Aq;-
HJc
8
8
I
I
I
I ·· I
I

·· · ··
ASR 07 6 2 67 6+ 2+ 77 7 3 7 60 8 I I I
BIT BITA 85 2 2 95 4 2 A5 4+ h B5 5 3 Bit Test A (M A A) I I 0
81T8 C5 2 2 D5 4 2 E5 4+ 2+ F5 5 3 Bit Test B (M A 81 I I 0
CLR CLRA
CLR8
4[
5F
2
2
I
I
O-A
O-B ··
0
0
I
I
0
0
0
0
(LR
·

•
OF 6 2 6F 6+ 2+ 7F 7 3 O-M 0 1 0 0
CMP CMPA 81 2 2 91 4 2 AI 4+ 2+ Bl 5 3 Compare M from A 8 I I I I
CMP8 Cl 2 2 01 4 2 El 4+ 2+ FI 5 3 Compare M from B 8 I I I I
CMPD 10
83
5 4 10
93
7 3 10
A3
7+ 3+ 10
B3
8 4 Compare M M + 1 from 0
·I I I I

CMPS II
8C
5 4 II
9C
7 3 II
AC
7+ 3+ II
BC
8 4 Compare M M + 1 from S
·I I I I

CMPU II
83
5 4 II
93
7 3 II
A3
7+ 3+ II
83
8 4 Compare M M + 1 from U
·I I I I

··
CMPX 8C 4 3 9C 6 2 AC 6+ 2+ 8C 7 3 Compare M M + 1 from X I I I I
CMPY 10 5 4 10 7 3 10 7+ 3+ 10 8 4 Compare M M + 1 from Y I I I I
8C 9C AC 8C

···
COM COMA 43 2 1 A-A I I 0 1
COM8 53 2 1 ii-8 I I 0 I
COM 031 6 2 63 6+ 2+ 73 7 3 M-M I I 0 I
CWAI 3C ~( 2 CC A IMM - CC Walt for Interrupt 7
DAA
DEC DECA
19
4A
2
2
1 DeCimal Adjust A
1 A I-A ·· · I
I
I
I
0
I
I

I
DEC8
DEC OA 6 2 6A 6+ 2+ 7A 7 3
5A 2 1 8-1-8
M-I-M ·· ··
I
I
I
I
I
I
EaR EORA
EOR8
88
C8
2
2
2
2
98
08
•
4
2
2
A8 4+
E8 4+
2+
2+
88
F8
5
5
3
3
A ..... M-A
B¥M-B ·· ··
I
I
I
I
0
0
EXG
INC
RI, R2
INCA
IE
4C
8
2
2 Rl-R2 2
I A+ I--A ·· · · · ··
I I I
INCB
INC OC 6 2 6C 6+ 2+ 7C 7 3
5C 2 I 8+ I-B
M+l-M
I
I·· ··
I
I
I
I

··· ·· ·· ·· ···
JMP OE 3 2 6E 3+ 2+ 7E 4 3 EA:;-PC
JSR 90 7 2 AD 7+ 2+ BD 8 3 Jump to Subroutine
LD LOA B6 2 2 96 4 2 A6 4+ 2+ B6 5 3 M-A I I 0

··· ···
LD8 C6 2 2 D6 4 2 E6 4+ 2+ F6 5 3 M-8 I I 0
LDD CC 3 3 DC 5 2 EC 5+ 2+ FC 6 3 M M+l-D I I 0
LOS 10 4 4 10 6 3 10 6+ 3+ 10 7 4 M M+l-S I I 0
CE DE EE FE
LOU
LOX
CE
BE
3
3
3
3
DE
9E
5
5
2
2
EE
AE
5+
5+
2+
2+
FE
8E
6
6
3
3
M M+l-U
M M+I-X
I
I ·· ··
I
I
0
0
LOY 10
BE
4 4 10
9E
6 3 10
AE
6+ 3+ 10
BE
7 4 MM+I-Y
· · I I 0

LEA LEAS
LEAU
32
33
4+ 2+ EA3_S
EA3_U ·· ·· ·· ·· ··
·· ·· ·· ··
4+ 2+
LEAX 30 4+ 2+ EA3_X I
LEAY 31 4+ 2+ EA3_y I
Legend M Complement of M Test and set If true, cleared otherwise
OP Operation Code I Hexadecimal! Transfer Into Not Affected
Number of MPU Cycles H Half-carry Ifrom bit 31 CC ConditIOn Code Register
Number of Program Bytes N Negative ISlgn bit I Concatenation
+ Anthmetlc Plus Z Zero result V Logical or
Anthmetlc MinUS V Overflow, 2'5 complement A Logical and
Multiply C Carry from ALU ¥ Logical Exclusive or

4-325
 MC6809E·MC68A09E·MC68B09E

FIGURE 20 - PROGRAMMING AID ICONTINUED)

Addressing Modes
,
- ,
Immediate Direct Indexed' Extended Inherent 5 3 2 0
Instruction Forms up up - # up - I Op - I Op I Description H N Z V C
LSL LSLA
LSLB
48
58
2
2
1
1 ~1[]+1 Iii I I I I ·· I
I
I
I
I
I
I
I

· ·
f-O
LSL DB 6 2 68 6+ 2+ 78 7 3 c b7 bO I I I I

~l -j I I I I I I I HJ ··
lSR LSRA 44 2 1 0 I I

·· · ···
LSRB 54 2 1 0 0 I I
LSR 04 6 2 54 6+ 2+ 74 7 3 b7 bO C 0 I I
MUL 3D 11 1 A x B- 0 (Unsigned) I 9
NEG NEGA 40 2 1 A+ l-A 8 I I I I
NEGB 50 2 1 B+ 1-8 8 I I I I
NEG 00 6 2 60 6+ 2+ 70 7 3 M+l-M 8 I I I I
NOP
OR ORA 8A 2 2 9A 4 2 AA 4+ 2+ BA 5 3
12 2 1 No Operation
A V M-A ·· · · · ·· I I 0
ORB
ORCC
CA
lA
2
3
2
2
OA 4 2 EA 4+ 2+ FA 5 3 B V M-B
CC V IMM-CC · ·I I 0
7
PSH PSHS
PSHU
34 5+ 4
36 5+ 4
2
2
Push Registers on S Slack
Push ReQISlers on U Stack ·· ·· ·· ·· ··
PUL PULS
PULU
35 5+ 4
37 5+ 4
2
2
Pull Registers from S Stack
Pull Registers from U Stack ·· ·· ·· ·· ··
~I L[H I I I I I [ I f:l ··
ROL ROLA 49 2 1 I I I I

•
ROLB E,9 2 1 I I I I

ROR
ROL
RORA
09 6 2 69 6+ 2+ 79 7 3
46 2 1
C b7 I

~14}+j I I I I III P ··
· ·
bO I
I
I
I
I I
I

· ··
RORB 56 2 1 I r I
ROR 06 6 2 66 6+ 2+ 76 7 3 c b7 bO I I I
RTI 3B 6/15 1 Return From Interrupt 7
RTS
SBC SBCA 82 2 2 92 4 2 A2 4+ 2+ B2 5 3
39 5 1 Return from SubroutIne
A~M~C-A
· · ···
8 II I I I
SBCB C2 2 2 02 4 2 E2 4+ 2+ F2 5 3 B~M~C-B 8 I I , I I
SEX
ST STA 97 4 2 A7 4+ 2+ B7 5 3
10 2 1 Sign Extend B Into A
A-M
·· ·· I
I
I
I
!G
0
STB
STD
07
OD
4
5
2
2
E7 4+
ED 5+
2+
2+
F7
FO
5
6
3
3
B-M
O-M M+ 1 ·· , ·· I
I
I
I
0
0
STS 10
DF
6 3 10 6+
EF
3+ 10
FF
7 4 S-M M+l
· I: · 0

STU
STX
DF
9F
5
5
2
2
EF 5+
AF 5+
2+
2+
FF
BF
6
6
3
3
U-M M+l
X-M M+ 1 ·· ··
I
I I
0
0

SUB
STY

SUBA SO 2 2
10
9F
90
6

4
3

2
10
AF 6+
AO 4+
3+
2+
10
BF
BO
7

5
4

3
Y-M M+l

A~M-A
· · 8
I

I
I

I II
0

·· · i: ·
SUBB CO 2 2 DO 4 2 EO 4+ 2+ FO 5 3 B~M-B 8 I I I
SUBD 83 4 3 93 6 2 A3 6+ 2+ B3 7 3 D~M M+l-D I I I
SWI SWI 3F 19 1 Software Interrupt 1

·····
• I.
,
SWI6 10 20 2 Software Interrupt 2
3F i
SWI6 11
3F
20 1 Software Interrupt 3
·· · •
I
10

SYNC
TFR R', R2
13
lF
;,,4
6
1 Synchronize to Interrupt
2 Rl- R2L ·· ·· ·· ·· ··
TST TSTA
TST8
40
5D
2
2
1 Test A
1 Test 8 ·· ·· I
I
I
I
0
0

Notes
TST 00 6 2 60 6+ 2+ 70 7 3 Test M
· · I I 0

1. ThiS column gives a base cycle and byte count To obtain total count, add the values obtained from the INDEXED ADDRESSING MODE table,
Table 2
2, R1 and R2 may be any pair of 8 bit or any pair of 16 bit registers
The 8 bit registers are A, B, CC, DP
The 16 bit registers are X, Y, U, S, D, PC
3 EA IS the effective address
4. The PSH and PUL instructions reqUire 5 cycles plus 1 cycle for each byte pushed or pulled
5, 5(6) means 5 cycles If branch not taken, 6 cycles If taken (Branch instructIOns)
6 SWI sets I and F bits SWI2 and SWI3 do not affect I and F
7 Conditions Codes set as a direct result of the Instruction
8 Vaue of half-carry flag IS undefined
9, Special Case - Carry set If b7 IS SET

4-326
MC6809E-MC68A09E-MC68B09E

FIGURE 20 - PROGRAMMING AID (CONTINUEDI

Branch Instructions

Addressing Addressing
Mode Mode
to!e~·~1T
5 3 2 1 0 I 5 3 2 1 0
Instruction Forms Description H N Z V C Instruction Forms OP - 5 I Description H N Z V C
BCC BCC
I LBCe
24
10
3
5(61
2 Branch C-O
4 long Branch
· · · ·· ··
BLS BLS 23 3 2 Branch Lower
or Same ·····
24 C~O LBLS 10 5161 4 Long Branch Lower
·····
· · · ·· ··
25 23 or Same

·· ·· ·· · ··
BCS BCS 3 2 Branch C = 1
LBCS 10 5(61 4 Long Branch BLT BlT 2D 3 ·2~h<Zero
25 C=:1 LBLT 10 5161 4 Long Branch < Zero

· · ·· ·· ··
BEQ BEQ 27 3 2 BranCh Z= 1 2D

·· ·· ·· · ··
LBEQ 10 5(61 4 Long Branch BMI BMI 2B 3 2 Branch Mmus
27 Z~O LBMI 10 5(61 4 Long Branch Minus

·· · ·· ··
BGE BGE 2C 3 2 Branch~Zero 2B
LBGE 10 S(S)
2C
4 long Branch~Zero BNE BNE
LBNE
26
10
3
5(6)
2 Branch 2=0
4 Long Branch ·· ·· ·· · ··
BGT BGT
LBGT
2E

2E
3
10 5(61
2 Branch> Zero
4 long Branch> Zero ·· · ·· ·· ·· BPL BPL
LBPL
26
2A
10
3
5161
UO
2 Branch Plus
4 Long Branch Plus ·· ·.!.· ·· ··
---a,:;;- BHI 22 3 2 Branch Higher
·· ·· ·· ·· 2A

•
LBHI 10 5(6) 4 Long Branch Higher BRA BRA 20 3 2 Branch Always
··· ·
·· ··· ··· ··· ···
22 LBRA 16 5 3 Long Branch AlWaYS
BHS BHS 24 3 2 Branch Higher
or Same · ··· BRN BRN
LBRN
21
10
3
5
2 Branch Never
4 Long Branch Never
LBHS 10
24
5(61 4 Long Branch Higher
or Same · ··· BSR BSR
21
BO 7 2 Branch to Subroutine
· ·· ·· · ··
BLE BLE
LBLE
2F 3
10 5151
2 Branch!!> Zero
4 Long Branch:S; Zero ·· · · ·· ·· LBSR 17 9 3 Long Branch to
Subroutine
2F
· ·· ·· ·· ··
·· · ·· ·· ··
BVe BVe 2B 3 2 Branch V - 0
~- BLO 25 3 2 Bra~ch lower LBVe 10 5(6) 4 Long Branch
LBLO 10 5161
25
4 Long Branch lower
BVS BVS
2B
29 3
V=O
2 Branch V-1 .,. · · ·
i ···
LBVS 10 5(61 4 Long Branch • I•
29 V=l

SIMPLE BRANCHES
OP SIMPLE CONDITIONAL BRANCHES (Notes 1-4)
BRA 20 3 Test True OP False OP
lBRA 16 5 N=l BMI 2B BPl 2A
BRN 21 2 Z=l BEG 27 BNE 26
lBRN 1021 4 V=l BVS 29 BVC 28
BSR 8D 2 C=l BCS 25 BCC 24
lBSR 17·

SIGNED CONDITIONAL BRANCHES (Notes 1-4) UNSIGNED CONDITIONAL BRANCHES (Notes 1-4)
Test True OP False OP Test True OP False OP
r>f'1 BGT 2E BlE 2F r>m BHI 22 BlS 23
r~m BGE 2C BlT 2D r~m BHS 24 BlO 25
r=m BEG 27 BNE 26 f=m BEG 27 BNE 26
rSm BlE 2F BGT 2E rsm BlS 23 BHI 22
r<m BlT 2D BGE 2C r<m BlO 25 BHS 24

Notes
All conditional branches have both short and long vanatlons
All short branches are 2 bytes and require 3 cycles
All conditional long branches are tormed by prefixing the short branch opcode with $10 and uSing a 16-blt destination offset
4 All conditional long branches require 4 bytes and 6 cycles If the branch IS taken or 5 cycles If the branch IS not taken
5 5(6) means 5 cycles If branch not taken, 6 cycles If taken

4-327
 MC6809Ee MC68A09Ee MC68B09E

INDEXED ADDRESSING MODES

NON INDIRECT INDIRECT
Assembler Post-Byte + + Assembler Post-Byte -+ +
TYPE FORMS Form OP Code II Form OP Code II
CONSTANT OFFSET FROM R NO OFFSET ,R 1 RR00100 0 0 I, RI 11RR10l00 3 0
5 BIT OFFSET n, R ORRnnnnn 1 0 defaults to 8-blt
8 BIT OFFSET n, R lRR01000 1 1 In, RI 1 RRl 1000 4 1
16 BIT OFFSET n, R lRR01.001 4 2 In, RI lRRll00l 7 2
ACCUMULATOR OFFSET FROM R A-REGISTER OFFSET A,R 1 RROOl 10 1 0 lA, RI 1 RR101 10 4 0
B-REGISTER OFFSET B,R 1 RR0010l 1 0 IB, RI lRR10l0l 4 0
D-REGISTER OFFSET D,R lRR010ll 4 0 ID, RI lRRll0ll 7 0
AUTO INCREMENT IDECREMENT R INCREMENT BY 1 ,R+ lRROOOOO 2 0 not allowed
INCREMENT BY 2 ,R++ lRROOOOl 3 0 [, R+ + I 11RR1000l 6 0
DECREMENT BY 1 ,-R 1 RR00010 2 0 not allowed
DECREMENT BY 2 ,--R lRROOOll 3 0 [, - -·RI lRR100ll 6 0
CONSTANT OFFSET FROM PC 8 BIT OFFSET n, PCR 1 XXOl 100 1 1 In, PCRI lXXlll00 4 1

16 BIT OFFSET n, PCR lXXOll0l 5 2 In, PCRI lXXlll0l 8 2

EXTENDED INDIRECT 16 BIT ADDRESS - - - - Inl 10011111 5 2
R = X, y, U, or S RR: OO=X 10=U
X - DON'T CARE 01 =Y 11 =S

INDEXED ADDRESSING POSTBYTE

REGISTER BIT ASSIGNMENTS

•
INDEXED
POST·BYTE REGISTER BIT
ADDRESSING
7 6 5 4 3 2 1 0
MODE
0 R R , , , , , EA - ,R + 5 Bit Offset
1 R R 0 0 0 0 0 ,R +
1 R R I 0 0 0 1 ,R + +
1 R R 0 0 0 1 0 R
1 R R I 0 0 1 1 - - R
1 R R I 0 1 0 0 EA _ ,R + 0 Offset
L~--=-:=:PC::=--=J ,"OC,," cou""
1 R R I 0 1 0 1 EA _ ,R + AceS Offset
1 R R I 0 1 1 0 EA - ,R + ACCA Offset i-A--T B_J
1 R R I 1 0 0 0 EA _ ,R + 8 Bit Offset '-.. ,/
1 R R EA ,R + 16 Bit Offset
I 1 0 0 1
o
1 R R EA _ ,R + 0 Offset
1 , ,
I
I
1
1
0
1
1
0
1
0 EA ,PC + 8 Bit Ollse! L_ DP- I DIRECT PAGE REGISTER

1 , , I 1 1 0 1 EA ,PC + 16 Bit Offset CC - CONDITION CODE

1 R R 1 1 1 1 1 EA _ LAddress! CARRY BORROW

I ' L:~ ~:!~FLOW

~u~ Ll - -
I L - - - Addressing Mode Field l NEGATIVE:
_ _ _ IRO INTERRUPT MASK

I L.- - - - - - I n d l r e c t Field
(Sign bit when b7 = 01
_ _ _ _ _ HALF CARRY

l=__ ~-== ;~~~RI~~~:~~~TN ~~~~K

I Register Field RR
00 = X
01 = y
x = Don', Care 10 = U
11 = S

PUSHI PULL POST BYTE 6809 SlACKING ORDER

PULL ORDER

A
CCR Jc
A
' -_ _ _ B
' -_ _ _ _ DPR DP 6809 VECTORS
X H, FFFE Restart
X Lo FFFC NMI
' -_ _ _ _ _ _ _ _ S/U YH, FFFA SWI
' -_ _ _ _ _ _ _ _ _ PC
YLo FFF8 IRO
U/S HI FFF6 FIRQ
TRANSFER/EXCHANGE POST BYTE U/S Lo FFF4 SWI2
PC HI FFF2 SWI3
[1OU:AC~ I D~STI~AT!ON I PC Lo
!
FFFO Reserved

PUSH ORDER
REGISTER FIELD
0000 o (A B) 1000 A INCREASING
0001 X 1001 B
MEMORY
0010 Y 1010 CCR
0011
0100
U
S
1011 DPR +
0101 PC

4-328
MC6809E-MC68A09E-MC68B09E

ORDERING INFORMATION

MC68A09ECP
Motorola In ••gra.ed Corcu,.
MIIBOO Fam,ly
Blank.- 1 0 MHz
T I TTl
-

A-15MHz
B-2,O MHZ
Device Designa',on
In MIIBOO FamIly
Tempera.ure Range _ _ _ _ _ _ _ _ _...J
Blank - 0°- + 70°C
C- - 40°- + B5°C
Package
p- Plastic
S·Cerdlp
l-Ceramlc

BmER PROGRAM

Better program processing IS available on all Wpes listed Add

suffll( letters to part numbf"r

Levell add "5" Level 2 add "0"

HI Temp testIng at T A max

Level 2 "0".168 Hour Burn"n at 125'C
Level 3 add 'OS'
Levell "5" = 10 Temp Cvcles - 1- 25 to lSO'Cl,

Level 3 "OS". Combination of Levell end 2

•
Speed Device Temperature Range

1.0 MHz M C6809EP, L, S 0.070'C

t 5 MHz MC68A09EP,L,S 0.0 +70'C
20 MHz MC68B09EP,L,S 0.0 + 70'C

4-329
 MeMllO
® MOTOROLA
(1=0- z)
MeMMAIO
(l.s-lIIiz)
MeMMBIO
(2.0-lIIIz)
128x8-BIT STATIC RANDOM ACCESS MEMORY
The MCM6810 IS a byte-organized memory designed for use In bus- MOS
organized systems. It IS fabricated with N-channel slhcon-gate (N-CHANNEL, SILICON-GATE)
technology. For ease of use, the device operates from a single power
supply, has compatlblhty with TTL and DTL, and needs no clocks or
refreshing because of static operation. 128x8-BIT STATIC
The memory IS compatible with the M6800 Microcomputer Family, RANDOM ACCESS
providing random storage In byte Increments. Memory expansion IS MEMORY
provided through multiple Chip Select Inputs
• Organized as 128 Bytes of 8 Bits
• Static Operation

fIII#/IJ:~
• Bidirectional Three-State Data Input/Output
• SIX Chip Select Inputs (Four ActIVe Low, Two Active Hlghl
• Single 5-Volt Power Supply 24 ' P SUFFIX
• TTL Compatible PLASTIC PACKAGE
1 CASE 709
• MaXimum Access Tlme=450 ns - MCM6810
360 ns - MCM68A 10

•
250 ns - MCM68Bl0

MCM6Bl0 RANDOM ACCESS MEMORY

BLOCK DIAGRAM
Data
~, ' LSUFFIX
CERAMIC PACKAGE
CASE 716

Bus

~''"­
~~W::RDIP~ACKAGE CASE 623

Memorv Address
and Control
PIN ASSIGNMENT

M6800 MICROCOMPUTER FAMILY Gndl~ Vee

BLOCK DIAGRAM
DOl 2 23 AO
0,. 3 22 Al
O~ 4 21 ~
031 5 2OpjA3
D4f: 6 191M
05( 7 18 ~A5
osl 8 17 ~AS
0719 16 IR/W
eso l110 15 ~ CS5
CSl1111 14 ICS4
CS2'112 13 ~CS3
Address Oata
BUI Bus
'------

4-330
MCM6810-MCM68A10-MCM68B10

MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage VCC -0.3 to + 70 V This device contains Circuitry to protect the In~
Input Voltage Y,n -0.3 to + 70 V puts against damage due to high static voltages
Operating Temperature Range TL to TH or electric fields, however, It IS advised that nor-
MCM6810, MCM68A10, MCM68B10 TA o to + 70 °c mal precautions be taken to aVOId application of
MCM6810C, MCM68A10C -40 to +85 any voltage higher than maximum rated voltages
Storage Temperature Range TSjg -85 to + 150 °c to this high Impedance Circuit Reliability of
operation IS enhanced If unused In"ut5 are tied to
an appropriate logiC voltage Ie g , either VSS or
THERMAL CHARACTERISTICS VCCI
Characteristics Symbol Value Unit
Thermal Resistance
Ceramic 60
PlastiC 8JA 120 °C/W
Cerdlp 65

•
POWER CONSIDERATIONS

The average chip-Junction temperature, T J, In °C can be obtained from·

TJ=TA+(PD 9JAI (1)
Where:
TA-Ambient Temperature, °C
9JA-Package Thermal ReSistance, Junctlon-to-Amblent, °C/W
PD-PINT+ PPORT
PINT-ICCxVCC, Watts - Chip Internal Power
PPORT - Port Power Dissipation, Watts - User Determined
For most applications PPORT.PINT and can be neglected PPORT may become Significant If the deVice IS configured to
drive Darlington bases or sink LED loads
An approximate relationship between PD and T J (if PPORT IS neglected) IS:
PD=K+iTJ+273°C) (2)
SolVing equations 1 and 2 for K gives.
K= PD-(TA + 273°C) +9JA-PD2 (3)
Where K IS a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at eqUilibrium)
for a known T A. USing this value of K the values of PD and T J can be obtained by solVing equations (1) and (2) Iteratively for any
value of TA.

DC ELECTRICAL CHARACTERISTICS IVcC=5 0 Vdc ±5%, VSS=O, TA=TL to TH unless otherwise notedl
Characteristic Symbol Min Max Unit
Input High Voltage VIH VSS+20 VCC V
Input Low Voltage VIL VSS-O 3 VSS+O 8 V
Input Current IAn, R/W, CSnl IV,n=O to 5.25 VI lin - 25 ,.A
Output High Voltage IIOH = - 205I'Ai VOH 24 - V
Output Low Voltage IIOL - 1 6 mAl Vo 04 V
Output Leakage Current (Three-Statel ICS=0.8 V or CS=2 0 V, Vou t=O.4 V to 2 4 VI ITSI - 10 ,.A
Supply Current 1.0MHz
ICC
- 80
rnA
IVrr= 525 V, All Other Pins Groundedl 15,2.0 MHz - 100
Input Capacitance IAn, R/Vii, CS n' CSnl IVIn=O, TA=25°C, 1=1 0 MHz) Cin - 75 pF
Output Capacitance IDnl IVout=O, TA=25°C, 1= 10 MHz, CSO=OI Cout - 125 pF

4-331
 MCM681 ()eMCM68A 10-MCM68B10

BLOCK DIAGRAM

2 DO
AO 23 3 01
A1 22 4 02
A2 21 5 03
A3 20 6 DO
A4 19 7 05
A5 18 8 06
A6 17 9 07
B5 15
B4 1.
CS3 13
B2 12
CS1 11
C$O 10

AC OPERATING CONDITIONS AND CHARACTERISTICS

READ CYCLE (VCC = 5 0 V ± 5%, VSS = 0, T A = TL to TH unless otherWISe noted)
MCM6810 MCM68Al0 MCM68Bl0
Characteristic Symbol Min Max Min Max Min Max Unit

•
Read Cycle TIme teyelR) 450 - 360 - 250 - ns
Access Time tace 450 360 - 250 ns
Address Setup Time tAS 20 - 20 - 20 - ns
Address Hold Time tAH 0 - 0 - 0 - ns
Data Delay TIme (Read) 'DDR - 230 - 220 180 ns
Read to Select Delay TIme 'RCS 0 - 0 - 0 - ns
Data Hold from Address 'DHA 10 - 10 - 10 - ns
Output Hold TIme 'H 10 - 10 - 10 - ns
Data Hold from Read 'DHR 10 80 10 60 10 60 ns
Read Hold from ChIp Select 'RH 0 - 0 - 0 - ns

READ CYCLE TIMING

~1----------------teycIRI-------------a~

~I--------- tace --------i~

Address

CS

~-------'OOR-----~~

R/W

Data Out -------------C

NOTES
1 Voltage levels shown are VLSO 4 V, VH~2 4 V, unless otherwIse specIfied
2 Measurement POintS shown are 0 8 V and 2 0 V. unless otherwIse specified ~ "" Don't Car.
3 CS and CS have same tIming

4·332
MCM6810-MCM68A10-MCM68B10

WRITE CYCLE IVCC = 5 0 V ± 5%, VSS = 0, TA = TL to TH unless otherwISe noted I

MCM6810 MCM68Al0 MCM68Bl0
CharacteristIC Symbol Mon Max Mon Ma. Mon Ma. Unit
Write Cycle Time tcyclWI 450 - 360 - 250 - n,
Address Setup Time tAS 20 - 20 - 20 - n,
Address Hold Time tAH 0 - 0 - 0 - n,
Chip Select Pulse Width tes 300 250 210 ns
Write to Chip Select Delay Time twcs 0 - 0 - 0 - ns
Data Setup Time (Write) tDSW 190 - 80 - 60 - ns
Input Hold Time tH 10 - 10 - 10 - ns
Write Hold Time from Chip Select tWH 0 0 0 n,

WRITE CYCLE TIMING

'~".=1
CS--------------~LL~~~
'AS
~ ''''''H
_____ 'cs ____...a*I__ .,j ~=============== •
~------------~Er77~~

R/Vii

rl-.·o-----'DSW
.. ----;~ r-
Dataln W&//~k----D.,-aln-Sta-ble-~~mmA

NOTES
1 Voltage levels shown are VLSO 4 V, VH202 4 V, unless otherwise specified
2 Measurement pOints shown are 0 8 V and 2 0 V, unless otherwise specified W ffi ~ Don', Ca..
3 es and CS have same timing

4·333
 MCM6810-MCM68A10-MCM68B10

FIGURE 1 - AC TEST LOAD

5.0 V

MM06150 RL=2.5 kO
or EqUiv.
Test POint
,
o-..,..-1r--i'....- .

11 7 kO ~ MM07000
, or EqUiv

·Includes Jig Capacitance

ORDERING INFORMATION

MCM68Al0CP

• Motorola Integrated CirCUit

M6800 Family
Blanks= 1 0 MHz
A=15 MHz
B=20MHz
Device Designation
In M6800 Family
-

Temperature Range _ _ _ _ _ _ _ _ _....1

Blank = 0'_ + 70'C
C= _40'_ +85'C
Package
=rTfJ

P = Plastic
S= Cerdlp
L=Ceramlc

BETIER PROGRAM

Better program processing IS available on aU types listed Add

suffix letters to part number

Levell add "s" Level 2 add "0" Level 3 add "OS"

Levell "s" = 10 TempCycles - (- 25 to 150'CI.

HI Temp testing at T A max
Level 2 "D" = 168 Hour Burn-In at 125'C
Level 3 "DS" = Combination of Levelland 2

Speed Device Temperatura Range

1.0 MHz
MCM6810P ,L,S o to + 70'C
MCM6810CP ,CL,CS -40 to +85'C
1.5 MHz
MCM68Al0P,L,S o to + 70'C
MCM68A 10CP ,CL,CS -40 to +85'C
2.0 MHz MCM68Bl0P,L,S o to + 70'C

4·334
 MC6821
(1.0 MHz)
@ MOTOROLA MCGAA21
(1.1 11Hz)
MC68B21
(2.0 MHz)

PERIPHERAL INTERFACE ADAPTER (PIA)

The MC6821 Peripheral Interface Adapter provides the universal MOS

means of Interfacing peripheral equipment to the M6800 family of (N-CHANNEL, SILICON-GATE,
microprocessors This device IS capable of Interfacing the M PU to DEPLETION LOAD)
peripherals through two 8-blt iJldlrectlonal peripheral data buses and
four control lines No external logic IS required for interfaCing to most PERIPHERAL INTERFACE
peripheral devices
ADAPTER
The functional configuration of the PIA IS programmed by the MPU
dUring system Initialization Each of the peripheral data lines can be pro-
grammed to act as an Input or output, and each of the four con-
trol/Interrupt lines may be programmed for one of several control
modes ThiS allows a high degree of fleXibility In the overall operation of
the Interface L SUFFIX
• 8-Blt Bidirectional Data Bus for Communication With the CERAMIC PACKAGE
CASE 715
MPU
• Two Bidirectional B-Blt Buses for Interface to Peripherals
• Two Programmable Control Registers
• Two Programmable Data Direction Registers , I I I S SUFFIX
L CEROIP PACKAGE
• Four Individually-Controlled Interrupt Input Lines, Two

I
CASE 734
Usable as Peripheral Control Outputs

~''"''''
• Handshake Control LogiC for Input and Output Peripheral
Operation
• High-Impedance Three-State and Direct TranSistor Drive
Peripheral Lines
1.' : ' ' PLAS~~~~~~IKAGE
• Program Controlled Interrupt and Interrupt Disable Capability
• CMOS Drive Capability on Side A Peripheral lines
• Two TTL Drive Capability en All A and B Side Buffers
• TTL-Compatible
PIN ASSIGNMENT
• Static Operation
CAl
CA2
MAXIMUM RATINGS IROA
IROB
Characteristics Symbol Value Unit
RSa
Supply Vollage vcc -0310 + 70 V
Inpul Voltage V ,n -0310 +70 V RSl
Operatmg Temperature Range h 10TH RESET
MC6821 , MC68A21, MC68821 TA 0 1070 cc
MC6821C, MC68A21C, MC68821C -40 10 +85 DO
Storage Temperature Range Tslg -5510+150 cc 01
PBO 02
THERMAL CHARACTERISTICS PBl 03
Characteristic Symbol Value Unit
PB2
Thermal ReSistance
Ceramic 50 05
8JA cC/W
PlastiC 100 06
Cerdlp 60
07
PB6
ThiS deVice contains circuitry to protect the Inputs agamst damage due to high PB7 CSl
static voltages or electriC fields, however, It IS adVIsed that normal precautions CBl
be taken to aVOid application of any voltage higher than maximum-rated
voltages to thiS high-Impedance Circuit Reliability of operation IS enhanced If C82 esa
unused Inputs are tied to an appropriate logiC voltage (I e ,either VSS or Vecl RiiN

4-335
 MC6821-MC68A21-MC68B21

POWER CONSIDERATIONS

The average chip-JunctIOn temperature, T J, In °c can be obtained from

T J ~ T A + IPDoOJA) il)
Where
TA",Amblent Temperature, °c
OJA'" Package Thermal Resistance, JunctlOn-to-Amblent, °C/W
PD'" PINT+ PPORT
PINT'" ICC x Vce Watts - Chip Internal Power
PPORT'" Port Power DIssipation, Walts - User Determined
:'or most applications PPORT<il PINT and can be neglected PPORT may become significant If the device IS configured to
drive Darlington bases or sink LED loads
An approximate relatIOnship between PD and T J Ilf PPORT IS neglected) IS
PD~K-ITJ+273°C) 12)
Solving equatIOns 1 and 2 for K gives
K ~ PDolT A + 273°C) + OJA"PD 2 13)
Where K IS a constant pertaining to the particular part K can be determined from equation 3 by measunng PD lat equillbnum)

•
for a known T A USing this value of K the values of PD and TJ can be obtained by solving equatIOns 111 and 12) Iteratively for any
value of T A

DC ELECTRICAL CHARACTERISTICS IVCC~5 0 Vdc ±5%, vSS~O, TA~TL to TH unless otherwise notedl
I Characteristic I Symbol I Min I Typ Max Unit
BUS CONTROL INPUTS IR/W, Enable, RESET, RSO, RS1, CSO, C51, C521
Input High Voltage VIH VSS + 20 - VCC V
Input Low Voltage VIL VSS - 03 - VSS + 08 V
Input Leakage Current (VIn=O to 5 25 V) Irn - 10 25 ~A
Capacitance IV,n~O, TA~25°C, f~1 0 MHzl C,n - - 75 pF
INTERRUPT OUTPUTS IIROA, IRQBI
Output Low Voltage IILoad ~ 32 mAl
Three-State Output Leakage Current
Capacitance IVrn~O, TA~25°C, f~1 0 MHzl
DATA BU5 100-07)
Input High Voltage VIH VSS + 20 - VCC V
Input Low Voltage VIL VSS-03 - VSS + 08 V
Three-State Input Leakage Current IV rn ~ 04 to 2 4 VI liZ - 20 10 ~A
Output High Voltage IILoad ~ - 205 ~AI VOH VSS + 24 - - V
Output Low Voltage IILoad -1 6 mAl VOL - - VSS+O 4 V
Capacitance IV,n - 0, TA ~ 25°C, f ~ 1 0 MHzl Crn - - 125 pF
PERIPHERAL BUS IPAG-PA7 PBO-PB7 CA 1 CA2 CB1 CB2)
Input Leakage Current R/W, RESET, RSO, RSt, cso, CS1, CS2, CAl, -
lin 1O 25 ~A
IV,n~Ot05 25VI r:S 1, Enable
Three-State Input Leakage Current {Vln = 0 4 to 2 4 V) PSO,PBl, CS2 I!Z - 20 10 ~A
Input High Current IVIH - 24 VI PAO-PAl, CA2 IIH -200 -400 - ~A
Darlington Dnve Current IVO~ 15 VI PRO-PSl, CB2 IOH -1O - -10 mA
Input Low Current IVIL ~ 04 VI PAO-PAl, CA2 IlL - -13 -24 mA
Output High Voltage
IILoad~ - 200 ~AI PAO-PAl, PSO-PBl, CA2, CB2 VOH VSS + 24 - - V
IILoad~ -lO~AI PAO-PA7, CA2 VCC-10 - -
Output Low Voltage IILoad - 32 mAl VOL VSS + 04 V
Capacitance IVrn~O, TA~25°C, f~1 ° MHzl C,n - - 10 pF
POWER REQUIREMENTS
Internal Power DISSipation (Measured at T A = TU 550 mW

4·336
MC6821- MC68A21-MC68821

BUS TIMING CHARACTERISTICS (See Notes 1 and 21

ldent. MC6B21 MC68A21 MC68B21
Characteristic Symbol Unit
Number Min Max Min Max Min I Max
1 Cycle Time teye 10 10 067 10 05 10 liS
2 Pulse Width, E Low PWEL 430 - 280 - 210 - ns
3 Pulse Width, E High PWEH 450 - 280 - 220 - ns
4 Clock Rise and Fall Time tr,tf 25 25 20 ns
9 Address Hold Time tAH 10 - 10 - 10 - ns
13 Address Setup Time Before E tAS 80 - 60 - 40 - ns
14 Chip Select Setup Time Before E tcs 80 - 60 - 40 - ns
15 Chip Select Hold Time tCH 10 - 10 - 10 - ns
18 Read Data Hold Time tDHR 20 100 20 100 20 100 ns
21 Wllte Data Hold Time tDHW 10 - 10 - 10 - ms
30 Output Data.Delay Time 290 180 150 ns

•
tDDR
31 Input Data Setup Time tDSW 165 - 80 - 60 ns

FIGURE 1 - BUS TIMING

1-~----------------~-r~---------(3~--------~

R/W, Address -.....!.+.6,..,...Tr-.,.......,....,r----.........,.......±--+1f------------------1+-~rn7

(NOn-MUxedl ___-t~~~~~~~~---~~~~~~;t1_~~---------------------==!j~~~~

Read Data ----+--.L"-_________M_p_U__R_ea_d__D_a_ta_N_o_n_-_M_u_x_ed_____------(t-----(J

Non-Muxed " ..,..--~=---:;:::---H-~r-

Wllte Data ---'---..L MPU Wllte Data Non-Muxed

Non-Muxed ,------------~~~~~~~~~~-----------,;:::~~______~=-+_-~

Notes
1 Voltage levels shown are VL:SO 4 V, VH,,2 4 V, unless otherwise specified
2 Measurement POints shown are 0 8 V and 2 0 V, unless otherwise specified

4-337
 MC6821-MC68A21-MC68B21

PERIPHERAL TIMING CHARACTERISTICS (VCC=5 0 V ±5% vss =0 v, TA = TL to TH unless otherwise specified I

MC6821 MC68A21 MC68B21 Reference
Characteristic Symbol Unit Fig. No.
Min Max Min Max Min Max
Data Setup Time tPDS 200 - 135 - 100 - ns 6
Data Hold Time tpDH 0 - 0 - 0 - ns 6
Delay Time, Enable Negative Transition to CA2 NegatIVe TransllIOn tCA2 - 10 - 0670 - 0500 p.s 3,7,8
Delay Time, Enable Negative Transition to CA2 Positive Transition TRSI - 10 - 0670 - 0500 p.s 3,7
Rise and Fall Times for CA 1 and CA2 Input Signals tr,tf - 10 - 10 - 10 p.s 8
Delay Time from CAl Active Transition to CA2 Positive Transition tRS2 - 20 - 135 - 10 p'S 3,8
Delay Time, Enable Negative Transition to Data Valid tPDW - 10 - 0670 .- 05 p.S 3,9,10
Delay Time, Enable Negative TranSition to CMOS Data Valid
tCMOS - 20 - 135 - 10 P.S 4,9
PAD-PA7, CA2
Delay Time, Enable PositIve Transition to C82 Negative TransItion tCB2 - 10 - 0.670 - 0.5 p.s 3,11,12
Delay TIme, Data Valid to CB2 Negative Transition tDC 20 - 20 - 20 - ns 3, 10
Delay Time, Enable Positive Transition to CB2 Positive Transition tASl - 10 - 0.670 - 0.5 p.s 3, 11
Control Output Pulse Width, CA2/CB2 PWCT 500 - 375 - 250 - ns 3, 11
A,se and Fall Time for CBl and CB2 Input Signals tr,tf - 10 - 10 - 10 p. 12

•
Delay Time, CB1 Active Transition to CB2 Positive Transition tAS2 - 2.0 - 135 - 10 p.s 3,12
Interrupt Aelease Time, IAQA and iliOll tlA - 160 - 110 - 085 p.s 5,14
Interrupt Response Time tAS3 - 10 - 10 - 10 p.s 5,13
Interrupt Input Pulse Time PWI 500 - 500 - 500 - ns 13
RESET Low Time' tAL 10 - 066 - 05 - p'S 15

'The AESET hne must be high a minimum of 1 0 p'S before addressing the PIA

FIGURE 3 - TIL EQUIVALENT

FIGURE 2 - BUS TIMING TEST LOADS
TEST LOAD
1D0-D7) 5.{) V (PAO-PA7, PBO-PB7. CA2. CB2)

5,0 V
AL=24kll

Test POint o---.-~p--+4--'; MMD6150

or Equlv
Test POint
_'I
o-~-,---1I+-";
MM06150
C A or Equlv
V,
130 pF 11 7 kll MMD7000
or EqUiv C R
MM07000
or Equlv.

C=30pF,R=12k

FIGURE 4 - CMOS EQUIVALENT FIGURE 5 - NMOS EQUIVALENT

TEST LOAD TEST LOAD

(IRQ Only)
'IPAO-PA7, CA2)
50V

Test Poon,
I
:-i 3 kll

100 pF I
4-338
MC6821. MC68A21·MC68B21

FIGURE 6 - PERIPHERAL DATA SETUP AND HOLD TIMES FIGURE 7 - CA2 DELAY TIME
(Read Mode) (Read Mode; CRA·5= CRA3= 1, CRA-4= 0)

• Assumes part was deselected during

the prevIous E pulse

FIGURE & - CA2 DELAY TIME FIGURE 9 - PERIPHERAL CMOS DATA DELAY TIMES
(Read Mode; CRA·5= 1, CRA·3= CRA-4=O) (Write Mode; CRA·5 = CRA·3 = 1, CRA-4 = 0)

Enable
/
Enable

'C_A_'~ ~'--~-~--
CA1 _ _ _ _

CA2 ~
PAO·PA7,
CA2

FIGURE 11 - CB2 DELAY TIME

•
FIGURE 10 - PERIPHERAL DATA AND CB2 DELAY TIMES
(Write Mode; CRB·5= CRB·3= 1, CRB-4= 0) (Write Mode; CRB·5= CRB·3= 1, CRB-4= 0)

Enabl.~ /

----,.I----t 'PDW

PBO~PB7 --:xr'1"~ _______

I- 'DC--j
CBt" -Assumes part was deselected during the
prevIous E pulse
*CB2 goes low as a result of the
positive transition of Enable.

FIGURE 12 - CB2 DELAY TIME FIGURE 13 - INTERRUPT PULSE WIDTH AND iiffi RESPONSE
(Write Mode; CRB·5= 1, CRB·3= CRB-4= 0)

'"'~ ::Qf"" • Assumes I nterrupt Enable Bits are set .

CB2 I

• Assumes part was deselected during

any previous e pulse.

Note Timing measurements are referenced to and from 2 low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

4·339
 MC6821. MC68A21. MC68B21

FIGURE 14 - iiiCi RELEASE TIME FIGURE 15 - RESET LOW TIME

Enable--1

_ ---tIR=t--
"The RESET line must be a VIH for a minimum of
IRQ
1 0 f'S before addressing the PIA.

Note T ImmQ measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2 a volts, unless otherwise noted

FIGURE 16 - EXPANDED BLOCK DIAGRAM

iAOA 3& 40 CA1

II
Interrupt Status
Control A
39 CA2

DO 33
01 32 Data Direction
02 31 Register A
(DORA)
03 30
04 29
05 28
06 27 2 PAC

07 26 3 PAl
4 PA2
Peripheral 5 PA3
Interface
6 PA4
A
7 PA5
Bus Input
Register 8 PAG
(SIRl 9 PA7

Vee'" Pin 20
10 PBO
VSS Pm 1
11 PBl
12 PB2
eso 13 PB3
eSl 24 14 PB4
CS2 23 15 PB5
ASO 36 16 PBS
RSl 35 17 PB7
Riw 21
Enable 25
AffiT 34
Data Direction
Register B
(00R8)

18 CBl
Interrupt Status
IROB 37 Contror B
19 CB2

4-340
MC6821·MC68A21·MC68B21

PIA INTERFACE SIGNALS FOR MPU

The PIA Interfaces to the M6800 bus with an 8-bIt bidirec- for the duration of the E pulse. The device is deselected
tional data 'bus, three chip select lines, two register select when any of the chip selects are in the inactive state.
lines, two Interrupt request lines, a read/write line, an enable
line and a reset line, To ensure proper operation With the Register Selects (RSO and RS1) - The two register
MC6800, MC6802, or MC6808 microprocessors, VMA select lines are used to select the various registers mside the
should be used as an active part of the address decoding, PIA. These two lines are used In conjunction With internal
Control Registers to select a particular register that is to be
written or read.
Bidirectional Data (00-07) - The bidirectional data lines The register and chip select lines should be stable for the
(00-07) allow the transfer of data between the MPU and the duration of the E pulse while In the read or write cycle.
PIA, The data bus output drivers are three-state devices that
remain In the high-Impedance (off) state except when the Interrupt Request UReA and IROB) - The active low In-
MPU performs a PIA read operation The read/write line IS 10 terrupt Request lines (iRQA and IROB) act to interrupt the
the read (high) state when the PIA' IS selected for a read MPU either directly or through interrupt priority cirCUitry.
operation, These lines are "open drain" (no load device on the chlpL
This permits all interrupt request lines to be tied together In a
Enable (E) - The enable pulse, E, IS the only timing wire-OR configuration.
signal that is supplied to the PIA, Timing of all other slg(lals Each Interrupt Request line has two Internal mterrupt flag
is referenced to the leading and trailing edges of the E pulse, bits that can cause the Interrupt Request line to go low, Each

•
flag bit IS associated With a particular peripheral Interrupt
Reed/Write (R/W) - This signal is generated by the line. Also, four interrupt enable bits are provided in the PIA
MPU to control the direction of data transfers on the data which may be used to inhibit a particular Interrupt from a
bus. A low state on the PIA read/Write line enables the input peripheral device,
buffers and data is transferred from the MPU to the PIA on Servicing an Interrupt by the MPU may be accomplished
the E signal if the device has been selected, A high on the by a software routine that, on a priOritized basis, sequentially'
read/Write line sets up the PIA for a transfer of data to the reads and tests the two control registers In each PIA for 10-
bus, The PIA output buffers are enabled when the proper ad- terrupt flag bits that are set,
dress and the enable pulse E are present, The interrupt flags are cleared (zeroed) as a result of an
MPU Read Peripheral Data Operation of the corresponding
RESEt - The active low RESET line IS used to reset all data register. After bemg cleared, the Interrupt flag bit can-
register bits 10 the PIA to a logical zero (lowL ThiS line can be not be enabled to be set until the PIA IS deselected during an
used as a power-on reset and as a master reset dUring E pulse. The E pulse is used to condition the Interrupt control
system operation, lines (CA', CA2, CB', CB2L When these lines are used as
Interrupt Inputs, at least one E pulse must or"cur from the In-
Chip Selects (CSO, CS1, and CS2) - These three Input active edge to the active edge of the Interrupt Input Signal to
Signals are used to select the PIA. CSO and CS, must be condition the edge sense network, If the Interrupt flag has
high and ~ must be low for selection of the device. Data been enabled and the edge sense cirCUit has been properly
transfers are then performed under the control of the enable conditioned, the interrupt flag Will be set on the next active
and read/write Signals. The chip select lines must be stable tranSition of the Interrupt input pm.

PIA PERIPHERAL INTERFACE LINES

The PIA provides two 8-bit bidirectional data buses and line while a "0" results in a "low," Data in Output Register A
four InterruptI control lines for interfaCing to peripheral may be read by an MPU "Read Peripheral Data A" operation
deviCes, when the corresponding lines are programmed as outputs,
ThiS data will be read property If the voltage on the
Section A Peripheral Data (PAO-PA7) - Each of the peripheral data lines IS greater than 2.0 volts for a logic "'"
peripheral data lines can be programmed to act as an input or output and less than 0,8 volt for a logic "0" output, Loading
output. ThiS IS accomplished by settmg a "'" in the cor- the output lines such that the voltage on these lines does not
responding Data Direction Register bit for those lines which reach full voltage causes the data transferred into the MPU
are to be outputs. A "0" in a bit of the Data Direction on a Read operation to differ from that contained In the
Register causes the corresponding peripheral data line to act respective bit of Output Register A,
as an input, During an MPU Read Peripheral Data Operation,
the data on peripheral lines programmed to act as inputs ap-
pears directly on the corresponding MPU Data Bus lines. In Section B Peripheral Data (PBO-PB7) - The peripheral
the mput mode, the internal pullup resistor on these lines data lines i[!l the B Section of the PIA can be programmed to
represents a maximum of '.5 standard TTL loads. act as either inputs or outputs m a Similar manner to PAo.
The data in Output Register A will appear on the data lines PA7, They have three-state capabiity, allowing them to enter
that are programmed to be outputs. A logical "1" written In- a high-Impedance state when the peripheral data line is used
to the register Will cause a "high" on the corresponding data as an input, In addition, data on the peripheral data lines

4·341
 MC6821 e MC68A21 e MC68B21

PBC-PB7 will be read properly from those lines programmed peripheral control output. As an output, this line is compati-
as outputs even if the voltages are below 2.0 volts for a ble with standard TTL; as an input the internal pullup resistor
"high" or above 0.8 V for a "low". As outputs, these lines on this line represents 1.5 standard TIL loads. The function
are compatible with standard TTL and may also be used as a of this signal line is programmed with Control Register A.
source of up to 1 milliampere at 1.5 volts to directly drive the
base .of a transistor switch: Peripheral Control (CB2) 1- Peripheral Control line CB2
may also be programmed to act as an interrupt input or
Interrupt Input (CAl and CB1) - Penpheral input lines peripheral control output. As an input, thiS line has high in-
CA 1 and CB 1 are Input only lines that set the interrupt flags put impedance and is compatible with standard TIL. As an
of the control registers. The active transition for these output it is compatible with standard TTL and may also be
signals is also programmed by the two control registers. used as a source of up to 1 milliampere at 1.5 volts to directly
dnve the base of a transistor switch. This line is programmed
Peripheral Control (CA2) - The penpheral control line by Control Register B.
CA2 can be programmed to act as an interrupt input or as a

INTERNAL CONTROLS

•
INITIALIZATION Notice the differences between a Port A and Port Bread
operation when in the output mode. When reading Port A,
A RESET has the effect of zeroing all PIA registers. ThiS
the actual Pin is read, whereas the B side read comes from an
will set PAC-PA7, PBC-PB7, CA2 and CB2 as Inputs, and all
output latch, ahead of the actual Pin.
Interrupts disabled. The PIA must be configured dUring the
restart program which follows the reset.
CONTROL REGISTERS (CRA and CRB)
There are SIX locations Within the PIA acceSSible to the
MPU data bus: two Peripheral Registers, two Data Direction The two Control Registers (CRA and CRBI allow the MPU
Registers, and two Control Registers. Selection of these to control the operation of the four peripheral control lines
locations is controlled by the RSO and RSl inputs together CAl, CA2, CB1, and CB2. In addition they allow the MPU to
With bit 2 in the Control Register, as shown In Table 1. enable the interrupt lines and mOnitor the status of the Inter-
Details of pOSSible configurations of the Data Direction rupt flags. Bits 0 through 5 of the two registers may be writ-
and Control Register are as follows· ten or read by the MPU when the proper chip select and
register select Signals are applied. Bits 6 and 7 of the two
registers are read only and are modified by external Interrupts
TABLE 1 - INTERNAL ADDRESSING occurring on control lines CAl, CA2, CB1, or CB2 The for-
Control mat of the control words IS shown In Figure 18.
Register Bit
RSI RSO CRA·2 CRB·2 LocRtlon Selected DATA DIRECTION ACCESS CONTROL BIT (CRA-2 and
CRB-2)
0 0 1 X Peripheral Register A
Bit 2, In each Control Register (CRA and CRBI, deter-
0 0 0 X Data DirectiOn Register A
mines selection of either a Peripheral Output Register or the
0 1 X X Control ~eglster A corresponding Data Direction E Register when the proper
1 0 X 1 Pertpheral Register B register select signals are applied to RSO and RS1. A "1" In
1 0 X 0 Data DirectiOn Register B bit 2 allows access of the Peripheral Interface Register, while
a "0" causes the Data Direction Register to be eddressed.
1 1 X X Control Register 8
Interrupt Rags (CRA-8, CRA-7, CRB-8, and CRB-7) -
x = Don't Care The four interrupt flag bits are set by active transitions of
signals on the four Interrupt and Peripheral Control lines
when those lines are programmed to be Inputs. These bits
cannot be set directly from the MPU Data Bus and are reset
PORT A-B HARDWARE CHARACTERISTICS
Indirectly by a Read Peripheral Data Operation on the ap-
As shown in Figure 17, the MC6821 has a pair of I/O ports propriate section.
whose characteristics differ greatly. The A Side is designed
to drive CMOS logiC to normal 30% to 70% levels, and incor- Control of CA2 and CB2 Peripheral Control Unes (CRA-3,
porates an internal pullup device that remains connected CRA-4, CRA-5, CRB-3, CRB-4, and CRB-6) - Bits 3, 4, and
even in the Input mode. Because of this, the A Side requires 5 of the two control registers are used to control the CA2 and
more drive current in the input mode than Port B. In con- CB2 Peripheral Control lines. These bits determine If the con-
trast, the B side uses a normal three-state NMOS buffer trol lines will be an Interrupt input or an output control
which cannot pullup to CMOS levels without external signal. If bit CRA-5 (CRB-5) is low, CA2 (CB2) IS an Interrupt
resistors. The B side can drive extra loads such as Darl- input line similar to CAl (CBll. When CRA-5 (CRB-5) IS
ingtons without problem. When the PIA comes out of reset, high, CA2 (CB2) becomes an output signal that may be used
the A port represents inputs with pull up resistors, whereas to control peripheral data transfers. When in the output
the B side (input mode also) will float high or low, depending mode, CA2 and CB2 have slightly different loading
upon the load connected to it. characteristics.

4-342
MC6821. MC68A21· MC68B21

Control of CAl and CBl Interrupt Input Lines (CRA-o. enable the, MPU Interrupt signals iRQA and iRTIli. respec-
CRB-l. CRA-l. and CRB-l) - The two lowest-order bits of tively. Bits CRA-l and CRB-l determine the active transition
the control registers are used to control the Interrupt Input of the interrupt Input signals CAl and CB1.
lines CAl and CB1. Bits CRA-O and CRB-O are used to

FIGURE 17 - PORT A AND PORT B EQUIVALENT CIRCUITS

Port A Port B
Vee Vee

Port Pin
Data Direction
DATA~.., __ Port Pin
Data_--,,_-,

•
Direction
(1- OutPllt Pin)
IO-lnput Plnl

Read of B
Data When
In Output
Mode

Read A Data Read of B

In Input or Data when
Output Mode In Input Mode

Internal PIA Bus

4-343
 MC6821-MC68A21-MC68821

Determine Active CAli CB 1) Transition for Setting FIGURE 18 - COl<jTROL WORD FORMAT
Interrupt Flag IRCAIB)l - lbit 7)
b1=0: IROAIB)l set by hlgh-to-Iow tranSlltOn on CAl
ICB1)
bl =1 IROAIB)l set by low-to-hlgh transition on CAl CAtICB1) Interrupt RequeIrt Enable/ Disable
ICB1) bO=O' Disables IROAIB) MPU Interrupt by CAl
ICB1) active transit Ion.'
bO=l Enable IROAIB) M PU Interrupt by CAl ICB1)
active transition
IRCAIB) 1 Interrupt Flag Ibit 7) 1 IROAIB) will ocbur on next IMPU generated) positive
Goes hlg h on active transition of CAl ICB1), Automa- transition of bO If CAl (C81) active transition De-
tlcally cleared by MPU Read of Output Register AlB) curred while Interrupt wa s disabled
May also be cleared by hardware Reset.

~ -1-
I I J I I I I bOl
b7 b6
Control Register IIROAIS)l IIROAIB)2
Flag Flag
I b5 b4
CA2ICB2)
Control
b3 b2
DDR
Access I
bl
CA1ICB1)
Control I
IRCAIB)2 Interrupt Flag Ibit 6)
I
When CA2 ICB2) IS an Input, IROAIB) goes high on ac- Determines Whether Data Direction Register Or Output
tive transition CA2 I CB2), Automatically cleared by Register is Addresaed

•
MPU Read of Output Register AlB) May also be b2= 0 Data Direction Register selected
cleared by hardware Reset b2 = 1 Output Register selected
CA2 ICB2) Establtshed as Output Ib5= 11. IROAIB)
2= 0, not affected by CA2 ICB2) transitions

1 L
CA2ICB2) Established as Output by b5= 1 CA2 ICB2) Established as Input by b5=O
INote that operaltOn of CA2 and CB2 output
b5 b4 b3 functions are not Identical) Q§ b4 b3
- - F---+-
1 0
CA2
b3=0 Read Strobe with CA 1 Restor.
o L CA2 ICB2) Interrupt Request Enable/Disable
CA2 goes Iowan first hlgh-to-Iow b3=0Disables IROAIAI MPU Interrupt by
E transition following an MPU read CA2 ICB21 active transition."
of Output Register A, returned high b3= 1 Enables IROAIB) MPU Interrupt by
by next active CAl tranSition, as CA2 ICB2) active transition
specified by bit 1 "IROAIB) will occur on next IMPU generat-
b3=1 Read Strobe with E Restore ted) positive transition of b3 If CA2 (CB2)
CA2 goes Iowan ftrst hlgh-to-Iow active tranSition occurred while Interrupt
E tranSItion following an MPU read was disabled
of Output Register A, returned high _Determines Active CA2 ICB2) Transition for
by next hlgh-ta-Iow E transition dur- Setting Interrupt Flag IRCAIB)2 - IBit b6)
I ng a deselect
b4=0' IRQAIB)2 set by hlgh-to-Iow transl-
~ CB2 tton on CA2 (CB2)
b3= 0 Writ. Strobe with CBI Restor. b4= 1 IROAIBI2 set by low-to-hlgh transI-
CB2 goes Iowan ftrst low-to-hlgh tion on CA2 (CB2)
E tranSition following an MPU write
Into Output Register B, returned
high by the next active CB 1 tranSI-
ItOn as specified by bit 1 CRB-b7
must first be cleared by a read of
data
b3 = 1 Write Stmbe with E Restor.
CB2 goes Iowan ftrst low-to-hlgh

--L
E transitIOn followmg an MPU write
Into Output Register B, returned
b5 b4 b3 high by the next low-to-hlgh E tran-
Sltlon following an E pulse which
occurred while the part was de-
selected
1 1 Set/Reset CA2ICB2)
CA2 ICB2) goes low as MPU wrttes
b3=0 Into Control Register
CA2 ICB2) goes high as MPU writes
b3= 1 Into Control Register

4-344
® MOTOROLA MC6822

Product Prev ie,""

MOS
IN-CHANNEL, SILICON-GATE
DEPLETION LOAD)

INDUSTRIAL INTERFACE ADAPTER INDUSTRIAL INTERFACE

ADAPTER

The MCM6822 Industrial Interface Adapter (lA) provides the universal

means of Interfacing Industrial peripheral equipment with the MC6800
Microprocessor Unit IMPU) This device IS capable of Interfacmg the
MPU With industrial penpherals through two B-blt bidirectional L SUFFIX
penpheral parts and four control lines No external logiC IS required for CERAMIC PACKAGE
interfacing With most peripheral deVices Due to the open-drain deSign, CASE 715
Penpheral Ports A and B, as well as the peripheral control lines I CA 1,
CA2, CB1, CB2) can be pulled-up externally to 180 V maximum The
recommended operating voltage range for these ports IS between 0 and
15 volts Thus, the IIA can directly Interface With 15 V CMOS (no level

•
shifters are required) The IIA IS also Ideal for Industrial applications
when Increased nOise margins are reqUired
The functional configuration of the IIA IS programmed by the MPU
dUring system initialization Each of the penpheral data lines can be pro-
grammed to act as an Input or output, and each of the four con-
trol/Interrupt lines may be programmed for one of several control
modes ThiS allows a high degree of fleXibility In the overall operation of
the Interface

• 8-Blt Bidirectional Data Bus for Communication With the MPU

PIN ASSIGNMENT

• Two Bidirectional 8-Blt Ports for Interface wltr Peripherals VSS CAl
PAO CA2
• Two Programmable Control Registers PAl iRciA
PA2 4 IROB
• Two Programmable Data Direction Registers
PA3 RSO
PA4 RS1
• Four IndiVidually-Controlled Interrupt Lines, Two Usable as
Penpheral Control Outputs RESET
DO
• Handshake Control LogiC for Input and Output Penpheral Operation Dl
PBO D2
• Open Drain Penpheral Lines Capable of InterfaCing With Industrial
EqUipment D3
PB2 D4
• Program Controlled Interrupt and Interrupt Disable Capability PB3 13 D5
PB4 14 D6
• CMOS Drive Capability on All Penpheral Lines PB5 15 D7
PB6 16
• Pin Compatible With MC6821 PIA
PB7 17 CSl

• TTL-Compatible Data Bus CBl 18 CS2

CB2 19 CSO
• Fully Static Operation VCC 20 Riw

4-345
 MC6822

IIA INTERFACE SIGNALS FOR MPU

The IIA Interfaces with the MC6800 MPU via an B-blt bidirec- trol of the Enable and Read/Write Signals. The chip select
tional data bus, three chip select lines, two register select lines must be stable for the duration of the E pulse The
lines, two Interrupt request lines, read/write line, enable line, deVice IS deselected when any of the chip selects are In the
and reset line. These signals, In conjunction with the Inactive state.
MC6800 VMA output, permit the MPU to have complete
control over the IIA. VMA should be utilized In conjunction
with an MPU address line Into a chip select of the IIA IIA REGISTER SELECT (RSO AND RS1)
The two register select lines are used to select the various
IIA BIDIRECTIONAL DATA (DO-D7) registers Inside the IIA These two lines are used In conJunc-
The bidirectional data lines (00-07) allow the transfer of tion with Internal Control Registers to select a particular
data between the MPU and the IIA The data bus output register that IS to be written or read
drivers are three-state devices that remain In the hlgh- The register and chip select lines should be stable for the
Impedance (off) state except when the MPU performs an IIA duration of the E pulse while In the read or write cycle
read operation. The Read/Write line IS In the Read (high)
state when the IIA IS selected for a Read operation
INTERRUPT REOUEST (iROA AND IROB)
IIA ENABLE (E) The active low Interrupt Request lines (IRQA and IROB)
act to Interrupt the MPU either directly or through Interrupt
The enable pulse, E, IS the only timing signal that IS sup-
PriOrity circuitry These lines are "open drain" (no load
plied to the IIA. Timing of all other signals IS referenced to
deVice on the chip!. ThiS permits all Interrupt request lines to

I
the leading and trailing edges of the E pulse This signal will
be tied together In a Wire-OR configuration
normally be a derivative of the MC6800 </>2 Clock
Each Interrupt Request line has two Internal Interrupt flag
bits that can cause the Interrupt Request line to go low. Each
IIA READ/WRITE (R/W)
flag bit IS associated With a particular peripheral Interrupt
This signal IS generated by the MPU to control the direc- line Also, four Interrupt enable bits are proVided In the IIA
tion of data transfers on the Data Bus A low state on the IIA which may be used to Inhibit a parllcular Interrupt from a
Read/Write line enables the Input buffers and data IS peripheral deVice
transferred from the MPU to the IIA by the E signal If the ServIcing an Interrupt by the MPU may be accomplished
device has been selected. A high on the Read/Write line sets by a software roullne that, on as prioritIZed baSIS, sequential-
up the IIA for a transfer of data to the bus. The IIA output ly reads and tests the two control registers In each IIA for in-
buffers are enabled when the proper address and the enable terrupt flag bits that are set.
pulse E are present The Interrupt flags are cleared (zeroed) as a result of an
MPU Read Peripheral Data Operation of the corresponding
RESET data register After being cleared, the Interupt flag bit cannot
The active low RESET line IS used to reset all register bits be enabled to be set unlll the IIA IS deselected dUring an E
In the IIA to a logical zero (Jaw) This line can be used as a pulse The E pulse IS used to condition the Interrupt control
power-on reset and as a master reset dUring system opera· lines (CA 1, CA2, CB 1, CB2) When these lines are used as In-
tlon terrupt Inputs, at least one E pulse must occur from the inac-
tive edge to the active edge of the Interrupt Input Signal to
IIA CHIP SELECT (CSO-CS1 AND CS2) condition the edge sense network If the Interrupt flag has
These three Input Signals are used to select the IIA C50 been enabled and the edge sense CIrCUIt has been properly
and CS 1 must be high and C52 must be low for selectIOn of conditIOned, the Interrupt flag will be set on the next active
the deVice Data transfers are then performed under the con- transition of the Interrupt Input Pin

4·346
MC6822

4-347
 ® MOTOROLA MC6828
MC8501
Note: The dual numbering system emphaSIS that
thiS deVice IS a bipolar LSI service and directly
compatible with the M6800X Microprocessor
Family The Priority Interrupt Controller may be
ordered by uSing either part number

PRIORITY INTERRUPT CONTROLLER

The MC6828/8507 Priority Interrupt Controller (PIC) IS used to

add prIOritized responses to Inputs to microprocessor systems. The
performance has been optimized for the M6800X system, but will MEGALOGIC
serve to eliminate Input polling routines from any processor system
The MC6828/8507 (PIC) modifies the vector ROM addresses PRIORITY INTERRUPT
that the microprocessor uses to Jump to an Interrupt routine The CONTROLLER
MC6828 provides the user with an additional eight latched Interrupt
inputs, and it can be cascaded to provide more Interrupts
An Interrupt mask prevents any latched Interrupt input of lower
priOrity than the mask level from generating an iRQ output.
The (PIC) allows for any added decode time by generating a Stretch

•
Signal which can be used to slow the processor clock while fetching
Interrupt routine starting addresses. The Stretch Signal allows the
Interrupt structure to be deSigned without concern for faster opera-
tion due to Improvements In processor speeds l SUFFIX
CERDIP PACKAGE
CASE 623-03

Latched Inputt
BLOCK DIAGRAM
PSUFFIX
PLASTIC PACKAGE
CASE 649-03
24
4'J 1
.

IN711 1-of-8
IN610 Priority Vector
IN5 9
IN4 8 -.b'7'1=T."'CriL~8~IL~~~;~P
IN3 7
IN2 6
IN1 5
INO 4 f - - - - + - - - - - < > 2 3 INT PIN ASSIGNMENT

4 24
23
Vector 22
8us
E 18 4 21
R/W 17
20
eso 3
eS1 1 ~22Z4 6 19
L....=T'-"'--...Jor Address --<> 21 2;3
4 18
I Address --02022
Bus 4 4 --019 Z1 8 17
9 16
L....______________ ~ 2 Str~ch

Vee'" PIn 24 10 15
Gnd = Pm 12 11 14
12 13

4-348
MC682S-MC8507

MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage Vcc -05 to + 7 0 Vde
Input Voltage VIR -10 to +5 5 Vde
Output Voltage VOH -0 4to +70 Vde

THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Thermal Resistance Cerdlp ReJA 65 °CIW
PlastIc 120

POWER CONSIDERATIONS

The average chip-Junction temperature, TJ, In °C can be obtained from

TJ = TA + (PO' 0JA) (1)
Where
TA:= Ambient Temperature, °C
0JA:= Package Thermal Resistance, Junctlon-to-Amblent, °C/W
Po == PINT + PPORT
PINT'" ICC x VCC, Watts - Chip Internal Power
PPORT:= Port Power DIssipation, Watts - Us"r Determined
For most applications PPORT <{ PINT and can be neglected, PPORT may become Significant If the deVice IS configured to
dTive Darlington bases or sink LED loads,
An approximate relatIOnship between Po and TJ (If PPORT IS neglected) IS'
II
Po = K.;- (TJ + 273°C) (2)
Solving equations 1 and 2 for K gives:
K = Po [TA + 273°C + (PO' 0JA)] (3)
Where K IS a constant pertaining tothe particular part K can be determined from equation (3) by measuring Po(atequilib-
Tlum)for a known TA USing thiS value of K the values of Po and TJ can be obtained by solving equations (1) and (2) iteratively
for any value of TA

ELECTRICAL CHARACTERISTICS (VCC = 5 0 Vde -+5%, TA = 0 to 75°C unless otherwise noted)

Characteristic Symbol Min Max Unit
Input Forward Current III ~Ade
= =
(Vll 0, VCC 5 25 Vde) CS1, E - -75
CSO, R/W - -150
A1 thru A4 - -225
INO thru IN7 - -1300
Input Leakage Current IIH "Ade
= =
(VIH 2 4 Vde, VCC 5 25 Vde) CS1 - 120
CSO - 240
Al thru A4 - 360
1 NO thru IN7 - -560
DC logiC "0" Output Voltage Val Vdc
= =
(lOl 1 6 mAde, VllT 0 8 Vde, ZI thru Z4, Stretch - 05
= =
VIHT 2 0 Vde, VCC 4 75 Vde)
= =
(lOl 3 2 mAde, VCC 4 75 Vde) IRQ - Open Collector - 0.5
DC logiC "1" Output Voltage VOH 24 - Vde
= =
(lOH -0 3 mAde, VllT 0 8 Vde, ZI thru Z4, Stretch
= =
VIHT 2 0 Vde, VCC 4 75 Vde)
Output Leakage Current ICEX - 200 "Ade
= =
(VCC VCEX 5 25 Vde) INT
Power Supply Drain Current ICC - 125 mAde
=
(VCC 5 0 Vde, All Inputs Open)

4·349
 MC6828-MC8507

SWITCHING TIMES (VCC; 50 Vdc, TA; 25°C)

Characteristic Symbol Min Max Unit
A, to Z, Delay Time (Not Selected) tAZ - 75 ns
A, to Z, Delay Time (Selected) tAZ - 60 ns
Select* to Z, Delay Time tcsz - 125 ns
(Al . A2· A3 . A4 . CSO . CSl toZ,)
Enable Pulse Width TCYC 100 - ns
Enable Low to CS 1 TCSl 125 - ns
Deselect to Stretch High tSTR</> - 125 ns
Select· to Stretch Delay Time tSTR - 140 ns
(Al . A2· A3· A4· CSO· CSl to StreiCh)
Enable to INT Delay Time, Non-Masked Mode tiNT - 240 ns
Enable to INT Delay Time, Masked Mode tMINT(IN1) - 360" ns
tMINT(INJ) - 200"
·Select:::: (A 1 A2 A3 A4 eso CSl RIW) which corresponds to FFFB or FFF9 Interrupt response In the M6800 system
"Value depends on mask level and stored Priority Input Maximum value occurs With mask laval 7 and stored Interrupt INO Minimum value occurs With mask level J
and stored Interrupt IN(J)

•
FIGURE 1 - FUNCTIONAL WAVEFORMS
NON-MASKED MODE MASKED MODE
Load
Load and MPU Outputs Interrupt Load & Mask 0
Store Vector Register Load Store (Reset) &
FFF8 & FFF9 Mask 8 Interrupt 0 Enable INT
(2 Cycles)
I I I
E
L..F\.... OV

iN'i thru
iN?
11
'MINT t-
R/W ~ ~

~ II
~

@J :' ~

At __A-____~~--~,~~~------~~----~~------~~-- ~ :, ~

A2 __~____~~__ ~~______~~____~~____~~-- ~ :, ~

~ :, ~

A4 --"-------'"'"1'-----1 ~ :, ~

Zt __f'-____~~~~~~~------~'----------~----~~-
Notes:
Z2 __n-____~~~~~~~------~'----------~----~~- 1. ~ Data not valid

Z3 _ " -____--''"'''-''\--...

Z4 __n-____~~1-~

4·350
MC6828-MC8507

OPERATING CHARACTERISTICS

The primary purpose of the Priority Interrupt Controller The 1-of-8 Priority encoder enables a vector corres-
(PIC) IS togenerate a modified address to ROM In response ponding to the stored Interrupt with the highest Priority
to prioritIZed Inputs. With the PIC, each interrupting device and places It on the vector Input port of a data selector In
IS assigned a unique ROM location which contains the addition an Interrupt request signal INT IS generated to
starting address of the appropriate service routine After signal the MPU that an Interrupt has been dstected The
the MPU detects and responds to an Interrupt, the PIC mask location register overrides and inhibits all Interrupts
directs the MPU to the proper memory location. with Priority below the mask level The mask can be
The basIc functions of the PIC are shown In the block thought of as a movable partition allowing responses to
diagram The 8-blt request register IS an edge clocked Inputs equal to or greater than the mask value For
D-type register with Internal 6 kfl pullup resistors on the inter- example If the stored mask level was 4, Inputs INO, iN'i,
rupt Inputs (INO thru IN7) Note the Inputs are active low IN2, and IN3 would not generate an Interrupt to the MPU
The Interrupt register IS loaded on the failing edge of the system The Input request register IS not affected by the
enable when the PIC IS not selected mask, and If the mask IS cleared (by loading It with zeros),
any previously stored Inputs will generate an IRQ signal

•
FIGURE 2 - MC6B2B TRUTH TABLE FOR M6BOO MICROPROCESSOR SYSTEMS

Output When Equivalent to

Selected Bits 1·4 of
Active BO, Bl ... , B15 Address ROM Byte.
Input Z4 Z3 Z2 ZI Hex Address Contain Address of:
Highest IN7 1 0 1 1 F F F 6 or 7 Priority 7 Routine
IN6 1 0 1 0 F F F 4 or 5 Priority 6 Routine
-
IN5 1 0 0 1 FFF20r3 Priority 5 Routme
IN4 1 0 0 0 F F F 0 or 1 Priority 4 Routme
IN3 0 1 1 1 F FEE or F Priority 3 Routine
IN2 0 1 1 0 F F E C or D Priority 2 Routme
TNT 0 1 0 1 F F E A or B Priority 1 Routme
Lowest INO 0 1 0 0 F F E 8 or 9 Priority 0 Routine
None 1 1 0 0 FFF80r9 Default Routine·
*Default routine IS the response to interrupt requests not generated by a PrioritIzed Input The default routine may contain pollmg
routines or may be an address In a loop for an Interrupt dnven system.

FIGURE 3 - MC6B2B TRUTH TABLE FOR M6B09 MICROPROCESSOR SYSTEMS

Output When
Selected
Active Equivalent Address ROM Bytes
Input Z4 Z3 Z2 ZI Hex Address Contain Address of:
Highest IN7 1 0 1 1 FFD6-FFD7 Priority 7 Routine
IN6 1 0 1 0 FFD4-FFD5 PriOrity 6 Routine
IN5 1 0 0 1 FFD2-FFD3 Prlonty 5 Routine
IN4 1 0 0 0 FFDO-FFD1 PriOrity 4 Routine
IN3 0 1 1 1 FFCE-FFCF PriOrity 3 Routine
IN2 0 1 1 0 FFCC-FFCD PriOrity 2 Routine
IN1 0 1 0 1 FFCA-FFCB Prlonty 1 Routine
INO 0 1 0 0 FFC8-FFC9 Priority 0 Routine
Lowest None 1 1 0 0 F FFI8-FFF9 Default Routine IIRQ)

4-351
 MC6828-MC8507

Chip Select and Stretch The Influence of the mask register on the Priority encoder
The chip select and decode circuitry controls all Internal IS shown In the truth table of Figure 6. The actual use olthe
functions of the PIC. The selected mode IS defined as the mask register Will vary with the system needs and the
logical AND function A1 . A2· A3· A4· CSO· CS1 . R;W. imaginative software programmer.
When the device IS not In the selected mode the request Special Cases
register clock IS enabled and the address Inputs A, passes As originally conceived, the PIC was only meant to be
directly through the data selector to the Z, outputs. When used with the MC6800 MPU. With the advent of higher
the MPU responds to the Interrupt request and the PIC performance/function microprocessors such as the
decodes the select address, the request register IS inhib- MC6809/MC6802/MC6808, priOritIZed Interrupts are
Ited and the data selector places the vector on the Z out- still reqUired. The Interrupt vector map for the M6800 IS
puts. The address delay added tothe MPU system IS shown located from FFF8 to FFFF With the MC6809, this vector
In Figure 4 This delay may be critical In some systems. A map extends downward to FFFO As can be seen in Figure 2.
stretch signal, which indicates the selected mode, IS pro- the normal configuration of the PIC places Priority Interrupt
vided for use with special MPU clock drivers to stretch the vectors from FFE8 to FFF7 which conflict with the eXisting
clock cycle when accessing slow ROM. This stretch signal MC6809 Interrupt vectors Figure 1 shows appropriate
IS applicable only to those microprocessors which incor- Circuitry reqUired to Interface with the MC6809. Figure 3
porate external clock generators, I.e., 6800, 6809E. The gives the "modified Priority vectors'" associated with thiS
user cannot directly connect stretch to MRDY on the hardware modification.
MC6809 or MC6802. as stretching the clock circuit with a

•
signal which IS derived from the clock will latch up the Note 1 Smce dUring normal operation of the MPU the address hnes and
MPU An alternative to this problem IS to use a one-shot the R/W line can be In an Indetermmate state, VMA should be
logically ANDed with one of the chip select Inputs of the PIC to
which would provide the reqUired amount of access time
prevent erroneous writes Into the mask register (non-6800
Figure 8 illustrates a tYPical such CirCUIt. The CSO output systems)
has one less gating level than the remainder of the select
decode logiC. This allows an external NAND gate to be
used for the fu II address decode without any Increase In
delay times
Programming the PIC
Changing the PriOrity level, or mask, In the PIC IS done FIGURE 4 - HIGH ROM ADDRESS
DELAY ADDED TO M6BOOX SYSTEMS
by writing to the deVice Unlike normal programming of a
peripheral where a specific data pattern IS written Into a
selected register, the PIC IS programmed by accessing a
location determined by A 1 through A4 while R/W IS low.
The decode logiC also controls the loading of the mask
location register. This register will be loaded on the failing \'--______1
edge olthe enable pulse when enabled by the logical AND
function CSO' CS 1 . R/W (Note 1). This means that In the
load mask mode the data on the data bus IS a don't care.
4>2 \ '--._ _---I/
However, in this mode the ROM will also be accessed and
both the ROM and MPU will be driVing the data bus. There-
fore the read/write line should be used as an active high
chip select or enable signal for ROM decoding.
Al-A4 f£;;~;;)( Valid
Address
1'---~I-tA-z-----------------­
Figure 5 shows the tYPical operation flow diagram for
'7/77'?77m=~
the PIC in an M6800 system. The functional timing for Z1-Z4 %"lnval1d Interrupt Valid ROM
thiS flow IS as shown in the first part of the waveforms in ~ Vector Addre..
Figure 1. The second half of Figure 1 shows the operation
of the mask. Interrupts will be stored even if they are
masked. When the mask is released the INT signal will
then be generated.

4·352
MC6828·MC8507

FIGURE 6 - BASIC FUNCTIONAL FLOW CHART

•
FIGURE 6 - MASK OPERATION

8 - MASK FLOW CHART

b - MASK TRUTH TABLE

Mask Register Response to Priority Inputs

·See Mask Contents 1 = Response to Input, 0 = No Response
Truth Table
M4
, ,, ,, ,
M3 M2 M" IN7 INS IN5 IN4 IN3 IN2 IN' INO

,,,
0 0 0 0 0 0 0 0

,, 0 ,
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

,, 0 ,,0
,
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

,
,
0
0 0 ,
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
,, ,, 0
,
0

,,,
0 0
0
,
0
0
0
0
0
0
0
0
0
0
0
0
0
0 ,, 0 ,
0

,, ,, ,, ,
0 0
0
0
0
0
0
0
0
0
0
0

,,
0
,
0
,, , , ,, 0 0 0 0

,,, ,, ,, , ,, ,
0 0 0 0 0
•• Must Have Been
Previously
0
0
0
0 0 ,
0
,
, , , , , , ,
0 0
0
Stored RAM 0 0 0 0

4-353
 MC6828-MC8507

FIGURE 7 - TYPICAL SYSTEM CONFIGURATION

+50

MC6800/02/08/01/09 33 k

F/IRQ 23

iNT ·See Text for

Stretch iii'
Stretch Signal Usage

R/W
INO
A15
INl
A14
A13 - IN2

II
A12 IN3 8 Interrupt
All Inputs from
IN4 PI As or Latches
Al0
A9 CSl IN5
10
A8 IN6
A7 11
IN7
A6
A5
MC6828
VMAon
Non~6809
Systems

Highest Address ROM

0
0
Al 16
OJ Al
A2
~
15
A2 AO
0
A3 14 19

~
A3 Zl Al
A4 13 20
.p A4 Z2 A2
::i' 24 21
+50 VCC Z3 A3
12 22
VSS Z4 A4

AO
- A5

A5 I Non-SaOg Connect
ROM Decode

"Not Required In
Non-GaOg Systems

4-354
MC6828- MC8507

FIGURE 8 - ACCESS TIME EXTENSION USING STiiEl'Cii AND MRDY

74121

14

4
A2

}
R1

3 11 Set Values
A1 for Appropriate
Length of Stretch

5 C1
B
10

Q
L....r
~------------. . . To MRDY on MC6809/MC6802!M6808

- or Clock Generators for

MC6800/MC6804

II
Ordering Information

Motorola Integrated Circuit ~

M6800 Family - - - - - - - - ' -
j
28

Device Designations - - - - - - - - '

JP 1
Package Designation
P = Plastic
L = Ceramic

4·355
 ® MOTOROLA

Advance Infor:rnation

MEMORY MANAGEMENT UNIT HMOS

(HIGH DENSITY N-CHANNEL, SILICON-GATE)
The principle function of the MC6829 Memory Management Unit
IMMU} is to expand the address space of the MC6809 from 64K bytes to MEMORY MANAGEMENT UNIT
a maximum of 2 Megabytes. Each MMU is capable of handling four dif- (MMU)
ferent concurrent tasks Including DMA. The MMU can also protect the
address space of one task from modification by another task. Memory
address space expansion is accomplished by applying the upper five ad-
dress lines of the processor IA ll-A 15} along with the contents of a 5-bit
task register to an Internal high-speed mapping RAM. The MMU output
consists of ten phYSical address lines IPA ll-PA20l which, when com-
bined with the eleven lower address lines of the processor IAO-A!o},
forms a phYSical address space of 2 Megabyt!ls. Each task IS assigned
memory In Increments of 2K bytes up to a total of 64K bytes. In thiS
manner, the address spaces of different tasks can be kept separate from
one another. The resulting simplification of the address space program-
ming model will Increase the software reliability of a complex multi-

•
process system .
• Expands Memory Address Space from 64K to 2 Megabytes
• Each MMU is Capable of Handling Four Separate Tasks
• Up to Eight MMUs can be Used in a· System
• ProVides Task Isolation and Write Protection
• Provides Efficient Memory Allocation; 1024 Pages of 2K Bytes Each PLASTIC PACKAGE
• Designed for Efficient Use with DMA CASE 711

• Fast, Automatic On-Chip Task SWitching

• Allows Inter-Process Communication Through Shared Resources
• Simplifies Programming Model of Address Space
PIN ASSIGNMENT
• Increases System Software Reliability
• MC6809/MC6800 Bus Compatible VSS Pl?-ll
• Single 5-Volt Power Supply A15 PA12
Al4 PA13
BLOCK DIAGRAM
PA14
Mappmg RAM
Task 0 Registers A12 PA15
Task 1 Registers All PA16
All-A15
RA PA17
RS6 PAlS
RS5 PA19
RS4 10 PA20
SA
RS3 11 07
SS 12 06
RS2
RESET RSl 13 05
RSO 14 04

a KVA 15 03
Q 16 02
DO-D7
17 01
BA 18 00
BS 10 Vee;
RESET 20 R/W

4·356
MC6829· MC68A29· MC68B29

MAXIMUM RATINGS
This device contains circuitry to protect the In-
Characteristics Symbol Value Unit puts against damage due to high static voltages
Supply Voltage Vcc -03to+70 V or electnc fields, however, It IS advised that nor-
Input Voltage Vin -03to +70 V mal precautlOns be taken to avoid application of
any voltage higher than maximum rated voltages
Operating Temperature Range h to TH to this high-Impedance CirCUIt Reliability of
MC6829. MC68A29. MC68B29 TA o to 70 'c
operation IS enhanced If unused Inputs are tied to
MC6829C. MC68A29C. MC68B29C -40 to +85
an appropriate logiC voltage level (e.g, either
Storage Temperature Range TstQ -55 to + 150 °C
VSS or VCC)

THERMAL CHARACTERISTICS
Symbol Value Rating
Thermal ReSistance
Plastic 100
6JA °C/W
Cerdlp 60
Ceramic 50

The average chip-junction temperature, T J,

TJ=TA+(POoOJA)
Where:
TA-Ambient Temperature. °c
In
POWER CONSIDERATIONS

°C can be obtained from:

OJA- Package Thermal ReSistance, Junctlon-to-Amblent, °C/W

PO- PINT + PPORT
(11
•
PINT-ICCxVCC, Watts - Chip Internal Power
PPORT- Port Power Oissipatlon, Watts - User Oetermlned
For most applications PPORT -C PINT and can be neglected PPORT may become significant If the deVice IS configured to
drive Oarlington bases or Sink LEO loads
An approximate relationship between Po and T J (If PPORT IS neglected 1 IS'
PO= K+ (T J + 273°C) (21
SolVing equations 1 and 2 for K gives
K = POon A + 273°CI + 8JAoP 0 2 (31
Where K IS a constant pertaining to the particular part K can be determined from equation 3 by measuring Po (at eqUilibrium)
for a known TA. USing this value of K the values of Po and T J can be obtained by solVing equations (11 and (21 Iteratively for any
value of T A.

DC ELECTRICAL CHARACTERISTICS (VCC~5 0 Vdc ±5%. vss~O. TA~TL to TH unless otherWise notedl
Characteristic Symbol Min Typ Max Unit
Input High Voltage All Inputs VIH VSS + 20 - VCC V
Input Low Voltage All Inputs VIL VSS 03 VSS+OB V
Input Leakage Current (V in - 0 to 5 25 V) Vcc-Max lin - 10 25 ~A
Three-State IOff State) Input Current IV In ~ 04 to 24 V) DO-D7 liZ - 20 10 ~A
Output High Voltage
(iload = -145 ~A) DO-D7 VOH VSS+24 - - V
Vcc~mm PA11-PA20 VSS + 24 - -
Output Low Voltage
(iload ~ 20 mAl DO-D7 VOL - - VSS+O 5 V
Vcc=max PA11-PA20 - - VSS+O 5
Internal Power DIsSipation (Measured at TA- TLI PINT 800 mW
"Input l;apacltance IV,n O,IA 2b°l;, f 1 bMHz) All Inputs l;1n IUU ILU P
Output Capacitance (V in =0, TA - 25'C, 1-1 5 MHz) All Outpu,s Cout - - 120 pF

4-357
 MC~MC~MC~B~

BUS TIMING CHARACTERISTICS (See Notes 1 and 21

klent. MC682!I MC88A29 MC6BB29
Characteristic Symbol Unit
Number Min Max Min Max Min Max
1 Cycle Time !eve 10 10 0667 10 05 10 "s
2 Pulse W,tdth, E Low PWEL 430 9600 280 9600 210 9700 ns
3 Pulse Width, E High PWEH 450 9500 2BO 9500 220 9700 ns
4 Clock Rise and Fall Time tr,tf - 25 - 25 - 20 ns
5 Pulse Width, a High PWaH 430 5000 2BO 5000 210 5000 ns
e Pulse Width, a Low PWaL 450 9500 2BO 9600 220 9500 ns
7 E to a Rise Delay Time· tAva 250 165 125 ns
9 Address Hold Time tAH 10 10 10 ns
13 Address Setup Time Before E tAS 80 60 - 40 ns
14 Chip Select Setup Time Before E tcs 80 - 60 - 40 - ns
15 Chip Sel9j:t Hold Time tCH 10 10 10 ns
18 Read Data Hold Time tDHR 20 100 20 100 20 100 ns
21 Wrote Data Hold lime tDHW 10 10 10 ns
30 Output Data Delay Time tDDR 290 180 150 ns

•
31 Input Data Setup Time tDSW 165 - 80 - 60 - ns
See Figures
2 and 3
Three-State Address Delay tTAD - 90 - 80 - 60 ns

See Figure 2 Mapped Address Delay tMAD - 200 - 145 - 110 ns

• At specified cycle lime

FIGURE 1 - BUS TIMING

~--------~2t-----------~~ ________________________ ~

R/VV,Address----~~~~~~,,~~~--~-,~~~----t1r---------------------------------i_~~?f7
(Non-Muxedl

Read Data ___~~......;t--------------~M;;.p.;:U;;.R;;.e:.:a:.:d..:D:.:a:.:ta:..:..N..:o;;.n-;;.M..:u:;.x..:ed:..:..---------1~=~

Non-Muxed -,...___; :______ -++_.,-

Wrote Data_
Non-MlIxed
-==!Jt==:~:- ________________ .....:M;;.p..:u:........w_r;;.lte:..:.D.:.at=a_N;;.o;;.n_-M.....:ux..:e..:d-_ _ 1~=~
l"'--;'-----:::-+-""r
Notes
1 Voltage levels shown are VLSO 4 V, VH:.2 4 V, unless otherwise specified
2 Measurement pOints shown are 0 8 V and 2 0 V, unless otherWise specified

4·358
MC6829-MC68A29-MC68B29

FIGURE 2 - MAP SWITCHING, ADDRESS MAPPING

.E _ _ -JI \,"-----JI \'--_--11

Q

A11-A1S

SA, SS

PA11-PA20 II
FIGURE 3 - RESET TIMING

\~---'/ \~---'/
E _ _ _ _/

PA11-PA20 If!!111mI//Jffflt

Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and 8 high voltage of 2.0 volts, unless otherwise noted.

4-359
 MC682ge MC68A2ge MC68B29

PIN DESCRIPTION RESET - RESET (Input). A low level on this input causes
the MMU to initialize its registers to a known state. An inter-
The following section describes each pin of the MMU In nal flag IS also set which forces $3FF onto the physical ad-
detail. dress lines until the Key Value Register is wntten. mET
must be low for at least one cycle.
VCC. VSS - Supplies power to the MC6829. VCC is +5
volts and VSS is ground.

E - Input E clock (from MC6809).

a- Input Q clock (from MC6809)' MMU OPERATION

R/W - Read/Write Line Input; 1 = Read, 0= Wnte. For every processor cycle, the MMU supplies a mapped
address based on the processor address and the current task
00-07 - Bi-dlrectional Data Bus. The data bus IS used number (refer to Figure 4), The current task number IS kept
when the M M U registers are to be read or written. In an on-chip register called the OPERATE KEY. Changing
the value of the operate key causes a new map to be
Al1-A15 - Logical Address Lines (Input to MMU). The selected.' The MMU also contains automatic task switching
physical address lines are generated by the M M U for every logiC to cause pre-defined task numbers to override the task
number In the operate key for certain events (Interrupts,

•
bus cycle. When multiple MMUs are present in a system, on-
ly one M M U will output a phYSical address. Each physical ad- Direct Memory Access, Reset)
dress line Will drive one Schottky TTL load or four TTL loads The MMU registers always appear as a block of 64 byes
and a maximum of 90 pF. located on the last page of task #0 (refer to Figure 5), When
the registers are accessed;the MMU outputs a phYSical ad-
PA11-PA20 - Physical Address Lines (Output from dress of $3FF (PA ll-PA20 all high) ThiS IS necessary Since
MMU). The phYSical address lines are generated by the the mapping RAM of the MMU cannot map an address and
MMU for every bus cycle. When multiple MMUs are present be modified at the same time.
in a system, only one MMU will output a phYSical address The exact location of the MMU registers Within the last
Each phYSical address line Will dnve one Schottky TTL load page of physical memory IS determined by the REGISTER
or four LS TTL loads and a maximum of 90 pF. ACCESS (RA) signal which IS Similar to a chip select line.
The RA Signal Will normally be denved from processor ad-
RSO-RS6 - Register Select Lines (Access to MMU dress lines A7-A 10 uSing a Simple 4-lnput gate. For example,
Registers). When accessing the MMU registers, the register a 4-lnput NOR gate would place the MMU registers ~t $FBOO
select lines determine which byte of Information IS being to $F87F In systems uSing DMA, the RA Input must Include
referenced Within the MMU. Valid addresses are detailed in the externally derived DMA/VMA Signal to prevent dead bus
the Register Select Truth Table. cycles from affecting the MMU Refer to Programming Con-
Siderations
BA, BS - Bus Available and Bus State (Inputs). These in- Inputs RSO-RS6 to the MMU are the register select lines.
puts are directly connected from the BA, BS lines of the These lines are normally connected to the low order address
MC6809. They proVide the MMU With information about the lines AO-A6 from the processor. The MMU registers are only
class of bus operation for each cycle. Note that when com- accessible if:
Ing out of a DMA cycle, the MC6809 BA, BS pinS change 1. the current task number IS zero;
back from DMA acknowledge (BA= I, BS= 1) to running 2 processor address lines All-A15 are aliI's,
(BA = 0, BS = 0) one cycle before the end of the DMA. 3. the Register Access line (RA) IS asserted low;
4. Register Select lines (RSO-RS6) contain a defined
RA - Register Access (Chip Select for MMU Registers).
register address, and
ThiS active low Input determines the location of the MMU
registers. Since the MMU registers are only accessible from 5. the System Bit (S-bit) IS set (for a write operation
the last page of task #0 ($FBOO-$FFFF), thiS Signal can be only).
derived from address lines A 10-A7 of the processor. When As a result of the above restnctlons on accessing the
RA IS asserted low, the MMU registers are selected If the MMU registers, the portion of the software that sets up and
current task number IS zero and AI5-All are all 1'5. maintains the memory maps for all tasks must run as task
zero ..
KVA - Key Value Access select line (Input). ThiS active The first 64 bytes of the MMU's register area comprise a
low Input enables access to the 3-blt Key Value register on "Window" through which anyone of the 4 maps may be
the MMU. Reading the Key Value Register IS allowed only Viewed or changed. The task number to be Viewed through
when the current task IS zero, address lines A ll-A 15 are all thiS "Window" IS written Into a read/write register called the
ones, RA=O (asselted), RS6-RSO are Within the range ACCESS KEY Thus, to examine or change the map for any
$40-$47 and KVA = 0 (also asserted), Wntlng the Key Value task, the processor must first wnte the task number into the
Register has the additional requirement of haVing the S-blt Access Key. Once set, the Access Key Will retain ItS value
set until expliCitly changed

"Refer to Register Select Truth Table for exact procedure to change thiS register

4-360
MC6829- MC68A29- MC68B29

FIGURE 4 - LOGIC-TO-PHYSICAL ADDRESS TRANSLATION DIAGRAM

Logical Address

Task # Aol
~
Interrupt ......
Mapping RAM
DMA_

~
PA11I PA10
Physical Address

Access
Key
Register
00
01
02
03
04
05
D7

PAlS

PAlS

PAlS
D6

PA17

PA17

PA17
FIGURE 5 - MMU REGISTER MODEL
D5

PA16

PA16

PA16
D4

PA15

PA15

PA15
D3

PA14

PA14

PA14
D2

PA13

PA13

PA13
Dl
PA20
PA12
PA20
PA12
PA20
PA12
DO
PA19
PAll
PA19
PAll
PA19
PA11
Logical Address

$OOOO-07FF

$08OO-$OFFF

$lOOO-$17FF
•
"Window"
./' ./
./ o
./
./' o
./
./ o ./
./' o /.
3E I I I I I PA20 I PA19
$F800-$FFFF
3F PAlS I PA17 I PA16 I PA15 I PA14 PA13 I PA12 I PAll
40 KV MMUO
41 KV MMUl Only one Key Value Register for
42 KV MMU2 each MMU, but all Key Value
43 KV MMU3 RegIsters fall In thiS range
44 KV MMU4
45 KV MMU5
46 KV MMU6'
47 KV MMU7
48 I S System! User flag bit
49 Fuse Map SWitch Fuse
T ask Currently Accessed Through
4A I Access Key
Register #$0-$3F
46 I Operate Key
Current Task
4C o
./ 0 ./
./' . / Undefined
. / ' 0 . /
7F rl----4------+----~----~?----_4----_+------+_--~
Notes
1 The contents of bytes $4C through $7F are undefined and do not respond to any reads or wntes
2 The Access, Operate and Key Value Registers are cleared on reset
-the S-blt IS set
3 Unused bits of defmed registers always read zeros
4, Locations $40-$47 are accessible only when KV A = 0
5 In multiple MMU configuratIOns, the MMU whose Key Value Register matches the upper three bits of the access key will respond to a pro-
cessor read of locations $48-$48 Processor wntes to these registers wIll cause the data to be wntten to all M~Us simultaneously

4-361
 MC682ge MC68A2ge MC68B29

Pages in physical memory require 10 bits to define their BUILDING AN MMU SYSTEM
location (refer to Figure 5), These 10 bits are arranged as a Up to 8 chips may be connected in parallel to~te a max-
pair of bytes in the MMU in order to allow the use of double imum of 32 tasks. All MMU pins except one (KVA) may be
byte instructions (e.g., LDD) in manipulating the MMU wired in parallel. Each M M U chip contains 1280 bits of fast
registers. These first 64 bytes of the register area are then ac- on-chip lookup RAM. ThiS RAM IS accessible 10 bits at a
cessed as 32 pairs of bytes with each pair describing the time for mapping purposes, and as 2 and 8 bits at a time
logical-to-physical mapping for one 2K page. Registers 0 and when the Operating System OS IS changing the contents of
1 contain the page number for Igoical addresses the RAM. In addition to the lookup RAM, each MMU con-
$000Q-$07FF, register 2 and 3 control logical addresses tains a separate copy of the Access Key, Operate Key, Fuse
$08QO-$OFFF, etc. Register, Key Value Register, and S-bit. A CPU write to the
Each MMU has a 3-bit register called the KEY VALUE Access, Operate, or Fuse Register causes all registers on all
REGISTER. This register determines the range of task MMUs to be updated. In contrast, the lookup RAM for each
numbers an MMU controls. The top three bits of the Operate chip is updated only when the top three bits of the Access
Key must match the Key Value Register for that task to be Key match the Key Value Register for that chip. DUring map-
active. Similarly, the Key Value Register must match the top ping operations, each MMU compares the value In Its
three bits of the Access Key to change or view registers #0 Operate Key (top three bits) with Its Key Value Register and
through #$3F. Each MMU must receive a unique key value responds only If a match is found. Similarly, when the pro-
when the system is initialized to guarantee that no two cessor reads the RAM, each MMU compares Its Key value
MMUs control the same range of tasks. To be able to write with the Access Key (Figure 6).
to each MMU's Key Value Register separately, an external

•
decoder must be provided. ThiS decode function can be REGISTER SELECT TRUTH TABLE
derived from address lines AO, A 1 and A2 uSing a 3-to-8 line .Table 1 shows how the M M U registers are accessed by
decoder. Writing to locations $40-$47 Will cause the Key the processor It IS assumed that the current task IS zero and
Value of the MMU to be updated only if the KVA Input IS that the processor address Il'nes A 11-A 15 are all ones. If the
low. In systems uSing a single MMU, the KVA Input may be S-blt IS not set, the registers are stili readable, but cannot be
wired low. modified

TABLE' - REGISTER SELECT TRUTH TABLE

RA R/W KVA RS6 RS5 RS4 RS3 RS2 RS' RSO register addressed

, X X X X X X X X X none

0 X 1 ,, 0 0 0 X X X none
0
0
1
0
0
0 , 0
0
0
0
0
0
X
X
X
X
X
X
read Key Value Register
write Key Value Register

0 X X 0 n n n n n n byte nnnnnn of MMU RAM INote 11

0 0 X ,, 0 0
,
1 0 0
,
0 none I Note 21
0
0
0
0
X
X , 0
0
0
0 1
0
0
0
1
,
0
write
wnte
Fuse Register
Access Key
0 0 X 1 0 0 1 0 1 wnte Operate Key

0
0 ,
1 X
X
1
1
0
0
0
0
1
1
0
0
0
0
0
1
read
read
S-blt INote 31
Fuse Register (Note 3)
0 1 X 1 0 0 1 0 1 0 read Access Key INote 31
0 1 X 1 0 0 1 0 1 1 read Operate Key INote 31

0 X X 1 0 0 1 1 X X none
0 X X 1 0 1 X X X X none
0 X X 1 1 X X X X X none

Notes
1 The MMU RAM IS accessible only If the Key Value Register IS equal to the top 3 bits of the Access Key Register The lower two bits of the
Access Key Register then determines which task IS to be accessed (R IWl
2 The S-bit IS read-only
3 The S-blt, Fuse, Access or Operate registers are readable only If the Key Value Register IS equal to the top 3 bits of the Access Key Register
ThiS Insures that only one MMU Will respond to a read request of these locations

4·362
MC6829- MC68A29- MC68B29

FIGURE 6 - MMU SYSTEMS CONFIGURATION

Up to 86829s
Task 28-31 In Parallel

•••
Task 8-11

BA r------,J~ 6829

BSf------~
Task 0
PA20
Ef------~
Task 1
Q~----+l

MC6809/MC6809E I----...J Task 2

System Bus

Al0
AO
Task 0= Operating System Task
Task 1 = DMA Task
Tasks 2-31 = User Tasks
PAO

•
System
Memory

MC6809
MC6809E
DO-D7 VMA

BA. BS. E. Q
R/W

DO-Dl
R/Vi

4-363
 MC6829-MC68A29-MC68B29

REGISTER DESCRIPTION counter IS decremented once. When the counter reaches

zero, the task number In the Operate Key will be the active
System Bit IS-bit) - Read-only bit that must beset IS= 1) task, mapping logical to phYSical address The value written
to write MMU registers. Reset and Interrupts set the S-bit. onto the Fuse Register must be the number of cycles It takes
Refer to Fuse Register for clearing the S-blt. to transfer program control from the store to Fuse Register
Instruction. It IS the responsibility of the Operating System
Operate Key - S-blt R/iN register that contains the cur- (task #0) to make sure the processor Will execute code from
rent task number The operate key retaons Its value until ex- the new task properly by changong the Program Counter the
pliCitly changed DUring DMA transfers, the MMU overndes same cycle that the Fuse Register reaches zero Isee follow-
the value on the operate key and forces task #1 to be the ac- Ing example)
tive task When the S-bit IS set, the operate key is also over-
ridden, and task #fJ IS forced to be the active key Change from Talk 10 to Taak n
LDA In
Key Value - 3-bit R/W register that contains the range of STA OPERATE
tasks an M M U controls The Key Value Register must match LDA 14
the t~hree bits of the Operate Key for a task to be active. STA FUSE
The KVA Signal must be low for an access of thiS register. JMP $XXXX

Cycle by tv'vnta 14
Access Key - S-blt R/W register that contains the task Cycle to Fuse Address Address Task N
number of a task to be Viewed or changed ThiS register re- Operation Register JMP High Low \iMA Opcode
taons ItS value until expliCitly changed Fuse Register 0 4 3 2 t 0

•
C'Ontents
Register #fJ to #3F - 64 bytes accessed as 32 pairs of
bytes With each pair descrlbong the logical to phYSical mapp- Refer to Section MMU in a MC6EKJ9 System for Fuse
Ing for one 2K page. Refer to Figure 5. Register use In returning from an Interrupt

Fuse Register - 3-blt count down register used to change

from task #0 to a user task When a write to thiS register IS MMU INITIALIZATION PROCEDURE
detected, the valuE' written IS loaded onto the counter and It
beginS to decrement by one for every processor cycle When The follOWing steps should be followed to Initialize a multi-
the counter underflows, the S-blt IS cleared and the next pro- ple MMU system IRefer to Hardware/Programming Con-
cessor cycle Will be mapped uSing the task number In the Siderations, Programmong Examples section I
operate key lOut of Reset, all MMUs are driVing the address lines,
PA 11 to PA20, high ThiS reqUires the Initialization
RESET OPERATION program to be located In thiS 2K byte page of phYSical
memory Each M M U must be deselected by writing a
When reset, the M M U performs the follOWing operations unique value to ItS Key Value Register except for the
MMU that Will run task #fJ (MMUOI MMUO's Key
1 The Key Value Register IS cleared,
Value Register must not be written to until task #0
2 The Fuse Register IS disabled, registers $00 to $3F are programmed, speCifYing the
3 The System bit (S-bltl IS set, logical to phYSical mapping of memory In addition, If
4 The Operate Key Register IS cleared, MMUO Key Value Register IS also initialized With a
5 The Access Key Register IS cleared, non-zero value at thiS time the entire memory space IS
6 An Internal reset flag IS set deselected and the operatong system Itask #01 cannot
be accessed I Example 11
Reset causes the MC6829 to automatically SWitch the
memory map to task #0 An Internal flag IS set causing all bus 2 Only one MMU IS now drlvong the address bus Task
cycles to access phYSical addresses $1 FF800-$lFFFFF IPAll #0 memory pages 12K per pagel must be assigned by
to PA20 all high, page $3FFI ThiS flag IS cleared when the writing the corresponding values onto registers $00 to
Key Value Register IS first written While the Internal reset $3F (Example 21
flag IS set, each MMU In the system Will be actively driVing 3 The Key Value Register must be written to MMUO's
the address bus An orderly start up procedure must assign key value to allow initialization of all other tasks by
each MMU a key value before Individual task allocations are removal of automatic mapping of PAll to PA20 high
made IExample 21
4 'At thiS time, each MMU has a unique key value, Task
#0 has a speCified memory map, and Task #fJ IS
FUSE REGISTER OPERATION operating Tasks can now be started by writing the
task number to be speCified In the Access Key
The Fuse Register IS a 3-blt register used to SWitch from Register, wrltong registers $00 to $3F to the memory
task #0 to any other task A wnte to thiS register causes an map desired, loadong the program Into memory and
Internal 3-blt counter to be loaded With the data On each causing a task SWitch by a correct use of the Fuse
successive valid I non-DMAI processor cycle the Internal Register

4-364
MC6829-MC68A29-MC68B29

INTERRUPTS/MAP SWITCHING The MMU uses these two signals directly from the pro-
cessor to determine what action to take for every bus cycle.
The MC6829 monttors the Bus Available (BA) and Bus The MMU, unhke other M6800 peripherals, Introduces an
Status (BS) lines from the processor to determine what type additIOnal delay (tMAD) In the system configuratIOn as it ac-
of bus operation IS occurring When an Interrupt IS detected, cepts address signals from the MPU and maps the MC6809
the current task IS overridden by Task #0 The map sWitch logical address to the system physical address When a
occurs dUring the processor vector fetch (BA=O, BS= 1) so system IS constructed this additional delay must be con-
that Task #0 supphes the Interrupt vector address Detecting Sidered
an Interrupt also sets the S-bit within the MMU allowing The system clock frequency IS determmed by these ad-
Task #0 to be the operating task while the Interrupt IS ser- dress timing delays. Figure 7 shows this data. The System
viced. Cycle time may be determined by adding
1 the MPU E to a rise delay tAVO (max)
2 the MPU address vahd to a rise to tAO (min)
DMA OPERATION
3 the MMU mapping delay tMAD (max)
For a DMA transfer, the memory map IS sWitched to Task 4 the system decode and buffer time tB (thiS IS the delay
#1 This allows transfers of up to 64K bytes without pro- due to bus buffers and decoding circuitry)
cessor Intervention and without interfering with any other 5 the address setup time reqUired by peripherals tAS
task (An external DMAIVMA signal should be Included In (note the setup time IS reqUired for the peripheral to
the decode CirCUitry for the RA Input to prevent dead bus determine If It IS selected as well as deselected dUring
cycles from affecting the MMU) At the end of the DMA every bus cycle)

•
transfer, the MC6829 returns to the task being used before 6 the MPU pulse Width high tPWEH
the transfer began (refer to Programming Considerations) NOTE
This equation must be satisfied
MMU IN A MC6809 SYSTEM tPWEL'" tAVO - tAO + tMAD+ tB+tAS

The MC6829 IS deSigned to work directly With the MC6809

processor Other 8-blt microcomputers may also use the DMA OPERATION - By decodmg the bus grant signal
MMU by generating the appropriate Inputs to the MMU The (BA= 1, BS= 1), the MMU Will automatically sWitch to Task
crUCial area for interfacing the computer to the MMU IS the #1. Even when the MC6809 occasionally steals back a cycle
deSign of the map sWitching hardware to refresh ItS mternal buses, this IS reflected by a change m
For the MC6809, the BA and BS signals are extremely the bus grant signal which causes the map to temporanly
useful for this function Decoding these two signals provides sWitch back to the normal running mode
the follOWing information Note that the bus grant status IS Identical to the Halt status
~ BS MC6809 State and IS thus mdlstmgUlshable from a HALT ThiS should not
o 0 Normal IrunOlngl mode cause a problem Since haltmg the processor Will Simply cause
o 1 Interrupt Acknowledge IIACKI the MMU to sWitch to Task #1 When the MC6809 starts to
o SYNC Acknowledge run agam, the status Imes Will change and cause the MMU to
1 HALT or Bus Grant sWitch to the proper map

FIGURE 7 - ADDRESS DELAY

~------tPWEL0~------J"i

tAO IS a MPU specIfication, refer to the

MC6809 Data Sheet for thiS value

4-365
 MC682geMC68A29-MC68B29

CHANGING TASK TO OPERATING SYSTEM (OS) - may be masked with external hardware during IRO opera-
The OS map (Task 10) IS automatically selected to service all tions.
interrupts. The Interrupt Acknowledge (lACK; BA=O, A typical interrupt service routine beginS like this:
BS = 1) signal is used to determine when an interrupt vector
ORCC I'+F
is being fetched. The map is sWitched at this time in order to STS SAVESP
supply the processor with an Interrupt vector from the OS LOS OSSP
address space, not the user's. At the time lACK is asserted,
all of the registers have been stacked for the interrupt in the
user's address map. This means that the only Information RETURNING FROM THE OS TO TASK N - The OS must
the OS needs to save concerning the running process IS ItS execute an RTI Instruction to get the processor to reload the
stack pointer. All other Information about the task is saved user registers. The map switch must occur after the opcode
on the user's stack and in the MMU registers. The map for the RTI IS fetched and before the first register is pulled
sWitch IS latched since lACK will only be present for two from the stack. Prior to the RTI, the OS must reload the
machine cycles, yet the OS must retain control until the In- stack pOinter from the one that corresponds to the task
terrupt IS serviced. This latched information is kept In a flag about to run. There must be no Interrupts from the time the
register called the S-bit. This bit is set on any lACK and re- stack pOinter is reloaded until the RTI is executed. The signal
mains set until cleared by software. The first thing the OS to the MMU that the map should be returned to the user task
must do is save the interrupted task's stack pOinter in a table is noted by a write to a 3-bit down counter called the FUSE

I
and load the stack pointer with the current top of stack In the REGISTER. When a write to thiS register IS detected, the
OS map. ThiS IS a critical section of code and must not be in- value written IS loaded into the counter and It begins to
terrupted. For this reason, an MMU system cannot accept decrement by one for every processor cycle. When the
two Interrupts In a row. The first interrupt causes the map to counter under flows, the S-bit is cleared and the next pro-
SWitch to task zero. The second Interrupt would stack the cessor cycle Will be mapped uSing the task number In the
machine state at the wrong address In the operating system Operate Key. For most systems, a 1 would be written to the
As a consequence of thiS, Non-Maskable Interrupts (NMIl Fuse Register immediately before the RTI opcode is ex-
must be forbidden In multi-tasking systems since an NMIIS ecuted. Note that DMA operations are still possible Within
possible at any time (even dUring another Interrupt). Similar- thiS critical section. The Fuse Register counts only non-DMA
ly, normal Interrupts (IRQ) do not set the Fast Interrupt cycles after the write to the Fuse Register In order to be sure
(FIRQ), bit F of the status register, in the processor and, of when to sWitch the map. Bus dead cycles are also exclud-
thus, potentially allow another Interrupt before the processor ed when clocking the Fuse Register. Thus, the Fuse Register
has a chance to sWitch stack pOinters. Simple extarnal hard- IS inhibited from counting whenever BA is high, and for the
ware can be used to disable FIRO when IRO IS pending. cycle after BA transitions from high to low. The common ex-
Unlike the NMI input, the FIRO Input IS level sensitive and It pOint for all OS functions looks something like this:

EXIT LOA TASK GET NEXT TASK TO RUN

STA OPERAT AND PLACE IT IN THE OPERATE KEY
STS OSSP SAVE CURRENT STACK POINTER
ORCC IF+I SET F AND I (ENTER CRITICAL SECTION)
LOS SAVESP RESTORE USER'S STACK POINTER
LOA I' CAUSE MAP SWITCH' CYCLE AFTER
STA FUSE WRITE TO FUSE REGISTER
RTI RETURN TO USER TASK

MAP SWITCH OCCURS, USER TASK RESUMES

4-366
 USING THE MC6Im the S-blt and allows the user process to continue By supply-
Ing a source of periodic Interrupts, the as can regain control
When uSing a MC6800 processor external logic is required of the processor and reschedule running processes.
to determine when to sWitch maps. The MMU is controlled Operating system requests for pnvileged operations by
by ItS BA, BS inputs, the S-bit and the Operate Key. For ex- running tasks are ideally handled using the SWI instruction.
ample, deceding any references to the Interrupt vectors and ThiS causes a map sWitch to task zero (lACK IS asserted on
generating lACK as a result will work as long as each task SWII which then processes the request and eventually
references these locations only when the processor IS fetch- returns control to the requesting task. Note that SWI sets
Ing an Interrupt vector Another possibility IS to monitor the the I and F bits dunng execution of the instruction so that
processor R/W line For the MC6800, the only time seven when the as IS entered, the critical section of saving the
writes occur in a row IS dUring an Interrupt sequence. Thus user task pOinter and reloadmg the as stack pOinter can be
the external logic that generates BA and B S must walt until It safely executed. Note that SWI2 and SWI3 do not have this
sees the seven writes and then assert lACK for the next two property and therefore require special handling. To safely
cycles. use SWI2 or SWI3, the programmer must expliCitly mask
A MC6800 processor Interface to the MMU must also in- hardware interrupts.
clude logic to generate the Q bus signal.
ORCC #I+F DISABLE INTERRUPTS
SWI2/3 CALL OS
HARDWARE/PROGRAMMING CONSIDERATIONS
MANAGING NON-EXISTENT MEMORY ACCESSES
The following sections contain examples and suggestions Memory accesses to non-existent memory requires careful
on how to apply the MMU In a system

MEMORY PROTECTION - The MMU can provide

memory protection on a per page basIs by defining the high
order physical address line (P A201 as a write access line If
write protection IS desired, this signal can be gated with the
consideration. Once an Instruction has begun execution,
there IS no way to stop It from completing. Thus, an instruc-
tion may reference a non-ex',stent memory location, or an In-
terrupt may cause the machine state to be stacked Into non-
eXistent memory. Once thiS has occurred, there IS not always
enough Information available to backtrack the last instruc-
II
read/write line, from the processor, to generate a disable tion
signal. This can be used to inhibit the memory chip select One solution to thiS problem IS a hardware FIFO When a
logic or generate an Interrupt to signal a violation of a write task IS initialized, a certain number of pages will be assigned
protected area. The write protect line can also be combined from available memory For example, a ROM program could
with the DMAIYMA logic that IS necessary In systems uSing be placed In a task's map along with RAM for stack and
DMA. In this case, writes to protected memory would ap- variable data areas. The remaining pages In the task's map
pear as dead cycles to the main memory. Note that the are unassigned and references to these unassigned areas re-
deslgntlon of the write protect line is purely arbitrary The qUire special handling. These gaps In the memory map of a
MMU Simply combines the Incoming address with the cur- task may be filled by constructing a "FIFO page" that returns
rent task number to determine a 10-blt result If no write pro- a known value when read Izerol and when written saves the
tection IS needed, PA20 can be used as a 21st address line, Iloglcall address and the data wntten to It If at any time the
giVing a total addressing range of 2 Megabyte This scheme FIFO IS not empty, the FIFO causes an Interrupt althe end of
can be reversed If desired and additional output lines from the current instruction The processor then examines the
the MMU can be used to specify more attributes of the contents of the FI Fa and allocates real pages where there
phYSical pages at the expense of reducing the number of were none before The data In the FIFO IS then placed In real
pages In phYSical memory memory and the task may resume execution Thus, the pro-
gram IS stopped at the end of the Instruction that causes a
MANAGING INTERRUPTS - An Interrupt causes the page fault, and all writes to non-exlstem memory are cap-
processor to suspend the current running task and perform a tured In the FI Fa
service routine for the interrupting device. User programs The maximum number of new pages that may be reqUIred
should not have to handle Interrupts directly Thus on inter- after any page fault IS four. Consider the follOWing instruc-
rupts, the MMU (the operating system OSI must sWitch tion sequence A task has Just started running and has only
from the current map to task 0 so that It can handle the inter- one page allocated to It 1$0000-$1 FFFI The program to be
rupt !The as may of course elect to pass the work of handl- executed IS as follows
Ing a specific Interrupt to a task that IS expecting It I The map
sWitching IS latched (indicated by the S-bitl so that the pro- ORG $0000 PROGRAM START ADDRESS
cessor has as much time as It needs to service the Interrupt LDS #$8000 INITIALIZE STACK
LDX #$3FFF POINT TO DATA AREA
After the Interrupt has been processed, the as can then look
LDD #$1234
at the current process prlontles and determine the next pro- STD .X INITIALIZE VARIABLE
cess to run If, after the Interrupt serVice, the task that was
running before the Interrupt IS to continue to run, the as Execution then proceeds as follows Upon executing the
causes the map to sWitch back to that task. If, however, fourth instruction, two bytes are wntten, one at location
another task is to start running, the as can Simply write the $3FFF and the other at $4000 Since neither of these two
new task number Into the Operate Key Register and then pages actually eXist, the FIFO catches the address and data
cause the map sWitch. Returning to the normal map clears written and pulls the IRQ line to signal a page fault. At the

4-367
 MC6829- MC68A29- MC68B29

end of the STD instruction, the processor will stack the stack push, the FIFO Interrupt would catch the Informallon
machine registers which causes two further page faults Since and the operating system would then allocate memory. If the
the stacking operation writes data to locations $7FF5-$8000 task never used thiS area, It would remain unallocated and
The FI FO must also catch these references since they con- thus be available for other uses Note that thiS approach pro-
tain the machine state at the time of the original Interrupt. Vides for dynamic memory expansion of growing data areas
When task zero gains control, the FI FO data must be cleared If the size of the static data areas IS known at load-time, then
before any attempt is made to reference the task's memory memory can be allocated to a task as needed. Heap manage-
map. If there are no available pages, the task may be made ment (such as for an editor buffer) can be handled by task
inactive until sufficient space eXists to allow the program to resident memory allocation routines which make operating
continue. system calls to obtain more heap space
The maximum number of bytes that may be written to The FIFO scheme does not Implement a demand paging
non-existent memory before task zero gains control IS 24 system It IS assumed that once a page has been assigned to
This occurs when the task pushes all of liS registers onto the a task the page remains assigned until the task ends execu-
stack when the stack POints to an unln,t,al,zed page Pushing tion or possibly gives It back (via a system call) to the
all registers reqUires 12 bytes. At the end of the instruction, operating system
an Interrupt Will be generated which again pushes the entire
machine state. Thus, the FIFO must be 24 bits Wide 116 ad-
dress + 8 data hnes) and 24 words deep DMAIVMA CIRCUIT
The primary benefit of thiS scheme IS to allow the MC6809

•
stack to grow dynamically. When a task starts to run, the The following CirCUit, Figure 8 , IS suggested to keep the
stack could be Initialized to $FFFF with no real memo I y at MC6829 deselected dUring dead bus cycles of DMA ThiS Cir-
that location When the task did ItS first subroutine call or CUit Will also work In a non-MMU system

FIGURE 8 - M6809 DMAIVMA LOGIC

RESET-------------------,

CLR

o
74LS74
BA-----.r--~D Of-------\

COMMON MMU EQUATES

Here IS a list of assembler equates that are used In the follOWing examples.

MMU EOU $F800 START OF MMU REGISTERS liN TASK 01

MMUO EQU MMU+ $40 FIRST MMU'S KEY VALUE REGISTER
MMU7 EQU MMU+ $47 LAST MMU'S KEY VALUE REGISTER
SBIT EOU MMU+$48 SYSTEM/USER FLAG BIT
FUSE EOU MMU+$49 MAP SWITCH COUNT-DOWN REGISTER
ACCESS EOU MMU+$4A ACCESS.KEY
OPERAT EOU MMU+ $4B OPERATE KEY
NTASK EOU 32 NUMBER OF TASKS IN SYSTEM
NPAGE EOU 32 NUMBER OF PAGES PER TASK
MAXPGE EOU $400 MAXIMUM NUMBER OF PAGES IN SYSTEM
PSIZE EOU 2048 NUMBER OF BYTES IN A PAGE

4·368
MC6829-MC68A29-MC68829

Programming Examples
Example #1 -
Write a program to initialize all MMU Key Value Registers except MMUO.

RESET ENTRY POINT FOR MMU SYSTEM

LOX IMMU7+1 POINT TO LAST MMU KEY VALUE REGISTER +1

LOA #7 INITIALIZE VALUE
KVINIT STA ,-x
DECA
BNE KVINIT

CONTINUE INITIALIZATION

At this point, each MMU will have a unique key value. Note that the Key Value Register for MMUO has not yet been
written so that page $3FF IS stili on the physical address bus. The difference IS that now only one MMU IS driVing the
address bus.

Example #2 -

II
Write an Initialization program that sets up the pages of Task #0 so that an address $XXXX In Task #0 corresponds
to phYSical address $1 FXXXX

FROM KEY VALUE INITIALIZATION

NOW INITIALIZE IDENTITY MAP FOR TASK 0

CLR ACCESS TALK TO TASK 0 IALREADY ZERO ANYWAYI

LOX IMMU
LDD I$3EO LAST PAGE - 32
MOINIT STD ,X+ +
INCB QUIT WHEN 0 = $200
BNE MOl NIT
CLR MMUO LET MMU #0 GO
JMP EXBUG TRANSFER TO MONITOR IEXBUGOBI

Example #3 -
Give task #9 phYSical page #88 and place It In the task's address space so that #9 refers to thiS page With addresses
$1000-$17FF. Write protect thiS page for thiS task. (The write protect bit IS defined as PA20 of the MMU.)

PROTEC EQU $200 WRITE PROTECT BIT POSITION IPA201

LOA #9 SELECT TASK #9 FOR

STA ACCESS MODIFICATION
LOX 188+ PROTEC WRITE PHYSICAL PAGE INTO
STX MMU+4 THE APPROPRIATE REGISTER

Example #4-
Write a subroutine that reads a byte from any task On entry, the A register contains the task number, and the X
register contains the address of that task to read Assume that the as
task has ItS third page free for thiS use. The
byte that IS read IS returned In A.

FPAGE EQU $1000 DEDICATED FREE PAGE

FREE EQU 4 OFFSET INTO MMU OF FPAGE

FUBYTE - FETCH USER BYTE

FUBYTE LBSR GETPAGE POINT TO PAGE

LOA ,x PICKUP BYTE
RTS

4-369
 MC682-MC68A2geMC68829

Example #5 -
Write a subroutine that writes a byte to any task, On entry the A register contains the task number and the X
register contains the address of that task to read, The B register contains the byte to place In the task's memory,
Assume that the as
task has its third page free for this use,

SUBYTE - SET USER BYTE

SUBYTE LBSR GETPAGE PLACE USER PAGE IN FPAGE

STB ,x
RTS

Example #6 -
Write a subroutine to be given a task number and memory address that returns a pOinter to that byte of the named
task, On entry, the A register contains the task number and the X register contains the task address
• GET PAGE - POINT TO USER BYTE
.. Given a task number In A and a task address In X,
• return With X pOinting to that byte In task 0
.. This subroutine assumes that task 0 has a free
• page IFPAGEI that It uses to map a page of the
.. specified task Into task D's map

I GETPAGE PSHS
STA
TFR
ASRA
D, Y
ACCESS
X, D
SAVE SOME REGISTERS
SETUP WINDOW TO TASK
MOVE POINTER INTO ACCUMULATOR
FIND PHYSICAL PAGE #
ASRA
ANDA #%00111110 MASK ALL BUT PAGE #
LDY #MMU
LDY A, Y PICKUP PAGE
CLR ACCESS NOW TALK TO OS MAP
STY MMU+ FREE 'FREE' OS PAGE
TFR X, D NOW POINT TO OFFSET
ANDA #%111 MASK HIGH BITS OF ADDRESS
LDX #FPAGE POINT TO PAGE START
LEAX D,X ADD OFFSET
PULS D, Y, PC RESTORE AND RETURN

The above method of fetching bytes from other tasks IS appropriate where only a few bytes of memory are to be
transferred, When larger amounts of memory are to be moved, a more general subroutine can be written that
transfers up to 2K bytes (one page) before the MMU registers need to be changed,

4·370
 MC683S
® MOTOROLA
(1.0 MHz)
MC68l3S MC68B3S
(1.5 MHz) (2.0 MHz)

Advance InforIllation
MOS
(HIGH-DENSITY, N-CHANNEL,
CRT CONTROLLER (CRTC) SILICON-GATE DEPLETION LOADI

The MC6835 IS a ROM based CRT Controller which Interfaces an MASK PROGRAMMED
MPU system to a raster scan CRT display. It IS Intended for use In MPU CRTC CONTROLLER
based controllers for CRT terminals In stand-alone or cluster configura- (CRTC)
tions The M C6835 supports two selectable mask programmed screen
formats uSing the program select Input (PROm.
The CRTC IS optimized for the hardware/software balance required
for maximum fleXibility All keyboard functions, reads, Writes, cursor
movements, scrolling, and editing are under processor control The
mask programmed registers of the CRTC are programmed to control
the Video format and timing
• Cost Effective ROM Based CRTC Which· Supports Two Screen
Formats
• Useful In Monochrome or Color CRT Applications
• Applications Include "Glass-Teletype," Smart, Programmable, Intel-

•
ligent CRT Terminals, Video Games, Information Displays
• Alphanumeric, Semlgraphlc, and Full GraphiC Capability
• Timing May Be Generated for Almost Any Alphanumeric Screen
Format, e g ,SOx 24, 72x 64, 132x 20
• Single + 5 Volt Supply
• M6800 Compatible Bus Interface
• TTL-Compatible Inputs and Outputs
• Start Address Register ProVides Hardware Scroll (By Page, Line, or
Character)
• Programmable Cursor Register Allows Control of Cursor Position
• Refresh (Screen) Memory May Be Multiplexed Between the CRTC FIGURE 1 - PIN ASSIGNMENTS
and the MPU Thus Removing the ReqUirements for line Buffers or
GND \(S
External DMA Devices
RESET HS
• Mask Programmable Interlace or Non-Interlace Scan Modes
• 14-Blt Refresh Address Allows Up to 16K of Refresh Memory PROG RAO
for Use In Character or Semlgraphlc Displays RAl
• 5-Blt Row Address Allows up to 32 Scan-Line Character Blocks MAl RA2
• By UtiliZing Both the Refresh Addresses and the Row Addresses, MA2 RA3
a 512K Address Space IS Available for Use In GraphiCS Systems
MA3 7 RA4
• Refresh Addresses are ProVided DUring Retrace, AllOWing the CRTC
to proVide Row Addresses to Refresh Dynamic RAMs MA4 8 DO
• Pin Compatible with the MC6845 The MC6845 May Be Used as a MA5 Dl
Prototype Part to Emulate the MC6835 MA6 D2
MA7 11 D3
MAS D4
MAXIMUM RATINGS
MAg D5
Rating Symbol Value Unit
Supply Voltage VCC· -03to +70 V MAlO D6
Input Voltage V In • -03to+70 V MAll D7
Operating Temperature Range MA12 16 CS
MC6835, MC68A35, MC68S35 TA o to + 70 °c
MC6835C, MC68A35C, MC68S35C -50 to +85 MA13 17 RS

Storage Temperature Range T5tg -55 to +150 °c DE 18 E

CURSOR 19 R/W
·W,th respect to GND (VSSI
Vee 20 eLK

4-371
 MC6835

FIGURE 2 - TYPICAL CRT CONTROLLER APPLICATION

~--'-----------~------------------------------------~AB
L ____J--II---';:--I----------------"l~--. . DB Pnmary Bus

Cursor,
Display
Enable

Row Addresses

HS VS

•
THERMAL CHARACTERISTICS
Characteristic Symbol Value Rating
Thermal Resistance ThiS device contams circUitry to protect the in-
puts against damage due to high static voltages
PlastiC 100
8JA "C/W Of electnc fields, however, It IS adVised that nor-
Cerdlp 60
mal precautions be taken to avoid application of
Ceramic 50
any voltage higher than maximum rated voltages
to thiS hlgh~lmpedance ClfCUlt For proper opera-
tion It IS recommended that Vin and V out be con-
RECOMMENDED OPERATING CONDITIONS stramed to the range V SS! ~ V ln or Vout) S Vee
Characteristic Symbol Min Typ Max Unit Reliability of operation IS enhanced If unused in-
Supply Voltage Vec 475 50 525 V puts are tied to an appropriate logic voltage level
Input Low Voltage -03 - 08 V Ie g ,either VSS or VCe!
VIL
Input High Voltage VIH 20 - Vec V

POWER CONSIDERATIONS

The average chip-Junction temperature, T J, In 'c can be obtained from

T J = TA + IPooOJAI III
Where
TA'" Ambient Temperature, "C
0JA'" Package Thermal ReSistance, Junctlon-to-Amblent, 'C/W
Po = PINT + PPORT
PINT=ICCxVCc, Watts - Chip Internal Power
PPORT= Port Power O,ss,patlon, Watts - User Oetermlned
For most applications PpORT<C PINT and can be neglected PPORT may become Significant If the deVice IS configured to
drive Oarllngton bases or sink LEO loads
An approximate relationship between Po and T J Ilf PPORT IS neglected I IS
PO= K+ IT J + 273'CI 121
Solving equations 1 and 2 for K gives
K = PO"IT A + 273°CI + OJA o P0 2 131
Where K IS a constant pertaining to the particular part K can be determined from equation 3 by measuring Po lat equilibrium I
for a known T A USing thiS value of K the values of Po and T J can be obtained by solving equations 111 and 121 Iteratively for any
value of T A.

4-372
MC6835

DC ELECTRICAL CHARACTERISTICS IVCC=5 0 Vdc ± 5% VSS=O TA=O to 70'C unless otherwise noted) IAeference Figures 3-5)
Characteristic Symbol Min Typ Max Unit
Input High Voltage VIH 2.0 - VCC V
Input Low Voltage VIL -03 - 0.8 V
Input Leakage Current lin - 0.1 2.5 ~A
Three-State IVCC-5.25 V) IV In -O.4 to 24 V) ITSI -10 - 10 ~A
Output High Voltage
II10ad = - 205 ~A) 00-07 VOH 2.4 3.0 - V
IILoad = -100 ~M Other Outputs 2.4 3.0 -
Output Low Voltage Ilload - 1 6 mAl VOL - 0.3 04 V
Internal Power DIssipation IMeasured at T A - TU Po - 600 750 mW
Input Capacitance 00-07 - - 125
C,n pF
All Others - - 10
Output Capacitance All Outputs Cout - - 10 pF

BUS TIMING CHARACTERISTICS IAeference Figures 3 and 41

Ident. MC6835 MC68A35 MC68B35
Characteristics Symbol Unit
Number Min Max Min Max Min Max
1 Cycle Time tcyc 10 10 067 10 05 10 ~s

•
2 Pulse Width, E Low PWEL 430 9500 280 9500 210 9500 ns
3 Pulse Width, E High PWEH 450 9500 280 9500 220 9500 ns
4 Clock Transition Time tr,tf - 25 - 25 - 20 ns
9 Address Hold Time lAS) tAH 10 - 10 - 10 - ns
13 AS Setup Before E tAS 80 - 60 - 40 - ns
14 R/W and CS Setup Before E tcs 80 - 60 - 40 - ns
15 Hold Time for A/W and "C'S" tCH 10 - 10 - 10 - ns
18 Peripheral Aead Data Hold Time Provided tDDR 20 50" 20 50" 20 50" ns
21 Wnte Data Hold Time ReqUired tDHW 10 - 10 - 10 - ns
30 Peripheral Output Data Delay tDDR - 290 - 180 0 150 ns
31 Peripheral Input Data Setup tDSW 165 - 80 - 60 ns
*The data bus output buffers are no longer sourcmg or slnkmg current by tOHR max (high Impedance)
FIGURE 3 - MC6835 BUS TIMING

~----------431-------~~

RS

RiwC§

Read Data ====!jt==:~=---------------------~~~~£!~------~------~:=================!jt===)

MPU Write Data
Wnte Data

4·373
 MC6835

CRTC TIMING CHARACTERISTICS ISee Figure 5)

Characteristics Symbol Min Max Unit
M,nimum Clock Pulse Width, low PWCl 160 - ns
M,nimum Clock Pulse Width, High PWCH 200 - ns
Clock Frequency Ic - 25 MHz
Rise and Fall Time lor Clock Input ter.lcf 20 ns
Memory Address Delay Time tMAD - 160 ns
Raster Address Delay Time tRAD - 160 ns
Display Timing Delay Time tOTO - 300 ns
Honzontal Sync Delay Time tHSD - 300 ns
Vertical Sync Delay Time tVSD - 300 ns
Cursor Display Timing Delay Time tCDD - 300 ns

FIGURE 4 - BUS TIMING TEST lOAD

50 V

•
C MMD6150
or EQu!v

C = 130 pF lor 00-07

= 30 pF for MAO-MA 13, RAO-RA4,
DE, HS, VS, and CURSOR
R= 11 kll lor 00-07
= 24 kll for All Other Outputs

FIGURE 5 - CRTC TIMING CHART

PWCH

ClK

RAO-RA4

DE

HS

VS

CURSOR

NOTE Timing measurements are referenced to and from a low voltage of 0 8 volts and a high voltage of 2 0 volts unless otherwise noted

4·374
MC6835

CRTC INTERFACE SYSTEM DESCRIPTION

The MC6835 CRT Controller generates the signals field) starts In the upper left hand corner, the second IOdd
necessary to Interface a digital system to a raster scan CRT field) In the upper center Both fields overlap as shown In
display In this type of display, an electron beam starts In the F,gure 7, thus Interlacing the two fIelds Into a Single frame.
upper left hand corner, moves qUickly across the screen and In order to dIsplay the characters on the CRT screen the
returns. This action IS called a hOrizontal scan After each frames must be continually repeated The data to be
hOrizontal scan the beam IS Incrementally moved down In the dIsplayed IS stored In the Refresh IScreenl memory by the
vertical direction until It has reached the bottom At thiS MPU controlling the data processing system. The data IS
pOint one frame has been displayed, as the beam has made usually Written In ASCII code, so It cannot be directly
many hOrizontal scans and one vertical scan dIsplayed as characters. A Character Generator ROM IS
Two types of raster scanning are used In CRTs, Interlace tYPIcally used to convert the ASCII codes Into the "dot" pat-
and non-Interlace, shown In Figures 6 and 7 Non-interlacing tern for every character
scanning consists of one field per frame The scan lines In The most common method of generating characters IS to
Figure 6 are shown as solId lines and the retrace patterns are create a matrix of "x" dots Icolumns) Wide and "y" dots
Indicated by the dotted lines Increasing the number of lrows) high Each character IS created by selectively fIlling In
frames per second Will decrease the flicker Ordinarily, eIther the dots As "x" and "y" get larger a more detaIled character
a 50 or 60 frame per second refresh rate IS used to minimize may be created Two common dot matrices are 5 x 7 and
beating between the frequency of the CRT hOrizontal 7 x 9 Many variatIons of these standards WIll allow Chinese,
OSCIllator and the power line frequency ThIS prevents the Japanese, or ArabiC letters Instead of English Since

•
displayed data from weaving or sWimming characters reqUIre some space between them, a character
Interlace scanning IS used In broadcast TV and on data block larger than the character IS typically used as shown In
monitors where high densIty or hIgh resolution data must be Figure 8. The figure also shows the corresponding timing
displayed. Two fields, or vertIcal scans are made down the and levels for a Video sIgnal that would generate the
screen for each Single pIcture or frame. The first field IEven characters

FIGURE 6 - RASTER SCAN SYSTEM INON,INTERLACE)

Vertical Scan Period

Vertical Retrace Period

_.31.-_

HOrizontal Scan HOrizontal Retrace

Period Period

FIGURE 7 - RASTER SCAN SYSTEM (INTERLACE)

- - - - Even Number Field IFlrst)

- - - - Odd Number Field ISecond)

4-375
 MC6835

FIGURE 8 - CHARACTER DISPLAY ON THE SCREEN AND VIDEO SIGNAL

One Character
Clock
~
4 6 8

Character
4
} Display

6
One Lme
14 Scan

}""'"~"
Lmes

10

12

14

II First Scan Line r- r-~ I II

Second Scan Line
lfl -- ~1 Jl J1
Referring to Figure 2, the MC6835 CRT controller 2 Processor gets Priority access anytime, but can be
generates the Refresh addresses (MAO-MA13), row ad- synchrOnized by an Interrupt to perform accesses only
dresses (RAO-RA4), and the video timing (vertical sync - dUring hOrizontal and vertical retrace times
VS, hOrizontal sync - HS and display enable - DE) Other 3 Synchronize the processor With memory walt cycles
functions Include an Internal cursor register which generates (states)
a Cursor output when Its contents compare to the current 4 Synchronize the processor to the character rate as
Refresh address. A setect Input, PROG, allows selection of shown In Figure 9 The M6800 processor family works
one of two mask programmed Video formats (e g , for 50 Hz very well In thiS configuration as constant cycle
and 60 Hz compatibility). lengths are present ThiS method proVides no
All timing In the CRTC IS derived from the ClK Input In overhead for the processor as there IS never a conten-
alphanumeric terminals, thiS signal IS the character rate The tion for a memory access All accesses are
Video rate or "dot" clock IS externally divided by high speed transparent
logiC (TTU to generate the ClK signal The high speed logiC FIGURE 9 - TRANSPARENT REFRESH MEMORY
must also generate the timing and control signals necessary CONFIGURATION TIMING USING M6800 FAMILY MPU
for the Shift Register, Latch and MUX Control shown In
Figure 2.
The processor communicates with the CRTC through an
8-btt data bus by writing Into the five user programmable
registers of the MC6835.
The Refresh memory address IS multiplexed between the
processor and the CRTC. Data appears on a secondary bus
separate from the processor's bus. The secondary data bus
concept In no way precludes uSing the Refresh RAM for I I
other purposes. It looks like any other RAM to the processor. : I
A number of approaches are possible for solVing contentIOns ~tcyC = nxtc or tc/m"'r------l..~:
for the Refresh memory. I I
1. Processor always gets priority. (Generally, "hash" oc-
curs as MPU and CRTC clocks are not synchronlzedJ Where m. n are Integers, tc IS character period

4-376
MC6835

PIN DESCRIPTION graphiCS system both the Memory Addresses and the Row
Addresses would be used to scan the Refresh RAM. Both
PROCESSOR INTERFACE the Memory Addresses and the Row Addresses continue to
The CRTC Interfaces to a processor bus on the bIdIrec- run dUring vertical retrace thus allOWing the CRTC to provide
tional data bus (00-07) uSing CS-, RS, E, and R/W for con- the refresh addresses reqUired to refresh dynamiC RAMs.
trol signals.
Refresh Memory Addresses (MAO-MA13) - These 14 out-
Data Bus (00-07) - The bidirectIOnal data lines (00-07) puts are used to refreSh the CRT screen With pages of data
allow data transfers between the Internal CRTC register file located Within a 16K block of refresh memory These outputs
and the processor. Data bus output drivers are hlgh- are capable of driVing one standard TTL load and 30 pF
Impedance buffers which remain In the high-Impedance state
until the processor performs a CRTC read operation Row Addresses (RAO-RA4) - These five outputs from the
Internal Row Address counter are used to address the
Enable (E) - The Enable signal IS a high-Impedance Character Generator ROM. These outputs are capable of
TTl! MOS-compatlble Input which enables the data bus In- driVing one standard TTL load and 30 pF
put/ output buffers and clocks data to and from the CRTe.
ThiS signal IS usually derived from the processor clock The OTHER PINS
hlgh-to-Iow transition IS the active edge Cursor - ThiS TTL-compatible output Indicates a valid
Cursor address to external Video processing logiC It IS an
Chip Select (CS) - The CS line IS an active-low hlgh- active-high Signal
Impedance TTl!MOS-compatlble Input which selects the

•
CRTC to read or write to the Internal register file. ThiS signal Clock (ClK) - The ClK IS a TTl! MOS-compatlble Input
should only be active when there IS a valid stable address be- used to synchronize all CRT functions except for the pro-
Ing decoded from the processor cessor Interface An external dot counter IS used to derive
thiS Signal which IS usually the character rate In an
Register Select (RS) - The RS line IS a high-Impedance alphanumeric CRT The active transition IS hlgh-to-Iow.
TTl! MOS-compatlble Input which selects either the Ad-
dress Register (RS = "0") or one of the Data Registers Program Select (PROG) - ThiS TTL-compatible Input
(RS = "1") of the Internal register file when CS IS low allows selection of one of two sets of mask programmed
Video formats. Set zero IS selected when PROG IS low and
Read/Write (R/W) - The R/W line IS a high-Impedance set one IS selected when PROG IS high
TTl!MOS-compatlble Input which determines whether the
Internal register file gets written or read. A write IS defined as VCC, GND - These Inputs supply + 5 Vdc ± 5% to the
a low level. CRTe.

CRT CONTROL RESET - The RESET Input IS used to reset the CRTC.
The CRTC proVides hOrizontal sync (HS), vertical sync Functionality of RESET differs from that of other M6800
(VS), and display enable (DE) signals. parts liEID must remain low for at least one cycle of the
character clock (ClK) A low level on the RESET Input
NOTE - Care should be exercised when interfaCing to forces the CRTC Into the follOWing state·
CRT mOnitors as many mOnitors claiming to be "TTL com- a. All counters In the CRTC are cleared and the deVice
patible," have transistor Input CirCUitS which reqUire the stops the display operation.
CRTC or TTL deVices buffering signals from the CRTC/vldeo b All the outputs are driven low, except the MAO-MA 13
CirCUitS to exceed the maximum rated drive currents. outputs which are driven to the current value In the
Start Address Register.
Vertical Sync (VS) and Horizontal Sync (HS) - These
c. The control registers of the CRTC are not affected and
TTL-compatible outputs are active-high signals which drive
remain unchanged.
the mOnitor directly or are fed to the Video processing Cir-
cUitry to generate a composite Video signal. The VS signal d. The CRTC resumes the display operation Immediately
determines the vertical position of the displayed text while after the release of RESET.
the HS signal determines the hOrizontal position of the
displayed text.
CRTC DESCRIPTION
Display Enable (DE) - ThiS TTL-compatible output IS an
active-high signal which Indicates the CRTC is proViding ad- The CRTC consists of mask-programmable hOrizontal and
dressing In the active Display Area. vertical timing generators, software-programmable linear ad-
dress register, mask-programmable cursor logiC and control
REFRESH MEMORY/CHARACTER GENERATOR AD- circuitry for InterfaCing to a M6800 family microprocessor
DRESSING bus.
The CRTC provides Memory Addresses (MAO-MA13) to All CRTC timing IS derived from ClK, usually the output of
scan the Refresh RAM. Row Addresses (RAO-RA4) are also an external dot rate counter. CoinCidence (CO) Circuits con-
provided for use with character generator ROMs. In a tinuously compare counter contents to the contents of the

4-377
 MC6835

TABLE 1 - INTERNAL REGISTER ASSIGNMENT

CS RS
43210 ,
Address Register Register
Register Rle
Program
Unit
Read Write
7
Number of Bits
6 5 4 3 2 1 0
1 X X X X X X X - - - - '\ 1,\ '\'\ 1"- '\ 1\1"-
D D X X X X X AA Address Aeglster - No Yes '\ I" "-
AD HOrizontal Total Char No No
A1 Honzontal Displayed Char No No
A2 H Sync Position Char No No
Note 3 A3 Sync Width - No No V V V V H H H H
A4 Vertical Total Char Aow No No '\
A5 V Total Adjust Scan Line No No l"- I" "-
A6 Vertical Displayed Char Aow No No 1"-.
A7 V Sync POSition Char Aaw No No 1"-.
AS Interlace Mode and Skew Note 1 No No C C 0 0 I I
A9 Max Scan Line Address Scan Line No No
I"I" "P
Al0 Cursor Start Scan Line No No 1"-8 INote 21
All Cursor End Scan Line No No 1,\'\ '\
0 1 0 1 1 0 0 A12 Start Address IHI - No Yes 0 0

•
0 1 0 1 1 0 1 A13 Start Address III - No Yes
0 1 0 1 1 1 0 A14 Cursor IHI - No Yes 0 0
0 1 0 1 1 1 1 A15 CUrsor III - No Yes

NOTES
1 The Interlace Control IS shown In Table 2 while Skew Control IS shown In Table 3
2. Bit 5 of the Cursor Start Raster Register IS used to blink period control, and Bit 6 IS used to select blink or non-blink
3 AD-Rll are mask-programmable and are not accessible via the data bus

mask programmable register file, RO-R11 For hOrizontal tim- cursor as indicated by the register contents
Ing generation, comparisons result In The linear Address Generator IS driven by ClK and
1. HOrizontal sync pulse IHS) of a frequency, position locates the relative positions of characters In memory and
and Width determined by the register contents therr positions on the screen Fourteen outputs, MAO-MA 13,
2 HOrizontal Display signal of a frequency, position and are available for addreSSing up to four pages of 4K
duration determined by the register contents characters, eight pages of 2K characters, etc
Five additional wrrte-only registers define the Start Ad-
The hOrizontal counter produces H clock which drives the
dress and cursor position USing the Start Address Register,
Scan line Counter and Vertical Control The contents of the
hardware scrolling through 16K characters IS possible The
Raster Counter are continuously compared to the Max Scan
linear Address Generator repeats the same sequence of ad-
line Address Register A cOincidence resets the Raster
dresses for each scan line of a character row The Start Ad-
Counter and clocks the Vertical Counter.
dress Register and the Cursor Position Register are program-
Comparisons of Vertical Counter contents and Vertical
med by the processor through the data bus, DO-D7 and the
Registers result In
control signals - R/W, C$, RS, and E Refer to Figure 10
1. Vertical sync pulse IVS) of a frequency, position and
Width determined by the register contents.
2. Vertical Display signal of a frequency, POSition, and REGISTER FILE DESCRIPTION
duration determined by the register contents.
The Vertical Control logiC has other functions The MC6835 has 17 control registers of which 12 are mask
programmable The remaining five registers - Address
1. Generate row selects, RAO-RA4, from the Raster
register, Start Address register parr, and Cursor Position
Count for the corresponding Interlace or non-Interlace
register parr - are write-only registers programmed by the
modes
MPU These registers control hOrizontal timing, vertical tim-
2. Extend the number of scan lines In the vertical total by Ing, Interlace operation, row address operation and define
the amount programmed In the Vertical Total Adjust the cursor, cursor address, start address and light pen
Register. register The register addresses and sIZes are shown In
The cursor logiC determines the sIZe and blink rate of the Table 1.

4-378
MC6835

FIGURE 10 - CRTC BLOCK DIAGRAM

Vee GND Prog R/W CS RS E RESET DO-07

elK -I----.,.---t

DE

HS

H
HH-
•
~::::::=f::::=F::::~>[::~~:J~~::==::==::==~~tlr----lr-~CURSOR

RAO-RA4 MAO-MA13

4·379
 MC6835

MASK PROGRAMMABLE REGISTERS RG-Rll decreased the display IS shifted to the right Any B-blt
The twelve mask programmable registers determine the number may be programmed as long as the sum of the con-
display format generated by the MC6835 The PROG Input IS tents of R1, R2, and the lower four bits of R3 are less than
used to select one of two sets of register values the contents of RO
Figure 11 shows the vIsible display area of a tYPical CRT
mOnitor giving the pOint of reference for hOrizontal registers Sync Width Register (R3) - This 8-blt register determines
as the left most displayed character position HOrizontal the Width of the vertical sync (VS) pulse and the hOrizontal
registers are programmed In character clock time Units with sync (HS) pulse Programming the upper four bits for 1-to-15
respect to the reference as shown In Figure 12 The pOint of Will select VS pulse Widths from 1-10-15 scan-line times Pro-
reference for the vertical registers IS the top character POSI- gramming the upper four bits as zeros Will select a VS pulse
tion displayed Vertical registers are programmed In Width of 16 scan line times The HS pulse Width may be pro-
character row times or scan line times as shown In Figure 13 grammed from 1-to-15 character clock periods thus allowing
compatibility with the HS pulse Width speCifications of many
Horizontal Total Register (RO) - This 8-blt register deter- different mOnitors If zeros are written Into the lower four
mines the hOrizontal sync (HS) frequency by defining the HS bits of this register, then no HS IS provided
period In character times It IS the total of the displayed
characters plus the non-displayed character times (retrace) Horizontal Timing Summary (Figure 12) - The difference
minus one between RO and R1 IS the hOrizontal blanking Interval This
Interval in the hOrizontal scan period allows the beam to
Horizontal Displayed Register (R1) - This 8-blt register return (retrace) to the left Side of the screen The retrace time
determines the number of displayed characters per line Any IS determined by the monitor's hOrizontal scan components
8-blt number may be programmed as long as the contents of Retrace time IS less than the hOrizontal blanking Interval A

II RO are greater than the contents of R1

Horizontal Sync Position Register (R2) - This 8-bit

register controls the H S position The hOrizontal sync POSI-
tion defines the hOrizontal sync delay (Front Porch) and the
hOrizontal scan delay (Back Porch) When the programmed
good rule of thumb IS to make the hOrizontal blanking about
20% of the total hOrizontal scanning period for a CRT In In-
expensive TV receivers, the beam overscans the display
screen so that aging 01 parts does not result In underscan-
nlng Because 01 thiS, the retrace time should be about 1/3
the hOrizontal scanning period The honzontal sync delay,
value of this register IS Increased, the display on the CRT H S pulse Width and hOrizontal scan delay are typically pro-
screen IS shifted to the left When the programmed value IS grammed With 1 2 2 ratio

FIGURE 11 - ILLUSTRATION OF THE CRT SCREEN FORMAT

r-I--------Number of Honzontal Total Char INht+ 1)-----------.1

~
l ~{Ir-----Number of Honzontal Displayed Char INhdl------. }Lone

A B C
"C Q)
> c:
~ ~
c:
;::: ~
+ aCo en
:; ~ E
~ >- E HOrizontal
~ a ~ Retrace
6 6 ::!! Penod

Display Penod

Vertical Retrace Penod

Total Scan Line AdJust INadJI-

Note 1 Tlmmg values are descnbed In Table 8

4-380
 s::
i
FIGURE 12 - CRTC HORIZONTAL TIMING

HOrizontal Total (ROI

~ tSI~(Nht+l)Xtc---------------------~1
t::=::;Ii:tc HOrizontal DIsplay (Rl INhd x tc .1_ Honzontal Retrace

ClK ~~~'V"L1"""LJI
1 I I I I I I I I I I ~·I I I ,-- I~ I j r- r
MAO-MA13'*
I

0
1
* * • I I

~
I I I

*==*~ fhd~* Nhd

I I
.I I I I I , I I I
* *
I I

~ tsp~, NhSP, ~ , Nht ~

~
~
....
CD Character # I
I
I 0
I
I- 1
I
I- 2
I
I
I
I
II
- ~ I
I
~ INhd~lll
I

_.
I Nhd
I I
II
. "J
I

I
I
~ INhSP~lNhSpl
I _
I I
II ~
_~ "
,
I
I
I r-...
_~ I
I
I
I
I Nht
I
I

I
I

I I I HS Pulse Width lR31 I

I Honzontal Sync Position (R21 ~N xt ~ I
I Front Porch (Sync Delay) ,- hsw c ~ Back P~h (Scan Delay) I
HSYNCI "" ~
I I
1""'·1 I
Dlspen i ~ '" '" '\.,
-Timing IS shown for first dIsplayed scan row only See Chart In Figure 16 for other rows The initIal MA IS determmed by the contents of Start
Address Register, R12/R13 Timing IS shown for R12/R13~O
Note'- Timing values are described In Table 5

•
 • s:
i
FIGURE 13 - CRTC VERTICAL TIMING

tF = ~ N vt + 1) x tre + Nadj x lsi

Field Time
RAO-RA4 I. Vertical TotallR41 + Vertical Total Adlust IR51 - - - , ..I
I I iii( Vertical Display= Nvd x trclR6) lit 1"1( L -.I Vertical Retrace )tl
ISInterlace tre ~ * ._1 .. .. r:-TSI~
Sync and
Video Mode 0111 !:hi 0111 I ~ I'KJsi 1 0, 1 I 0111
Odd Field IIN s l-lIl
I
INvd -11 x Nhd 11Nsi- 11:
Nsl
IN sl-lIl
Nsl j...QJlL Tadl = Nadl x lsi
Address Continues to Increment INsl-ll 1 Field Adjust Time

MAO-MA 13" 'IT--'-~-V-~-'--I-V---Y--I - - - - - - -

l,tNht*: ~NJ: INV~-lIJ!~d+NtH: I

Character
Row # .
I I
I 0
I I ~ II i
I Nvd
I
1;
II t: N vsp 1, Nvsp I
~ Nvt Nvt + 1
" I I I Vertical ~16xtSI~
~ VSYNC I I Sync Delay Vertical Scan Delay
I \, I
~
(Non-Interlace) Vertical Sync
I ~ertlcal Syn~ Pulse I
I\) VSYNC 1 1 Position I R7I' I I
IE yen FIe Idl I ....~ I"
to. II ~,/
---~~-.r------------------+
-"

VSYNC
:
I 1 I I. I , I
I
•
!§!
2
1-:: '-+-!§!
~_ _ _ _ _ _ _ _ _ _ _ _ _ _- ;
1
IOdd Fleldl
I I ... , " '"
I , I I I I
Display
Enable
rLl-~~~ , __~~_____________~
.. Nht must be an odd number for both Interlace modes
""Initial MA IS determmed by R12/R13 IStart Address Register), which IS zero In thiS timing example
···Nsl must be an odd nu:-nber for Interlace Sync and Video Mode

NOTES
1 Refer to Figure 7 - The Odd Field IS offset y.. hOrizontal scan time
2 Timing values are described In Table 5
MC6835

TABLE 2 - INTERLACE MODE REGISTER TABLE 3 - CURSOR START REGISTER

Bit 1 Bit 0 Mode Bit 6 Bit 5 Cursor Display Mode

0 0 0 0 Non-Blink
Normal Sync Mode (Non-Interlace)
1 0 0 1 Cursor Non-Display
0 1 Interlace Sync Mode 1 0 Blink, 1/16 Field Rate
1 1 Interlace Sync and Video Mode 1 1 Blink, 1/32 Field Rate

FIGURE 14 - INTERLACE CONTROL

Scan Line Address Scan Line Address Scan Line Address

0 I) 0

0 0 1 0
- --0
0 2- 3 - -
8" -1

2- 8 -& -1
4-e --e- -3
0 0
-9-- ~ -2
0 0
-e
0 0 0
- e- -fl
0 0 3 0 0 6 0 0
40 --&- e- -3 --& -e- -7

0
0 0 0 0
0 :-8 e--e -8-
0 0
tt=4 0
--1

•
6 0 0 6
--9
0
5
4 --- --3

0 0 7-8 8 -6 - -5

--9- e- -7 --7
Even Odd Even Odd
Field Field Field Field
al Normal Sync bl Interlace Sync c) Interlace Sync and Video

Vertical Total Register (R41 and Vertical Total Adjust Table 4 desc"bFs operation of the Cursor and DE skew
Register (R5) - The frequency of VS IS determined by both bits Cursor skew IS controlled by bits 6 and 7 of R8 while DE
R4 and R5 The calculated number of character line times IS skew IS controlled by bits 4 and 5
usually an Integer plus a fraction to get exactly a 50 or 60 Hz In the normal sync mode Inon-Interlace) only one field IS
vertical refresh rate The Integer number of character line available as shown In Figures 6 and 14a Each scan line IS
times minus one IS programmed In the 7-blt Vertical Total refreshed at the VS frequency Ie g , 50 or 60 HzI
Register (R4) The fraction of character line times IS pro- Two Interlace modes are available as shown In Figures 7,
grammed In the 5-blt Vertical Total Adjust Register IR51 as a 14b, and 14c The frame time IS divided between even and
number of scan line times. odd alternating fields The hOrizontal and vertical timing rela-
tionship IVS delayed by 112 scan line time) results In the
Vertical Displayed Register (R6) - ThiS 7-blt register displacement of scan lines In the odd field With respect to the
specifies the number of displayed character rows on the CRT even field
screen, and IS programmed In character row times. Any In the Interlace Sync mode the same Information IS painted
number smaller than the contents of R4 may be programmed In both fields as shown In Figure 14b ThiS IS a useful mode
Into R6. for filling In a character to enhance readability
In the Interlace Sync and Video mode alternating lines of
Vertical Sync Position (R7) - ThiS 7-blt register controls the character are displayed In the even field and the odd
the position of vertical sync with respect to the reference It field. ThiS effectively doubles the number of characters that
IS programmed In character row times. The value programm- may be displayed on a CRT montlor of a g.ven bandwidth.
ed In the register IS one less than the number of computed Care must be taken when uSing either Interlace mode to
character line times When the programmed value of thiS aVOid an apparent flicker effect. ThiS flicker effect IS due to
register IS Increased, the display position of the CRT screen the doubling of the refresh period for all scan lines since each
IS shifted up. When the programmed value IS decreased the field IS displayed alternately. Flicker may be minimized With
display position IS shifted down. Any number equal to or less proper monitor des.gn le.g., longer persistence phosphors).
than the vertical total I R4) may be used In addition, there are restrictions on the programming of
the CRTC registers for Interlace operation:
Interlace Mode and Skew Register (RB) - ThiS 6-blt a. The HOrizontal Total Register value, RO, must be odd
register controls the Interlace modes and allows a program- Il.e., an even number of character times)
mable delay of zero to two character clock times for the DE b. For the Interlace Sync and Video mode only, the Ver-
(display enable) and Cursor outputs. Table 2 shows the in- tical Displayed Register IR6) must be even The pro-
terlace modes available to the user. These modes are grammed number, Nvd, must be Y, the actual number
selected using the two low order bits of thiS 6-blt register. reqUIred.

4-383
 MC6835

TABLE 4 - CURSOR AND DE SKEW CONTROL tlon the cursor anywhere on the screen and allow the start
Value Skew address to be modified
00 No Character Skew The Address Register IS a five-bit wnte-only register used
as an "Indirect" or "pointer" register Its contents are the ~
01 One Character Skew
dress of one of the other 18 registers When both RS and CS
10 Two Character Skew
are low, the Address Register IS selected When CS IS low
11 Not Available and RS IS high, the register pOinted to by the Address
Register IS selected
Maximum Scan Line Address Register (R91 - This 5-blt
register determines the number of scan lines per character Start Address Register (R12-H, R13-LI - ThiS 14-blt
row Including the spacing thus controlling operation of the wnte-only register pair controls the first address output by
Row Address counter. The programmed value IS a maximum the CRTC after vertical blanking It consists of an 8-blt low
address and IS one less than the number of scan lines order (MAO-MAl) register and a 6-blt high order (MA8-
MA 13) register The start address register determines which
Cursor Start Register (Rl01 and Cursor End Register (Rll1 portion of the refresh RAM IS displayed on the CRT screen
- These registers allow a cursor of up to 32 scan lines In Hardware scrolling by character, line or page may be ac-
height to be placed on any scan line of the character block as complished by modifYing the contents of thiS register
shown In Figure 15 Rl0 IS a 7-blt register used to define the
start scan line and blink rate for the cursor Bits 5 and 6 of
the Cursor Start Address Register control the cursor opera- Cursor Register (Rl4-H. R15-LI - ThiS 14-blt wnte-only
tion as shown In Table 4 Non-display, display and two blink register pair IS programmed to position the cursor anywhere

•
modes (16 times or 32 times the field penod) are available In the refresh RAM area thus allOWing hardware paging and
R 11 IS a 5-blt register which defines the last scan line of the scrolling through memory Without loss of the anginal cursor
cursor position It conSists of an 8-blt low order (MAO-MA7) register
When an external blink feature on characters IS required, It and a 6-blt high order (MA8-MA 13) register
may be necessary to perform cursor blink externally so that
both blink rates are synchronIZed Note that an Invert/ non-
Invert cursor IS eaSily Implemented by programming the CRTC INITIALIZATION
CRTC for a blinking cursor and externally inverting the video Registers R12-R15 must be Initialized after the system IS
Signal with an exclusive-OR gate powered up The processor Will normally load the CRTC
leglster file from a firmware table Figure 16 shows an M6800
PROGRAMMABLE REGISTERS program which could be used to program the CRT Con-
The five programmable registers allow the MPU to POSI- troller

FIGURE 15 - CURSOR CONTROL

I ~+

--
On Off On
I I
I
~ Blink Penod=
I I 16 or 32 Times
Field Penod
Example of Cursor Display Mode

o-++-lr-l--+-++- o-+-+-1f-+H+ o
1-++H++-t- 1-+++-++-Hr- 1
2-++-+-++H- 2 -+-+-+-I-+--HI-- 2
3--+-+-t-++-t-t- 3-l-++-H-+-+- 3
4 -+++-1H-t-+- 4--+--+-+t-++-t- 4
5--+-+-t-++-t-t- 5--++-+-+-+-+-1- 5
6--+-+-t-++-t-t- 6-+-+-+-+-+-+-1- 6
7-++-H1-t-t-+- 7-+-++H-++- 7

J'~~~a*~
8--+-+-+-+-+-+-1- 8

16:~~~~~t3~
9
10
11-++-H1-t-t-+- l1-1-+++-HH- 11

Cursor Start Adr =9 Cursor Start Adr = 9 Cursor Start Adr = 1

Cursor End Adr : 9 Cursor End Adr : 10 Cursor End Adr = 5

4·384
MC6835

ADDITIONAL CRTC APPLICATIONS qUired to meet system speCifications The worksheet of

The foremost system function which may be performed by Table 5 IS extremely useful In computing proper register
the CRTC controller IS the refreshing of dynamic RAM This values for the MC6835 The program shown In Figure 16 may
IS qUite simple as the refresh addresses continually run be expanded to properly load the calculated register values In
Both the V S and the HS outputs may be used as a real the MC6B45 Once the two sets of register values have been
time clock Once programmed, the CRTC Will provide a developed, fill out the ROM program worksheet of Figure 19
stable reference frequency To order a custom programmed MC6835, contact your
local field service office, local sales person or your local
SELECTING MASK PROGRAMMED REGISTER VALUES Motorola representative A manufactunng mask Will be
A prototype system may be developed uSing the MC6B45 developed for the data entered In Figure 19
CRTC This Will allow register values to be modified as re-

FIGURE 16 - M6800 PROGRAM FOR CRTC INITIALIZATION

PAGE 001 CRTCINIT.SA:l MC6835 CRTC initialization program

00001 NAM MC6835

00002 TTL CRTC initialization program
00003 OPT G,S,LLE=85 print FCB'x, FOB's & XREF table

•
00004 ********************************************************
00005 * Assign CRTC address
00006 *
00007 9000 A CRT CAD EQU $9000 Address Register
00008 9001 A CRTCRG EQU CRTCAD+l Data Register
00009 ********************************************************
00010 * Initialization Program
00011 *
00012A 0000 ORG 0 a place to start
00013A 0000 C6 0C A LDAB $C initialize pointer
00014A 0002 CE 1020 A LDX 38RTTAB table pointer
00015A 0005 F7 9000 A CRTCI STAB CRTCAD load address register
00016A 0008 A6 00 A LDAA 0,X get register value from table
00017A 000A B7 9001 A STAA CRTCRG program register
00018A 0000 08 INX increment counter
00019A 000E 5C INCB
00020A 000F Dl 10 A CMPB $10 finished?
00021A 0011 26 F2 0005 BNE CRTCI no: take branch
00022A 0013 3F SWI yes: call monitor
00023 ********************************************************
00024 * CRTC register initialization table
00025 *
00026A 1020 ORG $1020 start of table
00027A 1020 0080 A CRTTAB FDB $0080 R12, R13 - Start Address
00028A 1022 0080 A FDB $0080 R14, R15 - Cursor Address
00029 END
TOTAL ERRORS 00000--00000

CRTCI 0005 CRT CAD 9000 CRTCRG 9001 CRT TAB 1020

4·385
 • s:
~

TABLE 5 - GRTG FORMAT WORKSHEET

Display Format Worksheet GRTC Registers

Displayed Characters per Row Char Decimal Hex

Displayed Character Rows per Screen Rows
RO HOflzontal Total I Line 15 - 1)
Character Matnx a Columns Columns
Rl Horizontal DIsplayed (Line 1)
Rows Rows
R2 HOrIZontal Sync Position ILlne 1 + Lme 12)
4 Charactel Block a Columns Columns
R3 HOrizontal Sync Width (Lme 13)
Rows Rows
114 Vertical Total (Line 9-1)
Frame Refresh Rate Hz
R5 Vertical Adjust (Line 9 Lines)
J:>. HOrIZontal OscIllator Frequency Hz
R6 Vertical Displayed ILlne 2)

~
m
7
8
Active Scan Lines (Line 2x Lme 4b)
Total Scan Lines (Line 6 - Line 5)
Lines
lines
R7 Vertical Sync Position (Line 2+ Line 10)
R8 Interlace 100 Normal, 01 interlace,
9 Total Rows Per Screen I Line 8 - Line 4b) _ _ Rows and _ _ Lines 03 interlace, and Video)
10 Vertical Sync Delay IChar Rows) Rows R9 Max Scan Line Add IL,ne 4b -11
11 Vertical Sync Width IScan Lines 11611 Lmes Rl0 Cursor Start
12 HOrIZontal Sync Delay (Character Times) Char Times R11 Cursor End
13 HOrizontal Sync Width (Character Times) Char Times R12. R13 Start Address IH and LI
14 HOrIZontal Scan Delay (Character Times) Char Times R14, R15 Cursor IH and U
15 Total Character Times (Line 1 + 12+ 13+ 14) Char Times

16 Character Rate I Line 6 x 15) Hz

17 Dot Clock Rate I Line 4a x 161 Hz

 3:

i
TABLE 6 - WORKSHEET FOR SOx 24 FORMAT

Oisplay Format Worksheet CRTC Registers

Displayed Characters per Row 80 Char Oecimal Hex

Displayed Character Rows per Screen 24 Rows
RD HOrizontal Total (Line 15 minus 11 101 ~
3 Character MatriX a Columns Columns
Rl HOrizontal Displayed (Line 1) 80 ---.fjQ
bRows 9 Rows
__9 ___ R2 HOrizontal Sync Position (Lme 1 + Lme 121 B6 __56
4 Character Block a Columns Columns
9 __9
bRows 11 Rows R3 Honzontal Sync Width ILlne 131
R4 Vertical Total 'I Line 9 minus 11 24 _ _1_8_ _
5 Frame Refresh Rate 60 Hz
6 HOrizontal Oscillator Frequency 18,800 Hz R5 Vertical Adjust (Line 9 Lmes) 10 ~
24 _ _1_8
~ 7 Active Scan Lines ILlne 2 x Line 4bl 264 Lmes R6 Vertical Displayed ILlne 21
CN 8 Total Scan Lines ILlne 6- Line 51 310 Ltnes R7 Vertical Sync Position ILlne 2+ Line 101 24 __18
00
..... 9 Total Rows Per Screen ILlne 8- Line 4bl 28_ Rows and__2__ Lines
__ R8 Interlace 100 Normal, 01 Interlace, 0
03 Interlace, and Vldeol
10 Vertical Sync Delay IChar Rowsl Rows __B
R9 Max Scan Line Add I Line 4b minus 11 11
11 Vertical Sync Width IScan Lines 11611 _ _1_6_ _ Lines
0 __0
RlO Cursor Start
12 Honzontal Sync Delay ICharacter Tlmesl 6 Char Times
11 __B
Rll Cursor End
13 HOrizontal Sync Width (Character Times) 9 Char Times
R12, R13 Start Address IH and LI 128 ~
14 HOrizontal Scan Delay (Character Times) Char Times
~
15 Total Character Times ILlne 1 + 12+ 13+ 141 102 Char TImes
R14, R15 Cursor IH and LI 128 ~
16 Character Rate ILlne 6 times 151 18972 M MHz
80
17 Dot Clock Rate ILllie 4a times 161 17075 M MHz

II
 MC6835

OPERATION OF THE CRTC

liming of the CRT Interface Signals - Timing charts of format of this example IS shown In Figure 11. Figure 18 IS an
CRT interface signals are Illustrated In this section with the illustration of the relation between Refresh Memory Address
aid of programmed example of the CRTC. When values (MAO-MA13), Raster Address (RAO-RA4) and the position
listed In Table 7 are programmed Into CRTC control on the screen. In this example, the start address IS assumed
registers, 'the device provides the outputs as shown In the to be "0"
Timing Diagrams (Figures 12, 13, 17, and 18L The screen

TABLE 7 - VALUES PROGRAMMED INTO CRTC REGISTERS

Register Programmed
Register Name Value
Number Value
AO H Total Nht+ l Nht
Al H Displayed Nhd Nhd
A2 H Sync POSItIOn Nhsp Nhsp
A3 H Sync Width Nhsw Nhsw
A4 V Total Nvt+l Nvt
A5 V Scan Line Adjust Nad Nad

•
A6 V Displayed Nvd Nvd
R7 V Sync Position Nvsp Nvsp
R8 Interlace Mode
R9 Max Scan Line Address Nsl Nsl
R10 Cursor Start
Rll Cursor End
R12 Start Address (H) 0
R13 Start Address (Ll 0
R14 Cursor (H)
R15 Cursor (Ll
R16 Light Pen (H)
R17 Light Pen (Ll

4·388
 s:
i
FIGURE 17 - CURSOR TIMING

R~R~, f f f
I I I I

MAO-MA13" ~ Nhd
T f f
I Nhd + 1 Nhd + 2
~I Nhd + , Nhd
• • ~.1 Nhd + ~
I Nhd + 1 INghd + 21
trtn Nhd
• •
I Nhd + 1 I Nhd + 2 I Nhd + 1
#
1 1 1 Nht I I I I 1 Nht I I I I Nht I

Character Row # I I : ; : : i : : : : I I : : I
.,. : 1 I: I I: I :
~ ~ I: : I~ I
~
Character,! : :
o I 2 Nht I Nht 0 I Nht
I I 1 1 I I
cursor!----1 ~ f--i~ ____
·TlmlnQ IS shown for non-Interlace and Interlace sync modes
Example shown has cursor programmed as
Cursor Register = Nhd + 2
Cursor Start = 1
Cursor End = 3
""The Initial MA IS determined by the contents of Start Address Register, R12/R13 Timing IS shown for R12/R13=O

Note 1 Timing values are described In Table 8

II
 • ~

ii;
u .5"
FIGURE 18 - REFRESH MEMORY ADDRESSING (MAO-MA13) STATE CHART

HOrizontal Display HOrizontal Retrace (Non-Display)

~
~ ~
.co
Ua: ~I~ II
I 0 1
I
)0 Nh9-1 N~d • Nht
I
O{N: 0
I
I
I
I )0
I
I
Nhd- 1 Nhd
I
)0
I
I
Nht
I
I

Npd Nh<j+ 1
• 2XNhd-1 2X~hd
• Nhd+ Nht

{N:
I
I I i I I

•
I I
Nhd Nhd+ 1 2XN~d 1 2XNhd )0
Nhd+ Nht

2
I 2XNhd
I
2XN nd+ 1
I
• 3XNhd-1
I
3X~hd
I
• 2Nhd+Nht
I

g>1 { Ns
.!Jl I I-
I
2XNhd 2XNh'd+ 1 • 3XNhd 1 3XNhd • 2Nhd'+ Nht i
13 !

~
>

.,..
(.)
1 1 J J 1 I
<0
o NVd- 1{ 0
I INvd-11 x Nhd
i
INvd-11 x Nhd+ 1
I
• Nvd xN hd+ 1
I
I
Nvd~ Nhd
I
• INvd-llxNhd+Nhtl

I I

•
I

Ns I INvd ;1 x Nhd INvd llx Nhd+ 1

• Nvd x Nhd 1 Nvd x Nhd INvd llxNhd+Nhtl
Nvd x Nhd
I
Nvdx Nhd+ 1
I • INvd+ II x Nhd-1
I
INvd + 11 x Nhd
I
I
)0 Nvd x Nhd + Nht
I
NVd{ I I I
>-
'"
~
Ns I Nvd x Nhd Nvd x Nhd+ 1 • INvd+ 11 x Nhd-1 INvt + 11 x Nhd • Nvd+ Nhd+ Nht

~o
z
l'l ;'vt x Nhd Nvtx Nhd+ 1 IN vt + II x Nhd-1 IN vt + II x Nhd Nvt x Nhd + Nht
~
;; I I
a: Nvt{ 0 I I i I I
rn Ns Nvt" Nhd I IN vt + II x Nhd-1 INvt+ II x Nhd Nvt x Nhd + Nht
"ii;
;0

IN v + II~hd + Nht
>
I INvt + 1I x Nhd IN v,+ II ,x Nhd+ 1 INv,+21 x Nhd-l INvt + ~I x Nhd
Nvt+ 1{ 0 I
I
I i I I
Nad I IN vt + 11 x Nhd IN vt + II x Nd+ 1 IN v,+21 x Nhd-1 INvt+ 21 x Nhd INvt + 1lNhd+ Nht
I

NOTE 1 The Initial MA IS determined by the contents of start address register, R12/R13 Timing IS shown for R12/R13= 0 Only Non-
Interlace and Interlace Sync Modes are shown
MC6835

FIGURE 19 - ROM PROGRAM WORKSHEET

The value In each register of the MC6846 should be entered without any modifications. Motorola Will take care of translating Into the appropnate
format.
o All numbers are In decimal oAll numbers are In hex.

ROM ROM
Program Program
Zero Ona
(PROG=O) (PROG=I)

RO

RI

R2

R3

R4

R5

•
R6

R7

RS

RS

RIO

RII

ORDERING INFORMATION

Motorola Integrated CIrCUit

-,-
MC~35CP
M8800 Family
8lanks= I 0 MHz
A=15MHz
8=20 MHz
DeVice DeSignation
In M8800 Family Speed Device Temperature Range
Temperature Range
10 MHz
MC6835P ,L,S o to 70°C
Blank = 0°_ + 70°C MC6835CP ,CL,CS -40 to +85°C
C= _40°_ +S5°C MC68A35P ,L,S Oto +70 0 C
Package 15 MHz
MC68A35CP,CL,CS -40 to +85°C
p= Plastic
S=Cerd,p
20 MHz MC68B35P, L, S o to +70 0 C
L=Ceramlc

BETTER PROGRAM

Better program processing IS available on all types hsted. Add

suffiX letters to part number.

Levell add" S" Level 2 add "0" Level 3 add "OS"

Levell "S"=10Temp Cycles - 1-25 to 150°CI,

HI Temp testing at T A max
Level 2 "0" = 168 Hour Burn-In at 125°C
Level 3 "OS" = Combination of Levelland 2

4-391
 MC68A39
® MOTOROLA
MC68B39
(1.5 MHz)

(2.0 MHz)

Advance InforIDation
MOS
FLOATING-POINT ROM IN-CHANNEL, SILICON-GATE)

The MC6839 standard product ROM provides floating pOint capability

FLOATING-POINT
for the MC6809 or MC6809E MPU The MC6839 Implements the entire
IEEE Proposed Standard for Binary Floatmg Pomt Arithmetic Draft 8.0, READ-ONLY MEMORY
prOViding a simple, economical and reliable solution to a wide variety of
numerical applications The slngle- and double-precIsion formats pro-
vide results which are blt-for-blt reproducible across all Draft 60 Im-
plementations, while the extended format prOVides the extra precIsion
needed for the Intermediate results of long calculations, In particular the
Implementation of transcendental functions and Interest calculations
All applications benefit from extensive error-checking and well-defined
responses to exceptions, which are strengths of the IEEE proposed
standard C SUFFIX
The MC6839 takes full advantage of the advanced architectural FRIT·SEAL
features of the MC6809 microprocessor. It IS position-Independent and CERAMIC PACKAGE
re-entrant, facilitating Its use In real-time, multi-tasking systems CASE 716

II
• Totally Position Independent
• Operates In any Contiguous BK Block of Memory

~
.
• Re-Entrant
--~ , '
• No Use of Absolute RAM
• All Memory References are made Relative to the Stack POinter 24 " .
• FleXible User Interface 1 I P SUFFIX
• Operands are Passed to the Package by One of Two Methods PLASTIC PACKAGE
1) Machine Registers are used as POinters to the Operands CASE 709
2) The Operands are Pushed onto the Hardware Stack
• The Latter Method Facilitates the use of the MC6839 In High-Level
Language Implementations
• Easy to Use Two/Three Address Architecture
• The User SpeCifies Addresses of Operands and Result and Need PIN ASSIGNMENT
Not be Concerned With any Internal Registers or Intermediate
Results
• A Complete Implementation of the Proposed IEEE Standard A7 Vee
Draft 6 0
A6 1 13 AS
• Includes All PreCIsions, Modes, and Operations Required or
Suggested by the Standard A5 2.' A9
• Single, Double, and Extended Formats 21 Al2
• Includes the Following Operations
Add 20
Subtract A2 AIO
Multiply
All
D,v,de
Remainder AO D7
Square Root DO D6
Integer Part
Dl D5
Absolute Value
Negate D2 D4
Predicate Compares 13 D3
Condition Code Compares VSS
Convert Integer- Floating POint
Convert Binary Floating POlnt- Decimal String

4·392
MC68A3ge MC68B39

AO 9 DO
Al Dl
10
A2 11 02
A3 13 03
BLOCK Address
A4 4 14 04
Dec.:>de
DIAGRAM A5 15 05
A6 16 06
A7 17 D7
A8 ?3
A9 22
Al0 19
A11 ,18
A12 21

E 20 Pin 24
Vee
VSS Pin 12

ABSOLUTE MAXIMUM RATINGS

Rating Symbol Value Untt
ThiS device contains circuitry to protect the
Supply Voltage VCC - a 5 to + 7 a V Inputs against damage due to high static
Input Voltage V,n - a 5 to + 7 a V voltages or electriC fields, however, It IS nd-
a to + 70 . vised that normal precautions be taken to
Operating Temperature Range TA "C
avoid application of any voltage higher than

•
Storage Temperature Range Tstg -65to+150 'c maximum rated voltages to thiS high 1m
pedance Circuit Reliability of operation IS
enhanced If unused Inputs are tied to an ap-
CAPACITANCE
propriate logic voltage {e 9 , either V SS or
VCCI
Characteristic
Input Capacitance
Output Capacttance

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherWise noted)

RECOMMENDED DC OPERATING CONDITIONS

Parameter Symbol Min Nom Max Unit
Supply Voltage
VCC 45 50 55 V
(VCC must be applied at least 100 J-Ls before proper device operation IS achieved)
Input High Voltage VIH 20 - 55 V
Input Low Voltage VIL -05 -- 08 V

DC CHARACTERISTICS
Characteristic Symbol Min Typ Max Unit
Input Current (V In ~ a to 55 V) lin -10 - 10 pA
Output High Voltage (IOH ~ - 220 pAl VOH 24 - - V
Output Low Voltage (IOL - 3 2 mAl VOL - - 04 V
Output Leakage Current IThree-State} IE-2 a V, Vout-O V to 5 5 VI ILO -10 - 10 pA
Supply Current - Active- (Minimum Cycle Rate) ICC - 25 40 mA
Supply Current - Standby (E ~ VIHI ISB - 7 10 rnA

- Current IS proportional to cycle rate

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Read Cycle)
RECOMMENDED AC OPERATING CONDITIONS ITA~O to 70'C VCC~5 aV ± 10% All timing with tr~tf~20 ns load of Figure 11
MC68A39 MC68B39
Parameter Symbol Unit
Min Max Min Max
Chip Enable Low to Chip Enable Low of Next Cycle ICycle Time} tELEL 450 - 375 - ns
Chip Enable Low to Chip Enable High tELEH 300 - 250 - ns
Chip Enable Low to Output Valid (Accessl tELOV - 300 - 250 ns
Chip Enable High to Output High Z (Off T,mel tEHQZ - 75 - 60 ns
Chip Enable Low to Address Don't Care (Holdl tELAX 75 - 60 - ns
Address Valid to Chip Enable Low (Address Setup) tAVEL a - a - ns
Chip Enable Precharge Time tEHEL 110 - 70 - ns

4-393
 MC68A3geMC68B39

FIGURE 1 - AC TEST LOAD

50V

Test Pomt 0 -.....- -+.-..

.....
MMD6150
or Equlv

100 pF' 109 k

MMD7000
or EqUtv

·Includes Jig Capacitance

FIGURE 2 - TIMING DIAGRAM

~------------------tELEL------------------~~

CHIP ENABLE. !;:

j4----------tELEH -------~~

ADDRESS. A

I
DATA OUTPUT. Q
VOH-
VOL-
III Z
1 VALID ----------H'Z----------

INTRODUCTION operaltons required or suggested by the IEEE proposed stan-

dard
Since the earliest days of computers It has has been ob- From ItS very Inception, the M6809 microprocessor was
VIOUS that no computer was capable of dOing all deSirable deSigned to support a concept of ROM able software by an
mathematical operations In binary Integer anthmetlc To Improved Instruction set and addreSSing modes. It was felt
meet the needs of those applications requiring the manipula- that the only way to reduce the escalating cost of software
tion of real numbers, floating pOint I FP) evolved and became was for the silicon manufacturer to supply software on
widely used Unfortunately, each computer manufacturer Silicon Since the manufacturer can amortize the cost of
created hiS own floating pOint I FP) representation and the developing the software over a very large volume, the cost of
ensUing wide vanatlon In formats, accuracy, and exception thiS software, above normal masked ROM costs, Will be low
handling almost guarantees that a program executed on one Also, to be useful In many diverse systems, the ROM must
computer will get different results If executed on another be position-independent and re-entrant
computer The Intent of thiS Advance Information Idata) Sheet IS to
Meanwhile, research has been completed which for- provide the reader With enough information to make an In-
mulates an optional binary floating pOint representation Un- telligent deCISion as to whether the MC6839 IS applicable to
fortunately, the eXisting manufacturers have far too much hiS system The Intent IS not to prOVide all the details
money Invested In software and hardware to Incur the costs necessary to Interface or program the MC6839, a users
of conversion to a new standard Powerful microprocessors, manual IS available for that purpose A familianty With the
on the other hand, were In their Infancy and the floating MC6809 Instruction set IS assumed In thiS document
pOint experts saw the opportunity to standardize a floating
pOint format for microprocessors The IEEE apPointed a
committee to address the standard and their work resulted In PHYSICAL CHARACTERISTICS
the IEEE Proposed Standard for Bmary Floatmg Pomt I
ArithmetiC Draft B.O The MC6839 IS housed In! one 24-pln 8K-by-8 mask pro-
The MC6839 represents a complete Implementation of the grammable ROM the MCM68364 ThiS ROM uses a single
IEEE proposed standard Since hardware Implementations of 5 V power supply and IS available With access times of 250 or
floating POint IFP) are always several orders of magnitude 350 nS The MC6839 IS deSigned to be used In MC6809 or
faster land more expensive) than software Implementations, MC6809E systems With up to 2 MHz Internal clocks Full
the MC6839 substitutes Increased functionality for speed deVice characteristics can be found at the front of thiS data
Therefore, the M C6839 supports all precISions, modes, and sheet

4·394
MC68A39- MC68B39

FLOATING POINT FORMATS

The MC6839 supports the three precIsions suggested by the IEEE Proposed Floating POint Standard. single, double, and extend-
ed. The values occupy 32,64, and BO bits 14, 8, and 10 bytes) respectively In the users memory The formats of the three precIsions
are descrdbed In the following paragraphs.

SINGLE FORMAT
All single precIsion numbers are represented In four bytes as

~--23 blts---lO~1
11 f--8--lOlO+'I...
1 s 1 exponent 1 slgnlflcand I
The exponent IS biased by + 127. That IS exponent of. 20 IS 127, 22 IS 129, and 2-2 IS 125 The slgnlflcand IS stored In sign
magnitude rather than twos complement form The equation for the single form representation IS
x= I -1)S x 2Iexp-127) x 11 slgnlflcand)
s = sign of the slgnlflcand
exp = biased exponent
signlficand = bit string of length 23 encoding the significant bits of the number that follow the binary pOint. Yielding a 24-blt signifi-

II
cant digit field for the number that always begins" 1___ "

Examples:
+1.0= 1.0x20=$3F BO 00 00
+30= 1.5x21=$40 40 00 00
-10= -1.0x20=$8F BO 00 00

DOUBLE FORMAT
All double precIsion numbers are represented by an 8-byte stnng as

11 j.-11 blts_)o+-II(~--52 blts---;.~I

liOL: exponent 1 slgnlflcand I

For double formats the exponent IS biased by + 1023 The rest of the Interpretation IS the same as for Single format The equa-
tion for double format IS
x = I - 1)S x 21exp - 1023) x 11 slgnlflcand)

Examples'
70= 175 =22= $40 1C 00 00 00 00 00 00
-300= -1 875 x 24 = $CO 3E 00 00 00 00 00 00
025= 1 0 x 22= $3F DO 00 00 00 00 00 00

EXTENDED FORMAT
Single- and double-formats should be used to represent the bulk of floating pOint IFP) numbers In the user's system Ie g ,
storage of arrays) Extended should only be used for Intermediate calculations such as occur In the evaluation of a complex expres-
sion In fact, extended may not be used at all by most users, but since It IS required Internally, It IS optIOnally provided Extended
numbers are represented In 10 bytes as

11 1+-15 bltS_lO,..II(r---64 blts---'.~I

1 s 1 exponent 11. Significant I

4·395
 MC68A3geMC68B39

A notable difference between this format and single and double IS the 1.0 IS expliCitly present In the slgnlflcand and the exponent
contains no bias and IS in twos complement form. The equation for double extended is
x = ( -1)s x ;zexp x significand
where the significand contains the explicit 1 O.

Examples:
0.5= 1.0x2- 1= $7F FF 80 00 00 00 00 00 00 00
-1.0= -1.0x20 $80 00 80 00 00 00 00 00 00 00
384.0= 1.5x2B $00 08 CO 00 00 00 00 00 00 00

BCD STRINGS
A BCD string IS the input to the BCD-to-Floatlng-Polnt conversion operation and the output of the Floatlng-Polnt-to-BCD con-
version operation All BCD strings have the following format:

o 1 5 6 24 25
se 4 digit BCD exponent sf 19 digit BCD fraction p

se= sign of the exponent $00= plus, $OF = minus (one byte)

•
sf = sign of the fraction. $00= plus, $OF = minus. (one byte)
p = number of fraction digits to the right of the decimal POint (one byte)
All BCD digits are unpacked and nght lustlfled In each byte.

7 o
10000 0-9

The byte ordering of the fraction and exponent IS consistent With all Motorola processors In that the most-significant BCD digit IS
in the lowest memory address.

Examples:
2.0=2 Ox 100 (p=OI
Address Data
0000 00 (se= +1
0001 00 00 00 00 lexponent = 01
0005 00 (sf= +1
0006 00 00 00 00 00 Ifractlon = 21
oooB 00 00 00 00 00
0010 00 00 00 00 00
0015 00 00 00 02
0019 00 Ip=OI
or 2.0=20,000 x 1O- 4(p=0)
Address Data
0000 OF (se= -I
0001 00 00 00 04 I exponent = 41
0005 00 Isf= + 1
0006 00 00 00 00 00 I fraction = 200001
oooB 00 00 00 00 00
0010 00 00 00 00 02
0015 00 00 00 00
0019 00 Ip=OI
(The above might be the output of a Floatlng-Polnt-to-BCD With k = 5)
or 2.0=2.0x 100 (p= 101
Address Data
0000 00 Ise= +1
0001 00 00 00 00 I exponent = 01
0005 00 Isf= +1
0006 00 00 00 00 00 Ifractlon = 200000000001
OOOB 00 00 00 02 00
0010 00 00 00 00 00
0015 00 00 00 00
0019 OA Ip=101

4-396
MC68A39-MC68B39

INTEGERS ASCII
Two sizes of Integers are supported; short and double. Mnemonic Description
Short Integers are 16 bits long and double Integers are 32 bits FADD Add arg1 to arg2 and store the result
long. The byte ordering IS consistent with all Motorola pro- FSUB Subtract arg2 from arg 1 and store the result
cessors In that the most-significant bits are In the lowest ad- FMUL Multiply arg1 times arg2 and store the result
dress.
FDIV D,v,de arg1 by arg2 and store the result
SPECIAL VALUES FREM Take the remainder of arg1 diVided by arg2 and
store the result The remainder IS biased to lie In
No derivable floating POint format can represent the in-
the range - arg212 < remalnder< + arg2/2, In-
finite number of possible real numbers, so It IS very useful If
stead of the usual range of 0" remalnder< arg2
some special numbers are recognized by a floating pOint
ThiS bias makes the function more useful In the
package These numbers are + 0, - 0, + ,nfin,ty, - infini-
Implementation of trigonometric and other func-
ty, very small (almost zero) numbers, and In some cases un-
tions
normahzed numbers. Also, It IS convenient to have a sepclal
format which indicates that the contents of memory do not FCMP Compare arg1 With arg2 and set the condition
contain a vahd floating POint number ThiS "not a number" codes to the result of the compare Arg1 and arg2
might occur If a variable IS defined In a HLL and IS used can be of different precIsions
before It IS Inltlahzed With a value The most positive and FTCMP Compare arg1 With arg2 and set the condition

•
negatIVe exponents of each format are reserved to represent codes to the result of the compare In addition,
these special vaues trap If an unordered exception occurs regardless
The detailed deSCription of these special values IS given In of the state of the UNOR (unorderedl bit In the
a later section. trap enable byte of the fpcb
FPCMP A predicate compare, thiS means compare arg1
With arg2 and affirm or disaffirm the Input
predicate (e g., 'IS arg1 = arg2' or 'IS arg1 <arg2')
ARCHITECTURE FTPCMP A trapping predicate compare, same as the
predicate compare except trap on an unordered
All floating pOint operations are of the "two address" or exception regardless of the state of the UNOR
"three address" variety, all the user need supply are the ad- (unordered I bit In the trap enable byte of the fpcb
dresses of the operand(sl and the result The package looks FSQRT Returns the square root of arg2 In the result
for operands at the speCified locatlon(s) and dehvers the FINT Returns the Interger part of arg2 In the result The
result to the speCified destination For example, result IS stili a floating pOint number For example,
Arg1 + Arg2 Result the Integer part of 3 14159 IS 3 00000
< source> < source> < destination> FFIX5 Convert arg2 to a short (16-bltl binary Integer
Intel mediate results are never presented to the user, FFIXD Convert arg2 to a long (32-bltl binary Integer
therefore, there are no Internal "registers" to be concerned FFL T5 Convert a short binary Integer to a floating pOint
about, keeping the Interface as Simple as pOSSible The end result
result IS ease of use
FFLTD Convert a long binary Integer to a floating pOint
There IS a user defined floating pOint control block (fpcb)
result
that defines the mode of the package ThiS control block IS
much like the control blocks frequently used to define 1/0 or BINDEC Convert a binary floating pOint value to a BCD
operating system operations The fpcb IS discussed In detail declma string.
In a later section DECBIN Convert a BCD deCimal string to a binary floating
pOint result
FAB5 Return the absolute value of ar92 In the result
FNEG Return the negative of arg2 In the 'esult
SUPPORTED OPERATIONS FMOV Move (or convertl arg1- arg2 ThiS function IS
useful for changing precIsions (e g , Single to
The MC6839 supports the follOWing operations On any double I With full exception checking for pOSSible
particular call to the floating pOint ROM a 1-byte opcode overflow or underflow
which Immediately follows the LBSR instruction chooses the All routines, except FMOV and the compares, accept
deSired operation Below are short deSCriptions of the func- arguments of the same precIsion and generate a result With
tions Implemented In the MC6839 along With suggested the same precIsion For moves and compares the sizes of the
men manics A table containing the opcodes and calhng se- arguments are passed to the package In a parameter word
quences for these functions IS presented at the end of thiS Details of each operation can be found In the MC6839
data sheet Users Manual

4-397
 MC68A3ge MC68B39

MODES OF OPERATION mahzed operand IS operated on such that ItS fraction remains
not normalIZed but ItS exponent IS no longer at ItS Original
In addition to supporting a wide range of precIsions and mlntmum value. By transforming denormallZed operands to
operations, the M C6839 supports all modes reqUired or sug- normalized, Internal form upon entering each operation, un-
gested by the IEEE Proposed Floating POint Standard. These normalIZed results are guaranteed not to occur
Include rounding modes, Infintty closure modes, and excep- Thus, when operating In thiS mode the user can be
tion handling modes. The various modes are selected by bits assured that no attempt Will be made to return an unnor-
In the floating POint control block (fpcbl that resides In user mallZed value to a Single or double destlnallOn A bit In the
memory. Thus, each user or task can have a unique set of control byte of the fpcb selects whether or not thiS mode IS
modes In effect for his calculations. The selection bits are In effect. ThiS mode IS forced whenever the round mode IS
defined In a later section on the fpcb either round toward plus or minus infinity UnnormallZed
numbers entenng an operation are not affected by thiS
ROUNDING MODES mode, only denormallzed ones are Unnormallzed and
Four rounding modes are suggested by the IEEE Proposed denormallzed operands are discussed In a later section
Floating POint Standard. They are
1. Round to nearest (RNI EXCEPTIONS
2. Round toward zero IRZI
3. Round toward plus Infinity IRP) One of the greatest strengths of the IEEE Proposed
4. Round toward minus Infinity IRN) Floating POint Standard IS the regular and conslstant handl-
Ing of exceptions. EXisting floating pOint Implementations
Round nearest will be used by most users because It pro-
are qUite vaned In the way they handle exceptions, so the

II
vides the most accurate answers for most calculations
Round towards zero Itruncate) IS useful when the MC6839 proposed IEEE standard has very carefully prescnbed how
exceptions must be handled and what constitutes an excep-
Implements real numbers In some high level languages that
tion Seven types of exceptions Will be recognIZed by the
require truncation lie., FORTRAN) Round towards plus
MC6839 Only the first 5 are required by the proposed IEEE
and minus infinity are used In Interval anthmellc
standard They are'
Normally a result IS rounded to the precIsion of ItS deSllna-
tlon. However, when the destination IS Extended, the user '1 Invalid Operation - a general exception that anses
can specify that the result slgntflcand be rounded to the when an operation has gone so wrong that the pro-
precIsion of the basic format - Single, double, or ex- gram cannot return any reasonable result or fit the ex-
tended - of hiS chOice, although the exponent range re- ception Into any of the other more speCifiC classes
mams extended 2 Underflow - arises when an operation generates a
result that IS too small to fit Into the deSired result
NO DOUBLE ROUNDING - The MC6839 IS Implemented preCISion
such that no result Will undergo more than one rounding er- 3 Overflow - anses when an operation generates a
ror. result that IS too large to fit Into the deSired result
preCIsion
INFINITY CLOSURE MODES 4 D,v,s,on by Zero - anses when diVISion by zero IS at-
The way In which Infinity IS handled In a floating POint tempted
package may limit the number of applications In which the 5 Inexact Result - anses when the result of an opera-
package can be used To solve th IS problem, the proposed tion was not exact and therefore was rounded to the
IEEE standard reqUires two types of Infinity closures A bit In deSired precIsion before being returned to the user
the control byte of the Floating POint Control Block Ifpcb)
6 Integer Overflow - anses when the binary Integer
Will select the type of closure that IS In effect at any time
result of a FIXSID) operation cannot fit Into 16(32)
bits
AFFINE CLOSURE - In affine closure
7 Companson of Unordered Values - anses when one
minus Inflnlty< (every finite number}< plus Infinity
of the arguments to a compare opecatlon IS a "NAN"
Thus, Inf,My takes part In the real number system tn the or an InflMy In the projective closure mode ISee the
same manner as any other signed quantity Infinity and Not a Number paragraphs for further ex-
planation of NANs and Infinity)
PROJECTIVE CLOSURE - In projective closure
For each exception the caller Will be given the option of
infinity = minus infinity = plus Infinity speCifYing whether the package should. 111 trap to a user
and all comparisons between Infinity and a floattng pOint supplied trap routine to process the exception, or (2) deliver
number InvolVing order relations other than equal (= ) or not a default result speCified by the proposed standard and pro-
equal I *) are Invalid operations In prOjective closure the real ceed with execution For most users the default result IS ade-
number system can be thought of as a Circle With zero at the quate and the user need not write any trap handlers
top and ,nf,n,ty at the bottom Regardless of whether a trap IS speCified or not, a status bit
Will be set In the status byte of the fpcb and Will remain set
NORMALIZE MODE until cleared by the caller's program. Selection of whether to
The purpose of the normalize mode IS to prevent un nor- trap or to continue Will be made by setting bits In the trap
mallZed results from being generated, which can otherWise enable byte of the fpcb For more details on the fpcb see the
happen Such an unnormallZed result arises when a den or- section on the Floating POint Control Block Ifpcb)

4·398
MC68A39-MC68839

If a trap IS taken, the floatmg point package supplies a 3 Underflow

pomter that pOints to an area on the stack containing the 4. D,v,s,on by Zero
following diagnostic ,nformat,on: 5. Unordered
1. Event that caused the tr,ap loverflow, etc.) 6. Integer Overflow
2. Where in the caller's program 7. Inexact Result
3. Opcode The user supplied trap routme Ilf any) Will usually do 1 of 3
4. The Input operands thmgs·
5. The default result m mternal format 1. F,x the result
In the event more than one exception occurs dUring the 2. Do nothmg to the result and allow the floating pomt
same operation, only one trap IS Invoked according to the package to deliver the default value to the result
follOWing precedence. 3. Abort execution
1 Invalid Operation SuffiCient detlls on how to write a trap routine are fur-
2. Overflow nished In the MC6839 Users Manual

USER INTERFACE

There are two types of calls to the floatmg pOint package. register calls and stack calls For register calls the user loads the
machine registers with pOinters laddresses) to the operandls) and to the result, the call to the package IS then performed For stack
calls the operandls) IS pushed on the stack and the call to the package IS performed With the result replacmg the operands on the
stack after completion The operand Is) must be pushed least-significant bytes first; thiS IS consistent With the other Motorola ar-
chitectures in that the most-significant byte reSides In the lowest address The two types of calls look like.
•
General form of a register call·
load registers
LBSR fpreg register call
FeB opcode
Example of a posItion-Independent call to the add routme
LEAU arg 1, pcr
LEA Y arg2, pcr
LEAX fpcbptr, pcr pOinter to fpcb
TFR x, d
LEAX result, pcr
LBSR fpreg
FeB fadd
General form of a stack call.
push arguments
LBSR fpstak stack call
FeB opcode
pull result

Example of a stack call to the add routine.

push argument 1
push argument 2
push fpcbptr pomter to fpcb
LBSR fpstak
FeB fadd
pull result

Details of the calling sequence for every type of operation can be found m the MC6839 Users Manual; a reference table of calling
sequences and opcodes can be found at the end of thiS data sheet

4·399
 MC68A39-MC68B39

STACK REQUIREMENTS
When the MC6839 IS called by the user, the package reserves local storage on the hardware stack It then moves the Input
arguments from user memory to the local storage area and expands them Into a convenient Internal format. The operations use
these "Internal" numbers to arrive at an "Internal" result which IS then converted to the memory format of the result and returned
to the user For this reason, the user must Insure that adequate memory eXists on the hardware stack before calling the MC6839
The maximum stack sizes that any particular function Will ever find necessary are
register calls 150 bytes
stack calls 185 bytes

FLOATING POINT CONTROL BLOCK (fpcb)

The fpcb IS a user-defined block that contains Information needed by the floating pOint package The fpcb IS also used to pass
status back to the caller or to Invoke the trap routine. The fpcb must reside In the user RAM space to InSure that the package can re-
main re-entrant. The caller of the floating pOint package must pass the address of the fpcb on each call The format of the fpcb IS

control byte 0
trap enable byte
status byte 2
secondary status byte 3

•
4
address of trap routine
5

The meaning of the various bit fields Within the fpcb are discussed In detail In the follOWing paragraphs

CONTROL BYTE - The control byte configures the floating pOint package for the caller's operation and IS written by the user
Various fields In the byte set the preCISion, round, infinity closure, and normalize modes

7 6 5 4 3 2 o
x NRM Roun~ Mode AlP

Bit 0 Closure IAI PI Bit

0= projective closure
1 = affine closure
Bits 1-2 Round Mode
00= round to nearest IRNI
01 = round to zero IRZI
10= round to plus infinity IRPI
11 = round to minus Infinity IRMI
Bit 3 Normalize INRMI Bit
1= normalize denormallzed numbers while In Internal format before uSing Precludes the creation of unnormallZed
numbers
0= do not normalize denormalized numbers Iwamlng model
NOTE
If the rounding mode IS RM or RP then normalize mode IS forced Unnormallzed numbers are not affected by bit 3
Bit 4 Undefined, reserved
Bits 5-7 PrecIsion Mode
000= Single
001 = Double
010= Extended With no forced rounding of result
011 = Extended - force round result to Single
100= Extended - force round result to double
101 = Undefined, reserved
110= Undefined, reserved
111 = Undefined, reserved
Note that If the control byte IS set to zero by the user, all defaults In the IEEE Proposed Floating POint Standard will be selected

4·400
MC68A39. MC68B39

STATUS BYTE

7 6 5 4 3 2 o
x INX IOV UN DZ UNF OVF lOP

The bits In the status byte are set If any errors have occurred Each bit of the status byte IS a "sticky" bit In that It must be manual-
ly reset by the user The FP package writes bits tnto the status byte but never clears eXlsttng bits ThiS IS done so that a long calcula-
tion can be completed and the status need only be checked once at the end
Bit 0 Invalid opertlon (see secondary status)
Bit 1 Overflow
Bit 2 Underflow
Bit 3 D,v,s,on by zero
Bit 4 Unordered
Bit 5 Integer overflow
Bit 6 Inexact result
Bit 7 Undefined, reserved

TRAP ENABLE BYTE

7 6
INX
5
IOV
4
UNOR
3
DZ
2
UNF OVF
o
lOP

A "1" In any bit of the trap enable byte enables the FP package to trap If that error occurs The bit definitions are the same as for
the status byte Note that If a trapPing compare IS executed and the result IS unordered, then the unordered trap Will be taken
regardless of the state of the UNOR bit In the trap enable byte
•
SECONDARY STATUS (55)
7 6 5 4 o
x

The FP package Will wnte a status Into thiS byte any time a new lOP occurs As IS the case With the status bytes, It IS up to the
caller to reset the "lOP type" field
Blls 0-4 Invalid Operation Type Field
0; no lOP error
1 = square root of a negatIve number, Inflntty In projective mode, or a not normalized number
2; (+ Infinity) + (- Infinity) In affine mode
3; tned to convert NAN to binary Integer
4; In divIsion 010, ,nf,n,ty/,nf,n,ty or divisor IS not normalized and the dividend IS not zero and IS ftnlte
5; one of the Input arguments was a trapping NAN
6; unordered values compared via predicate other than ; or '*'
7; k out of range for BINDEC or p out of range for DECBIN
8; projective closure use of + / - ,nfin,ty
9; 0 x infinity
10; In REM arg2 IS zero or not normalized or arg1 IS Infinite
11; unused, reserved
12; unused, reserved
13; BINDEC Integer too big to convert
14; DECBIN cannot represent Input string
15; tned to MOV a Single denormallzed number to a double destination
16; tned to return an unnormallzed number to single or double (,nvalid result)
17; divIsion by zero With divide by zero trap disabled

4-401
 MC68A39-MC68839

TRAP VECTOR - If any of the traps occur, the FP package Will jump indirectly through the trap addresS In the fpcb with an In-
dex in the A accumulator indicating the trap type:
0= Invalid Operation
1 = Overflow
2 = Underflow
3 =\ Divide by Zero
4= Unnormallzed
5 = Integer Overflow
6 = Inexact Result
If more than 1 enabled trap occurs, the MC6839 Will return the Index of the highest pnorty enabled error. Index = 0 = Invalid
operation IS the highest pnority, and, Index= 6 IS the lowest

SPECIAL VALUES (SINGLE- AND DOUBLE-FORMAT)

The encoding of the special values are given below. Generally, when used as operands, the special values flow through an opera-
tion creating a predictable result. Note that as with normalized numbers the extended format differs slightly from the single- and
double-formats.

I ZERO
Zero IS represented by a number With both a zero exponent and a zero slgnlflcand The sign IS Significant and differentiates be-
tween plus or minus zero.

o o

INFINITY
The Infinities are represented by a number With the maximum exponent and a zero slgnlflcand The sign differentiates plus or
minus infinity

I S 11111 .. 11111 o

DENORMALIZED (SMALL NUMBERS)

When a number IS so small that ItS exponent IS the smallest allowable normal biased value Ill, and It IS Impossible to normalize
the number Without further decrementing the exponent, then the number Will be allowed to become denormallzed The format for
denormal,zed numbers has a zero exponent and a non-zero slgnlflcand Note that In thiS form the ImpliCit bit IS no longer 1 but IS
zero The Interpretation for denormallzed numbers IS
Single: X = 1- liS x 2 - 126 x 10 slgnlflcandl
Double' X = 1- liS x 2 - 1022 x 10. slgnllicandl
Note that the exponent IS always Interpreted as 2 - 126 for Single and 2 - 1022 for double Instead of 2 - 127 ana 2 - 1023 as might
be expected. ThiS IS necessary since the only way to Insure the ImpliCit bit becomes zero IS to nght shift the slgnlflcand Id,v,de by 2)
and Increment the exponent Imultlply by 21 Thus, the exponent ends up With the interpretatIOn of 2 - 126 or 2 -1022
The format for denormallzed numbers IS

o non-zero

Note that zero may be conSidered a special case of denormallzed numbers where the number IS so small that the slgnlitcand has
been reduced to zero.

Examples:
Single:
1.0x2- 128 =0.25x 2- 126 =$00 20 00 00
Double.
1.0x2-1025=0.125x2-1022= $00 02 00 00 00 00 00 00

4-402
MC68A39-MC68B39

NOT A NUMBER (NAN)

A number containing a NAN ,nd,cates that the number IS not a vahd floating number NANs can be used to Inltlahze areas In
memory to Indicate they have not had a vahd floating pOint number stored In them They are also created by the MC6839 to Indicate
that an operation could not return a vahd result.
The format for a NAN has the largest allowable exponent, a non-zero slgnlflcand, and an undefined sign As an Implementation
feature (not required by the IEEE Proposed Floating POint Standard), the non-zero fraction and undefined sign are further defined

Id 11111... 1111 It I operation address 00 0000

d' 0= ThiS NAN has never entered Into an operation with another NAN
1 = ThiS NAN has entered Into an operation with other NANs
t: 0= ThiS NAN Will not necessanly cause an Invahd operation trap when operated upon.
1 = ThiS NAN Will cause an Invahd operation trap when operated upon (trapping NAN)

Operation address'
The 16 bits, Immediately to the nght of the t bit, contain the address of the Instruction Immediately follOWing the call to the FP
package of the operation that caused the NAN to be created If d (double NAN) IS also set, the address IS arbltranly one of the
addresses In the two or more offending NANs

•
SPECIAL VALUES (EXTENDED FORMAT)

ZERO
Zero IS represented by a number With the smallest unbiased exponent and a zero slgnlflcand

o
INFINITY
Infinity has the maximum unbiased exponent and a zero slgnlflcand

I s 1011111 o
DENORMALIZED NUMBERS
Denormahzed numbers have the smallest unbiased exponent and a non-zero slgnlflcand

Is 1100 000 10 non-zero

The exponent of denormahzed extended and Internal numbers IS Interpreted as haVing the exponent value 1 greater than the
smallest unbiased exponent value Thus, a denormahzed number has the exponent - 16384, but has the value
(-l)Sx 2-16383xO.f

Example'
10x2-16387=0625x2- 16383=$40 00 08 00 00 00 00 00 00 00

NANs
NANs have the largest unbiased exponent and a non-zero slgnlflcand The operation addresses "t" and "d" are Implementation
features and are the same as for slngle- and double-formats

operation addr I OOOOOOOO I

The operation address always appears In the 16 bits Immediately to the nght of the t bit

4-403
 MC68A39·MC68B39

UNNORMALZIED NUMBERS
Unnormalized numbers occur only in extended or Internal format. Un normalized numbers have an ex~onent greater than the
minimum In the extended format h.e., they are not denormallzed or normal zero) but the expliCit leading bit IS a zero. If the slgnlfl-
cand is zero, this is an unnormalized zero. Even though unnormallzed numbers and denormalized numbers are handled similarly in
most cases, they should not be confused. Denormalized numbers are numbers that are very small - have minimum exponent -
and hence have lost some bits of significance. Unnormalized numbers are not necessarily small (the exponent may be large or small)
but the significand has lost some bits of significance, hence, the explicit bit and pOSSibly some of the bits to the right of the expliCit
bit are zero.
I s I > 100... 000 10. significand

Note that unnormallzed numbers cannot be represented - and hence cannot exist - for single- and double-formats. ·Unnor-
malized numbers can only be created when denormalized numbers In single- or double-format are represented In extended or inter-
nal formats.

Example:
.0625 x 22 (unnorm.) = $00 02 OS 00 00 00 00 00 00 00

MC6839 CALLING SEQUENCE AND OPCODE REFERENCE TABLE

Function Opcode Register Calling Sequence Stack Calling Sequence 1

FADD $00 U-Addr of Argument #1 Push Argument #1
FSUB $02 Y-Addr of Argument #2 Push Argument #2
FMUL $04 D-Addr of FPCB Push Addr of FPCB
FDIV $06 X - Addr of Aesult LBSA FPSTAK

I FAEM
FSQAT
FINT
FFIXS
$OB
$12
$14
$16
LBSA FPAEO
FCB <opcode>
Y - Addr of Argument
D- Addr. of FPCB
X - Addr of Aesult
LBSA FPAEG
FCB <opcode>
Pull Aesult
Push Argument
Push Addr of FRCB
LBSA FPSTAK
FCB <opcode>
FFIXD $18 FCB <opcode> Pull Aesult
FAB $IE
FNEG $20
FFLTS $24
FFLTD $26
FCMP $8A U-Addr of Argument #1 Push Argument #1
FTCMP $CC Y-Addr of Argument #2 Push Argument #2
FPCMP $8E D-Addr of FPCB Push Parameter Word
FTPCMP $00 X - Parameter Word Push Addr of FPCB
LBSA FPAEG LBSA FPSTAK
FCB < opcode> FCB <opcode>
Pull Result (If predicate compare)
NOTE Result returned In the CC register For NOTE Result returned In the CC register for
predicate compares the Z-Blt IS set If predicate regular compares For predicate compares a one
ISaffirmed cleared If disaffirmed byte result IS returned on the top of the stack
The result IS zero If affirmed and - 1I$FFI If
disaffirmed
FMOV $9A U - PreCIsion Parameter Word Push Argument
Y - Addr of Argument Push PrecIsion Parameter Word
D-Addr of FPCB Push Addr of FPCB
X - Addr of Aesult LBSA FPSTAK
LBSA FPAEG FCB < opcode >
FCB < opcode> Pull Result
BINDEC $IC U - k 1# of digits In resultl Push Argument
Y - Addr of Argument Push k
D-Addr of FPCB Push Addr of FPCB
X - Addr of DeCimal Result LBSA FPSTAK
LBSR FPAEG FCB <opcode>
FCB < opcode > Pull BCD Stnng
DECBIN $22 U - Addr of BCD Input Stnng Push Addr of BCD Input Stnng
D-Addr of FPCB Push Addr of FPCB
X - Addr of Binary Aesult LBSA FPSTAK
LBSA FPAEG FCB < opcode >
FC B < opcode > Pull Binary Aesult

1All arguments are pushed on the stack least-significant bytes first so that the high-order byte IS always pushed last and reSides In the
lowest address
Entry POints to the MC6839 are defined as follows
FPAEG = ADM start + $30
FPST AK = ADM start + $3F

4·404
MC68A39-MC68B39

MC6B39 EXECUTION TIMES

Time in ~. Using 2 MHz 6809

Single Double Extended

Function Precision Precision Precision
FADD 1200-3300 1500- 3700 1100-3800
t= 1200+40IA) + 501N) t= 1500+40IA) + 501N) t= 1100+40IA) + 501N)
where
A = , shifts to align operands
N = # shifts to normalize result
FSUB ADD+11 ADD+ 11 ADD+11
FMUL 1400-1500 4100-4300 4500-4800
FDIV t- 2700+ 6010) t-6000+60IOI 5-6500+ 6010)
where
Q =# of quotient bits which are
are a '1'
FABS 540 750 650
DECBIN 8500-14,000 8500 - 23,000 -
(time depends on magnitude
of Input)

•
BINDEC 35,000-48,000 67,000-85,000 -
(time depends on # slgnlflcand
digits requested)

4·405
 MC6840
(1.0 MHz)

® MOTOROLA MC68A40
MC68B40
(1.5 MHz)

12.0 MHzl

PROGRAMMABLE TIMER MODULE (PTM)

MOS
The MC6840 IS a programmable subsystem component of the M6800
family designed to provide vanable system time Intervals.
IN-CHANNEL, SILICON-GATE
The MC6840 has three 16-blt binary counters, three corresponding DEPLETION LOAD)
control registers, and a status register. These counters are under soft-
ware control and may be used to cause system Interrupts and I or
generate output signals. The MC6840 may be utilized for such tasks as
PROGRAMMABLE TIMER
frequency measurements, event counting, Interval measuring, and
similar tasks The device may be used for square wave generation,
gated delay signals, single pulses of controlled duration, ~nd pulse

~
width modulation as well as system Interrupts
• Operates from a Single 5 Volt Power Supply
• Fully TTL Compatible LSUFFIX
, ' .' CERAMIC PACKAGE
• Single System Clock ReqUired (Enablel I II J, ' CASE 719
• Selectable Prescaler on Timer 3 Capable of 4 MHz for the MC6840,
6 MHz for the MC68A40 and 8 MHz for the MC68B40

~
• Programmable Interrupts (lRQI Output to MPU
• Readable Down Counter Indicates Counts to Go Until Time-Out

•
• Selectable Gating for Frequency or Pulse-Width Comparison PSUFFIX
PLASTIC PACKAGE
• RESET Input CASE 710
• Three Asynchronous External Clock and GatelTrigger Inputs

~
Internally Synchronized
• Three Maskable Outputs

~" SSUFFIX
' . CEROIP PACKAGE
, CASE 733

MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage VCC -03to +70 V
FIGURE 1 - PIN ASSIGNMENT
Input Voltage V ,n -03to+70 V
Operating Temperature Range - T L to T h
MC6840, MC68A40, MC68840
TA
o to + 70 'C VSS
M C6840C, M C68A40C -40 to +85 C1
Storage Temperature Range Tstq -55 to + 150 'c G2 01
02 G1
THERMAL CHARACTERISTICS C2 DO
Characteristic Symbol Value Unit
G3 D1
Thermal ReSistance
Cerdlp 65 03 D2
8JA 'c/W
PlastiC 115 C3 D3
Ceramic 50
RESET D4
IRO D5
RSO D6
ThiS deVice contains CirCUitry to protect the Inputs agamst damage due to high
RSl D7
static voltages or electriC fields, however, It IS adVised that normal precautions
be taken to avoid application of any voltage higher than maximum rated voltages RS2
to thiS high-Impedance CirCUit Reliability of operatIOn IS enhanced If unused in-
R/W CSl
puts are tied to an appropriate logiC voltage level (e 9 , eIther VSS or Vee)
VCC csa

4·406
MC6840-MC68A40-MC68B40

FIGURE 2 - BLOCK OIAGRAM

R/W RSO RS1 RS2 CSo CS1 f (Enablel

I
M

g~
< ..
o •
ua:

_1
RESET G3 C3 03 G2 C2 02 err C1 01

POWER CONSIOERATIONS

The average chip-Junction temperature. TJ. m °c can be obtamed from

T J=TA + (PO o8JA) (1)
Where.
TA-Amblent Temperature. °c
8JA- Package Thermal Resistance. Junction-to-Amblent. °C/W
PD" PINT + PPORT
PINT-ICCxVCC. Watts - Chip Internal Power
PPORT=Port Power DIssipation. Watts - User Determmed
For most apphcatlons PPORT<C PINT and can be neglected. PPORT may become significant If the deVice IS configured to
drive Darhngton bases or smk LED loads
An approximate relationship between PD and TJ (If PPORT IS neglected) IS
PD= K- (T"'j + 273°C) (2)
Solving equations 1 and 2 for K gives.
I<l PDo (TA+273°C)+8JAo PD 2 (3)
Where K IS a constant pertaining to the particular part K can be determmed from equation 3 by measuring PD (at eqUlhbrlum)
for a known T A Usmg thiS value of K the values of PD and TJ can be obtained by solving equations (1) and (2) IteratIVely for any
value of TA.

4-407
 MC6840-MC68A4OeMC68B40

DC ELECTRICAL CHARACTERISTICS (VCC=50 Vdc ±5% VSS=O TA=TL to TH unless otherwise notedl
Characteristic Symbol Min Typ Max Unit
Input High Voltage VIH VSS+ 20 - VCC V
Input Low Voltage VIL VSS 03 VSS+08 V
Input Leakage Current (V,n=O to 5 25 VI lin - 10 25 pA
Three-State (011 Statel Input Current (V,n = 05 to 24 VI 00-07 ITS I - 20 10 pA
Output High Voltage
II Load = -205pAI 00-07 VOH VSS + 2 4 - - V
II Load = - 200 pAl Other Outputs VSS + 2 4 - -
Output Low Voltage
II Load = 16 mAl 00-07 VOL - - VSS+04 V
(ILoad = 32 mAl 01-03, IRQ - - VSS+04
Output Leakage Current (Off Statel (VOH = 24 VI iRll ILOH - 10 10 pA
Internal Power DIssipation IMeasured at TA- TLI PINT - 470 700 mW
Input Capacitance
IV,n=O, T A =25'C, 1= 1 a MHzI 00-07 Crn - - 125 pF
All Others - - 75
Output Capacitance -
IV ,n oo O,TA=25'G,f=10MHzl IRQ Cout - - 50 pF
01 02 03 - - 10

• AC OPERATING CHARACTERISTICS (See Figures 4 91

Characteristic

Input Rise and Fall Times

(Figures 4 and 51 C, G and RESET
Input Pulse Width Low (Figure 41
..0s.rnchronous Input)
Symbol

tr,tf

PWL
Min

-
MC6840

tcycE + tsu + thd

Max

10·

-
MC68A40
Min

teyeE + tsu + thd

Max

0666·

-
MC68B40
Min

-
Max

teyeE: + tsu + thd

0500·

-
Unit

pS

ns
C, G and RESET
Input Pulse Width High (Figure 51
PWH teyeE + tsu + thd - teyeE + tsu + thd -
teyeE + tsu + thd - ns
IAsynchronous Inputl C, ~
Input Setup Time (Figure 6)
ISynchronous Inputl tsu 200 - 120 - 75 - ns
C, G and RESET
Input Hold Time IFlgure 61
l§~chronous Input) thd 50 - 50 - 50 - ns
C, G and RESET
Input Synchronization Time (Figure 9)
t sync 250 - 200 - 175 - ns
C3 (- 8 Prescaler Mode Onlyl
Input Pulse Width
PWL, PWH 120 - 80 - 60 - ns
C3 1-8 Prescaler Mode Onlyl
Output Delay, 01-03 (Figure 71
IVOH=2 4 V, Load BI TTL teo - 700 - 460 - 340 ns
IVOH = 24 V, Load 01 MOS tern - 450 - 450 - 340 ns
(VOH =07 VOO, Load 01 CMOS temos - 20 - 135 - 10 pS
Interrupt Release Time tlR - 12 - 09 - o7 ps

4-408
MC6840- MC68A40-MC68B40

BUS TIMING CHARACTERISTICS ISee Notes 1 2 and 31

Ident. MC6840 MC68A40 MC68B40
Number
Charactenstic Symbol Unit
Min Max Min Max Min Max
1 Cycle Time tm 10 10 067 10 05 10 ~s

2 Pulse Width, E Low PWEL 430 9500 280 9500 210 9500 ns
3 Pulse Width, E High PWEH 450 9500 280 9500 220 9500 ns
4 Clock R158 and Fall Time tr,tf - 25 - 25 20 ns
9 Address Hold Time tAH 10 - 10 - 10 - ns
13 Address Setup Time Before E tAS 80 - 80 - 40 - ns
14 Chip Select Setup Time Before E tcs 80 - 60 - 40 - ns
15 Chip Select Hold Tln)e tCH 10 - 10 - 10 - ns
18 Read Data Hold Time lJl..HR 20 50> 20 50> 20 50> ns
21 Wnte Data Hold Time tDHW 10 - 10 - 10 - ns
30 Peripheral Output Data Delay Time tDDR - 290 - 180 - 150 ns
31 Peripheral Input Data Setup Time tDSW 165 80 60 ns
"The data bus output buffers are no longer sourCing or sinking current by tOHR max (High Impedance)

FIGURE 3 - BUS TIMING

•
E
~----------~3'-----------~

R/VV,Addr~s--~~~~~~~~~--------'7~~-----rt---------------------------------~~~~
(Non-Muxedl _____t~~~~~~~~--------~~~----_t1_----------------------------------1_~~~~

cs----+-~------------------~

Read Data -----+---.L MPU Read Data Non·Muxed

Non-Muxed -----+--~~~------------~~~~~~~~~~--------------1t:::::j~--_:~--4_~~~

Write Data ----...!.---.L.. MPU Write Data Non-Muxed

Muxed P-----------------------~~~--------------------~~--~
"JL---'I"-----:=:-t----'f"

FIGURE 4 - INPUT PULSE WIDTH LOW FIGURE 5 - INPUT PULSE WIDTH HIGH

C1-C3
G1-63 C1-C3
RESET
G1-G3

NOTES
1 Not all signals are BlJpllCable to every part
2 Voltage levels shown are V L:S 0 4 V, VH ~ 2 4 V, unless otherwise specified
3 Measurement pOints shown are 0 8 V and 2 0 V, unless otherwise specified

4-409
 MC~MC~A~MC~B~

FIGURE 6 - INPUT SETUP AND HOLD TIMES FIGURE 7 - OUTPUT OELAV

E-4 IL \
t~. ~':~----

C'iT3, IT-'G3.
RESET >t
01-03

----
~

* tcmos '" a 7 x Vee

FIGURE 8 - IRQ RELEASE TIME

•
FIGURE 9- C3 INPUT SVNCHRONIZATION TIME (+ B PRESCALER MODE ONL V)

,.. Cycle N Cycle N + 1

Enable \!"'______.!
. . Ic,.--------:.I __--'I

t I
t t Transitions Processed Durmg N + 1 TX
Transitions Processed Dunng N

FIGURE 10 - BUS TIMING TEST LOADS

Load B Load C
Load A
(Q1,02,03) (IRQ Only)
(00-07)
(TTL Load)
5 av Vee of device under test 50V

MMD6150
Test POint 0--.-.--11+--+
RL == 1.25 k

MMD6150
~ 3 k

or Equlv or Equlv
Testpo'nt~
MMD 7000
or EqUiv
40 pF 11.7 k
MM070DO
or Equlv 100 pF I
Load D
(01,02,03)
(CMOS Load)
(MOS)

NOTE Timing measurements are referenced to and from a low voltage of 0 8 volts and a high voltage of 2 0 volts, unless otherwise noted

4·410
MC~MC~A~MC~B~

DEVICE OPERATION

The MC6840 IS part of the M6800 microprocessor family "open drain" output (no load deVice on the chip) which per-
and IS fully bus compatible With M6800 systems. The three mits other Similar Interrupt request hnes to be tied together In
timers In the MC6840 operate Independently and In several a Wire-OR configuration
distinct modes to fit a wide variety of measurement and syn- The IRQ hne IS activated If, and only If, the Composite In-
thesIs apphcatlons terrupt Flag (Bit 7 of the Internal Status Register) IS asserted
The MC6840 IS an Integrated set of three distinct The conditions under which the '"i'RQ line IS activated are
counter/timers (Figure 1) It consIsts of three 16-blt data discussed In conjunction With the Status Register
latches, three 16-blt counters (clocked Independently), and
the comparison and enable circuitry necessary to Implement RESET - A low level at thiS Input IS clocked Into the PTM
various measurement and synthesis functions. (n addition, It by the E (Enable) Input Two Enable pulses are reqUired to
contains Interrupt drivers to alert the processor that a par- synchrOnize and process the signal The PTM then
ticular function has been completed recognizes the active "low" or Inactive "high" on the third
In a typical apphcatlOn, a timer Will be loaded by first stor- Enable pulse. If the RESET signal IS asynchronous, an addi-
Ing two bytes of data Into an associated Counter Latch. ThiS tional Enable period IS required If setup times are not met
data IS then transferred Into the counter via a Counter In- The RESET Input must be stable High/Low for the minimum
Itiahzatlon cycle. If the counter IS enabled, the counter time stated In the AC Operating Characteristics
decrements on each subsequent clock period which may be Recognition of a low level at thiS Input by the PTM causes
an external clock, or Enable (E) until one of several predeter- the follOWing action to 'Occur
mined conditions causes It to halt or recycle The timers are a All counter latches are preset to their maximum count
thus programmable, cychc In nature, controllable by external values
Inputs or the MPU program, and acceSSible by the MPU at b All Control Register bits are cleared With the exception

•
any time of CR10 Ilnternal reset bill which IS set
c All counters are preset to the contents of the latches
BUS INTERFACE
d All counter outputs are reset and all counter clocks are
The Programmable Timer Module IPTM) Interfaces to the
disabled
M6800 Bus With an 6-blt bidirectIOnal data bus, two Chip
Select hnes, a Read/Write hne, a clock (Enable) hne, and In- e All Status Register bits (Interrupt flags) are cleared
terrupt Request hne, an external Reset hne, and three
Register select hnes VMA should be utlhzed In conjunction REGISTER SELECT LINES (RSO, RS1, RS2) - These In-
With an MPU address hne Into a Chip Select of the PTM puts are used In conjunction With the R/W hne to select the
when uSing the MC6800/6B02/6808. Internal registers, counters and latches as shown In Table 1

BIDIRECTIONAL DATA (00-07) - The bidirectIOnal data NOTE:

hnes (00-07) allow the transfer of data between the MPU The PTM is accessed via M PU Load and Store operations
and PTM The data bus output drivers are three-state in much the same manner as a memory device. The instruc-
deVices which remain In the high-Impedance (off) state ex- tions available with the M6800 family of MPUs which per-
cept when the M PU performs a PTM read operation form read-modify-write operations on memory should not be
(Read/Write and Enable hnes high and PTM Chip Selects ac- used when the PTM is accessed. These instructions actually
tIVated) fetch a byte from memory, perform an operation, then
restore it to the same address location. Since the PTM uses
CHIP SELECT (CSO, CS1) - These two signals are used the R/W line as an additional register select input, the
to actIVate the Data Bus Interface and allow transfer of data modified data will not be restored to the same register if
from the PTM With CSO=O and CS1=1, the deVice IS these instructions are used.
selected and data transfer Will occur
CONTROL REGISTER
READ/WRITE (R/W) - ThiS signal IS generated by the Each timer In the MC6840 has a corresponding write-only
MPU to control the direction of data transfer on the Data Control Register Control Register #2 has a unique address
Bus With the PTM selected, a low state on the PTM R/W space (RSO= 1, RS =0, RS2= Ol and therefore may be Writ-
hne enables the Input buffers and data IS transferred from the ten Into at any time The remaining Control Registers 1#1 and
M PU to the PTM on the tralhng edge of the E (Enable) clock #3) share the Address Space selected by a logiC zero on al!
Alternately, (under the same conditIOns) R/W = 1 and Register Select Inputs
Enable high allows data In the PTM to be read by the MPU.
CR20 - The least-Significant bit of Control Register #2
ENABLE (E CLOCK) - The E clock signal synchrOnizes (CR20) IS used as an additIOnal addreSSing bit for Control
data transfer between the MPU and the PTM It also per- Registers #1 and #3 Thus, With all Register selects and R/W
forms an eqUivalent synchronization function on the external Inputs at logiC zero, Control Register #1 Will be written Into If
clock, reset, and gate Inputs of the PTM CR20 IS a logiC one Under the same conditions, Control
Register #3 can also be written Into after a RESET low condi-
INTERRUPT REQUEST (mo) - The active low Interrupt tion has occurred, since all control register bits (except
Request signal IS normally tied directly (or through PriOrity In- CR10l are cleared Therefore, one may write In the sequence
terrupt circUitry) to the IRQ Input of the MPU ThiS IS an CR3, CR2, CR1

4-411
 TABLE 1 - REGISTER SELECTION

Register
Select Inputs Operations
RS2 RS1 RSO R/W=O RIW= 1

0 0 0
CR20 = a Write Control Register #3 No Operation
--------------------------
CR20 = 1 Write Control Register #1
a a 1 Wnte Control Register #2 Read Status Register
a 1 a Write MSB Buffer Register Read Timer #1 Counter
a 1 1 Write Timer #1 Latches Read LSB Buffer Register
1 a 0 Write MSB Buffer Register Read Timer #2 Counter
1 a 1 Write Timer #2 Latches Read LSB Buffer Register
1 1 a Wnte MSB Buffer Register Read TImer #3 Counter
1 1 1 Wnte Timer #3 Latches Read LSB Buffer Register

CR10 - The least-significant bit of Control Register #1 IS The least-slgnlfcant bit of Control Register #3 is used as a
used as an Internal Reset bit. When this bit IS a logic zero, all selector for a - 8 prescaler which IS available With Timer #3
timers are allowed to operate In the modes prescribed by the only The prescaler, If selected, IS effectively placed between
remaining bits of the control registers Writing a "one" Into the clock Input circuitry and the Input to Counter #3. It can
CR10 causes all counters to be preset with the contents of therefore be used With either the Internal clock (Enablel or an
the corresponding counter latches, all counter clocks to be external clock source

II
disabled, and the timer outputs and Interrupt flags (Status
Register) to be reset Counter Latches and Control Registers
are undisturbed by an Internal Reset and may be written Into CR30 - The functions depicted In the foregOing diSCUS-
,regardless of the state of CR10 sions are tabulated In Table 2 for ease of reference

TABLE 2 - CONTROL REGISTER BITS

CRxr Timer #X Counter Output Enable

a TX Output masked on output OX
1 TX Output enabled on output OX

CRX6 llmer IX Interrupt Enable

a Interrupt Flag masked on IRO
1 Interrupt Flag enabled to IRO

. \ 1;"'j~"" 1,,00, " Cooo", M,", '"" '00"'"'' CooO", "eo "." " J

Control Register X I 7 6 I I I I
5 4 3 21 1 I aI x ~ 1, 2 or 3

CRX2
0
Timer #X Counting Mode Control /~
TX configured for normal (16-bltl counting mode
1 TX configured for dual 8~blt counting mode

CRXI Timer #X Clock Source

0 TX uses external clock source on CX Input
1 TX uses Enable clock

CR 10 Internal Reset Bit CR20 Control Register Address Bit CR30 Timer #3 Clock Control
a All timers allowed to operate 0 CR#3 may be written 0 T3 Clock IS not prescaled
1 All timers held In preset state 1 CR#l may be written 1 T3 Clock IS presealed by ~ 8
X~1 X 2 X~3

4·412
MC6840· MC68A40. MC68840

Control Register Bits CR10, CR20, and CR30 are unique m An mterrupt flag IS cleared by a Timer Reset condition,
that each selects a different function The remammg bits 11 Ie, External RESET=O or Internal Reset Bit ICR10)=1 It
through 7) of each Control Register select common func- will also be cleared by a Read Timer Counter Command pro-
tions, with a particular Control Register affecting only Its cor- vided that the Status Register has previously been read while
respondmg timer the mterrupt flag was set ThiS condition on the Read Status
Register-Read Timer Counter IRS-RT) sequence IS deSigned
CRX1 - Bit 1 of Control Register #1 I CR 11) selects to prevent missing Interrupts which might occur after the
whether an Internal or external clock source IS to be used status register IS read, but prior to readmg the Timer
with Timer #1 Similarly, CR21 selects the clock source for Counter
Timer #2, and CR31 performs this function for Timer #3 The An Individual Interrupt Flag IS also cleared by a Write
function of each bit of Control Register "X" can therefore be Timer Latches IW) command or a Counter Initialization ICII
defined as shown In the remalnmg section of Table 2 sequence, provided that W or CI affects the Timer cor-
respondmg to the md,vldual Interrupt Flag
CRX2 - Control Register Bit 2 selects whether the binary
mformatlon contamed m the Counter Latches land subse- COUNTER LATCH INITIALIZATION
quently loaded Into the counter! IS to be treated as a smgle Each of the three ,ndependent timers consists of a 16-blt
16-blt word or two 8-blt bytes In the smgle 16-blt Counter addressable counter and a 16-blt addressable latch The
Mode ICRX2=0) the counter will decrement to zero after counters are preset to the binary numbers stored In the ,atch-
N + 1 enabled IG = 01 clock periods, where N IS defined as the es Counter InitialIZation results In the transfer of the latch
16-blt number In the Counter Latches With CRX2 = 1, a contents to the counter See notes In Table 4 regardmg the
similar Time Out will occur after IL+ 1I·IM + 1) enabled binary number N, L, or M placed mto the Latches and their
clock periods, where Land M, respectively, refer to the LSB relationship to the output waveforms and counter Tlme-
and MSB bytes m the Counter Latches Outs

•
Since the PTM data bus IS 8-blts wide and the counters are
CRX3-CRX7 - Control Register Bits 3, 4, and 5 are ex- 16-blts wide, a temporary register IMSB Buffer Register) IS
plamed m detail In the Timer Operating Mode section Bit 6 IS provided ThiS "write only" register IS for the Most-
an Interrupt mask bit which will be explained more fully In Significant Byte of the deSired latch data Three addresses
conjunction with the Status Register, and bit 7 IS used to are provided for the MSB Buffer Register las mdlcated In
enable the corresponding Timer Output A summary of the Table 11, but they all lead to the same Buffer Data from the
control register programm.ng modes IS shown m Table 3 MSB Buffer Will automatically be transferred Into the Most-
Significant Byte of Timer #X when a Write Timer #X Latches
Command IS performed So It can be seen that the MC6840
STATUS REGISTER/INTERRUPT FLAGS has been deSigned to allow transfer of two bytes of data Into
The MC6840 has an mternal Read-Only Status Register the counter latches provided that the MSB IS transferred
which contams four Interrupt Flags IT he remBlnlng four bits first The storage order must be observed to ensure proper
of the register are not used, and defaults to zeros when be- latch operation
Ing read) Bits 0, 1, and 2 are assigned to Timers 1, 2, and 3, In many applications, the source of the data Will be an
respectively, as Individual flag bits, while Bit 71s a Composite M6800 Family MPU It should be noted that the 15-blt store
Interrupt Flag ThiS flag bit will be asserted If any of the m- operations of the M6800 family microprocessors ISTS and
dlvldual flag bits IS set while Bit 6 of the corresponding Con- STXI transfer data m the order reqUired by the PTM A Store
trol Register IS at a logiC one The condltlOriS for asserting Index Register Instruction, for example, results In the MSB
the composite Interrupt Flag bit can therefore be expressed of the X register being transferred to the selected address,
as then the LSB of the X register bemg written Into the next
INT = 11·CR 16+ 12·CR26+ 13·CR36 higher location Thus, either the mdex register or stack
pOinter may be transferred directly Into a selected counter
where INT = Composite Interrupt Flag IBlt 7) latch With a single mstructlon
11 = Timer #1 Interrupt Flag IBlt 01 A logiC zero at the RESET Input also Initializes the counter
12= Timer #2 Interrupt Flag IBlt 11 latches In thiS case, all latches Will assume a maximum
13= Timer #3 Interrupt Flag IBlt 2) count of 65,53510 It IS Important to note that an Internal

CRX4 TABLE 3 - PTM OPERATING MODE SELECTION

CRX3-, I r CRX5
0 0 ~ ontlnuous Operating Mode Gate I or Write to Latches or Reset Cause:; Counter Initialization
fa fa ~ Frequency Comparison Mode Interrupt If Gate ~ls<Counter Time Out
'0 r,-- o Continuous Operating Mode Gate I or Reset Causes Counter Initialization
fa r,-- ~ Pulse Width Comparison Mode Interrupt If Gate ~ Counter Time Out
IS<
r;- ca ~ Single Shot Mode Gate l or Write to Latches or Reset Causes Counter Initialization
r,- fa ~ Frequency Comparison Mode Interrupt If Gate LI+ Counter Time Out
IS>
f-;'- r, o Single Shot Mode Gate I or Reset Causes Counter Initialization
r,-r,- r,- Pulse Width Comparison Mode Interrupt If Gate ~ Counter Time Out
IS>

4-413
 MC6840- MC68A40-MC68B40

Reset (Sit zero of Control Register 1 Set) has no effect on CLOCK INPUT C3 (- 8 PRESCALER MODE) - External
the counter latches. clock Input C3 represents a speCial case when Timer #3 IS
programmed to utilize ItS optional - 8 prescaler mode
COUNTER INITIALIZATION The dlvlde-by-8 prescaler contains an asynchronous ripple
Counter Initialization IS defined as the transfer of data from counter, thus, Input setup (tsul and hold times (thd) do not
the latches to the counter with subsequent clearing of the In- apply As long as minimum Input pulse Widths are maintain-
dividual Interrupt Flag associated With the counter. Counter ed, the counter Will recognize and process all Input clock
Initialization always occurs when a reset condition (0) transitions However, In order to guarantee that a clock
(RESET=O or CR10=1) IS recognized. It can also occur- transition IS processed dUring the current E cycle, a certain
depending on Timer Mode - With a Wnle Timer Latches
amo~t of synchronization time (tsync) IS reqUired between
command or recognition of a negative transition of the Gate
the C3 transition and the failing edge of Enable (see Figure
input.
9) If the synchrOnization time requirement IS not met, It IS
Counter recycling or re-Inltlallzatlon occurs when a
pOSSible that the C3 transition Will not be processed until the
negative transition of the clock Input IS recognized after the
counter has reached an all-zero state In thiS case, data IS follOWing E cycle
transferred from the Latches to the Counter The maximum Input frequency and allowable duty cycles
for the - 8 prescaler mode are speCified under the AC
ASYNCHRONOUS INPUT/OUTPUT LINES Operallng Characteristics Internally, the -8 prescaler out-
Each of the three timers Within the PTM has external clock put IS treated In the same manner as the preViously discussed
and gate Inputs as well as a counter output line The Inputs clock Inputs
are high-Impedance, TTL-compatible lines and ouputs are
capable of driving two standard TTL loads GATE INPUTS (G1, G2, G3) - Input pins G1, G2, and G3
accept asynchronous TTL-compatible Signals which are used
CLOCK INPUTS (C1, C2, and C3) - Input pins C1, C2, as triggers or clock gating functions to Timers 1, 2, and 3,

II
and C3 will accept asynchronous TTL voltage level Signals to respectively The gating Inputs are clocked Into the PTM by
decrement Timers 1, 2, and 3, respectively The high and low the E (enable) clock In the same manner as the preViously
levels of the external clocks must each be stable for at least discussed clock Inputs That IS, a Gate transition IS recogniz-
one system clock period plus the sum of the setup and hold ed by the PTM on the fourth Enable pulse (prOVided setup
times for the clock Inputs The asynchronous clock rate can and hold time requirements are met), and the high or low
vary from dc to the limit Imposed by the Enable Clock Setup,
levels of the Gate Input must be stable for at least one system
and Hold times
clock penod plus the sum of setup and hold times All
The external clock Inputs are clocked In by Enable pulses
Three Enable periods are used to synchronize and process references to G transition In thiS document relate to Internal
the external clock The fourth Enable pulse decrements the recognition of the Input transition
Internal counter ThiS does not affect the Input frequency, It The Gate Inputs of all timers directly affect the Internal
merely creates a delay between a clock Input transition and 16-bIt counter The operation of G3 IS therefore Independent
Internal recognition of that transition by the PTM All of the - 8 prescaler selection
references to C Inputs In thiS document relate to Internal
recognition of the Input tranSItion Note that a clock high or TIMER OUTPUTS (01, 02, 03) - Timer outputs 01,02,
low level which does not meet setup and hold time speCifica- and 03 are capable of driVing up to two TTL loads and pro-
tions may reqUire an additIOnal Enable pulse for recognitIOn duce a defined output waveform for either Continuous or
When obserVing recurring events, a lack of synchronization Single-Shot Timer modes Output waveform definition IS ac-
will result In "Jitter" being observed on the output 01 the complished by selecting either Single 16-blt or Dual 8-blt
PTM when uSing asynchronous clocks and gate Input operating modes The Single 16-blt mode Will produce a
Signals There are two types of Jitter "System Jitter" IS the square-wave output In the continuous mode and a Single
result of the Input Signals being out of synchronization With pulse In the Single-shot mode The Oual 8-bIt mode Will pro-
Enable, permitting Signals With marginal setup and hold time duce a variable duty cycle pulse In both the continuous and
to be recognized by either the bit time nearest the Input tran- Single-shot timer modes One bit of each Control Register
sition or the subsequent bit time (CRX7) IS used to enable the corresponding output If thiS bit
"Input Jitter" can be as great as the time between Input IS cleared, the output Will remain low (VOL) regardless of the
Signal negative gOing transitions plus the system jitter, If the operating mode If It IS cleared while the output IS high the
first transition IS recognized dUring one system cycle, and output will go low dUring the first enable cycle follOWing a
not recognized the next cycle, 01 vice versa See Figure 11 wnle to the Control Register
The Continuous and Single-Shot Timer Modes are the
FIGURE 11 - INPUT JITTER only ones for which output response IS defined In thiS data
sheet Refer to the Programmable Timer Fundamentals and
Applications manual for a diSCUSSion of the output Signals In
other modes Signals appear at the outputs (unless
CRX7 = 0) dunng Frequency and Pulse Width comparison
modes, but the actual waveform IS not predictable In tYPical
Here
~ r- System applications
I-~J- BIt Time
~~___ Jitter
Output

4-414
MC6840- MC68A40- MC68B40

TIMER OPERATING MODES that the timer output IS enabled ICRX7; 1), either a square
The MC6840 has been designed to operate effectively In a wave or a variable duty cycle waveform will be generated at
wide variety of applications This IS accomplished by uSing the Timer Output, OX The type of output IS selected via
three bits of each control register ICRX3, CRX4, and CRX5) Control Register Bit 2
to define different operating modes of the Timers These Either a Timer Reset ICR10; 1 or External Reset; 0) con-
modes are divided Into WAVE SYNTHESIS and WAVE dition or Internal recognition of a negative tranSition of the
MEASUREMENT modes, and are outlined In Table 4 Gate Input results In Counter Initialization A Wrtle Timer
latches command can be selected as a Counter Initialization
TABLE 4 - OPERATING MODES Signal by clearing CRX4
Control Register
The counter IS enabled by an absence of a Timer Reset
Timer Operating Mode condition and a logiC zero at the Gate Input In the 16-blt
CRX3 CRX4 CRX5
mode, the counter will decrement on the flfst clock cycle
0 0 Continuous
Synthesizer dUring or after the counter Initialization cycle. It continues to
0 t Single-Shot decrement on each clock Signal so long as G remains low and
1 0 Frequency Comparison no reset condition eXists A Counter Time Out (the flfst clock
Measurement
1 1 Pulse Width Comparison after all counter bits; 0) results In the Individual Interrupt
Flag being set and relnltlallzatlon of the counter
-Defmes Additional Timer Function Selection
In the DualS-bit mode ICRX2; 1) [refer to the example In
Figure 12 and Tables 5 and 61 the M S B decrements once for
One of the WAVE SYNTHESIS modes IS the Continuous every full countdown of the LSB + 1 When the LSB; 0, the
Operating mode, which IS useful for cyclic wave generation MSB IS unchanged, on the next clock pulse the LSB IS reset
Either symmetrical or variable duty-cycle waves can be to the count In the LSB Latches, and the MSB IS
generated In this mode The other wave syntheSIS mode, the decremented by 1 lone) The output, If enabled, remains low
Single-Shot mode, IS Similar In use to the Continuous dUring and after Initialization and Will remain low until the
operating mode, however, a Single pulse IS generated, With a
programmable preset width
The WAVE MEASUREMENT modes Include the Frequen-
cy Comparison and Pulse Width Comparison modes which
are used to measure cycliC and singular pulse widths, respec-
tively
counter MSB IS all zeroes The output Will go high at the
beginning of the next clock pulse The output remains high
until both the LSB and MSB of the counter are all zeroes At
the beginning of the next clock pulse the defined Time Out
ITO) Will occur and the output Will go low In the Dual S-blt
mode the period of the output of the example In Figure 12
II
In addition to the four timer modes In Table 4, the remain- would span 20 clock pulses as opposed to 1546 clock pulses
Ing control register bit IS used to modify counter Inltlallzatton uSing the normal 16-blt mode
and enabling or Interrupt conditions A speCial time-out condition eXists for the dual S-blt mode
ICRX2; 1) If L;O In thiS case, the counter Will revert 10 a
mode Similar to the Single 16-blt mode, except Time Out oc-
WAVE SYNTHESIS MODES
curs after M + 1* clock pulses The output. If enabled, goes
CONTINUOUS OPERATING MODE (TABLE 5) - The low dUring the Counter Initialization cycle and reverse, state
continuous mode will syntheSize a continuous wave With a at each Time Out The counter remains cyclical liS re-
period proportional to the preset number In the particular Initialized at each Time Out) and the IndiVidual Interrupt Flag
timer latches Any of the timers In the PTM may be program- IS set when Time Out occurs If M; L; 0, the Internal
med to operate In a continuous mode by writing zeroes Into counters do not change, but the output toggles at a rate of
bits 3 and 5 of the corresponding control register Assuming Y, the clock frequency

TABLE 5 - CONTINUOUS OPERATING MOOES

Synthesis Modes I CONTINUOUS MODE

ICRX3 ~ 0, CRX5 ~ 0)
Control Register Initialization/Output Waveforms
CRX2 CRX4 Counter InltiaiJzation "Timer Output (OX) (CRX7 ~ 1)

- r-(N+1HT1T(N+l1(T1T(N+l)(T)1
0 0 Gl+W+R

- I I I I-VOH

VOL
0 1 GI+R I I
to TO TO TO

1 0
-
GI+W+R
r--( L +1 j(M +1) (Tl----t--( L +1) (M +1) (TI-----1
~-VOH

- I --IILlITI I-- - - I ILiITI r--vOL

1 1 GI+R
to TO TO

4-415
 MC684()e MC68A4Oe MC68B40

FIGURE 12 - TIMER OUTPUT WAVEFORM EXAMPLE

(Continuous Dual 8-Bit Mode Using Internal Enable)

Exampls' Contents of MSB = 03 "" M

Contents of LSB "" 04 = L

Counter Output
----.,
,I , __- - - - - - - MIL + 1) + 1 - - - - - - - - - t - - L

.1-------4--------'--------'~ I
Algebraic ExpreSSIon
03(04 + 1) + 1 =
16 Enable.
!.
I
I
====1====- 04 V
2 4 V

I
Enable
(System cp2)
I
1.'--1 + L - _
- _... o o-- 1 + J.'. L~
5 Enable 5 Enable I
Pulses Pulses Pulses I
I ~1+L
: I I I 5 Enable I
I I I I Puis.. I

1---1-------'---'-'--- 1M + 1' )(L + 1 1

11----4-t-------1 :

•
II
I I
li~ I II
H•
~ ~ f7.j
Algebraic Expression
(M + 1)(L + 1) "" Period
(04 + 1)(03 + 1) = 20 Enable or
M(L + 1) + 1 = Low portion of period
External Clock Pulses
L = Pulse width
·Preset LSB and MSB to Respective Latches on the negative transItion of the Enable
.. "Preset LSB to LSB Latches and Decrement MSB by one on the negative tranSition of the Enable

The diSCUSSion of the Continuous Mode has assumed that the counter results In the setting of an Individual Interrupt
the application reqUires an output signal It should be noted Flag and re-Inltlallzatlon of the counter
that the Timer operates In the same manner with the output The second major difference between the Single-Shot and
disabled (CRX7=01 A Read Timer Counter command IS Continuous modes IS that the Internal counter enable IS .10t
valid regardless of the state of CRX7 dependent on the Gate Input level reamlnlng In the low state
for the SIngle-Shot mode
SINGLE-SHOT TIMER MODE - ThiS mode IS Identical to Another special condition IS Introduced In the Single-Shot
the Continuous Mode with three exceptions The first of mode If L= M =0 (Dual 8-b,t) or N =0 (Single 16-bltl, the
these IS obVIOUS from the name - the output returns to a output goes low on the first clock received dUring or after
low level after the Initial Time Out and remains low until Counter InitializatIOn The output remains low until the
another Counter Initialization cycle occurs Operating Mode IS changed or nonzero data IS written Into
As indicated In Table 6, the Internal counting mechanism the Counter Latches Time Outs continue to occur at the end
remains cyclical In the Single-Shot Mode Each Time Out of of each clock period

TABLE 6 - SINGLE-SHOT OPERATING MODES

Synthesis Modes I SINGLE-SHOT MODE
(CRX3 = 0, CRX7 = 1, CRX5 = 11
Control Register InitIalization/Output Waveforms
CRX2 CRX4 Counter Initialization Time, Output (OX)

-
0 0 GI+W+R [j:::(N+111T1~IN+1I1Tll
I---(NIITI
I~ I
0 1 GI+R to TO TO

1 0 r(L+1I(M+1I(TI~(L+1I(M+11ITll
GI+W+R ---j (LI(TI
1 1
-
GI+R
to
n TO TO

Symbols are 35 defmed In Table 5.

4·416
 The three differences between Single-Shot and Conlinous generation until a new Counter Initialization cycle has been
Timer Mode can be summanzed as attnbutes of the Slngle- completed When thiS Internal bit IS set, a negative transition
Shot mode of the Gate Input starts a new Counter Initialization cycle
1. Output IS enabled for only one pulse until It IS relnillallz- (The condition of 131 ;r.TO IS satisfied, since a Time Out
ed has occurred and no individual Interrupt has been
2. Counter Enable IS Independent of Gate generated)
Any of the timers Within the PTM may be programmed to
3 L = M = 0 or N = 0 disables output
compare the penod of a pulse (giVing the frequency after
ASide from these differences, the two modes are Identical calculations) at the Gate Input With the time pe'lod re-
quested for Counter Time Out A negative transition of the
WAVE MEASUREMENT MODES Gate Input enables the cdJunter and starts a Counter In-
TIME INTERVAL MODES - The Time Interval Modes are Itialization cycle - provided that other conditions, as noted
the Frequency (penod) Measurement and Pulse Width Com- In Table 8, are satisfied The counter decrements on each
panson Modes, and are provided for those applicatIOns clock signal recognized dunng or after Counter Initialization
which require more flexibility of Interrupt generation and until an Interrupt IS generated, a Wnte Timer Latches com-
Counter Initialization Individual Interrupt Flags are set In mand IS Issued, or a Timer Reset condition occurs It can be
these modes as a function of both Counter Time Out and seen from Table 8 that an Interrupt condition Will be
transitions of the Gate Input Counter Initialization IS also af- generated If CRX5= 0 and the period of the pulse (Single
fected by Interrupt Flag status pulse or measured separately repetitive pulses) at the Gate
A timer's output IS normally not used In a Wave Measure- Input IS less than the Counter Time Out penod If CRX5 = 1,
ment mode, but It IS defined If the output IS enabled, It will an Interrupt IS generated If the reverse IS true
operate as follows Dunng the period between relnltlallzatlon Assume now With CRX5= 1 that a Counter Initialization
of the timer and the first Time Out, the output Will be a has occurred and that the Gate Input has returned low prior
logical zero If the first Time Out IS completed (regardless of
ItS method of generation), the output Will go high If further
TO's occur, the output Will change state at each completion
of a Time-Out
The counter does operate In either Single 16-blt or Dual
8-blt modes as programmed by CRX2 Other features of the
to Counter Time Out Since there IS no IndiVidual Interrupt
Flag generated, thiS automatically starts a new Counter In-
Itialization Cycle The process Will continue With frequency
comparison being performed on each Gate Input cycle until
the mode IS changed, or a cycle IS determined to be above
the predetermined limit
II
Wave Measurement Modes are outlined In Table 7
Pulse Width Comparison Mode (CRX3= 1, CRX4= 1)
Frequency Comparison Or Period Measurement Mode ThiS mode IS Similar to the Frequency Comparison Mode ex-
(CRX3= 1, CRX4= 0) - The Frequency Companson Mode cept for a POSitive, rather than negative, transition of the
With CRX5= liS straightforward If Time Out occurs prior to Gate Input termlntes the count With CRX5= 0, an IndiVidual
the first negative transition of the Gate Input after a Counter Interrupt Flag will be generated If the zero level pulse applied
Initialization cycle, and IndiVidual Interrupt Flag IS set The to the Gate Input IS less than the time period required for
counter IS disabled, and a Counter Initialization cycle cannot Counter Time Out With CRX5= 1, the Interrupt IS genereted
begin until the Interrupt flag IS cleared and a negative transI- when the reverse conditIOn IS true
tIOn on G IS detected As can be seen In Table 8, a positive tranSition of the Gate
If CRX5 = 0, as shown In Tables 7 and 8, an Interrupt IS Input disables the counter With CRX5= 0, It IS therefore
generated If Gate Input returns low prior to a Time Out If a pOSSible to directly obtain the Width of any pulse causing an
Counter Time Out occurs first, the counter IS recycled and Interrupt Similar data for other Time Interval Modes and
continues to decr'ement A bit IS set Within the timer on the conditions can be obtained, If two sections of the PTM are
Initial Time Out which precludes further Individual Interrupt dedicated to the purpose

FIGURE 7 - OUTPUT DELAY

CRX3 ~ 1
CRX4 CRX5 Application Condition for Setting IndiVidual Interrupt Flag
0 0 Frequency Comparison Interrupt Generated If Gate Input Penod (l/FI IS less
than Counter Time Out (TO)
0 1 Frequency Comparison Interrupt Generated If Gate Input Penod (l/F) IS greater
than Counter Time Out (TO)
1 0 Pulse Width Comparison Interrupt Generated If Gate Input "Down Time" IS less
than Counter Time Out (TO)
1 1 Pulse Width ComparISon Interrupt Generated If Gate Input "Down Time" IS greater
than Counter TIme Out (TO)

4-417
 MC6840- MC68A4()e MC68B40

TABLE 8 - FREQUENCY COMPARISON MODE

Control Reg. Counter Counter Enable Counter Enable Interrupt Flag

Mode Bit 3 Bit 4
Bit 5 Initialization Flip-Flop Set (CE) Flip-Flop Reset (CE) Set (I)
Frequency 1 0 0 m.I±rcr-+TOI+A (j);W·tr.1 W+A+I Gl Before TO
Companson 1 0 1 GI.I+A GI.W.A.I W+A+I TO Before GI
Pulse Width 1 1 0 GI.I+R GIW.A.I W+A+I+G Gt Before TO
Comparison 1 1 1 GI·I+A GI·W.A·I W+A+I+G Gt Before TO

GI = NegatIve transition of Gate Input

W = Write Timer Latches Command
A = Timer Reset (CA1O= 1 or External AESET = 0)
N = 16·B,t Number In Counter Latch
TO = Counter Time Out (All Zero Condition)
I = Interrupt for a given timer

ie}

•
• All time Intervals shown above assume the Gate (G) and Clock signals are sycnhronlzed to the system clock
(E) with the specIfied setup and hold time requirements

4-418
 ® MOTOROLA MC6843

FLOPPY DISK CONTROLLER (FOC)

The MC6843 Floppy Disk Controller performs the complex

MPU/Floppy Interface function The FDC was designed to optimize the MOl
balance between Hardware dnd Software in order to achieve Integration (N-CHANNEl, SILICON-GATEI
of all key functions and maintain flexibility.
The FDC can Interface a wide range of drives with a minimum of ex- FLOPPY DISK CONTROLLER
ternal hardware. Multiple dnves can be controlled with the addition of
external multiplexing rather than additional FDCs.
• Format Compatible with IBM 3740
• User Programmable Read/Write Format
• Ten Powerful "rIacro Commands
• Macro-End Interrupt Allows Parallel Processing of MPU and FDC
• Controls Multiple Floppies With External Multiplexing
• Direct Interface With M6800 Bus
• Programmable Step and Settling Times Enable Op&ratlon With a
Wide Range of Floppy Dnves
• Offers Both Program Controlled I/O IPCIOI and DMA Data Transfer
Mode
• Free-Format Read or Wnte
• Single 5-Volt Power Supply
• All Registers Directly AcceSSible
P SUFFIX
PLASTIC PACKAGE
CASE 711 II
FIGURE 1 - SYSTEM BLOCK DIAGRAM

20
!oj vee
MC6844 36
FIGURE 2 - PIN ASSIGNMENT
"'0
TxRO
J-!.- RO Floppy Disk

6;~~:n ( 21
25
TxAck
oCK
CLK Drive

~
BO Read TRZ
r- t-
('~ ~!l ~ I ~
(' VfOC Recover Read Data
DO
01 32
~
01 RO
02 .t:!!!~ ~ 02
ROT
Oa..
~ III 03 ~(/)dl ~ 03
'" 39

1 WOT Wnte Data FI

,il
m D4I $DE- t--:- WGT
6
Wnte Gate
WPT
c~~
D4

V
D6
t-"',il j--1L
07
~!£ ~
05
D6
07
i
(j
::;:
HOR
STP
B
15
Head Direction
Slep
WGT 6

HLO
16
Head Load RESET 7
iRci 37
IRQ LCT
10
Low Current Track HDR 8
CLK 12 3
eLK FIR
RESE' 7 File Inoperable Reset DCK 9 Dl
RESET
R/W 22 4
R/W FI File Inoperable
.2 23
E 5 lCT 10 D2
VMA WPT Wnte Protect
AO 19 11 IDX II D3
RSO lOX Index
AI lB
RSI 40 ClK 12 D4
A2 17 TRl Track Zero
RS2
A3 ,.-L. ~ CS VSS ROY
13
Ready RDY 13 D5
A4
AS VFOC 14
'l_J2
AS
STP 15
.!!"
A7
AS
A9 ~ HlD 16

~~
Ala RS2 17
All ·Optlonal Three-State Buffers
AI2 MC68EIl for Inverted Data RSI 18
AI3 MC6889 for Non-Inverted Data
AI4 RSO 1&
AI5
'--- VCC 20

4·419
 MC6843

MAXIMUM RATING

Rating Symbol Value Unit

Supply Voltage Vcc -03to +7.0 V ThiS device contams circuitry to protect the in-
Input Voltage Vin -03to +7.0 V puts against damage due to high static voltages
or electriC fields, however, It IS adVised that nor-
Operating Temperature Range TA o to + 70 °c
mal precautions be taken to avoid application of
Storage Temperature Range Tstg -55 to + 150 °c any voltage higher than maximum rated voltages
to thiS high-Impedance CircUIt. Reliability of
THERMAL CHARACTERISTICS operation IS enhanced If unused Inputs are tied to
an appropriate logic voltage level (e g" either
Characteristic VSS or VCC!
Thermal Aeslstance

POWER CONSIDERATIONS

The average Chip-Junction temperature, TJ, In °c can be obtained from:

TJ=TA+IPD-9JA) (1)
Where:
TA-Ambient Temperature, °c
8JA!&Package Thermal Resistance, Junction-to-Amblent, °C/W

•
PD"PINT+ PPORT
PINT-ICCxVCC, Watts - Chip Internal Power
PPORT- Port Power DiSSipation, Watts - User Determined
For most applications PPORT<C PINT and can be neglected. PPORT may become significant If the device IS configured to
drive Darlington bases or Sink LED loads.
An approximate relationship between PD and TJ Ilf PPORT IS neglected) IS'
PD=K+ITJ+273°C) 12)
Solving equations 1 and 2 for K gives:
K= PD-ITA + 273°C) +9JA-PD2 (3)
Where K IS a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD lat equilibrium)
for a known T A. USing thiS value of K the values of PD and TJ can be obtained by solVing equations (1) and (2) Iteratively for any
value of TA

FIGURE 3 - TEST LOADS

Load A Load B
IDO-D7i 111m onlyi

VCC VCC

Test
POint
MMD6150
or Equlv
AL=2.49k

Test
POint
~"'"''
C A MMD7000
or Equlv

I 100PF

c = 130 pF for DO-D7

= 30 pF for HLD, STP, HDR, LCT, WGT, FIR TxRQ, BD
R = 11 7 k for DO-D7
=24 k for HLD, STP, HDR, LeR, LCT, WGT, FIR TxRQ, BD

4·420
MC6843

DC ELECTRICAL CHARACTERISTICS IVCC =5 0 Vdc ±5%, VSS =0, TA=O to 70'C unless otherwise notedl

Characteristic Symbol Min Typ Max Unit

Input High Voltage VIH VSS + 20 - VCC V
Input low Voltage Vil VSS-03 - VSS+O 8 V
Input leakage Current IV in = 0 to 5 5 V) lin - 10 25 p.A
Three-State Input leakage Current IV in - 0 4 to 2 4 V, VCC - 5 5 V) 00-07 liZ 10 2.0 10 p.A
Output High Voltage
Ilload= -205p.A) 00-07 VOH VSS+24 - - V
Iiload= -100p.A) Other Outputs VSS+24 - -
Output low Voltage Iiload -1.6 mAl VOL - - VSS+O.4 V
Three-State Output leakage Current IVOH - 24 V) IRO IOZ - 10 10 p.A
Internal Power DIssipation IMeasured at T A - T l to TH) PINT - - 750 mW
Input Capacitance
IV in =OV, f= 1 0 MHz, T A=25'C) Enable - - 10
Cin pF
00-07 - - 125
All Others - - 10

•
Output Capacitance IV,n = 0 V, f = 1 0 MHz, TA = 25'C) All Outputs Cout - - 10 pF
Clock Pulse Width, low IClK) PWCl 400 - - ns
Clock Pulse Width, High IClK) PWCH 400 - - ns
Master Clock Penod IClK) tMC 10 - - P.s
Data Clock Pulse Width, low lOCK) PWDl 13 195 - P.s
Data Clock Pulse Width, High lOCK) PWDH 13 195 - P.s
Data Clock Penod lOCK) tDC 25 40 - p'S
Read Data to Data Clock Delay Time 1 tRDD1 055 10 - P.s
Read Data to Data Clock Delay Time 2 tRDD2 0.55 1.0 - p'S
Read Data Pulse Width, High tRDH - 10 - p'S
Read Data Pulse Width, low tRDl - 10 - P.s
Index Pulse Width, High PWIDX 10 - - P.s
Transfer Request Release Time tTR - - 450 ns
Interrupt Request Release Time tlR 12 P.s
Bus Direction Delay Time tDBD - 330 ns
Wnte Data Pulse Width, High Ifc= 1 0 MHz) PWWD - 10 - p's
Write Data Cycle Time Ifc - 1 0 MHz) tcycWD 20 p's
Step Pulse Width, High Ifc-1 0 MHz) PWSTP - 32 p's
Step Cycle Time" Ifc= 1 0 MHz) tcycSTP 10 - 15 ms
Write Gate to Write Data Delay ISSW, SWD, MSW) tGD1 07 10 13 p's
Wnte Gate Hold Time tGH 0 - 0.3 p's
Write Gate to Write Data Delay IFFW) tGD2 02 20 p's
ClK to iRQ Delay tlROC - - 12 p's
ClK TO ISR0-3 Delay tlSRD - - 07 P.s
Index Pulse to STRB Bit 3 Delay tlROI - - 18 "'S
Index Pulse to 1RIT Delay tSTRB3 - - 10 P.s
Data Clock to Transfer Request Delay tDTx 400 - 700 ns
Signal Rise and Fall Times tr,tf - - 25 ns

"Step ISTPI cycle time IS programmable

4·421
 MC6843

BUS TIMING CHARACTERISTICS (See Notes 1 and 2)

ldent.
Number Charactariatlc Symbol Min Max Unit
1 Cycle Time tCYC 10 10 ,.s
2 Pulse Width, E low PWEl 430 9500 ns
3 Pulse Width, E High PWEH 460 9500 ns
4 Clock Rise and Fall Time tr,tf 25 ns
9 Non·Muxed Address Hold Time tAH 10 ns
13 Address Setup Time Before E tAS BO - ns
14 Chip-Select Setup Time Before E tcs BO - ns
15 Chip-Select Hold Time tCSH 10 - ns
18 Peripheral Read Data Hold Time Provided tDHR 20 100 ns
21 Wnte Data Hold Time tDHW 10 ns
30 Peripheral Output Data Delay Time tDDR 290 ns
31 Peripheral Input Data Setup Time tDSW 165 ns

FIGURE 4 - BUS TIMING CHARACTERISTICS (See Notes 1 and 2)

• E

R/VV,Address--~ti~~~?V~V'------~~~~--lHr-----------------------------ti~~O'
~--------~3~--------~

(Non-Muxed) ____~~~-L~~~~--------~~~----~r_--------------------------------ti~~~

cs----~~------------------~

Read Data ----+......,il

Non-Muxed ____ -+__~~~----------------------------------------------~:::::j~--_==_--~+_~~
Write Data ----~---- MPU Write Data Non-Muxed
Non-Muxed D-------------~~~~~~~~~~--------------~~~~~~~~--------_+--~

Notes
1 Voltage levels shown are VlSO 4 V, VH:.:2 4 V, unless otherwise speCified
2 Measurement POints shown are 0 8 V and 2 0 V, unless otherwise speCified

FIGURE 5 - MASTER CLOCK (ClK)

ClK

Note. Timing measurements are referenced to and from a low voltage of 0 8 volts and
a high voltage of 2 0 volts, unless otherwise noted

4-422
MC6843

FIGURE 6 - READ DATA TIMING

PWDH _/
~------------tDC--------------~

Data Clock IDCKI

Read Data IRDT!

•
FIGURE 7 - INDEX TIMING FIGURE 8 - ilm RELEASE TIME

'M"'~""7_1
Interrupt Request

r
FIGURE 9 - DATA BUS DIRECTION TIMING

Enable~

rtDBD-j,--__-
Bus Dlfectlon t
FIGURE 10 - WRITE DATA TIMING

Write Data

Note Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

4-423
 MC6843

J
FIGURE 11 - STEP TIMING (PROGRAMMABLE) FIGURE 12 - TxRQ RELEASE TIMING

~~W
Enable

Step I
~ tcycSTP
-(
----j r
ACknOWledge~~
Transfer ~ tTR
Transfer
Request --------X'-_____
FIGURE 13 - OELAY TIME FROM DATA CLOCK TO TRANSFER REQUEST (tDTx)

Read Data 1\ I
C D C D

Data Clock lOCK! ------1I tDTx ---,

~ I--
J \

•
Transfer
Request
I
I
FIGURE 14 - WRITE DATA versus WRITE GATE TIMING
a - SSW, SWD and MSW commands ISlngle Sector Write, Single Sector Write with Deleted Address Mark, and Multiple Sector Write!

WGT----1
I C D C D C
I
WDT _ _ -;.I__~
I
r--tGDl
b - FFW Command (Free Format Write)

WGT~ L
I C D C --ll--tGH

WDT _ _-i-l_ _~
I
"---___ --I1..I1-
I I
--..-.I l--tG D2

FIGURE 15 - INTERRUPT STATUS REGISTER AND INTERRUPT REQUEST TIMING

Master Clock ICLK!

11 MHz!
I
--1 :---tISRD

ISRO, ISR1, ISR2, ISR3

i
-..-! f---tIRQC

Note Timing measurements are referenced to and from a low voltage of a 8 volts and a high voltage of 20 volts, unless otherwise noted

4-424
MC6843

FIGURE 16 - TRACK NOT EQUAL ERROR TIMING

Command Set Command End

Index

Status
Register
B3

Interrupt Status
Register
a
Interrupt ---------------1
Request

a 8 volts 8rd a high voltage of 2 0 volts,

•
Note Timing measurements are referenced to and from a low voltage of unless otherwise noted

FIGURE 17 - INTERNAL BLOCK DIAGRAM

CLK-------------------------------------------.-------------------------------,

STP
Instruction
Decoder
and
TxRQ
Sequence
Controller

TxAK

DO LCT
D1
D2
D3
FIR
D4
HDR
D5
HLD
D6
WGT
D7
VFOC

FI
CS IDX
RSO TRZ
RS1 WPT
RS2 RDY
R/W
WDT

BD

RESei-- DCK
VCC-
VSS- RDT

4-425
 MC6843

GENERAL DESCRIPTION Logical-Track Address Register (LTAR) - The 7-blt track

The MC6843 FDC IS a single-density controller which is address used for read and write operations IS stored In the
IBM compatible. Data from the drive IS clocked Into the FDC LT AR by the bus Interface.
by an external phase lock loop OSCillator Internal syn-
chronization to the data stream IS handled automatically A Serializing Section
1 MHz clock IS used as a timing signal for the internal func- The serla:,zlng section handles the serlal-to-parallel and
tions of the FDC, such as head load and step, as well as shif- parallel-to-serlal conversions for Read/Write operations, as
ting data serially to the drive Status bits are provided to In- well as CRC generation/checking and the generation/detec-
dicate various error conditions and status of the drive DMA tion of the clock pattern. The Data Output Shift Register
or polled I/O modes are available !DOSR), Data Input Shift Register !DISR), CRC
Generator/Checker, and Clock Shift Register (CSR) com-
Register Section prise the serialiZing section of the FDC.
The register sect!'"'n consists of twelve user-accessible
registers used for controlling a floppy disk drive All twelve Bus Interface
are connected by the Internal data bus to allow the processor The Bus Interface section proVides the timing and control
access to them. logic that allows the FDC to operate With the M6800 bus,
and IS comprised of the Data Buffers, DMA Control. and the
Data Output Register (DOR) - The DOR IS an 8-blt Register Select CIrcuitry
register which holds the data to be written onto the disk The
Information IS stored here by the bus Interface Control

•
The Internal timing and control signals which sequence
Data Input Register (DIR) - The data words read from the
the FDC are derived from the macro instructions by the con-
disk are stored In the 8-blt DIR until read by the bus inter-
trol section.
face.

Current-Track Address Register (CTAR) - CTAR IS a 7-blt PIN DESCRIPTION

register containing the address of the track over which the
R/W head IS currently positioned POWER PINS

Command Register (CMR) - The macro commands are VCC: Input

written to the 8-blt CMR to begin their execution +5 volt (±5%) power Input.

Interrupt Status Register (lSR) - The four bits of the IS R VSS: Input
represent the four conditions that can cause an Interrupt to
Power Supply Ground
occur,
BUS PINS
Set-Up Register (SUR) - Variable Seek and Settling
times are programmed by the SUR Four bits are used to
Reset Input The RESET Input IS used to Initialize the
program the track-to-track seek time and four bits are used
FDC. When RESET becomes Low, the state of the outputs IS
to program the head settling time for the floppy disk drive
defined by the table below
used With the FDC
Output Stat. of Output Output Stat. of Output
Status Register A (STRA) - The eight bits of STRA are
FIR Low HLD Low
used to Indicate the state of the floppy disk Irlterface
WGT Low TxRQ Low
HDR Low IRQ High
Sector Address Register (SAR) - SAR contains the 5-blt STP Low WDT Low
sector address associated With the current data transfer.
Registers which are affected by RESET are shown In Tab!e 7
Status Register B (STRB) - The eight prror flags of STR B
are used to Signify error conditions detected by the FDC or Interrupt Request (IRQ) Output - The IRO line IS an open-
generated by the floppy disk drive. drain output that becomes a low level when the FDC re-
quests an Interrupt Interrupt' requests are controlled by the
General Count Register (GCR) - The seven bits of GCR Interrupt enables In CMR (Command Register) With the func-
contain the destination track address when a SEK (seek) tion causing the Interrupt shown In ISR (Interrupt Status
macro command IS being executed. If a multi-sector Read or Register)
Write macro command IS being executed, GCR contains the
number of sectors to be read or Wnlten Data Bus O-Data Bus 7 (00-07) Bidirectional - The eight
bidirectional data lines allow the transfer of data between the
CRC Control Register (CCR) - The two bits of the CCR FDC and the controlling system. The output buffers are
are used to enable the CRC and shift the CRC for the Free- three-state drivers that are enabled when the FDC IS transfer-
Format Commands. ring data to the data bus

4·426
MC6843

Enable (E) Input - The E Input to the FDC causes data TABLE 2 - REGISTER SELECTION
transfers to occur between the FDC and the system controll- FOR DMA TRANSFERS
Ing the FDC (MC6800 MPU, DMA Controller, etc J. E must
be a logiC '1' (high level) for any transfer to be enabled on Register
TxAK RSO-RS2 CS R/Vii Selected
DO-D7 The E Input IS normally connected to system <1>2
1 X X 1 DOR
1 X X 0 DIR
Chip-Select (CS) Input - The CS Input, In conjunction
with the E Input, IS used to enable data transfers on DO-D7 E
ThiS mode of operation IS normally used for DMA (Direct
must be a high level and Cs must be a low level to enable the
Memory Access) transfer With the FDC _
transfer The TxAK Input being a high level (logiC 'I') per-
When TxAK IS a low level the registers are selected by CS,
forms a function similar to Cs being a low level
R/Vii and RSO-RS2 as shown In Table 1.
Read/Write (R/W) Input - The R/W Input IS Issued by
Bus Direction (BO) Output - The BD output IS proVided
the system controlling the FDC (MC6800 MPU, DMA Con-
to control bidirectional buffers on the data bus (DO-D7I as
troller, etc) to signify If a read or wnte operation IS to be per-
shown In Figure 1 Its polanty IS shown by Table 3
formed on the FDC When TxAK IS a low level, R/Vii IS used
In conjunction with CS and RSO-RS2 to determine which TABLE 3 - BUS DIRECTION IBD) STATES
register IS accessed by the bus as shown In Table 1 When
TxAK IS a high level, R/W IS used to select either the DDR or TxAK CS BD
DIR to the data bus (see descnptlon of TxAK Input) 1 X R/W
0 1 0

•
Register Select O-Register Select 2 (RSO-RS2) Input 0 0 R/W
RSO-RS2, In conjunction with the R/W Input, are used to
select one of the user accessible registers In the FDC as IOperatlon of BD. as defined by thiS chart, allows the FDC to func-
shown In Table 1 tIOn With the DMA Controller MC6844)

TABLE 1 - ADDRESS CODES FOR USER I/O AND CONTROL PINS

ACCESSIBLE REGISTERS
Master Clock (ClK) Input - The ClK Input IS used to
TxAK RS2 RS' RSO R/W Registers
generate vanous timing sequences Internal to the FDC The
0 DOR IData Out Register) head settling and seek time, as well as the data and data
0 0 0 0
1 DIR IData In Register) clock timing, are generated from the ClK Input signal
0 0 0 1 1/0 CTAR ICurrent Track Address
Register) Head load (HlO) Output - HlD IS used to notify the disk
0 CMR ICommand Register) dnve that the R/W head should be loaded (placed In contact
0 0 1 0
1 1::>'1 nterrupt ::>tatus eglster With the media) When the FDC IS ready for the head to load,
0 SUR ISet Up Register) HlD IS a high level (logic 'I') A low level (logic '0') on HlD
0 0 1 1
1 I::>TRA I::>tatus Heglster AI indicates the head s~ould be unloaded
0 SAR ISector Address
0 1 0 0 Register) Step (STP) Output - The STP output, In conjunction
1 STRB IStatus Register B) With HDR, IS used to control head movement A 32"s Wide
0 1 0 1 0 GCR IGeneral Count Register) positive (logiC 'I') pulse IS generated on STP, to move the
0 1 1 0 0 eCR (CRe Sontral Register) R/W head one track In the direction defined by the HDR out-
0 1 1 1 0 LTAR I Logical Track Address put The penod of the STP signal IS programmable by the
Register) SUR (Set-Up Register) The number of pulses generated on
STP IS the difference between the contents of the CT AR
(Current Track Address Register) and the GCR (General
Transfer Request (TxRO) Output - TxRQ IS used In the Count Register) which contains the track address to which
DMA mode to request a data transfer by the DMAC TxRO IS the head IS to be moved
a high level If the FDC IS In the DMA mode ICMR bit 5 IS set)
when a data transfer request occurs (STRA bit' IS set) It IS Head Direction (HOR) Output - The HDR Signal controls
reset to a low leve) (logiC '0') when TxAK becomes a high the direction of head movement. A high level (logiC '1')
level (logiC 'I') Data transfer errors Will occur If TxAK does Signifies the head should step to the InSide (toward the hub)
not reset TxRO before the next data transfer IS reqUIred of the disk A low level (logic '0') Indicates the direction of
head movement should be to the outSide of the disk.
Transfer Acknowledge (TxAK) Input - TxAK IS generated
by the system controlling the FDC (MC6800 MPU, DMA low-Current Track (lCT) Output - The lCT signal IS us-
Controller, etc) and IS a response to a TxRO Issued by the ed to control the level of wnte current used by the disk dnve.
FDC A high level Iloglc '1') on TxAK causes the FDC to lCT IS a low level (logiC '0') when the write head IS posltlon-
neglect the state of RSO-RS2 and CS causing the FDC to eo over tracks 0-43 If It IS over tracks 44-76, lCT IS a high
select the DOR (Data Output Register) or DIR (Data Input level (logiC '1 ') LCT is determined from the contents of the
Register) to the data bus (DO-D7) as shown In Table 2 Current Track Address Register (CTAR)

4-427
 MC6843

Write Gate (WGT) Output - When a write operation IS DATA PINS

being performed, WGT IS a logic '1' (high levell. For a read
operation, WGT IS a low level (logic '0') Data Clock (OCK) Input - Data from the drive is clocked
Into the FOC on both positive and negative edges of the OCK
File-Inoperable Reset (FIR) Output - FIR IS an output Input. ThiS signal IS generated from the Read Recovery Cir-
from the FOC to the floppy disk drive to reset It from an in- CUit
operable status If the FI Input IS a '1', a 11's pulse IS
generated on the FIR output whenever Status Register B IS Read-Data (ROT) Input - ROT IS the senal data input
read from the Read Recovery CirCUit. The data stream Includes
both the clock and the data bits and must be presynchronlZ-
File Inoperable (F!) Input - FilS an Input to the FOC from ed to the Data Clock (OCK).
the drive A high level indicates the drive IS In an Inoperable
state Its current state can be examined by reading bit 5 of Write-Data (WOT) Output - WDT IS the double frequen-
Status Register B (STRBI cy modulated data output from the FOC The time between
clock bits IS 4/1 where f IS the frequency of the CLK Input
Track Zero (TRZ) Input - The TRZ Input IS reflected by bit The pulse Width for both clock and data IS 1If (see Figure
3 of STRA (Status Register A) The TRZ Input must be a 181 For the normal CLK frequency of 1 MHz the write period
high level (logiC '1') when the R/W head of the drive IS POSI- IS 41'S, the clock pulse Width IS 11's and the data pulse Width
tioned over track zero. A logic' l' on this Input Inhibits step IS 1 I's Figure 18 shows the relationship between the WOT
pulses dUring a Seek Track Zero command output and the frequency of the CLK Inputs
FIGURE 18 - WDT OUTPUT TIMING
Index (lOX) Input - The Index Input IS received from the
floppy disk drive and IS used to sense the Index hold in the
disk media. The lOX signal IS used to Initialize the Internal
FOC timing. The state of the lOX Input IS reflected by bit 6 of
Status Register A (STRA) A high level (logic '1') is to In-

•
dicate the Index hole IS under the Index sensor The Index In-
put IS used to count the number of disk revolutions while
searching for the address 10 field (see description of STRB Clock Data Clock Data
bit 3)
f= Frequency of the elK Input To Insure
Ready (ROY) Input - The ready input IS received from the IBM3740 compatibility the clock frequency
disk drive and can be read as bit 2 of STRA (Status Register must be 1 MHz
A) A high level (logic '1') ,nd,cates the drive IS ready and
allows the FOC to operate the drive
Variable-Frequency Oscillator Control NFOCI Output -
Write Protect (WPT) Input - WPT IS an Input Indicating VFOC IS used as a sync signal dUring system dlagnost'cs
when the media IS Wnte Protected. A high level dunng an Waveforms are shown In Figure 19
FOC write operation results In a Wnte Error (STRB bit 6) but
the FOC continues to perform the write function The state FORMAT
of the WPT Input can be read by examining bit 4 of the The format used by the MC6843, shown In Figure 20, IS
Status Register A (STRAI. compatible with the soft sector format of the IBM 3740.
FIGURE 19 - VARIABLE FREQUENCY OSCILLATOR CONTROL WAVEFORM
(Relation Between WGT and VFOC)
SSW,SWD,MSW Commands
~6 Bytes Data Field
ID Field Data Field 10 Field

T'ack _ . ; -....iI~!_-i---1 L , -_ _ -...IIlL..__--Ir-

!-- :: 1 Byte--l l i 6 Byt.,-' i--
6 BVtes--f
I
I
1 Byte-, ,--
" r---I'------------:-;I
i 1 Byte~ t--
I I I

WGT! I I L I I
I I 148 Bytesl I I I I
I I ~ 1--54 Byt.s--i I I I
I I r-----,' I ~i__l.~-_9-B-y-te-s--_--__,1I
VFOC~ LJ U U L.J
10 BYtes----! r-- --1 t---10 Bytes
SSR, RCR, MeR Commands

10 Field Data Field ID Data

T'ack _ _
_ -!f""IL..__. . . L_ _ _ _....., - - - ,...._ _ ---'J
I I 6 I I I I I II
"0" I t4-Bytesj --..j ~6 Bytes 1 Byte--, ~ -..., r--' Byte

WGT _ _ ~I~-'-__~I----r----------------------~I--------_r---'~I----------
I i I
I 1 Byte--j ~ I __: '--6 Bytesj
Ir-_ _ _ _-. I I I
VFOC--1
--I
LJ1-- 10 Bytes 26 Bytes--!
L-Jr-- LJ

4·428
MC6843

FIGURE 20 - SOFT SECTOR FORMAT

Index~r:'----_
L-
_ _ _ _~I~I-------------------IfIL--
Gap 1
Preamble (Post Index)
Track 46 Bytes 32 Bytes

'--I~'--'secto"lsectoc2Isecto'31111
Format

Index
I ,
Sector 24 Sector 25 Sector 26
'__ I Gap 4
Address Mark 274 Bytes
Data'" Fe (Pre Index
Clock"" 07 Gap)

ID
Address
Mark Gap 2 Gap 3
Data == FE (10 Gap) (Data Gap)
Clock'" C7 17 Bytes 33 Bytes

I-I~ '---'-,,-1
Sector
Format

•
Address 10 F laid
'--------v~----
Data
_____ CRC Next 10
Address Mark 2 Bytes Address Mark
6 Bytes 128 Bytes
1 ~ Track Address Data = Fa or £-8
2--00 Byte Clock = C7
3-Sector Address
4-0QByte
5-CRC
6-CRC

MACRO COMMAND SET SUR has explfed, the Settling Time Complete flag IS set IISR
The macro command set shown In Table 4 IS discussed In bit 11, Busy (STRA-7) IS reset, and CTAR and GCR are
the following paragraphs cleared The head remains In contact with the disk A com-
mand such as RCR IRead CRC) may be Issued following a
Seek Track Zero (S TZ) STZ If the head must be released
The STZ command causes the R/W head to be released
Seek (SEKI
from the surface of the disk IHLD IS reset) and positioned
above track 00. The FDC Issues step pulses on the STP out- The SEK command IS used to position the R/W head over
put until the TRZ Input becomes a high level or until 83 the track on which a Read/Write operation IS to be perforrT'-
ed. The contents of the GCR are taken as the destination ad-
pulses have been sent to the drive When the TRZ Input
dress and the contents of the CT AR IS the source address,
becomes high, the step pulses are inhibited on the STP out-
therefore, the number of pulses INl on the STP output are
put but the FDC remains busy until all 83 have been
given by.
generated Internally
If the TRZ Input remains low (logic '0') after all 83 pulses N = IICT AR) - IGCRll
have been genelated, the Seek Error flag (STRB bit 4),s set. HDR IS a '" for IGCRl>ICTAR) otherWise It IS a '0'
After all 83 pulses have been generated, the head IS loaded When a SEK command IS Issued, Busy IS set, the head IS
(HLD becomes a "'1 After the settling time speCified In the raised from the diSk, HDR IS set, and N number of pulses ap-

TABLE 4 - MACRO COMMAND SET

CMR Bits Hex

Bit 3 Bit 2 Bit 1 Bit 0 Code
1 STZ Seek Track Zero 0 0 1 0 2
2 SEK Seek 0 0 1 1 3
3 SSR Single Sector Read 0 1 0 0 4
4 SSW Single Sector Write 0 1 0 1 5
5 RCR Read CRC 0 1 1 0 6
6 SWD Single Sector Write with Delete Data Mark 0 1 1 1 7
7 MSW Multi Sector Write 1 1 0 1 D
8 MSR Multi Sector Read 1 1 0 0 C
9 FFW Free Format Write 1 0 1 1 B
10 FFR Free Format Read 1 0 1 0 A

4-429
 MC6843

number of pulses appear on the STP output After the last Single-Sector Write with Delete-Data Mark I SWD)
step pulse IS used, the head IS placed In contact with the The operatl(:nal flow of SIND IS exactly like that of SSW
disk. Once the head settling time has expired, the Settling For SWD, the data pattern of the Data-Address Mark
Time complete flag IISR bit 11 IS set, Busy IS reset, and the becomes F8 Instead of F8 The clock pattern remainS C7
contents of the GCR are transferred to the CT AR
Multi-Sector Commands (MSR/MSW)
SINGLE-SECTOR READ/WRITE COMMANDS MSR IS used for sequential reading of two or more sec-
The single-sector Read/Write commands ISSR, RCR, tors If S sectors are to be read, S1 must be written Into the
SSW, and SWDI are used to Read/Write data from a Single GCR before the command IS Issued
128 byte sector on the disk As shown In Figure 21 these The baSIC operation for the MSR and MSW IS the same as
types of Instructions can be divided Into two sections The that for the SSR and SSW repsectlvely. The baSIC operation
first section, which IS common to all Instructions, is the ad- begins With an address search operation, which IS followed
dress search operation, while the second section IS unique to by a Single-sector read or write operation ThiS completes
the requirements of each Instruction. the operation on the first sector The SAR IS Incremented,
the GCR IS decremented, and If no overflow IS detected from
FIGURE 21 - BASIC SINGLE SECTOR the GCR II e, GCR becomes negative) the sequence IS
COMMAND FLOW CHART
repeated until S number of sectors are read or written
The completion of an MSR or MSW IS like that of an SSR

•
or SSW command. First MCC IS set, after the settling time
has expired, Busy IS reset, and the head IS released.
If a delete-data mark IS detected dUring an MSR com-
mand, STRA bit 1 (Delete-Data Mark Detected) remains set
throughout the commands operation
When a multi-sector instruction IS Issued, the sum of the
SAR and GCR must be less than 27 If SAR + GCR > 26, an
address error (STRB bit 3 set) Will occur after the contents of
SAR becomes greater than 26

Free-Format Write (FFWI

The FFW has two modes of operation which are selected
by FWF (Free-Format Write Flag) which IS data bit 4 of the
CMR
When the FWF ~ '0', the data bits of the DOR are wntten
directly to the disk Without first writing the preamble, ad-
dress mark, etc The contents of the DOR are FM modulated
With a clock pattern of all ones
If FWF ~ '1' the odd bits of the DOR are used as clock bits
and even bits are used for data bits In thiS mode, the DOS R
Address Search Operation
clock IS tWice a normal write operation and one byte of DOR
The flow chart of Figure 22 shows the operation of the ad- IS one nibble (four bits of data) on the disk
dress search The two modes of the FFW command allow formatting a
disk With either the IBM 3470 format or a user defined for-
Single-Sector Read ISSRI mat
The single-sector read command follows the address After the FFW command IS loaded Into the CMR, WGT
search procedure as defined In the prevIous flowchart. If the becomes a high level, the contents of DOR are transferred to
search IS successful, status sense request IS set and the the DOSR, data transfer request (STRA bit OilS set, and the
operation continues as described by the flowchart of Figure serial bit pattern IS shifted out on the WDT line Therefore,
23 DOR must be loaded before the FFW command IS Issued
Data from the DOR IS continually transferred to the DOSR
Read CRC (RCR) and shifted out on WDT until the CMR has been written With
The RCR command IS used to verify that correct data was an all zero pattern. Wh'en CMR becomes zero, WGT
written on a disk The operation IS the same as for the SSR becomes a low level, but MCC IS not set and the R/W head
command With the exception that the data-transfer request IS left In contact With the disk
ISTRA bit OilS not set. The SSR Interrupt can be disabled by
uSing the DMA mode Free-Format Read (FFR)
FeR IS used to Input all data (,ncluding Address Marksl
Single-Sector Write ISSW) from a disk. Once the FFR command IS set Into the CM R, the
Single-sector write IS used to write 128 bytes of data on head IS loaded and after the settling time has expired the
the disk. After the command IS Issued, the address search IS senal data from the FDC IS brought Into the DISR After 8
performed. The remainder of the Instruction's operation IS bits have accumuiated, It IS transferred to the DIR and Data-
shown In Figure 24 Transfer Request (STRA bit 01 IS set

4-430
MC6843

FIGURE 22 - OPERATIONAL FLOW OF THE ADDRESS SEARCH SEQUENCE

Tnls Operation IS Conducted In Parallel with all Other Operations

Set Track Not Equal

Set MCCIISR Sit OJ

(eMR Sit 5)
Store Track Address
In OIR
t..---t-----;~~~:;~~::J
•
Set MCC (lSR 81t 0)
Set CRe Error
(STRB Sit 1)

4-431
 MC6843

FIGURE 23 - OPERATIONAL FLOW OF THE SSR COMMAND

Set Data Address

Mark Undetected
(STRB Bit 2)
Set MeC
ilSR B,t 01

Set CRe Error

(STRB 81t 1)

4-432
MC6843

FIGURE 24 - OPERATIONAL FLOW OF THE SSW COMMAND

Set Data
Transfer Request
(STRA Bit OJ
(Set Simultaneously
with Status
Sense Request)

Wrttethe
Data
Address Mark
(Clock = C7.
Data'" FB)
•

Transfer Contents
of DOR to DOSA
& S8t Data
Transfer Request
(STAA Bit 0)

4-433
 MC6843

This operation continues until a zero pattern IS stored In data transfer mode and Interrupt conditions are loaded Into
the CMR, terminattng the FFR command. As In the case of bits 4 through 7
the FFW command, MCC is not set and the head remains In
contact with the disk. Bit O-Bit 3: Macro Command
The first data that enters the DISR IS not necessartly the The Macro Command to be executed by the FDC IS Wrtt-
first bit of a data word Stnce the head may be lowered at any ten to bits 0-3
place on the disk To prevent the FDC from rematntng un-
synchronized to the data, the FFR command Will syn- Bit 4: Free-Format Write Flag (FWF)
chronize to either an 10 address mark (FE) or a Data-Address If a Free-Format Wrtte command IS Issued, the state of bit
Mark (FB or F81. 4 of the CM R determtnes what clock source Will be used
The FWF is defined ,n the FFW (Free-Format Wrttel com-
REGISTER DEFINITIONS mand explanation
DATA OUTPUT REGISTER (DOR)
Bit 5: DMA Flag
Hex address 0, wnte only
If bit 5 IS a '1' the FDC IS In the DMA mode Bit 5 being a
'1' tnhlblts setting of Status Sense Request IISR bit 21
thereby preventing ItS associated Interrupt A logiC '1' DMA
flag also enables the TxRQ output allowtng It to request
DMA transfers when the Data Transfer Request fl~g (STRA
When one of the four wnte macro commands (SSW,
bit 01 IS set
SWD, MSW, and FFW) IS executed, the Information con-

II
A logiC '0' DMA flag tnd,cates the program controlled 1/0
tained In the DOR IS loaded Into the DOSR, and IS shifted out (PC I/O) mode IS to be used
on the WDT line uSing a double frequency (FM) format
Bit 6: ISR3 Mask
DATA INPUT REGISTER (DIRI
CMR bit 6(ISR3 Maskl,s used to control the operation of
Hex address 0, read only ISR bit 3. A logiC '1' In CMR bit 6 tnhlblts ISR bit 3 from be-
tng set when STRB becomes non-zero If CMR bit 6 (ISR3
Mask) IS a '0' the ISR bit 3 Will be set If any btl In STRB
becomes set. The setting of ISR bit 3 Will cause an tnterrupt
If CMR bit 7 IS a '0'.
One of the three read macro commands (SSR, MSR, FFR)
executed, Will cause the tnformatlon on the RDT Input to be Bit 7: Function Interrupt Mask
clocked Into the DISR When eight clock pulses have oc- When CM R bit 7 IS a logiC '1' all Interrupts are Inhibited ex-
curred, the eight bits of tnformatlon In the DISR are transfer- cept Status Sense Request IISR bit 21 which can only be In-
red to the DIR where It can be read by the bus Interface hibited by the DMA flag (CMR bit 51. A logiC '0' tn CMR bit 7
3nables Interrupts from ISRO (Macro Command Completel
CURRENT TRACK ADDRESS (CTAR)
and ISRl (Settling Time Complete), and If the ISR3 Mask IS
Hex address 1, read/wnte '0', from ISR3

TABLE 5

Command Register Masks

The address of the track over which the R/'N head IS cur- That Affect Interrupts
rently positioned IS contained In the CT AR At the end of a Interrupt CMR7
SEK command, the contents of the GCR are transferred to Status Register (Function
(Bits Causing Interrupt CMR6 CMR5
the CT AR CT AR IS cleared at the completion of a STZ com-
Interrupts) Mask) (ISR3 Mask) (DMA Flag)
mand CT AR IS a read/wrtte register so that the head POSI-
lton can be updated when several drtves pre connected to ISRO
(Macro Command M X X
one FDC Bit 7 IS read as a '0' Complete)
COMMAND REGISTER (CMR) ISRt
(Settling Time M X X
Hex address 2, wrtte only Complete)
ISR2
Sit 7 Sit 6 Sit 5 Sit 4 Sit 3i Sit 2"jBlt tiSlt O· M
(Status Sense X X
Function ISR3 Request)
DMA
Interrupt Interrupt FWF Macro Command
ISR3
Mask Mask Flag
(STRB M M X
·B,ts 0-4 are cia red by RESET. Conditions)

The commands that control the FDC are loaded tnto the X" No effect
lower four bits of the CMR Informattan that controls the M == 81ts that are used as masks

4-434
MC6843

INTERRUPT STATUS REGISTER (lSR) to stop bounCing before any operations are performed The
Hex address 2, read only delay IS programmed by bits 0-3 and IS speCified by the equa-
tion
I I I
Bit 7 Bit 6 Bit 5 Bit 4 Blt3 Bit 2 Bit 1 Bit 0 Delay; 4096 _B
Status' Settling' Macro" f
Not Used
STRB' Sense TIme Com- B; Number contained In bits 0-3 of SUR
IRead as '0'1
Request Complete mand f; Frequency of elK Input
• Cleared by RESET For IBM 3740 compatibility f; 1 MHz and the timing range
Bit 0: Macro Command Complate Is4 096 ms for a '0001' to 6144 ms for a '1111'. A '0000' code
prevents Settling Time complete from being set and the FDC
When an SSR, RCR, SSW, SWD, MSR or MSW Macro
must be Reset
Command has completed execution, bit 0 bcomes set (logic
'1'1 If the function Interrupts are enabled (bit 7 of CMR IS a
Bit 4-Blt 7: Track-to-Track Seek Time
logic '0'1, the conclusion of a Macro command's execution
will cause an Interrupt The frequency of STP IS determined by bit 4-blt 7 of SUR
as shown below If the track-to-track seek time IS 0 the
Bit 1: Settling Time Com plate period of STP IS 64lf
Settling time complete IS set on SEK and STZ commands
to Indicate the head has been loaded and the 8ettllng time A= Number speCified In bits 4-7 of SUR
f = Frequency of clock Input
specified In SUR has expired Since MCC IS not set for the
SEK or STZ command, settling time complete can be used

•
as an Interrupt to Signify the SEK or STZ command has
finiShed. Settling Time Complete IS not set for any of the -------A
11oo... _10_,2_4 -------1....-11
RIW commands.
--l I-- 3,2
Bit 2: StatuI Senn Request
For an SSR, SSW, SWD, MSR, or MSW Command,
Jl_ _ _ _---IrL
Status Sense Request indicates that the specified address ID
field has been detected and verified by a CRC check. This IS A = Number specified In bits 4-7 of SUR,
used as an early indication that data transfers will occur after f .. Frequency of clock Input.
18 more byte times. For MSR and MSW commands, it IS set
for each sector. For IBM compatible operation, f IS 1 MHz. ThiS results In
In the PC 1/0 mode, an Interrupt occurs when Status an STP pulse width of 321's and an STP interval of 1.024 Ins
Sense Request becomes a logic '1' regardless of the state of for 0001 in bits 7-4 to 15.36 ms for 1111.
the CMR interrupt mask. In the DMA mode, (DMA flag of
CMR is setl Status Sense Request IS unchanged and does STATUS REGISTER A (STRA)
not generate an Interrupt when the address ID field has been Hex address 3, read only
verified.
Bit 7 Bit 6 Bit 5 Bit 4 Blt3 Bit 2 Bit 1 BII 0
Bit 3: STRB
Delete' Data·
STRB IS an 'OR' of all of the bits of Status Register Band Track' Write
Track Drive Data
IS disabled by the STRB Interrupt mask In the CMR (CMR bit Busy' Index Not Pro- Transfer
Zero Ready Mark
6) The equation' Equal tect Request
Detected
STRB; CMR6-(STRB + STRB1 + STRB2+
'Cleared by RESET
STRB3+ STRB4+ STRB5+ STRB6+ STRB71
describes the operation of Bit 3 of the ISR
ISRO, ISR1, and ISR2 are cleared when the Interrupt Bit 0: Data Transfer Request
Status Register IS read, but ISR3 IS cleared only after Status For a write operation (SSW, SWD, MSW, FFW) the
Register B has been read. transfer request bit Indicates that the DOR IS ready to accept
the next data word to be written on the disk. If data is not
SET-UP REGISTER (SUR) written into the DOR before the last data bit In the DOSR IS
Hex address 3, write only shifted out to the WDT line, the data transfer error bit (bit 0
of STRB) will be set. After a write command has been
Issued, the first transfer request occurs simultaneously with
the Status Sense Request. For a write operation, transfer re-
quest IS reset after the DOR has been written from the data
The SUR IS not affected by a reset operation; therefore, bus.
once It IS initialized, the Information remains until power IS DUring a read operation (SSR, MSR, FFRI the transfer re-
removed from the FDC quest bit Signifies data from the DIS R has been transferred
to the DIR. The DIR must be read before the DISR is full
Bit 0- Bit 3: Head Settling Time agam or the data transfer error bit (bit 0 of STRB) Will be set
The head settling time IS used to generate a delay after the For read operations, transfer request IS reset by a read of the
head IS placed In contact With the disk. ThiS allows the head DIR

4-435
 MC6843

Bit 1: Delete Data Mark Detected STATUS REGISTER B (STRB)

A Single-Sector Read operation that detects a delete data Hex address 4, read only
code (F8), Instead of a general code (FB) as a Data Address
Mark, will set the Delete Data Mark Detected bit For the Sit 7 Sit 6 Sit 5 Sit 4 8113 Sit 2 Sill Sit 0
MSR command, bit 1 IS set the first time an 'F8' code IS Sector" Data" Data"
found and remains set throughout the execution of the com- Hard- Wnte" File Seek" Address Mark CRe" Trans-
mand. Bit 1 IS reset whenever an SSR, SSW, SWD, MSR, Error Error Inop- Error Unde- Unde- Errorl fer
MSW, or RCR command IS Issued erable tected tected Error
Cleared by RESET
Bit 2: Drive Ready
The Drive Ready bit indicates the state of the Ready Input
from the floppy disk drive. If a command IS Issued With
The bits of the STR B represent possible error conditIOns
Ready at logiC '0', ItS execution will be Inhibited until Ready
that may occur dunng execution of macro commands
becomes a logiC '1' If ready becomes a '0' dunng the execu-
Whenever STR B IS reset, IS R bit 3 IS also reset
tIOn of a command the Hard Error Flag (STRB bit 71 IS set.
Bit 0: Data Transfer Error
Bit 3: Track Zero
Data Transfer Indicates an underflow or overflow of data.
The state of the Track Zero Input from the floppy disk
dnve IS reflected In thiS bit of STRA A logiC '1' on the Track If a Write operation is being performed, It Signifies that data
was not presented to the DOR before the DOSR became
Zero Input inhibits step pulses dUring an STZ command.
empty In thiS case, the current contents of the DOR are

II Bit 4: Write Protect

The Wnte Protect Input from the floppy disk drive IS
reflected by bit 4 of STRA A high level (logiC '1'1 on the
WPT Input dUring the execution of any write command
results In a write error (bit 6 of STRB setl
transferred to the DOSR and the write operation continues.
The data transfer error remains set until data IS written Into
the DOR The operation of the CRC IS unchanged.
For read commands, a data transfer error ,nd,cates that
data In the DIR was not read before the next data word from
the disk was transferred to the DIR. The read operation con-
Bit 5: Track Not Equal tinues until suffiCient data has been read from the disk to
satisfy the requirements of the command (128 bytes for
If the track address read from the address ID field does not SSRI. The error Indication remains set until STRB IS read,
cOincide With the address In the LTAR, the Track Not Equal
and the transfer request remains set until data IS read from
bit is set Track Not Equal applies to all non-free format
the DIR
read/wnte commands, and IS reset after a non-free format
read/Write command IS Issued
Bit 1: CRC Error
Bit 6: Index A CRC error occurs when the CRC read from the disk does
The state of the Index Input appears In bit 6 of STRA The not match that calculated by the FDC on the data It reads
Index Input IS used to count the number of disk revolutions from the disk. A CRC error can occur In three different situa-
while the FDC IS looking for the address ID field (see opera- tIOns; checking the address ID field, checking the data field,
tion of STR B bit 31 dUring the address search phase of a non- and checking the FFR data. (See operation of CCR I
free format read/Write command If the CRC error occurs dunng the check of an address ID
field, Sector Address Undetected (STRB bit 3) Will also be
Bit 7: Busy ,nd,cated (see Table 6) A CRC error of a data field IS In-
When Busy IS a logiC '1', the FDC IS executing a command dicated by a CRC error and no sector address error
and no new commands can be Issued

SECTOR ADDRESS REGISTER (SAR) Bit 2: Data Mark Undetected

Hex address 4, Write only If a valid mark IS not detected In the data block of a sector,
It IS indicated by a Data Mark Undetected error Data Mark
Undetected IS reset after a non-free format Read/Write com-
mand IS Issued.

Before a data transfer macro command (SSW, SWD, Bit 3: Sector Address Undetected
SSR, RCR, MSW, MSRI,s Issued, the address of the sector The sector address bit can be set on two conditions, not
on which the operation IS to be performed must be written fmdlng the sector address and a CRC error on an address ID
Into the SAR The address In the sector address byte of an field.
Address ID field of the disk IS compared With the contents of If the disk makes three revolutions dUring an address
the SAR. Dunng an MSWor MSR command, the SAR IS In- search operation and the sector address speCified In the sec-
cremented after each sector IS read or wntten When execu- tor address register IS not found m any of the address ID
tion IS complete, the SAR contains the address of the last fle'ds, a sector address undetected condition IS mdlcated
sector on which an operation was performed plus one At A CRC error that occurs on an address ID field Will set bit 3
the completion of an STZ or SEK command, SAR IS cleared also. Table 6 shows how bits 1 and 3 are related

4·436
MC6843

TABLE 6 - RELATIONSHIP OF CRC ERROR AND CRC CONTROL REGISTER (CCR)

SECTOR ADDRESS UNDETECTED Hex address 6, write only
Sector
Address
CRC Error Undetected
(STRB 11 (STRB 31 Condition
0 0 No Error
0 1 Sector Address not Detected The CCR Information IS used only 10 the free format com-
1 0 CRC Error on a Data Field mands, for all other commands thiS register IS masked and
1 1 CRC Error on Address 10 Field has no function

Bit 4: Seek Error Bit 0: CRC Enable

An STZ (Seek Track Zerol command that never receives a DUling an FFW command, CRC Enable IS set by software
track zero Indication on the track zero Input Will result In a and CRC generation takes effect on the next transfer of data
Seek Error (see deSCription of STZ command) from DOR to DOSR (see Figure 251 The CRC generation

II
continues until Shift CRC leCR bit 1) IS set
Bit 5: File Inoperable For an FFR command, CRC Enable IS set by software and
CRC generation takes effect on the next data read from DIR
The state of the File Inoperable Input appears In bit 5 If
The calculation continues for all data bytes read from DIR
the File Inoperable Input is a '1', a pulse of Width l/f (where
until CRC Enable IS reset The bytes read prevIous to reset-
f = Frequency of the clock Input) IS Issued on the FIR output
ting CRC Enable are conSidered the CRC Information bytes
when STRB IS read. FilS not latched but the Input IS gat~d to
and the CRC check IS made agamst them.
the bus when STRB IS read.
Bit 1: Shift CRC
Bit 6: Write Error
Bit 1 IS valid only tor the FFW command After setting, It
If the WPT Input becomes a high leveillogic '1') dUring the
takes effect on the next transfer of data from DOR to DOSR
execution of a write command the write error bit IS set.
(see Figure 26), Setting Shift CRC terminates the CRC
calculation and causes the CRC calculated on all the data
Bit 7: Hard Error
written Into DOR up to the setting of bit 1, to be shifted out
If the Ready input becomes a '0' during the operation of a the WDT output The CRC calculation Will not Include any
command (Busy IS set), a hard error indication will result data written to DOR after Shift CRC IS set

GENERAL COUNT REGISTER (GCR) LTAR (LOGICAL TRACK ADDRESS)

Hex address 5, write only Hex address 7, write only

The GCR contains the destinatIOn track address for the When a read or write macro command (SSW, SWD,
R/W head on an SEK Macro Command. The contents of the SSR, RCR, MSW, MSR) IS Issued, the address of the track
GCR are transferred to the CT AR at the end of the SEK on which the operation IS to be performed must be written
Command. For multi-sector read or write operations IMSR, Into the LTAR The address In the track address byte of an
MSW), the GCR contains the number of sectors to be read Address ID field of the disk IS compared With the contents of
minus one DUring the MSR or MSW execution the GCR IS the LTAR The contents of LTAR are not affected by the ex-
decremented after each sector IS read or written. ecution of any of the commands

4-437
 Read Data Read Data
•
FIGURE 25 - CCR CONTROL REGISTER TIMING FOR AN FFR COMMAND (READ)
Read Data Read Data CRC
3:

~
CRC' Read Data
Read Data Enable Byte 1 from Byte 2 from Byte n-1 from Byte n from E'lable Byte n+1
Byte 0 from Set DIR DIR DIR DIR Reset from DIA
DIR (CCRO=lI (Data 1) (Data 2) (Data n-1) (Data nJ ICCRO=O) (Data n+1)

DCK (Data
Clock Input)

Load Signal
from OISR
to DIR

DTR

CAG Enable
(CCRO)

CRC
valid

OISR Data 2
DIR Data 1 Data n+1

CRG Calculation Includes Data Byte 1 through Data Byte n

FIGURE 26 - CCR CONTROL REGISTER TIMING FOR AN FFW COMMAND (WRITE)

,J:o.
Wrtte
~ Byte n eCR Set Write Byte

~ to DOR (CCRO=ll n+1 to DOR

ShIft
Clock
Load signal
from DOR
to DaSA

STRAO
IDTR)

CCRO
(CRC Enable) ~

7s~7f:CRC) \\ 111-1-------t---'
CRG valid _ _ _ _ _ _~----'

DOR
DOSR
T
Data 0
T T21r--_-_--_··_--L
Data 1
l _________
Data .L_ _~~~_ _ _.L_ __=..::..:::_.:.:..._.:.:..._ _ C::::.:
WDT
Output II ----. - I ,--'_.

The CRG Calculation Includes Data Byte 1 through Data Byte n-1
MC6843

TABLE 7 - PROGRAMMING REFERENCE DATA

Table 7 IS a summary of the Information 10 the data sheet and can be used as a reference when programming the MC6843

I Hex
Reuister.1 Address
R/W
Mode
Data Bits

Bit 7
Function
B.t6
ISR3
B.t 5

OMA
81t4 B.t 3
.I B.t2
. B.t 1
. Bit 0
.
CMR 2 WO Interrupt Interrupt FWF Macro Command
Flag
Mask Mask

B.t 7 J Blt6 L B.t 5 J B.t4 Bit 3

. Bit 2 Bit 1 BitO

•
Status it Settling .. Macro II-

ISR 2 RO Not Used STRB Sense TIme Command

Request Complete Complete

STRA RO
Bit 7

Busy
. Bit 6 Bit 5
Track ..
B.t4

Write
B.t 3

Track
Bit 2

Onve
B.t 1
Delete ..
81tO
D8t8
1 ranster
3 Index Not 08t8 Mark
Protect Zero Ready
Equal Detected Requelt

STRB 4 RO
B.t 7

Hard
. Bit 6

Write
. Bit 5

File
B.t4

Seek
. B.t3
Sector
Address
it
Bit 2
Data
Mark
. Bit 1

CRC
. BitO

Data
.
Error Error Inoperable Error Error Transfer
Undetected Undetected

B.t6 B.t 5 Bit 4 Bit 3 Bit 2

Not Used

Bit 6 B.t5 Bit 4 B.t 3 Bit 2

7 Bit Search Track AJcJress
RO - Read Only "Cleared by Reset
WO - Wrote Only
R/W - Read/Wrote

MACRO COMMANDS
Hex Code Instruction Hex Code Instruction
2 STZ A FFR
3 SEK B FFW
4 SSR C MSR
5 SSW 0 MSW
6 RCR
7 SWD

4-439
 MC6843

TABLE 8
Table 8 IS a list of all error flags showing what conditions will cause the error,
the instructions for which they are valid, and what conditions reset them.

Name Flag Set Condition Reset Condtiion Command

Track Not STRAS The track address that IS read from the disk does not Upon Issuance of SSW. SSW, SSR, SWD,
Equal comClde wIth the content of the L TAR SSR, SWD, RCR,: MSR, RCR,MSR,MSW
MSW command
Data Transfer STRBO DUring the data transfer between the dnve and the Reading of STAB SSW, SSR, SWD,
Error MPU or memory, an overrun or underflow occurs RCR, MSR, MSW,
FFR, FFW
CRG Error STRBl In checking the CRe of an 10 field or a Data field, Reading of STRB SSW, SSR, SWD,
a CRG error occurs RCR, MSR, MSW,
(FFR)
Data Mark STRB2 If data address mark (FB or FS) IS not detected within Upon Issuance of SSW, SSR, SSR, RCR, MSR
SWD, RCR, MSR, MSW
Undetected 32 bytes after the address I D field has been detected Command
Sector Address STRB3 (1) The sector address that comcldes with the contents Reading of STRB SSW, SSR, SWD,
Undetected of the SAR does not eXist on the track RCR,MSR,MSW
(2) A CRC error occurs In checkmg the 10 field
Seek Error STRB4 STZ

I
During a STZ command, the TKZ Input remams low Reading of STRB
after 83 pulses have been Issued on the STP output
FI STRB5 File Inoperable Input IS high Readmg STR B causes the SSW, SWD, MSW,
FIR output to go High This FFW
should reset the F I Input
Wrl'~e Error STRB6 The WPT Input IS high, and a write opecatlOn Reading of STRB with SSW, SWD, MSW,
IS executed either WGT or WPT reset, FFW
Hard Error STRB7 DUring the executl01 of command (Busy IS 1) the Reading of STRB All commands
ROY Input becomes low.

4-440
 MC6844
® MOTOROLA
(1.0 MHz)
MC68A44
MC68844
(1.5 MHz)

(2.0 MHz)

DIRECT MEMORY ACCESS CONTROLLER (DMACI MOS

The MC6844 Direct Memory Access Controller IDMAC) performs the IN-CHANNEL, SILICON-GATE)
function of transferring data directly between memory and peripheral
device controllers. It directly transfers the data by controlling the ad- DIRECT MEMORY
dress and data bus In place of an MPU In a bus organized system
The bus Interface of the MC6844 Includes select, read/Write, inter- ACCESS CONTROLLER
rupt, transfer request/grant, a data port, and an address port which (DMAC)
allow data transfer over an B-blt bidirectional data bus. The funtlonal
configuration of the DMAC IS programmed via the data bus The Inter-
nal structure proVides for control and handling of four IndiVidual chan-
nels, each of which IS separately configured Programmable control
registers provide control for data transfer location and dat~ block
length, IndiVidual channel control and transfer mode configuration, ,.. :A'fiilill c~&~l~~
1'\11 \\111
Priority of channel servicing, data chaining, and Interrupt control
Status and control lines proVide control to peripheral controllers
Ir 1

~ SSUFFIX
The mode of transfer for each channel can be programmed as one of
two Single-byte transfer modes or a burst transfer mode.
TYPical MC6844 applications are a Floppy Disk Controller IFDCI and

•
, " , CERDIP PACKAGE
an Advanced Data Link Controller IADLC) DMA Interface I ' CASE 734
MC6844 features Include

~~"'''"
• Four DMA Channels, Each HaVing a 16-Blt Address Register and
a 16-Blt Byte Count Register
• 2 M Byte/Sec MaXimum Data Transfer Rate
• Selection of Fixed or Rotating PriOrity Service Control 1.. : (PLASTIC)

• Separate Control Bits for Each Channel

• Data Chain Function
• Address Increment or Decrement Update
• Programmable Interrupts and DMA End to Peripheral Controllers PIN ASSIGNMENT

Vss E
CS/Tx AKB 39 RffiT
R/VII 38 OGRNT
FIGURE I - M6800 MICROCOMPUTER FAMtL Y AD 37 ORal
BLOCK DIAGRAM
Al OR02

I M,e.oproeassor I A2
A3
Tx AKA
lXS'!'B
A4 TRQ/OENO

~
Read Only
Memory

Random
I A5
A6
Tx ROO
Tx ROI

A7 Tx R02

~ I
Access
fvlemory AB 12 Tx R03
A9 13 00
Peripheral

H Controller
J AID
All
14
15
01
02

,I
H MC6844
D.-rect
Memory Access
A12
A13
16
17
03
04
A14 18 05
Address Data A15 19 06
Bus Bus
Vee 20 07

4-441
 • 3:

R/W
FIGURE 2 -

AO-A4
BLOCK DIAGRAM OF DMAC

A5-A15 DO-D7 i
3:
Address Address ~
b-rt 'r
Data Bus

r+
Bus
Control
Bus
Bulter
Bus
Buffer
Buffer
J ~•
~
IAQ/
3:
f-+- ROtDEND
r--- ~
Control
~
CSIT
~ f- ....
Aeglster
L t
.t.
MPX Select Address Latco
.... ,.-
_0
Addreso Byte Count
increment/ Decrementer Decrementer
~
n 3
~
I-- Address
#0 H
I L Register _____
#0 H .1 _____
L
DAQ1 - ;'-H---:-- -"L--- 116x41 #1 H I L
DGANT
DRQ2
DRQ
Control
------t--------
#2 H I L
------"-------
I
--'"
r
-----+-----
r-_.!2_H__ ~ +__ __
r-- #3 H L
Channel
Control
#3 H L

Byte Count Register 116 x 41

#0 Register
------ 18x41
#1 Tx AQO
----- Tx RQ1
#2
----- Tx RQ/
Tx AQ2
Mode/Timing #3 Tx AK
E DMA Control General Control ~ Tx RQ3

--PCA 151
-----
ICR 151
-----
-DCA
Control
Register Pnorlty
Control
~

I+-
t:: ~

Tx AK f.-.-
~ Encoder~ Tx AKA
Tx STB

~'---
--
141

fJ
RESET
Vec
VSS ITx AKBI
~
~----------
MC6844-MC68A44- MC68B44

MAXIMUM RATINGS
Rating Symbol Value Unit This device contains Circuitry to protect the
Inputs against damage due to high statiC
Supply Voltage VCC· -03to +70 V
voltages or electnc fields, however, It IS ad-
Input Voltage Y,n -03to +70 V vised that normal precautions be taken to
Operating Temperature Range lL to TH aVOId application of any voltage higher than
MC6844, MC68A44, MC68B44 TA o to + 70 'c maximum rated voltages to thiS hlgh-
MC6844C, M C68A44C -40 to +85 Impedance Circuit Reliability of operation IS
Storage Temperature Range Tstg -55to +150 'c enhanced If unused Inputs are tied to an ap-
propriate logic voltage level (e 9 , either V S S
or VCCI
THERMAL CHARACTERISTICS
Characteristic Symbol Value Unit
Thermal Resistance
PlastiC 100
6JA 'C/W
Ceramic 50
Cerdlp 60

POWER CONSIDERATIONS

•
The average chip-Junction temperature, T J, In 'C can be obtained from
TJ=TA+(POoOJA) (1)
Where,
T A = Ambient Temperature, 'C
OJA'" Package Thermal ReSistance, Junctlon-to-Amblent. °C/W
PD= PINT+ PPORT
PINT= ICC x VCe. Watts - Chip Internal Power
PPORT = Port Power DISSipation, Watts - User Determined
For most applicatIOns PPORT<C PINT and can be neglected PPORT may become significant If the deVice IS configured to
drive Oarllngton bases or Sink LED loads
An approximate relationship between PD and T J (,f PPORT IS neglected) IS
Po = K - (T J + 273°C) (2)
Solving equations 1 and 2 for K gives
K = PDon A + 273°CI+OJAoP 0 2 (3)
Where K IS a constant pertaining to the particular part K can be determined from equation 3 by measuring PD (at eqUilibrium)
for a known T A USing thiS value of K the values of Po and T J can be obtained by solving equations (1) and (2) IteratIVely for any
value of T A

DC ELECTRICAL CHARACTERISTICS (VCC = 50 Vdc ± 5%, VSS= 0, T A = TL to TH unless otherwise notedl

Characteristic Symbol Min Typ Max Unit
Input HIQh Voltag~e All Inputs Vlti VSS + 2 0 - Vrr V
Input Low Voltage CS/Tx AKB VSS-03 - VSS + 0 6
VIL V
Other Inputs VSS-O 3 - VSS + 0 8
Input Leakage Current (V ,n = 0 to 5 25 V) Tx ROO-3, E, RESIT, OGRNT lin - - 25 ~A
Three-State Leakage Current AO-A15, R/W
ITSI -10 - 10 ~A
(V ,n =04to24VI 00-07
Output High Voltage
IILoad= -205~A 00-07 VSS+24 - -
VOH V
IILoad= -145~AI AO-A15, Riw VSS + 2 4 - -
IILoad= -100~AI All Others VSS + 2 4 - -
Output Low Voltage (ILoad = 1 6 mAl All Others VOL - - VSS+04 V
Source Current (V in = 0 V, Figure 101 CS/Tx AKB ICSS - 10 16 mA
Internal Power DISSipation (Measured at T A = TL to TH) PINT - 500 750 mW
Capacitance (V,n =0, T A=25'C, f= 1 0 MHzl E - - 20
00-07, CS, AO-A4, Riw C,n - - 125 pF
All Others - - 10
Cout - - 12 pF

4·443
 MC6844·MC68A44·MC68B44

MPU MODE TIMING (See Notes 1 and 2)

ldent. MC61144 MC68A44 MC68844
Characteristic Symbol Un~
Number MIn Max MIn i Max Min Max
1 Cycle T,me tcvc 10 10 067 10 05 10 fJS
2 Pulse W,dth, E Low PWFI 430 9500 280 9500 210 9500 ns
3 Pulse WIdth, E HIgh PWEH 450 9500 280 9500 220 9500 ns
4 Clock RIse and Fall T,me tr,tf - 25 - 25 - 20 ns
9 Address Hold TIme tAH 10 - 10 - 10 - ns
13 Address Setup TIme Before E tAS 80 - 80 - TBD ns
14 ChIp Select Setup TIme Before E tcs 80 - 60 - 40 - ns
15 ChIp Select Hold T,me tCH 10 - 10 - 10 - ns
18 Read Data Hold TIme tDHR 20 - 20 - 20 - ns
21 Write Data Hold Time tDHW 10 - 10 - 10 - ns
30 Peripheral Output Data Delay T,me tDDR - 290 - 160 TBD ns
31 Peripheral Input Data Setup TIme tDSW 165 - 60 - 60 I- ns

II FIGURE 3 - MPU MODE TIMING

R/VV,Addre$----rt~~~~~~~~--------~~~~--_l~------------------------------------tl~7\~
(Non-Muxed)

cs
Note 7 __--1'-+-/

Read Data MPU Read Data Non-Muxed

Non-Muxed __~r+__~P-----------------~~~~~~~f1~~--------------~ ________________+-~~~

Wnte Data
Non-Muxed _---1+_~

NOTES
1 Voltage levels shown are VLSO 4 V, VH2:2 4 V, unless otherwise specified
2 Measurement POints shown are 0 8 V and 2 0 V, unless otherwIse specified

4·444
MC6844- MC68A44-MC68B44

FIGURE 4 - MODE 1 TIMING

(TSC STEAL MODE)

----MPU - _ _ _~
.. I Dead I-- DMA--i Dead !--MPU--
Stretched
E
(MPU) ___ -'
,r--\\. __ ...Jt--\ ~ ________________________ ...J
,,-\\
E
(DMAC)

Tx RQ

DRQ1

DGRNT

Tx STB
•
Tx AKA

CSITx AKB [j] OJ

----------------~
AO-A15. RiVii
(Output) - - - - - - - - - - - - 1 f - - + < 1

AO-A4. RiVii'
IInput)

IRQ/DEND
___ ______ ~----_--J
T
IRO DEND
OJ CS Open Collector Input
CD Tx AK B Output

4·445
 MC6844- MC68A44- MC68B44

FIGURE 5 - MODE 2 TIMING

(HALT STEAL MODEl

MPU ~ Oead i-- DMA ---.j Dead ~-MPU -

Tx RO

DR02

• DGRNT

Tx STB

Tx AKA

CS/Tx AKB W
AO-A15, R/W
IOutput)

AO-A4, R/W
!Input}

\
----------=---------------i-J ,
IRO tDED2~ ~ tDEDl t--
OJ CS Open Collector Input DEND lAO

I1J Tx AKB Output

4·446
 3:

FIGURE 6 - MOOE 3 TIMING

(HALT BURST MODEl
i
3:

I
3:
Tx AQ
~to
DRQ2
:t
DGRNT

Tx STB

J:>.
.io. Tx AKA
J:>.
......
Cs/Tx AK8

AO-A15, R/W
(Output}

AO-A4, R/W ') (

(Input)

IRQ DEND iR6

ill CS Open Collector Input
WTx AKB Output
·No transfer (dummy cycle) because Tx AQ was negated at start of E cycle

II
 MC6844-MC68A44-MC68B44

DMA TIMING (Load Condition Figure 71

MC6844 MC68A44 MC68B44
Characteristic Symbol Unit
Min Max Min Max Min Max
Tx RO Setup Time
E RIsing Edge tTOSl 120 - 120 - 120 - ns
E Failing Edge trOS2 210 - 210 - 170 -

Tx RO Hold Time
E RIsing Edge tTOHl 20 - 10 - 10 - ns
E Failing Edge tTOH2 20 - 10 - 10 -

DGRNT Setup Time tOGS 155 - 125 - 115 - ns

DGRNT Hold Time tn(;H 10 - 10 - 10 - ns
Address Output Delay Time AO-A15, R/W tAD - 270 - 180 - 150 ns
Address Output Hold Time AO-A15, R/W t HO 30 - 20 - 20 - ns
Address Three-State Delay Time AO-A15, R/W tATSD - 720 - 460 - 370 ns
Address Three-State Recovery Time tATSR - 430 - 280 - 210 ns
Delay Time DR01,DR02 tDOD - 375 - 250 - 200 ns
Tx AK Delay Time

•
E RISing Edge tTKDl - 400 - 310 - 250 ns
DG RNT RISing Edge !TKn? - 190 - 160 - 145
IRO/DEND Delay Time
E Failing Edge tDEDl - 300 - 250 - 230 ns
DGRNT RISing Edge tDED2 - 190 - 160 - 145
Tx STS Output Delay Time tTD - 270 - 180 - 150 ns
Tx STS Output Hold Time lTH - 20 - 20 - 20 ns

FIGURE 7 - TEST LOADS FIGURE 8 - CS/Tx AKB

SOURCE CURRENT TEST CIRCUIT

50 V r --------------,
I Vee I
25 k
01
: ~IIC"
02 I I
e A 03
I TxAKB r

04 I I
I Vm = DC Ampere
Meter
I
Test Pm C = pF R -kn I
I Enable Vss
00-07 130 11 7
I cs Input
AO-A15, R/W 90 165
I' - _ _ _ _ _ _ _ _ _ _ _ _ -1
CS/Tx AKB 50 24
Others 30 24

4-448
MC6844. MC68A44.MC68B44

INTRODUCTION DMAC BUS CONTROL

Dunng DMA operation, the DMAC controls the system
The MC6844 DMAC has four DMA channels which can be address and data buses and generates system R/W The
Independently configured by software uSing fifteen ad- DMAC also generates Tx STB, which can be used to denve
dressable registers. Eight of the addressable registers are system VMA, Tx AKA and Tx AKB, which can be used to
16-blt registers, and seven are 8-blt registers Associated Identify which DMA channel IS In serVice, DR01 and DR02,
with each channel are a 16-blt Address Register, a 16-blt which are used for handshaking with the system MPU,
Byte Control Register, and an 8-blt Channel Control DEND, which IS asserted when the last byte of a data block IS
Reglster.The DMAC also has three 8-blt registers which af- being transferred, and IRO, which when enabled will Inter-
fect all of the channels: the Pnorlty Control Register, the In- rupt the system MPU when a data block transfer IS com-
terrupt Control Register, and the Data Chain Register. A pleted Data Itself does not pass through the DMAC, but IS
block diagram of the DMAC IS presented In Figure 2. transferred between memory and peripheral under control of
the DMAC
SOFTWARE INITIALIZATION
A channel IS initialized for DMA by loading the channel ad- TRANSFER MODES
dress register with the deSIred starting DMA address and the
channel byte control register with the number of bytes to be Each DMAC channel can be programmed to operate In
transferred In addition, the channel control register must be one of three modes' Two of the modes, mode 1 and mode
initialized for the direction of data transfer, for address 2, are single-byte transfer modes In which the DMAC returns
register Increment or decrement after each byte transfer, and the bus to the MPU after each DMA transfer by negating the
for DMA transfer mode. appropriate DMA Request IDR01 or DR02) These modes

•
Each channel can be initialized for one of three transfer are Intended to be used In applications requiring the MPU to
modes Mode 1, Mode 2, or Mode 3. Two read-only status regain control of the bus after each byte transfer Timing In-
bits In the channel control register indicate when the channel formation for modes 1 and 2 IS presented In Figures 4 and 5
IS busy transferring a block of data and when the DMA Mode 3 IS a block transfer mode In which the DMAC re-
transfer of a block of data IS complete tains control of the bus until the last byte of the DMA data
The pnonty control register, the Interrupt control register, block has been transferred Ibyte control register 0), If
and the data chain registers must also be Initialized DGRNT remains asserted dUring the entire block transfer In
The pnonty control register enables/ disables each channel mode 3, byte transfers are pOSSible at the DMAC clock fre-
and determines whether channel service requests are servIc- quency by asserting Tx RO each cycle ThiS mode offers the
ed In a fixed or a rotating pnonty The Interrupt control highest DMA transfer rate Mode 3 timing IS presented In
register controls assertion of IRO Interrupt by each channel Figure 6
at the end of a data block transfer and sets a flag when IR0 IS A flowchart of DMAC operation In each mode IS presented
asserted The data chain register controls selection of two or In Figure 9
four channel operation, selection of data chaining operation,
and the channel to be updated In the data chaining mode FUNCTIONAL PIN DESCRIPTIONS
When data chaining IS enabled, the contents of the chan-
nel3 address and byte count registers are stored Into the cor- VCC AND VSS
responding registers of the channel selected for chaining VCC and VSS prOVide power to the DMAC The power
after the channel data block transfer IS completed This supply should prOVide +5 V ±5% to VCC VSS should be
feature allows for repetitively reading or wntlng a block of tied to ground Total power diSSipatIOn will not exceed Po
memory mililwatts

HARDWARE INITIALIZATION RESET

At power-on reset (POR) and anytime RESET IS asserted, ThiS Input IS used to place the DMAC Into a known state
all device registers except the address and byte count and prOVide for an orderly startup procedure Assertion of
registers are cleared Therefore, the state of the DMAC after RESET clears all Internal registers except the address and the
reset IS as follows byte count registers Isee Hardware Initialization)
• all DMA channels are disabled,
E (ENABLE)
• all Interrupts are disabled,
ThiS TTL-compatible Input IS used to clock the DMAC
• all flags are cleared, with the MPU E clock. In systems that perform single-byte
• address register decrement IS selected fa! each transfers by stretching the MPU clock rather than by halting
channel, the MPU, the system must be deSigned to provide a non-
• mode 2 IS selected for each channel, stretched E clock to thiS Pin Clock modules such as the
• penpheral controller wlrte-to-memory IS selected for MC6875 are available which provide a separate stretchable E
each channel, clock to externally-driven MPUs and a non-stretched clock to
• two-channel operation IS selected, and the DMAC
• data chaining IS disabled 'Modes 1, 2, and 3 are also called TSC Steal, HALT Steal, and
HALT Burst modes

4·449
 MC6844· MC68A44.MC68B44

FIGURE 9 - FLOWCHART OF DMAC OPERATION

Initial State Walt

for Programming

Walt for Tx RQ
Input
Checked E . - r -

• Walt for
Tx RO
Input

CheckedE"t-

DMA Transfer
IAO-A15, Riw, Tx ST8,
Tx AKA/8 Output

Burst
Mode

4-450
MC6844· MC68A44. MC68B44

READ/WRITE (R/W) DMA REOUEST 1-2 (DR01, DR02)

This TTL-compatible bidirectional line IS a high-Impedance These active low TTL-compatible outputs are used by the
Input when the DMAC IS off the system bus (MPU mode), DMAC to handshake With the MPU In requesting the system
and an output when the DMAC IS controlling the bus (DMA bus for DMA operation DRQl IS asserted to Indicate that a
mode) In the MPU mode, this Input IS used to control the channel configured for mode 1 operation reqUires servIcing,
direction of data transfer through the DMAC data bus Inter- and DRQ2,s asserted to indicate that a channel configured for
face to allow MPU reads and writes to Internal registers In mode 2 or mode 3 operation requires servIcing Once
the DMA mode, Read/Write IS an output to the system bus, asserted, each output remains asserted until the DMAC
with ItS state controlled by bit 0 of the appropriate channel completes one DMA byte transfer In mode 1 and mode 2
control register DMA, or an entire byte block transfer In mode 3 DMA

ADDRESS AO-A15 DMA GRANT (DGRNT)

Address lines AO-A4 are bidirectional In the MPU mode, ThiS high-Impedance Input IS used to enable MC6844
these lines are Inputs used by the MPU to address DMAC DMA operation and should be asserted only after the MPU
registers In the DMA mode, these lines and lines A5-A 15 are has relinquished the system bus to the DMAC TYPically,
outputs which assert the contents of the address register of DGRNT will be asserted by the MPU In response to A DMA
the channel being serviced Address lines AO-A 15 are TTL request, Indicating that the system bus IS available for DMA
compatible
TRANSFER STROBE (Tx STB)

•
DATA DO-D7 T x STS IS asserted dUring each DMA transfer cycle and
These bidirectional TTL-compatible lines are used for data can be used as a transfer acknowledge for peripheral con-
transfer between the MPU and the DMAC These lines re- trollers and as a system VMA Tx STS IS a TTL-compatible
main In the high-Impedance state except when the MPU output
reads DMAC registers,
TRANSFER ACKNOWLEDGE A (Tx AKA)
INTERRUPT REQUEST/DMA END (lRO/DEND) Transfer Acknowledge A IS asserted dUring DMA opera-
tion and can be used With Tx AKB to Identify the DMA chan-
Interrupt Request/ DMA End IS a TTL-compatible, tlme-
nel being serviced, as shown In Table 1
multiplexed, active low output used to Interrupt the MPU
and Signal a peripheral controller when a DMAC data bl0ck
CHIP SELECT/TRANSFER ACKNOWLEDGE B
transfer has ended DEND IS asserted dUring the transfer of
(<:S/Tx AKB)
the last data byte of a block transfer for one E clock cycle
(see Figures 4, 5, and 6), IRQ IS asserted after the last byte ThiS bidirectional Pin serves two functions DUring MPU
transfer of a block transfer If enabled by setting the proper operation It IS a chip-select Input which when asserted allows
DEND IRQ enable bit In~e Interrupt control register (see MPU access to the DMAC registers DUring DMA transfers
Table 2) Once asserted, IRQ IS negated by reading the chan- thiS pin IS for Tx AKB output, used With Tx AKA to Identify
nel control register of the channel asserting the Interrupt the DMA channel being serviced (see Table 1)

TRANSFER REOUEST (Tx Roo-3)

Associated With each channel IS a high-Impedance Input TABLE 1 - ENCODING ORDER
Pin used by a peripheral controller to request DMA service by
the channel. The Tx RQ PinS are sampled by the DMAC In an CS/Tx AKB Tx AKA Channel #
order of Priority determined by the software-programmable 0 0 0
state of the Priority control register The Tx RQ PinS for 0 1 1
channels programmed for mode 1 or mode 2 operation 1 0 2
(Single-byte transfer modes) are sampled on the rising edge
1 1 3
of E If Tx RQ for one of these channels IS asserted when
sampled, the DMAC Will perform one DMA byte transfer for
the channel before sampling the Tx RQ pin of the channel
next In the Priority The T x RQ pins for channels programm- DMAC REGISTERS
ed for mode 3 operation (block transfer mode) are sampled
on the rising edge of E for the first DMA byte transfer only If All DMAC registers are read/write regslters, although
a Tx RQ for one of these channels is asserted when sampled, some of the register status bits are read-only Table 2
the first byte of the channel data block IS transferred, then presents a summary of the DMAC control registers, and
the Tx RQ pin IS sampled on failing edges of E for subs3- Table 3 !ists address and byte count register addresses,
quent byte transfers (see Figure 6) Once a channel program-
med for mode 3 operation begins DMA, that channel has ADDRESS REGISTERS
PriOrity of servIcing until the channel completes ItS entire ASSOCiated With each DMA channel IS an address register
block transfer which stores the 16-blt address to be asserted on the system

4-451
 MC6844· MC68A44. MC68B44

TABLE 2 - DMAC CONTROL REGISTERS

Addreos Register Content

Register
(Hexl Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DMA End
Channel Busy/Ready Address Read/Write
1x· Flag Not Used Not Used MCA MCB
Control Flag Up/Down IR/W)
IDENDI
Request Request Request Request
PriOrity Rotate
14 Not Used Not Used Not Used Enable #3 Enable #2 Enable #1 Enable 10
Control Control
IRE31 IRE2) IRE1) IREo)
DEND DEND IRQ DEND IRQ DEND IRQ DENDIRQ
Interrupt
15 IRQ Not Used Not Used Not Used Enable #3 Enable #2 Enable #1 Enable #0
Control
Flag IDIE3) IDIE2) IDIEll IDIEo)
Two/Four Data Chain Data Chain
Data Chain
Data Chain 16 Not Used Not Used Not Used Not Used Channel Channel Channel
Enable
Select 12/4) Select B Select A

·The x represents the binary eqUivalent of the channel deSired

II TABLE 3 - ADDRESS AND BYTE COUNT REGISTERS

Register

Address High
Channel

0
Address
I Hex)
0
bytes to be transferred by a channel before the channel
begins DMA The byte count register IS decremented at the
beginning of a DMA cycle

Address Low 0 1
CHANNEL CONTROL REGISTERS
Byte Count High 0 2 A channel control register associated With each channel IS
used to control the channel mode of operation, the state of
Byte Count Low 0 3
the R/W line dUring DMA, and whether the channel address
Address High 1 4
register Will Increment or decrement after each DMA cycle
Address Low 1 5 The channel control registers contain two read-only status
Byte Count High 1 6 flags which report the status of the channel The channel
Byte Count Low 1 7 control register bits are defined as follows
Address High 2 8 Bit 0 R/W Read/Write The direction of DMA transfer IS
Address Low 2 9 determined by the state of thiS bit When thiS
Byte Count High 2 A bit IS a "1", R/W Will be asserted high by the
B'/Ie Count Low 2 B
DMAC dUring DMA, and memory Will be read
by the peripheral controller When thiS bit IS a
Address High 3 C
"0", R/W Will be asserted low by the DMAC
Address Low 3 D dUring DMA and data transfer Will be from the
Byte Count High 3 E peripheral controller to memory
Byte Count Low 3 F Bit 1 MCB Mode Control B ThiS bit IS used to select the
channel DMA mode When thiS bit IS a "1",
mode 3 operation IS selected When thiS bit IS
address bus dUring the next DMA cycle of the channel After clear, either mode 1 or mode 2 operation IS
each DMA byte transfer, the address register Will Increment selected according to the state of channel con-
or decrement according to the state of bit 3 of the ap- trol register bit 2 Table 4 shows the DMA
propriate channel control register The starting address of a mode options.
DMA data block should be stored In the address register of a
channel to be used before beginning DMA operation With
TABLE 4 - DMA MODE SELECT
the channel
MCA MCB DMA Transfer Mode
0 0 Mode 2
BYTE COUNT REGISTERS 0 1 Mode 3
Each channel has a 16-blt byte count register which stores 1 0 Mode 1
the number of DMA cycles remaining In a channel DMA 1 1 Undefined
block. ThiS register should be loaded With the number of
MC6844-MC68A44-MC68844

Bit 2 MCA Mode Control A. This bit IS used with MCB to INTERRUPT CONTROL REGISTER
select the channel DMA mode. When MCB IS The Interrupt control register allows the user to selectIVely
set, this bit must be clear and mode 3 opera- enable each channel IRQ Interrupt When enabled, an IRQ IS
tion IS selected Setting both MCA and MCB generated when a DMA block transfer IS complete The in-
to a "1" places the DMAC Into an undefined terrupt control register also has a flag to indicate that the
mode of operation With MCB clear, setting DMAC IRQ IS asserted Interrupt control register bits are
M CA to a "1" places the channel Into mode 1 defined as follows·
and clearing MCA places the channel Into Bits 0-3 DIEO-3 DEND IRQ Enable These bits enable in-
mode 2 (see Table 21. diVidual channel IRQ Interrupts when set to
Bit 3 Address Up/ Down Bit 3 controls address "1", and mask these Interrupts when
register Increment/decrement dUring DMA If cleared The register bit number IS the same
this bit IS set to a "1", the address register in- as the channel number controlled by the
crements with each DMA cycle, If It IS clear, bit. An IRQ IS asserted only when a DMA
the address register decrements with each block transfer IS completed
DMA cycle Bits 4-6 Not used
Bits 4-5 Not used Bit 7 DEND IRQ Flag ThiS read-only bit IS set to
Bit 6 Busy/Ready Flag The Busy/Ready flag IS a "1" when the DMAC IRQ IS asserted, in-
read-only status bit that ,nd,cates a DMA block dicating the end of a channel block transfer
transfer IS In progress In the channel. After In-

•
IDEND assertion) With Interrupt enabled
ItialiZing the channel for a block transfer (ad- ThiS flag IS cleared and IRQ IS negated by a
dress register, byte count register, etc ), thiS read of the channel control register of the
flag sets when T x RQ IS recognized and clears channel causing the IRQ Interrupt.
dUring the last block byte transfer
Bit 7 DEND DMA End Flag IDEND) The DEND flag IS used DATA CHAIN REGISTER
to indicate when a DMA transfer IS complete. Repetitive reading or writing of a block of memory can
ThiS flag IS set dUring the transfer of the last best be performed uSing the data chain function ThiS func-
byte of a DMA block and IS cleared by reading tion transfers the contents of the channel 3 address and byte
the channel control register ThiS flag will count registers Into the respective registers of the channel
generate an IRQ Interrupt If enabled In the In- selected for data chaining These contents are transferred
terrupt control register dUring the E cycle follOWing the transfer of the last byte of a
block by the selected channel The data chain register IS
PRIORITY CONTROL REGISTER defined as follows·
The Prlonty Control Register IS used to IndiVidually enable Bit 0 DCE Data Chain Enable Data chaining IS en-
each DMA channel and to select the channel service priority abled when thiS bit IS set to a "1" When
scheme, With bits defined as follows thiS bit IS clear, data chaining IS disabled
Bits 0-3 REO-3 Request Enable 0-3 Each DMA channel IS In- Bit 1-2 DCA/ B Data Chain Select A, B The state of these
diVidually enabled by setting the appropriate two bits determine which channel Will be
RE bit (R EO for channel 0 etc) In the PriOrity updated when data chaining IS enabled, as
control register A clear channel RE bit 10- listed In Table 5
hlblts recognition of Tx RQ for the channel Two/Four Channel Select The DMAC Will
Bits 4-6 Not used operate With either two channels or four
Bit 7 Rotate Control One of two channel service channels, depending on the state of thiS
Priority schemes can be selected by bit 7 bit When thiS bit IS set to a "1", the four-
When thiS bit IS "0", the fixed Priority of ser- channel mode IS selected, and all four chan-
vIcing IS selected In which channel 0 has nels are selectable When thiS bit IS clear,
highest PriOrity, channel 1 has the next the two-channel mode IS selected and only
highest PriOrity, channel 2 the next highest channels 0 and 1 are selectable
PriOrity, and channel 3 the last Priority When Bits 4-7 Not used
thiS bit IS set to a "1", the rotating PriOrity of
servIcing IS selected. Rotating priority IS In-
TABLE 5 - CHANNEL SELECT
Itially the same as fixed PriOrity, In that the
lower numbered channels Initially have the DCB Bit 2 DCA Bit 1 Channel #
higher pmoltles However, once a channel IS 0 0 0
serviced In the rotating PriOrity mode, that 0 1 1
channel IS given last Priority of servIcing In 1 0 2
thiS scheme the channel last serviced gets 1 1 Undefined
the last priority

4-453
 MC6844· MC68A44.MC68844

APPLICATIONS Each CirCUit uses DMA GRANT to demultiplex the

IRQ/DEND DMAC output to ensure that the system IRQ IS
The MC6844 DMAC can be Interfaced to a wide variety of asserted at the proper time, only dUring MCU operation
MPUs, Including the Motorola MC68000 This section offers Whenever DMA GRANT IS high, IRO IS negated
examples of MC6844 Interface CirCUitS that can be used as The CIrCUitS also generate DEND and Tx AK for the pro-
starting POints In designing the DMAC Into a particular per channel, gated by Tx STB
system. The one-channel DMA mode requires no channel
decoding, so for thiS mode Tx AK IS derived from Tx STB
IRQ, DEND, Tx AK GENERATION directly, and Tx STB IS used to demultiplex the IRQ/DEND
Derivation of IRQ (Interrupt Request), DEND (DMA End), output for DEND generation
and Tx AK (Transfer Acknowledge) for one, two, and four- The two-channel mode CirCUit IS similar to the one-channel
channel DMA IS shown In Figure 10 IRO, If enabled, IS CIrCUit, but uses Tx AKA to Identify the active channel and
asserted by the DMA to Interrupt the MPU whenever a DMA generate the appropriate channel Signal (see Table 1)
block transfer IS completed. Tx AK IS asserted dUring each The four-channel CirCUit IS functionally Similar to the two-
DMA cycle and IS used to handshake with a peripheral con- channel CirCUit but uses a 74LS139 to decode Tx AKA and Tx
troller each time a DMA byte transfer occurs DEND IS used AKB for channelldentlflcallon The DMAC CS/Tx AKB Din
to handshake with a peripheral controller each time a DMA IS bidirectional dUring four-channel operation, so an open
block transfer IS complete collector gate must be used to drive CS In order to aVOid

•
drive contention

FIGURE 10 - IRQ, DEND, Tx AK GENERATION

I RQ (Open Collectod TAO (Open Collector)

DGRNT DEND 0
DGRNT

DEND 0 DEND 1

>>---~----- Tx AK a
~~r----"TxAKO

TxAKA NC ~~~---~TxAKl
TxAKA

CS/Tx AKB

IRQ IOpen Collectod

DENDO DENDl DEND2 OEND3

DGANT

IRO/OEND

TxSTBr-------;---,

TxAKAr------;--; ~>--~--+---+---+---TxAKO

)c~--~~--r---r--TxAKl
CS/Tx AKB r--.---;--;A 1 ~ _ _ _ _ _ _ _ ___ ~ ~r-_TxAK2

(Open >>--________ ~~-TxAK3

Collectorl

cs

4-454
MC6844-MC68A44-MC68B44

MC68000 BUS ARBITRATION INTERFACE DUring mode 2 or 3 DMA operation, the clock generator
Figure 11 shows an MC6844/ MC68000 Interface for has no control over DMA Grant To prevent DMA operation
DMAC mode 2 or mode 3 operation. The MC68000 Advanc- In mode 1 dunng a memory refresh cycle, system E
ed Information Data Sheet should be consulted for complete must be gated With refresh grant DGRNT must be the
understanding of the circuit ORed output of bus available IBA) and DMA grant from
The MC6844 must be Initialized for transfer mode, byte the clock generator In order to support all 3 DMA modes of
count, DMA starting address, etc. operation
Initially DGRNT IS low, BGACK output IS high, and Tx DUring the DMA cycle, a system VMA Signal must be
STB IS high. The MC6844 responds to a Tx RQ by asserting generated by the DMAC ThiS IS done by ORlng Tx STB and
DRQH Assertion of Tx RQ also asserts MC68000 BR For the MPU VMA line
DMA transfer, two conditIOns must be met· 1) DMAC DRQH
must be asserted and 2) all bus masters must relinqUish the MC6844/MC6809 BUS ARBITRATION INTERFACE
system bus Once DRQH IS asserted It remains asserted low An MC6844/MC6809 Interface IS presented In Figure 13
until DMA byte transfer In the halt-steal mode or until the last ThiS CIrCUit ensures that MC6809 DMA/BREQ IS asserted
byte of a DMA memory block IS being transferred In the halt- only dUring Q high, an MC6809 requirement The CIrCUit Will
burst mode A relinqUishing of the bus by all bus masters IS also generate a system VMA Ivalld memory address), often
Indicated by negated BGACK, AS, and DTACK after the referred to as DMA VMA
M C68000 asserts BG In response to a bus request The MC6809 does not generate a VMA output since the
When both conditions are met, the NAND flip-flop IS set only Invalid address asserted by the MPU IS $FFFF With R/W
by assertion of LSl38 03, asserting DGRNT and BGACK asserted high Therefore, an MC6809 system does not nor-

•
The DMAC then performs a byte transfer In the halt-steal mally need a VMA CIrCUit When uSing the MC6844 for DMA
mode or a block of byte transfers In the halt-burst mode In an MC6809 system, however, a VMA CIrCUit IS reqUired
The NAND flip-flop IS cleared on the rising edge of Tx STB Since the address lines are floating dunng dead cycles bet-
after asserting dUring each DMA cycle In the halt-steal ween the MPU and DMA modes DeVices on the bus must
mode, and dUring the last DMA cycle of a DMA block In the be deselected dUring thiS time
halt-burst mode Isee MC6844 timing diagrams) Initially, In the MPU mode, DRQ1/2 IS negated Ihlgh
Note that BR to the MC68000 IS negated when BGACK IS level), and the Q output of U3 IS high The output of the ex-
asserted, satisfYing an MC68000 reqUIrement clUSive OR gate U4 IS therefore a low, Inhibiting clocking of
U3 by forCing the output of U5 to remain a low. When
MC6800 BUS ARBITRATION INTERFACE DRQ1/2,s asserted low, the output of U4 changes to a high
A tYPical system deSign, uSing the MC6800/MC6844, IS If the MC6809 Q output IS high at thiS time, the output of U5
shown In Figure 12 A clock generator/driver IS used which changes to a high, clocking U3 If the MC6809 Q output IS
Will stretch the MPU clock dUring DMA operation While low at thiS time, the output of U5 Will be driven high on the
generating a non-stretched clock for system memory PriOri- next rising edge of Q, clocking U3 When U3 IS clocked, the
ty logiC IS used to give highest Priority to refresh request, Q output of U3 changes to a low asserting MC6809
since memory refresh and DMA transfers must not occur DMA/BREQ. The output of U4 at thiS time IS a low, since
dunng the same E cycles both of the U4 Inputs are low

FIGURE 11 - MC68000/MC6844 INTERFACE

BR L------.rr----<::-1=::::: ~...- ______ ~DRQ2 TxRQ

MC68000

BG~-r---I
AS~-r---I MC6844
DT ACK 1--1---1
BGACK f--<...-+---l
1-----1--\-~------~DGRNT
5V
BGACK
(Open Collector
Bufferl

4-455
 MC6844-MC68A44-MC68844

FIGURE 12 - MC6800/MC6844 INTERFACE

System
Signals

Address Bus ~ A

Data Bus

R/W

MC6800
VMA
-p- DMAC
Signals

Tx STB

r-~
IRO

HALT DR02
BA
) DGRNT
TSC
L:
<l>lJ t E

• -
MEM ClK

DMA/Ref 'Jr Ref GNT

rC U- E DMA

Clock ---
Ref RO

-
Generator/
Driver

DMA/Ref Req
DMA GNT

DMA RO

Priority
-
.. DR01

Logic

FIGURE 13 - MC6844/MC6809 INTERFACE

BS
System VMA
BA DGRNT

UI
System E
ClK
CLR System RESET

RESET RESI'T
DMAtBREO
DROl/2

o
MC6809 MC6844

After the DMA transfer, DROl/2 IS negated by the high, Indicating that the address on the system address bus
MC6844, forcing the output of U4 to a high Once again, U3 IS invalid dUring this dead cycle between MPU and DMA
will be clocked only when the MC6809 0 output IS high modes. On the next failing edge of E, Ul IS clocked high
VMA IS generated by Ul and U2 Initially, In the MPU forcing the output of U2 low dUring this DMA cycle When
mode, Ul IS clear, With a low 0 output The BA (bus BA IS negated after DMA, the output of U2 IS forced high un-
avallablel output of the MC6809 IS also a low Therefore, the til the next failing edge of E, Indicating Invalid address dUring
output of U2 (VMAI IS low (VMA asserted I When the this dead cycle
MC6809 asserts BA for DMA, the output of U2 becomes

4·456
 MC6845 MC6845*1

®
(1.0 MHz) (1.0 MHz)
MC68A45 MC68A45*1
MOTOROL.A (1.5 MHz) (1.5 MHz)
MC68B45 MC68B45*1
(2.0 MHz) (2.0 MHz)

CRT CONTROLLER (CRTC)

The MC6845 CRT Controller performs the Interface between an MPU MOS
and a raster-scan CRT display It IS Intended for use In MPU-based con-
trollers for CRT terminals In stand-alone or cluster configurations
(N-CHANNEL, SILICON-GATE)
The CRTC IS optimized for the hardware/software balance reqUired
for maximum flexibility All keyboard functions, reads, Writes, cursor
movements, and editing are under processor control The CRTC pro-
CRT CONTROLLER
vides video timing and refresh memory addressing (CRTC)
• Useful In Monochrome or Color CRT Applications
• Applications Include "Glass-Teletype," Smart, Programmable, Intel-
ligent CRT Terminals, Video Games, Information Displays
• Alphanumeric, Semi-GraphiC, and Full-Graphic Capability
• Fully Programmable Via Processor Data Bus Timing May Be Gen-
erated for Almost Any Alphanumeric Screen Format, e g ,BOx 24,
72x64, 132 x20 Ir
•
w;I! ·
~
\ I < I
l SUFFIX
CERAMIC PACKAGE
CASE 715
\,1 1 <

• Single + 5 V Supply

~''"''''
• M6800 Compatible Bus Interface
• TTL-Compatible Inputs and Outputs
.' I, " c '. l I. CERDIP PACKAGE
• Start Address Register Provides Hardware Scroll (by Page, Line, or

•
I I I ' I ,l C CASE 734
Character) I I'

~
• Programmable Cursor Register Allows Control of Cursor Format
and Blink Rate
• Light Pen Register " """, P SUFFIX
• Refresh (Screen) Memory May be Multiplexed Between the CRTC - , : - - -' PLASTIC PACKAGE
CASE 711
and the MPU Thus Removing the Requirements for Line Buffers or
External DM A Devices
'* - Package SuffiX
• Programmable Interlace or Non-Interlace Scan Modes
• 14-Blt Refresh Address Allows Up to 16K of Refresh Memory for
FIGURE 1 - PIN ASSIGNMENTS
Use In Character or Semi-GraphiC Displays
• 5-Blt Row Address Allows Up to 32 Scan-Line Character Blocks GNO VS
• By Utilizing Both the Refresh Addresses and the Row Addresses, RESET HS
a 512K Address Space IS Available for Use In GraphiCS Systems
RAO
• Refresh Addresses are ProVided DUring Retrace, AllOWing the CRTC
to Provide Row Addresses to Refresh Dynamic RAMs RAl

• Programmable Skew for Cursor and Display Enable IDE) MAl RA2
• Pin Compatible with the MC6B35 MA2 RA3
MA3 RA4
MAXIMUM RATINGS
Rating Symbol Value Umt MA4 00
Supply Voltage VCC' -03 to + 70 V MA5 01
Input Voltage Vm * -03 to + 70 V MA6 10 02
Operating Temperature Range Tl to TH MA7 11 03
M C6845, M C68A45, M C68845 TA o to 70 'c
MC6845C, MC68A45C, MC68845C -40 to +85 MAS 12 04
Storage Temperature Range TstQ - 55 to + 150 'c MA9 13 05
MAlO 14 06
THERMAL CHARACTERISTICS
Characteristic Symbol Value Rating MAll 15 07
Thermal Resistance MAI2 16 CS
PlastiC Package 100
8JA 'C/W MA13 17 RS
Cerdlp Package 50
Ceramic Package 50 OE 18

-ThiS device contains circuitry to protect the Inputs against damage due to high CURSOR 19 R/Vii
static voltages or electnc fields, however, It IS adVised that normal precautions 20 ClK
VCC
be taken to aVOid applicatIon of any voltage higher than maximum rated voltages
to thiS hlgh~lmpedance Circuit For proper operation It IS recommended that Vin
and V out be constrained to the range VSssIV ,n or VoutlsVCC

4-457
 MC6846-MC6845* 1-MC68A45-MC68A45 * 1-MC68845-MC68845* 1

FIGURE 2 - TYPICAL CRT CONTROLLER APPLICATION

~~~---------'---------------------------------+AB

L ____j--t---jr--I---------------~~--.DB Pnmary Bus

Cursor,
Display
Enable

Row Addresses

•
4

HS VS

RECOMMENDED OPERATING CONDITIONS

Characteristics Symbol Min Typ Max Unit
Supply Voltage VCC 475 50 525 V
Input Low Voltage VIL -03 - 08 V
Input High Voltage VIH 20 - VCC V

POWER CONSIDERATIONS

The average chip-Junction temperature, TJ, In °c can be obtained from

TJ = TA + IPoo8JA) (1)
Where
TA = Ambient Temperature, °c
8JA=Package Thermal Resistance, Junctlon-to-Amblent, °C/W
POEPINT+ PPORT
PINT'" ICC x VCC, Watts - Chip Internal Power
PPORT"Port Power Olsslpatlon, Watts - User Oetermlned
For most applications PPORT<C PINT and can be neglected PPORT may become significant If the device IS configured to
drive Oarllngton bases or Sink LEO loads
An approximate relationship between Po and TJ (,f PPORT IS neglected) IS
PO= K ~ (T J + 273°C) (2)
Solving equations 1 and 2 for K gives
K= POo(TA+273°C) +8JAoP0 2 (3)
Where K IS a constant pertaining to the particular part K can be determined from equation 3 by measuring Po /at eqUIlibrium)
for a known TA USing thiS value of K the values of Po and TJ can be obtained by solVing equations (1) and (2) Iteratively for any
value of TA

4·458
MC6845-MC6845* 1-MC68A45-MC68A45* 1-MC68B45-MC68B45* 1

DC ELECTRICAL CHARACTERISTICS IVcc -- 50 Vdc ± 10% VSS -- 0 T A -- 0 to 70'C unless otherlwse noted see Figures 3 51
Characteristic Symbol Min Typ Max Unit
Input High Voltage VIH 20 - VCC V
Input Low Voltage VIL -03 - 08 V
Input Leakage Current lin - 01 25 ~A
Three-State IV CC - 5 25 VI IV In - 0 4 to 2 4 VI ITSI -10 - 10 ~A
Output High Voltage
IILoad= - 205~AI 00-07 VDH 24 30 - V
IILoad= -l00~AI Other Outputs 24 30 -
Output Low Voltage II Load - 1 6 mAl VOL - 03 04 V
Internal Power DISSipation (Measured at TA-GoC) PINT - 600 750 mW
Input Capacitance 00-07 - - 125
C,n pF
All Others - - 10
Output Capacitance All Outputs Cout - - 10 pF

BUS TIMING CHARACTERISTICS ISee Notes 1 and 21 IReference Figures 3 and 41

MC6845 MC68A45 MC68B45
ldent.
Characteristic Symbol MC6845*1 MC68A45*1 MC68B45*1 Unit
Number
Min Max Min Max Min Max
1 Cycle Time tcyc 10 10 067 10 05 10 ~s

2 Pulse Width. E Low PWEL 430 9500 280 9500 210 9500 ns
3 Pulse Width. E High PWEH 450 9500 280 9500 220 9500 ns

•
4 Clock Rise and Fall Time tr.tf - 25 - 25 - 20 ns
9 Address Hold Time IRSI tAH 10 10 - 10 - ns
13 RS Setup Time Before E tAS 80 - 80 - 40 - ns
14 R/W and ~ Setup Time Before E tcs 80 - 80 - 40 - ns
15 R/W and ~ Hold Time tCH 10 - 10 - 10 - ns
18 Read Data Hold Time tDHR 20 50" 20 50" 20 50" ns
21 Write Data Hold Time tDHW 10 - 10 - 10 - ns
30 Peripheral Output Data Delay Time tDDR - 290 - 180 0 150 ns
31 Peripheral Input Data Setup Time tDSW 165 - 80 - 80 - ns
The data bus output buffers are no longer sourcing or sinking current by tOHR max (high Impedance)
FIGURE 3 - MC6845 BUS TIMING

~-------<D----~~

RS

R/W. cs

Read Data ====tl==~~~----------------------~~~~~!------==-------~==================!j==::)

Wnte Data

NOTES
1 Voltage levels shown are VLSO 4 V. VH,,2 4 V. unless otherwise specified
2 Measurement POints shown are 0 8 V and 2 0 V, unless otherwise specified

4-459
 *
MC6845·MC6845 1·MC68A45.MC68A45 1.MC68845.MC68845 1 * *

FIGURE 4 - BUS TIMING TEST LOAD

50 V

Test POint 0 - -. .- -...- 1---. RL = 24 kG

....

C MM06150
or EqUlv

C= 130 pF for 00-07

= 30 pF for MAO-MA 13, RAO-RA4,
DE, HS, VS, and CURSOR
R= 11 kG for 00-07
= 24 kG for All Other Outputs

• FIGURE 5 - CRTC TIMING CHART

DE

HS

VS

CURSOR

NOTE Timing measurements are referenced to and from a low voltage of 0 8 volts and a high voltage of 2 0 volts unless otherwise noted

4·460
 FIGURE 6 - CRTC-CLK, MAO-MA13, AND LPSTB TIMING

1 + - - - -1/fc - - - - - + I

CLK

MAO-MA13

LPSTB

tLPD2 l tLPDl
PWLPH

When the CRTC detects the riSing edge of LPSTB In

this period, the CRTC sets the Refresh Memory Ad-
dress 'M + 2' Into the LIGHT PEN REGISTER

tLPD1, tLPD2 Period of uncertainty for the Refresh

Memory Address

NOTE Timing measurements are referenced to and from a low voltage of 08 volts and a high voltage of 2 0 volts, unless otherWise noted
•
CRTC TIMING CHARACTERISTICS (Reference Figures 5 and 61
Characteristic Symbol Min Max Unit
M,nimum Clock Pulse Width, Low PWCL 160 - ns
Minimum Clock Pulse Width, High PWCH 200 - ns
Clock Frequency fe - 25 MHz
Rise and Fall Time for Clock Input t er , tcf - 20 ns
Memory Address Delay Time tMAD - 160 ns
Raster Address Delay Time tRAD - 160 ns
Display Timing Delay Time tDTO - 300 ns
HOrizontal Sync Delay Time tHSD - 300 ns
Vertical Sync Delay Time tVSD - 300 ns
Cursor Display Timing Delay Time tCDD - 300 ns
Light Pen Strobe Minimum Pulse Width PWLPH 100 - nS
Light Pen Strobe Disable Time tLPDl - 120 ns
tLPD2 - 0 ns

NOTE The light pen strobe must fall to low level before VS pulse rises

4·461
 MC6846eMC6846* 1eMC68A46e MC68A46* 1eMC68B46e MC68B46 * 1

CRTC INTERFACE SYSTEM DESCRIPTION

The CRT controller generates the signals necessary to in- and the Video timing (vertical sync - VS, hOrizontal sync -
terface a digital system to a raster scan CRT display. In this HS, and display enable - DE) Other functions Include an
type of display, an electron beam starts In the upper left Internal cursor register which generates a cursor output
hand corner, moves qUickly across the screen and returns. w~en Its contents compare to the current refreSh address A
This action IS called a horizontal scan After each hOrizontal light pen strobe Input Signal allows capture of the refresh ad-
scan the beam is Incrementally moved down In the vertical dress In an Internal IIqht Den reqlster.
direction until It has reached the bottom. At this pOint one All timing In the CRTC IS derived from the ClK Input In
frame has been displayed, as the beam has made many alphanumenc terminals, thiS signal IS the character rate The
honzontal scans and one vertical scan. Video rate or "dot" clock IS externally diVided by high-speed
Two types of raster scanning are used In CRTs, Interlace logiC (TTll to generate the ClK Input. In alphanumeric ter-
and non-Interlace, shown In Figures 7 and B. Non-interlace minals, thiS slgna~ IS 'the charact~r rate The Video rate or
scanning consists of one field per frame. The scan lines In "dot" clock IS externally diVided by high-speed logiC (TTL) to
Figure 7 are shown as solid lines and the retrace patterns are generate the ClK slgnat The high-speed logiC must also
Indicated by the dotted lines. IncreaSing the number of generate the timing and control Signals necessary for the
frames per second will decrease the flicker. Ordinarily, BIther shift register, latch, and MUX control
a 50 or 60 frame per second refresh rate IS used to minimize The processor communicates With the CRTC through an
beating between the CRT and the power line frequency. ThiS B-blt data bus by reading or writing Into the 19 registers
prevents the displayed data from weaving. The refresh memory address IS multiplexed between the
Interlace scanning IS used In broadcast TV and on data processor and the CRTC. Data appears on a secondary lJus
monitors where high denSity or high resolution data must be separate from the processor's bus The secondary data bus
displayed. Two fields, or vertical scans are made down the concept In no way precludes uSing the refresh RAM for other
screen for each single picture or frame. The first field (even purposes It looks like any other RAM to the processor A

•
field I starts In the upper left hand corner; the second (odd number of approaches are pOSSible for solVing contentions
field) In the upper center. Both fields overlap as shown In for the refresh memory.
Figure B, thus InterlaCing the two fields Into a Single frame. 1 Processor always gets Priority (Generally, "hash" oc-
In order to display the characters on the CRT screen the curs as MPU and CRTC clocks are not synchrOnized.)
frames must be continually repeated. The data to be 2 Processor gets PriOrity access anytime, but can be
displayed IS stored In the refresh (screen) memory by the synchronized by an Interrupt to perform accesses only
M PU controlling the data processing system. The data IS dunng honzontal and vertical retrace times
usually wntten In ASCII code, so It cannot be directly
displayed as characters. A character generator ROM IS 3 Synchronize the processor with memory walt cycles
tYPically used to convert the ASCII codes Into the "dot" pat- (states)
tern for every character. 4 Synchronize the processor to the character rate as
The most common method of generating characters IS to shown In Figure 10 The M6800 processor family
create a matrix of dots "x" dots (columns) Wide and "y" dots works very well In thiS configuration as constant cycle
(rowsl high Each character IS created by selectively filling In lengths are present ThiS method proVides no
the dots As "x" and "y" get larger a more detailed character overhead for the processor as there IS never a conten-
may be created. Two common dot matrices are 5 x 7 and tion for a memory access. All accesses are
7 x 9 Many variations of these standards Will allow Chinese, transparent.
Japanese, or ArabiC letters Instead of English. Since The present version of the CRTC IS being upgraded to Im-
characters require some space between them, a character prove functionality. ThiS data sheet contains the information
block larger than the character IS typically used, as shown In deSCribing both the MC6845 (present CRTC) and the
Figure 9. The figure also shows the corresponding timing MC6845-tr1 (upgraded CRTC) Complete compatibility be-
and levels for a Video Signal that would generate the tween both versions IS maintained by programming aTI
characters. register bits, which are undefined/unused, In the MC6845
Refemng to Figure 2, the CRT controller generates the with zero's
refresh addresses (MAO-MA13I, row addresses (RA()"RA4),

FIGURE 7 - RASTER SCAN SYSTEM (NON-INTERLACEI

Vertical Scan Penod

Vertical Retrace Penod

_.1-_

HOrizontal Scan HOrizontal Retrace

Penod Penod

4-462
 FIGURE 8 - RASTER SCAN SYSTEM (INTERLACE)

- - - - Even Number Field IFlrstl

- - - - - Odd Number Field {Secondl

FIGURE 9 -

~
2 4
CHARACTER DISPLAY ON THE SCREEN AND VIDEO SIGNAL

One Character
Clock

6 8
•
Character
4
} Display

6
One Lme
14 Scan

},,,.,-
Lines 8

10

12

14

First Scan Line Ir~ ~ I II

Second Scan Line
Ir~ ~1
~ J1 ~ ~n

4-463
 FIGURE 10 - TRANSPARENT REFRESH MEMORY TABLE 1 - CRTC OPERATING MODE
CONFIGURATION TIMING USING M6800 FAMILY MPU
RESET LPSTB Operating Mode
0 0 Reset
0 1 Test Mode
1 0 Normal Mode
1 1 Normal Mode

The test mode configures the memory ad-

dresses as two Independent 7-blt counters to
minimize test time
I
I I
I I
~tCYc= nxtc or tc/m---';
I I

Where m, n are Integers, tc IS character penod

PIN DESCRIPTION

II
PROCESSOR INTERFACE Vertical Sync (VS) and Horizontal Sync (HSI - These
The CRTC Interfaces to a processor bus on the bidirec- TTL-compatible outputs are active high signals which drive
tIOnal data bus 1D0-071 USIJ1g CS, RS, E, and R/W for con- the monitor directly or are fed to the Video processing Cir-
trol signals cUitry to generate a composite Video signal The VS signal
determines the vertical position of the displayed text while
Data Bus (00-071 - The bidirectional data lines 100-071 the H S signal determines the hOrizontal posItIOn of the
dllow data transfers between the Internal CRTC register file displayed text
and the processor Data bus output drivers are hlgh-
Impedance state until the processor performs a CRTC read Display Enable (DE) - ThiS TTL-compatible output IS an
operation active high signal which ,nd,cates the CRTC IS proViding ad-
dreSSing In the active display arpa
Enable (E) - The Enable signal IS a high-Impedance
TTL! MOS compatible Input which enables the data bus In- REFRESH MEMORY ICHARACTER GENERATOR
put/output buffers and clocks data to and from the CRTC ADDRESSING
ThiS signal IS usually derived from the processor clock The The CRTC proVides memory addresses IMAO-MA 131 to
hlgh-to-Iow transition IS the active edge scan the refresh RAM Row addresses IRAO-RA4) are also
proVided for use With character generator ROMs In a
Chip Select (CS) - The CS line IS B high-Impedance graphiCS system, both the memory addresses and the row
TTL/MOS compatible Input which selec!s the CRTC, when addresses would be used to scan the refresh RAM Both the
low, to read or write to the Internal register file ThiS signal memory addresses and the row addresses continue to run
should only be active when there IS a valid stable address be- dUring vertical retrace thus allOWing the CRTC to proVide the
Ing decoded from the processor refresh addresses reqUired to refresh dynamiC RAMs

Register Select (RS) - The RS line IS a high-Impedance Refresh Memory Addresses (MAO-MA 13) - These 14 out-
TTL!MOS compatible Input which selects either the address puts are used to refresh the CRT screen With pages of data
register IRS = "0") or one of the data register IRS = "1") or located Within a 16K block of refresh memory These outputs
the Internal register file are capable of driVing one standard TTL load and 30 pF

Read/Write (R/W) - The R/W line IS a high-Impedance Row Addresses (RAO-RA4) - These five outputs from the
TTL/MOS compatible Input which determines whether the Internal row address counter are used to address the
Internal register file gets written or read A write IS defined as character generator ROM These outputs are capable of driV-
a low level Ing one standard TTL load and 30 pF

CRT CONTROL
The CRTC provides hOrizontal sync IHS), vertical sync OTHER PINS
IVS), and display enable IDE) signals Cursor - ThiS TTL-compatible output ,nd,cates a valid
cursor address to external Video processing logiC It IS an ac-
NOTE tive high signal
Care should be exercised when interfaCing to CRT
monitors, as many monitors claiming to be "TTL com- Clock (ClK) - The ClK IS a TTL/MOS-compatlble Input
patible" have transistor Input CirCUitS which reqUire used to synchronize all CRT functions except for the pro-
the CRTC or TTL deVices buffering signals from the cessor Interface An external dot counter IS used to derive
CRTClvideo CIrCUitS to exceed the maximum-rated thiS signal which IS usually the character rate In an
drive currents alphanumeric CRT The active transition IS hlgh-to-Iow

4-464
 Light Pen Strobe (LPSTB) - A low-to-hlgh transition on lei The control registers of the CRTC are not affected and
this high-Impedance TTUMOS-compatlble Input latches the remain unchanged
current Refresh Address In the light pen register The latch~ Functionality of RESET differs from that of other M6800
Ing of the refresh address IS Internally synchronized to the parts In the following functions
character clock IClK) la) The RESET Input and the lPSTB Input are encoded as
shown In Table 1
Vee. VSS These Inputs supply + 5 Vdc ± 5% to the
Ib) After RESET has gone low and IlPSTB~"O"), MAO-
CRTC.
MA 13 and RAO~RA4 Will be driven Iowan the failing
edge of ClK RESET must remain low for at least one
RESET - The RESET Input IS used to reset the CRTC A
cycle of the character clock IClK)
low level on the RESET Input forces the CRTC Into the
following state lei The CRTC resumes the display operation Immediately
after the release of RESET DE IS not active until after
la) All counters In the CRTC are cleared and the deVice
the first VS pulse occurs
stops the display operation
Ib) All the outputs are driven low

CRTC DESCRIPTION
(Figure 11 CRTC Block Diagram)

The CRTC consists of programmable hOrizontal and ver- register The contents of the light pen register are subse-
tical timing generators, programmable linear address quently read by the processor

•
register, programmable cursor logiC, light pen capture Internal CRTC registers are programmed by the processor
register, and control circuitry for Interface to a processor through the data bus, 00-07, and the control Signals -
bus Riw, CS, RS, and E
All CRTC timing IS derived from ClK, usually the output of
an external dot rate counter COinCidence I CO) CIrCUitS con-
tinuously compare counter contents to the contents of the
programmable register file, RO-R17 For hOrizontal timing REGISTER FILE DESCRIPTIONS
generation, compansons result In 1) hOrizontal sync pulse
IHSI of a frequency, POSition, and Width determined by the The nineteen registers of the CRTC may be accessed
registers, 2) hOrizontal display Signal of a frequency, position, through the data bus Only two memory locations are re-
and duration determined by the registers qUired as one location IS used as a pOinter to address one of
The hOrizontal counter produces H ciock which drives the the remaining eighteen registers These eighteen registers
scan line counter and vertical contlol The contents of the control hOrIZontal timing, vertical timing, Interlace operation,
Raster Counter are continuously compared to the maximum row address operation, and define the cursor, cursor ad-
scan line address register A COinCidence resets the raster dress, start address, and light pen register The register ad-
counter and ciocks the vertical counter dresses and sizes are shown In Table 2
Comparisons of vertical counter contents and vertical
registers result In 1) vertical sync pulse IVSI of a frequency, ADDRESS REGISTER
Width and position determined by the registers, 2) vertical The address register IS a 5-blt write-only register used as
display of a frequency and position determined by the an "lndlrect"or "pointer" register It contains the address of
registers one of the other eighteen registers When both RS and CS
The vertical control logiC has other functions are low, the address register IS selected When CS IS low and
1 Generate row selects, RAO-RA4, from the raster count RS IS high, the register pOinted to by the address register IS
for the corresponding Interlace or non-Interlace selected
modes
TIMING REGISTERS RO-RS
2 Extend the number of scan lines ,n the vertical total by Figure 12 shows the VISible display area of a typical CRT
the amount programmed In the vertical total adjust
mOnitor giving the pOint of reference for hOrizontal registers
register
as the left most displayed character position HOrizontal
The linear address generator IS driven by ClK and locates registers are programmed In character clock time Units With
the relative positions of characters In memory With their POSI- lespect to the reference as shown In Fll)ure 13 The pOint of
tions on the screen Fourteen lines, MAO~MA 13, are reference for the vertical registers IS the top character POSI-
available for addreSSing up to four pages of 4K characters, 8 tion displayed Vertical registers are programmed In
pages of 2K characters, etc. USing the start ~ddress register, scan line times With respect to the reference as shown In
hardware scrolling through 16K characters IS pOSSible The Figure 14
linear address generator repeates the same sequence of ad-
dresses for each scan line of a character row Horizontal Total Register (RO) - ThiS 8-blt wnte~only
The cursor logiC determines the cursor location, Size, and register determines the hOrizontal sync IHSI frequency by
blink rate on the screen All are programmable defining the H S period In character times It IS the total of the
The light pen strobe gOing high causes the current con- displayed characters plus the non-displayed character times
tents of the address counter to be latched In the light pen I retrace I min us one

4·465
 *
MC6845·MC6845 1·MC68A45. MC68A45 1.MC68B45.MC68B45 1 * *

FIGURE 11 - CRTC BLOCK DIAGRAM

Vee GND RiW cs RS E R"ES'Ei' 00-07

cLK-r------<r-t

DE

HS

Q~--------~-+4--~~~HS

• H
HH

~:::::::f::::~::::~>(:J~~:Jf-----------~+----+-~CURSDR

t+-------+- LPSTB

4·466
 TABLE 2 - CRTC INTERNAL REGISTER ASSIGNMENT
(Features of the MC6840-1 have 1 subscriptl

cs RS
4
Address Register
3 2 1 0 ,
Register
Register File
Program
Unit
Read Write
7 6 5
Number of Bits
4 3 2 1 0
X X X X X X - - - - ""-... ........... ""-... ""-...
1
0
0
0
1
X
0
X
0
X
0
X
X
0
X
0
AR
RO
Address Register
HOrizontal Total
-
Char
No
No
Yes
Yes
...........
~ '-.., "'" ."'-
...........
"'"
0 1 0 0 0 0 1 R1 Honzontal Displayed Char No Yes
0 1 0 0 0 1 0 R2 H Sync Position Char No Yes
0 1 0 0 0 1 1 R3 Sync Width - No Yes V1 V1 V1 VI H H H H
0 1 0 0 1 0 0 R4 Vertical Total Char Row No Yes ~
0 1 0 0 1 0 1 R5 V Total Adlust Scan Line No Yes ~ 1'-.., 1'-..,
0 1 0 0 1 1 0 R6 Vertical Displayed Char Row No Yes ~
0 1 0 0 1 1 1 R7 V Sync Position Char Row No Yes ~

'" '"
0 1 0 1 0 0 0 RS Interlace Mode and Skew Note 1 No Yes C1 C1 D1 Dl I I
0 1 0 1 0 0 1 R9 Max Scan Une Address Scan Lme No Yes ~ '-.., '-..,
0 1 0 1 0 1 0 RIO Cursor Start Scan Line No Yes ~ B P (Note 21
0 1 0 1 0 1 1 Rl1 Cursor End Scan Line No Yes f"-.... '-.., ~
0 1 0 1 1 0 0 R12 Start Address (HI - Yes Yes 0 0

•
0 1 0 1 1 0 1 R13 Start Address (Ll - Yes Yes
0 1 0 1 1 1 0 R14 Cursor (HI - Yes Yes 0 0
0 1 0 1 1 1 1 R15 Cursor (Ll - Yes Yes
0 1 1 0 0 0 0 R16 Light Pen (H I - Yes No 0 0
0 1 1 0 0 0 1 R17 Light Pen III - Yes No

NOTES
1 The skew control IS shown In Table 3 and Interlace IS shown In Table 4
2. Bit 5 of the Cursor Start Raster Register IS used for blink penod control, and Bit 6 IS used to select blink or non-bhnk

FIGURE 12 - ILLUSTRATION OF THE CRT SCREEN FORMAT

r l - - - - - - - - - N u m b e r of Honzontal Total Char (Nht + 1 1 - - - - - - - - - - - - .
1

iff' }" "

r-----Number of Honzontal Displayed Char ( N h d l - - - - - - .

A B C

;=
+
i
U
~
(/)
'> E
z ~ ::I
- ro ~
~ ~ (0
u 0 ~

Display Penod

Vertical Retrace Penod

Total Scan Line Adlust (Nadll-

Note 1 Timing values are descnbed In Table 8

4·467
 MC6846-MC6845* 1-MC68A45-MC68A45 * 1-MC68B45-MC68B45* 1

Horizontal Displayed Register (R1) - This 8-bIt write-only value programmed In the register IS one less than the number
register determines the number of displayed characters per of computed character-line times. When the programmed
line. Any 8-bIt number may be programmed as long as the value of thiS register IS Increased, the display position of the
contents of RO are greater than the contents of R1 CRT screen IS shifted up. When the programmed value IS
decreased the display position IS shifted down Any number
Horizontal Sync Position Register (R2) - This 8-bIt wrlte- equal to or less than the vertical total (R4) may be used
only register controls the HS position. The hOrizontal sync
posItIOn defines the hOrizontal sync delay (Front Porch I and Interlace Mode and Skew Register (RS) - The MC6845
the hOrizontal scan delay (Back Porch) When the program- only allows control of the Interlace modes as programmed by
med value of this register IS Increased, the display on the the low order two bits of thiS write-only register The
CRT screen IS shifted to the left. When the programmed MC6845-1 controls the Interlace modes and allows a pro-
value IS decreased the display IS shifted to the right Any grammable delay of zero-to-two character clock times for the
8-blt number may be programmed as long as the sum of the DE (display enable) and cursor outputs Table 3 deSCribes
contents of R1, R2, and R3 are less than the contents of RO operation of the cursor and DE skew bits Cursor skew IS
controlled by bits 6 and -7 of R8 while DE skew IS controlled
Sync Width Register (R3) - This 8-blt write-only register by bits 4 and 5. Table 4 shows the Interlace modes available
determines the width of the vertical sync (VS) pulse and the to the user These modes are selected uSing the two low
hOrizontal sync (HS) pulse for the MCB845* 1 CRTC The order bits of thiS 6-blt write-only register
vertical sync pulse width IS fixed at 16 scan-line times for the In the normal sync mode (non-Interlace) only one field IS
MCB845 and the upper four bits of thiS register are treated as available as shown In Figures 7 and 15a Each scan line IS
"don't cares." refreshed at the VS frequency (e g , 50 or 60 Hz).
The MCB845* 1 allows control of the VS pulse width for Two Interlace modes are available as shown In Figures 8,

•
1-to-16 scan-line times. Programming the upper four bits for 15b, and 15c The frame time IS diVided between even and
1-to-15 will select pulse widths from 1-to-15 scan-line times odd alternating fields The hOrizontal and vertical timing rela-
Programming the upper four bits as zeros will select a VS tIOnship (VS delayed by % scan line time) results In the
pulse width of 16 scan-line times, allOWing compatibility With displacement of scan lines In the odd field With respect to the
the MCB845. even field
For both the MCB845 and the MCB845* 1, the HS pulse In the Interlace sync mode the same Information IS painted
width may be programmed from 1-to-15 character clock In both fields as shown In Figure 15b. ThiS IS a useful mode
periods thus allOWing compatibility With the HS pulse width for filling In a character to enhance readability
speCifications of many different monitors If zero IS written In the Interlace sync and Video mode, shown In Figure 15c,
Into thiS register then no H S IS prOVided alternating lines of the character are displayed In the even
field and the odd field. ThiS elfectlVely doubles the given
Horizontal TIming Summary (Figure 13) - The difference bandWidth of the CRT mOnitor
between RO and R1 IS the hOrizontal blanking Interval ThiS Care must be taken when uSing either Interlace mode to
Interval In the hOrizontal scan period allows the beam to aVOid an apparent flicker effect ThiS flicker effect IS due to
return (retrace) to the left Side of the screen The retrace time the doubling of the refresh time for all scan lines Since each
IS determllled by the monitor's hOrizontal scan components field IS displayed alternately and may be minimized With pro-
Retrace time IS less than the hOrizontal blanking Interval A per mOnitor deSign (e g , longer persistence phosphors)
good rule of thumb IS to make the hOrizontal blanking about In addition, there are restrictions on the programming of
20% of the total hOrizontal scanning period for a CRT In In- the CRTC registers for Interlace operation
expensive TV receivers, the beam overscans the display
screen so that aging of parts does not result In underscan- For the MCB845
nlng. Because of thiS, the retrace time should be about y, a. The hOrizontal total register value, RO, must be
the hOrizontal scanning period The horizontal sync delay, odd (I.e, an even number of character times).
HS pulse Width, and hOrizontal scan delay are typically pro- b For Interlace sync and Video mode only, the
grammed With a 1'2 2 ratio maximum scan-line address, R9, must be odd
lie, an even number of scan lines},
Vertical Total Register (R4) and Vertical Total Adjust c For Interlace sync and Video mode only, the ver-
Register (RS) - The frequency of VS IS determined by both tical displayed register I R6) must be even The
R4 and R5 The calculated number of character line times IS progra-mmed number Nvd, must be % the ac-
usually an Integer plus a fraction to get exactly a 50 or 60 Hz tual number reqUired The even numbered scan
vertical refresh rate The Integer number of character line Iones are displayed In the even field and the odd
times minus one IS programmed In the 7-blt write-only ver- numbered scan lines are displayed In the odd
tical total register (R41 The fractIOn of character line times IS field
programmed In the 5-blt write-only vertical total adjust d For Interlace sync and Video mode only, the cur-
register (R5) as a number of scan-line times sor start register (R 10) and cursor end register
(R 11) must both be even or both odd depending
Vertical Displayed Register (RS) - ThiS 7-bIt write-only on which field the cursor IS to be displayed In
register speCifies the number of displayed character rows on 2 For the MCB845* l'
the CRT screen, and IS programmed In character row times a The hOrizontal total register value, RO, must be
Any number smaller than the contents of R4 may be pro- odd II e , an even number of character times)
grammed Into R6. b For the Interlace sync and Video mode only, the
vertical displayed register (R6) must be even.
Vertical Sync Position (R7) - ThiS 7-bIt write-only register The programmed number, Nvd, must be % the
controls the posItion of vertical sync With respect to the actual number requrred
reference It IS programmed In character row times The

4-468
 ~

TABLE 3 - CURSOR AND DE SKEW CONTROL

i
~

i....,..
Value Skew
00 No Character Skew
01 One Character Skew
10 Two Character Skew

-11-Not Available •
~

FIGURE 13 - CRTC HORIZONTAL TIMING

Honzontal TotailROi
r•~~------------------------------------tsl~INht+llxtc--------------------------------------------------:~I
I
~

~
Honzontal Display IA11Nhdxtc .,.. Honzontal Aetrace

,..~....
.;,.
en
CD

•
~

~
~
~

-TImIng IS shown for first displayed scan row only See Chart In Figure 16 for other rows The initial MA IS determined by the contents of Start ~
,..~
Address Aeglster, A12/A13 Timing IS shown for A121R13~O
Note 1 Timing values are descnbed In Table 8

....

II
 • 3:

~
3:
FIGURE 14 - CRTC VERTICAL TIMING

tF= (Nvt+ II x trc+ Nadl x tsl

i.
.....
RAO-RM
( I
I...
Field Time
Vertical Total (R41 + Verllcal Total Adlust (R51
-101( L.... ~I
:I •
IS Interlace
--Vertical Display = Nvd x trc(R61
.lrc _ • * __ , .. .. f"""'TSI.,..,
Verllcal Retrace
3:
Sync and
Video Mode I 0 (11 I '" I&! I ... 1- oTIT-i-~1 "1st j-Y- Nsl -, 0,1 - ~-i -".- i O(1T - - , . - NSl j...-Ol1l Tadl= Nadl x tsl 81
, ¥ '~FIZIZZZZfIZZZZZIZZzrIZZZZIZIZZfZZZZIZZZIZIZIZZrZZZIZIZIZIZZZlZf ~•
Odd Field I I I(Nsl-lll I,rNvd-llxNhd/(Nst-lll (N sl-ll, Address Continues to Increment (N SI-ll, Field AdlustTlme ,
MAO-MAI3" ~ ~

Character
lit Nht*i
1
~
I
Nht*1
~,
(Nvd- 11 x N~d+ I
1
Nht , I
I~
1
1
, IlL
~~I
I I
-
I_ 3:
Row I I I 0 ~ I
I Nvd 1 Nvsp '" 1, Nvsp ' Nvt Nvt + 1 81
I jOOI(-l63xtsl~
~
.
~ I I I Vertical
~ ~ I I I ~~ ~~~
.....
o
(Non-Interlacel
I
I I \I
~erllcal syn~
, Vertical Sync
Pulse (R313 ,
VSYNC I i i PoslllOn !A71 .. I .. .....
(Even Fleldl

VSYNC
(Odd Fleldl

Display
-Enable
I ,
I I I I
I"'"
I
I
iii"", I "
I I

~~~~~--~,~--~~----------~
.. I , ,
....
..
!§!1t1
2
,v-,J----.I. . .------------------i
r-....:=--.L.J"---... •
~.!§!2
.,....-.,....:~....._--------------;
...
,•
3:
81
3:
·Nht must be an odd number for both Interlace modes
"Inlllal MA IS determined by R12/R13 (Start Address Reglsterl, which IS zero In this timing example 81
"""Nsl must be an odd number for Interlace Sync and Video Mode

NOTES
1 Refer to Figure 8 - The Odd Field IS offset 10 honzontal scan time
2 Timing values are descnbed In Table 8
3 Vertical Sync Pulse Width may be programmed from 1 to 16 scan hne times for the MC6845* 1
.
&
.....
MC6845e MC6845 * 1-MC68A45e MC68A45 * 1-MC68B45eMC68B45* 1

TABLE 4 - INTERLACE MOOE REGISTER TABLE 5 - CURSOR START REGISTER

Bit 1 Bit 0 Mode Bit 6 Bit 5 Curso. Oisplay Mode

0 0 0 0 Non-Blink
Normal Sync Mode INon-lnterlace)
1 0 0 1 Cursor Non-Display
0 1 Interlace Sync Mode 1 0 Blink, 1/16 Field Rate
1 1 Interlace Sync and Video Mode 1 1 Blink, 1/32 Field Rate
Example of Cursor Display Mode

FIGURE 15 - INTERLACE CONTROL

Scan Line Address Scan Line Address Scan Line Address
0----------------
==1
0
- --0
0 0 o o
2 0 0
-1

-2
:=1&- 0 0 0 - =:
4

3 0 0
-- -- - -3
4 0 0 0 0 0
--1
0 0

•
---- -5 -- - - ---3
6 0 0 6
-6
4--------------
- - - --5
0 0 7-~-------_E~
- -e~ -e-7 6----------------
------/
Even Odd Even Odd
Field Field Field Field
la) Normal Sync Ib) Interlace Sync Ic) Interlace Sync and Video

Maximum Scan Line Address Register (R91 - ThiS 5-blt the CRTC after vertical blanking It consists of an 8-blt low
write-only r'lglster determines the number of scan lines per order (MAO-MA7I reglstpr and a 6-blt high order (MA8-
character row Including the spacing, thus, controlling opera- MA 13) register The start address register determines which
tion of the row address counter The programmed value IS a portion of the refresh RAM IS displayed on the CRT screen
maximum address and IS one less than the number of scan Hardware scrolling by character, line, or page may be ac-
lines complished by modifYing the contents of thiS register

CURSOR CONTROL
Light Pen Register (R16-H, R17-LI - ThiS 14-bIt read-only
Cursor Start Register (R101 and Cursor End Reigster
register pair captures the refresh address output by the
(R11 I - These registers allow a cursor of up to 32 scan lines
CRTC on the positive edge of a pulse Input to the LPSTB
In height to be placed on any scan line of the character block
Pin It consists of an 8-blt low order IMAO-MA7I register and
as shown In Figure 16 Rl0 IS a 7-bIt write-only register used
a 6-blt high order (MAB-MA13) register Since the light pen
to define the start scan line and the cursor blink rate Bits 5
pulse IS asynchronous With respect to refresh address timing
and 6 of the cursor start address register control the cursor
an Internal synchronizer IS deSigned Into the CRTC Due to
operation as shown In Table 5 Non-display, display, and two
delays (Figure 3),n thiS CirCUit, the value of R16 and R17 Will
blink modes (16 times or 32 times the field period) are
need to be corrected In software Figure 17 shows an inter-
available Rll IS a 5-blt write-only register which defines the
rupt driven approach although a polling routine could be us-
last scan line of the cursor
ed
When an external blink feature on characters IS reqUired, It
may be necessary to perform cursor blink externally so that
both blink rates are synchronl7ed Note that an Invertl non- CRTC INITIALIZATION
Invert cursor IS eaSily Implemented by programming the Registers RO-R 15 must be initialized after the system IS
CRTC for a blinking cursor and externally Inverting the Video powered up The processor Will normally load the CRTC
Signal with an exclUSive-OR gate register file from a firmware table The worksheet of Table 6
IS extremely useful In computing proper register values for
Cursor Register (R14-H, R15-LI - ThiS 14-blt read/Write the CRTC Table 7 shows the worksheet filled out for an
register pair IS programmed to posItion the cursor anywhere BO x 24 configuration uSing a 7 x 9 character generator and
In the refresh RAM area, thus, allOWing hardware paging and Figure 18 shows an M6800 program which could be used to
scrolling through memory Without loss of the Original cursor program the CRT controller The programmed values allow
posItion It consists of an 8-blt low order (MAO MA7) register use of either an MC6845 or MC6845* 1 CRTC
and a 6-blt high order (MA8-MA 13) register The CRTC registers Will have an Initial value at power up
When uSing a direct dnve monitor (sans honzontal
OTHER REGISTERS OSCillator) these initial values may result In out-of-tolerance
Start Address Register (R12-H, R13-LI - ThiS 14-blt operation CRTC programming should be done Immediately
write-only register pair controls the first address output by after power up espeCially In thiS type of system

4-471
 MC6845- MC6845 * 1-MC68A45-MC68A45 * 1-MC68B45-MC68B45 * 1

FIGURE 16 - CURSOR CONTROL

I I I .+

o-+-+-I-+-+-H-
- I
I

I
I

I
Off On

: . - Blink Penod =
16 or 32 Times
Field Period

O-+-+-H-+-+-+- 0-+++-+4-+-+-
l-+-+-I-+-+-H- 1-+-+-H-+-+-+-
2-++-1-1-+-++
3 -+-+-I-+-+-H-
4-+-+-I-+-+-H-
5 -+-+-I-+-+-H-
6-+-+-I-+-+-H-
7-+-+-+-I1-+-+-+-
8:-+-+-+-+-+-+-+-
2-+-H-+-H-I-
3-+-+-f-++-I-+-
4--1-+++4-+--4-
5 -+-+-H--+-+-+-
6-+-+-H--+-+-+-
7-+-+-H--+-+-+-
8-+-+-H--+-+-+-
1111
6 ++~-+-+-4-
7--1-+4-+-I-+--4-
8-+++-1-+++-
16:i~~e1~t
9 -+++-I-+++-
19:!~~~!t 10 -+-+-+-II-+++-
11-+-++-I-+++- 11-++H--+-+-+- 11 -+-+-+-II-+++-
Cursor Start Adr = 9 Cursor- Start Adr = 9 Cursor Start Adr = 1

•
Cursor End Adr = 9 Cursor End Adr = 10 Curs?r End Adr = 5

FIGURE 17 - INTERFACING OF LIGHT PEN

MPU CR1C

Light Pen

4-472
MC6845- MC6845* 1- MC68A45- MC68A45 * 1- MC68B45- MC68B45 * 1

FIGURE 18 - MC6800 PROGRAM FOR CRTC INITIALIZATION

PlIGE 001 CRI'CINIT .SA: a 1<K:6845 / MC6845-1 CRl'C initialization pro<Jram

00001 NAM MC6845

00002 TTL / MC6845-1 cr<rc initialization program
00003 OPT G,S,LLE=85 print FCB's, FDB's & XREF table
00004 **************************************************
00005 * Assign CI<rc addresses
00006 *
00007 9000 A CRTCAD F.QU $9000 Address Hegister
00008 9001 A CRTCRG EQU CHTCAD+l Data Register
00009 **************************************************
00010 * Initialization pr~Jram
00011 *
00012A 0000 ORG o a place to start
OOOl3A 0000 5F CLRB clear counter
00014A 0001 CE 1020 A LOX lICRTl'AB table pointer
00015A 0004 F7 9000 A CRTCI ~;TAB CH'l'CAD load address register

•
00016A 0007 A6 00 A LDM O,X get register value from table
00017A 0009 B7 9001 A STM CRI'CRG pro<Jram register
OOOlBA OOOC 08 INX increment counters
00019A 0000 5C INCB
00020A OOOE ClIO A CMPB $10 finished?
00021A 0010 26 F2 0004 FlNE CRrCl no: take branch
00022A 0012 3F SWI yes: call monitor
00023 **************************************************
00024 * Cl<'I'C register initialization table
00025 *
00026A 1020 ORG $1020 start of table
00027A 1020 65 A CRITAB FCB $65,$50 RO, Rl - H total & H displayed
A 1021 50 11.
00028A 1022 56 A FCB $56,$09 H2, R3 - IlS pas. & HS vli(lth
A 1023 09 A
00029.\ 1024 18 A FCB $18,$OA R4, R5 - V total & V total a(lj.
A 1025 OA A
00030A 1026 Hl A FCB $18,$18 R6, R7 - V "isplaye(l $ VS pas.
A 1027 18 A
0003111. 1028 00 A FCB SOO,$OFl H8, R9 - Interlace & Max scan line
A 1029 DB A
00032A 102A 00 A FCB $OO,$OB RlO,Rll - Cursor start & end
A 102B OB A
00033A 102C 0080 A FOB $0080 Rl2,Rl3 - Start Mdress
00034A 102E 0080 A FDB S0080 H14,Rl5 - Cursor Address
00035 END
TerEAL ERroRS 00000-00000

CRrCl 0004 CRrCAO 9000 CRI'CRG 9001 CRTTAB 1020

4-473
 II
I
3:

Display Format Worksheet

TABLE 6 - CRTC FORMAT WORKSHEET

CRTC Registers
i.....
Displayed Characters per Row Char Decimal Hex 3:
•
3
2 Displayed Character Rows per Screen
Character Matrix a Columns
Rows
Columns
RO Honzontal Total ILine 15-1)
i
~•
R1 Honzontal Displayed ILlne 1)
Rows Rows
R2 Honzontal Sync Posilion (Line 1 + Line 12)
4 Character Block a Columns Columns
R3 Honzontal Sync Width ILlne 13)
bRows Rows
R4 Vertical TotallLlne 9-1)
3:
5
6
Frame Refresh Rate
HOrizontal Oscillator Frequency
Hz
Hz
R5 Vertical Adlust ILine 9 Lines)
i
.~....•
~ R6 Verllcal Displayed ,I Line 2)
.;:.. 7 AClIVe Scan Lines ILlne 2 x Lme 4b) Lines
R7 Vertical Sync Posilion ILlne 2+ Line 101
....... 8 Total Scan Lines (Line 6- Line 5) Lines
~ R8 Interlace (00 Normal, 01 Interlace,
9 Total Rows Per Screen ILlne 8- Line 4b) _ _ Rows and _ _ Lmes 03 Interlace, and Video)
10 Vertical Sync Delay IChar Rows) Rows R9 Max Scan Line Add ILine 4b -1)
11 Vertical Sync Width (Scan Lines 116)) 16 Lines R10 Cursor Start
3:
12 Honzontal Sync Delay ICharacter Times) Char Times Rll Cu,"or End
i
~
13 Honzontal Sync Width (Character Times) Char Times R12, R13 Start Address IH and U
14 Honzontal Scan Delay ICharacter Times) Char Times R14, R15 Cursor (H and U
15 Total Character Times (Line 1 + 12+ 13+ 14) Char Times
16 Character Rate (Line 6x 15) Hz
3:
17 Dot Clock Rate (Line 4a x 16) Hz
i
.....
&
 3:

~
3:

TABLE 7 - WORKSHEET FOR 8Ox24 FORMAT

i.
.....
Display Format Worksheet

Displayed Characters per Row 80 Char

CRTC Registers

Decimal Hex 3:
•

I
2 Displayed Character Rows per Screen 24 Rows
101 65
3 Character Matnx a Columns Columns
AO HOrizontal Total (Line 15 minus 1) ---
Rl HOrizontal Displayed (Line 1) 80 -----2Q
Rows 9 Rows
R2 HOrizontal Sync Position ILlne 1 + Lme 121 86 __56
4 Character Block a Columns 9 Columns
9 __9
_ _1_1_ _ R3 Honzontal Sync Width I Line' 31
Rows Rows
R4 Vertical Total (Line 9 mmus 11 24 _ _1_8
3:

!.
Frame Refresh Rate 60 Hz

6 HOrizontal Oscillator Frequency 18,600 Hz R5 Vertical Adjust ILlne 9 Llnesl 10 ~

",. R6 Vertical Displayed IL,ne 2) 24 _ _1_8
7 Active Scan Lines (Line 2 x Line 4bl 264 Lines
~
.....
U1
8 Total Scan Lines I Line 6 - Line 5) 310 Lines R7 Vertical Sync Position (Line 2+ Line 10) 24 18
---
0
9 Total Rows Per Screen (Line 8 - Line 4bl 28 Rows and 2 Lines RS Interlace (00 Normal, 01 Interlace,
.....
10 Vertical Sync Delay IChar Rows)
16
Rows
03 Interlace, and Video)
R9 Max Scan Line Add ILlne 4b minus 1) 11 B
---
•
3:
11 Vertical Sync Width IScan lines 116 1) Lines

~OJ
R10 Cursor Slart 0 0
---
12 HOrizontal Sync Delay (Character Times) 6 Char Times
11 __B
Rll Cursor End
13 Honzonlal Sync Wldlh (Character Times) 9 Char Times
128 00
R12, R13 Start Address IH and LI ---
~
14 HOrizontal Scan Delay (Character Times) Char Times
t02
- - 80
-
15 Total Character Times (Line 1+12+13+14) Char Times
128
16 Character Rate (Line 6 times 15) 18972 M MHz
R14, R15 Cursor IH and LI 00
--- 3:
~OJ
80
17 Dot Clock Rate (Line 4a times 16) 17075 M MHz

..
~
.....

II
 MC6845·MC6845 * l·MC68A45.MC68A45 * 1.MC68B45.MC68B45 * 1

OPERATION OF THE CRTC

TIMING CHART OF THE CRT INTERFACE SIGNALS IS qUite simple as the refresh addresses continually run
Timing charts of CRT Interface signals are Illustrated In Note that the LPSTB Input may be used to support addi-
this section with the aid of programmed example of the tional system functions other than a light pen A dlgltal-to-
CRTC When values listed In Table 8 are programmed Into analog converter IDACI and comparator could be configured
CRTC control registers, the deVice provides the outputs as to use the refresh addresses as a reference to a DAC com-
shown In the timing diagrams (Figures 13, 14, 19, and 201 posed of a resistive adder network connected to a com-
The screen format of thiS exmaple IS shown In Figure 12 parator The output of the comparator would generate the
which III ustrates the relation between refresh memory ad- LPSTB Input SignifYing a match between the refresh address
dress (MAO-MA131, raster address (RAO-RA41, and the POSI- analog level and the unknown voltage
tion on the screen In thiS example, the start address IS The light pen strobe Input could also be used as a
assumed to be "0" character strobe to allow the CRTC refresh addresses to
decode a keyboard matnx Llebounclng would need to be
done In software
ADDITIONAL CRTC APPLICATIONS Both the VS and HS outputs may be used as a ,eal-tlme
The foremost system function which may be performed by clock Once programmed, the CRTC Will provide a stable
the CRTC controller IS the refreshing of dynamiC RAM ThiS reference frequency

TABLE 8 - VALUES PROGRAMMED INTO CRTC REGISTERS

•
Programmed
Reg. # Register Name Value
Value
RO H Total Nht+ I Nht
Rl H Displayed Nhd Nhd
R2 H Sync Position Nhsp Nhsp
R3 H Sync Width Nhsw Nhsw
R4 V Tota! Nvt + I Nvt
R5 V Scan Line Adjust Nadl Nadl
R6 V Displayed Nvd Nvd
R7 V Sync POSition N vsp N vsp
R8 Interlace Mode
R9 Max Scan Line Address Nsl Nsl
RIO Cursor Start I
Rll Cursor End 3
Rl2 Start Address (Hl a
Rl3 Start Address III a
Rl4 Cursor IHI a
. Rl5 Cursor III 2
Rl6 Light Pen I H I
Rl7 Light Pen {U

4·476
 3:

i
3:

i*
....&

FIGURE 19 - CURSOR TIMING •

3:

!
RAO-RA4' ~ f , f
I I I I

MAO-MA13'"
I Nhd
, f
INhd+1Nhd+21
I I
~ I Nhd+ I
I Nht I I
• ~I Nhd+ ~ Nhd •I Nhd+1INhd+2i'
• Nhd •INhd+lINghd+21
I I I Nht I I
w
I
ctn
I
*
I Nhd+ I
Nht I 3:
I : : : : I : : :I : : jl I

~
Character Row # j I :
I I I
I I I I I I I I I I
~
~ Character # I
II..
;.:;: I I
I
I I"..~ I I I
I ~ I
....... I Nht 0 I Nht 0 I Nht
.......
Cursor
I
r---1
I I
t---l
I I I
f-----i. ._____ *3:•
....&

("')
·Tlmlng IS shown for non-Interlace and Interlace sync modes ~
Example shown has cursor programmed as CD
~
Cursor Register:::: Nhd + 2
CUTsor Start:::: 1
Cursor End = 3
""The initial MA IS determined by the contents of Start Address RegIster, R12/R13 Timing IS shown for R12/R13=O 3:
Note 1 Timing values are described In Table 8
~CD
8;
*
....&

II
 • s::

~ ..§'"
FIGURE 20 - REFRESH MEMORY ADORESSING IMAO-MA13) STAGE CHART

HOrizontal Display HOrizontal Retrace (Non-Display)

~s::
~ ~
~I~ I
i*
.<= 0
Uo:

I 0 1, Jo Nhd- 1 ,
Nhd Jo Nht

o{ N: I
I
I
0
I
I Jo Nh~
I
1
I
Nhd •
I
I
I
Nht ......
• s::•
{N~
Nrd Nhq+ 1 2XN~d-l 2X~hd ~ Nhd+ Nht
I
I I I I I

•
I I
Nhd Nhd+ 1 Jo 2XNhd 1 2XNhd Nhd+ Nht

•
Is::
I 2XNhd 2XNhd+ l'
, 1 3XNhd
I
3XNhd
, ~ 2Nhd+ Nht
~ O I I I
I I I
~
c5
"iii
2{NS I
2XNhd 2XNhd+ 1 • 3XNhd 1 3XNhd ~ 2Nhd'+Nht

~
Iii
>
~
~
"""
00
1 1 1 1 1
NVd- 1{ °
I INvd-llxNhd
i
INvd-1) x Nhd+ 1

,i
• Nvdx Nhd+ 1
I
I
Nvd x Nhd
I
I • INvd -1 IxNhd+Nht
I *......•
Ns I INvd ;1 x Nhd INvd llxNhd+l
• Nvd x Nhd 1 Nvd x Nhd ~ INvd
I
llxNhd+Nht s::
NVd{ 0
I Nvd x Nhd
I
Nvd x Nhd+ 1
, • INvd+ II x Nhd-1
I ,
INvd+ II x Nhd

I
~ Nvd x N 1d + Nht
~aJ
I I I
>- NsI Nvd x Nhd Nvdx Nhd+ 1 ~ INvd+ II x Nhd-1 IN vt + II x Nhd • Nvd + Nhd + Nht

~
~'"
~o s::
z
1l
W
~ Nvt x Nhd
I
Nvtx Nhd+ 1
I
INvt + 11 x Nhd-1
i
INvt + II
, x Nhd Nvt x Nhd + Nht
I I
~
~
0: Nvt{ 0 I I I
"iii
Ns Nvt xNhd I IN vt + 1) x Nhd-1 IN vt + 11 x Nhd Nvt x Nhd + Nht '
i"
>
N vt + l { 0
Nad I
I INvt+ 1) x Nhd
I
I
IN vt + 11 x Nhd
INvt + 11: Nhd+ 1
I
IN vt + 11 x Nd+ 1
INvt+2IxNhd-l
i
IN vt +21 x Nhd-1
INvt+~1 x Nhd
I
INvt+ 21 x Nhd
IN v + llNhd+ Nht I
I
I
INvt + 1INhd + Nht
,

I
*......
-i
NOTE 1 The Initial MA IS determined by the contents of start address register, R12/R13 Timing IS shown for RI2/NI3=O Only Non-
Interlace and Interlace Sync Modes are shown
 *
MC6845e MC6846 1e MC68A46eMC68A45* 1eMC68B46eMC68B45* 1

OROERING INFORMATION

--=rTTJ j
MC68A45CP1
~=~a~:~grated CIfCUlt
Blanks= 10 MHz _
A=15MHz
B=20MHz
Device Designation
In M6800 Family
Temperature Range
Blank = 0°_ + 70°C
Replaces { C= _40°_ +B5°C
"*" for Package' _ _ _ _ _ _ _ _ _ _ _---'
MC6846*l P=Plastlc
S=Cerdlp
L=Ceramlc
Enhanced Version of CRTC _ _ _ _ _ _..J

BETTER PROGRAM

Better program processing IS available on ali types listed Add

II
suffix letters to part number

Levell add "5" Level 2 add "0" Level 3 add "OS"

Levell "S"=10Temp Cycles - 1-2510 150 oCI.

HI Temp testing at T A max
Level 2 "0" = 168 Hour Burn-In at 125°C
Level 3 "OS" = Combination of Levelland 2

4-479
 MC6846
® MOTOROLA
MC68A46
(1.0 MHz)

(1.5 MHz)

MOS
ROM - 1/0 - TIMER
(N-CHANNEL, SILICON-GATE,
The MC6846 combination chip provides the means, In conlunctlon DEPLETION LOAD)
with the MC68Q2, to develop a basIc 2-chlp microcomputer system. The
MC6846 consists of 2048 bytes of mask-programmable ROM, an 8-blt ROM-I/O- TIMER
bidirectIOnal data port with control lines, and a 16-blt programmable
timer-counter.
ThiS device IS capable of interfaCing with the MC6802 (baSIC MC6800,
clock, and 128 bytes of RAM) as well as the entire M6800 family If
desired. No external logic IS reqUired to Interface with most peripheral . LSUFFIX
devices. CERAMIC PACKAGE
.••• ' - CASE 715
• 2048 8-Blt Bytes of Mask-Programmable ROM
• 8-Blt BidirectIOnal Data Port for Parallel Interface plus Two Control

~'"
Lines
• Programmable Interval Timer-Counter Functions SSUFFIX
• Programmable I/O Peripheral Data, Control, and Direction Registers , ,." • , CERDIP PACKAGE
, CASE 734
• Compat!ble with the Complete M6800 Microcomputer Product

• ~ .,,-
Famllv
• TTL-Compatible Data and Peripheral Lines
• Single 5-Volt Power Supply • ).' P SUFFIX
, ' -•' • PLASTIC PACKAGE
CASE 711

FIGURE 2 - PIN ASSIGNMENTS

FIGURE 1 - MC6846 BLOCK DIAGRAM

VSS A8
A7 A9
A6 Al0
DO
D1 A5 RESET
D2
D3 A4 IRQ
D4
D5 eso 6 ep2
D6
D7 R/IN epl
DO 8 AO
D1 Al
02 10 A2
D3 11 A3
D4 12 Vee
D5 13 P7
D6 14 P6
D7 15 P5
eSI 16 P4
PPO
PP1 C'fG 17 P3
PP2
2048 PP3 eTC 18 P2
Byte PP4
ROM CTa 19 Pl
PP5
PP6 E 20 PO
PP7
• Mask Programmable

4-480
MC6846- MC68A46

MAXIMUM RATINGS
Rating Symbol Value Unit
This deVice contains circuitry to protect the
Supply Voltage Vcc -03to+70 V Inputs against damage due to high static
Input Voltage V ,n -03to+70 V voltages or electnc fields, however, It IS ad-
Operating Temperature Range TA TL to TH 'C vised that normal precautions be taken to
M C6846, M C68A46 o
to + 70 avoid application of any voltage higher than
M C6846C, M C68A46C -40 to +85 maximum rated voltages to this hlgh-
Storage Temperature Range T 5tg -55to +150 °c Impedance Circuit Reliability of operation IS
enhanced If unused Inputs are tied to an ap-
propnate logiC voltage level (e 9 , either V SS
THERMAL CHARACTERISTICS
or VCC)
Characteristic Symbol Value Unit
Thermal Resistance
Ceramic 50
8JA 'C/W
Plastic 100
Cerdlp 60

POWER CONSIDERATIONS

The average chip-Junction temperature, T j, In 'c can be obtained from

Tj=TA+(PO·8jA) (1)
Where"

II
T A-Ambient Temperature, °c
8jA- Package Thermal ReSistance, junctlon-to-Amblent, °C/W
PO-PINT+ PPORT
PINT-ICC x VCC, Watts - Chip Internal Power
PPORT-Port Power Oissipatlon, Watts - User Oetermlned
For most applications PPORT<C PINT and can be neglected PPORT may become Significant If the deVice IS configured to
drive Oarllngton bases or sink LEO loads
An approximate relationship between Po and T j Ilf PPORT IS neglected) IS
PO=K-ITj+273°C) (2)
SolVing equatIOns 1 and 2 for K gives
K = PO.IT A + 273°C) + 8jA·P 0 2 (3)
Where K IS a constant pertaining to the particular part K can be determined from equation 3 by measuring Po lat eqUilibrium)
for a known T A. USing this value of K the values of Po and T j can be obtained by solVing equations (1) and (2) Iteratively for any
value of T A

FIGURE 3 - BUS TIMING TEST LOADS

Load A Load B
1D0-07, CTO, CP2, PPO-PP7) IIRQ Only)

VCC VCC

3 kO
Test POint
Test POint
MM06150
C or Equlv

MM07000 100 pF

I
or Equlv

C= 130 pF for 00-07

= 30 pF for CTO, CP2, PPO-PP7
R = 11 7 kll for 00-07
= 24 kll for CTO, CP2, PPO-PP7

4·481
 MC6846·MC68A46

ELECTRICAL CHARACTERISTICS (Vee= 50 V L 5% Vss = 0 T A = 0 to 70"e unless otherwise noted I

Characteristic Symbol Min Typ I Max Unit
Input High Voltage All Inputs VIH VSS + 20 - VCC V
Input Low Voltage All Inputs VIL VSS - 03 - VSS+OS V
Clock Overshoot/ Undershoot Input High Level VCC - 05 - VCC +05
Vas V
Input Low Level VSS -0 5 - VSS +05
Input Leakage Current R/W, ii"ESEi, CSO, CS 1
lin - 10 25 ~A
(V In =Ot05 25 VI CP1, CTG, CTc, E, AO-Al0
Three-State (Off Statellnput Current 00-07
'TS' - 20 10 ~A
(V,n=O 4 to 24 VI PPO-PP7, CP2
Output High Voltage
II Load = -205~AI 00-07 VOH VSS + 2 4 - - V
II Load = -2oo~AI Other Outputs VSS + 2 4 - --
Output Low Voltage
(ILoad = 1 6 mAl 00-07 VOL - - VSS+04 V
((Load = 32 mAl Other Outputs - - VSS + 0 4
Output High Current (Sourclngl
(VOH=2 4 VI 00-07 - 205 - -
~A
Other Outputs 10H -200 - - ~A
(Va = 1 5 V, the current for driving other than TTL,
e 9 , Darlington Basel CP2, PPO-PP7 -10 - -10 mA

•
Output Low Current (Sinking)
(VOL=04VI 00-07 10L 16 - - mA
Other Outputs 32 - -

Output Leakage Current (Ofl Statel IRQ

ILOH - - 10 ~A
(VOH=24VI
Internal Power DISSipation (Measured at T A:::: QOC) P,NT - - 1000 mW
Capacitance
IV In =0,TA=25"C,f=10MHzl 00-07 - - 20
PPO-PP7, CP2 C,n - - 125 pF
AO-A1O, R/Vii, RESET, CSO, CS1, CP1, eTC, CTG - - 10
IRQ - - 75
- - 50
PPO-PP7, C2, CTO Cout pF
- 10
Frequency of Operation MC6B46 01 - 10
I MHz
MC68A46 01 - 15
Clock Timing
Enable Cycle Time tcycE 10 - -
~s

Reset Low Time tRL 2 - - ~s

Interrupt Release tlR - - 16 ~s

1/0 TIMING - Peripheral 1/0 Lines

Characteristic Symbol Min Max Unit

Peripheral Data Setup tpDSU 200 - ns

Rise and Fall Times CP1, CP2 tpr, tpi - 10 ~s

Delay Time E to CP2 Fall tCP2 - 10 ~s

Delay Time I/O Data CP2 Fall toc 20 - ns

Delay Time E to CP2 Rise tRSl - 10 ~s

Delay Time CPl to CP2 Rise tRS2 - 20 ~s

Peripheral Data Delay tpDW - 10 ~s

Penpheral Data Setup Time for Latch tpoSU 100 - ns

Peripheral Data Hold Time for Latch tpDH 15 - ns

1/0 TIMING - Timer-Counter Lines

Input Rise and Fall Time CTCandCTG tCR, tCF - 100 ns
Input Pulse Width High (Asynchronous Model tpWH tcycE + 250 - ns
Input Pulse Width Low (Asynchronous Model tpWL tcycE + 250 - ns
Input Setup Time (Synchronous Model tsu 200 - ns
Input Hold Time (Synchronous Mode) thd 50 - ns
Output Delay tCTa - 10 ~s

4·482
MC6846·MC68A46

BUS TIMING CHARACTERISTICS ISee Notes 1 and 21

ldent MC6B46 MC68A46
Characteristic Symbol Unit
Number Min Max Min Max
1 Cycle Time tCYC 10 10 067 10 ,.s
2 Pulse Width. E Low PWEL 430 9600 280 9500 ns
3 Pulse Width. E High PWEH 450 9600 280 9500 ns
4 Clock Rise and Fall Time t.tt - 25 - 25 ns
9 Address Hold Time tAH 10 - 10 - ns
13 Address Setup Time Before E tAS 80 - 80 - ns
14 Chip Select Setup Time Before E tcs 80 - 60 - ns
15 Chip Select Hold Time tCH 10 - 10 - ns
18 Read Data Hold Time tDHR 20 100 20 100 ns
21 Write Data Hold Time tDHW 10 - 10 - ns
30 Output Data Delay Time tDDR - 290 - 180 ns
31 Input Data Setup Time tDSW 165 - 80 - ns

NOTES

II
1 Voltage levels shown are VLSO 4 V. VH",2 4 V. unless otherwise specified
2 Measurement POints shown are a 8 V and 2 0 V unless otherwIse specified

FIGURE 4 - BUS TIMING

~-------<D--------~

R/VV.Address-----r~~~JC~~~~~7\7\.~~aF----_rt_--------------------------·------t_rt~~
INon·Muxedl

Read Data MPU Read Data Non-Muxed

Non.Muxed ____ -+__-J~--------------------~--~--~--~~------------~~::~~ ________~4_--~

Write Data _____

Non-Muxed
L__t---------------------"M-"p-"U:...W.;.,:...r-"'te~D.:.at-"a-N-o:...n---M-"u-xe.:.d:..---------1~::=g
l<--------"''--------,=-l----'f

4-483
 MC6846-MC68A46

FIGURE 5 - PERIPHERAL PORT LATCH FIGURE 6 - PERIPHERAL DATA AND CP2 DELAY
SETUP AND HOLD TIME (Control Mode PCR5= 1, PCR4=0, PCR3= 1)

r--
PPO-PP7

tpsu
> C tpDH
Enable \
tpDW~
r-- lCP2 -
~

PPO-PP7
CP1
'} X
~lDC-- I-- lRS1-

r-
CP2'
I
·CP2 goes low as the result of positive transition of the second E pulse

FIGURE 7- IRQ RELEASE TIME FIGURE 8 - PERIPHERAL PORT SETUP TIME

I Enable
[\ PPO-PP7

?j
r
tlRi ftPDSU

Fa Enable \
FIGURE 9 - CP2 DELAY TIME FIGURE 10 - INPUT PULSE WIDTHS
(PCR5= 1, PCR4=0, PCR3=0)

Enable

tPr, tpi
CPl ---4----------~ CTC or
CTG

CP2~
~jr-~
FIGURE 11 - INPUT SETUP AND HOLD TIMES' FIGURE 12 - OUTPUT DELAY

Enable It / \
;;~=4 ~'K-- t
Enable
---1

CTO ____________t_C_TO
___

-ThiS mode IS valid only for synchronous operation

NOTE Timing measurements are referenced to and from a low voltage of 0 8 volts and a high voltag€ of 20 volts unless otherWise noted

4-484
MC6846- MC68A46

FIGURE 13 - TYPICAL MICROCOMPUTER

VCC VCC VCC VCC

MC6846 IRQ
MR
VMA
CSO VMA
Clock
RE
R/W R/W
MC6802
Parallel 1/6 MPU
00-07
EXtal
0

•
AO-A15 AO-A15 Xtal

Figure 13 IS a block diagram of a typical cost-effeCtive microcomputer The MPU IS the center of the microcomputer system and IS shown In a
minimum system Interfacing with a ROM combination chip It IS not Intended that this system be limited to this function but that It be expand-
able with other parts In the M6800 Microcomputer Family

GENERAL DESCRIPTION

The MC6846 combination chip may be partitioned Into The timer/counter control register allows control of the In-
three functional operating sections read-only memory, terrupt enable, output enable, selection of an Internal or ex-
timer-counter functions, and a parallel 1/0 port ternal clock source, a dlvlde-by-8 prescaler, and operating
mode. Input pin CTC (counter-timer clock) Will accept an
REA~-ONLY MEMORY (ROM) asynchronous clock pulse to decrement the Internal register
The mask-programmable ROM section IS Similar to other for the counter-timer. If the dlvlde-by-8 prescaler IS used, the
ROM products of the M6800 family The ROM IS organized maximum clock rate can be foUl times the master clock fre-
In a 2048 by 8-blt array to provide read-only storage for a quency Gate Input (CTG) accepts an asynchronous TTL-
minimum microcomputer system. Two mask-programmable compatible signal which may be used as a trigger or gating
chip selects are available for user definition function to the counter-timer. A counter-timer output (CTO)
Address Inputs AO-A 10 allow any of the 2048 bytes of IS also available and IS under software control being depen-
ROM to be uniquely addressed. Bidirectional data lines dent on the timer control register, the gate Input, and the
1000D7) allow the transfer of data between the MPU and the clock source
MC6846
PARALLEL I/O PORT
TIMER-COUNTER FUNCilONS The parallel bidirectional 1/0 port has functional opera-
Under software control this 16-blt binary counter may be tional characteristics Similar to the B port on the MC6821
programmed to count events, measure frequencies, time In- PIA. ThiS Includes eight bidirectional data lines and two
tervals, or Similar tasks. Internal registers associated with the handshake control Signals The control and operation of
I/O functions may be selected with AD, A1, and A2. It may these lines are completely software programmable.
also be used for square wave generation, single pulses of The Interrupt Input (CP1) Will set the Interrupt flag CSRl
controlled duration, and gated signals. Interrupts may be of the composite status register The peripheral control
generated from a number of conditions selectable by soft- (CP2) may be programmed to act as an Interrupt Input (set
ware programming CSR2) or as a peripheral control output

4·485
 MC6846e MC68A46

SIGNAL DESCRIPTION

BUS INTERFACE PERIPHERAL DATA (PO-P7)

The MC6846 interfaces to the M6800 Bus via an 8-blt The peripheral data lines can be ,nd,v,dually programmed
bidirectional data bus, two Chip Select lines, a Read/Write as either Inputs or outputs via the Data Direction Register
line, and eleven address lines. These signals, in conjunction When programmed as outputs, these lines Will drive two
with the M6800 VMA output, permit the MPU to control the standard TTL loads 13.2 mA). They are also capable of sour-
MC6846. cing up to 1.0 mA at 1.5 V ILoglc "1" output I
When programmed as Inputs, the output drivers
BIDIRECTIONAL DATA BUS (00-07) assOCiated With these lines enter a three-state Ihlgh Im-
The bidirectional data hnes (DO-D7) allow the transfer of pedance) mode. Since there IS no Internal pullup for these
data between the MPU and the MC6846. The data bus out- hnes, they represent a maximum 10 /LA load to the circuitry
put drivers are three-state devices which remain In the hlgh- driVing them - regardless of logiC state
Impedance 10ff) state except when the MPU performs an A logiC zero at the RESET Input forces the peripheral data
MC6846 register or ROM read IR/W = 1 and I/O Registers lines to the Input configuration by clearing the Data Direc-
or ROM selected). tion Register. ThiS allows the system deSigner to preclude
the pOSSibility of haVing a peripheral data output connected
CHIP SELECT (CSa, CS1) to an external driver output dUring power-up sequence
The CSO and CS 1 Inputs are used to select the ROM or

•
I/O timer of the MC6846. They are mask programmed to be INTERRUPT INPUT (CP1)
active high or active low as chosen by the user. Peripheral Input line CPl IS an Input-only that sets the In-
terrupt Flags of the Composite Status register The actIVe
ADDRESS INPUTS (AO-A10) transition for thiS Signal IS programmed by the peripheral
The Address Inputs allow any of the 2048 bytes of ROM to control register for the .parallel port CPl may also act as a
be uniquely selected when the Circuit IS operating In the strobe for the peripheral data register when It IS used as an
ROM mode. In the I/O-Timer mode, address Inputs AO, Al, Input latch Details for programming CPl are In the section
and A2 select the proper I/O Register, while A3 through on the parallel peripheral port
Al0 (together with CSO and CSll can be used as additional
qualifiers In the I/O Select Circuitry. ISee the section on 1/0- PERIPHERAL CONTROL (CP2)
Timer Select for additional details I Peripheral Control line CP2 may be programmed to act as
an Interrupt Input or Peripheral Control output As an Input,
RESET thiS line has high Impedance and IS compatible With standard
The active low state of the RESET Input IS used to Inltlahze TTL voltage levels As an output, It IS also TTL compatible
all register bits In the I/O section of the deVice to their proper and may be used as a source of 1 mA at 1 5 V to directly
values ISee the section on InitialIZation for reset conditions drive the base of a Darlington transistor SWitch ThiS line IS
for timer and peripheral registers I programmed by the Peripheral Control Register

ENABLE (EI COUNTER TIMER OUTPUT (CTO)

ThiS signal synchronIZes data transfer between the M PU The Counter Timer Output IS software programmable by
and the MC6846 It also performs an eqUivalent synchroniza- selected bits In the timer/counter control register The mode
tion function on the external clock, reset, and gate Inputs of of operation IS dependent on the Timer control register, the
the MC6846 Timer section gate Input, and the clock source The output IS TTL com-
patible
READ/WRITE (R/WI
ThiS signal IS generated by the MPU and IS used to control EXTERNAL CLOCK INPUT (CTCI
the direction of data transfer on the bidirectional data pins. Input pin CTC Will accept asynchronous TTL voltage
A low level on the R/W Input enables the MC6846 Input buf- Signals to be used as a clock to decrement the Timer. The
fers and data IS transferred to the circul! dUring the E pulse high and low levels of the external clock must be stable for at
when the part has been selected A high level on the R/W least one system clock period plus the sum of the setup and
Input enables the output buffers and data IS transferred to hold times for the Inputs The asynchronous clock rate can
the MPU dUring E when the part IS selected. vary from dc to the limit Imposed by E setup, and hold times
The external clock Input IS clocked In by Enable lEI pulses
INTERRUPT REQUEST (IRQ) Three E periods are used to synchrOnize and process the ex-
The active low IRQ output acts to Interrupt the MPU ternal clock The fourth E pulse decrements the Internal
through logiC Included on the MC6846. ThiS output utilIZes counter ThiS does not affect the Input frequency, It merely
an open-drain configuration and permits other Interrupt re- creates a delay between a clock Input tranSition and Internal
quest outputs from other CirCUitS to be connected In a wlre- recognition of that transition by the MC6846 All references
OR configuration to CTC Inputs In thiS document relate to Internal recognition

4·486
MC6846- MC68A46

of the input transition. Note that a clock transition which GATE INPUTS (CTGI
does not meet setup and hold time specifications may re- The Input pin CTG accepts an asynchronous TTL-
quire an additional E pulse for recognition. compatible signal which IS used as a tngger or a clock gating
When observing recurring events, a lack of synchroniza- function to the Timer The gating Input IS clocked Into the
tion will result In either "System Jitter" or "Input litter" being MC6846 by the E signal In the same manner as the previously
observed on the output of the M C6846 when uSing an asyn- discussed clock Inputs. That IS, CTG transition IS recognized
chronous clock and gate Input signal. "System Jitter" IS the on the fourth Enable pulse (provided setup and hold time re-
result of the Input signals being out of synchrOnization with qUirements are metl, and the high or low levels of the CTG
E permitting signals with marginal setup and hold time to be Input must be stable for at least one system clock penod plus
recognized by 8ilher the bit time nearest the Input transition the sum of setup and hold times. All references to CTG tran-
or subsequent bit time. "Input jitter" can be as great as the sition In thiS document relate to Internal recognition of the
time between the negative gOing transitions of the Input Input transition
signal plus the system Jitter If the first transition IS recognized The CTG Input of the timer directly affects the Internal
dunng one system cycle, and not recognized the next cycle 16-blt counter The operation of CTG IS therefore indepen-
or vice-versa. Refer to Figure 14. dent of the dlvlde-by-8 prescaler selection

FIGURE 14 - RECOGNITION OF CTC

Input Output

•
E
CTC Input

Jitter
Recog
Input I
Either ~ Or Here
Here

FUNCTIONAL SELECT CIRCUITRY

I/O-TIMER SELECT CIRCUITRY controlled by AO, A 1, and A2 (as shown In Table 11 proVided
CSO and CS 1 are user programmable Any of the four the I/O timer IS selected The combination status register IS
binary combinations of CSO and CS1 can be used to select Read-only, all other Registers are Read and Wnte
the ROM likeWise, any other combination can be used to INITIALIZATION
select the I/O-Timer. In addition, several address lines are When the RESET Input has accepted a low Signal, all
used as qualifiers for the I/O-Tlmer SpeCifically, A3= A4=- registers are Initialized to the reset state The data direction
A5= logical "0" A6 can be programmed to a "1", "0", or and penpheral data registers are cleared Th~heral
don't care A7 = A8 = A9 = A 10 = don't care or only one line Control Register IS cleared except for bit 7 (the RESET bltl
may be programmed to a logical "1" Figure 15 outlines In ThiS forces the parallel port to the Input mode With Inter-
diagrammatic form the available chip select options rupts disabled To remove the reset condition from the
parallel port, a "0" must be wntten Into the Peripheral Con-
INTERNAL ADDRESS trol Register bit 7 (PCR71
Seven I/O Register locations Within the MC6846 are ac- The counter latches are preset to their maximal count, the
ceSSible to the MPU data bus Selection of these registers IS Timer control register bits are reset to zero except for 81t a
(TCRO IS setl, the counter output IS cleared, and the counter
clock disabled. ThiS state forces the timer counter to remain
REGISTER SELECTED A2 Al AD In an Inactive state The combination status register IS
Combination Status Register 0 0 0 cleared of all Interrupt flags DUring timer initialization, the
Peripheral Control Register 0 D 1 reset bit (CCROI must be cleared
Data Direction Register D I 0
Peripheral Data Register 0 I I ROM
Combination Status Register 1 D 0 The Mask Programmable ROM section IS Similar In opera-
Timer Control Register 1 0 1
tion to other ROM products of the M6800 Mlcrocessor fami-
Timer MSB Register 1 1 0
ly The ROM IS organized as 2048 words of 8-blts to proVide
Timer LSB Register 1 1 1
ROM Address
read-only storage for a minimum microcomputer system
X X X
The ROM IS active when selected by the unique combination
TABLE 1 - INTERNAL REGISTER ADDRESSES of the chip select Inputs

4-487
 MC6846-MC68A46

FIGURE 15 - I/O-TIMER SELECT CIRCUITRY

CSI

I '"' I/O-TIMER
SELECT
cso

I ""-

Ala
A9 0-----0

r "
AS 0-----0

I
A7 0----0

--

AS

Ir
~

I
--

A5
A4
A3

ROM SELECT
The active levels of csa and CS1 for ROM and I/O select must be used for ROM or I/O select csa and CS1 are mask
are a user programmable option Either csa or CS 1 may be programmed simultaneously With the ROM pattern The
programmed active high or active low, but different codes ROM Select Circuitry IS shown In Figure 16

FIGURE 16 - ROM SELECT CIRCUITRY

CSI

ROM
Select

cso 0---,-----\

4·488
MC6846- MC68A46

TIMER OPERATION

The Timer may be programmed to operate In modes values It IS Important to note that an Internal reset (bit zero
which fit a wide variety of applications. The device IS fully of the Timer/Control Register Set) has no effect on the
bus compatible with the M6800 system, and IS accessed by counter latches
Load and Store operations from the MPU.
In a typical application, the timer will be loaded by storing
COUNTER INITIALIZATION
two bytes of data Into the counter latch ThiS data IS then
transferred Into the counter dUring a Counter InitialIZation Counter Initialization IS defined as the transfer of data
cycle. If enabled, the counter decrements on each subse- from the latches to the counter With attendant clearing of
quent clock cycle (which may be E or an external clock) until the IndiVidual Interrupt Flag associated With the counter
one of several predetermined conditions causes It to halt or Counter Initialization always occurs when a reset condition
recycle Thus, the timer IS programmable, cyclic In nature, (external RESET="O" or TCRO="l") 15 recognized It can
controllable by external Inputs or MPU program, and ac- also occur (dependent on The Timer Mode) With a Write
cessible to the MPU at any time. Timer Latches command or recognition of a negative transI-
tion of the Gate Input
COUNTER LATCH INITIALIZATION Counter recycling or relnltlallzatlon occurs when a clock
Input 15 recognized after the counter has reached an all-zero
The Timer consists of a 16-blt addressable counter and
state. In thiS case, data IS transferred from the Latches to the
two 8-blt addressable latches The function of the latches IS
Counter, but the Interrupt Flag IS unaffected
to store a binary eqUivalent of the deSIred count value minus
one Counter Initialization results In the transfer of the latch
TIMER CONTROL REGISTER

•
contents of the counter It should be noted that data transfer
to the counters IS always accomplished via the latches The Timer Control Register (see Table 2) In the MC6846 IS
Thus, the counter latches may be accurately described as a used to modify timer operation to SUit a variety of applica-
16-blt "counter Inltllization data" storage register tions The Timer Control Register has a unique address
In some modes of operation, the Initialization of the lat- space (AO="l", Al ="0", A2="1") and therefore may be
ches will cause Simultaneous counter initialization (, e , Im- written Into at any time The least Significant bit of the Con-
mediate transfer of the new latch data Into the counters) It trol Register IS used as an Internal reset bit. When thiS bit IS a
IS, therefore, necessary to Insure that all16 bits of the latch- logiC zero, all timers are allowed to operate In the modes
es are updated Simultaneously Since the MC6846 data bus prescribed by the remaining bits of the lImer control register
IS 8 bits wide, a temporary register (MSB Buffer Register) IS Writing "one" Into Timer Control Register BO (TCRO)
proVided for the Most Significant Byte of the deslr"d latch causes the counter to be preset With the contents of the
data. ThiS IS a "write-only" register selected via address lines counter latches, all counter clocks are disabled, and the
AO, A 1, and A2 Data IS transferred directly from the data timer output and Interrupt flag (Status Register) are reset
bus to the MSB Buffer when the chip IS selected, R/W IS The Counter Latch and Timer/Control Register are un-
low, and the timer MSB register IS selected (AO= "0", disturbed by an Internal Reset and may be written Into
Al=A2="1") regardless of the state of TCRO
The lower 8 bits of the counter latch can also be referred
to as a "write-only" register Data Bus Information will be Timer Control Register Bit 1 (TCR1) IS used to select the
transferred directly to the LSB of a counter latch when the clock source When TCR 1 = "0", the external clock Input
chip 15 selected, R/W IS low and the Timer LS8 Register IS CTC IS selected, and when TCRl = "1", the timer uses E
selected (AO=Al=A2="1") Data from the MSB Buffer Timer Control Register Bit 2 (TCR2) enables the dlvlde-
will automatically be transferred Into the Most Significant by-8 prescaler (TCR2= "1") In thiS mode, the clock fre-
Byte of the counter latches Simultaneously with the transfer quency IS diVided by eight before being applied to the
of the Data Bus information to the Least Significant Byte of counter When TCR2= "0" the system clock IS applied
the Counter Latch For brevity, the conditions for thiS opera- directly to the counter
tion will be referred to henceforth as a "Write Timer Latches
TCR3, 4, 5 select the Timer Operating Mode, and are
Command"
discussed In the next section
The MC6846 has been designed to allow transfer of two
bytes of data Into the counter latches from any source, pro- Timer Control Register Bit 6 (TCR6) IS used to mask or
vided the MSB IS transferred first In many applications, the enable the Timer Interrupt Request When TCR6 = "0", the
source of data will be an M6800 MPU It should therefore be Interrupt Flag IS masked from the timer When TCR6="1",
noted that the 16-blt store operations of the M6800 family the Interrupt Flag IS enabled Into Bit 7 of the Composite
microprocessors (STS and STX) transfer data In the order Status Register (Composite IRQ Bit), which appears on the
required by the MC6846 A Store Index Register instruction, IRQ output pin
for example, results In the MSB of the X register being Timer Control Register Bit 7 (TCR7) has a special function
transferred to the selected address, then the LS B of the X when the timer IS In the Cascaded Single Shot mode. (ThiS
register being written Into the next higher location. Thus, function IS explained In detail In the section deSCribing the
either the Index register or stack pOinter may be transferred mode) In all other modes, TCR7 merely acts as an output
directly Into a selected counter latch With a Single Instruc- enable bit If TCR7= "0", the Counter Timer Output (CTO)
tion IS forced low Writing a logiC one Into TCR7 enables CTO
A logic zero at the RESET Input also Initializes the counter For more Information on ItS operation, see the speCifiC mode
latches All latches Will assume maximum count (65,535) deSCription

4-489
 MC6846·MC68A46

TABLE 2 - FORMAT FOR TIMER/COUNTER CONTROL REGISTER (EI

CONTROL
REGISTER
BIT STATE BIT OEFINITION STATE DEFINITION
TCRO
,
0 Internal Reset Timer Enabled
Timer In Preset State
TCR'
,
0 Clock Source Timer uses External Clock (eTC)
Timer uses System Clock (EI
TCR2
,
0 ..!.. 8 Prescaler
Enabler
Clock
Clock
IS

IS
not Prescaled
prescaled by
.. 8 Counter
TCR3 X
TCR4 X Operating Mode See Table 3
TCRS X Selection
TCR6
,
0 Timer Interrupt
Enable
IRQ Masked from Timer
IRQ Enabled from Timer
TCR7 0 Timer Output Enable Counter Output (CTO) Set LOW

I
1 Counte~ Output Enabled

TIMER OPERATING MODES (TCR7 = "1"1, a square wave Will be generated at the Timer
The MC6846 has been designed to operate effectively In a Output CTO (see Table 4l.
wide variety of applications. This IS accomplished by uSing Either a Timer Reset (TCRO= "1" or External
three bits of the control register (TCR3, TCR4, and TCR51 to RESET = "0"1 condition or Internal recognition of a negative
define different operating modes of the Timer, outlined In tranSition of the CTG Input results In Counter Initialization. A
Table 3. Write Timer Latches command can be selected as a Counter
Initialization Signal by clearing TCR4
The diSCUSSion of the Continuous Mode has assumed the
CONTINUOUS OPERATING MODE (TCR3=O, TCR5=O) application requires an output Signal It should be noted the
The timer may be programmed to operate In a continuous Timer operates In the sarne manner with the output disabled
counting mode by wrltmg zeros Into bits 3 and 5 of the timer (TCR7 = "0") A Read Timer Counter command IS valid
control register Assummg that the timer output IS enabled regardless of the state of TCR7

TABLE 3 - OPERATING MODES

TCR3 TCR4 TCRS Timer Operating Mode Counter Initialization I nterrupt Flag Set
0 0 0 Continuous CTG.f+W+R T.O.
CTG.j. + R T.O.
0
,
0 I Cascaded Single Shot
CTG.j. + R T.O.
0
0 I ,
0 Continuous
Normal Single Shot CTG.j. + R T.O.
I 0 0 Frequency Comparison CTG.j. • I • (W + T 0.1 + R CTG.f Before T.O.
I
,
0 1 CTGi· 1+ R
CTG.j.· 1+ R
T.O Before CTG.f
CTGt Before T.O.
,
I
, 0
I
Pulse Width Comparison
T.O. Before CTGt

R = Reset Condition CTGt = Negative TranSition of Pin 17

W = Write Timer Latches CTGt = POsitive Transition of Pin 17
T.O. = Counter Time Out T= Interrupt Flag (CSROI = 0

4-490
MC6846-MC68A46

TABLE 4 - CONTINUOUS OPERATING MODES

CONTINUOUS MODE
(TCR3 = 0, TCR7 = I, TCR5 =01
CONTROL INITIALIZATION/OUTPUT WAVEFORMS
REGISTER

TCR2 TCR4 Counter Timer Output (2X)

Initialization I+iN + lIITI-+I+iN + l1ITI-+1 +iN + 11 (TI-+I
0 0 CfG~+W+R
II I
I
II [~~~
I
0 1 CfG~+R to T.O. TO. T.O.

eTG::: Negative Transition GATE Input. T = Period of Clock Input to Counter.

W= Write Timer Latches Command. to = Counter Initialization Cycle.
R = Timer Reset (TCRO = 1 or External RESET = 01 T.O.::: Counter Time Out (All Zero Condition).
N = 16 Bit Number in Counter Latch.

•
NORMAL SINGLE-SHOT TIMER MODE
(TCR3=O, TCR4=l, TCR5=1)
This mode is Identical to the Continuous Mode with two the setting of an IndiVidual Flag and re-Inltlallzatlon of the
exceptions. The first of these IS obvIous from the name - counter.
the output returns to a low-level after the Initial Time Out The second major difference between the Single-Shot
and remains low until another Counter Initialization cycle oc- and Continuous modes IS that the Internal counter enable IS
curs The output waveform ICTO) IS shown In Figure 17 not dependent on the CTG Input level remaining In the low
The Internal counting mechanism remains cyclical In the state for the Single-Shot mode ASide from these dif-
Single-Shot Mode Each Time Out of the counter results In ferences, the two modes are Identical

fiGURE 17 - SINGLE-SHOT MODES

to

f--- 1 -Ii------ N -J
4-~1 I~___ +_ _ _ _+
--+
CTO

l---'IN+1) IN+1) ----IN+1)-

(AI Normal Single-Shot Mode Output Waveform

I- IN+1)
'1-
IN+lI
·1· IN+1)
_I .. IN~
to TO TO TO TO
I

J
TRC7 = Output i I
After Timeout

I I
I I l' 0 I 1'1 I
IB) Cascaded Single-Shot Mode Output Waveform
1 =Wnte a "1" Into TCR-7
"Point at which an Interrupt may occur 0= Wnte a "0" Into TCR-7

NOTE All time Intervals shown above assume the Gate ICTG) and Clock (GTC) Signals are synchronized to E with the speCified setup and hold
time requirements

4·491
 MC6846e MC68A46

TABLE 5 - TIME INTERVAL MODES

TCRl= 1
TCR4 TCRS APPLICATION CONDITION FOR SETTING INDIVIDUAL INTERRUPT FLAG
0 0 Frequency Interrupt Generated If CTG Input Period (l/F)
Comparison is Less Than Counter Time Out (T.O,)
0 1 Frequency Interrupt Generated if CTG Input Period (l/F)
Comparison IS Greater Than Counter Time Out (T.OJ
1 0 Pulse Width Interrupt Generated If eTG Input "Down Time"
Comparison is less Than Counter Time Out (T.OJ
1 1 Pulse Width Interrupt Generated If CTG Input "Down Time"
Comparison IS Greater Than Counter Time Out (T.O.)

TIME INTERVAL MODES (TCR3 = 1) timer cycle before the output IS to change state), and 3) clear
The Time Interval Modes are provided for applications re- the Interrupt flag by reading the combination status register
qUlnng more flexibility of Interrupt generation and Counter followed by Read Timer MSB It IS also pOSSible, If deSired,
Initialization The Interrupt Flag IS set m these modes as a to change the length of the timer cycle by relnltlallzlng the
function of both Counter Time Out and translstlons of the timer latches. ThiS allows more fleXibility for obtaining
CTG input. Counter Initialization IS also affected by Interrupt deSired times

•
Flag status The output Signal IS not defmed In any of these
modes. Other features of the Time Interval Modes are out- FREQUENCY COMPARISON MODE
lined In Table 5. (TCR3; 1, TCR4; 0)
The timer Within the. MC6846 may be programmed to
CASCADED SINGlE·SHOT MODE compare the penod of a pulse (giVing the frequency after
(TCR3=O, TCR4=O, TCR5= 1) calculations) at the CTG Input With the time penod reqUired
ThiS mode IS Identical to the Single-shot mode with two for Counter Time Out A negative translstlon of the CTG in-
exceptions First. the output waveform does not return to a put enables the counter and starts a Counter Initialization cy-
low level and remain low after timeout Instead, the output cle - prOVided that other conditions, as noted In Table 6,
levels remains at ItS initialized level until It IS re-programmed are satisfied The counter decrements on each clock Signal
and changed by timeout The output level may be changed recognized dunng or after Couter Initialization until an Inter-
at any timeout or may have any number of tlmeouts between rupt IS generated, a Wnte Timer Latches command IS Issued,
changes. or a Timer Reset condition occurs It can be seen from
The second difference IS the method used to change the Table 6 that an Interrupt condition Will be generated If
output level Timer Control Register Bit 7 (TCR7) has a TCR5 = "0" and the penod of the pulse (Single pulse or
special function In thiS mode. The timer output (CTO) IS measured separately repetatlve pulses) at the CTG Input IS
equal to TCRl clocked by timeout At every timeout, the less than the Counter Time Out penod If TCR5= "1", an In-
contents of TCR7 IS clocked to and held at the CTO output terrupt IS generated If the reverse IS true
Thus, output pulses of length greater than one timer cycle Assume now With TCR5; "1" that a Counter Initialization
can be generated by cascading timer cycles and counting has occurred and that the CTG Input has returned low pnor
tlmeouts With a software program (See Figure 17 I to Counter Time Out Since there IS no IndiVidual Interrupt
An Interrupt IS generated at each timeout To cascade Flag generated, thiS automatically starts a new Counter In-
timer cycles, the MPU would need an Interrupt routine to 1) Itialization Cycle The process Will continue With frequency
count each timeout and determine when to change TCR7, 2) companson being performed on each CTG Input cycle until
wnte Into TCR7 the state corresponding to the next deSired the mode IS changed, or a cycle IS determined to be above
state of the output waveform (only necessary dunng the last the predetermined limit

TABLE 6 - FREQUENCY COMPARISON MODE

CRXl = 1, CRX4 = 0
Control Reg Counter Counter Enable Counter Enable Interrupt Flag
Bit S (CRXS) Initialization Fhp·Flop Set (CE) Flip·Flop Reset (CE) Set (II
0 GI·I· (CE+TO·CE)+R GI·W·R··, W+R+I GI Before TO

1 GI·I+R Gl \N·R f W+R+ I TO Before GI

I represents the interrupt for the timer.

4·492
MC6846- MC68A46

TABLE 7 - PULSE WIDTH COMPARISON MODE

CRX3 = 1, CRX4 = 1
Control Reg Counter Counter Enable Counter Enable Interrupt Flag
BIt 5 (CRX51 Inltlahzatlon Flop-Flop Set (CEI Flop-Flop Res.t (CEI Set !II

0 GI-I+R GI·W-R·I W+R+I+G Gt Before TO

1 GI-I+R GI W·R I W+R+I+G TO Before Gt

PULSE WIDTH COMPARISON MODE COMPOSITE STATUS REGISTER

(TCR3=1, TCR4=1) The Composite Status Register (CSR) IS a read-only
This mode IS similar to the Frequency Comparison Mode register which IS shared by the Timer and the Peripheral Data
except for the limiting factor being a positive, rather than Port of the MC6846. Three indiVidual Interrupt flags In the
negative, transition of the CTG Input With TCR5= "0", an register are set directly via the appropnate conditions In the
Individual Interrupt Flag will be generated If the zero level timer or peripheral port The composite Interrupt flag - and
pulse applied to the CTG input IS less than the time period re- the IRQ Output - respond to these individual Interrupts only
qUired for Counter Time Out With TCR5= "1", the Interrupt If corresponding enable bits are set In the appropriate Con-
IS generated when the reverse condition IS true trol Registers (See Figure 18 ) The sequence of assertion IS
As can be seen In Table 7, a positive transition of the CTG not detected Setting TCR6 while CSRO IS high Will cause
Input disables the counter With TCR5= "0", It IS ther€fore CSR7 to be set, for example.

I
pOSSible to directly obtain the Width of any pulse causing an The Composite Interrupt Flag (CSR7) IS clear only If all
Interrupt. enabled IndiVidual Interrupt Flags are clear The conditions
for cleanng CSRI and CSR2 are detailed In a later section
The Timer Interrupt Flag (CSRO) IS cleared under the follow-
Ing conditions
1) Timer Reset - Internal Reset Bit (TCRO) = "I" or Exter-
DIFFERENCES BETWEEN THE MC6840 AND THE nal RESET = "a'"
MC6846 TIMERS 2) Any Counter Initialization conditIOn
1) Control registers 1 and 3 are bUried (access through 3) A Wnte Timer Latches cornmand If Time Interval
control register 2 only) In the MC6840 timer In the MC6846, modes ITCR3= "I") are being used
all registers are directly accessable. 4) A Read Timer Counter command, prOVided thiS IS
2) The MC6840 has a dual 8-blt continuous mode for preceded by a Read Composite Status Register while CS RO
generating non-symmetrical waveforms The MC6846, in- IS set ThiS latter condition prevents missing an Interrupt Re-
stead, has a cascaded one shot mode which can accomplish quest generated after reading the Status Register and pnor
the same function, but also allows the user to generate to reading the counter
waveforms longer than one timeout The remaining bits of the Composite Status Register
3) Because of the different modes, there IS a difference In (CS R3-CS R6) are unused They return a logiC zero when
the control registers between the MC6840 and the MC6846 read

FIGURE 18 - COMPOSITE STATUS REGISTER AND ASSOCIATED LOGIC

4·493
 MC6846·MC68A46

1/0 OPERATION

PARALLEL PERIPHERAL PORT DATA DIRECTION REGISTER

The peripheral port of the MC6846 contains eight The MPU can write directly to thiS 8-blt register to con-
Peripheral Data lines (PO-P7), two Peripheral Control lines figure the Peripheral Data lines as either Inputs or outputs. A
(CPl and CP2), a Data Direction Register, a Peripheral Data particular bit Within the register (DDRN) IS used to control
Register, and a Penpheral Control Register. The port also the corresponding Peripheral Data line (PN) With
directly affects two bits (CS R1 and CS R2) of the Composite DDRN = "0", PN becomes an Input, If DDRN = "1", PN IS an
Status Register. output. As an example, writing Hex $OF Into the Data direc-
The Peripheral Port is similar to the "B" side of a PIA tion Register results In PO through P3 becoming outputs and
(MC6820 or MC6821) with the following exceptions: P4 through P7 being Inputs. Hex $55 In the Data direction
1) All registers are directly acceSSible in the MC6846. Data Register results in alternate outputs and Inputs at the parallel
Direction and Penpheral Data In the MC6820/6821 are port.
located at the same address, with Bit Two of the Control
Register used for register selection. PERIPHERAL DATA REGISTER
2) Peripheral Control Register Bit Two (PCR2) of the ThiS 8-blt register IS used for transferring data between the
MC6846 is used to select an optional input latch function. peripheral data port and the M PU. Any bit corresponding to
ThiS option IS not available with MC6820/6821 PIA's. an output line Will be used to drive the output buffer
3) Interrupt Flags are located In the MC6846 composite associated With that line. Data In these output bits IS normal-
status register rather than Bits 6 and 7 of the Control ly proVided by an MPU Write function. (Input bits - those
Register as used In the MC6820/MC6821. associated With Input lines - are unchanged by a Write

•
41 Interrupt Flags are cleared In the MC6820/6821 by Command. 1 Any Input bit Will reflect the state of the
reading data from the Penpheral Data Register. M C6846 In- associated Input line If the Input latch function IS deselected.
terrupt Flags are cleared by either reading or writing to the If the Control Reglster,ls programmed to proVide Input lat-
Peripheral Data Register - provided that this sequence IS ching, the Input bit Will retain the state at the time CP1 was
followed al Flag Set, b) Read Composite Status Register, cl actIVated until the Peripheral Data Register IS read by the
Read/Wnte Peripheral Data Register IS followed MPU.
5) Bit 6 of the MC6846 Peripheral Control Register IS not
used. Bit 7 (PCR7) IS an Internal Reset Bit not available on PERIPHERAL CONTROL REGISTER
the MC6820/6821. ThiS 8-blt register IS used to control the reset function as
61 The Peripheral Data lines (and C(?2) of the MC6846 well as for selection of optional functions of the two
feature Internal current limiting which allows them to directly peripheral control lines (CP1 and CP2). The Peripheral Con-
drive the base of Darlington NPN transistors. trol Register functions are outlined In Table 8.

TABLE B - PERIPHERAL CONTROL REGISTER FORMAT (EXPANDED)

PCR7
I PCR6
I PCRS
I PCR4 PCR3
I PCR2
I PCRI
I PCRD
J

I
0= CP2 Is INPUT
I
CP2 DIRECTION CONTROL

I
l 1
CPI INT. ENABLE
0= CPI INT MASKED

l
I = CP2 Is OUTPUT I = CPt INT. ENABLED

RESET (SET BY EXT. RESET = 0 OR WRITING

ONE INTO LOCATION, CLEARED BY
CPI ACTIVE EDGE SELECT
0= NEGATIVE WEDGE
I
WRITING ZERO TO THIS LOCATION I I = POSITIVE (t) EDGE
------------------
0= NORMAL OPERATION

l
CPI INPUT LATCH CONTROL
I = RESET CONDITION (CLEARS PER IPH 0= INPUT DATA NOT LATCHED
DATA & DATA DIRECTION REG + CSRI & CSR2) 1 = INPUT OATA LATCHED ON ACTIVE CPI

I CP2 Is INPUT (PCRS = 0)

I PCR4 PCR3 CP2 IS OUTPUT (PCR5 = 1)
I PCR4
I PCR3
I 0 0 INTERRUPT ACKNOWLEDGE

I II
0 I INPUT/OUTPUT ACKNOWLEDGE
CP2 INT. ENABLE PROGRAMMABLE OUTPUT
CP2 ACTIVE EDGE SELECT
0= NEGATIVE (~) EDGE 0= CP2 INT. MASKED I OOR I (CP2 REFLECTS DATA
I = POSITIVE (t) EDGE I = CP2 INT ENABLED WRITTEN INTO PCR3)

4·494
MC6846e MC68A46

PERIPHERAL PORT RESET (PCR7) that use of the Input latch function (which can be deselected
Bit 7 of the Peripheral Control Register (PCR7) may be us- by wntlng a zero into PCR2) has no effect on output data. It
ed to initialize the peripheral section of the MC6846. When also does not affect Interrupt function of CPl.
this bit is set high, the peripheral data register, the peripheral
CONTROL OF CP2 PERIPHERAL CONTROL LINE
data direction register, and the interrupt flags associated
with the peripheral port (CSRl and CSR2) are all cleared. CP2 may be used as an input by wnting a zero Into PCR5
Other bits In the penpheral control register are not affected In thiS configuration, CP2 becomes a dual of CPl In repard
by PCR7. to generation of Interrupts. An active transition (as selected
PCR7 is set by either a logic zero at the ExternalliESET In- by PCR4) causes Bit Two of the Composite Status Register
put or under program control by wntlng a "one" Into the to be set. PCR3 IS then used to select whether the CP2 tran-
location. In any case, PCR7 may be cleared only by wntlng a SItion IS to cause CSR7 to be set - and thereby cause IRO to
"zero" Into the location while RESET IS high The bit must go low. CP2 has no effect on the Input latch function of the
be cleared to activate the port. MC6846.
Wntlng a one Into PCR5 causes CP2 to function as an out-
CONTROL OF CPl PERIPHERAL CONTROL LINE put PCR4 then determines whether CP2 IS to be used In a
CPl may be used as an Interrupt request to the MC6846, handshake or programmable output mode With
PCR4= "1", CP2 Will merely reflect the data wntten Into

•
as a strobe to allow latching of Input data, or both In any
case, the Input can be programmed to be activated by either PCR3 Since thiS can readily be changed under program
a positive or negative transition of the signal. These ootlons control, thiS mode allows CP2 to be a programmable output
are selected via Control Register Bits PCRO, PCR1, and line In much the same manner as those lines selected as out-
PCR2. puts by the Data Direction Register
The handshaking mode (PCR5= "1", PCR4= "0") allows
Control Register Bit 0 (PCRO) IS used to enable the inter- CP2 to perform one of two functions as selected by PCR3
rupt transfer circuitry of the MC6846 Regardless of the state With PCR3= "1", CP2 Will go low on the first positive E tran-
of PCRO, an active transition of CPl causes the Composite sition. ThiS Input/Output Acknowledge signal IS released
Status Register Bit One (CSR1) to be set If PCRO= "1", thiS (returns high) on the next positive transition of E
Interrupt Will be reflected In the Composite Interrupt Flag
(CSR7), and thus at the IRO output. CSRl IS cleared by a In the Interrupt Acknowledge mode (PCR5="1",
PCR4= PCR3= "0"), CP2 IS set when CSRl IS set by an ac-
Penpheral Port Reset condition or by either reading or
wntlng to the penpheral data register after the Composite tive transition of CPl It IS released Igoes low) on the first
positive transition of E after CSRl has been cleared via an
Status Register was last read. ThiS precludes Inadvertent
MPU Read or Write to the Penpheral Data Register (Note
cleanng of Interrupt flags generated between the time the
that the preViously descnbed conditions for cleanng CSRl
Status Register IS read and the manipulation of penpheral
stili apply.)
data
Control Register Bit One (PCR1) IS used to select the edge
which activates CPl. When PCRl = "0", CPl IS active on RESET SEQUENCE
negative transitions (hlgh-to-Iow) Low-to-hlgh transitions A tYPical reset sequence for the MC6846 Will Include In-
are sensed by CPl when PCRl = "1" Itialization of both the Penpheral Control and Data Direction
In addition to ItS use as an Interrupt Input, CPl can be us- Registers of the parallel port. It IS necessary to set up the
ed as a stroDe to capture Input data In an Internal latch ThiS Peripheral Control Register first, Since PCR7 ~ "0" IS a con-
option IS selected by wntlng a "one" Into Penpheral Control dition for writing data Into the Data Direction Register (A
Register Bit Two (PCR2). In operation, the data at the pins logiC zero at the external RESET Input automatically sets
designated by the Data Direction Register as Inputs Will be PCR7 )
captured by an active transition of CPl. An MPU Read of the
Penpheral Data Register Will result In the captured data be- SUMMARY
Ing transferred to the MPU - and It also releases the latch to The M C6846 has several optional modes of operation
allow capture of new data Note that successive active tran- which allow It to be used In a variety of applications The
SIStlonS With no Read Penpheral Data Command between follOWing tables are proVided for reference In selecting these
does not update the Input latch. Also, It should be noted modes

4·495
 MC68460MC68A46

TABLE 9 - MC6846 INTERNAL REGISTER ADDRESSES

A2 Al AO REGISTER SELECTED
0 0 0 Combination Status Register
0 0 1 Peripheral Control Register
0 1 0 Data Direction Register
0 1 1 Peripheral Data Register
1 0 0 Combmation Status Register
1 0 1 Timer Control Register
1 1 0 Timer MSB Register
1 1 1 Timer LSB Register
X X X ROM Address

TABLE 10 - COMPOSITE STATUS REGISTER

CSR3-CSR6 NOT USED. DEFAULT

CSR7
I TO ZERO WHEN READ
I CSR2
I CSRI
I CSRO
I
I I I
COMPOSITE INTERRUPT FLAG I ITIMER INTERRUPT FLAG I

I
CP2 INTERRUPT FLAG I
0= NO ENABLED INTERRUPT FLAG SET 0" NO INT REQ 0= NO INT REQ.
1 = ONE OR MORE ENABLED INTERRUPT FLAGS SET.' 1 = INT REQUESTED 1 = INT REQUESTED

INVERSE OF THIS BIT APPEARS AT IRQ OUTPUT

CPl INTERRUPT
'STATUS OF THIS BIT CAN BE EXPRESSED AS 0= NO INT REQ.
CSR7 = CSRO - TCR6 + CSRI - PCRO + CSR2 - PCR3 1 = INT REQUESTED
I I

TABLE 11 - TIMER CONTROL REGISTER

TCR7
I TCR6
I TCR5
I TCR4
I TCR3
I TCR2
I TCRI
I TCRO
I
I L I I I
INTERRUPT ENABLE
0= IRQ MASKED
L I INTERNAL RESET
0= TIMER ENABLED
1 = IRQ ENABLED 1 = RESET STATE

CLOCK SOURCE
TIMER OUTPUT ENABLE
0= EXTERNAL CLOCK (CTC)
0= OUTPUT DISABLED (LOW)
1 = OUTPUT ENAB LED I 1 = INTERNAL CLOCK (<1>2)
-- ---------------
FOR CASCADED SINGLE-SHOT 78 PRESCALE ENABLE
0= OUTPUT GOES LOW AT TIME OUT
I
0= CLOCK NOT PRESCALED
1 = OUTPUT GOES HIGH AT TIME OUT 1 = CLOCK PRESCALED H- 8)

TCR3 TCR4 TCR5 TIMER OPERATING MODE COUNTER INITIALIZATION INTERRUPT FLAG SET
0 0 0 CONTINUOUS CTG,[ +W + R T.O.
0 0 1 CASCADED SINGLE SHOT CTG,[ + R T.O
0 1 0 CONTINUOUS CTG,[ + R T.O.
0 1 1 NORMAL SINGLE SHOT CTG,[ + R T.O.
1 0 0 FREQUENCY COMPARISON CTG,[ -I- (W+T.O) +R CTG,[ BEFORE T.O
1 0 1 CTG,[ - 1+ R TO. BEFORE CTG'[-
1 1 0 PULSE WIDTH COMPARISON CTG,[ - 1+ R CTGt BEFORE T.O.
1 1 1 T.O. BEFORE CTGt

R = RESET CONDITION CTG,[ = NEG TRANSITION OF PIN 17

W = WRITE TIMER LATCHES CTGt = POS TRANSITION OF PIN 17
T.O. = COUNTER TIME OUT T = INTERRUPT FLAG (CSRO) = 0

4-496
MC6846- MC68A46

TABLE 12 - PERIPHERAL CONTROL REGISTER

PCR7
I PCR6
I PCRS
I PCR4 PCR3
I PCR2
I PCRl
I PCRO
I
I I
CP2 DIRECTION CONTROL
0= CP2 Is INPUT
I CPl INT. ENABLE
0= CPl INT. MASKED
I 1 = CP2 Is OUTPUT 1 = CPl INT. ENABLED

RESET (SET BY EXT. RESET = 0 OR WRITING

ONE INTO LOCATION, CLEARED BY
ICPl ACTIVE EDGE SELECT
0= NEGATIVE It! EDGE
I
WRITING ZERO TO THIS LOCATIONI 1 = POSITIVE (tl EOGE
------------------
0= NORMAL OPERATION

l
CPl INPUT LATCH CONTROL
1 = RESET CONDITION (CLEARS PERIPH
0= INPUT DATA NOT LATCHED
DATA & DATA DIRECTION REG + CSRl & CSR21 1 = INPUT DATA LATCHED ON ACTIVE CPl

I CP2 Is INPUT (PCR5 = 01

I PCR~ PCR3 CP2 IS OUTPUT (PCR5 = 11

I PCR4
I PCR3
I 0 0 INTERRUPT ACKNOWLEDGE

•
0 1 INPUT/OUTPUT ACKNOWLEDGE

ICP2 ACTIVE EDGE SE LECT

0= NEGATIVE (.\.1 EDGE
II CP2 INT. ENABLE
0= CP2 INT. MASKED 1
PROGRAMMABLE OUTPUT
OOR 1 (C1'2 REFLECTS DATA
1 = POSITIVE (tl EDGE 1 = CP2 INT ENABLED WRITTEN INTO PCR31

CUSTOM PROGRAMMING*

By the programming of a single photomask for the After the EPROM(s) are marked, they should be placed In
MC6846, the customer may specify the content of the conductive IC camers and securely packed Do not use
memory and the method of enabling the outputs styrofoam
Information on the general options of the MC6846 should
be submitted on an Organizational Data form such as that
shown In Figure 19. FIGURE A-1
Information for custom memory content may be sent to
Motorola In one of two forms (shown In order of
preferencel'
1. EPROMs
2 MOOS Diskette
The specification should be formatted and packaged, as
xxx
indicated In the appropflate paragraph below, and mailed
prepaid and Insured With a cover letter to
Motorola Inc
MPU Marketing L2787
3501 Ed Bluestein Blvd
Austin, Texas 78721
A copy of the cover letter should also be mailed separately
xsoo XCOO

EPROMs xx = Customer 10
MCM2708 and MCM2716 type EPROMs, programmed
With the custom program (positive logic notation for address
and data), may be submitted for pattern generation The
MC2708s must be clearly marked to indicate which PROM MOOS DISKETTE
corresponds to which address space ($X800-$XFFF) See The start/end location should be wfltten on the label,
Figure A-l for recommended marking procedure EXORcisor format

"Motorola proVides two ROM patterns In the MC6846

1 MIKBUG 20 - MC6846L 1,P1
2 TVBUG 1 2 - MC6846L3,P3

4-497
 FIGURE 19 - FORMAT FOR PROGRAMMING GENERAL OPTIONS

ORGANIZATIONAL DATA
MC6846 COMBINATION ROM-I/O-TIMER

Customer:

Motorola Use Only:

Company

Part No. Quote: _ _ _ _ _ _ _ _ _ _ __

Originator _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ Part No.:

PhoneNo. _ _ _ _ _ _ _ _ _ _ ____ Specif. No.: _ _ _ _ _ _ _ _ __

I
Enable Options: (ROM ENABLE MUST DIFFER FROM I/O TIMER)
CHECK ONE COLUMN ONLY
o o I/O·TIMER SELECT 1;> 2.0V.

CSO 00 00 1
A6
0 X
A10
A9
X
X
1
X
X
1
X
X
X
x x=
0" O.8V.

CSI 00 00 DOD A8 x x X 1 X NOT USED

ROM SECTION I/O-TIMER SECTION A7 X X X X 1

4·498
 MC6847
@ MOTOROLA Non-Interlace
MC6847Y
Interlace

MOS
MC6847 I MC6847Y VIDEO DISPLAY GENERATOR (VDGl IN-CHANNEL, SILICON-GATE)

The video display generator IVDG) provides a means of Interfacing VIDEO DISPLAY
the M6800 microprocessor family lor similar products) to a standard col-
or or black and white NTSC televIsion receiver. Applications of the VDG GENERATOR
Include video games, process control displays, home computers,
education, commUniCations, and graphics applications
The VDG reads data from memory and produces a video signal which
will allow the generation of alphanumenc or graphic displays The
generated video signal may be modulated to either channel 3 or 4 by
uSing the compatible MC1372 (TV chroma and video modulator!' This
modulated signal IS sUitable for reception by a standard unmodified
televIsion receiver A typical TV game IS shown In Figure 1

• Compatible with the M6800 Family, the M68000 Family, and Other
Microprocessor Families

• Generates Four Different Alphanumenc Display Modes, Two Seml-

graphic Modes, and Eight Graphic Display Modes

•
• The Alphanumenc Modes Display 32 Characters Per Line by 16 Lines
USing Either the Internal ROM or an External Character Generator

~"""
• Alphanumenc and Semlgraphlc Modes May Be Mixed on a Char-
acter-by-Character BaSIS
I '( _S SUFFIX
• Alphanumenc Modes Support Selectable Inverse on a Character- ( , ' ' .' i CERDIP PACKAGE
by-Character BaSIS , CASE 734

• Internal ROM May Be Mask Programmed with a Custom Pattern

PIN ASSIGNMENT
• Full GraphiC Modes Offer 64x64, 128x64, 128x96, 128x 192, or
256 x 192 DenSities
Vss
• Full GraphiC Modes Use One of Two 4-Color Sets or One of Two DD6
2-Color Sets
DDO
• Compatible with the MC1372 and MC1373 Modulators Via Y, R-Y DDI
i<l>A), and B-Y I<I>B) Interface
DD2
• Compatible with the MC5683 174LS783) Synchronous-Address Multi- DD3
plexer

• Available In Either an Interlace INTSC Standard) or Non-Interlace

Version
CHB
</IB
GMD
GMI
y
GM2
DA4
DA3
DA2
DAI
DAD
DA12

4·499
 MC6847-MC6847Y

FIGURE 1 - BLOCK DIAGRAM OF A TV GAME USING THE VDG AND THE MC6B09E MPU

4X Color
Burst Freq
143B MHz
RF Sign .,
rlD~ to TV

L
t3
SO-S2 Synchronous ClK ClK
E E Address M
MC6883

11
MC6809E C
Multiplexer DAO DAO 1
MPU
Q Q 3
AO-A15 ZO-Z7 WE ~ RAS R'S HS </>B ~ 7

16 8
t f
I
1-
</>A ~
MC6847 Y ~RF
Video
2
jJ
Dynamic Display ~
00-07 RAM l Generator
8 Array A
IMCM4027,
MCM4116, MCM6633
r---<r- T
C ~ 00-07
H
AO-A15 or MCM6665)
-

•
r--
B
U
F
F Mode
E
~ 5

AO-A15
r--
l
Game
-
Paddles
00-07
CS
A
T
C
MC6646 ~ H
i...-
ROM
1/0 Timer

CS
2

ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Characteristics Symbol Value Unit ThiS deVice contains circuitry to protect the in-
puts against damage due to high static voltages
Supply Voltage VCC 03to +70 V
or electnc fields, however. It IS adVised that nor-
Input Voltage Any Pin V,n -03to +70 V mal precautions be taken to avoid application of
Operating Temperature TA a to + 70 ·C any voltage higher than maximum rated voltages
Storage Temperature Tstg 65 to + 150 ·C to thiS high Impedance circUit Reliability of
operation IS enhanced If unused Inputs are tied to
an appropriate logiC voltage Ie g , either VSS or
THERMAL CHARACTERISTICS VCC)

Characteristics Symbol Value Unit

Thermal Resistance
Ceramic 50
6JA ·C/W
PlastiC 100
Cerdlp 60

4-500
MC6847-MC6847Y

DC (STATIC) CHARACTERISTICS IVCC =5 0 V ±5%, VSS =00 V, T A =O°C to 70°C unless otherwise noted I
Characteristic Symbol Min Typ Max Unit
Input High Voltage :
ClK VIH Vss + 24 ~

VCC V
Other Inputs VSS + 2 0 ~

Vec
Input low Voltage
ClK Vil Vss ~O 3 ~

Vss + 04 V
Other Inputs VSS - 03 - VSS + 0 S
Input leakage Current, Force 5 25 V on Pin Under Test,
VCC=55 V ClK, GMO·GM2, INV, INT/EXT, MS, VSS, lin ~ ~

25 ~A
DDO-DD7, A/S, A/G
Three·State 10ff Statel Input Current DAO·DA 12
10l - ~

± 10 ~A
Force 2 4 V and 04 V on Pin Under Test
Output High Voltage ICload = 30 pF, Iload = ~ 100 ~A RP, HS, FS VOH 24 - ~

V
OutputHlghVoltageICload~55pF, Iload~ -l00~AI DAO·DA12 VOH 24 - ~

V
Output low Voltage ICload~3O pF, Iload~ 1 6 mAl RP, HS, FS VOL - ~

VSS + 04 V
Output low Voltage ICload = 55 pF, Iload = 1 6 mAl DAO·DA12 VOL - - VSS + 0 4 V
Output High Current ISourclng) All Outputs I Except
10H ~ 100 - - ~A
(VOH=24V) </>A, </>B, Y, and CHS)
Output low Current (Sinking) All Outputs I Except
10l 16 - - rnA
IVOl=O 4 V) </>A, </>B, Y, and CHB)

•
Input Capacitance (V in 0, TA 25°C, f 10MHz) All Inputs Cin 75 pF
Internal Power DISSipatIOn IMeasured at T A ~ 0 to 70°C) PINT 600 mW
Chroma </>A Voltage IFlgure 3) VIH 1S 20 22
ICload=20 pF, Rload= 100 kill VR 134 15 166 V
INote 11 VOL OS 10 12
Chroma </>B Voltage IFlgure 3) VIH 1S 20 22
ICload=20 pF, Rl oa d=l00 kill VR 134 15 i 66
V
INote 11 VOL o SO 10 12
VS urst 1 07 125 143
luminance Y Voltage IFlgure 3)
ICload = 20 pF, Rload = 100 kill
(Voltage Synchronization) Vs 09 10 11
IVoltage Blank) VSlank 063 077 09
V
IVoltage Blackl VSlack 058 072 o S3
IVoltage White low) VWl 051 065 075
IVoltage White Medluml VWM 040 054 065
IVoltage White Hlghl INote 11 VWH 027 042 053
Chroma Bias Voltage ICload=20 pF, Rload= 100 kill VR 027 VCC 03 VCC 033 VCC V
ReSistor % of VSS Tracking IAnalog Outputs linearity Errorl RT ~

10 30 %

NOTE 1 The speCified minimum and maximum number reflect performance of the VDG of the speCified temperature range OverlapPing vol-
tage levels Will not occur Refer to Figure 2

4-501
 MC6847-MC6847Y

POWER CONSIDERATIONS

The average chip-Junction temperature. T J. In °c can be obtained from'

TJ=TA+IPooOJA) 11)
Where
T A'" Ambient Temperature. °c
0JA- Package Thermal Resistance. Junctlon-to-Amblent. °C/W
PO'" PINT+ PPORT
PINT""ICC x VCC. Watts - Chip Internal Power
PPORT=Port Power Oissipation. Watts - User Oetermmed
For most applicatIOns PPORT<C PINT and can be neglected PPORT may become s'·,nlflcant If the device IS configured to
drive Oarlmgton bases or Sink LEO loads
An approximate relationship between Po and T J lif PPORT IS neglected) IS
PO= K-IT J + 273°C) 12)
Solvmg equations 1 and 2 for K gives
K = PoolT A + 273°C) +OJAOP0 2 13)
Where K IS a constant pertaining to the parllcular part K can be determined from equal' 'n 3 by measuring Po lat eqUilibrium)
for a known T A USing thiS value of K the values of Po and T J can be obtamed by solvmg equations 11) and 12) Iteratively for any
value of T A

• FIGURE 2 - PSEUDO ANALOG LUMINANCE RESISTOR CHAIN

+5V VS ync
--L

VBlack
--L

NOTE The chrommance output cham IS Similar In design to the luminance chain

4-502
MC6847e MC6847Y

-
AC (DYNAMIC) CHARACTERISTICS IVCC-5 0 V ±5% TA --O·C to 70·C) Iload ClfCUlt 01 Figure 3)
Characteristic Symbol Min Max Unit Figure
ClK IFrequency 13579545 Color Burst Frequency) I 3579635 35B7566 MHz 4
ClK Duty Cycle ClKdc 45 55 % 4
Clock Rise Time tClKr - 50 ns 4
Clock Fall Time tClKI - 50 ns 4
Clock Pulse Width PWClK 120 160 ns 4
Honzontal Display Address Delay from Counter DAD-DA3 tHDAD - 490 ns 4,5,6
DA4 tHDA4D - 550 ns 5,6
Honzontal Display Address Hold Time tHDAH 0 - 4,5,6
ns
tHDA4H 0 -
Display Data Setup Time CSS,INV, A/S, iJilT'/EXT, DDD-DD7 tDDS 70 - ns 4,5,6
Display Data Hold Time CSS,INV, A/S'\flT/EXT, DDD-DD7 tDDH 140 - ns 4,5,6
Honzontal Sync 1m) Delay Fall tDHSI - 550
ns 7
Rise tDHSr - 740
Row Preset IRP) Delay Fall tDRPI - 660
7
ns
Rise tDRDr 540
Vertical Display Address Delay Irom Counter DA5-DA12 WOAD - 60 "s 7
Vertical Display Address Hold Time tVDAH - 220 ns 7
Field Sync II'S) Delay Fall tDFSI - 520
ns 8

•
Rise tDFSr 600
Memory Select low to Display Address High-Impedance tDMST - 80 ns S
Memory Select High to Display Address Valid tDMSV - 400 ns S
Chroma Rise and Fall Times
Iq,A Rise Time) trCq,A - 100
trq,A - 100
Iq,A Fall Time) tICq,A - 100
tlq,A - 100 ns 12
Iq,B Rise Time) trCt/>B - 100
trq,B - 100
Iq,B Fall Time) tlCt/>B - 100
tlq,B - 100
Color Burst Rise Time on q,B Output tCBr - 100 ns 12
Color Burst Fall Time on q,B Output tCBI 100 ns 12
Chroma Phase Delay I Measured with Respect to "Y" Output)
q,A tVA -50 140 ns 11
q,B tYB -50 140
Lummance Rise Time try - 100 ns 12
luminance Fall Time tlv - 100 ns 12
Honzontal Sync Rise Time on Y Output tHr - 100 ns 12
HOrizontal Sync Fall Time on Y Output tHI 100 ns 12
Honzontal Blanking Rise Time on Y Output tHBr - 100 ns 12
Honzontal Blanking Fall Time on Y Output tHBI - 100 ns 12
Front Porch DuaratlOn Time 17 x 11fl tFP 18 2.4 ,.s 12
Back Porch Duration Time 117 5x 111) tBP 45 51 ,.s 12
Left Border DuratIOn Time 129 5 x 11fl tlB 75 83 "s 12
Right Border Duration Time 128 x 11fl tRB 75 83 ,.s 12
Color Burst DuratIOn Time 110 5 x 111) tCB 27 3,2 ,.s 12

FIGURE 3 - TEST lOADS

AD-A12, n, RP, HS 475 V q,A,q,B, Y, CHB

MMD6150
Test or EqUiv 250 kll
TestPolnt~

r
POint

0
24 k 100 k
MMD7000
30PF
or EqUiv
':' ':'

4-503
 MC6847e MC6847Y

FIGURE 4 - CLOCK AND LONG CYCLE HORIZONTAL ACCESS TIMING

tClKf--!~~_-

NOTES
1 The VDG may power-up uSing either the riSing or failing edge of the clock (dotted Ime)
2 Transitions of DA4-DA 12 occur outside the display area DAO~DA3 access the 16 bytes of data displayed dUring each scan line In the dls~

II play area
long cycle timing applies to CG1, RG1, RG2, and RG3 modes (see Table 31 A/G IS high, AS, INT IEXT, and INV Input levels do not affect
the VDG In long cycle modes
Usable RAM access time for the long cycle may be calculated USlflg the following equation
tRACl ~ S.l/l max - tHDAD max - tDDS max - tClK
If address and data buffers are used, the access time must be adjusted accordingly
All timing IS measured to and from a low voltage of 0 8 volts and a high voltage of 20 volts unless otherwise specified

FIGURE 5 - SHORT CYCLE HORIZONTAL ACCESS TIMING

tClKr

ClK

DAO-DA3

DA4

DDO-DDl
CSS, A/G,
INT/EXl

NOTES
The VOG may power-up uSing either the rising or falling edge of the clock as shown In Figure 4
Transitions of DA5-0A 12 occur outside the display area DAO-OA4 access the 32 bytes of data displayed during each scan line In the dis-
play area
3 Short cycle timing applies to the four alphanumenc modes, two semlgraphlc modes, and to the CG2, CG3, CG6, RG6 modes (see Table 3)
For the four graphic modes, A/G IS high and the A/S, INTI EXT, and INV Input levels do not affect the VDG
4 Usable RAM access time for the short cycle may be calculated uSing the follOWing equation
tRACS ~ 4.1/1 max - tHDA4D max - tDDS max - tClKr
If address and data buffers are used, the access time must be ad lusted accordingly
All timing IS measured to and from a low voltage of 0 8 volts and a high voltage of 20 volts unless otherWise specified

4-504
 s:
(")

~•
s:
(")

FIGURE 6 - HORIZONTAL ADDRESS AND VALID DATA SETUP AND HOLD TIMING
~-<
(Timing Relationships Shown From Beginning of Line)

DAO-OA3 --..ll-I\.. ....... Valid Address

Valid Address Valid Address

Ie lRACL---tt------ [' II 'CHARL II II -I

.... DDD·DO? - --~Valid Data (Forst Character on Screen Alter Borderl

Ot tCA~ :=-X~_-:.-:.-_ :=-_X~:=_
o(J1 DAO-DA3 Valid Address Valid Address Valid Address

DA4 ,II ~. Valid Address =:~X:==.:__ Valid Address :::x-:.:.=-:_ Valid Address

I..'nu.\o( (CHARS !I _I
ZZ(III(//j/Ilj//I///J//JI/Tf//iIlI//llj//]I///jllllffilJ'c~ ~ . ~. ~'''c ~ 'PIC
00000' VJ/J/1l/1711/1/II/IJ//IIT!IIi//L '£d':-D':;-~/f)lllIlJl7lll/l/lfJ/O€!!i§!;Wjj./mJ/II/flI/IJ///IIIIIj/I(/IJJ€'~~~~
C55 lNV A/S INTlm
DOD-DO?

-Long element/access modes CG1, RGl RG3

··Short element/access mode CG2, CG3 RG6, Alphanumencs Semlgraphlcs

•
 • s::
(')

~•
s::
(')

~-<

FIGURE 7 - VERTICAL ADDRESS, ROW PRESET AND HORIZONTAL SYNCHRONIZATION TIMING

~
c:n
o
en

NOTES
1 All timing IS measured to and from a low vol.age of 0 8 volts and a high voltage of 2 0 volts unless otherwise specified
2 HS pulse width may be determmed by IWHS = 16 5.1Jf~ tDHSF+ tOHSr
3 HS to RP may be determined by tHSRP = 3 5.1/1- tOHSr + tORP!
4 RP pulse width may be determined by IWRP = 3 5.1/1 - tORPt + tORPr
5 DA5-DA12 will change during the Inactive portion of the display
6 tPHS=2275.1!1
7 100T= '/,I
MC6847- MC6847Y

FIGURE 8 - FIELD SYNC (FS) TIMING

ClK

•
. .- - - - - - - - t P F S - - - - - - - - - + !
Note 2
NOTES
1 tWFS=32.tPHST= 32.(277 5.1ff)
2 tPFS=262.tPHST=262.1227 5·1/f) for MC6847
tpFS = 262 5.tPHST=262 5.1227 5·1ff) for MC6847Y

FIGURE 9 - MEMORY SELECT (MS) TIMING

MS
Note 1
tDMSV
tDMST

MAO-MA12 Valid Address Valid Address Valid Address

NOTES
1 MS IS asserted asynchronously with respect to ClK

4-507
 MC6847 e MC6847Y

FIGURE 10 - VIDEO AND CHRDMINANCE OUTPUT WAVEFORM RELATIONSHIPS

1 TFP

tWHS
J..
I - Left Border
tBP - - - -
IHST
Note 4 - - - - - - - - - - - - - - - . !
-------tAVB
Note 3

tlBlOlOt--------tAV
------ ..I
RIght Border I
-----1
~I<I(tRB1

Y ~:~Note~:lanc
~ ,",", ~~Ho~~~-l
WM ----" I r-----,I~_I-'""-__1 I
WH
End of
1---1, 1--__1 l-
, If A,iG ~O
Honzontal i'\/GoCSS
I I I
---t r
Stijfvnc tHC;IGOCSS
Note 1
tCB
I
I
I
I'
,
II
A/G+A/GoCSS I
VSurst A/G °
VOL
CSS I

II (Burst removed
I
IS
I I
for
i'\IG 0CSSoGMOI I I
I I

A/G + A/GoCSS
,
I
,Yellow, Blue
Red
~B~U~ff_~
II Magenta Orange

l::J
A/GoCSS ""_ _L...::G",re""e::.:.n.......,

NOTES
1 tHCD=35.1/f
2 tAV=128.1/f
3 tAVB= 185 5.1/f
4 Refer to Figure 7
5 tHBNK = 42·1 If

FIGURE 11 - CHROMA PHASE DELAY

tYA_
f-
</>A

--
</>B

-tYB

4·508
MC6847-MC6847Y

FIGURE 12 - TIMING DIAGRAMS

VIDEO RISE AND FALL TIMES IlIIustrates Beginning of One Horizontal Linel

tLB---l

Vsync

VSlank
y
VBlack
VWL
VWM

VWH

II
tCBr

<l>B ------...,':':'0:0:%'1

VBurst 90%
VOL
tCBf

tf<l>A

trC<I>A

tfC<I>A trC<I>A
VR
<l>A

VOL 90% '0%

4·509
 MC6847-MC6847Y

FIGURE 13 - DISPLAY AREA TIMING

Vertical Blanking 13 H Lines

Top Border 25 H Lines

-
-- - I--

"0
Q;
u: <1>
.c
" ~'" "
Jl
Active Display Area 192 H Lines
g)
c
g)
c .2 Ei:
.:; .:; <1> 0
z
~ .,. OJ!"Q;
N
N
w
<1>
c
E .:;
g) N
<0
C N
.:;
:s;
N
<0
Failing Edge of FS N

•
IStart of Vertical Blankl

~
Bottom Border 26 H Lines
-- I - -I-

Vertical Retrace 6 H Lmes

tAV

tAVS

tHST

FIGURE 14 - TYPICAL FORMAT OF THE TELEVISION SCREEN

BORDER
(Black In all alpha/semlgraphlc modes Green or buff (off-white)
,n all graphiC modes Controlled by the VDG I

- - - - 2 5 6 Dots ------JooI

DISPLAY AREA
149,152 dots, all under VDG
control In all modes Each
one of up to 8 colors when on
depending on mode l

·One on each non-Interlaced line, for Interlace, the lines of the odd
field are copied Into the even field thus doubling the number of dis-
played dots

4-510
MC6847-MC6847Y

VIDEO DISPLAY GENERATOR DESCRIPTION change dunng the active display area. A4 changes dunng the
actIVe display area m the alphanumencs, semlgraphics, CG2,
The MC6847/MC6847Y video display generators provide a CG3, CG6, and RG6 modes. A&-A12 cfl not togglewlthm the
simple mterface for display of digital Information on a color active display area but mstead, npple through the address
monitor or standard color/black and white televIsion dunng border and blankmg time.
receiver.
TelevIsion transmissions in North and South Amenca and DATA INPUTS (DOG-DD7)
Japan conform to the National TelevIsion System Commit- Eight TTL compatible data lines are used to Input data
tee INTSCI standards ThiS system IS based on a field repeti- from RAM to be processed by the VDG The data IS then In-
tIOn rate of 60 fields per second. There are 525 Interlaced terpreted and transformed mto luminance IY) and chroma
lines per frame or one-half thiS number per field. outputs Iq,A and q,B)
The MC6847 scans one field of 262 lines 60 times per sec-
ond. The MC6847 non-Interlace VDG IS recommended for POWER INPUTS - VCC reqUIres +5 volts ±5%. VSS
use In systems lie., TV games and personal computers) reqUires zero volts and IS normally ground. The tolerance and
where absolute NTSC compatibility IS not reqUired If NTSC current requirements of the VDG are specified In the Elec-
compatibility IS reqUired, perhaps for caption overlays on tncal Charactenstlcs.
broad-case signals, then the MC6847Y mterlace VDG IS
recommended. VIDEO OUTPUTS (q,A, q,B, Y, CHB) - These four analog
outputs are used to transfer luminance and color Information
NOTE to a standard NTSC color teleVISion receiver, either via the
A system with the MC6847 VDG and the MC1372 MC1372 RF modulator or via dnvers directly Into Y, q,A, q,B
Video modulator forms a transmitter, transmlttmg at teleVISion Video Inputs Isee Figures 10, 11, and 121.
61 2 MHz Ichannel3) or 6725 MHz Ichannel4) depen-

•
ding on component values chosen ThiS bemg a Class I Luminance (V) - ThiS SIX level analog output contams
TV deVice, care must be taken to meet FCC re- composite sync, blankmg and four levels of Video luminance.
qUirements Part 15, Subpart H However, If the com-
posite Video output from the MC1372 were to dnve the q,A - ThiS three level analog output IS used m combma-
teleVISion directly, Section 15.7 of the FCC specifica- tlon with q,B and Y outputs to speCify one of eight colors.
tIOn must be adhered to.
q,B - ThiS four level output IS used In combination with
q,A and Y outputs to speCify one of eight colors Additional-
SIGNAL DESCRIPTION Iy, one analog level IS used to specify the time of the color
bu rst reference Signal
DISPLAV ADDRESS OUTPUT LINES (DAG-DA12)
Thirteen address Imes are used by the VDG to scan the
display memory as shown m Figures 4-7 The starting ad- Chroma Bias (CHB) - ThiS pin IS an analog output and
dress of the display memory IS located at the upper left cor- proVides a DC reference corresponding to the quiescent
ner of the display screen. As the teleVISion sweeps from the value of q,A and </>B. CHB IS used to guarantee good thermal
left to nght and top to bottom, the VDG Increments the trackmg and minimize the vanatlOn between the MC1372end
RAM display address. The tlmmg for two accesses starting MC6847. ThiS pm, when pulled low, resets certain registers
at the begmnlng of the line IS shown In Figure 6 These lines wlthm the chip. In a user's system, thiS pm should not nor-
are TTL compatible and may be forced Into a hlgh- mally be used as an mput It IS used mamly to enhance test
Impedance state whenever MS Ipln 12) goes low AO-A3 capabilities wlthm the factory

FIGURE 15 - VIDEO TO B&W MONITOR

+5V
+5V

Luminance Y from ~'~~~ o-_""R""I'v---I 01

1 KII I Video Out

01,02-2N3646
Contributed by Ted Hanwlck, Honeywell, Inc

4·511
 MC6847- MC6847Y

SYNCHRONIZING INPUTS (~, ClK) HORIZONTAL SYNC (H§) - The m

pulse cOincides
THREE-STATE CONTROL - (1iiIS) IS a TTL compatible with the hOrizontal synchronization pulse furnished to the
Input WhiCh, when low, forces the VDG address lines Into a televIsion receiver by the VDG (see Figure 71 The hlgh-to-
high-Impedance state, as shown In Figure 9. This may be low transition of the HS output cOincides with the leading
done to allow other deVices (such as an MPU) to address the edge of the hOrizontal synchronizatIOn pulse and the low-to-
display memory (RAM), high transition cOincides with the trailing edge.

CLOCK (ClK) - The VDG clock Input (ClK) requires a ROW PRESET (RP) - If deSired, an external character
3 579545 M Hz (standard color burst) TV crystal frequency generator ROM may be used with the VDG However, an ex-
square wave The duty cycle of this clock must be between ternal four bit counter must be added to supply row ad-
45 and 55% Since It controls the width of alternate dots on dresses The counter IS clocked by the HS signal and IS
the televIsion screen The MC1372 RF modulator may be cleared by the RP signal. RP pulses occur In all alphanumeric
used to supply the 3 579545 MHz clock and has provIsions and semlgraphlcs modes; no pulses are output In. the full
for a duty cycle adjustment. The VDG will power-up uSing graphiC modes. RP occurs after the first valid 12 lines
either the rising or falling edge of the clock. The dotted line Therefore, use an FS clocked preloadable counter such as a
on the ClK signal In Figure 4 Indicates thiS characteristic of 74lS161 as shown In Figures 7, 14, and 23
latching In data on either clock edge
MODE CONTROL LINES INPUT (A/G, A/S, m/EXT,
SYNCHRONIZING OUTPUTS (i'S, AS, AP) GMO, GM1, GM2, CSS, INV)
Three TTL compatible outputs provide CirCUitS, exterior to Eight TTL compatible Inputs are used to control the
the VDG, with timing references to the following Internal operating mode of the VDG A/S INT/EXT, CSS, and INV
VDG states' may be changed on a character-by-character baSIS The CSS
Pin IS used to select between two pOSSible alphanumeric col-

I FIELD SYNC (i's) - The hlgh-to-Iow transition of the FS

output cOincides with the end of active display area (see
Figure 8), DUring thiS time Interval, an MPU may have total
access to the display RAM without causing undesired flicker
on the screen. The low-to-hlgh transition of FS cOincides
with the trailing edge of the vertical synchronizatIOn pulse
ors when the VDG IS In the alphanumeric mode and between
two color sets when the VDG IS In the Semlgraphlcs 6 or full
graphiC modes. Table 11l1ustrates.the variOus modes that can
be obtained uSing the mode control lines There are two dif-
ferent types of memory access concerning these modes,
they are a short and a long access cycle, which differ by a

FIGURE 16 - EXTERNAL CHARACTER GENERATOR ROW COUNTER FOR MC6847

+5V

3 5 6
+5V
PO P1 P2 P3
16
VCC
MR
CEP
9 10
From PE 74LS161 CET
MC6847
2 GND
CP~

00 01 02 03

11

\ )
v
Row Address
(Zero Through Eleven I

4-512
MC6847-MC6847Y

TABLE 1 - MODE CONTROL LINES (lNPUTSI

A/G A/S iFlf/EXT INV GM2 GMI GMO Alphal Graphic Mode Select , of Colors
0 0 0 0 X X X Internal Alphanumerics
0 0 0 1 X X X Internal Alphanumerics Inverted
2
0 0 1 0 X X X External Alphanumerics
0 0 1 1 X X X External Alphanumerics Inverted
0 1 0 X X X X Semlgraphlcs 4 (SG4) 8
0 1 1 X X X X Semlgraphlcs 6 ISG6) 8
1 X X X 0 0 0 64x64 Color Graphics One ICG1) 4
1 X X X 0 0 1 128x64 Resolution Graphics One IRG1) 2
1 X X X 0 1 0 128 x 64 Color Graphics Two ICG2) 4
1 X X X 0 1 1 128x96 Resolution Graphics Two IRG2) 2
1 X X X 1 0 0 128 x 96 Color Graphic. Three ICG3) 4
1 X X X 1 0 1 128x 192 Resolution Graphics Three IRG3) 2
1 X X X 1 1 0 128 x 192 Color Graphics S'x ICG6) 4
1 X X X 1 1 1 256 x 192 Resolution Graphics S'x IRG6) 2

shift of one full 3 58 MHz cycle One of the differences be- of every honzontal blanking penod ThiS color burst IS sup-
tween these access times, In the short access time frame, IS pressed dunng vertical sync and equaliZing Intervals Color
a shift of one full 358 MHz cycle from the corresponding burst IS also suppressed In the most dense two color graphiC
normal long access time frame, as shown In Figure 6 The modes ThiS leads to some Interesting rainbow effects on the

•
modes uSing short access times read memory tWice as often display which IS frequency and pattern dependent. The ver-
as the long access modes tical timing for the VDG IS given In Figure 18 Vertical retrace
IS Initiated by the luminance Signal being brought to the
blanking level The vertical blanking penod beginS With three
OPERATION OF THE VDG lines of equaliZing pulses followed by three lines of serrated
vertical sync pulses followed by three more lines of equaliz-
A slmphfled block diagram of the VDG IS shown In Figure Ing pulses The remaining vertical blanking penod contains
17a and a detailed block diagram IS shown In Figure 17b the normal honzontal sync pulses The equaliZing and serra-
The externally generated 3 58 MHz color burst clock dnves tion pulses are at half line frequency Notice the difference In
the VDG Refernng to Figures 11 and 12, note that the spacing between the last honzontal sync pulse and the first
honzontal screen span from blanking to blanking IS 193 1 equaliZing pulse In even and odd fields. It IS the half line dif-
clock penods ( '" 53 95 ,..sl The display Window IS offset from ference between fields that produces the Interlaced picture In
the left-hand edge by 283 penods and lasts for 128 penods a frame. Vertical timing between fields for the non-Interlaced
(35 75,...1 Of the 242 hnes on the vertical screen from blank- VDG, on the other hand, IS Identical The equaliZing and ser-
Ing to blanking, 192 hnes are used for the display The ration pulses are, however, at the honzontal frequency
display Window IS offset from the top by 25 lines Under the The 358M Hz color frequency IS also used to clock the
constraint of the master clock, the smallest display element Video shift register load counter ThiS counter and the Video
pOSSible for the VDG IS half penod of the 358 MHz clock shift clock inhibit circUitry denve the dot-clock for the output
Wide by one scan line high All other display elements are of the Video shift registers and the load Signals for the Video
multiples of thiS baSIC SIZe shift registers' Input latches The vertical and honzontal ad-
dress counters generate the addresses for the external
DISPLAY MEMORY ADDRESS DRIVERS display memory
The address dnvers normally dnve the Video refresh ad-
dress Into the display memory so characters may be INTERNAL CHARACTER GENERATOR ROM
displayed on the CRT When the memory select pin IMSI IS Since many uses of the VDG Will Involve the display of
pulled low by an external decoder, the dnver outputs go to a alphanumenc data, a character-generator ROM IS Included
high-Impedance state so external three-state dnvers may on the chip ThiS ROM Will generate 64 standard 5 x 7 dot
SWitch the M PU produced address onto the display memory matnx characters from standard 6-blt ASCII Input A stan-
address bus, the MPU may directly manipulate data In the dard character set IS Included In the MC6847 although the
display memory ROM IS custom programmable

VIDEO TIMING AND CONTROL INTERNAL/EXTERNAL CHARACTER GENERATOR

ThiS subsystem of the VDG Includes the mode decoding, MULTIPLEXER
timing generation, and assOCiated row counter logiC, and The Internal/external multiplexer allows the use of either
uses the 3 58 MHz color frequency to generate honzontal the Internal ROM or an external character generator ThiS
and vertical timing information (via linear shift register multiplexer may be SWitched on a character-by-character
countersl, which the Video and chroma encoder uses to baSIS to allOW mixed Internal and external characters on the
generate color Video information The honzontal timing for CRT. The external character may be any deSired dot-pattern
the VDG IS summanzed In Figure 7 Ten and one-half cycles In the standard 8 x 12 one-character display matnx, thus
of the 358M Hz subcarner are transmitted on the back porch allOWing the maximum 256 x 192 screen denSity.

4-513
 MC6847-MC6847Y

FIGURE 17. - SIMPLIFIED VDG BLOCK DIAGRAM

MPU Address Bus MPU Data Bus

+5 OV

VDD VSS
VDG
Refresh
RAM
13
512 Bytes to
6K Bytes
Timing
CC
and
Control
8
A/S

•
A/G
GM2
GMI
GMO
CSS

6,7 or B

Character
Generator
ROM

H--'y....O LumInance
Parallel To
Senal Shift Register,
Video Chroma Encoder

VIDEO AND COLOR SUBSYSTEM

The 8-bit output of the Internal/external multiplexer IS calied Y. The luminance Signal, Y, and the two chromlnance
serialized In an 8-blt shift register clocked at the dot-clock outputs, </>A (R-Y) and </>B (B-Y), can be combined
frequency. (modulated) by an MC1372 Into a composite video Signal
The luminance information from the shift register IS sum- with color. Figures 8, 9, 10, and 16 show the relallonshlp be-
med with the hOrizontal and vertical sync Signals to produce tween the luminance and chromlnance Signals and the resul-
a composite video Signal 1E'.ss the chromlnance Informallon, tant color.

4-514
 ~
(")

FIGURE 17b - DETAILED VDG BLOCK DIAGRAM

~•
~
(")

~-<

A/G
! i !
Row Counter
A/S I (-121 i
I I I
Jm'1
EXT

~
...
(J'I

(J'I .C2 , GM2

! Vertical +Immg ~
GMl lmear Shift Register Counter
I l S RC I I

GMO (From HOrizontal Time) 64th Microsecond Counted

Tlmmg
Decode

I I 1 I
!Horlzontal Timing!
I l.S R ~ I ~1 ~2

Vee 1 03 MHz
:Ei~~:,1 II I:~II :~
+5V Non-Interlaced

Voo

Vss VOG
':" 358MHz

elK

II
 MC6847- MC6857Y

FIGURE 18 - NON-INTERLACE VERTICAL TIMING

{For Inte~ace Vertical Timing Uee Ineerts)

3 tpHS --+I-
3 tpHS ~ 3 tPHS .-J
i+--------19tPHS .,

Odd Field Interlaced

"Y"
~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tF or (1/tvFNI)---

~------tvBNK--N-ot-e-3---~~ Note 4

• Y

</>B
~ G/AoCSS
~

G/AOJ;!
G/A+ G/A+
G/AoCSS
..
_!!l
G/AoCSS

~AOCSS
~ 1£ §
~
§ ; ~
~
~ ~

VIH GtA+G/AoCSS
</>A VR --~~cr=---~"</>WA"~I---~nrICI~~~=========
0

FS
VOL
-, I.
G/PioCSS

twFS .1
~I------------~\~-------------­
·Note. No Row Preset Occurs Here
RP

NOTES 1[ J I of 31 468 kHz clocks ·tHBNK could actually be considered as part of the border -
(1/31.468 kHzl=31.n83,.s especlallv for purposes of writing to the screen The same holds
Non-Parentheses = I of 358M Hz Clocks true for the upper border.
1/3.58 MHz=279.366 ns
Time marks 466 and 0 are the same pOints In time

Example Timing Calculations.

tHST= (227.5-0) x 279 366 ns=63.5ps
= (466-227.5) x 279.366 nS=63.5,..
tWHS = (455-438) x 279.366 ns-4 75 "s
Lower Border';' (524-472) x 31.nB3 ,.s-tHBNK
=1.6625 ms-l1 6 ns=l64 ms

Upper Border = (B6-36)x31 7783 ,..-tHBIIIK=

=1.5886,..-11.6,..=158 ms
2. tRP= 12 honzontal scan hnes
3. tvBNK=20.tpf'lS=20.(227.5.1/1)
4. tF=262.tPHS=262.(227 5.1/1) for Non-lnteMace.
tF=262.5.TpHS=262 5.(227.5.1/1) for Interlace

4-516
MC6847 e MC6847Y

FIGURE 18 - NON-INTERLACE VERTICAL TIMING

(For Interlace Venical TIming Use Insens)
(Continued)

.1'" 3tPHS ~ 3tpHS ~

------19H

Even F,eld Interlaced

~I
I
I
I
I

:::;1
I
II
-----+----------~:~~~~~n~~~----~---~

:::::::::i=::::::::::::::::~::::::::::=G~/A~+~G~/~(j~OC~S~S~~::~____
G/ AoCSS "<pA"
r-______ ~(]

I
------lU~~~====~tR;P====~.~~r----------------------------------­
~~tHSRP Note 2 ~~tWRP
First Row Preset to Occur
Comes After the FIrst ActIVe
Row of Characters

4·517
 MC6847- MC6847Y

DISPLAY MODES The 5 x 7 character font IS positioned two columns to the

There are two major display modes in the VDG Major right and three rows down Within the a x 12 character ele-
mode 1 contains four alphanumeric and two limited graphic ment. SIX bits of the a-bit data word are tYPically used for the
modes. Major mode 2 contains eight graphic modes. Of Internal ASCII character generator The remaining two bits
these, four are full color graphic and four restnctFld color may be used to Implement Inverse Video, color SWitching, or
graphic modes. The mode selection for the VDG IS sum- external character generator ROM selection on a character-
marized in Table 2. The mnemonics of these fourteen modes by-character basIs. For those who Wish to display lower case
are explained in the following sections. letters, special characters, or even limited-graphics, an exter-
In major mode 1 the display window IS diVided Into 32 col- nal ROM may be used If such external ROM IS used, all of
umns by 16 character element rows thus requIring 512 bytes the ax 12 picture elements, or pixels, In the character ele-
of memory. Each character element IS a half periods by 12 ment can be utilized. Characters may be either green on a
scan lines In size as shown In Figure 19. The area outSide the dark green background or orange on a dark orange
display Window IS black. background, depending on the state of the CSS pin The in-
The VDG has a bUilt-In character generator ROM contaln- vert pin can be used to display dark characters on a bright
mg the 64 ASCII characters In a 5 x 7 format (see Figure 201. background.

•
TABLE 2 - SUMMARY OF MODES
Major Mode 1 - Alpha Modes

Title Memory Display Elements Colors

Alphanumerics 512x a 2
2-1 H 5

[tjJT
(Internal)

+D~
T 12

TH:"
Alphanumerics 512xa
00
0
0
0
T 2

... ~
0 0
0 0 12
(External) 0
0
0
0

0
0 0

4·518
MC6847-MC6847Y

TABLE 2 - SUMMARY OF MODES

Major Mode 1 - Alpha Modes
(Continued)

Title Memory Display Elements Colors

Semlgraphlc 4 512 x 8

[W",m",
Semlgraphlc 6 512x8
~"'m,"' 4

•
Major Mode 2 - Graphics Modes

Title Memory Colors Comments

64 x 64 Color Graphic 1 kx8 4 Matrix 64 x 64 Elements
128 x 64 Graphics· 1 kx8 2 Matrix 128 Elements Wide by
128 x 64 Color Graphic 2kx8 4 64 Elements High
128 x 96 Graphics· 1.5 kx8 2 Matrix 128 Elements Wide by
128 x 96 Color Graphic 3kx8 4 96 Elements High
128 x 192 Graphics· 3kx8 2 Matrix 128 Elements Wide by
128x 192 Color Graphic 6kx8 4 192 Elements High
256 x 192 Graphics 6kx8 2 Matrix 256 Elements Wide by
192 Elements High

·Graphlcs mode turns on or off each element. The color may be one of two.

4-519
 MC6847- MC6857Y

TABLE 3 - DETAILED DESCRIPTION OF VDG MODES

G S
VDG Pins
EXT/lNT GM2 GMl GMO CSS INV Character Cob
Green
Col••
Background
Black
...... OllPleyMode
32 Characters
Black Black per row
Green
Orange Black 16 Characters
Black Orange Black

Green Black Black

32 Characler~
Black Green per row
Orange Black Black
16 Characters
Black Orange

l, C2 Cl CO Color
0 X X Black
64 Display elements
0 0 G...n
per row
0 I Yellow
0 Blue Black
32 Display elements
Rod
Buff
1 Cyan

II
0 Magenta
1 1 Orange
l, Cl CO Color
0 X Black
0 Green
64 Display elements
0 Yellow
per row
1 Blue Black
R.d
48 Display elements
Black
Buff
Cyan
Magenta
1 Orange
Cl CO I 1,..0 or
0 0 Green
0 Yellow Green 64 Display elements
Blue per row
R.d
Buff Buff 64 Display elements
Cyan
Magenta
Orange
l, Color 128 Display elements
0 Black Green per row
1 G... n
0 Black 64 Display elements
Buff Buff
128 Display elements
Same color as Greer per row
Color GraphICs
a..
64 Display elements
Buff
128 Display elements
Same color as Green per row
Resolution
GraphiCS One 96 Display elements
Buff
128 Display elements ,
S8me color 8S Green per row
Color GraphiCS
On.
96 Display elements
Buff mrows
128 Display elements
Same color as Green per row
Resolution
Graphics One
192 DISpl8Y elements
Buff In rows

Same color as 128 Display elements

G"",n
Color GraphICs per row
On.
192 Display Elements
Buff

Sam8color as 256 Display elements

Green
Resolution per row
Gr8phICsOne
192 Dlsplav elements
Buff

4-520
MC6847 e MC6847Y

TABLE 3 - DETAILED DESCRIPTION OF VDG MODES

(Continued)

TV Scr••n
VDG Dat8 Bua Comments

The ALPHANUMERIC INTERNAL mode uses an Internal character

generator (whIch contams the follOWing five dot by seven dOl
characters .@ABCDEFGHIJKLMNOPQRSTUVWXYZ

I- I-I-I, .II. -I -II 1\1!I .... SP 1"1$%&'( )"+.-,0123456789,<"'>? The

ASCl1 code leaves twO bits free and these may be externally con
nected to the mode pms IG/A, S/'A, EXT/'iNT, GM2, GM" GMO,
51X bll

C55 or INV}
extra ASCII Code

IntemalAlphanumerlCS

The ALPHANUMERIC EXTERNAL mode uses an external character

..... 8 .......
generator as well as a row counter Thus. custom character fonts or

.t !.::.: I I I I II I II
graphiC symbol sets with up 10 256 different 8 x 12 dot "characters"

1" ~:::
may be displayed

One Row of
Custom Characters
~
The SEMIGRAPHICS FOUR mode uses an Internal "course graphics"

'f6 ~~
generator In which a rectangle (eight dots by twelve dots) IS diVided
Into four equal parts The luminance of each part IS determined by a
L3 L2

t---
corresponding bit on the VDG data bus The color of Illuminated parts
IS determined by three bits

6 Ll La \000
i -'-- Element

• L5
4
144H44~

L3 L,
• L1 LO
l4

} 0o,
Element
Ic, ICo IL51"1 L31 L,I L11 Lol
The SEMIGRAPHIC SIX mode IS Similar to the SEMIGRAPHIC FOUR
mode with the follOWing differences The eight dot by twelve dot rec-
tangle IS diVided Into SIX equal parts Color IS determined by the two
remaining bits

The COLOR GRAPHICS ONE mode uses a maximum of 1024 bytes of

•
display RAM In which one pair of bits speCifies one picture element

I c11eo Ic11eo IC11 Co Ic, /col

The RESOLUTION GRAPHICS ONE mode uses a maximum of 1024
bytes of display RAM In which one bit speCifies one picture element

Ic, ICo Ic, ICo IC11 Co Ic, Icol The COLOR GRAPHICS TWO mode uses a maximum of 2048 bytes
of display RAM In which one pair of bits speCifies one picture element

The RESOLUTION GRAPHICS TWO mode uses a maximum of 1536

-+1'1+- i. bytes of display RAM In which one bit speCifies one picture element
!L7 , '" II " ,
La T
The COLOR GRAPHICS THREE mode uses a maximum of 3072 bytes
of display RAM In which one pair of bytes speCifies one picture ele-
ment

The RESOLUTION GRAPHICS THREE mode uses a maximum of

-+j'h I I I , i 3072 bytes of display RAM In which one bit speCifies one picture ele-

L7 'C:t ment

The COLOR GRAPHICS SIX mode uses a maximum of 6144 bytes of

Ic, I Co IC11 Co IC11 Co IC11 Co I display RAM In which one pair 01 bits speCifies one picture element

The RESOLUTION GRAPHICS SIX mode uses a maximum of 6144

bytes of display RAM In which one bit speCifies one picture element

4-521
 MC6857· MC6847Y

FIGURE 19 - ALPHANUMERIC MODE (INTERNAL) FIGURE 20 - AVAILABLE ALPHANUMERICS

512 Characters (32 x 161
Typical Character
ooonoo(X;·
00000000
88~rl..I~88
oo;oooeo
ooeoooeo e -Dot
o -Dot Off
Lit HmB
-...
..a::==
_0
o = Inverted Character -

1 2 3 _4 5 _6 7
MD4= INV= D4
MD7= AS= D7
illuminated BaCkground,
Dark Character

8 _ 9 _ A _B _C _ 0 _ E _ F

88ro~~ 000
ra.
..81 0_ ABC 0 E F G H I J K l M N 0

§~~8§
HiiUH
1__ paR STU V W x Y Z I

00000000 " 5 ".

Inverted Normal _0123456789
Black Character Black Background
Orange or Green Orange or Green L@OOGGGGGOOOOOOOG
Background (Selectablel Character (Selectablel ,- 0 G Ci) 0 0 C!) G " 0 GOO. O • •
Character Source: .- • 0 • 0 0 0 0 • 00 • 0 • CD • •
Internal - 6 Bit ASCII Generator ROM On Chip or User Definable
External - Users ROM
7·0008000000 • • • • • 0

THE 128x64 COLOR GRAPHICS TWO ICG2) MODE -

The two limited graphic modes are Semlgraphlcs 4 and The 128 x 64 color graphiCS mode generates a display matnx
Semlgraphlcs 6 In Semlgraphlcs 4, the 8 x 12 dot character 128 elements Wide by 64 elements high. Each element may
block IS divided Into four pixels leach pixel IS four half-clocks be one of four colors A 2k x 8 display memory IS reqUired
by SIX scan lines). The four low-order bits 1000-0031 of each The display RAM IS accessed 32 times per honzontal line
Incoming byte of data select one of sixteen pOSSible Illumina- Each pixel equals two half-clocks by three scan lines
tion patterns while the next three bits 1004-006) determine

•
the color of the Illuminated elements. The most Significant THE 128 x 96 RESOLUTION GRAPHICS TWO IRG2)
bit IS unused Figure 21 shows the color and pattern selec- MODE - The 128 x 96 graphiCS mode generates a display
tions. In Semlgraphlcs 6 the 8 x 12 dot character block IS matnx 128 elements Wide by 96 elements high Each element
diVided Into SIX pixels, each four half-clocks by four scan may be either ON or OFF However, the entire display may
lines. The SIX low-order bits of each byte of incoming data be one of two colors selected by uSing the color set select
select one of 64 pOSSible Illumination patterns while the ess pin A 1 5k x 8 display memory IS reqUired The display RAM
Input and the high-order data bits 1006-0071 determine the IS accessed 16 times per honzontal line Each pixel equals
color of the Illuminated elements two half-clocks by two scan lines
The display window In malar mode 2 Ifull graphiCS) has a
less ngorous format than In major mode 1 The display THE 128 x 96 COLOR GRAPHICS THREE ICG3) MODE -
elements vary from one scan line to three scan lines In The 128 x 96 color graphiCS mode generates a display 128
height. The length of the display element IS either eight or elements Wide by 96 elements high Each element may be
sixteen half-penods wide Each display element IS diVided in- one of four colors A 3k x 8 display memory IS reqUired The
to four or eight pixels. The former corresponds to a full color display RAM IS accessed 32 times per honzontal line Each
mode while the latter a restncted color mode, like the pixel equals two half-clocks by two scan lines
semlgraphlcs modes, represents IlIumlnaliOn data When It IS
high the pixel IS Illuminated with the color chosen by the col- THE 128 x 192 RESOLUTION GRAPHICS THREE IRG3)
or set select leSSI pin. When It IS low the pixel IS black In MODE - The 128 x 192 graphiCS mode generates a display
the full color modes, pairs of data bits choose one of four matnx 128 elements Wide by 192 elements high Each ele-
colors In one of two color sets defined by the ess pin ment may be either ON or OFF, but the ON element may be
Oependlng on the state of the ess Pin, the area outSide the one of two colors selected With the color set select pin A
display window IS either green or buff The display formats 3k x 8 display memory IS reqUired. The display RAM IS ac-
and color selection for thiS major mode are summanzed In cessed 16 times per honzontal line Each pixel equals two
Figure 19. half-clocks by one scan line
THE 64x64 COLOR GRAPHICS ONE (CG1) MODE - THE 128x 192 COLOR GRAPHICS SIX ICG6) MODE -
The 64 x 64 color graphiCS mode generates a display matnx The 128x 192 color graphiCS mode generates a display 128
of 64 elements Wide by 64 elements high. Each element may elements Wide by 192 elements high Each element may be
be one of four colors. A lk x 8 display memory IS reqUired one of four colors. A 6k x 8 display memory IS reqUired The
The display RAM IS accessed 16 times per honzontal line. display RAM IS accessed 32 times per honzontal Ime Each
Each pixel equals four half-clocks by three scan lines pixel equals two half-clocks by one scan line

THE 128 x 64 RESOLUTION GRAPHICS ONE (RG1) THE 256 x 192 RESOLUTION GRAPHICS SIX (RG6)
MODE - The 128x 64 graphiCS mode generates a matnx MODE - The 256 x 193 graphiCS mode generates a display
128 elements Wide by 64 elements high. Each element may 256 elements Wide by 192 elements high. Each element may
be either ON or OFF. However, the entire display may be one be either ON or OFF, but the ON element may be one of two
of two colors, selected by uSing the color set select pin. A colors selected With the color set select prn A 6k x 8 display
lkx8 display memory IS reqUired. The display RAM IS ac- memory IS reqUired. The display RAM IS accessed 32 times
cessed 16 times per honzontal line Each pixel equals two per hOrizontal line. Each pixel equals one half-clock by one
half-clocks by three scan lines. scan Irne.

4-522
MC6847-MC6857Y

FIGURE 21 - SEMIGRAPHIC MODE ENCODING

lal Data and Display Formats

f.- Chroma __ I.., Luma----..J

Semigraphics 4

05 04

I CSS I I D7 I Os I 05 I 04 I D3 I 02 I 01 I DO I 03 O2
1-
f..-- Chroma I... Luma
Semigraphics 6
--I 01 Do 4L

Ibl Color Selection

Luma SG4 SG6
Color
ON 06 D5 04 CSS 07 De
0 X X X X X X Black
1 0 0 0 0 0 0 Green

•
1 0 0 1 0 0 1 Yellow
1 0 1 0 0 1 0 Blue
1 0 1 1 0 1 1 Red
1 1 0 0 1 0 0 Buff
1 1 0 1 1 0 1 Cyan
1 1 1 0 1 1 0 Magenta
1 1 1 1 1 1 1 Orange

FIGURE 22 - GRAPHIC MODE ENCODING

lal Data Format Ibl Display Format
1-
IJ..
3L CGl I 3L CG2

LI_D7'---_D...:6:..LI...:D5::....._D_4:....L..I_D.::.3_D...:2:..LI_D..;.1_ _
D::JOIColor Graphic ~--L--4-I~T/-2}-~~--~~lr ~--'--2-n~/2-}-.J.L......-'~T
,......{ - - - - - - C h r o m a - - - - - - J . o t l
..t..
I~~~~;~~~~hIC I I I I I I I I I
I 2L CG3
I D7 I D6 I D5 I ID4 D3 I D2 I I
D1 DO -;:RG1
'---'---2-n'-/21-.j-'----l\+T
I'" Luma --I 2 IT 12} ---l j.-lr
..:1..
I 2L RG2 r=:r:=r:::::::r:::::::J1 *G6
~~~~2~IT-/2~}~~~~lr 21T/21~ ~

c:r:r=~]I~I~IC=[1~I ~G3 c:J=::I::I::J1 +G6

21T/21.j ~ 1 IT/21.j 1+
Long Element Modes Short Element Modes
lei Color Selection
Resolution
Color Mode
CSS Border Color Mode
DN Color DN+1 DN Color
0 Green 0 Black 0 0 Green
0 Green 1 Green 0 1 Yellow
0 Green 1 Green 1 0 Blue
0 Green 1 Green 1 1 Red
1 Buff 0 Black 0 0 Buff
1 Buff 1 Buff 0 1 Cyan
1 Buff 1 Buff 1 0 Magenta
1 Buff 1 Buff 1 1 Orange

4-523
 MC6847e MC6847Y

TYPICAL SYSTEM IMPLEMENTATION rows The presence of row preset In major mode 1 serves as
The block diagram In Figure 23 shows how the VDG IS a flag for the beginning of a new element row DetectIOn of
related to other functional blocks In a typical system thiS Signal can Initiate a major mode SWitch from 1 to 2
(non-6883l. A negative row preset signal (Rl') generated by Display memory size IS a function of the display denSity
the VDG initializes the row scan counter for the external QUite often a graphiC display contains shapes that are several
character generator once every twelve scan lines, while the times larger than that of the display elements In the VDG
negative hOrizontal sync (~) acts as clock to thiS counter. ThiS IS particularly true of certain Video games Much of the
The negative field sync (rs) generates an Interrupt to the display consists of a fixed background The vertical size of a
MPU, signifying that the display memory can be updated display element can be doubled or quadrupled by Simply Ig-
without Interference with the VDG display function ThiS nOring the lowest order or the first two low order vertical ad-
signal must not be confused with the system vertical sync dresses, respectively, from the VDG. Reduction of address
signal. Field sync IS activated by the end of the vertical lines naturally leads to reduction In memory size Another
display window and deactIVated by the trailing edge of ver- method of memory reduction IS to store objects or object
tical sync. ThiS gives the MPU a total of thirty-two scan lines fragments In ROM and store their display addresses In the
or 2.03 ms to update the display memory. The MPU RAM portion of display memory Here, the larger the object
acknowledges the interrupt request from the VDG by bring- fragment, the greater the memory saving
Ing the negative memory select Input (MS) to the VDG low ASSOCIATED DEVICES
This puts the address bus output from the VDG Into hlgh-
Impedance state, thus relinquishing bus control to the MPU. MC6883 - SYNCHRONOUS ADDRESS MULTIPLEXER
The timing relationship of hOrizontal sync, row preset, and (SAM)
field sync are shown In Figures 7, 8, and 13. ThiS deVice, a linear bipolar companion to the MC6800 or
The display memory IS an element-· by-element map of the MC6809E (external clock Inputs), IS primarily a VDG
display window on the screen The VDG addresses the transparent-access controller. It allows the microprocessor

II display memory storage locations in succession and to load and store to VDG display memory ("screen RAM")
translates their contents Into luminance and chromlnance Without waiting for a blank screen Interval Figure 1 shows a
levels. The frequency of address update IS dependent on the tYPical system uSing the SAM and the MC6809E The in-
length of the display element. Recall that display elements In herent Interleaved direct memory accesses IIDMA) which
major mode 1 are four periods and major mode 2 are either occur, continuously keep the VDG updated With the proper
four or eight periods of the master clock. Data from the data (,ndependently of mode), as well as keeping the
display memory IS latched on every address transition. dynamiC memory (used as system memory With the M C6833)
Hence, the data for the first display element must be stable refreshed ThiS IS done through a IDMA process as well, dur-
four or eight periods before the hOrizontal display Window Ing the time the VDG does not need display data Ihorlzontal
depending on the display mode selected. ThiS timing reqUire- and vertical sync times)
ment IS Illustrated In Figure 6. In addition to being a transparent memory access and
Examination of Figures 21 and 22 reveal that all display dynamiC memory controller, the SAM also functions as an
elements Within major mode 1 are similar while those Within external clock generator for the MC6800/6809E (slight addi-
major mode 2 are largely diSSimilar Therefore, mode SWitch- tional circuitry IS reqUired for the MC6800).
Ing between alphanumeric modes and semlgraphlc modes
can be carned out freely Care must be taken, however, MC1372/1373 CHROMA/RF MODULATOR
when performing mode SWitching In major mode 2. The only The MC1372 IS a chromlnance phase-shift modulator With
compatible modes are between CG1 and RG1, and between bUilt In RF up-converter. The part may be used Without the
CG6 and RG6 Minor mode SWitching Within the same major RF modulator for chroma only, or the RF OSCillator may be
mode In a given element row can be achieved as long as It IS defeated and composite chromlnance and luminance can be
between compatible modes. It should be qUite apparent that obtained.
major mode SWitching on an element-by-element baSIS IS Im- The MC1373 IS an RF modulator only (Similar to the sec-
practical. It can be achieved, however, at the expense of ond half of the MC1372) and can be used to up-modulate
added component count The element formats in the VDG separate luma and chroma Signals at the receiver for high
lend themselves to major mode SWitching between element quality Video reception

4·524
 I,
I
MC6847· MC6847Y

FIGURE 23 - TYPICAL VDG SYSTEM

Game
Paddles

Dr-f,,------~~t_------------~------------------------~~----_.

Ar-~176~~'~2----~~----------------r-~
Addr
M68XX
Decoder
MPU Latch

iROb-----------------------------,
eLK
Display
i'S Mode Me Memory
eLK Control
ToTV Set

12

R~ y

II
MC6847
MC1372
B~Y VDC

eHB
0

RF
Tank INT/EXT

358 MHz A/S-----.,_~

f1S i'S m>
XTAL

External

~ ______
I-~'-;------------,l_l ~ow ~:~:~~:~~
~ ROM
0

Char Add

APPENDIX A FIGURE 24 - PROM MARKING

CUSTOM MC6847 ORDERING INFORMATION
The following information IS reqUired when ordering a
custom MCU This Information may be transmitted to
Motorola In the follOWing media
PROM(sl MCM2716s or MCM2708s
MOOS disk file
To Initiate a ROM pattern for the MCU It IS necessary to
first contact your local field service office, local sales person, 000 400
or your local Motorola representatIVe
xxx:= Customer 10

PROMs - The MCM2708 or MCM2716 type PROMs, pro-

grammed With the customer program (positive logiC sense VERIFICATION MEDIA
for address and datal, may be submitted for pattern genera- All original pattern media IPROMs or Floppy Dlskl are flied
tion The PROMs must be clearly marked to indicate which for contractual purposes and are not returned A computer
PROM corresponds to which address space (OOO-3FF HEXI, listing of the ROM code Will be generated and returned along
1400-7FFI or IOOO-7FF) See Figure 24 for recommended With a listing verification form The listing should be
marking procedure thoroughly checked and the venf,cat,on form completed,
After the PROM lsi are marked they should be placed In signed, and returned to Motorola The signed verification
conductive IC carners and securely packed Do not use form constitutes the contractual agreement for creation of
styrofoam the customer mask If deSired, Motorola will program a blank

4·525
 MC6857· MC6847Y

2716 EPROM (supplied by the customer! from the data file disk with a felt-tip pen The floppies are not to be returned by
used to create the custom mask to aid In the venf,catlon pro- Motorola as they are used for archival storage The minimum
cess M DOS system files must be on the disk as well as the ab-
ROM VERIFICATION UNITS solute binary object file (filename LO type of fllel An object
Ten MC6847s containing the customer's ROM pattern will file made from a memory dump uSing the ROLLOUT com-
be sent for program venf,cat,on These units will have been mand IS also admissable Consider submitting a source
made uSing the custom mask but are for the purpose of listing as well as the following files filename LX (EXOR-
ROM venf,cat,on only For expediency they are usually un- ciser'" loadable formatl and filename SA (ASCII Source
marked, packaged In ceramiC, and tested only at room Codel These files will of course be kept confidential and are
temperature and 5 volts These RVUs are Included In the used 11 to speed up the process In house If any problems
mask charge and are not production parts anse, and 21 to speed up our customer to factory Interface If
a user finds any software errors and needs assistance qUickly
FLEXIBLE DISKS from the factory representatives
The disk media submitted must be slllgie-sided, slngle- MDOS IS Motorola's Disk Operating System available on
denSity, 8-lnch, MDOS compatible flOPPies The customer development systems such as EXORcisers, or EXORsets,
must wnte the biliary file name and company name on the etc

•
FIGURE A-2

Customer Name ___________________________________________________________________________________

Address ________________________________________________________________________________________

City ___________________________________________________________________________________________

Phone 1 _________ I___________________ State _______________________--'-Z,p _______________________

Contact Ms/Mr ___________________________________________________________________________________

Customer Part Number _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___

Pattern Media
2708 PROM
2716 PROM

MOOS Disk
INote 21 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Other (NOTE Other media requires prior factory approval)

Signature

Title __________________________________________________

4-526
 MC6RSO
® MOTOROLA
11_0 MHz)
MC68ASO
11.5 MHz)
MCG8BSO
12.0 MHz)

ASYNCHRONOUS COMMUNICATIONS INTERFACE

ADAPTER (ACIA) MOS
IN-CHANNEL, SILICON-GATE)
The MC6850 Asynchronous Communlcalions Interface Adapter pro-
vides the dRta formatting and control to Interface senal asynchronous ASYNCHRONOUS
data communications information to bus organized systems such as the COMMUNICATIONS INTERFACE
MC6800 Microprocessing Unit
ADAPTER
The bus Interface of the MC6850 Includes select, enable, read/write,
Interrupt and bus Interface logic to allow data transfer over an 8-blt
bidirectional data bus The parallel data of the bus system IS senally
transmitted and received by the asynchronous data Interface, with pro
per formatting and error checking The functional configuration of the
ACIA IS programmed via the data bus dunng system Initialization A S SUFFIX
programmable Control Register provides vanabll3 word lengths, clock lE:.RDIP PAll<..!-I.("E:
divIsion ratios, transmit control, receive control, and Interrupt control. LASt- 623
For penpheral or modem operalion, three control lines are provided
These lines allow the ACIA to Interface directly with the MC6860L
0-600 bps digital modem
• 8- and 9-Blt Transmission P SUFFIX

•
• Optional Even and Odd Panty PLASTIC PACKAGE
CASE 700
• Panty, Overrun and Framing Error Checking
• Programmable Control Register
• Oplional ~ 1, -16, and - 64 Clock Modes

~
-
• Up to 1 0 Mbps Transmission
- -- l SUFFIX
• False Start Bit Deletion
• Penpheral/ Modem Control Functions
II CERAMIC PACKAGE
\ I CASE 716
• Double Buffered
• One- or Two-Stop Bit Operation

PIN ASSIGNMENT
MC6850 ASYNCHRONOUS COMMUNICATIONS INTERFACE ADAPTER
BLOCK DIAGRAM
VSS eTS
Rx Data i5Co
Ax ClK DQ

Data
Tx elK D1
TransmIt
Data Bus Bus
Data RTS D2
Buffers
Tx Data D3
iiiQ D4
Receive
Data eso D5
eS2 D6
eSl D7
Address
Selection
Control RS
and
and
Control
Interrupt Perlpherall Vee 13 A/iN
Modem
Control

4-527
 MC6850-MC68A50-MC68850

MAXIMUM RATINGS
Characteristics Symbol Value Unit This device contains circuitry to protect the
Supply Voltage Vce - 03 to + 70 V Inputs against damage due to high static
Input Voltage Y,n - 03 to + 70 V voltages or electnc fields, however, It IS ad-
Operating Temperature Range
vised that normdl precautions be taken to
TL to TH
MC6850, MC68A50, MC68B50 aVOid application of dny voltage higher than
TA 0 to 70 'c
MC6850C, MC68A50C, MC68B50C -40 to +85 maximum rated voltages to this hlgh-
Impedance CirCUit Reliability of operation IS
Storage Temperature Range Tstg 55 to +150 "C enhanced If unused Inputs are tied to an ap-
pr0prlate logic voltage level (e 9 , either VSS
THERMAL CHARACTERISTICS or VCCI
Characteristic Symbol Value UOit
Thermal Resistance
Plastic 120
Ceramic °JA 60 "c/W
Cerdlp 65

POWER CONSIDERATIONS

The average chip-Junction temperature, T J, In °C can be obtained from

TJ=TA+IPD o8JAI III

•
Where
TA=Amblent Temperature, °C
8JA= Package Thermal Resistance, JunctlOn-to-Amblent, °C/W
PD= PINT+ PPORT
PINT=ICCxVCc. Watts - Chip Internal Power
PPORT= Port Power DIssipatIOn, Watts - User Deterrnlned
For most applications PPORT<C PINT and can be neglected PPORT may become Significant If the device IS configured to
drive Darlington bases or sink LED loads.
An approximate relationship between PD and T J Ilf PPORT IS neglected I IS
PD= K- IT J+ 273°CI {21
Solving equations 1 and 2 for K gives.
K = PDolT A + 273°CI + 8JA o PD 2 131
Where K IS a constant pertaining to the particular part K can be determined from equation 3 by measuring PD lat equillbrluml
for a known T A- USing thiS value of K the values of PD and T J can be obtained by solving equations 111 and 121 IteratIVely for any
value of T A

DC ELECTRICAL CHARACTERISTICS IVce~ 5 0 Vdc +

- 5%, VSS ~ 0, TA ~ TL to TH unless otherwise noted I
Characteristic Symbol Min Typ Max Unit
Input High Voltage VIH VSS+20 - VCC V
Input Low Voltage VIL VSS-03 - VSS +0 8 V
Input Le3kage Current R/W, CSO, CS1, C~ Enable
lin - 10 25 ~A
IV,n =Ot0525VI RS, Rx D, Rx C, CTS, DCD
Three-State IOff Statellnput Current DO-D7
ITS I - 20 10 ~A
IV,n~OA to 2 4 VI
Output H!gh Voltage DO-D7
II Load = -205 ~A, Enable Pulse Width <25 ~sl VOH VSS+24 - - V
IILoad= -l00~A, Enable Pulse Wldth<25~sl Tx Data, RTS VSS+24 - -
Output Low Voltage IILoad-1 6 mA, Enable Pulse Wldth<25 ~sl VOL VSS+O 4 V
Output Leakage Current {Off Statel IVOH = 24 VI IRO ILOH - 10 10 ~A
Internal Power DISSipation {Measured at TA=TL) PINT - 300 525 mW
Internal Input Capacitance
IV In =0,TA=25°C,f=10MHzl DO-D7 C,n - 10 125 pF
E, Tx CLK, Rx CLK, R/W, RS, Rx Data, CSO, CS1, CS2, CTS, DCD - 70 75
Output Capacitance RTS, Tx Data - - 10
Cout pF
{VIn=O, TA=25°C,f=1 OMHzl IRO - - 50

4·528
MC6850-MC68A50-MC68B50

SERIAL DATA TIMING CHARACTERISTICS

MC68tiO MC68A50 MC88B60
Charactaristic Symbol Unit
Min Max Min Max Min Max
Data Clock Pulse Width, Low + 16, + 64 Modes
PWCL
600 - 450 - 280 - ns
(See Figure 1) + 1 Mode 900 - 650 - 500 -
Data Clock Pulse Width, High + 16, + 64 Modes 600 - 450 - 280 -
(See Figure 2) +1 Mode PWCH
900 - 650 - 500 - ns

Data Clock Frequency + 16, + 64 Modes

fC
- 08 - 10 - 15 MHz
+1 Mode - 500 - 750 - 1000 kHz
Data Clock-to-Data Delay for Transmitter (See Figure 3) trOD - 600 - 540 - 400 ns
Receive Data Setup Time I See Figure 4) +1 Mode tRDS 250 100 30 ns
Receive Data Hold Time (See Figure 5) +1 Mode tRDH 250 - 100 - 30 - ns
Interrupt Request Release Time (See Figure 6) tlR - 12 - 09 - 07 p.s
Request-to-Send Delay Time (See Figure 6) tRTS - 560 - 480 - 400 ns
Input Rise and Fall Times lor 10% of the pulse Width If smaller) tr,tf - 10 - 06 - 0.25 PoS

F)GURE 1 - CLOCK PULSE W)DTH, LOW-STATE FIGURE 2 - CLOCK PULSE WIDTH, HIGH-STATE

Tx elk

I
Tx elk
0" Rx elk
Rx elk

FIGURE 4 - RECEIVE DATA SETUP T)ME

FIGURE 3 - TRANSMIT DATA OUTPUT DELAY (+1 Mode)

"o.=1'----~
Tx elk

r-- tROS-----:--

Tx Data -------.X+J=------
'Too

Rx Clock ¥ "-

FIGURE 5 - RECEIVE DATA HOLD TIME FIGURE 6 - REQUEST-TO-SEND DELAY AND

(+ 1 Mode) INTERRUPT-REQUEST RELEASE TIMES

Enable
Rxel\(

RTS
Ax Data

IRQ

Note Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 20 volts, unless otherwise noted

4-529
 MC6850e MC68A50e MC68B50

BUS TIMING CHARACTERISTICS (See Notes 1 and 2 and Figure 71

ldent. MC6850 MC68A50 MC68B50
Characteristic Symbol Unit
Number Min Max Min Max Min Max
1 Cycle Time tcyC 1.0 10 067 10 0.5 10 I's
2 Pulse Width. E Low PWEL 430 9500 280 9500 210 9500 ns
3 Pulse Width. E High PWEH 450 9500 280 9500 220 9500 ns
4 Clock Rise and Fall Time tr,tf - 25 - 25 - 20 ns
9 Address Hold Time tAH 10 - 10 10 - ns
13 Address Setup Time Before E tAS 80 - 60 - 40 - ns
14 Chip Select Setup Time Before E tcs 80 - 60 - 40 - ns
15 Chip Select Hold Time tCH 10 - 10 - 10 - ns
18 Read Data Hold Time tDHR 20 100 20 100 20 100 ns
21 Wnte Data Hold Time tDHW 10 - 10 - 10 - ns
30 Output Data Delay Time tDDR - 290 - 180 - 150 ns
31 Input Data Setup Time tDSW 165 - 80 - 60 - ns

FIGURE 7 - BUS TIMING CHARACTERISTICS

I r-~--------------~~f~r--------(3~------~

R/VV,Address--~-+~~ri~~~~~------~~~~----~t-----------------------------~-+~~~

(NonMMuxed) ____~~~~~~~~~-------L~~~----~~--------------------------------~~~~~

Read Data
Non-Muxed
-----+--.....D---------------~~~~~~~~~~--------------~~:::::~=---~~--t1--~~
MPU Read Data Non-Muxed

Write Data -----'----.L. MPU Write Data Non-Muxee'

Muxed r---------------~r-------------------------------~::==:s~------~~~--t
Voltage levels shown are VL'!SO 4 V, VHi2:2 4 V, unless otherwise specified
2 Measurement POints shown are 0 8 V and 2 0 V. unless otherWise specified

FIGURE 8 - BUS TIMING TEST LOADS

Load A load B
100-07. RTS. Tx Datal IIRO Onlvl
sov

Test Pomt <r-+-1~--joI---+ MMD6150

C R
or ~4UIV

MMD7000
or Equ IV
Test POint

-t 3 kll
50V

I'00PF
C = 130 pF for DO 07 R =: 11.7 kH for 00-07

RTS
..: 30 pF for and Tx Data = 24 kn for RTSand Tx Data

4·530
 FIGURE 9 - EXPANDED BLOCK DIAGRAM

Transmit Clock 4 - - - - - - - - - - - - - - - - -.... .,1--;,:::1

Read/Wnte 13
ChlpSelectO 8 Transmit
Chip Select 1 10 Data 6 Transmit Data
Chip Select 2 9 Register
Register Select 11

b=~=~~~~;2----- 24 Clear-to-Send
DO 22
5tatus
0121 Register

D220 7 Interrupt Request

L _____.....~=====~__ 23 Data Carner Detect

0319

0418

0517
5 Request-to-Send
0616

0715 Control
Register

I
Vcc= Pin 12 Receive Receive
Data Shift 2 Receive Date
VSS=Pln1 Register Register

Receive Clock 3 - - - - - - - - - - - - - - - - -....L~=-~

DEVICE OPERATION power-on reset IS released by means of the bus-programmed

master reset which must be applied prior to operating the
At the bus mterface, the ACIA appears as two addressable ACIA. After master resetting the ACIA, the programmable
memory locations. Internally, there are four registers. two Control Register can be set for a number of options such as
read-only and two write-only registers The read-only variable clock divider ratiOS, variable word length, one or two
registers are Status and Receive Data; the write-only stop bitS, panty (even, odd, or nonel, etc
registers are Control and Transmit Data The serial Interface
consists of serial mput and output lines With Independent TRANSMIT
clocks, and three peripheral/modem control lines. A typical transmitting sequence consists of readmg the
ACIA Status Register either as a result of an mterrupt or m
POWER ON/MASTER RESET the ACIA's turn m a polling sequence. A character may be
The master r.eset (CRO, CR1) should be set dUring system written Into the Transmit Data Register If the status read
Initialization to Insure the reset condition and prepare for pro- operation has Indicated that the Transmit Data Register IS
gramming the ACIA functional configuratIOn when the com- empty. ThiS character is transferred to a Shift Register where
mUnications channel IS reqUired. DUring the first master It is serialized and transmitted from the Transmit Data output
reset, the IRO and RTS o~ts are held at level 1 On all preceded by a start bit and followed by one or two stop bits
other master resets, the RTS output can be programmed Internal panty (odd or even) can be optionally added to the
high or low With the IRO output held high. Control bits CR5 character and Will occur between the last data bit and the
and CR6 should also be programmed to defme the state of first· stop bit. After the first character IS written m the Data
RTS whenever master reset IS utilized. The ACIA also con- Register, the Status Register Can be read again to check for a
tams mternal power-on reset logic to detect the power line T -ansmit Data Register Empty conditIOn and current
turn-on transition and hold the chip m a reset state to pre- peripheral status. If the register IS empty, another character
vent erroneous output transitions prior to Initialization ThiS can be loaded for transmission even though the first
Circuitry depends on clean power turn-on transitions. The character IS In the process of bemg transmitted (because of

4-531
 double buffering). The second character Will be automatical- turned off and the MPU wntes Into a selected register.
ly transferred Into the Shift Register when the first character Therefore, the Read/Write signal IS used to select read-only
transmission IS completed. This sequence continues until all or wnte-only regIsters WIthin the ACIA.
the characters have been transmitted.
Chip Select (CSO, CS1, CS2) - These three hlgh-
RECEIVE Impedance TTL-compatible input lines are used to address
Data IS received from a peripheral by means of the Receive the ACIA The ACIA is selected when CSO and CS 1 are hIgh
Data Input A dlvlde-by-one clock ratio IS provided for an ex- and CS2 IS low. Transfers of data to and from the ACIA are
ternally synchronized clock (to ItS data) while the dlvide- then performed under the control of the Enable SIgnal,
by-16 and 64 ratios are provided for Internal synchronIZation Read/Write, and RegIster Select
Bit synchronization In the dlvlde-by-16 and 64 modes IS in-
Itiated by the detection of 8 or 32 low samples on the reCillve Register Select (RS) - The RegIster Select line IS a hlgh-
line In the dlvlde-by-16 and 64 modes respectively False start Impedance Input that IS TTL compatible. A high level IS used
bit deletion capability Insures that a full half bit of a start bit to select the Transmit/ ReceIve Data RegIsters and a low
has been received before the Internal clock IS synchronIZed level the Control/ Status Registers. The Read/Write signal
to the bit time As a character IS being received, parity (odd line IS used 10 conjunction WIth Register Select to select the
or even) Will be checked and the error IndicaliOn will be read-only or write-only register In each register pair.
available In the Status Register along With framing error,
overrun error, and Receive Data RegIster full. In a tYPIcal Interrupt Request (IRQ) - Interrupt Request is a TTL-
receiving sequence, the Status Register IS read to determine compatible, open-drain (no Internal pullup), active low out-
If a character has been received from a peripheral. If the put that is used to Interrupt the MPU The IRQ output re-
ReceIver Data Register IS full, the character IS placed on the mains low as long as the cause of the Interrupt IS present and
8-blt ACIA bus when a Read Data command IS received from the appropriate Interrupt enable WIthin the ACIA IS set The

II
the MPU. When parity has been selected for a 7-bit word (7 IRQ status bit, when high, Indicates the iRO output IS In the
bits plus parity), the receIver striPS the parity bIt (07 = 0) so active state.
that data alone is transferred to the MPU. ThiS feature Interrupts result from condItIons In both the transmitter
reduces MPU programming. The Status Register can con- and receIver sections of the ACIA The transmitter sectIOn
linue to be read to determine when another character IS causes an Interrupt when the Transmitter Interrupt Enabled
available In the ReceIve Data RegIster The receIver IS also condition IS selected (CR5eCR6), and the Transmit Data
double buffered so that a character can be read from the Register Empty (TDRE) status bIt IS high. The TORE status
data regIster as another character IS being receIved In the bIt Indicates the current status of the TransmItter Data
shIft register The above sequence continues until all RegIster except when inhibIted by Clear-ta-Send (CTS) be-
characters have been received. Ing hIgh or the ACIA beIng maIntained In the Reset condi-
tlon. The Interrupt IS cleared by wrlling data Into the
Transmit Data Register. The Interrupt IS masked by dIsabling
the Transmitter Interrupt via CR5 or CRB or by the loss of
INPUT/OUTPUT FUNCTIONS CTS whIch InhIbits the TORE status bit The Receiver sec-
tion causes an Interrupt when the ReceIver Interrupt Enable
ACIA INTERFACE SIGNALS FOR MPU IS set and the Receive Data RegIster Full (RDRF) status bIt IS
The ACIA Interfaces to the M6800 M PU With an 8-blt hIgh, an Overrun has occ"rred, or Data Carner Detect (DCD)
bidirectional data bus, three chip select lines, a regIster select has gone hIgh An Interrupt resultIng from the RDRF status
line, an Interrupt request line, read/Write line, and enable bIt can be cleared by reading data or resetting the ACIA. In-
line These SIgnals permit the MPU to have complete control terrupts caused by Overrun or loss of OCD are cleared by
over the ACIA. readIng the status regIster after the error conditIon has oc-
curred and then reading the Receive Data Register or reset-
ACIA Bidirectional Data (00-07) - The bIdirectional data ting the ACIA The receIver Interrupt IS masked by resetling
lines (DO-D7l allow for data transfer between the ACIA and the Receiver Interrupt Enable.
the MPU. The data bus output drivers are three-state deVices
that remain In the hIgh-Impedance (off) state except when CLOCK INPUTS
the MPU performs an ACIA read operatIon. Separate hIgh-Impedance TTL-compatible Inputs are pro-
Vided for clocking of transmItted and receIved data Clock
ACIA Enable (E) - The Enable Signal, E, IS a hlgh- frequencIes of 1, 16, or 64 times the data rate may be
Impedance TTL-compatIble Input that enables the bus In- selected.
put! output data buffers and clocks data to and from the
ACIA. ThIS Signal WIll normally be a derivatIve of the MC6800 Transmit Clock (Tx ClK) - The Transmit Clock Input IS
<1>2 Clock or MC6809 E clock. used for the clocking of transmItted data. The transmItter In-
Itiates data on the negative transItIon of the clock.
Read/Write (R/W) - The Read/Wnte line IS a hlgh-
Impedance Input that is TTL compatIble and IS used to con- Receive Clock (Rx ClK) - The Receive Clock Input IS
trol the directIon of data flow through the ACIA's Input/ out- used for synchronization of receIved data. (In the -1 mode,
put data bus Interface. When Read/Write is hIgh (MPU Read the clock and data must be synchronized externally) The
cycle), ACIA output drivers are turned on and a selected receiver samples the data on the POSItive tranSItion of the
regIster is read When It IS low, the ACIA output drivers are clock

4-532
MC6850-MC68A50-MC68B50

SERIAL INPUT/OUTPUT LINES ACIA REGISTERS

Receive Data (Rx Data) - The Receive Data line IS a hlgh- The expanded block diagram for the ACIA Indicates the in-
Impedance TTL-compatible Input through which data IS ternal registers on the chip that are used for the status, con-
received in a senal format Synchronization with a clock for trol, receiving, and transmitting of data. The content of each
detection of data IS accomplished Internally when clock rates of the registers IS summanzed In Table 1
of 16 or 64 times the bit rate are used

Transmit Data (Tx Data) - The Transmit Data output line TRANSMIT DATA REGISTER (TOR)
transfers senal data to a modem or other penpheral. Data IS wntten In the Transmit Data Register dunng the
negative transition of the enable (E) when the ACIA has been
PERIPHERAL/MODEM CONTROL addressed with RS high and R/W low. Wntlng data Into the
The ACIA Includes several functions that permit limited register causes the Transmit Data Register Empty bit In the
control of a penpheral or modem. The functions Included are Status Register to go low. Data can then be transmitted If
Clear-to-Send, Request-to-Send and Data Carner Detect the transmitter IS Idling and no character IS being transmit-
ted, then the transfer will take place within l-blt time of the
Clear-to-Send (CTS) This high-Impedance TTl- trailing edge of the Wnte command If a character IS being
compatible Input provides automatic control of the transmit- transmitted, the new data character will commence as soon
ting end of a commUnications link via the modem Clear-to- as the prevIous character IS complete The transfer of data
Send active low output by inhibiting the Transmit Data causes the Transmit Data Register Empty (TORE) bit to in-
Register Empty (TORE) status M. dicate empty

Request-to-Send (RTS) - The Requesl-lo-Send output RECEIVE DATA REGISTER (RDR)

II
enables the MPU to control a penpheral or modem via the Data IS automatically transferred to the empty Receive
data bus. The RTS output corresponds to the state of the Data Register (RDR) from the receiver desenalizer (a shift
Control Register bits CR5 and CR6 When CR6 = 0 or both register) upon receiving a complete character ThiS event
CR5 and CR6 = 1, the RTS output IS low (the active state) causes the Receive Data Register Full bit (RDRF) In the
This output can also be used for Data Terminal Ready (DTR) status buffer to go high (full). Data may then be read
through the bus by addreSSing the ACIA and selecting the
Data Carrier Detect (DCD) - ThiS high-Impedance TTl- Receive Data Register with RS and R/W high when the
compatible Input provides automatic control, such as In the ACIA IS enabled. The non-destructive read cycle causes the
receiving end of a commUnications link by means of a RDRF bit to be cleared to empty although the data IS re-
modem Data Carner Detect output. The DCD Input Inhibits tained In the RDR. The status IS maintained by RDRF as to
and initializes the receiver section of the ACIA when high A whether or not the data IS current. When the Receive Data
low-to-hlgh transition of the Data Carner Detect Initiates an Register IS full, the automatic transfer of data from the
Interrupt to the MPU to indicate the occurrence of a loss of Receiver Shift Register to the Data Register IS inhibited and
carner when the Receive Interrupt Enable bit IS set The the RDR contents remain valid With ItS current status stored
Rx ClK must be running for proper DCD operation In the Status Register

TABLE 1 - DEFINITION OF ACIA REGISTER CONTENTS

Buffer Address

Data RS. R!W RS. R!W RS. RlW RS. R!W

Bus Transmit Receive
Line Data Data Control Status
Number Register Register Register Register
(Wr Ite Only) (Read Only) (Wnte Only) (Read Onlyl
Data Bit O· Data 81t a Counter DIvide Receive Data Register
Select 1 (CRO~ Full JRDRFl
Data Sit 1 Data 81t 1 Counter DIvide Transmit Data Register
Select 2 leA 1) f::mpty ITORE)

Datd Sit 2 Data 8,t 2 Word Select 1 Data Carner Detect

(CR2) (OCD)

Data 81t 3 D.ata 81t 3 Word Select 2 Clear to Send

(eR3) (CTS)
Data 81t 4 Data 81t 4 Word Select 3 Framing Error
(CR4) (F E)

Data Bit 5 Data Bit 5 Transrnlt Control 1 Receiver Overrun

(CR5) (OVRNl
Data Bit 6 Data Bit 6 Transmit Control 2 Panty Error (PEl
(CR6)
Data Bit 7'" Data Bit 7" Receive Interrupt Interrupt Rel.juest
Enable (CR7) Iif~(5)

• Leading bit LSB = Bit 0

•• Data bit will be zefO In 7 bit plus parity modes
••• Data bit IS "don't care" In 7 hit plus panty modes

4·533
 CONTROL REGISTER STATUS REGISTER
The ACIA Control Register consists of eight bits of wnte- Information on the status of the ACIA is available to the
only buffer that are selected when RS and R/W are low. This MPU by reading the ACIA Status Register ThiS read-only
register controls the function of the receiver, transmitter, in- register IS selected when RS IS low and R/W IS high. Infor-
terrupt enables, and the Request-to-Send peri- mation stored In thiS register Indicates the status of the
pheral/ modem control output. Transmit Data Register, the Receive Data Register and error
logiC, and the penpheral/modem status Inputs of the ACIA.
Counter Divide Select Bits (CRO and CR1) - The Counter
D,v,de Select Bits (CRO and CRll determine the divide ratios Receive Data Register Full (RDRF), Bit 0 - Receive Data
utilized In both the transmitter and receiver sections of the Register Full indicates that received data has been trans-
ACIA. Additionally, these bits are used to prOVide a master ferred to the Receive Data Register RDRF IS cleared after an
reset for the ACIA which clears the Status Register (except MPU read of the Receive Data Register or by a master reset.
for external conditions on CTS and DCD) and Initializes both The cleared or empty state indicates that the contents of the
the receiver and transmitter. Master reset does not affect Receive Data Register are not current. Data Carner Detect
other Control Register bits Note that after power-on or a being high also causes RDRF to indicate empty
power fali'! restart, these bits must be set hijlh to reset the
ACIA. After resetting, the clock diVide ratio may be selected. Transmit Data Register Empty (TORE), Bit 1 - The
These counter select bits provide for the following clock Transmit Data Register Empty bit being set high ,nd,cates
divide ratios: that the Transmit Data Register contents have been trans-
ferred and that new data may be entered The low state In-
CRI CRO Function dicates that the register IS full and that transmission of a new
a a +1 character has not begun since the last write data command
a 1 +16

I 1
1
a
1
+64
Master Reset

Word Select Bits (CR2, CR3, and CR4) - The Word

Select bits are used to select word length, panty, and the
number of stop bits. The encoding format IS as follows:
Data Carrier Detect (DCD), Bit 2 - The Data Carner
Detect bit Will be high when the DCCi input from a modem
has gone high to indicate that a carner IS not present. ThiS bit
gOing high causes an Interrupt Request to be generated
when the Receive Interrupt Enable IS set It remains high
after the l5CD Input IS returned low until cleared by first
CM CR3 CR2 Function reading the Status Register and then the Data Register or
a a a 7 Blts+Even Panty+2 Stop Bits until a master reset occurs. If the DCD InPut remains high
a
a ,, a 1
a
7 Bits + Odd Parny+2 Stop Bits
7 Blts+ Even Panty+ 1 Stop Bit
after read status and read data or master reset has occurred,
the interrupt IS cleared, the DCD status bit remains high and
,, a
0 1
a
7 Bits + Odd Panty + 1 Stop Bit
8 BltH 2 Stop Bits
will follow the l5CD Input.

, a,, 1
a
8 ~its +' Stop Bit
B Bits + Even parity + 1 Stop Bit
Clear-to-Send (ffi), Bit 3 - The Clear-to-Send bit In-
dicates the state of the Clear-to-Send Input from a modem.
1 1 B Ejlts+ Odd Parny+ 1 Stop Bit A low ffi indicates that there is a Clear-to-Send from the
modem. In the high state, the Transmit Data Register Empty
Word length, Parity Select, and Stop Bit changes are not
bit IS Inhibited and the Clear-to-Send status bit Will be high
buffered and therefore become effective immediately.
Master reset does not affect the Clear-to-Send status bit.
Trensmitter Control Bits (CR6 and CRe) - Two Transmit-
Framing Error (FE), Bit 4 - Framing error indicates that
ter Control bits provide for the control of the interrupt from
the received character IS Improperly framed by a start and a
the Transmit Data Register Empty condition, the Request-to-
stop bit and is detected by the absence of the first stop bit.
Send (m) output, and the transmission of a Break level
ThiS error indicates a synchrOnization error, faulty transmis-
(space). The following encoding format is used:
sion, or a break condition. The framing error flag IS set or
reset dUring the receive data transfer time. Therefore, thiS er-
CRS CR6 Function
ror Indicator is present throughout the time that the
a
a ,
a ~=Iow, Transmitting Interrupt Disabled.
RTS= low, Transmitting Interrupt Enabled.
associated character IS available.
1
1 ,
a ~ = high, Transmitting Interrupt Disabled
RTS = low, Transmits a Break level on the Receiver Overrun (OVRN), Bit 6 - Overrun IS an error flag
that indicates that one or more characters In the data stream
Transmit Data Output Transmitting Inter-
rupt Disabled, were lost. That IS, a character or a number of characters
were received but not read from the Receive Data Register
Receive Intarrupt Enable Bit (CR7) - The follOWing inter- (RDR) pnor to subsequent characters being received. The
rupts Will be enabled by a high level in bit position 7 of the overrun condition begins at the midpOint of the last bit of the
Control Register (CR7): Receive Data Register Full, Overrun, second character received in succession without a read of
or a low-to-hlgh transition on the Data Carrier Detect (DCD) the RDR haVing occurred. The Overrun does not occur In the
signal line. Status Register until the valid character pnor to Overrun has

4·534
M~MamA~MC~BOO

been read. The RDRF bit remains set until the Overrun IS character IS In the RDR. If no panty IS selected, then both the
reset. Character synchronization IS maintained during the transmitter panty generator output and the receiver partly
Overrun condition. The Overrun Indication IS reset after the check results are inhibited.
reading of data from the Receive Data Register or by a
Master Reset. Interrupt Request (lRQI, Bit 7 - The IRQ bit indicates the
state of the TRQ output. Any interrupt c.:lndltlon with Its ap-
Parity Error (PEl, Bit 6 - The panty error flag indicates plicable enable will be Indicated in this status bit. Anytime
that the number of highs (ones) in the character does not the iRQ output is low the 'iRObit will be high to Indicate the
agree with the preselected odd or even parity. Odd panty is Interrupt or service request status. IRQ is cleared by a read
defined to be when the total number of ones IS odd. The operation to the Receive Data Register or a write operation
parity error indication Will be present as long as the data to the T r&nsmit Data Register.

4-535
 MC6852
®
(1.0 MHzl

MOTOROLA MC68AS2
(1.5 MHzl
MC68BS2
(2.0 MHz)

SYNCHRONOUS SERIAL DATA ADAPTER (SSDA) MOS

IN-CHANNEL, SILICON-GATE)
The MC6852 Synchronous Serial Data Adapter provides a bidirec-
tional serial interface for synchronous data information Interchange. It
contains Interface logic f')r simultaneously transmitting and receiving
SYNCHRONOUS SERIAL
standard synchronous communications characters In bus organized DATA ADAPTER
systems such as the M6800 Microprocessor systems.
The bus Interface of the MC6852 Includes select, enable, read/write,
Interrupt, and bus Interface logiC to allow data transfer over an 8-blt bi-
directional data bus The parallel data of the bus system IS sen ally

~J
transmitted and received by the synchronous data Interface with syn-
chronization, fill character Insertion/deletion, and error checking The
functional configuration of the SSDA IS programmed via the data bus 24 P SUFFIX
dunng system initialization. Programmable control registers proVide . PLASTIC PACKAGE
control for vanable word lengths, transmit control, receive control, syn- CASE 709
chronization control, and Interrupt control Status, timing and control
lines proVide penpheral or modem control.
TYPical applications Include floppy disk controllers, cassette or car-
tndge tape controllers, data communications terminals, and numencal
control systems.

I
• Programmable Interrupts from Transmitter, Receiver, and Error
Detection LogiC
• Character Synchronization on One- or Two-Sync Codes
• External Synchronization Available for Parallel-Senal Operation
• Programmable Sync Code Register

~~'
• Up to 1.5 MHz TransmiSSion
• Penpheral/ Modem Control Functions
• Three Bytes of FIFO Buffenng on Both Transmit and Receive
• 7-,8-, or 9-Blt Transmission
S SUFFIX
• Optional Even and Odd Panty . CERDIP PACKAGE
• Panty, Overrun, and Underflow Status CASE 623

SYNCHRONOUS SERIAL DATA ADAPTER BLOCK DIAGRAM

PIN ASSIGNMENT

Addressl Control
and Interrupt VSS CTS
Rx Data DCD

Peripheral! Rx CLK DO
Modem Tx CLK D1
Control
SM/DTR D2
Tx Data D3
ReceIve

Data
Data iRO D4
Bus TUF D5
1/0 Transmit
RESET D6
Data
CS D7
RS

VCC R/W

4-536
MC6852- MC68A52- MC68B52

MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage Vcc -03to+70 V
Input Voltage Vin 03to +70 V This device contains circuitry to protect the in-
Operating Temperature Range h toTH puts agamst damage due to high static voitages
MC6852, MC68A52, MC68B52 o to + 70 or electnc fields, however, It IS advsled that nor-
MC6852C, MC68A52C TA -40 to +85 °c mal precautions be taken to avoid application of
any voltage higher than maximum-rated voltages
Storage Temperature Range Tstg -55 to +150 °c to this high-Impedance CirCUit Reliability of
operation IS enhanced If unused Inputs are tled to
THERMAL CHARACTERISTICS an appropriate logic voltage level Ie g , either
VSS or VCC)
Characteristic Symbol Value Unit
Thermal Resistance
Plastic Package 120
Ceramic Package 8JA °C/W
60
Cerdlp Package 65

POWER CONSIDERATIONS

The average chip-Junction temperature, T J, 10 °C can be obtained from'

•
T J=TA+ (POoOJA) (1)
Where
TAEAmblent Temperature, °C
0JA. Package Thermal Resistance, Junctlon-to-Amblent, °C/W
PO-PINT+ PPORT
PINT"" ICC x VCC, Watts - Chip Internal Power
PPORTE Port Power DIssipatIOn, Watts - User Determined
For most applicatIOns PPORT<C PINT and can be neglected PPORT may become Significant If the device Ie configured to
drive Darlington bases or Sink LED loads
An approximate relatIOnship between Po and T J (,f PPORT IS neglected) IS
PO= K- IT J + 273°C) (2)
SolVing equations 1 and 2 for K gives'
K= POo(TA+273°C) +OJAo P0 2 (3)
Where K 15 a constant pertaining to the particular part K can be determined from equation 3 by measuring Po (at eqUilibrium)
for a known T A USing thiS value of K the values of Po and T J can be obtained by solVing equatIOns (1) and (2) Iteratively for any
value of TA.

DC ELECTRICAL CHARACTERISTICS IVcC-5 - 0 Vdc ±6% vSs-O - TA=TL to TH unless otherwise noted)
Charactaristic Symbol Min Typ Max Unit
Input High Voltage VIH VS$+20 - - V
Input Low Voltage VIL - - VSS+O 8 V
Input Leakage Current Tx CLK, Rx CLK, Rx Data, Enable,
IV,n=Oto 5 25 V) REm, RS, R/Vii, CS, i5Cl'i, CTS lin - 10 25 "A
Three-State 10ff-State) Input Current 00-07
IV,n=O 4 to 2 4 V, VCC=5 25 V) liZ - 20 10 "A
Output High Voltage
II Load = - 205 "A, Enable Pulse Width < 25,,5) 00-07 VOH VSS+25 - - V
II Load = -100"A, Enable Pulse W,dth< 25 ,,5) TX Data, i'i'm, TUF VSS+24 - -
Output Low Voltage IILoad-1 6 mA, Enable Pulse Wldth<25"s) VOL - - VSS+04 V
Output Leakage Current lOll-State) IVOH =24 V) IRO 10Z - 1.0 10 "A
Internal Power DISSipatIOn IMeasured at TA = h) PINT - 300 525 mW
Input CapaCitance
IV,n=O, TA=25°C,f=1 OMHz) 00-07 C,n - - 125 pF
All Other Inputs - - 75
Output Capacitance Tx Data, SM/l5i1\, TUF 10
IV,n=O, TA=25°C,f=1 OMHz) IRO Cout - - 50
pF

4·537
 MC6852-MC68A52-MC68B52

AC ELECTRICAL CHARACTERISTICS IVCC= 5 0 V ±5% VSS =0 TA = Tl to TH unless otherwise noted I

MC6852 MC68A52 MC68B52
Characteristic Symbol Min Max Unit
Min Max Min Max
Senal Clock Pulse Width, low IF,gure 11 PWCl 700 - 400 - 280 - ns
Senal Clock Pulse Width, High IF,gure 21 PWCH 700 - 400 - 280 - ns
Senal Clock Frequency IRx ClK, Tx ClKI fc - 600 - 1000 - 1500 kHz
Receive Data Setup Time IFlgure 3, 71 tRDSU 350 - 200 - 160 - ns
Receive Data Hold Time IFlgure 31 tRDH 350 - 200 - 160 - ns
Sync Match Delay Time IFlgure 3) tSM - 10 - 0666 - 0500 I'S
Clock-to-Data Delay for Transmitter I Figure 41 TOO - 10 - 0666 - 0500 I'S
Transmitter Underflow I Figures 4, 6) tTUF - 10 - 0666 - 0500 I'S
[5TI! Delay Time I Figure 5) tDTR - 10 - 0666 - 0500 I's
Interrupt Request Release Time IF,gure 5) I(R - 16 - 11 - 0850 I's
RESET Pulse Width tRESET 10 - 0666 - 0500 - I's
CTS Setup Time I Figure 61 tCTS 200 - 150 - 120 - ns
DCi3 Setup Time I Figure 7) to CD 500 - 350 - 250 - ns
Input Rise and Fall Times IExcept Enablel t r , tf - 10' - 10' 10' I'S
1.0l'S or 10% of the pulse Width, whichever IS smaller

I FIGURE 1 - CLOCK PULSE WIDTH, lOW-STATE

Tx ClK
or
FIGURE 2 - CLOCK PULSE WIDTH, HIGH-STATE

Tx ClK
or
Rx ClK Rx ClK

FIGURE 3 - RECEIVE DATA SETUP AND HOLD TIMES AND SYNC MATCH DELAY TIME

Dn-1 On DO
Rx ClK

Rx Data
>....>..>""""">....>..>"1''-----'

n = Number of Bits In Character

~ = Don't Care
Sync Match

=: 1 Rx elK Period

Note Timing measurements are referef"lced to and from a low voltage of 0 8 volts and a high voltage of 2 0 volts, unless otherWise noted

4-538
MC6852-MC68A52-MC68B52

FIGURE 4 - TRANSMIT DATA OUTPUT DELAY AND FIGURE 5 - DATA TERMINAL READY AND INTERRUPT
TRANSMITIER UNDERFLOW DELAY TIME REQUEST RELEASE TIMES

Tx ClK
Enable
tTDD

Tx Data

tTUF

TUF-------------------J
IRQ

n = Number of bas In character

CTS
FIGURE 6 -

)--
ClEAR-TO-SEND SETUP TIME FIGURE 7 -

Rx ClK
DATA CARRIER DETECT SETUP TIME

1"--_---'1.-_ _-1 1 •
Tx ClK
Notes
Must occur before OCD goes low.
First data bit placed In Rx shift register
last data bit of byte placed In Rx shift register
Tx Data
Rx data byte transferred from shift register to Rx FIFO
e Clock edge required for generation ofiR'Ei by RDA status
Note Refer to Figure 3 for the Rx data setup and hold times

Note Timing measurements are referenced to and from a low voltage of 08 volts and a high voltage of 2 a volts, unless otherWise noted

BUS TIMING TEST lOADS

load A Load B
100-07, DTR, Tx Data, TUF) IIRQ Only)

50V 50V

RL=25kO ~ 3 kO

Test POint 0--.--.--100II1--4

MMD6150
or Equlv TestPolnt~
C R
MMD7000
or Equlv
1 100PF

C = 130 pF for DO-D7 R = 11 7 kO for 00-07

= 30 pF for DiR, Tx Data, and TUF =24 kO for DTR, Tx Data, and TUF

4-539
 MC6852· MC68A52. MC68B52

BUS TIMING CHARACTERISTICS ISee Notes 1 and 21

Indent MC6852 MC68A52 MC68B52
Characteristic Symbol Unit
Number Min Max Min Max Min Max
1 Cycle Time tcyc 10 10 067 10 05 10 ~s

2 Pulse Width, E Low PWEL 430 280 210 ns

3 Pulse Width, E High PWEH 450 - 280 - 220 - ns
4 Clock Rise and Fall Time tr,tf - 25 - 25 - 20 ns
9 Address Hold Time tAH 10 - 10 - 10 - ns
13 Address Setup Time Before E tAS 80 80 40 ns
14 Chip Select Setup Time Before E tcs 80 - 80 - 40 - ns
15 Chip Select Hold Time tCH 10 - 10 - 10 - ns
18 Read Data Hold Time tDHR 20 50" 20 50" 30 50" ns
21 Wnte Data Hold Time tDHW 10 - 10 - 10 - ns
30 Output Data Delay Time tDDR - 290 180 - 150 ns
31 Input Data Setup Time tDSW 165 - 80 - 80 - ns

"The data bus output buffers are no longer sourCing or smkmg current by tOHRmax (High Impedance)

FIGURE 8 - BUS TIMING CHARACTERISTICS

(READ/WRITE INFORMATION)

• ~-----------r3\-----------~

R/W,Address--~-t~~~~~~CT--------\7~~-----rt---------------------------------tl~7V~

INon-Muxedl _____+~~~~~~~~----~~~~---_+~----------------------~~~~~

Read Data ---t-""-D________.....;.M:.;.p:.;.u=-R;,.:e~a~d;,.:D;,.:a:.;.ta=_N:.;.o_n-_M_u_x;,.:e:.;.d_ _ _----~f---<1

Non-M uxed .,.---'ii'"---:::--+-I-.....<r-

Wnte Data ---...:.-""'- MPU Wnte Data Non-Muxed

Muxed D-------------~~~~~~~----~--------------~----_<I
~--~~------~--~

Notes
1. Voltage levels shown are VLsO 4 V, VH",2 4 V, unless otherwise specified
2 Measurement POints shown are 0.8 V and 2 0 V, unless otherwise specified

4·540
 s::

EXPANDED BLOCK DIAGRAM

~s::
(")
~
l>
Enable 14 + Parity
~
Read/Wnte 13 _____ Transmit
Data!=IFO
~
,
Generator

s::
(")
Chip Select 10-----.
I
Address

L 0 9,e U r-- ~
OJ
Reg ..ter Select 11 ~ f----,
{'r Transmitter ~
L #3
Transmit
Fr Underflow

24 Clear to Send

•
Control

DO 22 -.-i
~ y ~+=+=~==~::====1-
~ '" 23 Data Came,
Detect
J:>. Dl 2 1 _, Interrupt
I rterrupt
0, l Logic
Request
J:>. D2 20~
......
D3 19- Data
Bus
D4 18_ Buffers

~
D5 17_

D6 16_

D7 15_

RESET
rF~~;-;---"'o-~==::::t--~---- Receive
./'-.l~~1:-======-J----'-..L--l 2 Data
L.'-
f'"TTii-:=====:;-.......Jr-,--,----i 3 Receive
Clock

Sync
Match!
V cc =Pln12 Data Termmal
V SS =Pln1 Ready

II
 MC6852-MC68A52-MC68B52

DEVICE OPERATION TRANSMITIER OPERATION

Data IS transferred to the transmitter section In parallel
At the bus Interface, the SSDA appears as two ad- form by means of the data bus and Transmit Data FIFO The
dressable memory locations Internally, there are seven Transmit Data FIFO IS a 3-byte register whose status IS In-
registers two read-only and five wnte-only registers The dicated by the Transmitter Data Register Available status bit
read-only registers are Status and Receive Data, the wnte- ITDRAI and ItS associated Interrupt enable bit Data IS
only registers are Control 1, Control 2, Control 3, Sync Code transferred through the FIFO on negative edges of Enable lEI
and Transmit Data The senal Interface consists of senal In- pulses Two data transfer modes are provided In the SSDA
put and output lines with Independent clocks, and four The 1-byte transfer mode prOVides for wnllng data to the
penpheral/modem control lines. transmitter section land reading from the receiver sectlonl
Data to be transmitted IS transferred directly Into the one ayte at a time The 2-byte transfer mode provides for
3-byte Transmit Data Flrst-in First-Out IFIFOI Register from wntlng two data characters In succession
the data bus. Availability of the input to the FIFO IS Indicated Data Will automatically transfer from the last register loca-
by the TDRA bit In the Status Register, once data IS entered, tion In the Transmit Data FIFO Iwhen It contains datal to the
It moves through the FIFO to the last empty location. Data at Transmitter Shift Register dunng the last half of the last bit
the output of the FI FO IS automatically transferred from the of the prevIous character A character IS transferred Into the
FIFO to the Transmitter Shift Register as the shift register Shift Register by the Transmitter Clock Data IS transmitted
becomes available to transmit the next character If data IS LS8 first, aCld odd or even panty can be optionally append-
not available from the FIFO lunderflow condltlonl, the ed. The unused bit positions In short word length characters,
Transmitter Shift Register IS automatically loaded with either from the data bus, are "don't cares" I Note The data bus in-
a sync code or an all "l's" character The transmit seclton puts may be reversed for applications requiring the MSB to
may be programmed to append even, odd, or no panty to be transferred first, e g., IBM format for floppy diSks,

•
the transmitted word. An external control line IClear-to- however, care must be taken to properly program the control
Sendl is provided to Inhibit the transmitter without clearing registers - Table 1 Will have Its bit positions reversed I
the FIFO. When the Shift Register becomes empty, and data IS not
Senal data IS accumulated In the receiver based on the available for transfer from the Transmit Data FIFO, an
synchronization mode selected. In the external sync mode, "underflow" occurs, and a character IS Inserted Into the
used for parallel-senal operation, the receiver IS synchronized transmitter data stream to maintain character synchroniza-
by the DCD iData Carner Detectl Input IFlgure 91 and tion The character transmitted on underflow Will be either a
transfers succeSSive bytes of data to the Input of the "Mark" lall "1's"l or the contents of the Sync Code
Receiver FIFO. The slngle-sync-character mode requires that Register, depending upon the state of the 'Transmlt Sync
a match occur between the Sync Code Register and one In- Code on Underflow control bit The underflow condition IS
coming character before data transfer to the FIFO begins. ,nd,cated by a pulse 1=1 Tx ClK high penodl on the
The two-sync-character mode requires that two sync codes Underflow output Iwhen In Tx Sync on underflow model
be received In sequence to establish synchronization. Subse- The Underflow output occurs cOincident with the transfer of
quent to synchronization In any mode, data is accumulated the last half of the last bit preceding the underflow character
In the shift register, and panty IS oPtionally checked An In- The Underflow status bit IS set until cleared by means of the
dication of panty error IS carned through the Receiver FI FO Clear Underflow control bit ThiS output may be used In flop-
with each character to the last empty location. Availability of py disk systems to synchronize wnte operations and for ap-
a word at the FIFO output IS indicated by the RDA status bit pending CRCC
In the Status Register, as IS a panty error IPEI Transmission IS Initiated by cleanng the Transmitter Reset
The SSDA and ItS Internal registers are selected by RS, bit In Control Register 1 When the Transmitter Reset bit IS
CS, Read/Wnte IR/VVI and Enable centrol lines. To con- cleared, the first full positive half-cycle of the Transmit Clock
figure the SSDA, Control Registers are selected and the ap- will Initiate the transmit cycle, with the transmission of data
propriate bits set. The Status Register IS addressable for or underflow characters beginning on the negative edge of
reading status. _ the Transmit Clock pulse which started the cycle. If the
Other I/O lines, in addition to Clear-to-Send ICTSI and Transmit Data FIFO was not loaded, an underflow character
Data Carrier Detect (DeDI, Include SM/DTR ISync Will be transmitted Isee~re 41.
Match/Data Terminal Readyl and Transmitter Underflow The Clear-to-Send ICTSI Input prOVides for automatic
ITUFI. The transmitter and receiver each have ,nd,v,dual control of the transmltt~ means of external system hard-
clock inputs allowing simultaneous operation under separate ware; e.g., the modem CTS output .E.':.£.vldes the control In a
clock control. Signals to the microprocessor are the Data data communications system The CTS Input resets and In-
Bus and Interrupt Request IIRQI. hibits the transmitter section when high, but does not reset
the Transmit Data FIFO. The TDRA status bit IS Inhibited by
INITIALIZATION CTS being high In either the one-sync character or two-sync
During a power-on sequence, the SSDA is reset via the character mode of operation. In the external sync mode,
RESET input and internally latched in a reset condition to TDRA IS unaffected by m In order to prOVide Transmit
prevent erroneous output transitions. The Receiver Shift Data FIFO status for preload~ and operating the transmit-
Register is set to all "1's". The Sync Code Register, Control ter under the control of the CTS Input. When the Transmit-
Register 2, and Control Register 3 should be programmed ter Reset bit ITx Rslls set, the Transmit Data FIFO IS cleared
prior to the programmed release of the Transmitter and/or and the TDRA status bit is cleared. After one E clock has oc-
Receiver Reset bits; these bits in Control Register 1 should curred, the Transmit Data FIFO becomes available for new
be cleared after the RESET line has gone high. data with TDRA inhibited.

4·542
MC6852-MC68A52-MC68B52

RECEIVER OPERATION register locations are full Data being available In the Receive
Data and a presynchronlzed clock are provided to the Data FIFO causes an Interrupt request If the Receiver Inter-
SSDA receiver section by means of the Receive Data (Rx rupt Enable (RIEl bit IS set. The MPU Will then read the
Datal and Receive Clock (Rx CLKI,nputs. The data IS a con- SSDA Status Register which Will Indicate that data IS
tinuous stream of binary data bits without means for Identi- available for the MPU read from the Receive Data FIFO
fYing character boundanes within the stream It IS, therefore, register The IRO and RDA status bits are reset by a read
necessary to achieve character synchronization for the data from the FIFO. If more than one character has been received
at the beginning of the data block Once synchronization IS and IS resident In the Receive Data FI FO, subsequent E
achieved, It IS assumed to be retained for all successive clocks Will cause the FIFO to update and the RDA and IRO
characters within the block. status bits Will agam be set The read data operation for the
Data commUnications systems utilize the detection of sync 2-byte transfer mode reqUires an intervening E clock be-
codes dunng the Initial portion of the preamble to establish tween reads to allow the FIFO data to shift Optional panty IS
character synchronization. ThiS requires the detection of a automatically checked as data IS received, and the panty
single code or two successive sync codes Floppy disk and status condition IS maintained With each character until the
cartndge tape Units require sixteen bits of defined preamble data IS read from the Receive Data FIFO Panty errors Will
and cassettes require eight bits of preamble to establish the cause an Interrupt request If the Error Interrupt Enable (EIE)
reference for the start of record All three are functionally has been set The panty bit IS not transferred to the data bus
eqUivalent to the detection of sync codes Systems which do but must be checked In the Status Register NOTE In the
not ullllze code detection techniques require custom logic 2-byte transfer mode, panty should be checked pnor to
external to the SSDA for character synchronization and use reading the second byte, since a FIFO read clears the error
of the parallel-to-senal (external sync! mode (Note The bit
Receiver Shift Register IS set to ones when reset I Other status bits which pertain to the receiver section are

II
Receiver Overrun and .Data Carner Detect ('i:5EC5) The Over-
run status bit IS automatically set when a transfer of a
SYNCRHONIZATION
character to the Receive Data FIFO occurs and the first
The SSDA provides three operating modes With respect to register of the Receive Data FI FO IS. full Overrun causes an
character synchronization one-sync-character mode, two- Interrupt If Error Interrupt Enable (EIEI has been set The
sync-character mode, and external sync mode The external transfer of the overrunning character Into the FIFO causes
sync mode reqUires synchronization and contlol of the the prevIous character In the FIFO Input register location to
receiving section through the Data Carner Detect (Delil In- be lost The Overrun status bit IS cleared by reading the
put (see Figure 71 ThiS external synchronlzallon could con- Status Register (when the overrun condition IS present!.
SiSt of direct line control from the transmitting end of the followed by a Receive data FIFO Register read Overrun can-
senal data link or from external logic designed to detect the not occur and be cleared Without provldmg an opportunity to
start of the message block The one-sync-character mode detect ItS occurrence via the Status Register
searches on a blt-by-blt basIs until a match IS achieved be- A positive transition on the DCD Input causes an Interrupt
tween the data In the Shift Register and the Sync Code If the EI E control bit has been set The Interrupt caused by
Register The match indicates character synchronization IS DCD IS cleared by reading the Status Register when the Li'CD
complete and Will be retained for the message block In the status bit IS high, followed by a Receive data FIFO read The
two-sync-character mode, the receiver searches for the first 5CD status bit Will subsequently follow the state of the DCD
sync code match on a blt-by-blt basIs and then looks for a se- Input when It goes low
cond successIVe sync code character pnor to establishing
character synchronization If the second sync code character
IS not received, the blt-by-blt search for the first sync code IS
resumed INPUT/OUTPUT FUNCITONS
Sync codes received pnor to the completion of syn-
chrOnization (one or two characterl are not transferred to the SSDA INTERFACE SIGNALS FOR MPU
Receive Data FIFO Redundant sync codes dunng the The SSDA Interfaces to the MC6800 MPU With an 8-blt bi-
preamble or sync codes which occur as "fill characters" can directional data bus, a chip-select line, a register-select line,
automatically be stnpped from the data, when the Stnp an Interrupt-request line, read/wnte line, an enable line, and
Sync control bit IS set, to minimize system loading The a reset line These Signals, In conjunction With the MC6800
character synchronization Will be retained until cleared by VMA output, permit the MPU to have complete control over
means of the Clear Sync bit, which also Inh,b,ts synchroniza- the SSDA
tion search when set
SSDA Bi-Directional Data (DO-D7) - Tne bl-directlOnal
RECEIVING DATA data lines (00-071 allow for data transfer between the SSDA
Once synchronization has been achieved, subsequent and the MPU The data bus output dnvers are three-state
characters are automatically transferred Into the Receive deVices that remain In the high-Impedance (off) state except
Data FIFO and clocked through the FIFO to the last empty when the MPU performs an SSDA read operation
location by E pulses (MPU System </>2) The Receiver Data
Available status bit (RDAllndlcates when data IS available to SSDA Enable (E) - The Enable Signal, E, IS a hlgh-
be read from the last FIFO location (#3) when In the l-byte Impedance TTL-compatible Input that enables the bus In-
transfer mode. The 2-byte transfer mode causes the RDA put/output data buffers, clocks data to and from the SSDA,
status bit to Indicate data IS available when the last two FI FO and moves data through the FIFO Registers

4·543
 MC6852-MC68A52-MC68B52

Read/Write (R/W) - The Read/Wnte line IS a hlgh- SERIAL INPUT/OUTPUT LINES

Impedance Input that IS TTL compatible and IS used to con- Receive Data (Rx Data) - The Receive Data line IS a hlgh-
trol the direction of data flow through the SSDA's in- Impedance TTL-compatible Input through which data IS
put/ output data bus Interface When Read/Wnte IS high received In a senal format
(MPU read cycle), SSDA output dnvers are turned on If the
chip IS selected and a selected register IS read When It IS Transmit Data (Tx Data) - The Transmit Data output line
low, the SSDA output dnvers are turned off and the MPU transfers senal data to a modem or other penpheral.
wntes Into a selected register The Read/Wnte signal IS also
used to select read-only or wnte-only registers within the PERIPHERAL/MODEM CONTROL
SSDA. The SSDA Includes several functions that permit limited
control of a penpheral or modem The functions Included are
Chip Select (CS) - ThiS high-Impedance TTL-compatible Clear-to-Send, Sync Match/Data Terminal Ready, Data Car-
Input line IS used to address tlie SS DA. The S SDA IS ner Detect, and Transmitter Underflow
selected when CS IS low VMA should be used In generating
the CS Input to Insure that false selects Will not occur Clear-to-Send (CTS) - The CTS Input provides a real-
Transfers of data to ~nd from the SSDA are then performed time inhibit to the transmitter section (the Tx Data FIFD IS
under the control of the Enable signal, Read/Wnte, and not disturbed) A positive CTS transition resets the Tx Shift
Register Select Register and inhibits the TDRA status bit and ItS associated
Interrupt In both the one-sync-character and two-sync-
Register Select (RS) - The Register Select line IS a hlgh- character modes of operation TDRA IS not affected by the
Impedance Input that IS TTL compatible. A high level IS used CTS Input In the external sync mode
to select Control Registers C2 and C3, the Sync Code The posItIVe transition of CTS IS stored Within the SSDA
Register, and the Transmit/Receive Data Registers. A low

I
to Insure that ItS occurrence Will be acknowledged by the
level selects the Control 1 and Status Registers (see Table 1) system. The stored CTS Information and ItS associated IRQ
Ilf enabled) are cleared by wntlng a "1" In the Clear CT~
Interrupt Request (iRQ) - Interrupt Request IS a TTL In Control Register 3 or In the Transmitter Reset bit The CTS
compatible, open-drain Ina Internal pullup), active low out- status bit subsequently follows the CTS Input when It goes
put that IS used to Interrupt the MPU The Interrupt Request low
remains low until cleared by the M PU The CTS Input provides character timing for transmitter
data when In the external sync mode Transmission IS In-
RESET Input - The RESET Input provides a means of Itiated on the negatIVe transition of the first full positive clock
resetting the SSDA from an external source In the low pulse of the transmitter clock (Tx ClK) after the release of
state. the RESET Input causes the follOWing CTS Isee Figure 6)
1 Receiver Reset (Rx Rs) and Transmitter Reset ITx Rs)
bits are set causing both the receiver and transmitter Data Carrier Detect (DCD) - The DCD Input proVides a
sections to be held In a reset condition real-time Inhblt to the receiver section Ithe Rx FIFO IS not
2 Penpheral Control bits PCl and PC2 are reset to zero, disturbed!. A positive DCD transition resets and Inhlbts the
causing the SM/DTI! output to be high receiver section except for the Receive FIFO and the RDRA
3 The Error Irterrupt Enable IEIE) bit IS reset status bit and ItS associated IRQ
4 An Internal synchrol1lzatlon mode IS selected The positive transition ofl5Ci') IS stored Within the SSDA
5. The Transmitter Data Register Available ITDRA) to Insure that ItS OCCurrence Will be acknowledged by the
status bit IS cleared and inhibited system The stored DCD Information and ItS associated iRIT
6 The Receiver Shift Register IS set to l's Ilf enabled) are cleared by reading the Status Register and
When RESET returns high Ithe inactive state), the then the Receiver FIFO, or by wntlng a "1" Into the Receiver
transmitter and receiver sections Will remain In the reset state Reset bit The DCD status bit subsequently follows the l5'ELi
until the Receiver Reset and Transmitter Reset bits are Input when It goes low. The DCD Input proVides character
cleared via the data bus under software control The control synchrol1lzatlon timing for the receiver dunng the external
Register bits affected by REID (Rx Rs, Tx Rs, PC1, PC2, sync mode of operation The receiver will be initialized and
EIE, and E/I Sync) cannot be changed when RESET IS low data Will be sampled on the positive transition of the first full
Receive Clock cycle after release of OeD Isee Figure 71
CLOCK INPUTS
Separate high-Impedance TTL-compatible Inputs are pro- Sync Match/Data Terminal Ready (SM/DTR) - The
Vided for clocking of transmitted and received data. SM/DTR output proVides four functions Isee Table 1)
depending on the state of the PCl and PC2 control bits
Transmit Clock (Tx ClK) - The Transmit Clock Input IS When the Sync Match' mode IS selected (PC = "1" ,
used for the clocking of transmitted data The transmitter PC2= "0"), the output proVides a one-blt-wlde pulse when a
shifts data on the negative transition of the clock sync code is detected. ThiS pulse occurs for each sync code
match even If the receiver has already attained synchrol1lza-
Receive Clock (Rx ClK) - The Receive Clock Input IS us- lion The SM output IS Inhibited when PC2= "1" The DTR
ed for clocking In received data The clock and data must be mode (PCl = "0") provides an output level corresponding to
synchrol1lzed externally The receiver samples the data on the complement of PC2 (DTR="O" when PC2="1") (See
the posItive transition of the clock. Table 1.)

4-544
MC6852-MC68A52-MC68B52

TABLE 1 - SSDA PROGRAMMING MODEL

Control Address
Register Content
Register In uts Control
RS RIW AC2 AC1 Bit 7 BIt 6 BIt 5 BIt 4 BIt 3 BIt 2 Bit 1 BIt 0
Status lSI 0 1 X X Interrupt Rpcelver Receiver Transmitter Clear-to- Datd Calner Tlansmltter Receiver
Request Panty Overrun Undelflow Send Detect Ddta Ddla
IiRQI Error (Rx. Dvro ITUFI ICTSI IDCOI Reglstel Available
IPEI Avaddble IROAI
ITORAI
Control 1 0 0 X X Address Addtess Receiver TtdnSmlttel Cleat SttiP Sync Transmitter Receiver
ICli Control 2 Control 1 Interrupt Intet rupt Sym. Chal<Jclels Reset Reset
IAC21 IACli Enable Enable IStrop Syncl ITx Rsl IRx Rsl
IRIEI ITIEI
Receive 1 1 X X 07 06 05 04 03 02 01 DO
Data FIFO
Control 2 1 0 0 0 Error Transmit Word Word WOld l-Byte/2-Byte Peripheral Penphetal
IC21 Interrupt Sync Code Length Length Length Ttanstel Control 2 Conttoll
Enable on Select 3 Select 2 Select 1 11-Byte/2 By tel IPC21 IPCll
IEIEI Underflow IWS31 IWS21 IWSll
ITx Svncl
Control 3 1 0 0 1 Not Used Not Used Not Used Not Used Clear Cled' CTS One~Sync~ Externall
IC31 TranMTlItter Slatus Characterl Internal
Underflow ICled< CTSI Two-Sync Sync Mode

•
Status Character Control
ICTUFI Mode Control IE/I Syncl
(1 Syncl
2 Syncl
Sync Code 1 0 1 0 07 D6 05 04 03 02 01 DO
Transmit 1 0 1 1 07 06 05 04 03 02 01 DO
Data FIFO
x~ Don t care
STATUS REGISTER CONTROL REGISTER 2
IRQ Bit 7 The I RQ flag
cleared when the source of the IRQ IS
IS EIE Bit 7 When ",", enahles the PE, Rx Ovrn,
cle•.lred The so urce IS determined by the enables 10 the TUF, CTS, and DCD mterrupt flags
Control Reglste rs TIE, RIE, EIE IS BIts 6 th,ough 71
B11S6-0 indicate the SSO A status at a pomt In time, and can be Tx Sync Bit 6 When ",", allows .:oync code contpnt
reset as follows to he tran~ferred on underflow, dnd
PE Bit 6 Read Rx Data FIFO,ora"1"lntoRx Rs (el BltO) enables the TUF Status bit and out~
Rx Ovrn Bit 5 Read Sta tus and then Rx Data FIFO, or a "'" Into put. When "0". an all mark character
15 transmitted on underflow
Rx Rs IC 1 Bit 01
81t4 A"l"m to CTUF IC3 BIt 31 or Into Tx Rs ICI BIt 11 WS3, 2, 1 Bits 5-3 Word Length Select
TUF
CTS Blt3 A"1"1n to Clear "CiS" (C3 Bit 2) or a "1" into Tx As
Bit 5 Blf4 Bit 3
IC1 Blt11 Word Length
WS3 WS2 WSI
DCIJ Bit 2 Read Sta tus and then R)( Data FIFO or a "1" IOta
Rx Rs IC 1 BIt 01 0 0 0 6 Bits" Even Parity
TDRA Bit 1 Wllte Int o Tx Data FIFO 0 0 1 6 Bits + Odd Parity
ROA BIt 0 Read Rx Data FIFO_ 0 1 0 7 Bits
0 1 1 8 BllS
CONTROL REGISTER 1
1 0 0 7 Bits" Even Panty
AC2, ACI Bits 7, 6 Used to access other registers, as shown above 1 0 1 7 Bits t Odd Panty
RIE Bit 5 When '" ", enables Interrupt on RDA (S Bit 0) 1 1 0 8 Bits t Even Parity
TIE BIt 4 When "1 ", enables Interrupt on TDRA (S Bit 1) 1 1 1 8 Bits + Odd P.mty
Clear Sync Bit 3 When '" ", clears receiver character synchronization
StriP Sync Bit 2 When "1 , striPS all sync codes from the received l-Byte/2-Byte Bit 2 When ",". enables the TDRA and
data stream RDA bits to Indicate when a l-byte
Tx Rs Bit 1 When '" " , resets and Inhibits the transmitter section transfer can occur. when "0". Ihe
Rx Rs Bit 0 When "1 " . resets and tnhlblts the receiver section TORA and RDA hits Indicate when
a 2-byte transfer can occur
CONTROL REGISTER 3 PC2, PCl Bits 1-~0 SM/1TI"R Output Control
CTUF BIt 3 When "1 " ,clears TUF (S Bit 4), and IRQ If enabled
Bit 1 Bit 0
Clear CTS Bit 2 When "1 ", clears CTS IS BIt 31, and IRQ If enabled SM/l5'FR Output at Pm 5
PC2 PCl
, Sync/2 Sync Bit 1 When "1 , selects the one-sync-character mode, when
"O",selects the two-sync-character mode 0 0 1
Ell Sync Btt a When "1 , selects the external sync mode. when "0", 0 1 Pulse .s-1- 1 Bit Wide on SM
s~lects th e Internal sy nc mode 1 0 0
1 1 SM Inhibited, a
NOTE When the SSDA IS used In applications requlrlOg the MSB of data to
be received and transmitted first, the data bus Inputs to the SSDA may be
reversed (00 to 07, etc) Caution must be used when thiS IS done since the
bit positions In this table will be reversed, and the parity should not be selected.

4-545
 MC6852-MC68A52-MC68B52

Transmitter Underflow (TUF) - The Underflow output In- Transmitter Interrupt Enable (TIE), Cl Bit 4 - TIE enables
dicates the occurrence of a transfer of a "fill character" to both the Interrupt Request output (iRTIl and Interrupt Re-
the Transmitter Shift Register when the last location (#3) In quest status bit to indicate a transmitter service request
the Transmit Data FIFO IS emtpy The Underflow output When TIE IS set and the TDRA status bit IS high, the IRQ out-
pulse IS approximately one Tx ClK high penod wide and oc- put Will go low (the active state) and the iRQ status bit Will
curs dunng the last half of the last bit of the character go high
preceding the "Underflow" (see Figure 41. The Underflow
output pulse does not occur when the Tx Sync bit IS In the Receiver Interrupt Enable (RIE), Cl Bit 5 - RIE enables
reset state both the Interrupt Request output ((RQ) and the (nterrupt
Request stacus bit to indicate a receiver service request.
SSDA REGISTERS When RIE IS set and the RDA status bit IS high, the T'RL! out-
Seven registers In the SSDA can be accessed by means of put Will go low (the active state) and the IRQ status bit Will
the data bus. The registers are defined as read-only or wnte- go high
only according to the direction of Information flow The
Register Select Input (RS) selects two registers In each state, Address Control 1 (AC1) and Address Control 2 (AC2), Cl
one being read-only and the other wnte-only. The Bits 6 and 7 - ACI and AC2 select one of the write-only
Read/Wnte Input (R/W) defines which of the two selected registers - Control 2, Control 3, Sync Code, or Tx Data
registers will actually be accessed. Four registers (two read- FIFO - as shown In Table 1, when RS = "1" and
only and two wnte-only) can be accessed via the bus at any R/W="O"
particular time These registers and the reqUired addressing
are defined In Table 1. CONTROL REGISTER 2 (C2)
Control Register 2 IS an 8-blt wnte-only register which can

•
CONTROL REGISTER 1 (Cl) be programmed from the data bus when the Address Control
Control Register 1 IS an 8-blt wnte-only register that can be bits In Control Register 1 (ACI and AC2) are reset, RS = "1"
directly addressed from the data bus Control Register 1 IS and R/W="O"
accessed when RS = "0" and R/W="(J'.
Peripheral Control (PC1) and Peripheral Control 2 (PC2),
Receiver Reset (Rx Rs), Cl Bit 0 - The Receiver Reset C2 Bits 0 and 1 - Two control bitS, PCl and PC2, determine
control bit provides both a reset and inhibit function to the the operating charactenstlcs of the Sync Match/ DTR out-
receiver section When Rx Rs IS set, It clears the receiver put PC1, when high, selects the Sync Match mode PC2
control logic, sync logic, error logic, Rx Data FIFO Control, proVides the Inhibit/enable control for the SM/DTR output
Panty Error status bit, and DCD Interrupt The Receiver Shift In the Sync Match mode A one-blt-wlde pulse IS generated
Register IS set to ones. The Rx Rs bit must be cleared after at the output when PC2 IS "0", and a match occurs between
the occurrence of a low level on RESET In order to enable the contents of the Sync Code Register and the Incoming
the receiver section of the SSDA. data even If sync IS inhibited (Clear Sync blt= ''1'') The
Sync Match pulse IS referenced to the negative edge of Rx -
Transmitter Reset (Tx Rs), Cl Bit 1 - The Transmitter ClK pulse causing the match (see Figure 3)
Reset control bit proVides both reset and inhibit to the The Data Terminal Ready (DTR) mode IS selected when
transmitter section When Tx Rs IS set, It clears the transmit- PClis low When PC2="I" the SM/DTR output="O" and
ter control section, Transmitter Shift Register, Tx Data FIFO vice versa The operation of PC2 and PCl IS summanzed In
Control (the Tx Data FIFO can be reloaded after one E clock Table 1
pulse), the Transmitter Underflow status bit, and the CTS In-
terrupt, and Inhibits the TDRA status bit (In the one-sync- l-Byte/2-Byte Transfer (1-Byte/2-Byte), C2, Bit 2 -
character and two-sync-character modes) The T x Rs bit When 1-Byte/2-Byte IS set, the TDRA and RDA status bits
must be cleared after the occurrence of a low level on RESE'i" Will Indicate the avallabltlly of their respective data FIFO
In order to enable the transmitter section of the SSDA If the registers for a Single-byte data transfer Alternately, If
Tx FIFO IS not preloaded, It must be loaded Immediately after l-Byte/2-Byte IS reset, the TDRA and RDA status bits In-
the Tx Rs release to prevent a transmitter underflow condi- dicate when two bytes of data can be moved Without a se-
tlon. cond status read An intervening Enable pulse must occur
between data transfers
Strip Synchronization Characters (Strip Sync), Cl Bit 2 -
If the Stnp Sync bit IS set, the SSDA Will automatically stnp Word length Selects (WS1, WS2, WS3), C2 Bits 3, 4,5
all received characters which match the contents of the Sync - Word length Select bits WS1, WS2, and WS3 select
Code Register The characters used for synchrOnization (one word lengths of 7, 8, or 9 bits Including panty as shown In
or two characters of sync) are always stnpped 'from the Table 1
received data stream
Transmit Sync Code on Underflow (Tx Sync), C2 Bit 6 -
Clear Synchronization (Clear Sync), Cl Bit 3 - The Clear When Tx Sync IS set, the transmitter Will automatically send
Sync control bit proVides the capability of drOPPing receiver a sync character when data IS not available for transmission
character synchronization and inhibiting resynchronlzatlon If Tx Sync IS reset, the transmitter Will transmit a Mark
The Clear Sync bit IS set to clear and inhibit receiver syn- character (including the panty bit position) on underflow
chrOnization In all modes and IS reset to zero to enable resyn- When the underflow IS detected, a pulse approximately one
chronlzatlon Tx ClK high penod Wide Will occur on the underflow output

4·546
MC6852·MC68A52-MC68B52

If the Tx Sync bit IS set Internal panty generation IS Inh!blted state of the CTS Input The Clear CTS control bit does not
dunng underflow except for sync code fill character affect the CTS Input nor ItS inhibit of the transmitter section
transmission In a-bit plus panty word lengths The Clear CTS command bit IS self-cleanng, and wntlng a
"0" Into thiS bit 1° a nonfunctional operation
Error Interrupt Enable (EIE), C2 Bit 7 - When EIE IS set,
the IRO status bit Will go high and the IRO output Will go low Clear Transmit Underflow Status (CTUF), C3 Bit 3 -
If When a "'" IS written Into the CTUF status bit, the CTUF bit
A receiver overrun occurs The Interrupt IS cleared by and ItS associated Interrupt are reset The CTUF command
reading the Status Register and reading the Rx Data bit IS self-cleanng and writing a "0" Into thiS bit IS a nonfunc-
FIFO tional operation
2 DCD Input has gone to a "'" The Interrupt IS cleared
by reading the Status Register and reading the Rx
SYNC CODE REGISTER
Data FIFO
3 A parity elror eXists for the character In the last loca- The Sync Code Register IS an a-bit register for stonng the
tIOn 1#3) of the Hx Data FIFO The Interrupt IS cleared programmable sync code reqUired for received data character
by reading the Rx Data FIFO synchrOnization In the one-sync-character and two-sync-
4. The CTS Input has gone to a "'" The Interrupt IS character modes The Sync Code Register also prOVides for
cleared by writing a "'" In the Clear CTS bit, C3 bit 2, stnpplng the sync/fill characters from the received data la
or by a Tx Reset programmable option) as well as automatic insertion of fill
5 The transmitter has underflowed (In the Tx Sync on characters In the transmitted data stream The Sync Code
Underflow mode) The Interrupt IS cleared by wntlng a Register IS not utilized for receiver character synchronization
"'" Into the Clear Underflow, C3 bit 3, or Tx Reset In the external sync mode, however, It prOVides storage of
receiver match and transmit fill characters.

II
When EIE IS a "0", the IRO status bit and the IRO output
The Sync Code Register can be loaded when AC2 and
are disabled for the above error conditIOns A low level on
AC' are a "'" and "0", respectively, and R/W'="O" and
the RESET Input resets EIE to "0"
RS="'"
The Sync Code Register may be changed after the detec-
CONTROL REGISTER 3 (C3)
tion of a match With the received data Ithe first sync code
Control Register 3 IS a 4-blt wnte-only register which can haVing been detected) to synchrOnize With a double-word
be programmed from the data bus whe RS= "'" and sync pattern. IThis sync code change must occur pnor to the
R/W="O" and Address Control bit AC'="'" and completion of the second character.) The sync match ISM)
AC2="0" output can be used to Interrupt the M PU system to indicate
that the first eight bits have matched The service routine
External/Internal Sync Mode Conrol (Ell Sync), C3, Bit 0 would then change the sync match register to the second
- When the Ell Sync Mode bit IS high, the SSDA IS In the half of the pattern Alternately, the one-sync-character mode
external sync mode and the receiver synchrOnization logiC IS can be used for sync codes for '6 or more bits by uSing soft-
disabled SynchrOnization can be achieved by means of the ware to check the second and subsequent bytes after
t5cri Input or by starting Rx ClK at the midpOint of data bit 0 reading them from the FIFO
of a cahracter with DCl) low Both the transmitter and The detection of the sync code can be programmed to ap-
receiver sections operate as parallel - senal converters In pear on the Sync Match/1JTIi output by writing a "'" In PC,
the External Sync mode The Clear Sync bit In Control IC2 bit 01 and a "0" In PC2 IC2 bit') The Sync Match out-
Register' acts as a receiver sync Inhibit when high to pro- put Will go high for one bit time beginning at the character in-
Vide a bus controllable inhibit The Sync Code Register can terface between the sync code and the next character Isee
serve as a transmitter fill character register and a receiver Figure 3)
match register In thiS mode A "low" on the RESET Input
resets the Ell Sync Mode bit plaCing the '>SDA In the inter-
nal sync mode PARITY FOR SYNC CHARACTER

One-Sync-Character/Two-Sync-Character Mode Control Transmitter

(1-Sync/2-Sync), C3 Bit' - When the '-Sync/2-Sync bit IS
Transmitter does not generate parity for the sync
set, the SSDA Will synchronize on a Single match between
character except 9-blt mode
the received data and the contents of the Sync Code
Register When the '-Syncl2-Sync bit IS reset, two suc- _9-bIt la-bit + panty) a-bit sync character + panty
cessive sync characters must be received pnor to receiver 8-blt 17-blt+ panty) 8-blt sync character Ino panty)
synhnchronlzatlon. If the second sync character IS not 7-blt 16-blt+ pantyl. 7-blt sync character Ino panty)
detected, the blt-by-blt search resumes from the first bit In
the second character See the descnptlon of the Sync Code Receiver
Register for more details. At Synchronizatton
Receiver automatically striPS the sync characterls) Itwo
Clear CTS Status (Clear CTS), C3 Bit 2 - When a "'" IS sync characters If '2 sync' mode IS selected) which IS used to
wntten Into the Clear CTS bit, the stored status and Interrupt establish synchronization Panty IS not checked for these
are cleared Subsequently, the CTS status bit reflects the sync chardcters.

4-547
 MC6852-MC68A52-MC68852

After SynchronizatIon Is Established Unused data bits for short word lengths Will be handled as
When 'stnp sync' bit IS selected, the sync characters (fill "don't cares." The parity bit IS not transferred over the data
characters) are stripped and panty IS not checked for the bus Since the SSDA generates panty at transmission.
stnpped sync (fill) characters. When "stnp sync" bit IS not When an Underflow occurs, the Underflow character Will
selected (low), the sync character IS assumed to be normal be either the contents of the Sync Code Register or an all
data and It IS transferred mto FI FO after partly checking "l's" character The underflow Will be stored In the Status
(When non-parity format IS selected panty IS not checked ) Register until cleared and Will appear on the Underflow out-
WSO-WS2 put as a pulse approxlmatley one Tx ClK high penod Wide
Strip Sync (Data Format)
(C1, Bit 2) (C2, Bits 3-5) STATUS REGISTER (S)
No transfer of sync code The Status Register IS an 8-blt read-only register which
1 X
No panty Check of sync code proVides the real-tIme status of the SSDA and the associated
·Transfer data and sync codes senal data channel. Reading the Status Register IS a non-
0 With Panty
Panty check destructive process The method. of cleanng status bits
"Transfer data and sync codes depends upon the function each bit represents and IS
0 Without Pa"ly
NO-'1.ar& check discussed for each bit In the register.
·Subsequent to synchronization
Receiver Data Available (RDA), S Bit 0 - The Receiver
It IS necessary to consider panty m the selected sync Data Available status bit indicates when receiver data can be
character In the followmg cases Data Format IS (6+ panty), read from the Rx Data FIFO The receiver data being present
(7 + panty), stnp sync IS not selected (low), and when syr,c In the last register (#3) of the FIFO causes RDA to be high for
code IS used as a fill character after synchrontzatlon

•
the l-byte trarisfer mode The RDA bit being high indicates
The transmitter sends a sync character without panty, but' that the last two registers (#2 and #3) are full when m the
the receiver checks the panty as If It IS normal data 2-byte transfer mode The second character can be read
Therefore, the sync character should be chosen to match the Without a second status read (to determine that the
panty check selected for the receiver In this speCial case. See character IS available). An E pulse must occur between reads
the followmg section for unused bit assignment m short- of the Rx Data FIFO to allow the FIFO to shift. Status must
word length be read on a word-by-word basIs If receiver data error check-
ing IS Important. The RDA status bit IS reset automatically
RECEIVE DATA FIRST-IN FIRST-OUT REGISTER (Rx Data when data IS not available
FIFO)
The Receive Data FI FO Register consists of three 8-btl Transmitter Data Register Available (TDRA), S Bit 1 -
registers which are used for buffer storage of received data. The TDRA status bit Indicates that data can be loaded into
Each 8-blt register has an Internal status bit which montlors the Tx Data FIFO Register The first register (#1) of the Tx
ItS full or empty condition Data IS always transferred from a Data IFFO being empty Will be Indicated by a high level In the
full register to an adjacent empty register. The transfer from TDRA status bit In the l-byte transfer mode The first two
register to register occurs on E pulses The RDA status bit registers (#1 and #2) must be empty for TDRA to be high
Will be high when data IS available In the last location of the wh'Jn m the 2-byte transfer mode The Tx Data FI FO can be
Rx Data FIFO loaded With two bytes wltnout an Interventng status read,
In an Overrun condition, the overrunntng character Will be however, one E pulse must occur between loads TDRA IS
transferred Into the full first stage of the FIFO register and inhibited by the Tx Reset or RESET When Tx Reset IS set,
Will cause the loss of that data character Successive over- the Tx Data FIFO IS cleared and then released on the next E
runs continue to overwnte the first register of the FI FO This clock pulse The Tx Data FIFO can then be loaded With up to
destruction of data IS Indicated by means of the Overrun three characters of data, even though TDRA IS Inhibited
status bit The Overrun bit Will be set when the overrun oc- ThiS feature allows preloadmg data prior to the release of Tx
curs and remains set ~nlll the Status ReglstE" IS read, follow- Reset A high level on the m Input Inhibits the TDRA
ed by a read of the Rx Data FI FO. status bit m either sync mode of operation (one-sync-
Unused data bits for short word lengths (Including the character or two-sync-character) CTS does not affect
panty bit) Will appear as "O's" on the data bus when the Rx TDRA In the external sync mode ThiS enables the SSDA to
Data FIFO IS read operate under the control of the rnInput With TDRA In-
dlcatmg the status of the Tx Data FIFO The CTS Input does
TRANSMIT DATA FIRST-IN FIRST-OUT REGISTER (Tx not clear the Tx Data FIFO m any operating mode
Data FIFO)
The Transmit Data FI FO Register consists of thee 8-blt Data Carrier Detect (DCD), S Bit 2 - A POSitive tranSlllOn
registers which are used for buffer storage of data to be on t'1e DCD Input IS stored m the SSDA unttl cleared by
transmitted Each 8-blt register has an Internal status bit reaelng both Status and Rx Data FIFO A "1" written Into Rx
which monttors ItS full or empty condition. Data IS always Rs also clears the stored DCD status The DCD status bit,
transferred from a full register to an adjacent empty register when set, mdlcates that the i'5ClJ Input has gone high The
The transfer IS clocked by E pulses readmg of Status followed by reading of the Receive Data
The TDRA status bit Will be high If the Tx Data FIFO IS FIFO allows Bit 2 of subsequent Status reads to Indicate the
available for data state of the DCD mput until the next posillve transition

4-548
MC6852-MC68A52-MC68B52

Clear-to-Send (CTS), S Bit 3 - A positive tranSItIOn on resulting In data loss The Rx Ovrn status bit IS set when
the CTS Input IS stored In the SSDA until cleared by writing overrun occurs The Rx Ovrn status bit IS cleared by reading
a "'" Into the Clear CTS control bit or the Tx Rs bit. The Status followed by reading the Rx Data FIFO or by setting
CTS status bit, when set, Indicates that the CTS Input has the Rx Rs control bit
gone high. The Clear CTS command (a "'" Into C3 Bit 2)
allows Bit 3 of subsequent Status reads to ,nd,cate the state Receiver Parity Error (PE), S Bit 6 - The panty error
of the m Input until the next positive transition status bit Indicates that panty for the character In the last
register of the Rx Data FIFO did not agree With selected pan-
Transmitter Underflow (TUF), S Bit 4 - When data IS not ty The panty error IS cleared when the character to which It
available for the transmitter, an underflow occurs and IS so pertains IS read from the Rx Data FI FO or when Rx Rs oc-
indicated In the Status Register (In the Tx Sync on underflow curs The OeD Input does not clear the Panty Error or Rx
mode) The underflow status bit IS cleared by wntlng a"'" Data FIFO status bits
Into the Clear Underflow (CTUF) control bit or the Tx Rs bit
TUF Indicates that a sync character will be transmitted as the Interrupt Request (jim.), S Bit 7 - The Interrupt Request
next character A TU F IS indicated on the output only when status bit indicates when the IRQ output IS In the active state
the contents of the Sync Code Register IS to be transferred (IRQ output= "0"), The IRQ status bit IS subject to the same
(transmit sync code on underflow= ",") Interrupt enables (RIE, TIE, and EIE) as the iRa output The
'J'fITI status Olt Simplifies status InqUines for polling systems
Receiver Overrun (Rx Ovrn), S Bit 5 - Overrun Indicates by prOViding Single bit Indication of service requests
data has been received when the Rx Data FIFO IS full,

4-549
 MC6854
®
(1.0 MHz)

MOTOROLA MC68A54
(1.5 MHz)

M~t"r'
ADVANCED DATA-LINK CONTROLLER (ADLC)

The MC6854 ADLC performs the complex MPW/data communocatlon MOS

link function for the "Advanced Data Communocatlon Control Pro- (N-CHANNEL, SILICON GATE)
cedure" (ADCCP), High-Level Data-Link Control (HDLC) and Syn-
chronous Data-Link Control (SDLC) standards. The ADLC provides key
ADVANCED DATA-LINK
interface requirements with Improved software efficiency. The ADLC is
designed to provide the data communications Interface for both pnmary CONTROLLER
and secondary stations in stand-alone, polling, and loop configurations.
• M6800 Compatible
• Protocol Features
• Automatic Flag Detection and Synchronization
• Zero Insertion and Deletion
• Extendable Address, Control and Logical Control Fields (Optionall
• Vanable Word Length Information Field - 5-,6-, 7-, or 8-8its L SUFFIX
• Automatic Frame Check Sequence Generation and Check CERAMIC PACKAGE
CASE 719
• Abort Detection and Transmision
• Idle Detection and Transmission

~
~~UUU" ,,.:,~",~~,
• Loop Mode Operation

•
• Loop 8ack Self-Test Mode
• NRZ/NRZI Modes
• Quad Data 8uffers for Each Rx and Tx
CASEll0
• Prioritized Status Register (Optionall

~
• MODEM/DMA/Loop Interface

~,,: :':: CERDIP

SSUFFIX
PACKAGE
I," . CASE 733
I" .

MAXIMUM RATINGS
Rating Symbol Value Un~
PIN DESCRIPTION
Supply Voltage VCC -0.3 to + 7.0 V
Input Voltage V,n 0.3 to + 70 V
Operating Temperature Aange VSS
ITL to TH)
MC6854, MC68A54, MC68B54 TA Oto 70 ·C 5Ci5
MC6854C, MC68A54C -40 to 85
AxD ITiC/iSili
Storage Temperature Aange Tstg -65 to +150 ·C
AxC
TxC TDSA
THERMAL CHRACTERISTICS
TxO ADSA
Characteriatic Symbol Value Unit
Thermal Aeslstance IAQ 00
PlastiC 115 AESET 01
8JA ·C/W
Ceramic 60
Cerdlp 65 C!l 02
ASO 03
AS1 04
ThiS device contains circuitry to protect the Inputs against damage due to high 05
static voltages or electnc fields, however, It IS adVised that normal precautions
06
be taken to aVOid application of any voltage higher than maximum rated voltages
to thiS high-Impedance Circuit Reliability of operation IS enhanced If unused In- VCC 07
puts are tied to an appropriate logic voltage level Ie g , either VSS or VCC)

4-550
MC6854.MC68A54. MC68B54

FIGURE 1 - ADLC GENERAL BLOCK DIAGRAM

Control Control

oco
RxC

Data
Bu,
00-07

Vss Pm 1
Vee Pm 14
iRCi
TOSR
ROSR
+-------'
~-------'
~ _ _ _ _ _ _--'
LOC/DTR
RTS
RESET
TxO

TxC
CTS
•
POWER CONSIDERATIONS

The average chip-Junction temperature, T J, In °c can be obtained from

TJ=TA+(PO"OJAI (11
Where
T A'" Ambient Temperature, °c
OJA'" Package Thermal Resistance, Junctlon-to-Amblent, °C/W
PO'" PINT+ PPORT
PINT=ICCxVCC, Watts - Chip Internal Power
PpORT'" Port Power Oissipatlon, Watts - User Oetermlned
For most applications PPORT<C PINT and can be neglected PPORT may become Significant If the device IS configured to
drive Oarllngton bases or sink LEO loads
An approximate relationship between Po and T J (,f PPORT IS neglected 1 IS
PO'" K- (T J + 273°CI (21
Solving equations 1 and 2 for K gives,
K = PO"(T A + 273°CI +OJA"P 0 2 (31
Where K IS a constant pertaining to the particular part K can be determined from equation 3 by measuring Po (at equillbrlumi
for a known T A USing thiS value of K the values of Po and T J can be obtained by solving equations (11 and (21 IteratIVely for any
value of T A

4-551
 MC6854e MC68A54e MC68B54

- Vdc ±5% vSS-o

DC ELECTRICAL CHARACTERISTICS IVcc-50 - TA=TL to TH unless otherwise notedl
Characteristic Symbol Min Typ Max Unit
Input High Voltage VIH VSS+20 - - V
Input Low Voltage VIL - - VSS+O 8 V
Input Leakage Current (V,n - 0 to 5 25 VI All Inputs Except 00-07 lin - 10 25 ~A
Three-State 10ff-Statel Input Current 00-07
liZ - 20 10 ~A
IV,n=O 4 to 24 V, VCC=5 25 VI
DC Output High Voltage
11 Load = -205"AI 00-07 VOH VSS + 24 - - V
IVLoad= -100"AI All Others VSS + 2 4 - -
DC Output Low Voltage 11 Load -1 6 mAl VOL VSS+O 4 V
Output Leakage Current 1011 Statel IVOH = 24 VI ilm 10Z 10 10 I'A
Internal Power DIssipatIOn Imeasured at T A hi PINT 850 mW
Capacitance
IVIn=O, TA=25°C,I=1 OMHzI 00-07 C,n - - 125 pF
All Other Ihputs - -- 75
TIm Cout
- - 50
pF
All Others - - 10

AC ELECTRICAL CHARACTERISTICS IV'CC= 50 V ± 5% VSS= O A=T L to TH un ess ot erwlse notedl

, T
MC6854 MC68A54 MC68B54
Characteristic Symbol Unit
Min Max Min Max Min Max

•
Clock Pulse Width, Low IRxC, TxCI PWCL 700 - 450 - 280 - ns
Clock Pulse Width, High IRxC, TxCI PWCH 700 - 450 - 280 - ns
Senal Clock Frequency I RxC, TxCI ISC - 066 - 10 - 15 MHz
Receive Data Setup Time tRDSU 150 - 100 - 50 ns
Receive Data Hold Time tRDH 60 60 60 ns
Request-to-Send Delay Time tRTS 680 460 340 ns
Clock-to-Data Delay lor Transmitter tTDD - 300 - 250 - 200 ns
Flag Detect Delay Time tFD - 680 - 460 - 340 ns
DT R Delay Time tDTR - 680 - 460 - 340 ns
Loop On-Line Control Delay Time tLOC - 680 - 460 - 340 ns
RDSR Delay Time tRDSR - 540 - 400 - 340 ns
TDSR Delay Time tTDSR - 540 - 400 - 340 ns
Interrupt Request Release Time tlR - 12 - 09 - 07 I's
i'iESIT Pulse Width tAESET 10 - 065 - 040 -
~s

Input Alse and Fall Times IExcept Enablel 108 V to 20 VI tr,tl - 10' - 10' - 10' I's

'1 0 I'S or 10% 01 the pulse width, whichever IS smaller

FIGURE 2 - BUS TIMING TEST LOADS

Load A Load B
1D0-D7 m, TxD, ROSA, TOSA 50V
1i'RCi=-{nIYI 50 V
FCAGi5TI, LOci is''i'Rl
AL=25k[J 3 k[J
MMC6150 Test POint
Test POint
or Equlv

C A
MMD7000
or EqUiv roe
C = 130 pF lor 00-07
= 30 pF lor others
A=11 7 k[J lor 00-07
= 24 kn lor others

4·552
MC6854· MC68A54· MC68B54

FIGURE 3 RECEIVER DATA SETUP/HOLD, FLAG DETECT AND LOOP ON-LINE CONTROL DELAY TIMING
~PWCH __
RxC
'i
j.----PWCL-

RxD

tRDS tRDH - - - -

_tFD_

~tLDC ~

•
FIGURE 4 - TRANSMIT DATA OUTPUT DELAY AND REOUEST-TO-SEND DELAY TIMING

PWCH

TxC

TxO

FIGURE 6 - TDSR/RDSR DELAYS, IRQ RELEASE DELAY, RTS AND '6TR DELAY TIMING

E /

ATS
_'ATS-

OTA

_'OTA_

IAa

'IA

TOSA
AOSA
'AOSA
'TOSA
Note' TIming measurement~ are referenced to and from a low voltage of 0.8 volts and 8 hIgh voltage of 2.0 volts, unless otherwise noted

4-553
 MC6854- MC68A54-MC68B54

BUS TIMING CHARACTERISTICS (See Notes 1 and 21

Idem. MC8864 MC68A54 MC88B64
ehe_rietl.. Symbol Unit
Number Min Max Min Max Min Max
1 Cycle Time tcve 1.0 10 0.67 10 0.5 10
2
3
Pulse Width, E Low
Pulse Width, E High
PWEL
PWEH
430
460
9600
9500
280
2BO
9600
9600
210
220
9600
9600
""
ns
ns
4 Clock Rise and Fall Time tr,tf - 25 - 25 - 20 ns
9 Address Hold Time tAH 10 - 10 - 10 - ns
13 Address Setup Time Before E tAS 80 - 80 - 40 - ns
14 Chip Select Setup Time Before E tcs 80 - 80 - 40 - ns
15 Chip Select Hold Time tCH 10 - 10 - 10 - ns
18 Read Data Hold Time tDHR 20 100 20 roo 20 100 ns
21 Wllte Data Hold Time tDHW 10 - 10 10 ns
30 Output Data Delay Time tDDR - 290 - 180 - 150 ns
31 Input Data Setup Time tDSW 165 - 80 - 80 - ns

FIGURE 6 - BUS TIMING

I r-----------~3.-----------_;

R/VV,Addr~s--~~~~~~~~~--------~rr~----~~--------------------------------~~~~

(Non-Muxedl ____ I1~~~~~~~--------~~~;:~~t_~------------------------------tt~~~

cs--~r-;r------------------~

Read Data ---+.....,~::.=_ __________~M~P~U~R~ea~d~D~a~t!a~N~o~n-~M~u~x~e~d_____==_______t==:t.--------1t. . . t

Non-Muxed ---+--orl)
Wnte Data ----'---~ MPU Wllte Data Non-Muxed
Muxed --------~----------------~--~~~~--~~------------~i:.:-=-=-=~~--------~+_--or

Notes
1 Voltage levels are VLSO 4 V, VH,,2 4 V, unless othewlse speCified
2 Measurement pOints shown are 0 8 V and 2 0 V, unless otherwise specified

4-554,
MC6854- MC68A54- MC68854

FRAME FORMAT

The ADLC transmits and receives data (,nformatIOn or opening flag and closing flag, a frame contains an address
cantrall In a format called a frame All frames start with an field, control field, Information field (optlonall and frame
opening flag (FI and end with a closing flag (FI Between the check sequence field

FIGURE 7 - DATA FORMAT OF A FRAME

1~4e-----------------------------------------AFrame ------------------------------------------.~I
01111110 Variable
8 Bits 01111110
Per Byte Length
(5-8)

(Opening) Address' Control" Logical Control Frame Check (ClOSing)

Flag Field Field Sub-Field (OptIOn) Sequence FIeld Flag
'Extendable (OptIOnal! Information Field
(Optional!
---I

Flag (FI - The flag IS the unique binary pattern

(011111101 It proVides the frame boundary and a reference
for the POSition of each field of the frame.
The ADLC transmitter generates a flag pattern Internally
and the opening flag and clOSing flags are appended to a
frame automatically. Two successIve frames can share one
flag for a clOSing flag of the first frame and for the opening
flag of the next frame, If the "FF" I"F" control bit In the con-
trol register IS reset
Control (CI Field - The 8 bits follOWing the address field IS
the control (link control I field When the Extended Control
Field bit In control register #3 IS selected, the C-fleld IS ex-
tended to 16 bits

Information (I) Field - The I-field follows the C-f,eld and

precedes the FCS field The I-field contains "data" to be
transferred but IS not always necessarily contained In every
frame The word length of the I-field can be selected from 5
•
The receiver searches for a flag on a blt-by-blt basIs and to 8 bits per byte by control bits In control register #4 The
recognIZes a flag at any time The receiver establishes the I-field Will continue until It IS terminated by the FCS and clos-
frame synchronization With every flag The flags mark the Ing flag The receiver has the capability to handle a "partial"
frame boundary and reference for each field but they are not last byte. The last informatIOn byte can be any word length
transferred to the Rx FI FO The detection of a flag IS In- between 1 and 8 bits If the last byte In the I-field IS less than
dicated by the Flag Detect output and by a status bit In the the selected word length, the receiver Will nght Justify the
status register received bitS, fill the remaining bits of the receiver shift
register With zeros, and transfer a full byte to the Rx FIFO
Order of Bit Transmission - Address, control and Infor- Regardless of selected byte length, the ADLC Will transfer 8
mation field bytes are transferred between the MPU and the bits of data to the data bus Unused bits for word lengths of
ADLC In parallel by means of the data bus The bit on DO 5, 6, and 7 Will be zeroed
(data bus bit 0, pin 221 IS senally transmitted firSt, and the
first senally received bit IS transferred to the MPU on DO The Logical Control (LCI Field - When the Logical Control
FCS field IS transmitted and received MSB first Field Select bit, In control register #3, IS selected the ADLC
separates the I-field Into two sub-fields The first sub-field IS
Address (AI Field - The 8 bits follOWing the opening flag the Logical Control field and the follOWing sub-field IS the
are the address (AI field The A-field can be extendable If the "data" portion of the I-field The logical control field IS 8 bits
Auto-Address Extend Mode IS selected In control register #3 and follows the C-fleld, which IS extendable by octets, If It IS
In the Address Extend Mode, the first bit (bit 01 In every ad- selected The last bit (bit 71 IS the extend control bit, and If It
dress octet becomes the extend control bit When the bit IS IS a "1", the LC-f,eld IS extended one octet
"0", the ADLC assumes another address octet Will follow,
and when the bit IS "1", the address extension IS terminated NOTE
A "null" address (all "O's"l does not extend. In the receiver,
the Address Present status bit distingUishes the address field Hereafter the word "Information field" or "I-field" IS
from other fields When an address byte IS available to be used as the data portion of the information field, and
read In the receive FIFO register, the Address Present status excludes the logical control field ThiS IS done In order
bit IS set and causes an Interrupt (,f enabledl The Address to keep the consistency of the meaning of "Informa-
Present bit IS set for every address octet when the Address tIOn field" as specified In SDLC, HDLC, and ADCCP
Extend Mode IS used standards

4-555
 MC6854- MC68A54- MC68B54

Frame Check Sequence (FCS) Field - The 16 bits of the aborted frame has not transferred to the M PU
preceding the closing flag is the FCS field. The FCS is the yet. The ADLC clears the aborted frame data In the
"cyclic redundancy check character (CRCC)''' The FIFO and clears flag synchronization. Neither an inter-
polynomial x16 + x12 + x5 + 1 is used both for the transmitter rupt nor a stored status occurs. The status indication
and receiver. Both the transmitter and receiver polynomial IS the same as (11 above.
registers are Initialized to all "l's" prior to calculation of the 3. An abort "in frame" after 26 bits or more are received
FCS. The transmitter calculates the FCS on all bits of the ad- after an opening flag - under thiS condition, some
dress, control, logical control (if selected I , and information fields of the aborted frame might have been transfer-
fields, and transmits the complement of the resulting re- red onto the data bus. The abort status is stored in the
mainder as FCS. The receiver performs the similar computa- receiver status register and the data of the aborted
tion on all bits of the address, control, logical control (if frame In the ADLC is cleared The synchronization is
selected I , Information, and received FCS fields and com- also cleared.
pares the result to FOB8 I Hexadecimal!. When the result
matches FOB8, the Frame Valid status bit is set In the status Idle and Time Fill - When the transmitter IS In an "out of
register. If the result does not match, the Error status bit IS frame" condition (the transmitter is not iransmlttlng a
set. The FCS generation, transmission, and checking are framel, It IS In an idle state. Either a series of contiguous flags
performed automatically by the ADLC transmitter and Itlme filii or a mark Idle (consecutive "l's" on a blt·by-bit
receiver. The FCS field IS not transferred to the Rx FIFO. basis I is selected for the transmiSSion In an Idle state by the
Flag/Mark Idle control bit. When the receiver receives 15 or
Invalid Frame - Any valid frames should have at least the more consecutive "l's", the Receive Idle status bit is set and
A-field, C-field, and FCS field between the opening flag and causes an interrupt. The flags and mark Idle are not transfer-
the clOSing flag. YVhen Invalid frames are received, the ADLC red to the Rx FI FO.
handles them as follows.

I 1. A short frame which has less than 25 bits between

flags - the ADLC Ignores the short frame and Its
reception is not reported to the MPU
2 A frame less than 32 bits between the flags, or a frame
32 bits or more With an extended A-field or C-f,eld that
is not completed. - This frame IS transferred Into the tNITIALIZATION
OPERATION

Rx FIFO. The FCS/IF Error status bit indicates the DUring a power-on sequence, the ADLC IS reset via the
reception of the Invalid frame at the end of the frame. RESET Input and Internally latched In a reset condition to
3. Aborted Frame - The frame which IS aborted by prevent erroneous output tranSitions. The four control
receiving an abort or DCD failure IS also an Invalid registers must be programmed prior to the release of the
frame. Refer to "Abort" and "DCD status bit". reset condition. The release of the reset condition IS perform-
ed via software by writing a "0" Into the Rx RS control bit
Zero Insertion and Zero Deletion - The Zero insertion and (receiver! and/or Tx RS control bit Itransmltterl. The release
deletion, which allows the content of the frame to be of the reset condition must be done after the RESET input
transparent, are performed by the ADLC automatically. A has gone high
binary 0 IS Inserted by the transmitter after any succession of At any time dunng operation, writing a "1" Into the Rx RS
five "l's" within a frame lA, C, LC, I, and FCS fleldl. The control bit or Tx RS control bit causes the reset condition of
receiver deletes a binary 0 that follows successive five con- the receiver or the transmitter.
tinUOUS "1' S" within a frame.
TRANSMITTER OPERATION
Abort - The function of prematurely terminating a data The Tx FIFO register cannot be pre-loaded when the
link IS called "abort." The transmitter aborts a frame by transmitter IS In a reset state. After the reset release, the
sending at least eight consecutive "1' s" Immediately after Flag/Mark Idle control bit selects either the mark Idle state
the Tx Abort control bit in control register #4 IS set to a "1". (,nact,ve Idle) or the Flag "time fill" lactive Idlel state. ThiS
ITx FIFO IS also cleared by the Tx Abort control bit at the active or inactive mark Idle state Will continue until data IS
same time. I The abort can be extended up to (at leastl 16 loaded Into the Tx FIFO.
consecutIVe "1 '5", If the Abort Extend control bit In the con- The availability of the Tx FIFO IS indicated by the TDRA
trol register #4 IS set when an abort IS sent. ThiS feature is status bit under the control of the 2-Byte/l-Byte control bit
useful to force mark Idle transmission Reception of seven or TDRA status is Inhibited by the Tx RS bit or CTS Input being
more consecutive "l's" IS Interpreted as an abort by the high. When the l-Byte mode IS selected, one byte of the
receiver. The receiver responds to a received abort as FIFO IS available for data transfer when TDRA goes high
follows. . When the 2-Byte mode IS selected, two successive bytes can
1. An abort in an "out of frame" condition - an abort be transferred when TDRA goes high
during the idle or time fill has no meaning. The abort The first byte IAddress field I should be wntten Into the Tx
reception IS Indicated in the status register as long as FIFO at the "Frame Continue" address. Then the transmis-
the abort condition continues; but neither an Interrupt sion of a frame automatically starts. If the transmitter IS In a
nor a stored condition occurs. The abort indication mark Idle state, the transfer of an address causes an opening
disappears after 15 or more consecutive "l's" are flag within two or three transmitter clock cycles. If the
received IReceived Idle status IS set.) transmitter has been In a time fill state, the current time fill
2. An abort "In frame" after less than 26 bits are received flag being transmitted IS assumed as an opening flag and the
after an opening flag - under this condillon, any field address field Will follow It

4-556
MC6854-MC68A54-MC68B54

FIGURE Sa - ADLC TRANSMITTER STATE DIAGRAM

(Cibi ref..... to control register bit)

FIFO Empty
Data Being Transmitted:
F = flag
A"" address
C = (link) control
LC = logical control (optional)
I = information
FCS "" frame check sequence
ABT = abort
Flag Idle (C2b2 "" 1)

•
C4b2

C3b2

C3b1 Extend Control

(1 Byte only)

4-557
 MC6854-MC68A54-MC68B54

FIGURE 8b - ADLC RECEIVER STATE DIAGRAM

II

Address Extend

·Out·of·freme Abort (No IRQ)

A frame continues as long as dats is written into the Tx causes the last character to be transmitted and the FCS field
FIFO at the "Frame Continue" address. The ADLC internally to automatically be appended along with a closing flag. Data
keeps track of the field sequence in the frama. The frame for- for a new frame can be loaded into the Tx FIFO immediately
mat is described in the "FRAME FORMAT" section. after the old frame data. if TDRA is high. The closing Flag
The frame is terminated by one of two methods. The most can serve as the opening Flag of the next frame or separate
efficient way to terminate the frames from a software stand- opening and closing Flags may be transmitted. If a new
point is to write the last data character into the Transmit frame is not ready to be transmitted. the ADLC will
FIFO "Frame Terminate" address (RS1. RSO= 11> rather automatically transmit the Active (Flagl or Inactive (Mark)
than the Transmit FIFO "Frame Continue" address (RS1. Idle condition.
RSO= 10), An alternate method is to follow the last write of If the Tx FIFO becomes empty at any time during frame
data in the Tx FIFO "Frame Continue" address with the set- transmission (the FIFO has no data to transfer Into transmit-
ting of the Transmit Last Data control bit. Either method ter shift register during transmission of the last hl!lf of the

4-558
MC6854- MC68A54- MC68B54

next to last bit of a word), an underrun will occur and the read on consecutive E cycles. Address Present proVides for'
transmitter automatically terminates the frame by transmit- byte transfers Oflly.
ting an abort. The underrun state IS Indicated by the Tx The sequence of each field In the received frame IS
Underrun status bit. automatically handled by the ADLC. The frame format IS
Any time the Tx ABORT Control bit IS set, the transmitter described in the "FRAME FORMAT" section.
immediately aborts the frame (transmits at least 8 con- When a clOSing flag IS received, the frame is terminated.
secutive ""s") and clears the Tx FIFO If the Abort Extend The '6 bits preceding the closing flag are regarded as the
Control bit IS set at the time, an Idle (at least '6 consecutive FCS and are not transferred to the MPU. Whatever data is
""s") IS transmitted. An abort or idle in an "out of frame" present in the most-Significant byte portion of the receiver
condition can be useful to gain 8 or '6 bits of delay. (For an buffer register it is right justified and transferred to the Rx
example, see "Programming Considerations.") FIFO. The frame boundary pOinter, which IS explained in the
The CTS (Clear-to-Send) input and RTS (Request-to- "Rx FIFO REGISTER" section, is set simultaneously in the
Send) output are provided for a MODEM or other hardware Rx FIFO. The frame boundary pointer sets the Frame Valid
Interface. status bit (when the frame was completed With no error) or
The TDRA! FC status bit (when selected to be Frame the FCSIIF Error Status bit (when the frame was completed
Complete Status) can cause an Interrupt upon frame com- With error) when the last byte of the frame appears at the last
pletion h.e., a flag or abort completion I. location of the Rx FIFO. As long as the Frame Valid or
Details regarding the Inputs and outputs, status bits, con- FCSIIF Error status bit is set, the data transfer from the
trol bits, and FI FO operation are described In their respective second location of the Rx FIFO to the last location of the Rx
sections. FIFO IS inhibited. '
Any time the Frame Discontinue control bit IS set, the
RECEIVER dPERATION ADLC discards the current frame data in the ADLC without

•
Data and a pre-synchrOnized clock are proVided to the dropping flag synchrOnization. This feature can be used to
ADLC receiver section by means of the Receive Data (RxD) Ignore a frame which IS addressed to another station.
and Receive Clock (RxC) Inputs. The data IS a continuous The reception of an abort or idle is explained in the
stream of binary bits With the characteristic that a maximum "FRAME FORMAT" section. The details regarding the In-
of five ""s" can occur in succession unless Abort, Flag, or puts, outputs, status bits, control bits, and Rx FIFO opera-
Idling condition occurs. The receiver continuously (on a blt- tion are described In their respective sections.
by-bit basis) searches for Flags and Aborts.
When a flag is detected, the receiver establishes frame
synchronization to the flag timing. If a series of flags is LOOP MODE OPERATION
received, the receiver resynchronizes to each flag. The ADLC In the loop mode, not only performs the
If the frame IS terminated before the Internal buffer time transmission and receiVing of data frames in the manner
expires (the frame data IS less than 25 bits after an opening previously described, but also has additional features for
flag), the frame is simply Ignored. NOise on the data Input gaining and relinqUishing loop control. In Figure 9a, a con-
(RxDl dUring time fill can cause this kind of Invalid frame. figuration is shown which depicts loop mode operation. The
The received serial data enters a 32-bit shift register (clock- system configuration shows a pnmary station and several
ed by RxC) before It IS transferred into the Rx Data FIFO. secondary stations. The loop IS always under control of the
Synchronization IS established when a Flag IS detected In the primary station. When the primary wants to receive data, It
first eight locations of the shift register. Once synchrOniza- transmits a Poll sequence and allows frame transmission to
tion has been achieved, data IS clocked through to the last secondary stations on the loop. Each secondary IS In series
byte location of the shift register where it is transferred byte- and adds one bit of delay to the loop. Secondary A In the
per-byte Into the Rx Data FIFO. The Rx Data FIFO IS clocked figure receives data from the primary via ItS Rx Data Input,
by E to cause received data to move through the FIFO to the delays the data' bit, and transmits It to secondary B via ItS
last empty register location. The Receiver Data Available Tx Data Output. Secondaries B, C, and 0 operate In a Similar
status bit (RDA) Indicates when data is present In the last manner. Therefore, data passes through each secondary and
register (Register '3) for the '-Byte Transfer Mode. The IS received back by the primary controller.
2-Byte Transfer Mode causes the RDA status bit to Indicate Certain protocol rules must be followed In the manner by
data IS available when the last two FI FO register locations which the secondary station places Itself on-loop (connects
(Registers #2 and '3) are full. If the data character present In ItS transmitter output to the loop), goes active on the loop
the FIFO is an address octet, the status register Will exhibit (starts transmitting Its own station's data on the loop), and
an Address Present status condition. Data being available in goes off the loop (disconnects Its transmitter output). Other-
the Rx Data FIFO causes an interrupt to be Initiated (assum- wise loop data to other stations down loop would be In-
ing the receiver interrupt IS enabled, RIE= "'''1. The MPU terfered. The data stream always flows the same way and
will read the ADLC Status Register as a result of the Interrupt the order in which secondary terminals are serviced IS deter-
or in its turn In a polling sequence. RDA or Address Present
will indicate that receiver data IS available and the MPU
should subsequently read the Rx Data FIFO register. The in-
times the delay through the loop. Should it exceed n
times, where n IS the number of secondary terminals on the
+'
mined by the hardware configuration. The primary controller
bit

terrupt and status bit Will then be reset automatically. If more loop, it Will indicate a loop failure. Control is transferred to a
than one character had been received and was resident in the secondary by transmitting a "Go Ahead" signal following the
Rx Data FIFO, subsequent E clocks will cause the FIFO to clOSing Flag of a polling trame (request for a response from
update and the RDA status bit and Interrupt will again be the secondary) from the primary station. The "Go Ahead"
SET. In the 2-Byte Transfer Mode both data bytes may be from the pnmary is a "0" and seven ""s" followed by mark

4·559
 MC6854-MC68A54- MC68B54

FIGURE Sa - TYPICAL LOOP CONFIGURATION

Primary "Poll Frame" + "Secondary

Controller Station Fram .... + "1111111' .. ,"
(Non-loop)

"Poll Frame" + "0111111' .. ,"

Secondary Stations (A,B,C,D)

Operate In Loop Mode

FIGURE 9b - EXAMPLE OF EXTERNAL LOOP LOGIC

• AOLC r- - - - - - - - - - - - - - - --,
I
I
,---------+--< UP-Loop Data
RxO

DOwn Loop Data

TxO

LOC
I
IL ________________ -.J

Idling. The pnmary can abort Its response request by inter- through gate A to the down Loop statIons. Any Up-Loop
rupting its Idle wIth flags. The secondary should ImmedIately transmission WIll be receIved by the ADLC The Loop
stop transmissIon and return control back to the pnmary Mode/Non-Loop Mode Control bIt (bIt 5 m Control RegIster
When the secondary completes ItS frame, a closIng flag is 3) must be set to place the ADLC In the Loop Mode. The
transmItted followed by all "1's". The primary detects the ADLC now monitors ItS Rx Data mput for a string of seven
final 01111111 .. ("Go Ahead" to the pnmary) and control is consecutIve "1's" whIch WIll allow a statIon to go on Ime.
gIven back to the primary. Note that, If a down-loop secon- The Loop operatIon may be monItored by use of the Loop
dary (e g., station D) needs to msert informatton follOWIng Status bIt m Status RegIster 1 After power up and reset, thIS
an up-loop statIon (e.g., station A), the go ahead to statIon bIt IS a zero. When seven consecutIve ""s" are receIved by
D IS the last "0" of the closIng flag from statIon A fOllowed the ADLC the LOC/DTR output WIll go to a low level, disabl-
by""s". Ing gate A (refer to FIgure 9b), enabling gate B and connec-
The ADLC In the primary statIon should operate In a non- tIng the ADLC Tx Data output to the down Loop statIons.
loop full-duplex mode. The ADLC in the secondanes should . The up Loop data IS now repeated to the down Loop stattons
operate m a loop mode, monttonng up-loop data on ItS vIa the ADLC. A 1-blt delay IS mserted In the data (m NRZI
receiver data mput. The ADLC can recognize the necessary mode, there will be a 2-blt delay) as It cIrculates through the
sequences In the data stream to automatically go on/off the ADLC. The ADLC IS now on-line- and the Loop Status bIt m
loop and to Insert its own statIon data. The procedure IS the Status RegIster 1 WIll be at a one.
follOWIng and is summarized in Table 1.
(2) Go Active after Poll - The receIver sectIon WIll montlor
(1) Go On-Loop - When the ADLC powers up, the ter- the up-link data for a general or addressed poll command
minal station will be off line. The first task IS to become an and the Tx FIFO should be loaded WIth data so that when the
actIve termmal on the loop. The ADLC must be connected to go ahead sequence of a zero followed by seven ''1's''
a Loop Link via an external sWItch as shown In FIgure Sa. 101111111---) IS detected, transmIssion can be InitIated Im-
After a hardware reset, the ADLC LOC/i5iR Output will be mediately. When the polling frame IS detected, the Go-
In the high state and the up-loop receive data repeated Active-On-Poll control bit must be set (bIt 6 In Control

4-560
MC6854- MC68A54- MC68854

TABLE 1 - SUMMARY OF LOOP MODE OPERATION

STATE RX SECTION TX SECTION LOOP

STATUS BIT

OFF-LOOP Rx section receives data from loop and searches Inactive "a"
tor 7 "1'5" (when On-Loop Control bit set) to go 1) NRZ MODE Tx data output is maintained
ON-LOOP "h igh" (mark l.
2) NRZI MODE. Tx data output reflects the Rx
data input state delayed by one
bit time (Not normally con-
nected to loop.) The N AZ, data
IS Internally decoded to provide
error-free transitions to On-Loop
mode.

ON-LOOP 1) When Go-Active on poll bit IS set, Rx section

searches for 01111111 pattern (the EOP or 'Go
Inactive
1) NRZ MODE Tx data output reflects Ax data "'"
Ahead') to become the active terminal on the input state delayed one bit time.
loop 2) NRZI MODE. Tx data output reflects Ax data
2) When On-Loop control bit IS reset, Rx section input state delayed 2 bit times
searches for 8 "1's" to go OFF·Loop

ACTIVE Rx section searches for flag (an Interrupt from the Tx data Originates wlthm ADLC until Go Active on "0"
loop controller) at Rx data Input Received flag Poll bit IS reset and a flag or Abort IS completed
causes FO output to go low I RO IS generated If Then returns to ON-Loop state

I
R'iE and FDSE control bits are set

Register 3) A maximum of seven bit times are available to (4) Go Off-Loop - The ADLC can drop off the Loop (go
set this control bit after the clOSing flag of the poll When the off-Ilnel similar to the way It went on-line When the Loop
Go-Ahead IS detected by the receiver, the ADLC will On-Line control bit IS reset the ADLC receiver section looks
automatically change the seventh one to a zero so that the for eight successive "l's" before allOWing the LOC/DTR out-
repeated sequence out gate B In Figure 9b IS now an opening put to return high (the inactive state I Gate A In Figure 9b
flag sequence (011111110) Transmission now continues will be enabled and gate B disabled allOWing the loop to
from the Tx FIFO with data (address, control, etc) as maintain continuity Without disturbance The Loop Status
previously descnbed When the ADLC has gone actlve-on- bit will show an off-line condition (logical zerol
poll, the Loop Status bit In Status Register 1 will go to a
zero The receiver searches for a flag, which indicates that
the pnmary station IS Interrupting the current operation SIGNAL DESCRIPTIONS

(3) Go Inactive when On-Loop - The Go-Actlve-On-Poll All Inputs of ADLC are high-Impedance and TTL-
control bit may be RESET at any time dunng transmission compatible level Inputs All outputs of the ADLC are com-
When the frame IS complete (the clOSing Flag or abort IS patible With standard TTL Interrupt Request IIRQI,
transmlttedl, the Loop IS automatically released and the sta- however, IS an open-drain output Ina Internal pullupl
tion reverts back to being Just a 1-blt delay In the Loop,
repealing up-link data If the Go-Actlve-On-Poll control bit IS INTERFACE FOR MPU
not reset by software and the final frame IS transmitted
lFlag/Mark Idle b,t=O), then the transmitter Will mark Idle Bidirectional Data Bus (DO-D7) - These data bus I/O
and Will not release the loop to up-loop data A Tx Abort ports allow the data transfer between ADLC and system bus
command would have to be used In thiS case In order to go The data bus dnvers are three-state deVices that remain In
inactive when on the loop Also, If the Tx FIFO was not the high-Impedance (offl state except when the MPU per-
preloaded with data (address, control, etc I pnor to chang- forms an ADLC read operation
Ing the "Go Ahead Character" to a Flag, the ADLC Will either
transmit flags (active Idle characterl until data IS loaded Enable Clock (EI - E activates the address Inputs (CS,
(when Flag/ Mark Idle Control bit IS high) or Will go Into an RSO, and RSlI and R/W Input and enables the data transfer
underrun condition and transmit an Abort (when Flag/Mark on the data bus E also moves data through the Tx FIFO and
Idle control bit IS lowl When an abort IS transmitted, the Go- Rx FIFO E should be a free-running clock such as the
Actlve-on-Poll control bit IS reset automatically and the MC6800 MPU system clock
ADLC reverts to ItS repeating mode, (TxD = delayed RxDJ
When the ADLC transmitter lets go of the loop, the Loop Chip Select (CS) - An ADLC read or write operation IS
Status bit will return to a "1", indicating normal on-loop enabled only when the CS Input IS low and the E clock Input
retransmisSion of up-loop data IS high (E·ESI

4-561
 MC6854· MC68A54· MC68B54

Register Selects (RSO, RS1) - When the Register Select PERIPHERAL/MODEM CONTROL
inputs are enabled by (E.CS), they select internal registers in
conjunction with the Read/Write input and Address Control Request-to-Send Output (RTS) - The Request-to-Send
bit (control register 1, bit OJ. Register addressing IS defined in output is controlled by the Request-to-Send control bit in
Table 2. conjunction with the state of the transmitter section. When
the RTS bit goes high, the RTS output Islorced low. When
Read/Write Control Line (R/W) - The R/W input con- the RTS bit returns low, the RTS output remains low until
trols the direction of data flow on the data bus when it is the end 01 the frame and there IS no further data in the Tx
enabled by (E.CSI. When R/W is high, the I/O Buffer acts FIFO for a new frame. The positive transition of RTS occurs
as an output driver and as an input buffer when low. It also alter the completion of a Flag, an Abort, or when the RTS
selects the Read Only and Write Only registers within the control bit IS reset dunnJ!...! mark Idling state. When the
ADLC. RESET Input IS low, the RTS output goes high.

Reset Input (RESET) The RESET Input provides a Clear-to-Send Input (CTS) -. The CTS Input provides a
means of resetting the ADLC from a hardware source. In the real-time inhibit to the TDRA status bit and Its associated In-
"low state," the RESET input causes the following: terrupt. The positive transition of CTS IS stored Within the
'Rx Reset and Tx Reset are SET causing both the ReceiV- ADLC to ensure ItS occurrence Will be acknowledged by the
er and Transmitter sections to be held In a reset condi- system. The stored CTS information and ItS associated IRQ
tIOn. (if enabled) are cleared by wntlng a "1" In the Clear Tx
'Resets the following control bits: Transmit Abort, RTS, Status bit or In the Transmitter Reset bit.
Loop Mode, and Loop On-Llne/DTR.
'Clears all stored status condition of the status registers. Data-Carrier-Datset Inupt (DCD) - The DCD Input prCil-

I
'Outputs: RTS and LOC/DTR go high TxD goes to the vldes a real-tIme inhibit to the receiver section. A high level
mark state ("l's" are transmittedl. on the DCD Input resets and Inhibits the receiver register,
When RESET returns "high" (the inactive state) the but data In the Rx FI Fa from a prevIous frame is not disturb-
transmitter and receiver sections will remain In the reset state ed. The positive transition of DCD IS stored Within the ADLC
until Tx Reset and Rx Reset are cleared via the data bus to ensure that its occurrence will be acknowledged by the
undel software control. The Control Register bits affected by system. The stored DCD information and ItS associated IRQ
RESET cannot be changed when RESET is "low." (,f enabled) are cleared by means of the Clear Rx Status Con-
trol bit or by the Rx Reset bit.
Interrupt Request Output (IRQ) - IRQ will be low if an in-
terrupt situation eXists and the appropriate Interrupt enable loop On-Line Control/ Data Terminal Ready Output
has been set. The Interrupt remains as long as the cause for (LOC/DTR) - The LOC/DTR output serves as a DTR out-
the interrupt is present and the enable is set. IRQ will be low put in the non-loop mode or as a Loop Control output In the
as long as the IRQ status bit IS set and is high il the IRQ loop mode. When LOC/DTR output performs the DTR func-
status bit is not set. tion, It is turned on and off by means of the LOC/DTR con-
trol bit. When the LOC/ DTR control bit IS high the DTR out-
CLOCK AND DATA OF TRANSMITTER AND RECEIVER put Will be low. In the loop mode the LOC/ DTR output pro-
vides the means 01 controlling the external loop Interface
Transmitter Clock Input (TxC) - The transmitter shilts hardware to go On-line or OfHne. When the LOCI DTR con-
data on the negative transition 01 the TxC clock input. When trol bit IS SET and the loop has "Idled" lor 7 bit times or more
the Loop Mode or Test Mode IS selected, TxC should be the (RxD=Ollllll1...), the LOC/DTR output Will go low (on-
same frequency and phase as the RxC clock The data rate of line) The RESET Input being low Will cause the LOC/DTR
the transmitter should not exceed the E frequency. output to be high.

Receiver Clock Input (RxC) - The receiver samples the Flag Datect Output (FD) - An output to ,nd,cate the
data on the positive transition of the RxC clock RxC should reception of a flag and initiate an external time-out counter
be synchronized with receive data externally. for the loop mode operation. The FD output goes low for 1
bit time beginning at the last bit of the flag character, as
Transmit Data Output (TxD) - The senal data from the sampled by the receiver clock (RxCI.
transmitter IS coded In NRZ or NRZI (Zero Complement) data
format.

Receiver Date Input (RxD) - The senal data to be re- DMA INTERFACE
ceived by the ADLC can be coded ,n NRZ or N RZI (Zero
Complementl data format. The data rate of the receiver Receiver Data Service Request Output (RDSR) - The
should not exceed the E frequency. If a partial byte receptIOn RDSR Output IS provided primarily for use In DMA Mode
is possible at the end of a frame, the maximum data rate 01 operation and indicates (when high) that the Rx FIFO re-
the receiver IS Indicated by the following relationship: quests service (RSDR output reflects the RDA status bit
regardless of the state of the RDSR mode control bit In
fRxCS - - ' - - - CR1). If the prioritized Status Mode is selected, RDSR Will
2tE + 300 ns be inhibited when any other receiver status conditions are
where tE is the period 01 E. present. RDSR goes low when the Rx FIFO IS read

4-562
MC6854-MC68A54-MC68B54

Transmitter Data Service Request Output (TDSR) - The used for the data transfer. Each register has pOinter bits
TDSR Output is provided for DMA mode operation and in- which point the frame boundary. When these pointers ap-
dicates (when highl that the Tx FIFO request service pear at the last FIFO location, they update the Address Pre-
regardless of the state of the TDSR Mode Control bit In CR1 sent, Frame Valid, or FCS/IF Error status bits.
TDSR goes low when the Tx FIFO is loaded. TDSR is In- The RDA,status bit indicates the state of the Rx FIFO.
hibited by: the Tx RS control bit being SET, RESET being When RDA status bit is "1", the Rx FIFO IS ready to be read.
low, or CTS being high. If the prioritized status mode IS us- The RDA status is controlled by the 2-Byte/1-Byte control
"ed, Tx Underrun also inhibits TDSR. TDSR reflects the bit. When overrun occurs, the data In the first byte of the Rx
TDRA status bit except In the FC mode. In the FC mode the FIFO are not longer valid.
TDSR line IS inhibited. Both the Rx Reset bit and RESET input clear the Rx FIFO.
Abort ("in Frame") and a high level on the DCD input also
ADLC REGISTERS clears the Rx FIFO, but the last bytes of the previous frame,
Eight registers In the ADLC can be accessed by means of which are separated by the frame boundary pointer, are not
the MPU data and address buses. The registers are defined disturbed.
as read-only or write-only according to the direction of infor-
mation flow. The addresses of these registers are defined in
Table 2. The transltter FI FO register can be accessed by two TRANSMITTER DATA FIRST-IN FIRST-OUT REGISTER
different adgresses, the "Frame Terminate" address and the
"Frame Continue" address. (The function of these addresses Tx FIFO - The Tx FIFO consists of three B-bit registers
are discussed In the FIFO section.! which are used for buffer storage of data to be transmitted.
Data is always transferred from a full register to an empty ad-

•
TABLE 2 - REGISTER ADDRESSING jacent register; the transfer occurs on both phases of the E
Input clock. The Tx FIFO can be addressed by two different
Add,ess
Control Bit register addresses, the "Frame Continue" address and the
Register Selected R/W RSl RSO (el bO) "Frame Terminate" address. Each register has pOinter bits
Write Control Register #1 0 0
which point to the frame boundary. When a data byte IS writ-
0 X
ten at the "Frame Continue" address, the pointer of the first
Write Control Register #2 0 0 1 0
FI FO register is set. When a data byte is written at the
Write Control Register #3 0 0 1 1 "Frame Terminate" address, the pointer of the first FIFO
Write Transmit FIFO 0 1 0 X register is reset. Rx RS control bit or Tx Abort control bit
(Frame Continue) resets all pointers. The pointer will shift through the FIFO.
Write Transmit FIFO 0 1 1 0 When a pOSitive transition is detected at the third location of
(Frame Terminate) FIFO, the transmitter initiates a frame with an open flag.
When the negative transition is detected at tt-e third location
Write Control Register #4 0 1 1 1
of FIFO, the transmitter closes a frame, appending the FCS
Read Status Register #1 1 0 0 X
and closing Flag to the last byte.
Read Status Register #2 1 0 1 X The Tx last control bit can be used Instead of uSing the
Read Receiver FIFO 1 1 X X "Frame Terminate" address. When the T x last control bit IS
set with a "1" , the logiC searches the last byte location In the
FIFO and resets the pointer in the FIFO register.
The status of Tx FIFO is Indicated by the TDRA status bit.
RECEIVER DATA FIRST-IN FIRST-OUT REGISTER When TDRA IS "1", the Tx FIFO is available for loading data.
Rx FIFO - The Rx FI FO consists of three B-bit registers The TDRA status IS controlled by the 2-Byte/1-Byte control
which are used for the buffer storage of received data. Data bit. The Tx FIFO is reset by both Tx Reset and RESET input.
bytes are always transferred from a full register to an adla- During this reset condition or when CTS input is high, the
cent empty register; and both phases of the E Input clock are TDRA status bit is suppressed and data loading is Inhibited.

4-563
 MC6854-MC68A54-MC68B54

ADLC INTERNAL REGISTER STRUCTURE

RS1 RSO-OO RS1 RSO -01 RS1 RSO= 10 RS1 RSO -11
Receive, Data
Bit # Status Register #1 Status Register #2 Register

.~

'i
0
1
ADA
Status #2
Aead Aequest
Address Present
Frame Valid
BitO
Bit 1

II: 2 Loop Inactive Idle Received Bit 2

~ 3 F lag Detected Abort ReceIVed Bit 3

0 (When Enabled) Same as AS1, ASO "" 10

"II:: 4 CTS FCS Error Bit4

5 Tx Underrun DCD Bit 5
6 TDAA/Frame Rx Overrun Blt6
C::omplete
7 IAQ Present ADA (Receiver Data Available) Bit 7

Transmitter Transmitter:
Date Data
Control Registar #1 Control Register #2 Control Register #3 (Continue Data) (Last Data) Control Register #4
Bit # (C1bO = 0) (C1bO -1) (C1bO -0) (C1bO= 1)
0 Address Control (AC) PriOritized Status Logical Control BltO BltO Double Flag/Single

.
I
Enable Field Select Flag Interframe
f Control
t: 1 Receiver Interrupt 2 Byte/1 Byte Extended Control Bit 1 Bit 1 Word Length Select
'f Enable (A IE) Transfer Field Select Transmit #1
II:
> 2 Transmitter Interrupt Flag/Mark Idle Auto, Address Bit 2 Bit 2 Word Length Select
'E Enable (TIE) ExtenSion Mode Transmit #2
0
3 ADSA Mode (DMA) Frame Completel 01/11 Idle Bit 3 Bit 3 Word Length Select
.~
TDRA Select Receive #1
~
4 TDSA Mode (DMA) Transmit Last Data F lag Detected Blt4 Bit 4 Word Length Select
Status Enable Receive #2
5 Rx Frame C LA A x Status Loop/Non-Loop Mode Bit 5 Bit 5 Transmit Abort
Discontinue
6 Ax AESET CLA Tx Status Go Active on Poll/Test Bit 6 Bit 6 Abort Extend
7 Tx AESET ATS Control Loop On-Line Bit 7 Bit 7 NAZI/NAZ
ControlDTR

4-564
MC6854-MC68A54-MC68B54

CONTROL REGISTERS

CONTROL REGISTER 1 (CR1)

7 6 5 4 3 2 1 0
RSl RSO R/W AC TxRS RxRS Dlscontmue TDSR RDSR TIE RIE AC
0 0 0 X Mode Mode

bO - Address Control (AC) - AC provides another RS b5 - Rx Frame Discontinue (DISCONTINUE) - When

•
(Register Selectl signal I"ternally The AC bit IS used In con- the DISCONTINUE bit IS set, the currently received frame IS
junction with RSO, RS1, and R/W Inputs to select particular Ignored and the ADLC discards the data of the current
registers, as shown In Table 2 frame The DISCONTINUE bit only discontinues the current-
ly received frame and has no affect on subsequent frames,
bl Receiver Interrupt Enable (RIE) RIE even If a follOWing frame has entered the receiver section
enablesl disables the Interrupt request caused by the receiver The DISCONTINUE bit IS automatically reset when the last
section 1 enable, 0 disable byte of the frame IS discarded When the Ignored frame IS
aborted by receiving an Abort or DCD failure, the DISCON-
b2 - Transmitter Interrupt Eanble (TIE) TIE TI NU E bit IS also reset
enablesl disables the Interrupt request caused by the
transmitter 1 enable, 0 disable b6 - Receiver Reset (Rx RS) - When the Rx RS bit IS
"1", the receiver section stays In the reset condition Ali
b3 - Receiver Data Service Request Mode (RDSR reclever sections, Including the Rx FIFO register and the
MODE) - The RDSR MODE bit provides the capability of receiver status bits In both status registers, are reset (During
operation with a bus system In the DMA mode when used In reset, the stored DCD status IS reset but the DCD status bit
conjunction with the prioritIZed status mode When RDSR follows the DCD Input) Rx RS IS set by forcing a low level on
MODE IS set, an Interrupt request caused by RDA status IS the RESET Input or by writing a "1" Into the bit from the
inhibited, and the ADLC does not request data transfer via data bus Rx RS must be reset by writing a "0" from the data
the IRQ output bus after RESET has gone high

b4 - Transmitter Data Service Request Mode (TDSR b7 - Transmitter Reset (Tx RS) - When the Tx RS bit IS
MODE) - The TDS R MODE bit provides the capability of "'1", the transmitter section stays In the reset condition and
operation with a bus system In the DMA mode when used In transmits marks ("1's"l. All transmitter sections, including
conjunction with the Prioritized status mode When TDSR the Tx FIFO and the transmitter status bitS, are reset (FIFO
MODE IS set, an Interrupt request caused by TDRA status IS cannot be loaded) DUring reset, the stored CTS status IS
inhibited, and the ADLC does not request a data transfer via reset but the CTS status bit follows the CTS Input Tx RS IS
the IRQ output set by forcing a low level on the RESET Input or by writing a
"1" from the data bus It must be reset by writing a "0" after
RESET has gone high

4-565
 MC6854- MC68A54- MC68B54

CONTROL REGISTER 2 (CR2)

7 6 5 4 3 2 1 0
RS1 RSO RM AC RTS CLR CLR Tx FCITDRA F/M 2/1 PSE
0 1 0 0 TxST RxST Last Select Idle Byte

bO - Prioritized Status Enable IPSE) - When the PSE bit after loading the last data byte and before the Tx FIFO emp-
IS SET, the status bits In both status registers are prioritized ties. When the Tx Last bit IS set, the AOLC assumes the byte
as defmed In the Status Register section. When PSE is low, IS the last byte and terminates the frame by appending CRCC
the status bits indicate current status without bit suppression and a closing Flag. This control bit IS useful for OMA opera-
by other status bits. The exception to this rule is the CTS tion. Tx Last bit automatically returns to the "0" state.

I status bit which always supresses the TORA status.

b1 - 2-Byte/1-Byte Transfer (2/1 Byte) - When the 2/1

Byte bit IS RESET the TORA and ROA status bits then will In-
dlcate the availability of their respective data FIFO registers
b5 - Clear Receiver Status (CLR Rx ST) - When a "1" is
written into the CLR Rx ST bit, a reset signal IS generated for
the receiver status bits in status registers #1 and #2 (except
AP and ROA bltsl. The reset signal IS enabled only for the
for a single-byte data transfer. Similarly, If 2/1 Byte IS set, bits which have been present dUring the last "read status"
the TORA and RDA status bit indicate when two bytes of operation. The CLR Rx ST bit automatically returns to the
data can be moved without a second status read. "0" state.

b2 - Flag/Mark Idle Select (F/M Idle) - The F/M Idle bit b6 - Clear Transmitter Status (CLR Tx ST) - When a
selects Flag characters or blt-by-blt Mark Idle for the time fill "1" IS written Into CLR Tx ST bit, a reset signal IS generated
or the Idle state of the transmitter. When Mark Idle IS for the transmitter status bits In status register #1 (except
selected, Go-Ahead code can be generated for loop opera- TORA). The reset signal IS enabled for the bits which have
tion in conjunction with the 01111 Idle control bit (C3b3). been present dUring the last "read status" operation. The
1... Flag time fill, O... Mark Idle. CLR Tx ST bit automatically returns to the "0" state.

b3 - Frame CompletelTDRA Select (FC/TDRA b7 - Request-to-Send Control (RTS) - The RTS bit,
Select) - The FC/TORA Select bit selects TORA status or when high, causes the RTS output to be low (the active
FC status for the TORA/ FC status bit Ind,Calion 1. FC statel. When the RTS bit returns low and data IS being
status, 0 .. TORA status. transmitted, the RTS output remains low until the last
character of the frame (the closing Flag or Abort) has been
b4 - Transmit Last Data (Tx Last) - Tx Last bit provides completed and the Tx FIFO IS empty. If the transmitter IS Idl-
another method to terminate a frame This bit should be set Ing when the RTS bit returns low, the RTS output will go
high (the Inactive state) Within two bit times

4-566
MC6854- MC68A54- MC68B54

CONTROL REGISTER 3 (CR3)

7 6 5 4 3 2 1 0
RSl RSO R/W AC LOCI GAPI Loop FDSE 01/11 AEX CEX LCF
o 0 1 DTR TST Idle

bO - Logical Control Field Select (LCF) - The LCF select detection will cause the Flag Detect output to go low for 1 bit
bit causes the first byte(s) of data belonging to the informa- time regardless of the state of FDS E.
tion field to remain 8-bit characters until the logical control
field IS complete. The logical control field (when selected) IS b5 - LOOP/NON-LOOP Mode (LOOP) - When the
an automatically extendable field which IS extended when bit LOOP bit IS set, loop mode operation IS selected and the

•
7 of a logical control character IS a "1." When the LCF Select GAPITST control bit, LOC/DTR control bit and LOC/DTR
bit IS reset the ADLC assumes no logical control field IS pre- output are selected to perform the loop control functions.
sent for either the transmit or received data channels. When When LOOP IS reset, the AOLC operates in the point-to-
the logical control field IS terminated, the word length of the point data communications mode.
Information data IS then defined by WLSl and WLS2
b6 - Go Active On Poll/Test (GAP/TST) - In the Loop
b1 - Extended Control Field Select (CEX) - When the Mode - The GAP/TST bit is used to respond to the poll se-
CEX bit IS a "1", the control field IS extended and asusmed to quence and to begin transmission. When GAP/TST IS set,
be 16 bits. When CEX IS "0", the control field IS assumed to the receiver searches for the "Go Ahead" (or End of Poll,
be 8 bits. EOP). The receiver "Go ahead" is converted to an opening
Flag and the AOLC starts its own transmission. When
b2 - Autol Address Extend Mode (AEX) - The AEX bit GAPITST is reset dUring the transmiSSion, the end of the
when "low" allows full 8 bits of the address octet to be utiliz- frame (the completion of Flag or Abort) causes the termina-
ed for addressing because address extension IS inhibited. tion of the "go-active-on-poll" operation and the Rx Data to
When the AEX bit IS "high," bit 0 of address octet equal to Tx Data link is re-establlshed. The AOLC then returns to the
"0" causes the Address field to be extended by one octet. "Ioop-on-line" state.
The exception to this automatic address field extension is In the Non-Loop Mode - The GAP/TST bit IS used for
when the first address octet IS all "O's" (the Null Address!. self-test purposes. If GAP/TST bit IS set, the TxO output is
connected to the RxO Input Internally, and prOVides a "Ioop-
b3 - 01 I 11 Idle (01 I 11 Idle) - The 01 I 11 Idle Control bit back" feature. For normal operation, the GAP/TST bit
determines whether the inactive (Mark) Idle condition beginS should be reset.
with a "a" or not. If the 01/11 Idle Control IS SET, the clOSing
flag (or Abort) will be followed by a 011111 ... pattern. This IS b7 - Loop On-Line ControllDTR Control (LOC/DTR) -
reqUired of the controller for the "Go Ahead" character In In the Loop Mode - The LOC/OTR bit is used to go on-line
the Loop Mode. When 01111 IS RESET, the Idling condition or to go off-line. When LOC/OTR is set, the ADLC goes to
Will be all "l's" the on-line state after 7 consecutive "l's" occur at the RxO
Input. When LOCIDTR IS reset, the ADLC goes to the "off-
b4 - Flag Detect Status Enable (FDSE) - The FDSE bit line" state after eight consecutive "l's" occur at the RxO in-
enables the FD status bit In Status Register #1 to indicate the put.
occurrence of a received Flag character. The status Indica- In the Non-Loop Mode - The LOC/OTR bit directly con-
tion will be accompanied by an Interrupt If RIE IS SET Flag trols the Loop On-Llne/OTR output state 1...0TR output
goes to low level, O... DTR output goes to high level.

4-567
 MC6854. MC68A54· MC68B54

CONTROL REGISTER 4 (CR4)

7 6 5 4 I 3 2 I , 0

, ,
RS' RSO R/W AC
0 , NRZI/NRZ ABTEX ABT
WLS2
Rx
WLS, WLS2
Tx
WLS,
"FF"/F

bO - Double Flag/Single Flag Interframe Control '-blt delay IS added to the transmitted data (TxD) to allow for
("FF" /"F") - The "FF"I"F" Control bit determines NAZI encoding. ' ... NAZI, O... NAZ.
whether the transmitter will transmit separate closmg and
opening Flags when frames are transmitted successively. NOTE
When the "FF"I"F" control bit is low, the closing flag of the NAZI coding - The serial data remains m the same
first frame will serve as the opening flag of the second frame state to send a binary "'" and sWitches to the op-
When the bit IS high, Independent opening and closmg flags posite state to send a binary "0".

I will be transmitted.

bl, b2 - Transmitter Word Length Select (Tx WLSI and

WLS2) - Tx WLS' and WLS2 are used to select the word
length of the transmitter Information field. The encoding for-
mat IS shown In Table 3.
STATUS REGISTER
The Status Aeglster #, is the mam status register. The lAO
bit Indicates whether the ADLC requests service or not The
S2AO bit mdlcates whether any bits m status register 12 re-
quest any service. TDAA and ADA, because they are most
bJ, b4 - Receiver Word Length Select (Rx WLSI and often used, are located In bit positions that are more conve-
WLS2) - Rx WLS' and WLS2 are used to select the word nient to test. ADA reflects the state of the ADA bit In status
length of the receiver information field. The encodmg format register 12.
IS shown in Table 3.
The Status Aeglster #2 provides the detailed status mfor-
mation con tamed m the S2AO bit and these bits reflect
receiver status. The FD bit IS the only receiver status which IS
TABLE 3 - I-FIELD CHARACTER LENGTH SELECT
not Indicated In status register #2
WLSI WLS2 I·Field Character Length The prioritized status mode provides maximum effiCiency
0 0 5 bits In searchmg the status bits and Indicates only the most Im-
1 0 6 bits
portant action reqUired to service the ADLC The pnorlty
0 1 7 bits
trees of both status registers are proVided In Figure' O.
1 1 8 bits
Aeadlng the status register IS a non-destructIVe process
The method of cleanng status depends upon the bit's func-
tion and IS discussed for each bit In the register
b5 - Transmit Abort (AST) - The ABT bit causes an
Abort (at least 8 bits of "'" In succession) to be transmitted FIGURE 10 - STATUS REGISTER PRIORITY TREE (PSE=11
The Abort IS Initiated and the Tx FIFO IS cleared when the
SR #1
control bit goes high. Once Abort begins, the Tx Abort con-
(Tx) (Rx) SR#Z (Rx)
trol bit assumes the low state DecreaSing
Priority ".- CTS FD EAR, FV, OeD,
I t t OVRN,tx ABT
b6 - Abort Extend (ASTEX) - If ABTEX IS set, the abort ( TXU s2Ra
code Initiated by ABT IS extended up to at least '6 bits of
consecutive ""s", the mark Idle State. 1 \
.,. TDRA/FC
t t
RDA
Ax Idle
t
AP
t
b7 - NRZI (Zero Complementl/NRZ Select RDA
(NRZI/NAZ) - NAZI/NAZ bit selects the transmit/receive
data format to be NAZI or NAZ In both Loop Mode or Non- "Pnontlzed even when PSE ::: 0
Loop mode operation When the NAZI Mode IS selected, a NOTE Status bit above Will inhibit one below It

4·568
MC6854- MC68A54- MC68B54

STATUS REGISTER 1 (SR1)

7 6 5 4 3 2 1 0
RSl RSO R/W AC IRQ TDRA/FC TXU CTS FD LOOP S2RQ RDA
0 0 1 X

bO - Receiver Data Available (RDA) - The RDA status b5 - Transmitter Underrun (TxU) - When the transmit-
bit reflects the state of the RDA status bit In status register ter runs out of data dUring a frame transmiSSion, an underrun
#2. It provides the means of achieving data transfers of occurs and the frame IS automatically terminated by
received data In the full Duplex Mode without haVing to read transmitting an Abort. The underrun condition IS Indicated

•
both status registers. by the TxU status bit. TxU can be cleared by means of the
Clear Tx Status Control bit or by Tx Reset
bl - Status Register #2 Read Request (S2RO) - All the
status bits (stored conditions) of status register #2 (except b6 - Transmitter Data Register Available/Frame Com-
RDA bit) are logically ORed and Indicated by the S2RQ plete (TDRA/FC) - The TDRA Status bit serves two pur-
status bit. Therefore, S2RQ indicates that status register #2 poses depending upon the state of the Frame Com-
needs to be read. When S2RQ IS "0", It IS not necessary to plete/TDRA Select control bit. When thiS bit serves as a
read status register #2. The bit IS cleared when the ap- TDRA status bit, It Indicates that data (to be transmitted)
propriate bits In status register #2 are cleared or when Rx can be loaded into the Tx Data FIFO register. The first
Reset is used. register (Register #1) of the Tx Data FIFO being empty
(TDRA = "1 ") will be Indicated by the TDRA Status bit In the
b2 - Loop Status (LOOP) - The LOOP status bit IS used "1-8yte Transfer Mode." The first two registers (Registers
to monitor the loop operation of the ADLC. This bit does not #1 and #2) must be empty for TDRA to be high when in the
cause an IRQ. When Non-Loop Mode IS selected, LOOP bit "2-8yte Transfer Mode." TDRA IS Inhibited by Tx Reset, or
stays "0". When Loop Mode IS selected, the LOOP status bit CTS being high.
goes to "1" dUring "On-Loop" condition. When ADLC IS in When the Frame Complete Mode of operation IS selected,
an "Off-Loop" condition or "Go-Active-On-Poll" condition, the TDRA/ FC status bit goes high when an abort IS transmit-
the LOOP status bit is a "0" ted or when a flag IS transmitted With no data In the Tx FIFO.
The bit remains high until cleared by resetting the TDRA/ FC
b3 - Flag Detected (FD) - The FD Status bit Indicates control bit or setting the Tx Reset bit.
that a flag has been received If the Flag Detect Enable control
bit has been set. The bit goes high at the last bit of the Flag b7 - Interrpt Request (lRO) - The Interrupt Request
Character received (when the Flag Detect Output goes low) status bit Indicates when the IRQ output is in the active state
and IS stored until cleared by Clear Rx Status or Rx Reset (IRQ Output = "0"1. The IRQ status bit IS subject to the same
Interrupt enables (RIE, TIE) as the IRQ output, I.e., with both
b4 - Clear-to-Send (CTS) - The CTS input positive tran- transmitter and receiver Interrupts enabled, the IRQ status
sition IS stored In the status register and causes an IRQ (if bit IS a logical ORed Indication of Status Register 1 status
Enabledl. The'stored CTS condition and ItS IRQ are cleared bits. The IRQ bit only reflects the set status bits which have
by Clear Tx Status control bit or Tx Reset bit. After the Interrupts enabled. The IRQ status bit simplifies status in-
stored status IS reset, the CTS status bit reflects the state of qUiries for polling systems by prOViding Single bit Indication
the CTS Input. of service requests.

4-569
 MC6854-MC68A54-MC68B54

STATUS REGISTER 2 (SR2)

7 6 5 4 3 2 1 0
RS1 RSO R/W AC RDA OVRN DCD ERR Rx Rx FV AP
o x ABT Idle

bO - Add_ PIW8I1t (AP) - The AP status bit provides Abort condition IS cleared by the Clear Rx Status Control bit
the frame boundary and indicates an Address octet is or Rx Reset.
available in the Rx Data FIFO register. In the Extended Ad- b4 - Frame Check Sequenoe/lnvalid Frame Error
dressing Mode, the AP bit continues to Indicate addresses (ERR) - When a frame is complete with a cyclic redundancy
until the Address field is complete. The Address present check (CRC) error or a short frame error (the frame does not
status bit is 'cleared by reading data or by Rx Reset. have complete Address and Control fields), the ER R status
bit is set instead of the Frame Valid status bit. Other func-

I bl - Frame Valid (FV) - The FV status bit provides the

frame boundary indication to the MPU and also Indicates
that a frame IS complete with no error. The FV status bit IS
set when the last data byte of a frame IS transferred Into the
last location of the Rx FIFO (available to be read by MPUl.
Once FV status is set, the ADLC stops further data transfer
tions, frame boundry indication and control function, are ex-
actly the same as for the Frame Valid status bit. Refer to the
FV status bit.

b6 - Data Carrier Detect (DCD) - A positive transition

on the DCD input is stored in the status register and causes
Into the last location of the Rx FIFO lin order to prevent the an IRQ (if enabled!. The stored DCD condition and its IRQ
mixing of two frames) until the status bit is cleared by the are cleared by the Clear Rx Status Control bit or RX Reset.
Clear Rx Status bit or Rx Reset. After stored status IS reset, the DCD status bit follows the
state of the input. Both the stored DCD condition and the
b2 - Inactive Idle Received (Rx Idle) - The Rx Idle status DCD Input cause the reset of the receiver section when they
bit Indicates that a minimum of 15 consecutive "l's" have are high.
been received. The event IS stored within the status register
and can cause an interrupt. The interrupt and stored condi- b6 - Receiver Overrun (OVRN) - OVRN status indicates
tIOn are cleared by the Clear Rx Status Control bit. The that receiver data has been transferred Into the Rx FIFO
Status bit IS the Logical OR of the receiver Idhng detector when it is full, resulting In data loss. The OVRN status is
(which continues to reflect idling until a "0" IS received) and cleared by the Clear Rx Status bit or Rx Reset Continued
the stored inactive idle condition. overrunning only destroys data In the first FIFO Register.

b3 - Abort Received (RxABT) - The RxABT status bit b7 - Receiver Data Available (RDA) - The Receiver Data
indicates that seven or more consecutive "l's" have been Available status bit indicates when receiver data can be read
received. Abort has no meaning under out-of-frame condi- from the Rx Data FIFO. When the prioritized status mode IS
tions; therefore, no Interrupt nor storing of the status will oc- used, the RDA bit indicates that non-address and non-last
cur unless a Flag has been detected prior to the Abort. An data are available In the Rx FIFO. The receiver data being
Abort Received when "in frame" is stored In the status present in the last register of the FIFO causes RDA to be high
register and causes an IRQ. The status bit IS the logical OR of for the "l-Byte Transfer Mode." The RDA bit being high in-
the stored conditions and the Rx Abort detect logic, which IS dicates that the last.two registers are full when In the "2-Byte
cleared after 15 consecutive "l's" have occurred. The stored Transfer Mode." The RDA status bit IS reset automatically
when data IS not available

4·570
MC6854- MC68A54- MC68B54

PROGRAMMING CONSIDERATIONS

1. Status Priority - When the prioritized status mode is us- Test RDA to indicate whether a I-byte read should be
ed, It is best to test for the lowest Priority conditions first. performed. Then clear the frame end status.
The lowest Priority conditions tYPically occur more fre-
quently and are the most likely conditions to exist when 6. Frame Complete Status and RTS Release - In many
the processor IS interrupted. cases, a MODEM will require a delay for releaSing RTS.
2. Stored va Present Status - Certain status bits (DCD, An a-bit or 16-bit delay can be added to the ADlC RTS
CTS, Rx Abort, and Rx Idle) Indicate a status which is the output by using an Abort. At the end of a transmission,
logical OR of a stored and a present condition. It IS the frame complete status Will Indicate the frame completion.
stored status that causes an Interrupt and which is After frame complete status goes high, write "1" Into the
cleared by a Status Clear control bit. After being cleared, Abt control bit (and Abt Extend bit If a 16-bit delay is re-
the status register will reflect the present condition of an qUired). After the Abt control bit is set, write "0" Into the
input or a receiver Input sequence. R'fS control bit. The transmitter will transmit eight or SIX-
3. Clearing status Registers - In order to clear an Interrupt teen "1 's" and the RTS output will then go high
With the two Status Clear control bitS, a particular status (Inactive).
condition must be read before it can be cleared. In the 7. Note to users not using the MC6800 - (a) Care should be
priOritized mode, clearing a higher PriOrity condition taken when performing a write followed by a read on suc-
might result In another iRQ caused by a lower priority cessive E pulses at a high frequency rate. Time must be
condition whose status was suppressed when a status allowed for status changes to occur. If thiS IS done, the
time that E is low between successive writel read E pulses

•
register was first read. ThiS guarantees that a status con-
dition IS never Inadvertently cleared. should be at least 500 ns. (b) The ADlC IS a completely
4. Clearing the Rx FIFO - An Rx Reset Will effectively clear static part. However, the E frequency should be high
the contents of all three Rx FIFO bytes. However, the enough to move data through the FI FOs and to service
FIFO may contain data from two different frames when the peripheral requirements. Also, the period between
abort or DCD failure occurs. When this happens, the data successive E pulses should be less than the period of RxC
from a previously closed frame (a frame whose clOSing or TxC In order to maintain synchronization between the
flag has been received) Will not be destroyed. data bus and the peripherals
5. Servicing the Rx FIFO in a 2-Byt8 Mode - The procedure 8. Clear-to-Send (CTS) - The CTS input, when high, pro-
for reading the last bytes of data IS the same, regardless of vides a real-time Inhibit to the TDRA status bit and ItS
whether the frame contains an even or an odd number of associated interrupt. All other status bits Will be opera-
bytes. Continue to read 2 bytes until an Interrupt cocurs tional. Since it inhibits TDRA, CTS also inhlbts the TDSR
that IS caused by an end-of-frame status (FV or ERR) DMA request. The CTS Input being high does not affect
When this occurs, Indicating the last byte either has been any other part of the transmitter Information In the T X
read or IS ready to be read, switch temporarily to the FIFO and Tx Shift Register Will, therefore, continue to be
I-byte mode with no prioritIZed status (control register 2). transmitted as long as the Tx ClK IS running.

ORDERING INFORMATION

Motorola Integrated CirCUit

M6800 Family
Blanks~ 1 0 MHz
A~15 MHz
"TTr
MC68A54CP

-
Levell "S"~ 10 Temp Cycles - 1-25 to l50"CI,
HI Temp testing at T A max
Level 2 "D" = 168 Hour Burn-In at 125°C
Level 3 "DS" = Combination of Levelland 2

B~20MHz
DeVice DeSignation
In M6800 Family Speed Device Temperature Range
Temperature Range _ _ _ _ _ _ _ _...1
1.0 MHz MC6854P,L,S o to 70·C
Blank = 0°_ + 70°C MC6854CP,CL,CS -40 to +85·C
C~ -40"- +85"C
Package ____________---l 15 MHz MC68A54P,L,S o to + 70·C
P = PlastiC MC68A54CP,CL,CS -40 to +85·C
5 ~ Cerdlp 20 MHz MC68B54P,L,S o to + 70·C
L= Ceramic
BETTER PROGRAM
Better program processing IS available on all types listed Add
suffiX letters to part number
Levell add "5" Level 2 add "D" Level 3 add "DS"

4-571
 ® MOTOROLA MC68SS

Product Prey ie""

HMOS
(HIGH-DENSITY, N-CHANNEL
SILlCDN-GATEI

MC6855 SERIAL DIRECT MEMORY ACCESS PROCESSOR

The Senal Direct Memory Access Processor IS intended as a high-speed senal link between MPU's or other Intelligent con-
trollers This deVice can automatically transfer data to or from memory and receive or transmit that data over a serlallrnk USing
bit onented protocols lie, SDLC, HDLC, l( 251, the SDMAP IS capable of handling multidrop, pOlnHo-polnt. or loop con-
figurations In a full or half duplex environment Bit rates of up to4 MHz full duplex can be used The Data Link IS configured With
a pnmary SDMAP connected to one or more secondary SDMAP's The primary station ISDMAP and ItS associated local MPUI
has responsibility for the data link control, such as mode of operation and polling of the secondary SOMAP's The secondary
stations which are relatively transparent to the local MPU Will respond only to link commands from the primary station Each

•
SDMAP has the ability to respond to link-level commands With automatic responses or station status and handle link level error
recovery Without Intervention by the local MPU
An Internal DMA controller IS contained In the SDMAP and is capable of handling both a transmit and receive channel
Simultaneously The DMA controller IS transparent to the user The local MPU only needs to wille the location of a parameter
table to the SDMAP ThiS parameter table contains the start address, message length, type of message, etc The SDMAP
automatically reads and loads the parameters Into It's Internal registers and then starts to transmit (or receive I data
The SDMAP contains 7 control registers and 3 status registers The control registers are used to configure the SDMAP, con-
trol recepllon and transmission of frames, and selectively mask Interrupts The status registers are used to monitor link activity,
error conditIOns, and status of the SDMAP
Other registers ore Included for local and group station addresses, test, I·frame counts (SDLC secondary onlyl, and pOinter
registers used to define blocks of frames to transmit and blocks of receive buffers

• Up to 4 MHz Bit Rate

• External Data Recovery
• External Clocks
• DMA Chamlng
• Automatic Processing of a Subset of SDLC Commands
• HOLCISDLC Protocols
• Fulll Half Duplex Operation
• DMA Capability
• Normal or System Address Detection
• MC6809 Compatibility
• NRZ Operation
• Internal Byte Synchronization
• POlnt-to-Polnt Mode
• Multidrop Mode
• Loop Mode
• Separately Powered Pass- rhrough LogiC [Loop Model
MC6855

MPU INTERFACE PINS select Inputs and are used only as outputs to select the pro-
per memory location
Power - The SDMAP uses a single supply with two pins
dedicated to + 5 V and two pinS for ground DO-D7 (Data Bus Bidirectional) - The 8 bidirectIOnal data
lines allow the transfer of data between the SDMAP and the
RESET - The RES ET Pin IS an Input used to reset the controlling system
SDMAP and place It In the Power-Dn-Reset mode
MCLK - The MCLK Input supplied to the SDMAP IS a
R/W (Read/Write) - R/W determines the direction of
crystal controlled 8 MHz clock used to supply the Internal
data transfers on the data bus fo' register or DMA accesses
timing of the SDMAP

MRDY (Memory Ready Output) - MRDY IS output by the

SDMA to stretch the failing edge of E dUring a register read
or write operation to allow time for the data to be stable on
DATA TRANSFERS the data bus prior to the failing edge of E

When DMAGNT IS asserted and the DMAREO was DMAVMA (DMA Valid Memory Address Output) -
generated by the SDMAP, the R/W pin IS generated as an DMAVMA goes low at the beginning of a DMA cycle to
output The condition of the R/W pin Ilow or high) IS depen- allow time for one controlling deVice to release the bus and
dent upon the direction of data as determined by the another deVice to become the bus master DMAVMA goes
SDMAP When DMAGNT IS low, R/W IS an Input controlled to zero on the rising edge of DMAGNT and returns to a one

•
bv the external processor and determines the directIOn of state on the next failing edge of E It IS dUring thiS time that
data transfers to or from the SDMAP registers address lines are allowed to SWitch

TDATA (Transmit Data Output) - TDA T A IS the serial bit

IRQ (Output) - IRQ will be set low by the SDMAP to in- stream sent by the SDMAP In a synchronous format
terrupt the MPU TDATA IS shifted out In an NRZ format on the negative edge
of TXCLK
CS (Chip Select Input) The Cs Input, In conjunction
Wlttl the E Input, IS used to enable data transfers on DO-D7 E TXCLK (Transmit Clock Input) - TXCLK IS an Input to the
must be a high level and CS must be a low level to enable the SDMAP generated by an external crystal OSCillator source
transfer The DMA Grant Input being a high level performs a ThiS Input takes standard TTL levels and IS a Xl Input
similar function as CS being a low level while In the DMA
mode CS IS Invalid dUring a DMA cycle RDATA (Receive Data Input) - RDATA IS the serial bit
stream received by the S DMAP In a synchronous format
E Clock (Input) - The E Input to the SDMAP causes data The RDATA IS synchronized externally to the RXCLK and IS
transfers to occur between the SDMAP and the system con- strobed Into the SDMAP on the positive edge of the clock
trolling the SDMAP (MC6809 MPU, etc) The SDMAP reqUires the data to be Input In an NRZ data for-
mat
Q (Quadrature Clock Input) - 0 IS an Input to the SDMAP
which precedes E by 90 degrees It IS used as an Internal tim- RXCLK (Receive Clock Input) - RXCLK IS an Input to the
Ing Signal SDMAP generated by an external crystal OSCillator source It
IS a standard TTL level externally synchronized to the receive
DMAR (DMA Request Output) - The DMAR IS data and strobes the data Into the SDMAP on the positive
developed at the rising edge of 0 to request the bus for data edge of the Xl Receive Clock
transfer DMAR IS dropped dUring O.
RTS (Request to Send Output) - The RTS pin, when us-
DMAGNT (DMA Grant Input) - DMAGNT goes active on ed In systems requIring modems, Signals the modem to turn
the failing edge of E plaCing the MPU bus In a 3-state mode on the transmit carner and initiate the return of CTS In
and allOWing the requesting deVice to become a bus master systems not requiring modems, RTS IS used as needed to
DMAGNT takes the place of CS when In a DMA operation control the flow of data on the senal line

AO-A15 (Address Bus Bidirectional) - AO-A15, In con- CTS (Clear to Send Input) - In systems uSing modems,
Junction With the R/W Input, are used to select one of the CTS IS a function of RTS and the modem's requirements for
MPU acceSSible registers In the SDMAP for programmed line turnaround In systems not uSing modems, CTS IS a
data transfer. function of fiTS or RTS and an external delay CirCUit No
DUring any DMA operation AO-A15 are Ignored as register data IS transmitted by the SDMAP until ITS IS true
 ® MOTOROLA Me68S9

Advance In:forIDatlon
MOS
DEPLETION LOAD
DATA SECURITY DEVICE IN-CHANNEL, SILICON-GATEI

DATA SECURITY DEVICE

The MC6859 Data SecUrity Device (DSD) is a monohthlc MOS In-
tegrated circuit designed to be Integrated Into a wide range of eqUip-
ment reqUIring protection of data by the employment of cryptographic
measures.
The cryptographic algorithm utihzed by the device IS the Data Encryp-

~
tion Standard (DES) as adopted by the U.S. Department of Commerce, ~-
National Bureau of Standards (NBS), In pubhcatlon FIPS PUB 46
(1-15-1977) I
Through the use of flexible on-chip control and status CircUitry and 24 I'
, I L SUFFIX
external control lines, the DSD provides direct capabihty of adapting the 1 CERAMIC PACKAGE
functional ImplementatIOn of the DES algorithm for various speCifiC • CASE 716
system reqUirements for data protection.

~" ':1':':
• Direct Compatlbihty with the M6800 Microprocessor Family

•
• Data Encryption Standard Algorithm
• Two Separate Interrupt Output Lines for Program Controlled
SSUFFIX
Interrupt Capability , ,1 • • • CERDIP PACKAGE
• Up to 400 KBPS Throughput Rate of 64-Blt Block Cipher (ExclUSive I: ' • CASE 623
of Software Overhead)
• TTL Compatible
• Single +5 V Power Supply

PIN ASSIGNMENT

IROPE
07

DATA SECURITY DEVICE BLOCK DIAGRAM AO 05

A1 04
A2 03

VCC 02

RESET 01
DO
2XE
CS4 VSS
CS3
eso

NOTICE
ThiS product may not be exported
Without prior approval from the U.S.
Department of State, Office of MUni-
tions Control.

4·574
MC6859

MAXIMUM RATINGS
Characteristics Symbol Value Unit ThiS device contains circUItry to protect the in-
Supply Voltage Vcc -03to +70 V puts against damage due to high static voltages
Input Voltage V,n -03to +70 V or electriC fields, however, It IS adVised that nor-
Operating Temperature Range mal precuatlons be taken to avoid application of
TL to TH
MC6869 o to 70 any voltage higher than maximum rated voltages
TA °c
MC6869C -40 to +85 to thiS high-Impedance Circuit Reliability of
operation IS enhanced If unused Inputs are tied to
Storage Temperature Range Tstg -55 to + 150 °c an appropriate logic voltage level (e 9 • either
THERMAL CHARACTERISTICS VSS or VCC)
Characteristic Symbol Value Unit
Thermal Resistance
Ceramic Package 9JA 60 °C/W
Cerdlp Package 65

POWER CONSIDERATIONS

The average Chip-Junction temperature, T J, In °c can be obtained from

TJ=TA + (PO·8JA) (1)
Where.
TA-Amblent Temperature, °c
8JA- Package Thermal ReSistance, Junctlon-to-Amblent, °C/W
PO" PINT + PPORT
PINT-ICC x VCC, Watts - Chip Internal Power
PPORT-Port Power Oissipatlon, Watts - User Oetermlned
For most applicatIOns PPORT<C PINT and can be neglected PPORT may become significant If the deVice IS configured to
II
drive Darlington bases or Sink LED loads.
An approximate relationship between Po and T J (,f PPORT IS neglected) IS
PO= K ... (T J + 273°C) (2)
SolVing equations 1 and 2 for K gives'
K = PO.n A + 273°C) + 6JA·P 0 2 (3)
Where K IS a constant pertaining to the particular part K can be determined from equation 3 by measuring Po (at eqUilibrium)
for a known T A. USing thiS value of K the values of Po and T J can be obtained by solVing equations (1) and (2) Iteratively for any
value of TA

DC ELECTRICAL CHARACTERISTICS (VCC=5 0 Vdc ±5%, VSS=O, TA=TL to TH unless otherWise noted I
Characteristic Symbol Min Typ Max Unit
Input High Voltage VIH VSS+20 - VCC V
Input Low Voltage VIL VSS-O 3 - VSS+08 V
Input Leakage Current (V," - 0 to 5 25 V) lin 10 25 "A
Three-State (all State) Input Current (V ,n - 0 to 5 25 V) DO-07 liZ - 20 10 "A
Output High Voltage IILoad= -205 "A) (See Figure 2) 00-07 VOH VSS+24 - - V
Output Low Voltage
IILoad = 1 6 rnA) 00-07 VOL - - VSS+04 V
II Load = 3 2 rnA) (See Figure 2) iROPE,lROR - - VSS+O 6
Output Leakage Current (Off State) (VOH - 2 4 V) IROPE, )ROR 10Z - 10 10 ~A
Internal Power DISSipation (Measured at TA=TL) PINT - 1000 - mW
Input CapaCitance (V,n=O, TA=25°C, 1= 10 MHz) 00-07
Cin
- - 125
pF
All Others - - 75
Output Capacitance (V,n=O, TA=25°C, 1= 1 0 MHz) IROPE,IROR Cout - - 50 pF

4-575
 MC6859

BUS TIMING CHARACTERISTICS (See Notes 1 and 21

Indent MC6859 MC68A59 MC68B59
Characteristic Symbol Unit
Number Min Max Min Max Min Max
1 Cycle Time tcvc 10 10 067 10 05 10 ~s

2 Pulse Width. E Low PWEL 430 - 280 - 210 - ns

3 Pulse Width. E High PWEH 450 - 280 - 220 - ns
4 Clock Rise and Fall Time tr.tf - 25 - 25 - 20 ns
9 Address Hold Time tAH 10 10 10 ns
13 Address Setup Time Before E tAS 80 80 40 ns
14 Chip Select Setup Time Before E tcs 80 - 80 - 40 - ns
15 Chip Select Hold Time tCH 10 - 10 - 10 - ns
18 Read Data Hold Time tDHR 20 100 20 100 20 100 ns
21 Write Data Hold Time tDHW 10 - 10 - 10 - ns
30 Output Data Delay Time tDDR - 290 - 180 - 150 ns

. 31 Input Data Setup Time

See Mask Sets for Mask set AK6 Data Setup time
tDSW· 165 - 80 - 80 - ns

FIGURE 1 - BUS TIMING

• E
~----------(3r---------~

R/VV.Address--~-r~~~~~~~--------~rT~-----r+---------------------------------~~~~

(Non-Muxedl ____-+~~~~~~~~--------~~~----_+_r----------------------------------_r~~~~

Read Data -----+---"l. MPU Read Data Non-Muxed

Non-Muxed -----+--~~~----------------------------------------------~:::::j~--~~--~+_~Jt

Write Data ----...:..---- MPU Write Data Non-Muxed

Non-Muxed D---------------~~~~~~~~~~--------------~~----<I
1"---'I"-----=+---r
Notes
1 Voltage levels shown are VLSO 4 V. VH",2 4 V. unless otherwise specified
2 Measurement POints shown are 0 8 V and 2 0 V I unless otherWise specified

4·576
MC6859

FIGURE 2 - BUS TIMING TEST LOADS

(00-07) IRoPE,IROR
Vee

MMD6150
Test POInt 0----.----....- ....1--<. or Equlv Test POInt

e R
130 pF 117k
MMD7000
or EqUiv

FIGURE 3 - INTERRUPT RELEASE TIME

•
E

IROPE,IROR

Note Timing measurements are referenced from a low voltage of 08 volts and a high voltage of 20 volts, unless otherwise noted

4·577
 MC6859

BUS INTERFACE Modes - OperatIOnal and control modes are Invoked by

The MC6859 Data SecUrity Device (DSo) Interfaces to the addreSSing DSD registers at the addresses In Tables 1 and 2
M6800 bus via an 8-blt bidirectional data bus, five chip select
lines, a read/write (R/W) Ime, an external RESET line, three TABLE 1 - OPERATIONAL MODES
register select lines, an Enable (System q,2) line, a 2XEnabie
(2XE) clock Ime, and two Interrupt request lines These Control Address
Operational Mode
signals permit the M6800 MPU to control the DSD and per- AO, A1, A2 R/W
form data transfers between the two 0 0 0 W Write DatarC" Key Operation (1st 7 bytes)
"I 0 1 W EnCipher Data
Bidirectional Data Bus (DO-07) - The bidirectional data
"0 0 1 W Decipher Data
lines (DO-D7) allow the transfer of Information between the
MPU and DSD. The data bus Input/output drivers are three- 0 0 1 R Read Data
state devices which remain In the high-Impedance (off) state 0 1 0 R Read Status
except when the MPU performs a DSD read or write opera-
tion.
TABLE 2 - CONTROL MODES
Chip Select (CSO, CS1, CS2, CS3, and CS4) - These five
signals are used to activate the data bus Interface and allow Control Address
Control Mode
DSD data transfers When CSO= CS3= CS4= 1 and AO, AI, A2 R/W
CSi = CS2 = 0, the device IS selected 1 0 0 W Reset/Initialize
0 1 0 W Enter Malor Key
Read/Write (R/W) - With the DSD selected, thiS Input 1 1 0 W Enter Plain Secondary Key
controls the direction of data transfer on the data bus When "0 1 1 W Decipher Secondary Key
R/W IS high, data In the DSD IS read by the MPU on the trail-

I
"I 1 1 W EnCipher Secondary Key
Ing edge of E. A low state on the R/W line enables data
1 0 0 R Transfer Malor Key
transfer from the MPU on the trailing edge of the 2XE signal
on the AK6 mask set and on the trailing edge of E for all • Instruction Initiated after eighth byte of Key Block entry
other mask sets. (See Mask Sets)

Enable (E) and 2XEnable (2XE) - The rising edge of the Interrupt Requests - These open drain outputs are used
Enable Input Initiates data transfer from the DSD to the MPU to convey Internal DSD status information to the MPU.
dUring a read cycle The failing edge of the Enable Input lat- Ready Interrupt Request (IROR) - ThiS ac-
ches MPU data mto the DSD dUring a write cycle The 2XE tive low output signals the MPU that the DSD IS
Input IS used In processing the encryption/decryption ready to Initiate another operation The IROR
algorithm for all mask sets E and 2XE are completely asyn- signal Will be Inactive dUring encrYPtion/decryp-
chronous. See section on Mask Sets for exceptions on prior tion or key transfer
revIsion of the DSD Parity Error Interrupt Request (lROPE) - ThiS
active low output IS used to signal the MPU that
Reset (RESET) - ThiS Input signal IS used to initialize the the DSD has detected a parity error The IROPE
Internal control logic, status flags, and counters of the DSD signal Will remain low until a hardware or soft-
The contents of the active key register and major key register ware reset IS received
remain unchanged The RESET function should be coupled
with the system power-on reset to provide orderly system
Initialization It may also be used as a master reset to the chip
dUring system operation
To abort the encryption algOrithm before the required 320 DSD FUNCTIONAL DESCRIPTION
clock cycles (2XE) have occurred, It IS necessary to provide a The MC6859 Data Security DeVice appears to an MPU
RESET signal or a software reset command to the DSD system as an Interface adapter deVice An example of a
When thiS occurs, Information ,n the data register and active system With the encryption function IS shown In Figure 4
key register IS no longer valid The contents of the major key Internal construction of the DSD IS Illustrated by the block
register are unaffected diagram The deVice consists of a Single 8-blt data bus buffer
With three-state operation, through which data may be
Address Lines (AD, A 1, A2) - These Inputs are used In entered Into
conjunction With the R/W line to select one of eleven POSSI- 1) the 56-bit active key register
ble DSD operations, as shown In Tables 1 and 2 The DSD IS 2) the 54-bit major key register
accessed via M PU read and write operations In much the 3) the 54-bit data register
same manner as a memory deVice
Output data from the status register or the data register IS
NOTE: also sWitched through the data bus buffers
Instructions performing operations directly on memory At the bus Interface, the DSD data register appears as
should not be used when the DSD IS accessed Since the eight addressable memory locatIOns to the MPU, through
DSD uses the R/W line as an additional register select Input, which the operatIOnal mode of the chip may be selected,
read-modlfy-wrlte type Instructions Will conflict With normal chip status mOnitored, key or data written Into the device,
operation of the Data Security DeVice and data read from the deVice

4-578
MC6859

OPERATING MODES Data IS always processed uSing the current ActIVe Key Dur-
As shown In Table 1, the operation of the DSD IS split Into Ing algOrithm operation, the DSD constantly performs parity
five major modes: checking on the contents of the active key register The busy
1) status readout flag will be set dUring encryption and then reset when the
algOrithm has finished Completion reqUIres 320 cycles of
2) loading of data or encrypted key
2XE DUring thiS time the DSD Will Ignore all external com-
3) data encryption mands except status read, hardware reset and software
4) data decryptIOn reset
5) data readout
These and additional control modes are activated by three Decipher Data - ThiS process IS Identical to enCipher data
address Input lines and a read/write Input line. except that the eighth byte IS written to the DeCipher Data
register. DUring deCipher or enCipher only a read status
register, hardware reset, or software reset Will be recognIZ-
ed All other commands Will be Ignored
Read Status - Only two bits are used In the status Read Data - ThiS command IS normally executed upon
readout. D7= Parity Error (PE) and D6= READY The re- completion of the enCipher/decipher algorithm (,nd,cated by
maining SIX bits are always read as logiC zeros A read of the READY=O). A read prior to completion of busy Will result In
status register does not change these bits. all zeros being read from DO-D7 As each byte of data IS read,
The PE flag IS set when a parity error IS detected while zeros are automatically shifted Into the data register to en-
loading either a major or secondary key or when the active sure data security.
key IS checked dUring algOrithm operation The PE flag re-

II
mains set and the IRQPE signal Will remain low until a hard- CONTROL MODES
ware/software reset IS received. Shown In Table 2 are the control modes which faCilitate
The READY flag IS set and the IRQR output goes high programming of the primary and secondary keys
whenever the deVice IS processing a block of data. The flag IS
cleared, pulling the IRQR output low, whenever the DSD IS Reset/Initialize - The DSD may be software reset by
not encoding/decoding data or transferring major key IRQR writing the reset/,nit,al,ze command at any time the data bus
may be tied to IRQ of a M6800 family processor for Interrupt- IS Ignored Like the hardware reset, this command initializes
driven encryption If no other peripherals share the IRQ line. the Internal control logiC, status flags, and counters Without
altering the contents of the active key register or the major
Encipher Data - To enCipher an 8 byte block of data, the key register. If a hardware or software reset IS Issued dUring
first seven bytes are written to the Write Data/"C" Key the algonthm processing, the Information In the data register
register The eighth byte is written to the EnCipher Data and active key register Will no longer be valid However, the
register. ThiS automatically Initiates the encryption process contents of the major key register are not affected.

FIGURE 4 - M6800 MICROCOMPUTER FAMILY BLOCK OIAGRAM

M6800
Microprocessor

I--____-,,-____--,_____--,______-,-__.Oata
Bus

4-579
 MC6859

Load Major Key - An unencrypted key will be entered In- more receivers, the follOWing tYPical sequence might be used
to both the active key register and the major key register to transmit confidential data
when eight consecutive bytes are wntten Into the Enter Ma- 11 A software reset IS Issued to each DSD by ItS MPU
Jor Key Register Panty error checking IS automatically per- 21 The sending M PU loads a major key (eight bytes I Into
formed
ItS DSD. ThiS Will serve as the active key If a secondary
key IS not entered
Load Plain Secondary Key - An unencrypted key may be
31 The receiving station must also load thiS same major
loaded Into the active key register and simultaneously
checked for panty errors by wntlng eight consecutive bytes key before data transmission can begin. If lhe current
Into the Enter Plain Secondary Key Register The Major Key major (or secondary) key IS not known In advance, It
Register IS unaffected can be transmitted by the sending MPU, but may not
be encoded as the receiving M PU system has no key
Encipher Secondary Key - A Iter a secondary key IS load- to decode It by The MPU at the receiving station must
ed, It can be enciphered or deciphered (the source of an en- be programmed With the mode and format being used
crypted key IS usually another DSDI A secondary key may for data transmission so ItS DSD can process the data
correctly At thiS pOint both the transmlttlr'g and
be enciphered by loading the first seven bytes of plain text to
receiving stations are ready for data transfer
the Wnte Data/"C" Key register The eighth byte IS entered
to the Encipher Secondary Key register This causes the 41 The sending MPU writes eight bytes of data Into ItS
secondary key to be enciphered uSing the current major key DSD which enciphers them
and automatically loaded Into the Active Key register and 5) The sending MPU retrieves eight bytes of encrypted
checked for panty This operation requires 328 cycles of 2XE data from ItS DSD and transmits them to the receiving
MPU
Decipher Secondary Key - This function IS similar to the 61 The receiving MPU writes these eight bytes of data in-

I Encipher Secondary Key operation The first seven bytes of

the key are loaded Into the Wnte Data/"C" Key register The
eighth byte IS entered by addreSSing the Decipher Secondary
Key register The secondary key IS then deciphered uSing the
current major key and automatically loaded Into the Active
Key register and checked for panty This operation reqUires
to ItS OS D to be deciphered
7) The receiving MPU retrieves eight bytes of data from
ItS DSD In the onglnal plain text form.
Steps four through seven are repeated for each 8-byte
block of data to be transmitted If the major key or secondary
key IS to be changed, steps two and three must also be car-
328 cycles of 2XE
ned out

Transfer Major Key - The contents of the Major Key SECURITY CONSIDERATIONS
register Will be transferred to the ActIVe Key register by a The security of a system emplOYing the NBS Data Encryp-
read of the Transfer Major Key register The data bus IS Ig- tIOn Standard (DESI depends only upon the key used, not
nored The Major Key register remains unchanged This the availability of the algOrithm or of equipment used to Im-
operation requires eight cycles of 2XE plement the algOrithm The key IS the most critical piece of
information In the system and secunty of the key Itself must
KEY CONVENTIONS be maintained both inSide and outside the system
The key used for coding IS a 56-bit data word plus eight GUidelines to be used In selecting a key are
bits of odd panty In the DSD seven bits of key and the panty • Consider the key to be a single 56-bit number
bit make up a key character Eight key characters make up
• Avoid bias In selecting the key
the total key information required by the DSD If panty errors
are to be checked via the PE signal If panty IS not needed for • Change key as frequently as praCtlc31
some reason, then the panty bit need not be calculated and One way to help ensure the security of the key IS to make
can be lelt as a zero An example key With panty IS shown In frequent use of secondary keys Secondary keys can be
Table 3 generated by the sender and distributed selectively to one or
more receivers Since the MC6859 can encipher or decipher
TABLE 3 - EXAMPLE KEY secondary keys uSing the major key, the sender can transmit
Binary Value Parity the secondary key In encrypted form to further ensure
Key Character Hex Value
system security However, the receiver must be aware that a
Byte 1 7C 0 1 1 1 1 1 0 0
secondary key IS being transmitted and must decrypt the key
Byte 2 Al 1 0 1 0 0 0 0 1 If It was sent In encrypted form
Byte 3 10 0 0 0 1 0 0 0 0 Assuming that secrecy of the key IS maintained, It IS nearly
Byte 4 45 0 1 0 0 0 1 0 1 ImpOSSible for an unauthorized user to decode an In-
Byte 5 4A 0 1 0 0 1 0 1 0 tercepted message Into ItS orl91nal form. Since the DES
Byte 6 lA 0 0 0 1 1 0 1 0 algOrithm utilizes a 56-bit active key, there are 256 (or about
Byte 7 6E 0 1 1 0 1 1 1 0 7x 10 16 1 possible encrypted messages which must be
searched to retrieve the original message. In addition, If the
Byts 8 57 0 1 0 1 0 1 1 1
key were changed regularly only a small portion of the
Data Lines 07 06 05 04 03 02 01 DO
message would be retrieved for each successful exhaustive
search Therefore, the basIc "block Cipher" technique
TYPICAL SYSTEM OPERATION described In the TYPical System Operation seclion IS ade-
For a communicatIOns link between a sender and one or quate for today's data security applications

4·580
MC6859

If additional security IS required for some reason, several CFB DECIPHER

techniques can be used to Increase data security These in- The baSIC flow of the decipher CFB operation IS shown In
clude Figure 6
• Perform multiple encryption and/ or decryption uSing The same Initial fill as used for enCiphering must be used
the same key or different keys to Initialize the deCipher RAM buffer The same key used to
• Reverse the algorithm (declpher-transmlt-enclpherl enCipher must also be used to load the DSD aCtIVe key
• Utilize cipher feedback or other feedback techniques register prior to receiving Cipher text bytes When a Cipher
The process of multiple encryption or decryption IS an text byte IS received It IS exclUSive ORed With the key byte
easy way to effectIVely Increase the size of the key to any generated by the DSD and the result IS the plain text data
desired length. For example, the sender might successively byte. The received Cipher text byte IS shifted Into the RAM
encipher, decipher, and encipher a block of data uSing one buffer and becomes the newest RAM buffer byte The oldest
key for the encipher operations and another for the decipher RAM buffer byte IS discarded and the eight byte RAM buffer
operation. The receiver would then have to decipher, en- IS loaded Into the DSD for block deCiphering One byte of the
cipher, and decipher the data uSing the same pair of keys DSD data register IS read out and thiS byte becomes the key
ThiS technique would greatly Increase data security while byte for the next Cipher text byte received
redUCing throughput by a factor of three Many such multi-
ple encryption combinations are pOSSible FIGURE 5 - CFB ENCIPHER DATA FLOW
An easy way to Increase security without redUCing (TRANSMITTING)
throughput IS to perform the DES algOrithm "In reverse" In
other words, data or keys can be deCiphered by the sender
and then enCiphered by the receiver to Yield the or,glnal Ct-7
message ThiS technique works because the enCiphering and

•
deCiphering algOrithms are "mirror Images" of each other DES RAM
Many different feedback techniques are available as alter- AlgOrithm Buffer
natives to the baSIC 64-blt block cipher One of these, known
as cipher feedback (CFB), IS deSCribed below CFB IS a byte-
oriented Implementation In that only one byte IS transmitted
at a time Thus, throughput IS reduced by a factor of eight
(excluding software overhead) Implementation of the CFB
technique IS more dependent upon the system configuration
than IS the block cipher. Ct+l

CFB ENCIPHER
The baSIC flow of the CFB enCipher procedure IS shown In
FIGURE 6 - CFB ENCIPHER DATA FLOW
Figure 5 (RECEIVING)
An Initial eight byte fill of the RAM buffer must be done
prior to accepting plain text bytes for enCiphering ThiS infor-
mation can be conSidered to be a data subset of the key, but
may be any combination of eight-bit bytes as long as the
deCiphering deVice uses the same Imllal fill
After the block of data In the RAM buffer IS enCiphered, RAM DES
one byte of enCiphered data IS read from the DSD ThiS byte Buffer Algcnthm
IS the key byte (Kt+ 11 The plain text byte (Pt+ 1) IS ex-
Ct
clUSive ORed With the key byte and the result IS the Cipher
text byte (Ct + 1) The Cipher text byte IS shifted Into the bot-
tom of the RAM buffer and now IS the newest byte In the
block The oldest prevIous byte IS discarded The Cipher text
byte IS now available for use The new RAM buffer block IS
loaded Into the DSD for enCiphering and Yields the next key Ct+l------~----------~

for further processing

To purchase a copy of the NBS Data Encryption Standard ask for the Federal Information
Processing Standards (FIPS) PublicatIOn, FIPSP 46 at the follOWing address
National Technical Information Service
U S. Department of Commerce
5285 Port Royal Road
Springfield, VA 22161

4·581
 MC6859

MASK SETS old" AK6" mask set and those usmg the more recent mask
Devices marked "AK6XXXX", where "AK6" IS the mask sets.
set designation, latch M PU data mto the DS D on the failing The change to the" AK6" mask set allows the user to treat
edge of 2XEnabie dUring a write cycle as shown m Figure 7 the DSD like any other M6800 peripheral since all data
E and 2XE must be synchronized. Devices marked with a transfers are referenced to the Enable clock E and 2XE are
mask set designation other than" AK6" latch MPU data mto asynchronous on all mask sets except AK6. For thiS reason
the DSD on the failing edge of Enable dUring a write opera- deVices will no longer be produced uSing the" AK6" mask
tion as desCribed m thiS data sheet. ThiS IS the only opera- set. The" AK6" mask set can be Identified by the" AK6"
tional difference between deVices manufactured usmg the deSignatIOn preceding the data code on top of the package

FIGURE 7 - BUS WRITE TIMING CHARACTERISTICS

(WRITE INFORMATION INTO OSO)
(AK6 MASK SET ONLY)

~--------------------tcycE----------------------------------------~~

1 + - - - - - PWEH - - - - - - + 1

•
\ 1-tE------ PWEL -------+-1

tf tf
t8

2XE

to
tAS tAH

I
Address
I I
tH--1
-)
Data8us-----------------------------------------------
t I

-Data IS latched Into the Internal registers on the falling edge of 2XE and while Enable IS high. Therefore, for system conSiderations tDSW=
tDSWl +tD+2X tf MinimIZe tD to ensure operation at 1 MHz tDSWl IS the data setup time for the "AK6" mask set

Note Timing measurements are referenced to and from a low voltage of 0 8 volts and a high voltage of 2 a volts, unless otherwise noted

C"CUlt diagrams external to or containing Motorola products are Included as a means of Illustration only Complete Informa-
tion sufficient for construction purposes may not be fully Illustrated Although the Information herem has been carefully checked
and IS believed to be reliable, Motorola assumes no responsibility for Inaccuracies. Information herem does not convey to the
purchaser any license under the patent rights of Motorola or others.
The mformation contained herem IS for gUidance only, with no warranty of any type, expressed or Implied. Motorola reserves
the right to make any changes to the mformatlon and the product(s) to which the mformatlon applies and to dlscontmue
manufacture of the product(s) at any time.

4-582
 ® MOTOROLA MC6860

0-600 bps DIGITAL MODEM MOS

The MC6860 IS a MOS subsystem designed to be Integrated Into a
IN-CHANNEL, SILICON-GATE)
wide range of eqUipment utilizing senal data commUnications
The modem provides the necessary modulation, demodulation and
supervisory control functions to Implement a senal data communica- 0-600 bps
tions link, over a vOice grade channel, utilizing frequency shift keYing DIGITAL MODEM
(FSK) at bit rates up to 600 bps The MC6860 can be Implemented Into a
wide range of data handling systems, including stand alone modems,
data storage deVices, remote data commUnication terminals and 1/0 in-
terfaces for minicomputers.
N-channel sIlicon-gate technology permits the MC6860 to operate us-

~
Ing a single-voltage supply and be fully TTL compatible
S SUFFIX
The modem IS compatible with the M6800 microcomputer family, In- CERDIP PACKAGe
terfaCing directly With the Asynchronous Communications Interface ~.\l.'· CASE 623
Adapter to provide low-speed data commUnications capability
• Onglnate and Answer Mode
• Crystal or External Reference Control
•
•
•
•
•
Modem Self Test
Terminal Interfaces TTL-Compatible
Full-Duplex or Half-Duplex Operation
Automatic Answer and Disconnect
Compatible Functions for 100 Senes Data Sets
4' P SUFFIX
PLASTIC PACKAGE
CASE 709

•
~-- I
• Compatible Functions for 1001 AI B Data Couplers
LSUFFIX
CERAMIC PACKAGE
I ~ASE 7t6

FIGURE 1 - TYPICAL MC6860 SYSTEM CONFIGURATION

Telephone
Network
PIN ASSIGNMENT
Control t
J
I
Control Signals Data
VSS Rx Data
I Coupler
Tx Data eTs
Rx Brk ESD
An Ph SH
Transmit Carner
DuplexeT ELS i5TR
Asynchronous Receive ESS RI
Communications Data MC6860
Interface TO TST
Adapter
Tx Brk Rx Car

I ~
Receive '8';kii ST
Filter
Tx Car Mode
Threshold FO Rx Rate

Transmit
Data
Detect I
I
Threshold
Detector r-- VCC Xtal

r-
Receive
Carner J Limiter
I

4-583
 MC6860

MAXIMUM RATINGS
ThiS device contains circuitry to protect the
Rating Symbol Value UnIt Inputs against damage due to high static
Supply Voltage Vcc -03to +70 V voltages or electnc fields. however. It IS ad M

Input Voltage Von 03to +70 V vised that normal precautions be taken to
OperatIng Temperature Range aVOId application of any voltage higher than
TL to TH
MC6860 o to 70 'c maximum rated voltages to thiS high Im~
TA
MC6860S, MC6860C -40 to +85 pedance CircUIt
Reliability of operation IS enhanced If unus-
Storage Temperature Range Tstg -55 to +150 'c
ed Inputs are tied to an appropriate logic
voltage level Ie g , eother VSS or VCC)
THERMAL CHARACTERISTICS
Characteristics Symbol Value Unit
Thermal Resistance
Cerdlp 65
8JA 'C/W
PlastiC 120
Ceramic 60

• Tj:TA+I POo8jA)
Where
TA",Amblent Temperature, °c
POWER CONSIDERATIONS

The average chIp-JunctIon temperature, T j, In ac can be obtaIned from

8jA'" Package Thermal ResIstance, JunctIon-to-AmbIent, °C/W

(1)

Po IE PINT + PPORT
PINT'" iCC x V CC, Watts - ChIp Internal Power
PPORT'E Port Power Olsslpatlon, Watts - User Oetermlned
For most applIcatIons PPORT'" PINT and can be neglected PPORT may become s,gn,f,cant If the devIce IS confIgured to
drove Oarllngton bases or Sink LEO loads
An approxImate relatIonshIp between Po and T j Ilf PPORT IS neglected) IS
PO=K-lTj+273°C) (2)
SolVIng equatIons 1 and 2 for K gIves
K=PooITA+273°C)+8jAOP02 (3)
Where K IS a constant pertainIng to the partIcular part K can be determIned from equatIon 3 by measuring Po lat eqUIlIbrium)
for a known T A USIng thIS value of K tile values of Po and T j can be obtained by solVIng equations (1) and (2) iteratIvely for any
value of TA

4·584
MC6860

DC ELECTRICAL CHARACTERISTICS
(Vee == 50 ± 5% Vdc all voltages referenced to VSS ==0 T A == TL to TH all outputs loaded as shown In Figure 2 unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
Input High Voltage. All Inputs Except Crystal VIH 20 - VCC V
Input Low Voltage. All Inputs Except Crystal VIL VSS - 080 V
Crystal Input Voltage
(Crystal Input Dnven from an External Reference, Input Coupling Capacitor = 200 pF, Vin 15 - 20 Vp _p
Duty Cycle = 50 ± 5% I
Input Current
(V,n = VSSI All Inputs Except Rx Car. Tx Data. m. TST. AT. SH lin - - -02 rnA
Ai. SH Inputs - - -16
Input Leakage Current IV,n = 70 V. VCC = VSS. TA = 25'CI IlL - - 10 ~A
Output High Voltage. All Outputs Except An Ph and Tx Car
VOH1 24 - VCC V
IIOH1 = -004 rnA. Load AI
Output Low Voltage. All Outputs Except An Ph and Tx Car IIOL 1 = 1 6 rnA. Load AI VOll VSS - 040 V
Output High Current. An Ph IVOH2=0 8 V. Load BI IOH2 030 - - rnA
Output Low Voltage. An Ph IiOL2=O. Load BI VOL2 VSS - 030 V
Input Capacitance (f = 0 1 MHz. T A = 25'CI C,n - 50 - pF
Output Capacitance If=O 1 MHz. TA=25'CI Cout - 10 - pF
Transmit Carner Output Voltage (Load CI VCO 020 035 050 VIRMSI
Transmit Carrier Output 2nd Harmonic (Load C) V2H -25 -32 - d8

•
Input Transition Times, All Inputs Except Crystal tr - - 10'
~s
(Operating In the Crystal Input Mode, from 10% to 90% POints) tf - - 10'
Input Transition Times, Crystal Input tr - - 30
ns
(Operating In External Input Reference Model tf - - 30
Output Transition Times, All Outputs Except Tx Car tr - - 50
~s
(From 10% to 90% POints) tf - - 50
Internal Power DISSipation (All Inputs at VSS and All Outputs Open) (Measured at TA = TLl PINT - - 340 mW

"Maximum l!lput TranSition Times are :sO 1 x Pulse Width or the specified maximum of lOllS, whichever is smaller

FIGURE 2 - OUTPUT TEST LOADS

Load A - TIL Output Load for Receive Break, Digital Carrier, Mode, Clear-to-Send, load B - Answer Phone Load
and Receive Data Outputs

Vee
RL
257 k
± 1%

Test V,
POint o-----.----.---forII.-"' MMD5100
or Equlv Load C - Transmit Carner Load
100 k
RL
60 k
± 1%

MMD7000
or EqUiv
Simulated TTL Load

CT = 20 pF = total parasI11c capacl1ance, which Includes pfobe, wifing, and load capacitance

4-585
 MC6860

FIGURE 3 - BLOCK DIAGRAM

Data Terminal
Ready 20 4 Answer Phone

Clear-to-Send 23 19 Ring Indicator

Auto
Answerl
Break Release 9 DIsconnect 21 SWitch Hook
LogIC
Receive Break 3 15 Mode

Transmit Break 8 7 Threshold Detect

Vee Pm 12
Digital Carner 11
VSS Pin 1

Transmit Data 2 Modulator

Transmit Carner 10

Receive Data 24

I
Receive 14 Oe
Data Rate modulator
NOTE 1
Receive Carner 17
ES5 Enable Space DI$connert
E'LS Enahle Long Space Disconnect
m Enable Shon Space Disconnec 1
Crystal 13

Test Clock 18

Self Test 16 22 6 ES'StNotell

ES5 ELs

DEVICE OPERATION*

GENERAL
Figure 1 shows the modem and Its Interconnections The all Input-output (1/0) logiC need not be RS-232 compatible.
data to be transmitted IS presented m serial format to the The use of MC1488 and MC1489A line drivers and receivers
modulator for converSion to FS K signals for transmission on Will provide a RS-232 Interface conformmg to the EIA
the telephone line (refer to Figure 3), The modulator output specification.
IS buffered before drlvmg the line
The FSK signal from the remote modem IS received via the
telephone line and filtered to remove extraneous signals such ANSWER MODE
as the local Transmit Carner ThiS filtering can be either a Automatic answering IS first Initiated by a receipt of a Rmg
bandpass which passes only the deSired band of frequencies Indicator (Rii signal. ThiS can be either a low level for at least
or a notch which relects the known Interfering signal The 51 ms as would come from a CBS data coupler. or at least
deSired signal IS then limited to preserve the aXIs crossmgs 20 cycles of a 20-47 Hz ringing smgal (low level," 50% of the
and fed to the demodulator where the data IS recovered from duty cycle) as would come from a CBT data coupler The
the received FS K carner presence of the Rmg Indicator signal places the modem In
The Supervisory Control provides the necessary com- the Answer Mode; If the Data Termmal Ready line IS low. m-
mands and responses for handshaKing with the remote dlcatlng the commUnication terminal IS ready to send or
modem. along with the mterface signals to the data coupler receive data. the Answer Phone output goes high ThiS out-
and commUnication terminal If the modem IS a bUilt-In Unit. put IS deSigned to drive a transistor SWitch which Will activate

·See Tables 1 and 2 for delay time tolerances

4·586
MC6860

the Off Hook (OH) and Data Transmission (DA) relays In the If ESD IS high the modem Will transmit data until hang-up
data coupler Upon answering the phone the 2225-Hz occurs 3 s later Receive Break IS clamped 150 ms follOWing
Transmit Carner IS turned on the Data Terminal Ready Interrupt Refer to Figure 7
The originate modem at the other end detects this 2225-Hz
signal and after a 450 ms delay (used to disable any echo INPUT/OUTPUT FUNCTIONS
suppressors In the telephone network) transmits a 1270-Hz Figure B shows the I/O Interface for the low speed
signal which the local answering modem detects, provided modem The follOWing IS a descnptlon of each Individual
the amplitude and frequency requirements are met The Signal
amplitude threshold IS set external to the modem chip If the
signal level IS suffiCient the fB Input should be low for 20 ,.s Receiver Carrier (Rx Carl
at least once every 32 ms. The absence of a threshold Indica-
The Receive Carner IS the FSK Input to the demodulator
tion for a period greater than 51 ms denotes the loss of
The local Transmit Carner must be balanced or filtered out
Receive Carner and the modem begins hang-up procedures
and the remaining Signal hard limited. The conditioned
Hang-up Will occur 17 s after Ai has been released provided
receive carner IS measured by the MC6B60 Any half-cycle
the handshaking routine IS not re-established The frequeny
penod greater than or equal to 429 ± 1 0 P.s for the low band
tolerance dunng handshaking IS ± 100 Hz from the Mark fre-
or 235 ± 1 0 ,.S for the high band IS detected as a space
quency.
Resultant peak phase Jitter IS as follows
After the 1270-Hz signal has been received for 150 ms, the
Receive Data IS unclamped from a Mark condition and data
Data Rate Answer Mode Originate Mode
can be received. The Clear-to-Send output goes low 450 ms Bits per Second oI>J (Peek %) oI>J (Peek %)
after the receipt of carner and data presented to the answer
300 70 37
modem IS transmitted Refer to Figure 4
200 47 25

•
AUTOMATIC DISCONNECT 150 35 18
110 26 14
Upon receipt of a space of 150 ms or greater duration, the
modem clamps the Receive Break high. ThiS condition eXists
until a Break Release command IS Issued at the receiving sta- Ring Indicator (RII
tion Upon receipt of a 0 3 s space, With Enable Short Space The modem function Will recognize the receipt of a call
Disconnect at the most negative voltage (low), the modem from the CBT data coupler If at least 20 cycles of the
automatically hangs up If Enable Long Space Disconnect IS 20-47 Hz nnglng slngal lIow level '" 50% of the duty cycle)
low, the modem requires 1 5 s of continuous space to hang are present. The CBS data coupler AI Signal must be level-
up Refer to Figure 5 converted to TTL according to the E.IA RS-232 speCificatIOn
before InterfaCing It With the modem function The receipt of
ORIGINATE MODE a call from the CB S data coupler IS recognized If the Ai Signal
Upon receipt of a SWitch Hook (SH) command the IS present for at least 51 ms ThiS Input IS held high except
modem function IS placed In the Originate Mode If the Data dunng nnglng. An Ai Signal automatically places the modem
Terminal Ready Input IS enabled (low) the modem Will pro- function In the Answer Mode
Vide a logiC high output at Answer Phone The modem IS
now ready to receive the 2225-Hz signal from the remote Switch Hook (SH)
answenng modem It Will continue to look for thiS signal until
SH Interfaces directly With the CBT data coupler and via
17 S after SH has been released Disconnect occurs If the
the £LA RS-232 level conversion for the CBS data coupler
handshaking routine IS not established.
An SH Signal automatically places the modem function In the
Upon receiving 2225± 100 Hz for 150 ms at an acceptable
Originate Mode
amplitude, the receive Data output IS unclamped from a
SH IS low dUring origination of a call The modem will
Mark condition and data reception can be accomplished
automatically hang up 17 s after releaSing S H If the hand-
450 ms after receiving a 2225-Hz signal, a 1270-Hz signal IS
shaking routine has not been accomplished
transmitted to the remote modem 750 ms after receiving the
2225-Hz signal, the Clear-to-Send output IS taken low and
data can now be transmitted as well as received Refer to Threshold Detect (TO I
Figure 6 ThiS Input IS denved from an external threshold detector If
the Signal level IS suffiCient, the TO Input must be low for
INITIATE DISCONNECT 20 ,.s at least once every 32 ms to maintain normal opera-
In order to command the remote modem to automatically tion An InsuffiCient Signal level Indicates the absence of the
hang up, a disconnect signal IS sent by the local modem Receive Carner, an absence for less than 32 ms Will not
ThiS IS accomplished by pulSing the normally low Data Ter- cause channel establishment to be lost, however, data dur-
minal Ready Into a high state for greater than 34 ms.' The Ing thiS Interval Will be Invalid
local modem then sends a 3 s continuous space and hangs If the Signal IS present and the level IS acceptable at all
up provided the Enable Space Disconnect IS low. If the times, then the threshold Input can be low permanently.
remote modem hangs up before 3 s, loss of Threshold Loss of threshold for 51 ms or longer results In a loss of
Detect Will cause loss of Clear-to-Send, which marks the line Clear-to-Send. The Transmit Carner of the onglnate modem
In Answer Mode and turns the carner off In the Originate IS clamped off and a constant Mark IS transmitted from the
Mode. answer modem

4·587
 MC6860

TIMING DIAGRAMS

FIGURE 4 - ANSWER MODE

Call Received

-I 51ms l-
Ring IndIcator ~r--------------------------------
Ring Indicator CBTlflJi.n.rl.J--------------------------------
I
Mode {~~~;:rte ~ Answer (Low)

Data Terminal On (Low) I

Ready
Answer Phone ------1----------
r---------------------------------
Transmit Carrier - - - - - - { \

Receive Carner - - - - - - - - - - - - - - - - - - - {
_.-.-+-.,-.--h-.--.-_.-.--

•
Threshold Detect -c1_H-',9:..h.;,.'_ _ _ _ _ _ _ _ _ _ _ _ _ _ _+r_,.---,-_
Off (High)
Clear to Send -::.;..:..:.:..="---------------1====;;;;~;:=+====!_~~~:!....----

Tr~::lt {~:~~e Clamped at Mark _ _ _ _ _ _ _ _ _ _ _ _t-_______ +-____,'"=~u;;..n"c,,'a"'m.;.;p:;...'-'d""''"''

=============t;;;~~-~~~~
Receive
Data Space -
{ Mark - - - - - - - - - - - - - - - - - 1 - 150 ms ±150 ms
---------Clamped ------------I-+------Unclamped - - - - - - -
at Mark

FIGURE 5 - AUTOMATIC DISCONNECT - LONG OR SHORT SPACE

High
Rtng I ndleator
CBS High
Ring IndlLator --A-n-s-w-er-IL-o-w-,----CC~B~T;O----------------------------
Mode _ _ ~_~~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

On (Low)
Data Terminal
Ready
Answer Phone - - - - - - - - - - - - - - - - - - - - - - - ,

Transmit Carrier

Receive Carner

Threshold Detect -----.__---,---,-..,---~-_.-.__-r+-----------------

On (Low)
Clear to Send

Tram,mlt {~;~~e Clamped at Mark

Clamped at Mark

4-588
MC6860

FIGURE 6 - ORIGINATE MODE

SH Can Be Released
Switch Hook
~##~
On (Low)
Data TermInal
Ready Originate (HIgh)

Mode { ~r~~:;;:rte
Answer (H Igh)

Answer Phone 2025 Hz

I-Establlsh C a l l - - - - t - -
Receive Carner

Threshold Detect

ReceIve Data
Clamped at Mark ---------j----

Transmit Carner

Clear to Send
---------------j~==============77~500~m~'~============::~On{LOW)
Transm It Data

Enable Space
Disconnect
Clamped at Mark
On (Low) Unclamped
I
FIGURE 7 - INITIATE DISCONNECT

SWitch Hook
--j t--- 34 ms Pulse I nltlates Space DIsconnect

Data Terminal
Ready ~.--------------------------
Mocte
Off Hook
Answer Phone
On Hook
03sESS I
- 2025 Hz Or 2225 Hz - - + - - 1 5 s m ~
Receive Carner
Threshold Detect

- - - - - - - Undamped I I 50 ms Internal Threshold Detect Delay

Receive Data Clamped at Mark

Transmit Carner

3'---------~

On (Low)
Clear to Send

Transmit Oata E%%' unclamped~ Cldrnped at Space Clamped dt Mark

Enable Space On (Low}

Disconnect

4-589
 MC6860

Receive Data Rate (Rx Rate) Enabled Space Disconnect (ESD)

The demodulator has been optimized for slgnai-to-nOise When ESD IS strapped low and DTR IS pulsed to Initiate a
performance at 300 bps and 600 bps. The Receive Data Rate disconnect, the modem transmits a space for either 3 s or
Input must be low for 0-600 bps and should be high for until a loss of threshold IS detected, whichever occurs first If
(J..300 bps ESD IS strapped high, data Instead of a space IS transmitted
A disconnect occurs at the end of 3 s
Transmit Data (Tx Data)
Transmit Data IS the binary information presented to the Enable Short Space Disconnect (ESS)
modem function for modulation with FSK techniques. A ESS IS a strapprng option WhiCh, when low, Will
high level represents a Mark automatically hang up the phone upon receipt of a con-
tinuous space for 03 s ESS and ELS must not be
Data Terminal Ready (DTR) simultaneously strapped low.
The Data Terminal Ready signal must be low before the
modem function will be enabled To initiate a disconnect, Enable Long Space Disconnect (ELS)
DTR IS held high for 34 ms minimum. A disconnect will oc-
ELS IS a strapping option WhiCh, when low, Will
cur 3 slater,
automatically hang up the phone upon receipt of a con-
lin uous space for 1 5 s
Break Release (Brk R)
After receiving a 150 ms space signal, the clamped high Crystal (Xta!)
condition of the Receive Break output can be removed by A 10M Hz crystal with the following parameters IS re-
holding Break Release low for at least 20 !'s. qUired to utilize the on-chip OSCillator A 1.0-MHz square
Transmit Break (Tx Brk) wave can also be fed Into thiS Input to satisfy the clock re-
The Break command IS used to signal the remote modem qUirement

I to stop sending data

A Transmit Break (low) greater than 34 ms forces the
modem to send a continuous space signal for 233 ms
Transmit Break must be Initiated only after CTS has been
established This IS a negative edge sense Input Prior to In-
Itiating Tx Brk, thiS Input must be held high for a minimum of
Mode'
Frequency
Serres ReSistance
Shunt Capacitance'
Temperature
Test Level
Parallel
10MHz±01%
750 ohms max
70 pF max
0-70°C
10mW
34 ms. Load CapaCItance, 13 pF

FIGURE 8 - 1/0 INTERFACE CONNECTIONS FOR MC6S60

(ORIGINATE/ANSWER MODEM)

ThreShO'd~
Threshold

~
J
J Bandpa" f--
cur
Filter and
Vee t
+50 V
Receive
I Amplifier

Limiter
I
I Mode
Transmit Data

Receive Data
Transm It Carner
J Low Pass
Filter
, Duplexer
l
Enable Long Space Disconnect
Data Terminal

Communi
cations
Ready

Clear to Send
Receive Data Rate
J +50 V

MC6860 Enable Short Space Disconnec. t

TermInal Modem
Receive Break

Transmit Break
Enable Space Disconnect

~
1 ·v
1
-v

1
SWitch Hook DT
Break Release
SH
CST
Ring I nOlcator Datd Telephone
R I COl:Pler Line
Self Test

i'Yl OH

J L
Answer Phone

vSS
-=- T
-k 1 0 MH, C,y"al
"-~ DA
DR Gnd

·See Motorola Application Note AN 747 tor more mforrnation Lf

4-590
MC6860

When utilizing the 1.0 MHz crystal, external parasitic Transmit

capacitance, Including crystal shunt capacitance, must be Mode Date
Frequ,ncy
To.ranee·
s9 pF at the crystal Input. Reliable crystal oscillator start-up 0"9 l nate Mark 1270·Hz -015 Hz
requires that the VCC power-on transition time be > 15 0"9 l nate Space 1070 Hz 090 Hz
milliseconds. Answer Mark 2225 Hz -031 Hz
Answer Space 2025 Hz -071 Hz
Test Clock (TSn , The reference frequency tolerance IS not Included
A test signal input IS provided to decrease the test time of
the chip. In normal operation this Input must be strapped The proper output frequency IS transmitted wlthm 3.0 j<S
low. follOWing a data bit change with no more than 2 0 "s phase
discontinUity The typical output level IS 0.35 V (RMS) Into
Self Test (Sn
100 k ohm load Impedance.
When a low voltage level IS placed on this Input, the The second harmOniC IS typically 32 dB below the fun-
demodulator IS switched to the modulator frequency and damental lsee Figure 101.
demodulates the transmitted FSK signal. Channel
establlshement, which occurred dUring the Initial handshake, POWER-ON RESET
is not lost dUring self test. The Mode Control ouput changes
Power-on reset IS proVided on-chip to Insure that when
state dUring Self Test, permitting the receive filters to pass
power IS forst applied the Answer Phone output IS In the low
the local Transmit Carner
(,nact,ve) state. ThiS holds the modem In the inactive or Idle
mode until a SH or AI Signal has been applied. Once power
ST SH RI Mode
has been applied, a momentary loss of power at a later time
H -U-' H H may not be of sufficient time to guarantee a chip reset

•
H H L L through the power-on reset CirCUit
L I-r"' H L To Insure Initial power-on reset action, the external
L H L H parasitiC capacitance on Ai and SH should be < 30 pF
CapaCitance values> 30 pF may reqUire the use of an exter-
'Note maximum SH low time In Table 1
nal pullup resistor to V CC on these mputs In addition to the
Answer Phone (An Ph) pullup deVices already prOVided on chip
Upon receipt of Ring Indicator or SWitch Hook Signal and
Data Terminal Ready, the Answer Phone output goes high
[(SH + Fiil,DTRJ. ThiS Signal drives the base of a transistor
which activates the Off Hook, and Data Transmission control
lines In the data coupler Upon call completion, the Answer
.o
Phone Signal returns to a low level. ;;
Mode
The Mode output Indicates the Answer (low) or Originate
(high) status of the modem. ThiS output changes state when
.
"'
9
."
~
a Self Test command IS applied. 0.
E
..:
Clear-To-Send (CTS)
A low on the CTS output Indicates the Transmit Data in-
put has been unclamped from a steady Mark, thus allowmg
data transmission.

Receive Data (Rx Data) FIGURE 9 - TRANSMIT CARRIER SINE WAVE

The Receive Data output IS the data resulting from
demodulating the Receive Carner A Mark IS a high level

Receive Break (Rx Brk)

Upon receipt of a continuous 150 ms space, the modem
automatically clamps the Receive Break output high ThiS
output IS also clamped high until Clear-to-Send IS establish-
ed

Digital Carrier (FO)

A test Signal output IS prOVided to decrease the chip test
time The Signal IS a square wave at the transmit frequency.

Transmit Carrier ITx Car)

The Transmit Carner IS a digitally-synthesized sme wave
(Figure 9) derived from the 1 0 MHz crystal reference. The
Harmonics
frequency characteristics are as follows· Frequency
FIGURE 10 - TRANSMIT CARRIER
FREQUENCY SPECTRUM

4·591
 MC6860

TABLE 1 - ASYNCHRONOUS INPUT PULSE WIDTH AND OUTPUT DELAY VARIATIONS

(Time delays specified do not Include the 1-MHz reference tolerance)

Due to the asynchronous nature of the Input signals with respect to the Cln:.Ull Internal clock, a delay variation or Input
pulse width requirement WI!! eXist Time uelay A IS the maximum time for which no response will occur Time delay 8 IS the mini
mum time required to guarantee an Input response Input '>Ignal widths In the cross hatched region (I e, greater than A but less
than B) mayor may not be recognized as valid
For output delays, time A IS the minimum delay before an output will respond Time B IS the maximum delay for an output
to respond Output signal response mayor may not occur In the cross-hatched region (I e., greater than A but less than B)

INPUT PULSES OUTPUT DELAYS

,:," e.;;I
t- 32ms-i
[j 5TR

Tx Car·

ES5 =
~
s(~:~~~~sconnect) I

Low e'A""16 ms- j -J

Wi%I""'
B =- 51 ms
B == 34 ms

I
D'TR
~'
SH (I nltlate Space
I
~

t'6ms~ B = 34 ms
~

J
Disconnect)
An Ph

l,"nm.rB= 3 0 5 6 m s _

DTR
m (Inltlate~

1='m.~
(Loss of ~~s:coennect) I ~
Threshold)

t='65ms~
Rx Brk

B oe 51 ms
B'" 185 ms

Answer Mode
TO ~dueto Rx Car (1270 Hz)
DTR
~ ~

1-'6msLJ
I
(I nltlate Spacp
Disconnect)
B CO- 34 ms
C"TS or Rx Srk

C A0432ms~

B=451ms
~
DTR
~
~ ~
J I
T;B";'k
rw'~
t16ms~ J
An Ph

B "" 34 ms Ai or SH = Low l'6ms~ B - 34 ms

• Digital Representation (continued)

4-592
MC6860

TABLE 1 - OUTPUT DELAY VARIATIONS (contlnuedl

Tx Br~L____________________________ RXDat~ Space

I ~~----

l
I
~ II ~
Tx Car· k/SP

A" 16 ms-l I
Space An Ph

E'S'S = High
f- A" 16949 ms ---j I
B '" 34 ms ----l Us '" High
LBO 17034 ms ----j

RXDa~ Space To --.J

I ~---------- {Loss of I
Th,esho_'_d;..1 --7"-------------'~"'''''''~~
--I
AnPh

ESS =
Us=
Low
High
t I

'0 282 ms ----I

B = 301 ms
~

------I
I

I
CTS 0' Rx B,k I---- A" 32 ms

~-Bo51ms~
I

r- II
Orlgmate Mode

RXD~ Space Todue to Rx Car (2225 Hz)

I >----'------
>----:W:ia:::.::~----
l~1496mS ~II
An Ph
CTS "' R x B,k I
~
r--A 731 ms--J I
-----I
E'S'S = H Igh
0

E'LS ~, Low
B ~ 1520 ms --------+j I----- B C 752 inS

Originate Mode
RXD~ Space
TO -----,L - - , , TiS due to Rx Car (2225 Hz)
I - - - - -

I ~
~-A 132ms~
Rx Brk
c I
L - B 0151 inS ~ ---~
• Digital Representation

TABLE 2 - TRANSMIT BREAK AND DISCONNECT DELAYS

Function DeSCription Mon Max UOit
Tx Brk (Space Duration) 232 235 ms
Space Disconnect (Space DIHatlon) 3010 3023 ms
(5i'R High, ESD and T5 Lowl
0 0

Loss of Carner Disconnect 16965 17034 ms

(Measured from positive edge of m
to nega-
tive edge of An Ph, with AT, SH, and f5 = High)

Override Disconnect 16916 17101

(Measured from positive edge of
negative edge of An Ph, with f'5
AT or SH
= High)
to

:J

4-593
 MC6860

FIGURE 11 - FLOW DIAGRAM

No Ai No
Low Low

Ves

No No

No

I ES'T'R
Low

Ves

No
Answer
Mode

Ves

An Ph Goes HIgh An Ph Goes High

Transmit 2225 Hz
Remote Modem Sends
Rernote Modem Responds
2225 Hz
With 1270 Hz

Ves

No

4·594
MC6860

FIGURE 11 - FLOW DIAGRAM (CONTINUED)

Ves Answer No
Mode

Receive No No Receive
1270 Hz In >-=------.-----'-=< 2225 Hz In
Band Band

Ves Ves

Receive No No Receive
1270 Hz 2225 Hz
>150ms >150ms

•
C'Ts And R x Srk Go Lowl
I Unciamp Tx Data FromJ
Mark

No

Note 1

Loss Yes
at Rx Car
>51ms
Note 2
No

No CTS
low

L _ _N~O=-< 0 2335
Delay Note 2 Due to loss 01 Rx Cdr, tile 11l0(lem will (Iaillp
Tx Data to d Mark In ItH' Answer Mode and will
y.,
turn off Tx Car In the Originate Mode If Rx
Car IS deta( led Ilefore comliletion of Tx Srk or
Initiate Space Ols(.onnect, normal operation 01
Note 1 Transmit Break, Initiate Space Disconnect,
Tx Srk or Imtlate Space Disconnect Will con
and Receive Space are mutually exclusive events
Iinue until completion of their respective time
delays

4-595
 MC6860

FIGURE 11 - FLOW DIAGRAM (CONCLUDED)

• 0145
No

Delay
Ye, 014 s
Delav

No

No

3 0, No
Delay

03, Ye,
Delay

No
ES'S
Low

No

1 5, Ye,
Delay

No Ye,
IT"S
Low

No

17> Ye,
Delav

No

4-596
 ® MOTOROLA MC6862

2400 bps DIGITAL MODULATOR

MOS
IN-CHANNEL, SILICON-GATEI
The MC6862 IS a MOS subsystem designed to be Integrated Into a
wide range of eqUipment utilIZing senal data commUnication. 2400 bps
The modulator provides the necessary modulation and control func- MODULATOR
tions to Implement a senal data commUnication link over a vOice grade
channel, utilizing differential phase shift keYing (DKSPI at bit rates of
1200 or 2400 bps. Phase options are provided for both the U S. and in-
ternatIOnal markets The MC6862 can be Implemented Into a Wide range
of data handling systems, including stand-alone modems, data storage

.,, "'l:~
devices, remote data commUicatlon terminals, and I/O Interfaces for
counters. S SUFFIX
CERDIP PACKAGE
N-channel silicon-gate technology permits the M C6862 to operate us-
Ing a single voltage supply and be fully TTL compatible
The modulator IS compatible with the M6800 microcomputer family,
. I>' I ~ ~ ~
CASE 623

and proVides medium-speed data communications capability

~
• Clear-to-Send Delay Options P SUFFIX

•
PLASTIC PACKAGE
• 511-Blt CCITT Test Pattern CASE 700
• Terminal Interfaces are TTL Compatible
• Compatible Functions for 201 B/ C Data Sets

~
• CCITT and U S Phase OptIOns
• 1200/2400 bps OperatIOn . , -- I lSUFFIX
• Answer-Back Tone CERAMIC PACKAGE
I I CASE 716

BLOCK DIAGRAM PIN ASSIGNMENT

Delayed
VSS[~PDSC
Clear Request 13432 MHz External CTS2[ 2 23 ~Tx ClK
to Send to Send Clock Clock
4 5 10 11 CTS1[3 22PS5
CTS[ 4 21 pB4
DRTS[ 5 20 ~S3
Rpquest to Send 7
~B2
Delay Options I
crS1 3
CT52 2
13 Test Clock
TPE[ 6
RTS[ 7
19
18 PSl
Tx Mk[ 8 17 pSO
Tx Data[ 9 16 ~PSS
23 T ran5ml! Clock
CLK[ 10 15 ~DRS
Transmit Data 9 24 Olbll Clock

Data Rate Select 15

Ex ClK[ 11 14 pAn Bk
Phase Shift Salee! 16
VCer 12 13 ~TST

~: :: J
Answer Back 140----..0

1800 Hz
6·811
Data
Camer
19 82 Word
Generator
Vcc=Pln 12 Transmit MarkB ~ 18 B1
VSS=Plnl
17 80

4·597
 MC6862

MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage Vcc -03to+70 V
Input Voltage V,n This device contains cirCUitry to protect the In-
-03to +70 V
puts against damage due to high static voltage')
Operating Temperature Range TL to TH or electric fields however, It IS advised that rlor
MC6862 TA o to 70 'c mal precautions be taken to avoid application of
MC6862S, MC6862C -40 to +85 any voltage higher than maximum raled voltages
Storage Temperature Range Tstg -55 to + 150 'c to this high-Impedance CirCUit AeilabJilty of
operation IS enhanced If unused Inputs are tied to
THERMAL CHARACTERISTICS an appropriate logic voltage level Ie 9 , Bither
Characteristic Symbol Value Unit VSS or Vcel
Thermal Resistance
Ceramic Package 60
Plastic Package 8JA 120 'C/W
Cerdlp Package 65

POWER CONSIDERATIONS

The average chip-Junction temperature, T J, In °c can be obtained from'

T J = TA + IPO'8JAI 111
Where:
T A'" Ambient Temperature, °c
8JA'" Package Thermal Resistance, Junction-to-Amblent, °C/W

I PO'" PINT+ PPORT

PINT",ICCxVCC, Watts - Chip Internal Power
PPORT'" Port Power DIssipation, Watts - User Determined
For most applications PPORT<C PINT and can be neglected PPORT may become significant If the device IS configured to
drive Darlington bases or sink LED loads
An approximate relationship between Po and T J Ilf PPORT IS neglected I IS
PO=K-ITJ+273°CI 121
Solving equations 1 and 2 for K gives'
K = PO'IT A + 273°CI + 8JA'P 0 2 131
Where K IS a constant pertaining to the particular part K can be determined from equation 3 by measuring Po lat equillbrlumi
for a known T A. USing thiS value of K the values of Po and T J can be obtained by solving equations 111 and 121 Iteratively for any
value of T A

DC ELECTRICAL CHARACTERISTICS
IVcc ~ 50 ± 025 Vdc, VSS ~ 0, TA ~ TL to TH, all outputs loaded as shown In Figure 1 unless otherwise noted I
Characteristic Symbol Min Typ Max Unit
Input High Voltage VIH VSS + 20 - VCC V
Input Low Voltage VIL VSS - VSS+08 V
Input Current
IV,n=VSSI CTS1, CTS2, PSS, DRS,;;;:;;sr, and TXiii1K lin - - -02 mA
ii'i'SandTPE - - -16
Input Leakage Current IVIn~5 25 V, VCC=VSSI IlL - - 25 pA
Output High Voltage
IIOH~ -0 04 mA, Load AI VOHl VSS+24 - VCC V
IIOH ~O 0 mA, Load BI VOH2 VCC-05V - VCC
Output Low Voltage IIOL - 1 6 mA, Load AI VOL VSS - VSS+O 4 V
Input Capacitance If-O 1 MHz, TA-25'CI Cin - 50 - pF
Internal Power DIsSipation IMeasured at TA- TLI
IAII Inputs at VSS except Pin 13= 576kHz and ALL outputs openl PINT - 210 315 mW

Input TransItIOn Times, All Inputs Except 1 8432 MHz Input

tr,tf - - 10· pS
I From 10% to 90% POints I
Input TranSItIOn Times, 1.8432 MHz Input IFrom 0 8 V to 2 0 VI tr,tf - - 40 ns
Input Clock Duty Cycle, 1 8432 MHz Input (Measured at 1 5 V leveli DC 30 70 %
Tx Data Setup Time IFlgure 2) ts 35 - - p.s
Tx Data Hold Time IF,gure 21 tH 35 - - P.s
Output TranSition Times tr,tf - - 50 pS

-MaXimum Input TranSition TImes are sO 1 x Pulse Width or the speCified maximum of 1 0 ",5, whichever IS smaller

4·598
MC6862

FIGURE 1 - OUTPUT TEST LOAD FIGURE 2 - TRANSMIT DATA SETUP

AND HOLD TIME
~C-; -l
Rl=25kll
iI Tx CL K
J
MMD6150
or Equlv
ts
I tH

-I
I I

I RL
60k MMD7000
I
I
Tx Da ta
~ K
I ±1% or EqUiv

1 -=- 1
_ _ _ --1 Note Tlmmg measurements are referenced to and from a low
voltage of 0 8 volts and a hIgh voltage of 2 0 volts. unless
CT = 20 pF = total parasItIc capacItance. whIch Includes otherwise noted
probe. wIfing, and load capacitances

FIGURE 3 - 2400 bps MODULATOR INTERFACE

-10

-20
•
d8 -30

-40
RS-232
-liD

1.0 2.0 3.0 4.0 6.0

kHz
B5 Option A (CCITT)
Signal Spectra
B4

B3 OPSK Signal
MC1406
MC6862 to Line
B2 D/A
Modulator
Converter
Bl

BO Option 8 (U.S.)
Signal Spectra
0

-10

-20

-30

-40

-60
18432 MHz
to 005% 1.0 4.0 5.0
3.0
kHz

4-599
 MC6862

DELAY TIMINGS ISee Figures 4 and 51

Characteristic Symbol Min ryp Max Unit
~ to DBC Delay tl - - 8 P.s
DBC to RrS Delay t2 45 P.s
R'rn-15IITS Delay 13 - - 35 P.s
R'rn-~Del.y
CTSI =0, CrS2= 1 a - 35 P.s
CrSl = 1, CTS2=0 4" 855 - 935 ms
CrS1 = 1, CTS2= 1 249 - 264 ms
CTSI =0, CTS2=0 147 a - 154 a ms
CTS-DBC Delay
CTSI = 1, CTS2=0
t5
- - 35
p.s
CTSI = 1, CrS2= 1 - - 35
CTS1-0, CTS2-0 - - 35
RTS to crs Low 16 - - 160 ms
RTS Min Delay 17 167 ms
DBC to DRTS Delay IS 35 P.s
DBC Cycle Time IDBC 833 28 83333 83337 p.s

·The reference frequency tolerance IS not Included

I FIGURE 4 - R'rn-C'ffi AND R'fS-Diii'S DELAYS

2:'~~S Tx ClK

1200 bps Tx CLK

Mode

DBC

RTS~~~~~~ __________________________________________-+___________

RTS-crs delay options are selected by Ihe CTSI and CrS2 In- i5Ri'S Will go low Within t3 of the ne~ transilion 01 RTS With
puts, and are slated as lime delay Interval 4 An RTS Input signal the exception of the no-delay option, CTS Will go low within 15 of
synchronized about pOint A Will synchronize CTS With the positive the positive transition of D8C, follOWing the t4 delay selected ThiS
transition of DBC ID,blt Clock I Delay 4 IS measured with respect to applies when lfrn' IS synchronized to POint A as shown
the negative tranSition ofm If RTS goes high and remains high", 20 p.s Wllhln time Interv~
!ITS" signals synchronized with Ihe positive Iransltlon of DBC a reset of the Internal RTS-rn tlmer function Will occur If ~
lpolnl BI, Will resuilin the same crs delay 141 For thiS case the goes high for less than 20 P.s, the CirCUli mayor may not respond to
negative tranSition of CiS" IS synchronlzed With the negative tranSI-
tion of DBC with delay 4 measured with respect 10 the negative
thiS momentary loss of the m Signal

transition of R'i'S.

Note Timing measurements are referenced to and from a low voltage of 0 8 volts and a high voltage of 2 0 volts, unless otherWise noted

4·600
MC6862

FIGURE 5 - LOSS OF RTS TO ORTS DELAY

DBC

CTS

DRTS ---~.
-r-
•
A positive tranSition of RTS after CTS has become active can go high Within t8 of the next negative tranSition of DBC If RTS were
result In different functional characteristics of the CTS and DRTS to go low after t7, the RTS-CTS delay times given In Figure 4 will
output signals, depending on the time duration that RTS remains in- result
active If ATS goes high In the shaded region shown, and then returns
Under all conditions, CTS will go high within t3 following a low within time Interval t6, the negative tranSition of CTS will follow
positive transition of RTS If RTS goes high In the shaded region within 35/J-s, and "B1ITS will remain In the active or low state Under
shown (j e , synchronized to the positive tranSition of DBc) and re- these conditions, the normal Ri"S-CTS delay times are not en-
mains high beyond the time Interval defined as t7, then ORTS will countered when RTS IS reactivated If RTS goes low for less than
20 p's, the Circuit mayor may not respond

NOTE Timing measurements are referenced to and from a low voltage of 0 8 volts and a high voltage of 2 0 volts, unless otherWise noted

DEVICE OPERATION

GENERAL the negative transition of RTS, and goes negative within t3

Figure 3 shows the modulator and Its Intra-connections of the negative transition of RTS I Figure 41 The delay from a
The data to be transmitted IS presented In synchronous serial positive tranSition of RTS to a positive tranSItIOn of DRTS IS
format to the modulator for converSion to DPS K Signals shown In Figure 5 The DRTS delay aliows data within the
used In transmission The modulator output IS digital, modulator to be transmitted before transmission IS Inhibited
therefore, a DI A converter and a filter transform the Signal to
an analog form Clear to Send (eTS)
The control functions prOVide four different Clear-to-Send CTS follows RTS to both the logiC 0 and logiC 1 levels The
delay options An Answer-Back tone IS available for delay from a negative transition of rn to a negative CTS
automatic answering applicatIOns The modulator has a transition IS selectable by external strapping of CTS 1 and
built-In 511-blt pseudorandom pattern generator for use In CTS2 The delay from a positive tranSItIOn of RTS to a
system diagnostic tests. positive CTS tranSItIOn IS less than t4
CTS Will go low within t5 after the positive transition of the
INPUT /OUTPUT FUNCTIONS Dlblt Clock (see Figure 41 except when the non-delay opllon
IS selected For the no-delay optIOn, CTS follows fiTS within
Request to Send (RTS) t5
The RTS Signal from the data terminal controls transmiS-
Sion from the modulator A low level on m activates the RTS-CTS Delay Options (CTS1, CTS2)
modulator data output A constant mark, for synchroniza- The RTS-CTS delays are selectable according to the
tion, IS sent dUring the R'i'S to CTS delay Interval Termina- follOWing strapping options
tion of the transmission IS accomplished by taking RTS high
(see Figures 4 and 51. Ri'S-CTS Delay CTSI CTS2
00+ 0035 ms, - 0 0 ms 0 1
Delayed Request to Send (ORTS) 855 to 935 ms 1 0
ThiS output can be used to control transmission as 24 90 to 26 4 ms 1 1
speCified by the Transmit Mark control Input Lil'iT"S follows 147 0 to 154 0 ms 0 0

4-601
 MC6862

Transmit Mark (Tx Mk) selected by the Test Pattern Enable Signal or any other Signal
The Transmit Mark control allows the system designer to that IS found SUitable
select whether the Delayed Request to Send actlvitates and The scrambling of data In the data comm environment IS
deactivates the transmission on the modulator chip or off the not done In an attempt to encrypt information In the normal
chip in the output amplifier. sense of the word Rather, the purpose of the scrambling of
When Tx Mk IS high, transmission IS controlled on the data IS to guarantee that With respect to the modem carner,
modulator ChiP, and occurs from the chip only when i5iii'S there IS always random data on the line With little chance for
or Answer Back IS In the logiC 0 state (see Figure 6) a long string of ones or zeros to exist ThiS IS particularly Im-
When Tx Mk is low, transmission IS controlled off the portant If an adaptive equalizer is being Incorporated at the
modulator chip. In thiS mode, the modulator chip transmits demodulator. The adaptive equalizer Will require reasonably
marks at all times except when data or an Answer-Back tone evenly distributed data to optimize ItS statistical response to
IS being transmitted (see Figure 61. the Incoming Signal The normally used code IS the CCITT
511 sequence which IS EXOR'd With data.
Test Pattern Enable ii'PE) The test pattern generator can be enabled only when CTS
A 511-blt test pattern generator IS contained on the and FiTSare logiC O. If TPE IS activated outSide thiS time In-
modulator chip ThiS pattern IS In accord with CCITT terval, the previously stated mornand 1i'rS-l5R'f'S
speclflcallOn V52. delays, shown In Figures 4 and 5, are not valid
-I,tIe 511-bIt test pattern IS activated by applYing a logic 0 to
TPE.~ark (logic 1) condlllOn on the Transmit Data Input
Data-Rate Select (DRS)
with TPE activated (logic 0) causes the test pattern to appear The modulator can transmit at either 2400 bps or 1200 bps
at the data output. A space (logic 0) condition on Tx Data Both data rates utilize an 1800 Hz carner Signal and employ
with 'TPt activated causes the test pattern data to appear in- phase shlfllng at 1200 Hz. The 2400 bps rate IS obtained by

•
verted at the data output. encoding two bits of data Into each phase shift. The 2400 Hz
Although the Motorola 2400 bps modulator contains a rate IS selected by applYing a logic 1 to the Data-Rate Select
CCITT 511 test pattern generator It does not Incorporate the lead. The 1200 Hz rate IS selected by applYing a logiC 0 to
511 data randomlzer or scrambler. DRS.
Random data applied to Tx data With TPE activated causes
Phase-Shift Select (PSS)
the test pattern data to be scrambled (exclUSive NORed) With
the data, and the result appears at the data output Option A (CCITT) or OpllOn B IU S ) phase shift can be
The MC6863 demodulator does contain a built-In data selected for 2400 bps operation The Input data format and
descrambler, which IS enabled by TPtlnput gOing active To phase shift relationship for these two options are as follows:
scramble data using the modulator, the cirCUit In Figure 7
must precede the TX Data input of the modulator Tx Data IS PSS=O PSS=1
added to the scrambler output pattern. Then the data IS
Data Option A* Option B
delayed by a full data bit before being transmitted by the 00 00 +46 0
modem. ThiS assures a proper Transmit Data/Transmit 01 +90 0 +135 0
Clock phase relationship. 11 +180 0 +225 0
If the data scrambler IS to be an opllOnal feature, then the 10 +270 0 +315 0
transmit data multiplexer would also have to be bUilt ThiS IS • See example Figure 8

FIGURE 6 - TRANSMIT MARK CONTROL

~ ~r--------------------------------------

I I

No An Sk No No
Signal Signal Signal Mark Data Signal
T'X"'Mk,., High

An Bk
Mark Signal Mark MlIrk D .... Mark
Tx Mk "" Low

4-602
MC6862

FIGURE 7 - MODULATOR CCITT 511 DATA SCRAMBLER

1. . . . ------ 511 Data Scrambler - - - - 4..~l {. . . .

-----1-Blt Delay - - - - - -... l
Q D Q

TxCLK

Tx Data .-------1

TPE ...-----!--------1~-...q

•
\:I-----,;,.c:.--.
Tx Data
To Pin 9 Modulator

{ ........----Data Multiplexer

FIGURE 8 - EXAMPLE-CARRIER PHASE SHIFTS FOR OPTION A

Senal Data 11011000 Data Phase Shift

"\
D,b,t 00 0"
01 90
11 01 10 00 11 180
180" 90" 270" 0" 10 270

For 1200 bps operation, Option C (CCITTI or Option 0 Transmit Data (Tx Data)
(U S I phase shift can be selected Transmit Data IS the serial binary Information presented
for DPSK modulation A high level represents a mark For
PSS~O PSS~1
timing, see Transmit Clock (Figure 41.
Data Option C Option D
0 +90" +45 0 Transmit Clock (Tx CLK)
1 +270" +225" A 2400/1200 Hz Transmit Clock output IS provided for the
commUnication terminal The Transmit Data signal IS sampl-
Option C IS selected by applYing a logic 0 to the Phase ed on the POSitive transltton of Transmit Clock The Transmit
Shift Select lead when the Data Rate Select lead IS strapped Data to Transmit Clock setup and hold time requirements are
for 1200 bps operation (logic 01 Option D IS selected by ap- shown In the Electrical Characteristics Table and In Figure 2.
plYing a logic 1 to PSS With DRS at logic 0 The phase shifts
Dibit Clock (DBC)
shown are the difference In phase between the signal at the
end of one dlblt period and the new signal at the beginning A 1200 Hz Dlblt Clock Identifies the modulation tlrnlng
of the next dlblt. ThiS Signal goes negative less than 100 "S prior to the start of
dlblt modulation

4-603
 MC6862

External Clock (Ex ClK) from a transition on An Bk to the appropriate signal at the
A 2400/1200 Hz clock signal applied to the External Clock modulator chip output IS less than 2 ms
lead causes Transmit Clock to be synchronized with Ex elK ActlvallOn of An Bk la logiC 01 will disable all other opera-
This input must have an accuracy within ± 0.005% tion modes Including the Tx Mk function, and Will reset CTS
When no transitions occur on this Input, the internal clock to an Inactive state along With the RTX-CTS Internal timer
provides the 2400/1200 Hz transmit tlmmg signal. Fast syn- An Bk should therefore be activated only before mltlallng
chronization of Tx ClK to Ex ClK IS not provided on the RTS or after loss of the ORTS output signal The combma-
chip. When Ex eLK IS not used, it should be tied to either the tlon of a logic 0 on An Bk With a logiC 0 on TPE IS not used In
logic 0 or logic 1 state. normal system operation, and hence IS used as a reset Input
dUring deVice test
1.8432 MHz (ClK)
This Input must be a square wave With rise and fall times Digital Output (BO-B5)
of less than 40 ns and a 50 ± 20% duty cycle The clock ac- These outputs are desl::Jned to Interface With a 6-blt
curacy must be written ± 0.005% dlgltal-to-analog converter The resultant signal out of the
0/ A IS the differential phase shift keyed signal quantIZed at a
Answer Back (An Bkl 14.4 kHz rate A low-pass filter can then be used to smooth
A logic 0 level applied to Answer Back causes a 2025 Hz the data transitions. BO IS the least-significant bit, and the
carner to be generated on the modulator chip mstead or a positive level the active state
phase shifted 1800 Hz carner A logic 1 level applied to An Bk
enables the modulator to generate the normal phase shifted Test Clock (TST)
1800 Hz carner signal, as shown In Figure 6 The time delay A test signal Input IS provided to decrease test time of the
chip. In normal operation this input must be strapped low

4..604
 ® MOTOROLA
MC6870, MC6871
series
MC6871A
CRYSTAL osc.
1.0 MHz
@MOTOROLA

actual size

Two-Phase Microprocessor Clocks

Designed to drive the Motorola MC6800 MPU
The Functional Module approach to data communications hardware Reliability- Decreased Component Count -Thick film hybrids
design significantly decreases the time between the "Idea" stage and offer a reliability advantage that comes pnmanly from reduced com-
the marketable product. ponent count and therefore reduced interconnections Further, the
A fundamental bUilding block In a modular microcomputer system IS Single hermetic seal on the hybnd package reduces the failure rate
the 2-phase clock oscillator used to drive the microprocessor whereas In a discrete deSign a separate sealing process With an
Motorola IS uniquely qualified to provide thiS bUilding block because of assOCiated failure rate IS needed for each component
expertise In the three relevant fields oscillator design. quartz crystal High Density Packaging -The hybrid MPU clock allows compact
technology. and thick film hybrid Integrated CirCUit manufacturing microcomputer deSign It takes up only 1 34"x .840" space and has a
ThiS one-of-a-klnd expertise has created several clocks designed to seated height of 200"
drive Motorola's MC6800 Microprocessor ThiS plug-In Unit contains Ruggedized Design-MaXimum reliability at minimum cost IS the

•
the crystal. the oscillator CirCUit. the NMOS and TIL drivers, and the result of combining three of Motorola's fields of experience. quartz
waveshaplng and Interface CirCUitry, all the components necessary to crystal technology, clock OSCillator deSign, and thick film hybrid inte-
provide the cntlcal non-overlapping 2-phase waveforms used by the grated CirCUit manufactUring. Mass automated production techniques
MC6800 MPU assure volume production. Gold plating of all crystals and Class 100
FEATURES clean room processing testify that no short cuts are taken that might
diminish reliability EnVIronmental testing proves the effectiveness of
Clock Module-Each clock module requires only a single 5 volt
the rugged deSign for those apphcaliOns In which shock and Vibration
power supply The NMOS outputs can drive highly capacitive loads
are likely hazards
ranging from 80 pf to 160 pf end meet all MPU Input waveshape and
timing requirements Complete Process Control- Motorola IS the only totally Integrated
manufacturer of quartz frequency control deVices; full control of all
Each TIL output signal leads the <l>z NMOS so that additional system
processes from growing, sawing. lapping, and finishing quartz to
device delays can be accommodated All TTL outputs are buffered so
combining it With other components Into an electroniC product - the
they can drive 5 TIL devices and maintain all output speCifications MC6870A, MC6871A, and MC6871B MPU clocks.
Each module IS crystal-controlled and IS compensated for vanatlons In Volume Production - Production faCilities are Oriented to mass
temperature, voltage. and load The standard frequency of each
automated producliOn techniques. And, If required. capital for expan-
model IS 1 MHz; however. other frequencies between 250 kHz and 2 5 Sion IS available to meet even greater reqUirements.
MHz can be ordered

environmental specifications solderability specifications

Temperature Cycle: ±5 ppm max, 0 to Materiall:
120°C, 3 cycles. 2 hrs max each, 25 1 1 Solder 60% lin and 40% lead
±2°C ref 1 2 Flux The flux shall be 25 percent by
Shock: , aOOG's 035 mllilsec, 1(2 Sine walle, weight of Grade WW rosin and 75 percent
3 shocks each plane by weight of 99 percent Isopropyl alcohol
Vibration: 10-55 Hz. 060" D A , 55·2000Hz, Procedure:
35 G's Duration Tlme-12 Hours 2 1 Solder Bath The solder bath shall be
Humidity: 85% Rei Humidity. @ +85"C, maintained at 232 ±6°C
250 Hours
22 Solderability DIp the terminals Into the
flux to the depth that IS to be soldered or to
mechanical specifications a maximum depth of 025" from the body
GroSi Leak relt: All units 100% leak tested of the OSCillator Keep them In the flux for at
In de-IOnized HID least 5 seconds Withdraw them from the
HermeUc Sealed Package: Mass spectrom- flux DIp them Immediately Into the molten
eter leak rate less than 2 x ,0 8 almos solder to the same depth Keep them In the
cc/sec of helium molten solder for 2 to 5 seconds
8eal Strengh: 20 Ibs max force perpen- Withdraw them and allow the solder to
dicular 10 lOp and bottom cool In air
Pin Material: Phosphor bronze, 114 hard, Requirements:
Grade A 00003" Ihlck gold flash finish 3 1 The terminals are conSidered solderable
Bend Telt: Will Withstand maximum bend
of 90° reference to base for 1 bend
Marking Ink: Epoxy, heat cured
I'
and acceptable for electncal connection
purposes 90 percent of the cold solder
surface IS uniform and free from breaks and
Solvent Reliltance: Isopropyl Alcohol pinholes The other 10 percent of the cooled
Tncholoroethane Freon TMC No marking or solder surface may show only pinholes,
seal destruction Dipped 1 minute @ +25°C VOids, or rough spots that are not
±5°C In solvent concentrated to one area
Note (1) Unit can be cleaned by only one
type solvent listed
Note (2) UltrasoniC degreaser not to be
used unless frequency and Vibration
of cleaner specified

4·605
 MC6870A +5V DC ~ ~~ II, NMOS
limited funcUon microprocessor clock GND MC6870A p, NMOS
L -______~ ~TTL
250 kHz to 2.5 MHz

specifications
Rlting Symbol Vllue Unit
Supply Voltage V" 5.00+5% Vdc
Operallng Temperature Range T. Oto +70 ·C
Storage Temperature Til'll -55 to +125 ·C
Power Supply Dram (max.) I.. 100 mA

ELECTRICAL CHARACTERISTICS (V"

= O· to 70·C. unless otherwise noted)
=
5.0 ± 5%. V.. = O.T.
Chlrlcteriltlc Symbol Min Typ MI. Unit
Frequency PIN CONNECTION
Operatmg Frequency I, .250 2.5 MHz 1 GND
Il'"requency slaomty_ Iinclusive ±.Ul Ulo
01 calibration tolerance at 3 NC
+25·C. operating temperature.

•
5 0,TTL
mput voltage change, load
change, aging, shock and 7 V" (+5VDC)
vibration)
12 0. NMOS
NMOS Outputl It 1.0 MHz Operltlon""
Pulse Width (meas. at Tl2l,H 430 ns 13 0, NMOS
V,,= -.3V dc level) Tl2l,H 450 ns GND
18
LogiC Levels VOLC V.. ·.l - V.. +3 Vdc
VOHC V,,-.3 - V,,+.1 Vdc 20 NC
Rise and Fall Times t. 5 12 50 ns NC
22
t, 5 12 50 ns
'Overshoot/Undershoot 24 NC
Logic "I" V,,-.5 V,,+.5 Vdc
Logic "0" Vos V.. -.5 V.. +.5 Vdc
Pulse duration 01 any over-
Note All dlmenstOns are In Inches
shoot or undershoot Tos 40 ns
Period @ 0.3V dc Level tcyc 1.00 us
Edge Timing @ V,,_0.3V dc Tx 940 ns
NMOS Relationship t.., 0
@ +0.5V dc Level I., 0 8.0 us
nLOutpull
In rei. 10 0, NMOS @ 0.3V dc
0, TTL @ +1.4V dc T. 15 30 45 ns
TH 10 25 40 ns
Logic Levell VOH 2.4 3.2 Vdc
VOL .3 .4 Vdc
Rise and Fall Times
.4Vand 2.4V t. 15 ns
2.4Vand .4V I, 15 ns
Logic "0" Sink (lGale) 10L -1.6 mA
LogiC "I" Source (lGate) 10H +40 uA
Currenl Outpul Shorted Isc -18 -57 mA
Load
NMOS-Load Capacity l2l" l2l, I eN""" I 80 120 160 I pi
TTL-No. 01 Loads I I I 5 I ttl
TTL-Load Capacity I Cm I I I 50 J pi
*Into speCified test load
"'Apply the following parameters for frequencies other than 1 0 MHz
T\>,H=O 5 (P-140) ns
T\>,H=O 5 (P-l00) ns
Tx=(P-60) ns
where P=deSlred penod of operation In nanoseconds

4·606
MC6870A (continued)
DIMENSIONS
- 1 .340 ------J
1 MAX I
MC6870A
MPU CLOCK .840
FREQ.-
~~~~~i~~L;: ~MAX.
SYMBOL DENOTES
PIN #1 LOCATION

•227 ± .01OL
J i
~ 'IT 'IT 'ITt.~20+
~
L183 MAX •

.010
-I i- 015- 021 (DIA PIf~S) -

WAVEFORM TIMING
(ALL TIME IN NANOSECONDS)

T0,H

~------------~-----T,-------~

ld,
!oo----T0,H-----01 I !4---T0,H--------IM
II
V,,-.3V

.5V
F-----------------"f .3V

l.4V 1.4V 1.4V 1.4V l,4V

TEST CIRCUIT
1.01'F

111---+-......,

SCOPE
PROBES
- A
OSCILLOSCOPE
TEKTRONIX
25 pFd M
~ 7904 OR EQUIV
B

'- 100 MHz

FREQUENCY
COUNTER
HP5327C
OR EQUIV
CUL - MAX CAPACITY 50 pF

CN"os-120 pF ± 40 pF IS THE SPECIFIED

MAX LOAD CAPACITANCE
Rs-(22n) SIMULATES
REAL PART OF MPU
1
TO EXTERNAL
THAT SIMULATES THE MOTOROLA FREQUENCY
MC6800 MPU INPUT STANDARD

4·607
 +5VDC ~ ~ 2xfc
MC6871A GND MC6871A 0, NMOS
0,NMOS
full function microprocessor clock 0,TTL
850 kHz to 2.5 MHz f f
HOLD 1 MEMORY
MEMORY CLOCK

READY
specifications
Rating Symbol Value Unit
Supply Voltage V" 5.00-+-5% Vdc
Operattng Temperature Range T, o to +70 °C
Storage Temperature T,tg -55 to +125 °C
Power Supply Drain (max.) I.. 100 mA
ELECTRICAL CHARACTERISTICS (V" = 5.0 ± 5%, V.. = O,T,
= 0° to 70°C, unless otherWise noted)
Characteristic Symbol Min Typ Max Unit
Frequency
Operatlnq Frequency I, 850 25 MHz PIN CONNECTION
IFrequency staoility (InClUSive ±01 %
01 calibration tolerance at 1 GND
+25°C, operating temperature,
Input voltage change, load 3 MEMORY CLOCK
change, aging, shock and 5 0,TTL
Vibration)
NMOS Outputs at 1.0 MHz Operation'" 7 V" (+5VDC)
Pulse Width (meas. at T0,H 430 ns 12 0, NMOS
V,,= - 3V dc level) T0,H 450 ns
Logic Levels VOLe V.. -.1 - V.. +.3 Vdc 13 0, NMOS
VoHc V,,-3 - V,,+-1 Vdc

•
18 GND
Rise and Fall Times t, 5 12 50 ns
t, 5 12 50 ns 20 HOLD 1
• Overshoot/ Undershoot 22 MEMORY READY
Logic "1" V,,-.5 V,,+ 5 Vdc
Logic "0" Vas V.. - 5 V.. + 5 Vdc 24 2xfc
Pulse duration 01 any over-
shoot or undershoot Tos 40 ns
Note All dimenSions are In ,nches
Period @ 0.3V dc Level tc~ t 100 us
Edge Timing @ V,,=O 3V dc Tx 940 ns
NMOS Relationship td' 0
@ +0 5V dc Level td' 0 80 us
TTL Outputs
In ref 100, NMOS @ 0 3V dc
0, TTL T, 15 30 45 ns
@ 1 4V de TH 10 25 40 ns
Memory Clock Te 30 50 70 ns
@ 1 4V dc TJ 20 40 60 ns
2xlc @ 1 4Vdc T, 40 80 120 ns
logic levels VOH 24 32 Vdc
VOL .3 A Vdc
Rise and Fall Times
o4V and 204V t, 15 ns
2AVand AV I, 15 ns
LogiC "0" Sink (lGale) 10L -16 mA
LogiC "1" Source (lGale) 10H +40 uA
Currenl OUlpul Shorted Ise -18 -57 mA
load
NMOS-Load Capaclly 0,,0, CNMOS 80 120 160 pi
TTL-No. 01 Loads 5 ttl
TTL-Load Capacily GTTL 50 pi
logic Inputs" ("O" Level Applies HOLD or MEMORY READY)
Holds 0, NMOS 'High', 0, HOLD 1 -.2 +4 Vdc
NMOS 'Low', 0, TTL 'Low'
Holds 0, NMOS 'Low', 0, NMOS MEM- -2 +4 Vdc
'High', 0, TTL 'High', and ORY
MEMORY CLOCK 'High' READY
"'nto speCified test load
'**Must be externally held at "1 ' level (2 4V min, 5 OV max) If not used
* *" Apply the follOWing parameters for frequencies other than 1 MHz
T¢,H=O 5 (P-140) ns
T¢,H=O 5 (P-100) ns
Tx=(P-60) ns
where P=deslred period of operation In nanoseconds

4-608
MC6871A (continued)

MC6871A
MPU CLOCK
--1- --1.100

~~:="='=-::'::'
-::-::='='=-
FREO - I,. 1M; MOTOROLA ==~ ~,8t MAX
I
.600
DIMENSIONS L SYMBOL DENOTES :!: .005
PIN #1 LOCATION
j L
J l - f - T 8 3 MAX

,227 :!: ,OlOe] ~ tr ~ 'If L. 020 + .010 ,400

--'-~f- ,015,,021 DIA (PINSI :!: .005

WAVEFORM TIMING
(ALL TIME IN NANOSECONDS)

TO,
TTL

MEMORY
CLOCK
1,4V •
lAV

2xfc

~--__-_nMEMORY CLOCK

w........----< 02 NMOS
Q-I........
.-
OUT
SCOPE A
PROBE S OSCILLOSCOPE
25 pF M AX TEKTRONIX
7904 OR EOUIV
"1= B
L-______________--{ HOLDl
1 O~F L-________________ -< MEMORY READY
~
100 MHz
2xfc FREOUENCY
COUNTER
Cm - MAX CAPACITY 50 pF HP5327C
CNMOS - 120 pF ± 40 pF IS THE SPECIFIED I cm OR EOUIV

~
MAX LOAD CAPACITANCE
THAT SIMULATES THE MOTOROLA
MC6800 MPU INPUT Rs-(22.!l.) SIMULATES
REAL PART OF MPU TO EXTERNAL
'HOLD AND MEMORY READY MUST FREQUENCY
STANDARD
BE EXTERNALLY HELD AT 1
LEVEL (2 4VDC MIN. 5 OVDC MAX)
WHEN NOT USED

4-609
 +5VDC ~ MC6~~ 0,
2xfc
MC6871B GND NMOS
0,NMOS
0,nL
alternate function microprocessor clock
250 kHz to 2.5 MHz
~~ 0,UNGATED
HOLD 1 HOLD 2

specifications
Rating Symbol Value Unit
Supply Voltage V" 5.00+5% Vdc
Operating Temperature Range T, o to +70 "C
Storage Temperature T"g -55 to + 125 "C
Power Supply Drain (max) I.. 100 rnA

ELECTRICAL CHARACTERISTICS (V" = 50 ± 5%, V.. = O,T,

= 0" to 70"C, unless otherwise noted)
Characteristic symbol Min Typ Max Unit
Frequency
Operating Frequency I, 250 25 MHz PIN CONNECTION
Frequency stability (inclusive ±01 % 1 GND
01 calibration tolerance at
+25"C, operating temperature, 3 0, TTL UNGATED
Input voltage change, load
change, aging, shock and 5 0,TTL
vibration)
7 V" (+5VDC)
NMOS Outputs at 1.0 MHz Operation'"
12 0,NMOS
Pulse Width (meas at T0,H 430 ns
V" = - 3V dc level) T0,H 450 ns 13 0, NMOS
LogiC Levels VOle V.. - 1 - V.. + 3 Vdc

•
18 GND
VoHc V,,-3 - V,,+.1 Vdc
Rise and Fall Times t. 5 12 50 ns 20 HOLD 1
tf 5 12 50 ns
22 HOLD2
• Overshoot/Undershoot
LogiC "1" V,,-5 V,,+.5 Vdc 24 2xfc
LogiC "0" Vas V.. - 5 V.. +.5 Vdc
Note 4xfc available on request
Pulse duration 01 any over-
shoot or undershoot Tos 40 ns Nole All dimenSions are In Inches

Period @ 0 3V dc Level tCyc 1 00 us

Edge Timing @ V,,=O 3V dc Tx 940 ns
NMOS Relationship td • 0
@ +05Vdc td, 0 8.0 us
TTL Outputs
In reI to 0, NMOS @ 0 3V dc
0, TTL @ 1 4V dc T, 15 30 45 ns
TH 10 25 40 ns
0, Ungated @ 1 4V dc Tc 30 50 70 ns
TJ 20 40 60 ns
2xlc @ 1 4Vdc T. 40 80 120 ns
I
Logic Levelii VOH 2.4 3.2 Vdc
Val .3 .4 Vdc
Rise and Fall Times
.4V and 2.4V t. 15 ns
2.4Vand 4V tf 15 ns
LogiC "0" Srnk (lGate) 10l -16 mA
LogiC "1" Source (lGate) 10H +40 uA
Current Output Shorted Ise -18 -57 rnA
L9ad
NMOS-Load Capacity 0,,0, 1 CNMOS 1 80 1120 1 160 1 pI
TTL-No. of Loads 1 I I I 5 ttl
TTL-Load Capacity I Cm I I I 50 pf
Logic Inputs" ("0" Level applies HOLD)
Holds 0 f NMOS 'High', 0, HOLD 1 -.2 +.4 Vdc
NMOS 'Low', 0, TTL 'Low'
Holds 0, NMOS 'Low', 0, NMOS HOLD 2 -.2 +.4 Vdc
'High', 0, TTL 'High'
* Into specified test load
"Must be externally held at "1" level (2 4V min, 5 OV max) If not used
•• * Apply the follOWing parameters for frequencies other than 1 MHz
T¢,H=O 5 (P-140) ns
T¢,H=O 5 (P-l00) ns
Tx=(P-60) ns
where P=deslred period of operatIon In nanoseconds

4-610
MC6871 (continued)
--1.100

FREO
MC6871B
MPU CLOCK I .840

=:::J~ MAX
}l:::::C=M=-O=T=O=R=O=LA=--='
DIMENSIONS
SYMBOL DENOTES
PIN #1 LOCATION

Jr-----------J' ~
~3MAX

.227 ± , 010ctr tr 'll' tr UL,020 ± ,010

...j I- .015-.021 DIA (PINS)

WAVEFORM TIMING
ALL TIME IN NANOSECONDS.

/I4--------------+----T, ---------1*
I-------------+---tcyc-----_o/

•
Ti1!,
NMOS .5V
,3V

Ti1!, 1,4V

~~TE~D~-----_..J

2xfc

~ __~_~o~,nL
UNGATED

r"!'---------1------1D fII, TTL

-A
SCOPE OSCILLOSCOPE
PROBE S TEKTRONIX
25 pF M AX 7904 OR EOUIV
~--------------<HOLD1 f= B
10l'F
~--------<HOLD2
Cm - MAX CAPACITY 50 pF ~-------<p---<2xfc
CNMOS - 120 pF ± 40 pF IS THE SPECIFIED
MAX LOAD CAPACITANCE
THAT SIMULATES THE MOTOROLA
*cm ~
100 MHz
FREOUENCY
COUNTER
HP5327C
MC6BOO MPU INPUT
OR EOUIV
'HOLD 1 AND HOLD 2 MUST BE Rs-(22,n) SIMULATES
EXTERNALLY HELD AT "1" LEVEL
(2 4VDC MIN. 50VDC MAX)
WHEN NOT USED
REAL PART OF MPU
~
TO EXTERNAL
FREOUENCY
STANDARD
4·611
 ® MOTOROLA MC6875
MC6875A

Specifications and Applications

InforIllation
M6800 TWO·PHASE
CLOCK GENERATOR/DRIVER
M6800 CLOCK GENERATOR
SCHOTTKY MONOLITHIC
Intended to supply the non-overlapping 1/>1 and 1/>2 clock signals INTEGRATED CIRCUIT
required by the microprocessor, this clock generator is compatible
with 1.0, 1.5, and 2.0 MHz versions of the MC6800. Both the
oscillator and high capacitance driver elements are included along
with numerous other logic accessory functions for easy system
expansion.
Schottky technology is employed for high speed and PNP-buffered
inputs are employed for NMOS compatibility. A single +5 V power

~
supply, and a crystal or RC network for frequency determination
are required.

"flN1N VU ~
• Typical MPU System with Bus Extenders

GND +5 V
</l1 (>2
c::J 4
-.:r
x fa MPU
L SUFFIX
CERAMIC PACKAGE
CASE 620

PIN CONNECTIONS

X1 vee
X2 MPU</>1
ADDRESS Ext In Reset Output
AND 4 x fo MPU</>2
CONTROL
BUS 2 x to Power-On Reset
Memory
DMA/Ref Grant
Ready
Bus¢2 OMAlRef Req
Ground Memory Clock

ORDERING INFORMATION
Device Temperatura Range Package
MC6875L I o to +70 0 C I Ceramic Dip
MC6875AL I -55 to +1250 C l Ceramic DIp

4·612
MC6875- MC6875A

ABSOLUTE MAXIMUM RATINGS (Unless otherwise noted TA ~ 250 e.)

Rating Symbol Value Unit
Power Supply Voltage Vee +7.0 Vdc
Input Voltage VI +5.5 Vdc
Operating Ambient Temperature Range TA °e
MC6875l o to +70
Me61!75Al ·55 to +125
NOTE
Storage Temperature Range T stg °e MC6875AL requires the use of a
Ceramic Package -65 to +150
heat sink See note to Thermal Data.

Operating Junction Temperature TJ °e

Ceramic Package 175

RECOMMENDED OPERATING CONDITIONS

I Rating I Symbol I V.lue 1 Unit
I Power Supply Voltage I Vee I+4.75 to +5.25 I Vdc
I Opar.ting Ambient Tempar.ture Range ITA I Oto+70 I
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted speCificatIOns applv over recommended power supply and temperature ranges.
TYPical values measured at Vee = 5.0 V and TA = 25 0 e.)
Characteristic Symbol Min Typ Max Unit
Output Voltage - High logic State
MPU ¢ 1 and 1/>2 Outputs V

•
(Vee = 4.75 V, IOHM ~ -200 "AI VOHM Vee - 0 6 - -
(Vee = 5.25 V, IOHMK = +5.0 rnA) VOHMK - - Vee + 1.0
Bus I/> 2 Output v
(Vee =4.75 V,IOHB = -10 mAl VOHB 24 - -
(Vee = 5.25 V, IOHBK = +5.0 mAl VOHBK - - Vee + 1.0
4 x 10 Output V
(Vee =4.75 V, VIH = 2.0 V,IOH4X • -500 "A) VOH4X 2.4 - -
2 x 10, DMA/Relr•• h Grant and Memory elock Outputs VOH 2.4 - - V
~ee = 4.75 V, IOH = -500 "AI
Reset Output VOHR 2.4 - - V
(Vee =4.75 V, VIH = 3.3 V,IOHR = -100 "A)
Output Voltage - low logiC State
MPU I/> 1 and I/> 2 Outputs \I
(Vee = 4.75 V, IOlM = +200 "AI VOlM - - 0.4
(Vee = 4.75 V,lOlMK = -5.0 rnA) VOlMK - - -10
Bus I/> 2 Output V
(Vec = 4.75 V,lOlB = +48 mAl VOlB - - 05
(Vec = 4.75 V, IOlBK = -5.0 mAl VOlBK - - -1.0
4 x 10 Output V
(Vec = 4.75 V, Vil = 0.8 V,IOl4X = 16 mAl VOl4X - - 05
2 x 10, DMA/Reiresh Grant and Memory Clock Outputs VOL 05 V
~CC = 4.75 V,lOl = 16 rnA)
Reset Output VOlR - - 0.5 V
(VCC = 4.75 V, Vil = 0.8 V,IOlR= 3.2 mAl
I nput Voltage - High logiC St.te V
Ext. In, Memory Ready and DMA/Reiresh Request Inputs VIH 2.0 - -
Input Voltage - low logiC State V
Ext In, Memory Ready and DMA/Refresh Request Inputs Vil - - 08

Input Thresholds Power.Qn Reset Input (Se. Figure 21 V

Output low to High VllH - 2.8 3.6
Output High to low VIHl 0.8 1.4 -
Input Clamp Voltage MC6875l Vie - - -1.0 V
(Vce' 4.75 V,IIC = -5.0 mAl MC6875Al - - -1.5
I nput Current - High logic State
Ext. In, Memory Reedy and DMA/Refresh Request Inputs IIH - - 25 "A
(Vec = 4.75 V, VIH = 5.0 V)
Power.Qn Reset IIHR - - 50' "A
(Vec = 5.0 V, VIHR = 5.0 V)
Input eurrent - low logiC State
Ext. In, Memory Ready and DMA/Refresh Request Inputs III - - -250 "A
(Vee = 5.25 V, Vil =0.5 VI
Power.Qn R.... lnput' IllR - - -250 "A
(Vee = 5.26 V, Vil = 0.5 V)

4-613
 MC6875. MC6875A

OPERATING DYNAMIC POWER SUPPLY CURRENT

Characteristic Symbol Min Typ Max Unit
Power Supply Currents
(VCC: 5.25 V. fosc: 8.0 MHz, VIL: a v, VIH: 3.0 V)
Normal Operation ICCN - - 150 mA
(Memory Ready and DMA/Refresh Request I nputs at
HIgh Logic State)
Memory Ready Stretch Operation ICCMR - - 135 mA
(Memory Ready Input at Low Logic State;
DMA/Refresh Request Input at HIgh Logic State)
DMA/Refresh Request Stretch Operation ICCDR - - 135 mA
(Memory Ready Input at High Logic State,
DMA/Refresh Request Input at Low Logic State)

SWITCHING CHARACTERISTICS
(These specifications apply whether the Internal Oscillator (see Figure 9) or an External Oscillator IS used (see Figure 10)
TYPical values measured at Vee = 5.0 V, T A = 2SoC, fa = 1.0 MHz (see Figure 8),

Characteristic Symbol Min Typ Max Unit

MPU <1>1 AND <1>2 CHARACTERISTICS
Output Period (Figure 3) to 500 - - ns

•
Pulse Width (Figure 3) tpWM ns
(fo: 1.0 MHz) 400 - -
(fo: 1.5 MHz) 230 - -
(fo: 2.0 MHz) 180 - -
Total Up Time (Figure 3) tUPM ns
(fo: 1.0 MHz) 900 - -
(fo: 1.5 MHz) 600 - -
(fo : 2.0 MHz) 440 - -
Delay Time Referenced to Output Complement (Figure 31
Output High to Low State (Clock Overlap at 1.0 V) tPLHM 0 - - ns
Delay Times Referenced to 2 x to (FIgure 4 MPU r/J2 only)
Output Low to High Logic State tpLHM2X - - 85 ns
Output High to Low Logic State tPHLM2X - - 70 ns
TransitIon Times (Figure 3)
Output Low to High Logic State tTLHM - - 25 ns
Output High to Low Logic State tTHLM - - 25 ns
BUS </>2 CHARACTER ISTICS
Pulse W,dth - Low Logic State (Figure 4) tpWLB ns
(fo : 1.0 MHz! 430 - -
(fo = 1.5 MHz) 280 - -
(fo: 2.0 MHz! 210 - -
Pulse WIdth - High Logic State tpWHB ns
(fo : 1.0 MHz) 450 - -
(fo : 1.5 MHz) 295 - -
(fo : 2.0 MHz) 235 - -
Delay Times - (Referenced to MPU <pI) (Figure 4)
Output Low to High LogIc State tpLHBMl ns
(to: 1.0 MHz! 480 - -
(fo = 1.5 MHz) 320 - -
(fo : 2.0 MHz) 240 - -
Output High to Low Logic State tpHLBMl
(CL : 300 pF) - - 25
(CL: 100 pF) - - 20
Delay Times (Referenced to MPU <l>2! (Figure 4)
Output Low to High Logic State tPLHBM2 -30 - +25 ns
Output High to Low Logic State tPHLBM2 0 - +40 ns
Transition Times (Figure 4)
Output Low to High Logic State tTLHB - - 20 ns
Output High to Low Logic State tTHLB - - 20 ns

4-614
MC687S- MC687SA

SWITCHING CHARACTERISTICS (continued)

Characterlltlc Symbol Min Typ Max Unit
MEMORY CLOCK CHARACTERISTICS
Oelay Times (Referenced to MPU </>21 (Figure 41
Output Low to High Logic State tPLHCM -50 - +25 n.
Output High to Low Logic State tPHLCM 0 - +40 n.
Delay Tome. (Referenced to 2 x fol (Figure 41
Output Low to High LogIc State tpLHC2X - - 65 n.
Output HIgh to Low Logic State tPHLC2X - - 85 n.
Transition Times (Figure 4)
Output Low to High State tTLHC - - 25 n.
Output High to Low State tTHLC - - 25 n.
2 x fo CHARACTERISTICS
Delay Times (Referenced to 4 x fol (Figure 41
Output Low to High Logic State tpLH2X - - 50 ns
Output High to Low Logic State tPHL2X - - 65 n.
Delay TIme (Referenc.d to MPU </>11 (F,gure 41
Output High to Low Logic State tpHL2XMl n.
(fo = 1.0 MHz) 365 - -
(fo = 1.5 MHz) 220 - -
Transition Times (Figure 4)
Output Low to High Logic State tTLH2X - - 25 ns
Output High to Low Logic State tTHL2X - - 25 n.

•
4 x fo CHARACTERISTICS
Delay Times (Referenced to Ext. Inl (Figure 4)
Output Low to High Logic State tPLH4X - - 50 ns
Output High to Low Logic State tpHL4X - - 30 n.
Transition Time (Figure 41
Output Low to High Logic State tTLH4X - - 25 n.
Output High to Low Logic State tTHL4X - - 25 ns
MEMORY READY CHARACTERISTICS
Set·Up Times (Figure 51
Low Input Logic State tSMRL 55 - - ns
High Input Logic State tSMRH 75 - - n.
Hold TIme (Figure 5)
Low Input Logic State tHMRL 10 - - ns
DMAIREFRESH REQUEST CHARACTERISTICS
Set·Up Times (FIgure 6)
Low Input Logic State tSDRL 65 - - n.
High Input Logic Stata tSDRH 75 - - ns
Hold Time (Figure 6)
Low Input Logic State tHDRL 10 - - n.
DMAIREFRESH GRANT CHARACTERISTICS
Delay Time Referenced to Memory Clock (Figure 6)
Output Low to High LogIc State tPLHG -15 - +25 ns
Output High to Low Logic State tPHLG -25 - +15 ns
Transition Times (Figure 61
Output Low to High Logic State tTLHG - - 25 ns
Output High to Low Logic State tTHLG - - 25 ns
RESET CHARACTERISTICS
Delay Time Referenced to Power-On Resat (Figure 71
Output Low to High Logic State tPLHR - - 1000 ns
Output High to Low Logic State tpHLR - - 260 ns
Transition Times IFigure 7)
Output Low to High Logic State tTLHR - - 100 ns
OutPUt High to Low Logic State tTHLR - - 60 ns

DESCRIPTION OF PIN FUNCTIONS

• 4 x to - A fNt runnlnll OIClllltOr .t tour limes the MPU clock,.. lillful tor I .ysUm Iync stgn"
• 2 x to
• DMAfflEF "EQ
- A 'ree running oleillat« It two II,"" the MPU clock rate
- An aynctlronous Input uHd to fmB the MPU clock. In the ~1 high. ,2 low sU:tt for
• SUS,2
• MEMORY CLOCK - An output nomlnellv In phlle Wllh MPU
• POWER.()N RESET
,2
- An output nomllWlllv In phueWlth MPU ,2 hiving MC8T26A Iype d'l"ec::!lP8blllty
wt'llc::h ft'ee ru,. dUring e refr .. h requR5t c::yele
A Sl;:hmltl tngger Input wtltc::11 controls Rasat A Clpac::ttor to ground IS reqll1red to SRI the
dvn."uc memory r,fresh or cycle stal DMA (Dlrtct Memory AccesJ) d"lred time constInt IntlrlWll 60 k ...!Stor 10 Vcc SIR Gen...11 DlISllln Suggestions lor
• REF GRANT - A synchronous output used to Ivnchronln the refrelh Of DMA optI'ltJon to till' MPU Mlnull R.et Operation
• MEMORY READY - An MvncI'Ironoul Input used to ' ...u the MPUcloc:kSlntht.'low.,2h!ghrtatlforslow • RESET - AnoutputtotheMPU ..dllOdevlC8S
mernoryln1erftce • X1,X2 - PrOVISIon to IItKh • IIrlil retOI'IInt c::ryllil or AC network
• ,,",PU,1 - ClPlbI.ofdrlvlngth"1.nd'2InputsontwoMce&oo. • EXT IN - Allows driVing by . . IIXterlWll TTL II"''' to svnchronlR me MPU to iln e"terlWllsystem
MPU.2

4·615
 MC6875. MC6875A

FIGURE 1 - BLOCK DIAGRAM

4 x fo 2 x fo

Xl

X2'

In

e Q~~r-------'-~

(6) BUS "'2

Memory Ready 0--'----+------10s 0f-f-r---f---L.J1

•
MPU 1;2
(13)

;;D:;:M~A;;-/"R~e-;frCCe--cShC"( 0' ~O)+__-+____---jD Q (II)

Req u est S f----------1r-L J OMA/Refresh
Grant
Vee

50 k Reset (14)
'Output 0-+------------' Pin 16 ~ +5,0 Volts
Pin 8 - Gnd

FIGURE 2 - TYPICAL HYSTERESIS CHARACTERISTIC FIGURE 3 - TIMING DIAGRAM FOR

OF RESET FUNCTION MPU 1>1 AND 1>2
50
r-- Vee 0 50 V f------------- to -------------1
TA 0 25 0 e
~ 40
o
~
w 0
'"
«
>:;
o
>
0
~
!;
o
6 0
>

0
10 20 3D 40 50 Vov = 1 0 V ::: Clock Overlap
V" INPUT VOLTAGE (VOLTS)' POWER·ON RESET PIN measurement pomt

4-616
MC6875. MC6875A

FIGURE 4 - TIMING DIAGRAM FOR NON·STRETCHED OPERATION

(Memory Ready and DMA/Refresh Request held high continuously)
Ext. In Input Voltage: 0 V to 3.0 V, f = 8.0 MHz, Duty Cycle = 50%, tTLHEX =tTHLEX = 5.0 ns

DMA/Aefresh Grant (Low)

4-617
 MC687S. MC687SA

FIGURE 5 - TIMING DIAGRAM FOR MEMORY READY STRETCH OPERATION

(Minimum Stretch Shown)
Input Voltage: 3.0 to 0 V, tTHLMR = tTLHMR = 5.0 ns

2.0 V

Memorv Ready

0.8 V

DMA/Refresh Request
~ Irrelevant

DMA/Refresh Grant
(Low)

4-618
MC6875- MC6875A

FIGURE 6 - TIMING DIAGRAM FOR DMA/REFRESH REQUEST STRETCH OPERATION

(Minimum Stretch Shown)
Input Voltage: 3.0 to 0 V. tTHLDR - tTLHDR = 5.0 ns

Memory Readv
~ Irrolov8nt

tTLHDR

1.5 Vee
•
-+----tPwDMA = fO -2-

2.0 V 20 V
OMAlFIefr.sh Gr.nt

o.s V OSV

4·619
 MC6875- MC6875A

FIGURE 7 - POWER ON RESET

Input Voltage: 0 to 5,0 V, f = 100 kHz - Pulse Width z 1,0 ).IS, tTLH =tTHL = 25 ns

5.0 V ----"--+--tr----------------,

Power-On Reset

OV _ _ _ _--I

Reset

0,8 V 0.8 V

• FIGURE 8 - LOAD CIRCUITS

+50 V

RLL=18k
For 8us ¢2

+5

RLL
68
av

RLH RLH
20 k 240
An dIodes are 1 N916 All diodes are 1 N916
or equIvalent or equ Iva lent

MPU 1>1 CL = 35 pF, RD = 20 n

MPU 1>2 CL = 70 pF, RD = 15 n

For 4 x fo. 2 x fa, Memory Clock and DMA/Refresh Grant

For Reset Output

+50 Volts

RLL = 240 RLL=1,2k

foutput
Pm i'4--+---.----+4.--+
CL'

100pF I RLH
4.7 k
All diodes are 1 N916
Dr equIvalent
All dIodes are 1 N916
or equ Ivalent

.. Load capacitance includes fixture and probe capacitance

4-620
MC6875- MC6875A

APPLICATIONS INFORMATION
FIGURE 9 - TYPICAL RC FREQUENCY versus VOLTAGE GENERAL
+11.0 The MC6875 Clock Generator/Driver should be located

.",
...- on the same board and within two inches of the MC6800
MPU, Series damping resistors of 10-30 ohms may be
utilized between the MC6875 and the MC6800 on the .pI
V and .p2 clocks to suppress overshoot and reflections.
The VCC pin (pin 16) of the MC6875 should be
/ bypassed to the ground pin (pin 8) at the package with a
/" fo ~ 1 OMH'.:- - 0.1 IlF capacitor. 8ecause of the high peak currents
/' @VCC=50V'
TA~25'C - - associated with driving high Iy capacitive loads. an ade,
./" 1 1 quately large ground strip to pin 8 should be used on the
V MC6875. Grounds should be carefully routed to minimize
coupling of noise to the sensitive oscillator inputs. Unnec-
-2.0 essary grounds or ground planes should be avoided near
45 50 5.5 60 65 7.0
Vcc. SUPPLY VOLTAGE (VOLTS) pin 2 or the frequency determining components. These
components should be located as near as possible to the
respective pins of the MC6875. Stray capacitance near
FIGURE 10 - TYPICAL RC FREQUENCY pin 2 or the crystal. can affect the frequency. The can of

I
versus TEMPERATURE the crystal should not be grounded. The ground Side
of the crysta1 or the C of the R-C oscillator should be con-
+1.0 /
1/ nected as directly as possible to pin 8.
~ +D.8 ./ Unused Inputs should be connected to VCC or ground.
w / Memory Ready. DMA/Refresh Request and Power·On
'"~ +06 ./ Reset should be connected to VCC when not used.
'" i'/ The External Input should be connected to ground
'"
> ./
ffi +0.4 / when not used.
g ./ fo~1.0MHz._
~ +0.2 - OSCILLATOR
/ ~:~C2;~COV- -
/ A tank circuit tuned to the desired crystal frequency
:t V connected between terminals X 1 and X2 as shown in

--
-02 V Figure 12. is recommended to prevent the oscillator from
I starting at other than the desired frequency. The 1kn
-10 w ~ ~ ~ ~ ~ ro ~ 00
resistor reduces the Q sufficiently to maintain stable
TA. TEMPERATURE (1:)
crystal control. Crystal manufacturers may recommend a
capacitance (CLl to be used in series with the crystal for
optimum performance at senes resonance.
FIGURE 11 - TYPICAL FREQUENCY.ersus See Figures 9 and 10 for tYPical oscillator temperature
RESISTANCE FOR C VARIABLE
200
and VCC supply dependence for R-C operation.
........ r-.,. I I I I I I

"'""" " "'-

FIGURE 12 - QSCILLATOR-CRYSTAL OPERATION
NOTE RC OperatIOn not -
recommended above
(1)
4Xf.=20MH, ,_ r-----~--~~----~X,
100

80 ......
~
....... ...... ...... MC6875
~

60 "- ........ ........ "- 1

w Vcri=5 0V'-
........ ........ ........

,,,, '" ""\.

"'\.
(2)
'"Z<[ TA=25 0 C -
............ .......
t: _lL •
-I
~
'"
f<[
'"
",'

20
."" ...... ~
~

,,"
"\ r\
~
'\ [\
iF
(Trim) L__ -
CL

_
(3)
Ext In

4 X fo'" Crystal frequency

~"\
=XTAL

'"
\ \
"I\.
I - 4 X fO=1 ' Ar::-
2"~-TCT

10
I'
i
R 5 k 4k i 3k 2k 1k 0 5k
1
• Requ Ired by some
2.5 "H " LT " 22 "H
75 pF'" CT'" 200 pF
1 7 8 9 10 Crystal manufacturers RT = lkO
4 X fo. FREQUENCY (MHz)

4-621
 MC6875- MC6875A

TABLE 1 - OSCtLLATOR COMPONENTS

CTS KNIGHTS McCOY ELECT. CO. TYCO CRYSTAL PRODUCTS
TANK CIRCUIT APPROXIMATE 400 REIMANN AVE. WATTS & CHESTNUTS STS. 3940 W. MONTECITO
PARAMETERS CRYSTAL PARAMETERS SANDWICH,IL MT. HOLLY SPRING. PA PHOENIX.AZ
60548 17065 85019
IT CT RS Co Cl fo (8151 786-8411 (7171 486-3411 (6021 272·7945
#H pF Ohms pF mpF MHz
10 150 15·75 3-6 12 4.0 MP-04A 150-3260
113-31
.. 390pF
4.7 82 8-45 4·7 23 8.0 MP.()80 150-3270
113-32
.. 47 pF

I nductors may be obtained from COIIf;raft, Cary, I L 60013 (312) 639·2361

FIGURE 13
a solid Vo L output level until VCC has reached 3.5 to
RC OPERATION 4.0 V. During this time transients may appear on the
(II clock outputs as the oscillator begins to start. This
XI happens at approximately VCC = 3 V. At some Vec level
EXTERNAL INPUT
A above that, where Reset Output goes low, all the clock
(11
121 0-- XI outputs will begin functioning normally. This phenom·
X2 Open enon of the start·up sequence should not cause any
problems except possibly in systems with battery back·up
MC6875

I
(21
C memory. The transients on the clock lines during the
X2
(31 time the Reset Output is high impedance could initiate
Ext I" MC6876 the system in some unknown mode and possibly write

I
into the backup memory system. Therefore in battery
(31
Ext In backup systems, more elaborate reset circuitry will
be required.
51
External Pulse
Please note that the Power·On Reset input pin of the
Generator MC6875 is not suitable for use with a manual MPU reset
switch if the DMA/Ref Req or Memory Ready inputs are
going to be used. The power on reset circuitry is used to
To precisely time a crystal to desired frequency, a
initialize the internal control logic and whenever the
variable trimmer capacitor in the range of 7 to 40 pF
input is switched low, the MC6875 is irresponsive to
would typically be used. Note it is not a recommended
the DMA/Ref Req or Memory Ready inputs. This may
practice to tune the crystal with a parallel load capaci·
result in the loss of dynamic memory and/or possibly
tance.
a byte of slow static memory. The circuit of Figure 14
The table above shows typical values for CT and LT.
is recommended for applications which do not utilize the
typical crystal characteristics. and manufacturers' part
DMA/Ref Req or Memory Ready inputs. The circuit of
numbers for 4.0 and 8.0 megahertz operation.
Figure 15 is recommended for those appl ications that do.
The MC6875 will function as an R-C oscillator when
FIGURE 14 - MANUAL RESET FOR APPLICATIONS NOT USING
connected as shown in Figure 13. The desired output OMA/REFRESH REQUEST OR MEMORY REAOY INPUTS
frequency (M¢1) is approximately:
Vcc
Formula 320 C in picofarads
4 x fa '" C (R+ .27) + 23 R in K ohms
(See Figure 11) 4 x fo in Megahertz
cl 12 14 40

y\
It would be desirable to select a capacitor greater than
15 pF to minimize the effects of stray capacitance. It is
also desirable to keep the resistor in the 1 to 5 k n
range. There is a nominal 270 n resistor internally at
X, which is In series with the external R. By keeping
-= Manual Reset Switch

the external R as large as possible, the effects due to FIGURE 15 - MANUAL RESET FOR SYSTEMS USING
process variations of the internal resistor on the frequency DYNAMIC RAM OR SLOW STATIC RAM IN CONJUNCTION
will be reduced. There will, however, still be some WITH MEMORY REAOY OR DMA/REFRESH REQUEST INPUTS
variation in frequency in a production lot both from VCC
the resistance variations, external and internal, and 1/474LS08
process variations of the input switching thresholds. 47 k
Therefore, in a production system, it is recommended
a potentiometer be placed in series with a fixed R 14
between X1 and X2.
POWERoON RESET '\:' Manual Asset
As the power to the MC6875 comes up, the Reset J:..Switch
Output will be in a high impedance state and will not give

4-622
MC6875- MC6875A

OUTLINE DIMENSIONS

NOTE:
Operation of the MC6875AL over the full military tem-
perature range (to maximum T A) will result in excessive
operating Junction temperature_
MILLIMETERS INCHES
The use of a clip on 16 pin heat sink similar to AAVID DIM MIN MAX MIN MAX

•
Engineering, Inc_, Model 5007 (ReCA = 180 C/W) IS A 1905 19.81 0.750 I 0780
recommended above T A "" 950 C_ a 6.22 698 0.245 0 275

oC 406
0.38
5.08
0.51
I 0160 100.020
.200
F 1.40 165 0065
G 2.54 asc asc
Contact AAVID Englneenng, Inc. H 0.51 1 14 0.020 0.045
J 0.20 0 30 0.008 0.012
30 Cook Court K 3.18 4.06 0125 0.160
Lacoma, New Hampshire 03246 L 737 787 0290 0310
M 150 150
Tel. (603) 524-4443 N 0.51 1.02 0.020 0.040
NOTES
1 LEAOSWITHINO.13mm(0005)RAOIUS
OF TRUE POSITION AT SEATING PLANE
AT MAXIMUM MATERIAL CONOITION
PKG INOEX NOTCH IN LEAD
NOTCH IN CERAMIC OR INK DOT
DIM "L" TO CENTER OF LEADS
WHEN FORMED PARALLEL

CASE 620-02
R8JA = 100oC/W (Tvp)

ROJClp •• k) = 150 C/W

THERMAL INFORMATION
The maximum power consumption an Integrated CirCUit the sum of the products of the supply voltages and supply
can tolerate at a given operating ambient temperature, can currents at the worst case operating condition
be found from the equation TJ(max) = MaXimum Operating Junction Temperature
TJ(max) -TA as listed In the MaXimum Ratings Section
PD(T A) = ROJA T A = MaXimum DeSIred Operating Ambient
Temperature
Where PD(T A) = Power DISSipation allowable at a given
ROJA = Thermal Resistance Junction to Ambient
operating ambient temperature. ThiS must be greater than
R8JC = Thermal Resistance Junction to Case

4·623
 ® MOTOROLA
MC6880A
MC8T26A
This device may be ordered under
either of the above type numbers.

QUAD THREE-STATE BUS TRANSCEIVER

QUAD THREE-STATE
This quad three-state bus transceiver features both excellent MOS BUS TRANSCEIVER
or MPU compatibility, due to ItS high Impedance PNP transistor
Input, and high-speed operation made possible by the use of Schottky
MONOLITHIC SCHOTTKY
diode clamping. Both the -48 mA driver and -20 mA receiver out-
puts are short-circuit protected and employ three-5tate enabling inputs.
INTEGRATED CIRCUITS
The device IS useful as a bus extender In systems emploYing the
M6800 family or other comparable MPU devices. The maximum
Input current of 200 JJ.A at any of the device Input pinS assures
proper operation despite the limited drive capability of the MPU
chip The Inputs are also protected with Schottky·barner diode
clamps to suppress excessive undershoot voltages.
The MC8T26A IS identical to the N E8T26A and it opel ates from
a single +5 V supply.

• High Impedance Inputs L SUFFIX

• Single Power Supply CERAMIC PACKAGE

I
CASE 620
• High Speed Schottky Technology
• Three·State Drivers and Receivers
• Compatible with M6800 Family Microprocessor PSUFFIX
PLASTIC PACKAGE
CASE 648

MICROPROCESSOR BUS EXTENDER APPLICATION PIN CONNECTIONS - Mq6BBOA

(Clock) MCBT26A
GNO +5 V 1J1 rp2

Rece.Ver
Enable
Input
1 Vee
Receiver Driver
Output Enable
1 Input

Bus 1 14 Aecelver
Output
Driver 4
Input Bus4
1
Receiver Driver
Output Input
2 4
Receiver
Output
3
Dnver
Input 7 Bus3
2
Driver
Gnd Input
3

ORDERING INFORMATION
Temperatur.
Device Alternate Range Package

MC6880AL MC8T26AL 0 to +15°C Ceramic DIP

MC6880AP MC8T26AP 0 to + 75 C PlastiC DIP

4-624
MC6880AI MC8T26A

MAXIMUM RATINGS ITA = 25"C unlessotherwloe noted.)

Rating Symbol Value Unit
Power Supply Voltage VCC 8.0 Vdc
Input Voltage VI 5.5 Vdc
Junction Temperature TJ °c
Ceramic Package 175
PlastiC Package 150
Operating Ambient Temperature Range TA oto +75 °c
Storage Temperature Range T stg -65 to+150 uc

ELECTRICAL CHARACTERISTICS 14.75 V .. VCC" 5.25 V and OOC .. TA .. 750 C unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Input Current - Low Logic State
I Aecelver Enable Input, VILIAEI = 04 VI IILIREI - - -200 ~A
I Dnver Enable Input, VILIDEI = 04 VI IILlDE) - - -200
IDnver Input, VILIDI = 04 VI IILIDI - - -200
IBus I Aecelver! Input, VILIBI = 04 VI IILlBI - - -200
Input Disabled Current - Low Logic State
IILIDI DIS

•
IDriver Input. VILIDI = 0.4 V) - - -25 itA
Input Current-High Logic State
I Receiver Enable Input, VIHIREI = 525 VI IIHIREI - - 25 ~A
IDriver Enable Input, VI HIDEI = 525 VI IIHIDEI - - 25
IDnver Input, VI HIDI = 525 VI IIHIDI - - 25
IRecelver Input, VIHIBI = 5.25 VI IIHIBI - - 100
Input Voltage - Low Logic State
I Receiver Enable Input) VILIREI - - 085 V
I Driver Enable Input VILIDEI - - 085
(Driver Inputl VILIDI - - 085
(Receiver Input) VILIBI - - 085

Input Voltage - High Logic State

(Receiver Enable Input) VIHlREI 20 - - V
(Driver Enable Input) VIHIDEI 20 - -
(Dnver Input) VIHIDI 20 - -
(Receiver Input) VIHIBI 2.0 - -
Output Voltage - Low Logic State
IBus Driver) Output. 10LIBI = 48 mAl VOLIBI - - 05 V
IRecelver Output. 10LIAI = 20 mAl VOLIRI - - 05
Output Voltage - High LogIc State
IBus IDriverl Output, 10HIB) = -10 mAl VOHIBI 2.4 31 - V
I Receiver Output, 10HIAI = -2.0 mAl VOHIRI 2.4 31 -
IAecolver Output, 10HIA) = -100/ itA. VCC = 5.0 VI 3,5 - -
Output Disabled Leakage Current - High Logic State
IBus Driver) Output. VOHIBI = 2,4 V)
IRecelver Output. VOHIR) = 2,4 V)
10HLIBI -- -
-
100
100
IlA
10HLIRI
Output Disabled Leakage Current - Low Logic State
IBus Output. VOLIBI = 0.5 V) 10LLIBI - - -100 IlA
IRecelver Output. VOLIR) = 0.5 V) 10LLIA) - - -100
Input Clamp Voltage
IDriver Enable Input IIDIDE) = -12 mAl VICIDEI - - -10 V
IAeceiver Enable Input IICIAE) = +12 mAl VICIREI - - -10
IDnver Input IICIDI = -12 mAl VICIDI - - -10
Output Short· CirCUit Current, VCC = 525 V C 1/
I Bus IDnverl Output) 10SIBI -50 - -150 mA
IAeceiver Output) 10SIRI -30 - -75
Power Supply Current ICC - - 87 mA
IVCC = 5.25 VI
11) Only one output may be short-cirCUIled at. time.

4·625
 MC6880A/MCST26A

SWITCHING CHARACTERISTICS (Unless otherwIse noted, specIfIcations apply at TA • 250 e and Vee = 5.0 V)
C",acteristic Symbol Figura Min Max Unit
PropagatIon Delay TIme from Receiver (Bus) Input to tPLH(R) 1 - 14 ns
High LogIc State Receiver Output
Propagation Delay Time from Receiver (Bus) I "put to tPHL(R) 1 - 14 ns
Low LOQ1c State Receiver Output
Propagation Delay Time from Driver I"put to tPLH(o) 2 - 14 ns
High LogIc State orrver (Bus) Output
Propagation Delay Time from Driver I nput to tPHL(D) 2 - 14 ns
Low LogIc State Drrver (Bus) Output
PropagatIon Delay Time from Receiver Enable I nput to tPLZ(RE) 3 - 15 ns
HIgh Impedance (Open) LogIc State ReceIver Output
Propagation Delay Time from Receiver Enable Input to tPZL(RE) 3 - 20 ns
Low Logic level Receiver Output
Propagation Delay Tune from Dnver Enable Input to tPLZ(oE) 4 - 20 ns
HIgh Impedance LogIc State Drrver (Bus) Output
Propagation Delay Time from DrIVer Enable Input to tpZL(DE) 4 - 25 ns
Low LogIc State Drrver (Bus) Output

I FIGURE 1 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY FROM

BUS (RECEIVER) INPUT TO RECEIVER OUTPUT, tPLH(R) AND tPHL(R)

tTLH .; 5.0 ns tTHL < 5.0 ns

Input
o V _-:'=31
Input Pulse Frequency'" 10 MHz
tpHLfR) Duty Cycle:::: 50%
VOH---_
Output
VOL----------·~-------J

2.6 V
To Scope ~r To Scope
(Input) "E,;';ijj; (Input)
Input

92
Receiver lN916
Output or Equiv.

Orlver
Input
Pulse 51 1.3 k 30pF
E?river
Generator
Enable
Input

4-626
MC6880AI MC8T26A

FIGURE 2 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
DRIVER INPUT TO BUS (DRIVER) OUTPUT, tPLH(D) AND tpHLlD)

tTHL';;; 5.0"s

2.6V-----
Input

o V ---'-''''':'''::'1 Input Pulse FreQuency == 10 MHz

tpHL(O) Duty Cycle = 50%
VOH------
Output
VOL _ _ _ _ _ _ \...... _ _ _ _ _ _- J

26V 26V
To Scope Dnver To Scope
(Input) Enable (Output)
Input

Driver 30
(Bus) lN916
Driver
Input Output or EqU1V

Receiver
Output
51 260 300 pF
~
Enable
Input

FIGURE 3 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
RECEIVER ENABLE INPUT TO RECEIVER OUTPUT, tpLZ(RE) AND tpZL(RE)

tTLH '" 5.0 ns tTHL~5.0n5

r-
2.6 V ---+;I.:-:=C----=~
Input
OV---Jrl

tPLZ(AE) tpZL(AE)
"'3.5 V ----+--;;;.__-------,. Input Pulse Frequency = 50 MHz
Duty Cycle == 50%
Output 1.5 V
VOL----~

To Scope 2.6 V 50V

To Scope
(Input) (Output)

2.4 k 240
Receiver
Output

Pulse 51
Generator
lN916
5.0 k 30 pF or EqU1V

4·627
 MC6880A/MC8T26A

FIGURE 4 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIMES FROM
DRIVER ENABLE INPUT TO DRIVER (BUS) OUTPUT, tpLZ(OE) AND tpZL(DE)

tTHL ~ 5.0 ns

26 V ---+-;I.;;=------.\-
Input
oii _ _ _.71 Input Pulse Frequency = 5.0 MHz
Duty Cvcle = 50%
tpZL(DE)
~3.5V----

Output
VOL------'-------~

+2.6 V

I
5.0 V
To Scope
To Scope Driver Enable (Output)
Input
----.----+---(>----1
(InpU'r':...)

24k 70
Driver
Input

Driver (Bus)
Pulse I'L 51 Recetver Output
Generator Output
1N916
50k 300pF or Equlv
~
Eii86'ie
Input

FIGURE 5 - BIDIRECTIONAL BUS APPLICATIONS

Receiver
Outputs Receiver
Outputs

Oriver Driver
Inputs Inputs

To Other
Drivers/Receivers

Driver Receiver
Enable Enable

4·628
MC6880AI MC8T26A

L SUFFIX P SUFFIX
Q

[C ~ :p"":~::::""
CERAMIC PACKAGE PLASTIC PACKAGE
CASE 648-06
: : : : : : :
A8JA - 100o C/W (Tvp)

~F~ I
OPTIONAL LEAD
CON FIG. (1,8,9,& 16)

~JBl
JH~ ~ G
-iL MJl f.- JLD SEATING
PLANE
K
NOTES:
1 LEADS WITHIN 0.13 mm (0.005) RADIUS
OF TRUE POSITION AT SEATING PLANE
AT MAXIMUM MATERIAL CONDITION
PKG. INDEX. NDTCH IN LEAD
NOTCH IN CERAMIC OR INK DOT
DIM "L" TO CENTER OF LEADS
NOTES.
1. LEADS WITHIN 0.13 mm
(0,005) RADIUS OF TRUE
POSITION AT SEATING
PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION "L" TO
3. DIMENSION "8" DOES NOT
INCLUDE MOLD FLASH.
4. "F" DIMENSION IS FOR FULL
LEADS. "HALF" LEADS ARE
OPTIONAL AT LEAD POSITIONS
1,8,9, and 16).
II
WHEN FORMED PARALLEL CENTER OF LEADS 5. ROUNDED CORNERS OPTIONAL.
WHEN FORMED
PARALLEL.
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 19.06 19.81
B 6.22 6.98 ~
C 4.06 5.08 ..w.!-
D 0.38 0.51 ~
F 1.40 1.65 ~
G 2.54 BSC ~
H 0.51 1.14 ~
J 0.20 0.30 : 0.012
K 3.18 4.06 0.160
L 131 1.81 0.310
M
N
-
0.51
150
1.02
-
0.020
1
10
0.040

THERMAL INFORMATION

The maximum power consumption an Integrated CirCUit the sum of the products of the supplv voltages and supply
can tolerate at a given operating ambient temperature, can currents at the worst case operating condition.
be found from the equation
TJ(max) = MaXimum Operating Junction Temperature
TJ(max) -TA
as listed In the MaXimum Ratings Section
PD(T A) = ROJA(Typ)
T A = MaXimum DeSired Operating Ambient
Where. PD(T A) = Power DISSipation allowable at a given Temper ature
RIIJA(Typ) = TYPical Thermal ReSistance Junction to
operating ambient temperature. ThiS must be greater than
Ambient
 @ MOTOROLA SN74LS783
Me6883

Advance Information
SYNCHRONOUS
SYNCHRONOUS ADDRESS MULTIPLEXER ADDRESS
The SN74LS783/MC6883 brings together the MC6809E
MUL TIPLEXER
(MPU). the MC6847 (Color Video Display Generator) and dy-
namic RAM to form a highly effective, compact and cost ef-
LOW POWER SCHOTTKY
fective computer and display system.
• MC6809E, MC6800, MC6801E, MC68000 and MC6847 (VDG)
Compatible
• Transparent MPUIVDG/Refresh
• RAM size - 4K, 8K, 16K, 32K or 64K Bytes (Dynamic or
Static)
• Addressing Range - 96K Bytes N SUFFIX
• Single Crystal Provides All Timing PLASTIC PACKAGE
CASE 711
• Register Programmable:
VDG Addressing Modes

~,u,'"
VDG Offset (0 to 64K)

II RAM Size
Page Switch
MPU Rate (Crystal + 16 or + 8)
MPU Rate (Address Dependent or Independent)
• System "Device Selects" Decoded 'On Chip'
1 CERAMIC PACKAGE
CASE 734
• Timing is Optimized for Standard Dynamic RAMs
• + 5.0 V Only Operation
• Easy Synchronization of Multiple SAM Systems
PIN ASSIGNMENT
• DMA Mode

1 40
SYSTEM BLOCK DIAGRAM 2 39
3 38
4 37
5 36
TV DIsplay SectIon
IS Optional 6 35 (RAS1)
7 34
8 33
9 32
Address AO-AI5 SN74LS7831
MC6883 10 31
RIWI---_ _ _ SAM
11
~

= 14 MHz
30
E~---; 12 29
To a i"4-----I 13 28
ROMs 14 27
and MC6809E
110 MPU 15 26
16 25
DYNAMIC 17 24
Data RAM 18 23
4K. BK. 16K
32K or 64K 19 22
BYTES
20 21

4-630
SN74LS783-MC6883

MAXIMUM RATINGS (TA = 25'C unless otherwise noted)

Rating Symbol Value Unit
Power Supply Voltage VCC -0.5 to +7.0 Vdc
Input Voltage (Except OSCln) VI -0.5 to 10 Vdc
Input Current (Except OSCln) II -30 to +5.0 rnA
Output Voltage Vo -0.5 to +7.0 Vdc
Operating Ambient Temperature Range TA o to +70 'c
Storage Temperature Range Tsta -S5 to + 150 'c
Input Voltage OSCln VIOSCln -0.5 to VCC Vdc
Input Current OSCln II0sCIn -0.5 to +5.0 rnA

RECOMMENDED OPERATING CONDITIONS

Rating Symbol Value Unit
Power Supply Voltage VCC 4.75 to 5.25 Vdc
Operating Ambient Temperature Range TA o to +70 'c

DC CHARACTERISTICS (Unless otherwise noted specifications apply over recommended power supply and

•
temperature ranges)
Characteristic Symbol Min Typ Max Units
Input Voltage - High logic State VIH 2.0 - - V
Input Voltage - low logic State Vil - - 0.8 V
Input Clamp Voltage VIK - - -1.5 V
(VCC = Min, lin = -18 rnA) All Inputs Except OSCln
Input Current - High logic State at Max Input Voltage II ",A
(VCC = Max, Vin = 5.25 V) VClk Input - - 200
(VCC = Max, Vin = 5.25 V) DAO Input - - 100
(VCC = Max, Vin = 5.25 V) OSCOut Input - - 250
(VCC = Max, Vin = 7.0 V) All Other Inputs Except OSCln - - 100
Input Current High logic State IIH ",A
(VCC = Max, Vin = 2.7 V) All Inputs Except VClk, OSCln* - - 20
Input Current - low logic State III rnA
(VCC = Max, Vin = 0.4 V) DAO Input - - -1.2
(VCC = Max, Vin = 0.4 V) VClk Input - -30 -SO
(VCC = Max, Vin = 0.4 V, OSCln = Gnd) OSCOut Input - - -8
(VCC = Max, Vin = 0.4 V) All Other Inputs Except OSCln - - -.4
Output Voltage - High logic Sta~ _ _ V
(VCC = Min, 10H = -1.0 rnA) RASO, RAS1, CAS, WE VOH(C) 3.0 - -
(VCC = Min, 10H = -0.2 rnA) E, Q VOH(E) VCC - 0.75 - -
(VCC = Min,IOH = -0.2 rnA) All Other Outputs VOH 2.7 - -
Output Voltage - low logic State_ V
(VCC = Min, 10l = 8.0 rnA) RASO, RAS1, CAS, WE VOl(C) - - 0.5
(VCC = Min, 10l = 4.0 rnA) E, Q Outputs VOllE) - - 0.5
(VCC = Min, 10l = 0.8 mAl VClk Output VOl(V) - - O.S
(VCC = Min, 10l = 4.0 rnA) All Other Outputs VOL - - 0.5
Power Supply Current ICC - 180 230 rnA
Output Short-Circuit Current lOS 30 - 225 rnA
*Including OSCOut (when OSCln is grounded).

4-631
 SN74LS783·MC6883

AC CHARACTERISTICS (4 75 V",VCC"'5 25 V and 0",TA"'70°C, unless otherwise noted).

Characteristic Symbol Min Typ Max Units
Propagation Delay Times ns
(See Circuit in Figure 9) Oscillator-In "- to Oscillator-Oulf Id(Ol-OH) - 3.0 -
Oscillator-In I to Oscillator-Out't- td(OH-Ol) - 20 -
(Cl = 195 pF) AO thru A15 to ZO, ZI, Z2 thru Z7 td(A-Z) - 28 -
(Cl = 30 pF) AO thru A15, R/W to SO, SI, S3 td(A-S) - 18 -
(Cl = 95 pF) Oscillator-Out "- to RASO I td(Ol-ROH) - 20 -
(Cl = 95 pF) Oscillator-Out "- to RASO "- td(Ol-ROl) - 18 -
(Cl = 95 pF) Oscillator-Out "-to RASI I td(Ol-R1H) - 22 -
(Cl = 95 pF) Oscillator-Out "- to RASI "- td(Ol-Rl l) - 20 -
(Cl = 195 pF) Oscillator-Out "- to CAS I td (Ol-CH) - 20 -
(Cl = 195 pF) Oscillator-Out "- to CAS "- td(Ol-Cl) - 20 -
(Cl = 195 pF) Oscillator-Out "- to WE I td(Ol-WH) - 22 -
(Cl = 195 pF) Oscillator-Out "- to WE "- td(Ol-Wl) - 40 -
(Cl = 100 pF) Oscillator-Out "- to E I td(Ol-EH) - 55 -
(Cl = 100 pF) Oscillator-Out "- to E "- td(Ol-El) - 25 -
(Cl = 100 pF) Oscillator-Out 'L to Q I td(Ol-QH) - 55 -
(Cl = 100 pF) Oscillator-Out "- to Q "- - 25 -

I
td(Ol-Ql)
(Cl = 30 pF) Oscillator-Out I to VClk I td(OH-VH) - 50 -
(CL = 30 pF) Oscillator-Out I to VClk "- td(OH-Vl) - 65 -
(Cl = 195 pF) Oscillator-Out "- to Row Address td(OL-AR) - 36 -
(Cl = 195 pF) Oscillator-Out "- to Column Address td(Ol-AC) - 33 -
(Cl = 15 pF) Oscillator-Out "- to DAO I Earliest(l) td(Ol-DH) - -15 -
(el = 15 pF) Oscillator-Out . ._ to DAO Ilatest(1) td(Ol-DH) - +15 -
(Cl = 95 pF on RAS, Cl = 195 pFon CAS) CAS "- to RASI td(Cl-RH) - 208 -
Setup Time for AD thru A15, R/W Rate = -16 tsu(A) - 28 - ns
Rate = - 8 - 28
Hold Time for AO thru A15, R/W Rate = -16 Ih(A) - 30 - ns
Rate = - 8 - 30 -
Width of HS low 2 twl(HS) 2.0 5.0 6.0 fLS

Notes' 1 When uSing the SAM with an MC6847, the rising edge of DAO IS confined within the range shown In the timing diagrams (unless the
synchronizing process IS Incomplete) The synchronization process requires a maximum of 32 cycles of OSCOut for completion
2. tWl(HS) wider than 6 0 J.lS may Yield more than 8 sequential refresh addresses

FIGURE 1 - PROPAGATION DELAY TIMES

VERSUS LOAD CAPACITANCE

40

~
30
td IOL·R1LI
~
F
>- 20
~.
;;3 ~ p-f td IOL·CL)
'"z
10 ~
td (OL·ROLI
'"~
<.:>
;t
'"g:
50 100 200 300 400 500
CL, LOAD CAPACITANCE (pFI

4-632
SN74LS783·MC6883

PIN DESCRIPTION TABLE

Name No. Function
Gi VCC 40 Apply + 5 volts ± 5%. SAM draws less than 230 rnA.
~
...
0 Gnd 20 I Return Ground for + 5 volts.
A15 36 Most Significant Bit.
A14 37
A13 38 MPU address bits AO-A15. These 16 signals come directly from the MPU and are used to
A12 39 directly address up to 64K memory locations or to indirectly address up to 96K memory
] All 1 locations. (See pages 17 and 18 for memory maps). Each input is approximately equivalent
c:
0 Ala 2 to one low power Schottky load.
...c:
I,)
A9 3
..., A8 4
..
.. ...i.,
A7
A6
24
23
c: A5 22
ii: A4 21
,.co. ...<I:
~
~ A3 19
.E ::E A2 18
Al 17
AO 16 Least Significant Bit.

•
RfW 15 MPU READ or WRITE. This signal comes directly from the MPU and is used to enable writing
to the SAM control register, dynamic RAM (via WE). and to enable device select #0.
Oscln 5 Apply 14.31818' MHz crystal and 2.5-30 pF trimmer to ground. See page 12.
DAO 8 Display Address DAO. The primary function of this pin is to input the least significant bit of a
16-bit video display address. The more significant 15-bits are outputs from an internal 15-bit
counter which is clocked by DAO. The secondary function of this pin is to indirectly input the
logic level of the VDG "FS" (field synchronization pulse) for vertical video address updating.
0
O~
2 HS 9 Horizontal Synchronization. The primary function of this pin is to detect the falling edge of
> I,)~ VDG "HS" pulse in orderto initiate eight dynamic RAM refresh cycles. Thesecondary function
is to reset up to 4 least significant bits of the internal video address counter.
r- VClk 7 VDG Clock. The primary function of this pin is to output a 3.579545 MHz square wave" to the
VDG "Clk" pin. The secondary function resets the SAM when this VClk pin is pulled to logic
"a" level, acting as an input.
OS C Out 6 Apply 1.5 k!l resistor to 14.31818' MHz crystal and 33 pF capacItor to ground. See page 12.

....Z
.!!
52
51
25
26
Most Significant Bit (Device Select Bits). The binary value of 52, 51, SO selects one of eight
"chunks" of MPU address space (numbers a through 7). Varying in length, these "chunks"
> .. provide efficient memory mapping for ROMs, RAMs, Input/Output devices, and MPU Vectors.
~;;;I (Requires 74LS 138-type demultiplexer).
SO 27 Least Significant Bit.
..
... ..."
E 14 E (Enable Clock) "E" and "0" are 90" out of phase and are both used as MPU clocks for the
~

.. ::Eo!!
c: I,)
0 13
MC6809E. For the MC6800 and MC6801E, only "E" is used. "E" is also used for many MC6800
peripheral chips .
o (Ouadrature Clock).
ii:
,.
~
Z7t 35 Most Significant Bit
S-
,. Z6t 34 First, the least significant address bits from the MPU or "VDG" are presented to ZO-Z5 (4K
0 ::E :1
Z5t
Z4t
33
32
x 1 RAMs) or ZO-Z6 (16K x 1 RAMs) or ZO-Z7 (64K x 1 RAMs). Next, the most significant
address bits from the MPU or "VDG" are presented to ZO -Z5 (4K x 1 RAMs) or ZO -Z6
:~I Z3t 31 (16K x 1 RAMs) or ZO -Z7 (64K x 1 RAMs). Note that for 4K x 1 and 16K x 1 RAMs, Z7 (Pin
<1:, Z2t 30 35) is not needed for address information. Therefore, Pin 35 is used for a second row
Zlt 29 address select which is labeled (RAS1).
ZOt 28 Least Significant Bit.
RASlt 35 Row Address Strobe One. This pulse strobes the least significant 6,7 or 8 address bits into
dynamic RAMs in Bank #1.
::E f RASOt 12 Row Address Strobe Zero. This pulse strobes the least significant 6,7 or 8 address bits into
<l:c
II: 0
dynamic RAMs in Bank #0.
I,) CASt 11 Column Address Strobe. This pulse strobes the most significant 6,7 or 8 address bits into
dynamic RAMs.
WEt 10 Write Enable. When low, this pulse enables the MPU to write into dynamic RAM.

*14.31818 MHz is 4 times 3.579545 MHz television color subcarrier. Other frequencies may be used. (See page 12.)
"When VOG and SAM are not yet synchronized the "square wave" will stretch (see page 10.)
t Due to fast transitions. fernte beads in series With these outputs may be necessary to avoid high frequency (= 60 MHz) resonances.
4

4-633
 • en
z
:i:>!
r
en
TIMING WAVEFORMS for MPU RATE = SLOW
ffi
FIGURE 2 -

I ..... ONE MACHINE CYCLE .1 s:•

~
SYMBOL DEFINITlONS

~ CHANGE fROM H TO L WILL CHANGE FROM H TO l

~ CHANGE FROM l TO H WILL CHANGE FROM L TO H

Osq" ~ ANY CHANGE PERMITTED

OSCOut "iYV"""' ___ -ff

--ll--ldlOl EHI IdlOl-Ell --11-

__ I~·QHI
OHIEI
_ 1_
1_ IdlOL·OLJ
~;l
VOUEI
VOLlE)
VOHIE) -;1

: ''''SlI_~ :stt~l~'
1.lsulAlfH

m
w ,1,0-,1,15. RW
~

~
1 1 1 1 1 '"""'_1
.~~~~~========~==~========================~======+=======~=====t====~~~~~~~~~~~==================i=::i-~
~ ~
Vown
1--ldIOHVU

--1/~~b::td{Ql AC)
VALID vaG ADDRESS (COLUMN)
IdIOL-ARI_I~b. I I Id(oL.Ac)_I;~~
VAllO MPU ADDRESS (ROW
!dIDl-ARI

7' 'V.
l~o{1
'0' 'oc
.1""'dIOLR1HI __11_td!OLR1LI
AASl VOHle) -is
'dlOl ROHI __ It-- -IJ.- 'dIOL-ROli
om vOHle) VOlle) -is
'dleL.RH) vouel 1~ld(Ol CHI ----=::;r,:;::=-'dIOl ell
~ •• ~ • VOliel VOHlel VOLIel _~I
WE I ~:~~~l Wll 'diaL WHI __ I,I;=- . n
OHIC
itTlmlng pOints marked With "4" are defined elsewhere (specifically, 8 cycles of "OSCOut" to the left or right I

Note 1 The penod of "VClk" IS four times that of "OSCOut" unless the synchronization process IS Incomplete Also,
VClk may rise Within td(OH-VH) nanoseconds of TO, ,:,1, T2 or TF

'"
 en
z
~
r
FIGURE 3- TIMING WAVEFORMS for MPU RATE = FAST
en
fS
i" ONE MACHINE CYCLE ~1
•
~
(')

~ CHANGE FROM HTO l

~
~ CHANGE FROM L TO If

~ ANY CHANGE PERMITTED

OSCQul' ' - - ......... -is

Rele'encePolnts,nT,me-+-t

---jl
~ VOLIEI

a, V IhIM)
(,.)
(J1
AOA15 AW-' IH_ ::!
"IL t<lIA_5)

~~~~=======t==~===================t==~~~~~OODt==t=====t=====t=====t===========t==jm~~.:~
VOL VOH

'-.......--JI b-: I 1\,_

_ -v
v" "IH _, 'alQl.QHI
Earhesl
,ldlOL DHI
--'11r-Latest
~- ~
I
•
--I I--ldlOH VHI
VOH I VOLIVI (See Nole 2)
Vll ' I I "IL

_~' ,~:
I I
.--; Id(OH-VLI

VOH ~~VOH IdlOl ARI_ \f-- VOH I }OH tdlOl A~~\H

• DDRESS (ROW) No!e 1 VALID MPU ADDRESS (COLUMNI No!e 1 VALID MPU ADDRESS ROWI VALID MPU ADDRESS (COLUMNI ~

-
lalso Z7 ,j on 64K model I VOL VOL ~~ I vol."l VOL
YO,

__

~"';~
MSo-

m _. • td(CL-RHI
VO",,/
-1t-ldIOL RfHI

-"
-h-"ldIOLROHI
'v
0"101 -+j~"o,,",
VOHIC}
.-I
VOLIC)
IdiOl-Rlll

-JrtdIOLROLI

_:-1r-'''0''''
VOLle)
.
.~$

~
VOLIC) . ..... i-.talOl Wll _ t--tdIOL.WH)
W'E-- --_]VOlICI VOHIC)

*Tlmlng POints marked With "." are defined elsewhere (specifically, 8 cycles of "OSCOut" to the left or the right)
Notes'- In the "fast MPU rate" mode, the time slot otherwise used for a VDG address is used for a second MPU address
2: The period of "VClk" IS four times that of "OSCOut" un!ess the synchrOnization process IS mcomplete
Also, VClk may rise wlthm td(OH-VH) nanoseconds of 'to, '1'1. '1'2. or TF

•
0>
 SN74LS783·MC6883

FIGURE 4 - SAM BLOCK DIAGRAM

52 S1 SO VCC Gnd
n n n n n
$ FFCO • $ FFDF E

l Addr •••
Decode
J Refresh Refresh
Re~est yant RIW

h Refresh Cou nter

06 05 04 03 02 01
c~'--
00 I- Refresh ~ BOSe 7 16

t ,~
Clock

t~
Logic
12

L -_ _- " Control Register _<-

)-lao PI C6 C5 C4 C3 C2 C1 CO
Write Strobe
A15 CIJ---"'I-, 815 -2 Fe
"-' A15

A14 Ct---4--'1 A14 B14 42 F5

A13 CU--"'I---I"'l A13 813 -2 F4

A12 [t---4r-.., A12 B12 .- 2 F3

A11 [t---""+--I~ A11 B11 -2 F2

• A10

A9

A8
[j--"'t---.J

[j----"'t-.,

[j----"'t-.,

A7Ct----+--I~ A7
A10

A9

AS
Address
Multiplexer

(See page 9 for signal

routing and timing)
810

89

B8

B7
-2

-2

-2

-2
u
a;
E
~
0

~
-0
~
« r,;-;:-
TY~ TV ~

PI ~ P1 ~
a
F1

FO
a;
1;;

a::
"0
-2

-2
BOSC

u -160n h
[t---4-~ A6 B6 -2 g? ~~
:g'g
r---- V2 I-' VClk

[J--""""'t-.., A5 B5 -2 tFll---
«:;
VI
Manual ,[
[ (external)

~t8~'"
Reset
[t---t-~ A4 84

A 3 [ t - - t - . , A3 83 -2 '-- ~ Ml

A2 [LJ---t-..., A2 B2 -2 Ml....-' V-- MO

Q Automatic [
[ (Internal)
A1 [U---t-..., A1 Bl \ -2 r R1
Reset
-CP,-
AO [U--+--I'" AO BO v- RO
Z7 ze Z5 Z4 Z3 Z2 ZI ZO
Refresh
Reyest y DAORefresh
G.:r.nt

Multiplexer J'
Control,
Logic

}5
RNV:c1--~~--~-~-~~-~-+-+--t--~R~/W~-
- RASI
__~~--~~~~'~Window
r....
M~ =""" , ,
Select
1
0
E Master
Timing
1-7 Start
~BOSC
4161 ~OS
1/1
~
......
? Pp Oscl n

o [O------+--1f-+-j-+-+--I--t-----~ OSCOut
'R.s.t '---Tj--;jr--.,---'+
Destlnat;ons; L-----_-_-::.I..r1.J:,...LrlWT""IL-..lJr .,-lUr-r-wr-r-wr "';w'''';
1 . . . J r - - - - - - - -wr-'wrr-r,U--------..J
r
RAS1'Z7 Z8 Z5 Z4 Z3 Z2 Z1 ZO iim CAS WE

See Text ... Pege B.

4-636
SN74LS783·MC6883

SAM BLOCK DIAGRAM DESCRIPTION

MPU Addresses (AO - A 15):
These 16 signals come directly from the MPU and are used to directly address up to 64K memory locations
(K= 1024) or to indirectly address up to 96K memory locations, by using a paging bit "P" (see pages 17 and
18 for memory maps.) Each input is approximately equivalent to one low power Schottky load.
VDG Address Counter (80 - 815):
These 16 signals are derived from one input (DAO) which is the least significant bit of the VDG address. Most
of the counter is simply binary. However, to duplicate the various addressing modes of the MC6847 VDG,
ADDRESS MODIFIER logic is used. Selected by three VDG mode bits (V2, Vl, and YO) from the SAM CONTROL
REGISTER, eight address modifications are obtained as shown in Figure 5.
Also, notice that bits B9-B15 may be loaded from bits FO-F6 from the CONTROL REGISTER. This allows the
starting address of the VDG display to be offset (in V2K increments) from $0000 to $FFFFt. 89-B15 are loaded
when a VERTICAL PRE-LOAD(VP) pulse is generated. VP goes active (high) when HS from the VDG rises if DAO
is high (or a high impedance.) This condition should occur only while the TV electron beam is in vertical
blanking and is simply implemented by connecting FS and MS together on the MC6847. The VP pulse also
clears bits B 1 - B8.
Finally, a HORIZONTAL RESET (HR) pulse may also affect the counter by clearing bits Bl - B3 or Bl - B4
when HS from the VDG is LOW (see Figure 5.) The HR pulse should occur only while the TV electron beam is
in horizontal blanking.
In summary, DAO clocks the VDG ADDRESS COUNTER; HR initializes the horizontal portion and VP initializes
the vertical portion of the VDG ADDRESS COUNTER.

•
REFresh Address Counter (CO - C6):
A seven bit binary counter with outputs labeled CO - C6 supplies bursts of eight* sequential addresses
triggered by a HS high to low transition. Thus, while the TV electron beam is in horizontal blanking, eight
sequential addresses are accessed. Likewise, the next eight addresses are accessed during the next horizontal
blanking period, etc. In this manner, all 128 addresses are refreshed in less than 1.1 milliseconds.
Address Multiplexer:
Occupying a large portion of the block diagram in Figure 4, is the address multiplexer which outputs bits
ZO-Z7 (as addresses to dynamic RAM's.) Inputs to the address multiplexer include the VDG address (BO - B15)
the REFresh address (CO- C6) and the MPU address (AO - A 15) or (AO - A 14 plus one paging bit "P".) The pagmg
bit "P" is one bit in the SAM CONTROL REGISTER that is used in place of A 15 when memory map TYpe #0 is
selected (via the SAM CONTROL REGISTER "TY" bit.)
Figure 6 shows which inputs are routed to ZO - Z7 and when the routing occurs relative to one SAM machine
cycle. Notice that Z7 and RAS1 share the same pin. Z7 is selected if "M1" in the SAM CONTROL REGISTER IS
HIGH (Memory size = 64K.)
Address Decode:
At the top left of Figure 4, is the Address Decode block. Outputs S2, S1, and SO form a three bit encoded
binary word(S). Thus S may be one of eight values (0 through 7) with each value representing a different range
of MPU addresses. (To enable peripheral ROM's or 1/0, decode the S2, S1, and SO bits into eight seperate
signals by using a 74LS138, 74LS155 or 74LS156. Notice that S2, Sl, and SO are not gated with any timing
signals such as E or 0.)
Along with the A5 - A15 inputs is the MEMORY MAP TYpe bit (TY.) This bit is soft-programmable (as are all
16 bits in the SAM CONTROL REGISTER,) and selects one of two memory maps. Memory map #0 is intended
to be used in systems that are primarily ROM based. Whereas, memory map #1 is intended for a primarily
RAM based system with 64K contiguous RAM locations (minus 256 locations.) The various meanings of S2, Sl,
SO are tabulated in Figure 16 (page 19) and again on pages 17 and 18.
In addition to S2, S1, and SO outputs is a decode of $FFCO through $FFDF which, when gated with E and
R/W, results in the write strobe for the SAM CONTROL REGISTER.
SAM Control Register
As shown in Figure 4, the CONTROL REGISTER has 16 "outputs":
~DG Addressing Modes: V2, V1, VO MPU Rate: R1, RO
VDG Address OFFset: F6, F5, F4, F3, F2, Fl, FO ~emory Size (RAM): Ml,MO
32K fage Switch: P Memory Map TYpe: TY
When the SAM is reset (see page 10,) all 16 bits are cleared. To set anyone of these 16 bits, the MPU simply
writes to a unique** odd address (within $FFCl through $FFDF.) To clear anyone of these 16 bits, the MPU
.. If HS IS held low longer than 8 ",,5, then the number of sequential addresses 10 one refresh "BURST" IS proportional to the time Interval
dunng which HS IS low.
** See pages 11 or 18 for speCific addresses.
t In thiS document. the "s" symbol always preceeds hexidecimal characters
8

4-637
 SN74LS783-MC6883

simply writes to a unique"" even address (within $FFCO through $FFDE.) Note that the data on the MPU data
bus is irrevelant.
Inputs to the control register include A4, A3, A2, A 1 (which are used to select which one of 16 bits is to be
cleared or set), AO (which determines the polarity ... clear or set,) and R/W, E and $FFCO - $FFDF (which
restrict the method, timing and addresses for changing one of the 16 bits.) For more detailed descriptions of
the purposes of the 16 control bits, refer to related sections in the BLOCK D.IAGRAM DESCRIPTION (pages 8
through 12) and the PROGRAMMING GUIDE (pages 14 through 18).
** See pages 17 or 18 for specific addresses.

FIGURE 5 - VDG ADDRESS MODIFIER

Mode Division Variables Bits Cleared by HS (lowl
V2 V1 VO X Y
0 a a 1 12 Bl-B4
0 0 1 3 1 Bl-B3
0 1 0 1 3 Bl-B4
0 1 1 2 1 81-B3
1 0 0 1 2 Bl-B4
1 0 1 1 1 Bl-B3
1 1 0 1 1 Bl-B4
1 1 1 1 1 None IDMA MODE)

•
FIGURE 6 - SIGNAL ROUTING for ADDRESS MULTIPLEXER
Memory Size RowlColumn Signals Routed to ZO-Z7 Timing
Signal
Ml MO Source Z7 Z6 Z5 Z4 Z3 Z2 Zl ZO (Figure 2)

4K 0 0 MPU ROW * A6 AS A4 A3 A2 Al AD T7-TA

COL * L All Al0 A9 A8 A7 A6 TA-TF
VDG ROW * B6 BS B4 B3 B2 Bl BO TF-T2
COL * L Bll Bl0 89 B8 B7 B6 T2-T7
REF ROW * C6 CS C4 C3 C2 Cl CO TF-T2
COL * L L L L L L L T2-T7

16K 0 1 MPU ROW * A6 AS A4 A3 A2 Al AO T7-TA

COL * A13 A12 All Al0 A9 A8 A7 TA-TF
VDG ROW * B6 B5 B4 B3 B2 Bl BO TF-T2
COL * B13 B12 Bll Bl0 B9 B8 B7 T2-T7
REF ROW * C6 C5 C4 C3 C2 Cl CO TF-T2
COL * L L L L L L L T2-T7

64K (dynamic) MPU ROW A7 A6 AS A4 A3 A2 Al AD T7-TA

COL PIA lS*** A14 A13 A12 All Al0 A9 AS TA-TF
1 0
VDG ROW B7 B6 BS B4 B3 B2 Bl BO TF-T2
COL B1S B14 B13 B12 Bll 810 B9 B8 T2-T7
REF ROW L C6 CS C4 C3 C2 Cl CO TF-T2
COL L L L L L L L L T2-T7

64K (static) MPU ROW A7 A6 AS A4 A3 A2 Al AO T7-T9

1 1 COL PIA 15*** A14 A13 A12 All Al0 A9 A8 T9-TF
VDG ROW B7 B6 B5 B4 B3 B2 Bl BO TF-n
COL 815 B14 B13 812 Bll Bl0 B9 B8 n-T7
REF ROW L C6 C5 C4 C3 C2 Cl CO TF·n
COL L L L L L L L L n·T7

Notes: "L" Implies logical LOW level.

'Z7 functions 88 RAS1 and It8levells address dependent. For example, when using two banks of 16K x 1 RAMs, RASO is active for addresses
$0000 to $3FFF and HAS1 Is active lor addres.es $4000 to $7FFF.
'''K Map TYpe = O. then page bit "P" Is the output (otherwls. A15).
9

4-638
SN74LS783-MC6883

Internal Reset
By lowering VCC below 0.6 volts for at least one millisecond, a complete SAM reset is initiated and is
completed within 500 nanoseconds after VCC rises above 4.25 volts.
NOTE: In some applications, (for example, multiple "VDG-RAM" systems controlled by a single MPU)
multiple SAM ICs can be synchronized as follows:
• Drive all SAM's from one external oscillator.
• Stop external oscillator.
• Lower VCC below 0.6 volts for at least 1.0 millisecond.
• Raise VCC to 5.0 volts.
• Start external oscillator.
• Wait at least 500 nanoseconds.
Now, the "E" clocks from all SAM's should be in-phase.
External Reset
When the VClk pin on SAM is forced below 0.8 volts for at least eight cycles of "oscillator-out", the SAM
becomes partially reset. That is, all bits in the SAM control register are cleared. However, signals such as RAS,
CAS, WE, E or Q are not stopped (as they are with an internel reset), since the SAM must maintain dynamic
RAM refresh even during this external reset period.
Figure 7 shows how VClk can be pulled low through diode D1 when node "A" is low.* When node "A" is
high, only the backbiased capacitance of diode D1 loads the 3.58 MHz on VClk. Diode D2 helps discharge C1

•
(Power-on-Reset capacitor) when power is turned off. Diode D3 allows the MPU reset time constant R2C2 to
be greater than the SAM reset time constant. Thereby, ensuring release of the SAM reset prior to attempting
to program the SAM control register.

FIGURE 7 - EXTERNAL RESET CIRCUITRY

+5.0 V +5.0 V

100 k!l 100 kO

R2
03

Manual 1
System
Reset
SWitch'
/1

MC6883 MC6847 MC6809E

VDG Synchronization
In order for the VDG and MPU to share the same dynamic RAM (see page 13,) the VDG clock must be stopped
until the VDG data fetch and MPU data fetch are synchronized as shown in Figure 12. Once synchronized, the
VDG clock resumes its 3.579545 MHz rate and is not stopped again unless an extreme temperature change (or
SAM reset) occurs. When stopped, the VDG clock remains stopped for no more than 32 OSCOut cycles (ap-
proximately 2 microseconds.)
In the block diagram in Figure 4, DAO enters a block labeled VDG Timing Error Detector. If DAO rises between
time reference points** "A and "c, then Error is high and VClk is the result of dividing BOSC (Buffered OSCOut
= 14 MHz) by four. However, if DAO rises outside the time Window "A to "c, then Error goes LOW and the VDG
stops. A START pulse at time reference point "B (center of Window) restarts the VDG ... properly synchronized.

*Use a diode with sufficiently low forward voltage drop to meet VIL requirement at VClk

**See tlmmg diagrams on page 5 and 6.

10

4-639
 SN74LS783-MC6883

Changing the MPU Rate (by changing SAM control register bits RO, R1).
Two bits in the SAM control register determine the period of both "E" and "0" MPU clocks. Three rate modes
are implemented as follows:

RATE MODE R1 RO
SLOW 0 0 The frequency of "E" (and "0") is f crystal - 1S. This rate mode is automatically selected when
the SAM is reset. Note that system timing is least critical In this "SLOW" rate mode.
A.D. 0 1 The frequency of "E" (and "0") is either f crystal - 16 or f crystal - 8, depending on the address
(Address Dependent) the MPU is presenting.

FAST 1 X The frequency of "E" (and "0") is f crystal - 8. This is accomplished by stealing the time that
is normally used for VDG/REFRESH, and uSing this time for the MPU. Note: Neither VDG display
nor dynamic RAM refresh are available In the "FAST" rate mode. (Both are available In SLOW
and A.D. rate modes).

When changing between any two of the three rate modes, the following procedures must be followed to
ensure that MPU timing specifications are met:

RATE MODE

I SLOW
A.D.
FAST
------------Z--
~m" ~'~" /:
~quen'::f~__
(See Below)
Set RO, then CLEAR R1
S R1
et .
Th;. o;rect ,."" ;
- - ' \ ~t~owed exce£.!...b~: __
hardware reset ....-I
•

May be ANY address from $0000 to $7FFF.

SE~UENCE #1: ___
7D 00 00 TST #$0000 ... Synchronizes STA instruction to write dUring T2-TG (See Figure #8).-
21 00 BRN 00
B7 FF DS STA #$FFDS ... Clears bit RO

*Note: "TST" instruction affects Me6S09E condition code register

Changing the MPU Rate (In Address Dependent Mode)

When the SAM control register bits "R1", and "RO" are programmed to "0" and "1", respectively, the
Address Dependent Rate Mode is selected. In this mode, the + 16 MPU rate is automatically used when
addressing within $0000 to $7FFF* or $FFOO to $FF1 F ranges. Otherwise the ~ 8 MPU rate is automatically
used. (Refer to Figure 8 for sample "E" and "0" waveforms yielding ~ 8 to - 16 and ~ 16 to - 8 rate
changes). This mode often nearly doubles the MPU throughput while still providing transparent VDG and
dynamic, RAM refresh functions. For example, since much of the MPU's time may be spent performing
internal MPU functions (address = $FFFF)**, accessing ROM (address = $8000 to $FEFF) or accessing I/O
(address = $FF20 -- $FF5F), the faster f crystal + 8 MPU rate may be used much of the time.
Note The VDG operates normally when USing the SLOW or A.D rate modes However, In the FAST rate mode, the VDG IS not allowed access to
the dynamiC RAM.

FIGURE 8 - RATE CHANGE E AND Q WAVEFORMS

fast slow fast

(~ ______JA 'r~------------------~A~-------------------- ~ ~ __
E:~ I ~
0:--,L.....Jr - 1L-Jr - 11'--;-......
r---...J- 1 I r-----JLJ
"slow" address detected herte t
"fast" address detected here

·When uSing Memory Map 0, addresses $0000 to $7fFF may access DynamiC RAM
·-The MC6S0S outputs $FFFF on AD-A 15 when no other valid addresses are being presented

11

4-640
SN74LS783-MC6883

Oscillator
In Figure 4, an amplifier between OSCln and OSCOut provides the gain for oscillation (using a crystal as shown
in Figure 9.) Alternately, Pin 5 (OSCln) may be grounded while Pin 6 (OSCOut) may be driven at low-power
Schottky levels as shown in Figure 10. Also, see VIH, VIL on page 2.

AC Specifications"
OseOut Units
Max Typ Min
tDH(Ose) - 30 22 ns
tDLlOse) - 30 22 ns
tevclOse) - 70 62.4 ns

FIGURE 9 - CRYSTAL OSCILLATOR

•
Suggested Component Values
Freq.
CV
MHz CV" CF" R1" n;'* E:~* X1
SAM
14.31818
2.5-30
pF
33
pF
1.5
kn - 100K 10K .
.
MC6883

~---------------"6
OseOut ""\ ' 16.0000
2.5-30
pF
33
pF
1.5
kn - 100K 10K
\\
\ \
\ \
\ \

Recommended Crystal Parameters

1\
RS
14.31818 MHz"
10 n ± 2.0 n
16.0000 MHz"
10 n ± 2.0 n
I
\
"
"A ------lIDf-1___ B
\

"- AC~'
CO 5.0 pF ± 1.5 pF 6.0 pF ± 1.0 pF \
C1 0.0245 pF ± 15% 0.0319 pF ± 15%
L1 5.05 mH 3.1 mH
Q 50K ± 10K 40K ± 10K
CO
Calibration Tolerance 0002% at 26°C
Temperature Tolerance 0001% oDe to 70 D
e

FIGURE 10 - TTL CLOCK INPUT

SAM (R4 = 200 n Typ, 50 n Min)

MC6883 _o<1~....... -+-___ ..;,R;V41r-C-rr-r---< ~

L..________________......J Os~Out ~ 74LSOO

(Used as an input)

*Optimum values depend on characteristics of the crystal (X1). For many applications, VClk must be 3.579545 MHz ± 50 Hzl Hence,
08COut must be made similarly "drift resistant" (by balancing temperature coefficients of Xl, CV, CF, Rl, R2 and R31.
**Speclfically cut for MC6883 are International Crystal Manufacturing, Inc. Crystals (#167568 for 14.31818 MHz or #167569 for 16.0 MHz).
However, other crystals may be used

12

4-641
 SN74LS783·MC6883

THEORY OF OPERATION
Video or No Video
Although the MC6883 may be used as a dynamic RAM controller without a video display*, most applications
are likely to include a MC6847 video display generator (VDG). Therefore, this document emphasizes MC6883
with MC6847 systems.

Shared RAM (with interleaved DMA)

To minimize the number of RAM and interface chips, both the MPU and VDG share common dynamic RAM.
Yet, the use of common RAM creates an apparent difficulty. That is, the MPU and VDG must both access the
RAM without contention. This difficulty is overcome by taking advantage of the timing and architecture of
Motorola MPU's (MC6800, MC6801E, MC6809E, MC68000). Specifically, all MPU accesses of external memory
always occur in the latter half of the machine cycle, as shown below:

FIGURE 11 - MOTOROLA MPU TIMING

One Machine Cycle

( A~ ______~\
'E' Clock:·
(Approx.1 MHz)ll I I
1"'-------,
I '--___-""
r
', ________ y __ ----.J Y---------'f------.Jy

•
MPU Address MPU Data MPU Address MPU Data
Window Window

Similarly, the MC6847 (non-interlaced) VDG transfers a data byte in a half machine cycle (E or <1>2). Thus,
when properly positioned, VDG and MPU RAM accesses interleave without contention as shown below:

FIGURE 12 - MOTOROLA MPU WITH VDG TIMING

VDG Data VDG Data
VDG Address Window VDG Address Window
(_________ A
_____ -----..~---------A---___..,~
'E' Clock:
(Approx. 1 MHz) l I MPU Half I VDG Half r
'---------v---------...J~--------f----...Jy
MPU Address MPU Data MPU Address MPU Data
Window Wmdow

This Interleaved Direct Memory Access (IDMA) is synchronized via the MC6883 by centering the VDG data
window half-way between MPU data windows.**
The result is a shared RAM system without MPUIVDG RAM access contention, with both MPU and VDG
running uninterrupted at normal operating speed, each transparent to the other.
RAM Refresh
Dynamic RAM refresh is accomplished by accessing eight*** sequential addresses every 64*** microseconds
until 128 consecutive addresses have been accessed. To avoid RAM access contention between REFRESH and
MPU, each of the 128 refresh accesses occupies the "VDG half" of the interleaved DMA (IDMA). Furthermore,
refresh accesses occur only during the television retrace period (at which time the VDG doesn't need to access
RAM).
In summary, the VDG, MPU and MC6883's Refresh Counter all transparently access the common dynamic
RAM without contention or interruption.
Why IDMA?
Use of the interleaved direct memory access results in fast modification to variable portions of display RAM,
by the MPU, without any distracting flashes on the screen (due to RAM access contention.) In addition, the
MPU is not slowed down nor stopped by the MC6883; thereby, assuring accurate software timing loops without
costly additional hardware timers. Furthermore, additional hardware and software to give "access permission"
to the MPU is eliminated since the MPU may access RAM at any time.
* Only 1 pm, (DAO) out of 40 PinS is dedIcated to the video display
** See VDG synchronization (page 10) for more detail.
*** When not uSing a MC6847, HS may be wired low for continuous transparent refresh 13

4-642
SN74LS783-MC6883

"Systems On Silicon" Concept

Total Timing
For most applications, the SAM can supply complete system timing from its on-chip precision 14.31818 MHz
oscillator. This includes buffered MPU clocks (E and Q), VDG clock, color subcarrier (3.58 MHz), row address
select (RAS), column address select (CAS) and write enable (WE).
Total Addrass Decode
For most applications, the SAM plus a "1 of 8 decoder" chip completely decodes 1/0, ROM and RAM chip
selects without wasting memory address space and without needlessly chopping-up contiguous address space.
Chip selects are positioned in address space to allow three types of memory (RAM, local ROM and cartridge
ROM) independent room for growth. For example, RAM may grow from address $OOOO-up, cartridge ROM may
grow from address $FEFF-down and local ROM may grow from $FBFF-down. Alternately, if the application
requires minimum ROM and maximum contiguous RAM, a second choice of two memory maps places RAM
from $0000 to $FEFF. (See pages 17 and 18.)
In both memory maps all 1/0, MPU vectors, SAM control registers, and some reserved address spaces are
efficiently contained between addresses $FFOO and $FFFF. '
How Much RAM?
Using nine SAM pins (ZO - Z7 and RASO) the following combinations require no additional address logic .

MSB
Address:
LSB
FIGURE 13 -

Z5Z4Z3Z2Z 1ZO ..................................... RASO

RAM CONFIGURATIONS
Chip Select:

Z5Z4Z3Z2Z1Z0 ..................................... RAS1 (=Z7)

Z6Z5Z4Z3Z2Z1Z0 ..................................... RASO
I
r -----One or two banks of 4K x 8 (like MCM4027's)
I
Z6Z5Z4Z3Z2Z1 ZO ..................................... RAS 1 (= Z7) \ - - - - - - One or two banks of 16K x 8 (like MCM4116's)
•
Z7Z6Z5Z4Z3Z2Z1Z0 ..................................... RASO - - - - - - - - - - - One bank of 64K x 8 (like MCM6665's)

PROGRAMMING GUIDE
SAM - Programmability
The SAM contains a l6-bit control register which allows the MC6809E to program the SAM for the following
options:
VDG Addressing Mode .......... 3-bits
VDG Address Offset ............... 7-bits
32K Page Switch ..................... l-bit
MPU Rate ............................... 2-bits
Memory Size .......................... 2-bits
Map Type ................................ l-bit
Note that when the SAM is reset by first applying power or by manual hardware reset,t all control register
bits are cleared (to a logic "0").
VDG Addressing Mode
Three bits (V2, Vl, VOl control the sequence of DISPLAY ADDRESSES generated by the SAM (which are used
to scan dynamic RAM for video information). For example, if you wish to display Dynamic RAM data as
INTERNAL ALPHANUMERICS VIDEO, you should program; the MC6847 for the INTERNAL ALPHANUMERICS
MODE and CLEAR BITS V2, Vl and VO in the SAM. The table on the following page summarizes the available
modes:
t See Figure 7 for manual reset circuit.
*Typically, part of •PIA (MC6821) at location $FF22 is used to control MC6847 modes. (See MC6847 Data Sheet. I

14

4-643
 SN74LS783·MC6883

MC6847 Mode SAM Mode

GM8
Mode Type G/A GM2 GMl EXTii CSS V2 V1 VO
Internal Alphanumerics a x x a x 0 a 0
External Alphanumerics a x x 1 X a a 0
OSemigraphics - 4 a x x a x 0 a 0
Semigraphics - 6 a x x 1 X a 0 0
Semigraphics - S' a x x a x a 1 a
Semigraphics - 12' a x x a x 1 a a
Semigraphics - 24' a x x a x 1 1 a
Full Graphics - lC 1 a 0 0 x 0 0 1
Full Graphics - 1R 1 a a 1 x 0 0 1
Full Graphics - 2C 1 0 1 a x a 1 a
Full Graphics - 2R 1 0 1 1 X 0 1 1
Full Graphics - 3C 1 1 0 a X , a 0
Full Graphics - 3R 1 1 a 1 X 1 a 1

•
Full Graphics - 6e 1 1 1 0 X 1 1 0
Full Graphics - 6R 1 1 1 1 X 1 1 0
Direct Memory Accesst X X X X X 1 1 1
*58,512, & 824 modes are not descnbed In the MC6847 Data Sheet. See appendix ,A " .
I

tDMA is identical to 6R except as shown in Figure 5 on page 9

VDG Address Offset

Seven bits (F6, F5, F4, F3, F2, Fl and FO) determine the Starting Address for the video display. The
"Starting Address" is defined as "the address corresponding to data displayed in the Upper Left corner of
the TV screen". The "Starting Address" is shown below in binary:

Note that the "Starting Address" may be placed anywhere within the 64K address space with a resolution of
'12K (the size of one alphanumeric page).
The F6-FO bits take effect during the TV vertical synchronization pulse (i.e., when FS from MC6847 is low).

Page Switch
One bit (P1) is used "in place of" A 15 from the MC6809E in order to refer access within $OOOO-$7FFF to one
of two 32K byte'pages of RAM. If the system does not use more than 32K bytes of RAM, Pl can be ignored.--

**When using 4K x 1 RAMS, two banks of eight IC's are allowed ThiS accounts for Addresses $OOOO-1FFF. Also, thiS same RAM can be
addressed at $2000·$3FFF, $400Q·$5FFF and $6000·$7FFF

15

4-644
SN74LS783-MC6883

MPU Rate
Two bits (R1, RO) control the clock rate to the MCS809E MPU. The options are:

RATE (FREQUENCY OF "E" CLOCK) R1 RO

0.9 MHz (Crystal Frequency -;- 16) Slow 0 0
0.9/1.8 MHz (Address Dependent Rate) 0 1
1.8 MHz (Crystal Frequency ~ 8) Fast 1 X

(Typical Crystal Frequency = 14.31818 MHz)

In the "address dependent rate" mode, accesses to $0000-$7FFF and $FFOO-$FF1 F are slowed to 0.9 MHz
(crystal frequency -;- 16) and all other addresses are accessed at 1.8 MHz (crystal frequency ~ 8.)
Memory Size
Two bits IM1 and MO) determine RAM memory size. The options are:

SIZE M1 MO

•
One or two banks of 4K x 1 dynamic RAMs 0 0
One or two banks of 16K x 1 dynamic RAMs 0 1
One bank of 64K x 1 dynamic RAMs 1 0
Up to 64K static RAM" 1 1

*Requlres a latch for demultlplexmg the RAM address

IMPORTANT!
Note: 8e sure to program the SAM for the correct memory size before using RAM (i.e., for a subroutine
stack).

Map Type
One bit lTV) is used to select between two memory map configurations.
Refer to pages 17, 18 and 19 for details. When using Map Type "TV = 1", only the "Slow" MPU rate may
be used. Future versions of the SAM may allow use of all rates.

Writing To The SAM Control Register

Any bit in the control register (CR) may be set by writing to a specific unique address. Each bit has two unique
addresses ... writing to the even # address clears the bit and writing to the odd # address sets the bit. (Data
on the data bus is irrelevant in this procedure.) The specific addresses are tabulated on pages 17 and 18.
If desired, a short routine may be written to program the SAM CR "a word at a time". For example, the
following routine copies "8" bits from "A" register to SAM CR addresses beginning with address "X".

SAMl 46 ROR A 7 6 5 4 3 2
24 06 BCC SAM2
30
A7
01
80
INX
STA
(LEAX1,X)
O,X·
(I II I
20 02 BRA SAM3
SAM2 A7 81 STA O,X"
SAM3 5A DEC B
26 F2 BNE SAMl
39 RTS

16

4·645
 SN74LS783-MC6883

FIGURE 14 - MEMORY MAP (TYPE #0)

COURSE FINE
MC6809E
MC6809E ___ S _ Address
Vectors, Bits f Definitions
SAM ~ $FFFF ~---
Control,
110
1"- $FFOO

ROM2**

(S=3)

(S

Reserved
- - - - k$COOO for future
MPU
ROM1 •• enhancements.

Do not use!
(S=2)

I - - - - k$AOOO

ROMO"'

(S= 1)
{ Transparent
~ Refresh

r---+-- --- k$SOOO

I (S
RAM
(S=OifRIW = 1)
(5=7 if RIW = 0)
I
I
I
I
I
I
1
-<$4000

iT
:
1
I
16K (5 1102

I
1
I (S 11O,
,--
I
f-<$1000
1 T
I

:
'--'v-"' ' '--'v-"'
r $0000
IS IIOO(Slowl

Page 1 Page 0

*Note: **May also be RAM

M.S. = Most Significant S = Set Bit ( . .
L.S. == Least Significant C == CI ear B't
I
(All bits are cleared when SAM IS reset. I
S = Device Select value = 4 x 52 + 2 x 51 + 1 x SO
17

4-646
SN74LS783·MC6883

FIGURE 15 - MEMORY MAP (TYPE #1)

COURSE FINE

MC6S09E 52,
Me6S09E
.... 8 -+- Address 51, SO Me6809E
Vectors, Bits t Label
SAM ~ J$FFFF
Control, ~ I"\.
110, Boot 1 '$FFOO
ROM

(S =3
If
R/W =0)

(S =0
If
R/W =1) Reserved
~ - -.~j-<$COOO
(S=2 ••• for future
If MPU
enhancements,
R/W =0)
(5 = 0 Do not use!
If

•
R/W ='1)
r-(S~~
=1
-f-< SAQOO
if
R/W =0)
l Transparent
(8 = 0 } Refresh
if
:2
«
a:: r!!/~ =- '!.!/-< $8000
...J
...J
« (8=0
if
R/VV=1)

(5=7
if
R/W=O)

**Oecode 52,51, and SO with an open

collector SN74LS156 and 'wire-or' state 7
with state 2. (See Appendix B for
suggested decode circuit.)
***To avoid ROM enable during Riw = LOW,
the ROM at 5 ~ 2 must ba gated with R/W.
(See Appendix B for suggested decode circuit.)

,'-----'-< $0000
I/Ool51ow}

*Note:
M,S ... Most Significant
L,S ... Least Significant ~ : ~~;a~i~it \ IAII bits are cleared when SAM is reset.)
= Device Select value = 4 x 52 +

/
S 2 x 51 + 1 x SO
18

4-647
 SN74LS783·MC6883

FIGURE 16 - MEMORY ALLOCATION TABLE

(Also, see the memory MAPs on pages 17 and 18.)

Type # 0: (Primarily for ROM based systems)

8=4(82)+2
(81)+80
Address Range 8 Value Intended Use
$FFF2 to FFFF 2 MC6B09E Vectors: Reset, NMI, 8WI, IRO, FIRO, 8W12, 8W13.
FFEO to FFF1 2 Reserved for future MPU enhancements.
FFCO to FFDF 7 8AM Control Register: VO, - V2, FO - F6, P, RO, R1, MO, M1, TY.
FF60 to FFBF 7 Reserved for future control register enhancements.
FF40 to FF5F 6 1102: InputiOutput (PIAs, ACIAs, etc.) To subdivide, use AO-A4.
FF20 to FF3F 5 1101: InputlOutput (PIAs, ACIAs, etc.) To subdivide, use AO - A4.
FFOO to FF1 F 4 1100: InputlOutput (PIAs, ACIAs, etc.) To subdivide, use AO - A4.
COOO to FEFF 3 ROM2: 16K addresses. External cartridge ROM".
AOOO to BFFF 2 ROM1: BK addresses. Internal ROM". Note that MC6S0SE vector addresses select this
ROM".
BOOO to SFFF L ROMO: BK addresses. Internal ROM".
0000 to 7FFF o if R/W = 1 RAM: 32K addresses. RAM shared by MPU and VDG.
7 if Riw =0

• Type # 1:

Address Range
$FFF2 to FFFF
8 Value
2
*Not restricted to ROM. For example, RAM or 1/0 may be used here.

(primarily for RAM based systems)

8=4(82)+2
(81)+80
Intended Use
MC6B09E Vectors: Reset, NMI, 8WI, IRO, FIRO, 8W12, 8W13.
FFEO to FFF1 2 Reserved for future MPU enhancements.
FFCO to FFDF 7 8AM Control Register: VO - V2, FO - F6, P, RO, R1, MO, M1, TY.
FF60 to FFBF 7 8mall ROM: Boot load program and initial MC6BOS vecto~s.
FF40 to FF5F 6 1102: Input/Output (PIAs, ACIAs, etc.) To subdivide, use AO·A4.
FF20 to FF3F 5 1/01: InputlOutput (PIAs, ACIAs, etc.) To subdivide, use AO-A4.
FFOO to FF1F 4 1100: Input/Output (PIAs, ACIAs, etc.) To subdivide, use A2-A4.
,0000 to FEFF o if R/W = 1 RAM: 64K( - 256) addresses, shared by MPU and VDG.
(If R/W = 0 then 8 = 3 for $COOO-$FEFF; 8 = 2 for $AOOO-$BFFF; 8 = 1 for
$BOOO-$SFFF and 8 = 7 for $OOOO-$7FFF.)

19

4-648
S N74LS783- M C6883

APPENDIX A
VDG/SAM Video Display System Offers 3 New Modes
by
Paul Fletcher
There are three new modes created when the VDG ience B2 should be made equal to BO and B3 should
and SAM are used together in a video display sys- be made equal to B1. This eliminates a screen place-
tem. These modes offer alphanumeric compatibility ment problem which would cause other codes to
with 8 color low-to-high resolution graphics, change patterns when moved vertically on the
64H*64V, 64H*96V, 64H*192V. The new modes S8, screen. The illuminated boxes can be one of eight
S12, and S24 are created by placing the VDG in the colors which are controlled by B4 - B6 (see Figure
Alpha Internal mode and having the SAM in a 2K, 18), The bytes needed to control all the boxes in the
3K or 6K full color graphics mode. In all modes the 8*12 dot box must be spaced 32 address spaces
VDG's S/1>. and Inv. pins are connected to data bits apart in the display RAM because of the addressing
DD7 and DD6 to allow switching on the fly between scheme orginally used in the VDG and duplicated
Alpha and Semigraphics and between inverted by the SAM. This means to place an alphanumeric
and non-inverted alpha. This method is used in character on the TV screen it requires 4, 6, or 12
most \(DG systems to obtain maximum flexibility. bytes depending on the mode used. These bytes are
The three modes divide the standard 8*12 dot box placed 32 memory locations apart in the display
used by the VDG for the standard alpha and semi- RAM (see Figure 18). This multiple byte format al-

•
graphics modes into eight 4*3 dot boxes for the S8 lows the mixing of character rows of different char-
mode, twelve 4 *2 dot boxes for the S 12 mode, and acters in the same 8*12 dot box creating new char-
twenty-four 4*1 dot boxes for the S24 mode. Figure acters and symbols. It also allows overlining and
17 shows the arrangement ofthese boxes. One byte underlining in eight colors by switching to semi-
is needed to control two horizontally consecutive graphics at the correct time.
boxes. It therefore takes four bytes for the S8, six These new modes optimize the memory versus
bytes for the S12, and 12 bytes for the S24 mode to screen density tradeoffs for RF performance on
control the entire 8*12 dot box. These two horizon- color TVs. This could make them the most versatile
tally consecutive boxes have four combinations of of all the modes depending on the users creativity
luminance controlled by bits BO - B3. For conven- and the software sophistication.

APPENDIX B
Memory Decode for "MAP TYPE = 1"
MPU Vectors and
Boot Load ROM
128 X 8 (or 256 X 8)
EN EN

Vee ~ 16
Gnd ~ 8 +5.0 RIW
V
'1103a) 4
+5.0
Ea
6 (02a) 5 V 1/0 2
-= Ea +5.0
5 (01a) 6 V 1/01
+5.0
V
'4 (OOa) liDo
7
SN74LS156

12
3' (03b) Ne

'~~l
11
52 Eb '2 (02b)
Eb
10
-= 3
T(01b) Ne
51 A1 +5.0 V
So 13
AO o(OOb) 9

RAM READ

20

4-649
 SN74LS783-MC6883

FIGURE 17 - DISPLAY MODES 58, 512, 524

BiWisible Dot Correlation

~8~ .
A~~ress Byte

1
Scan
$XXOO ($011
Lines
•
• • $XX20 ($011
$01 is the
58 • • VDG "ASCII"
12
• •

I
• • • •• $XX40 ($011 code for 'A',

• •
•
• $XX60 ($011

• Alphanumerrc Compatible

• Scan
lines

512
~8_1

1 12
Left

Red

Blue

Off
Right

Red

Off

Green
..
$XXOO ($BFI

$XX20 ($AAI

$XX40 ($851

I
Orange Orange $XX60 ($FFI

Off Off $XX80 ($801

Yellow Yellow $XXAO ($9FI

• Options: One of 8 colors for

Lor R or both. Off = Black

Scan
li nes
1- -1 8

f------+-----l
1 Blue
Black
Black

•
Blue
Black
Black
• • • ••
•
*
$XXOO
$XX20
$XX40
$XX60
$XX80
($AFI
($801
($801 VDG
($141 _Code
($181 for T
•••
~r----ij
$XXAO ($18Ij
$XXCO ($181 VDG
524 • • $XXEO ($181 Code
• • $Xl00 ($181 for X
• Black•
Black
$X120 ($181
$X140 ($801
Green Green $X160 ($8FI

• Underline, Overline

• Mix Character Dot Rows

*** Characters will always remain In standard VDG positions.

21

4-650
 en
FIGURE 18 - 58 DISPLAY FORMAT EXAMPLES
LX C2 Cl CO B3,B1 B2,BO
z
~
Color 4

0 X X X Black 0 0 I o~-I ~J r
en
r-(1~.-j 1 0 0 0 Green
ffi•
l I I
BO

L1 LO a) •• Semi
1 0 0 1 Yellow 0 1 [ Off Color
s:
~
1 0 1 0 Blue

L1 LO (b)
Alpha
1 0 1 1 Red 1 0 I I I
Color Off
S8
L1

L1
LO

LO
J 12

(d)
C)
Extra ASCII Code
1

1
1

1
0

1
0

1
Buff

Cyan

Magenta

Orange
1 1 , - - color

en Memory Map

(a)1 $0000
(a)2
(a)3
1st row of 4 x 3
~ _I (a)4

I~
(11 Column 32 Columns dot boxes
m

+
(a)5
c.n of 58 Blocks 32
.....
.. ,~"..
(a§ I
::)1111111111111
"1"1
1 (a)32
(b)1
(b)2
(b)3
$0020

(d) 2nd row of 4 x 3I

(b)4
dot boxes
(b)5

One ROWOf+ (b)32

8 x 12 (c)1 $0040
(c)2
(c)3
TV Screen 3rd row of 4 x 3
(c)4
Resolution dot boxes

+
16 Rows (c)5
Semi = 64 x 64 of 58 Blocks
Alpha = 32 Char. H. x 16 Rows V
(c 32
(d)1 $0060
(d)2
(d)3
4th row of 4 x
(d)4
dot boxes
(d)5

d 32
$0080

I:l

•
 SN74LS783·MC6883

RGURE 19 - EXAMPLE of Mel

) ENDC

r-- ~ .--- ~
I
A15

Al'
A13
A12 21 21
S S
A11 18 18
S A11
19 19
~- Al0 Al0
A9 12 22

AS 23 23

A7 1 1

A6 2 2

A5 3 3

A. CSl 2' CSl 2.

• •
A3 eso 22 CSO 22 5 5

A2 6 6

I Al

AD

RiN
RSl

RSO

CS2
35

36

~I/Oo
21
RSO

CS2
RSl
35

36

~IIOl
21
7

S~ROM2
7

E~·ROM' E

EXPANSION BA
CONNECTOR
"5
BUSY
lIC
...l> '"
0 '"03: '"03:
TSC
~ s:
3: 3: 3: 3: ;;::
n n n n n
) E
en
~
25 (II
co 25 3: ...
3: 3:

...'"l> '"'"l>w
Q ~ co 1 ~
~ '"
II:!
'"'"
FIRQ
IRQ 38,37 38,37
IRQA,B iRQA,B
HALT
NMI
RESET 3' 34

~+12V
+5V 20 20 2. 2.

GND 1 1 12 12

~ -12 V
D7 26 26 17 17
07 D7 07 D7 D7
D6 27 27 16 16

D5 28 15 15

D4
2"
29 29 ,. ,.
03 30 30 13 13

D2 31 31 11 11

Dl 32 32 10 10

DO 33 33 9 9
DO DO DO DO DO
DSPB

'-- '--

64 KEY
ca- .I
l17116115114113\121"1'°\
PB- PA- CB- CA- KEYBOARD PB- PA-
, , ~
CA-

~
~ CONNECTS ~
7 6 5
•
3 2 1 0 7 6 5 • 3 2 1 0 2 1 2 1 HERE 7 6 5 4 3 2 1 0 2 1 2 II
91 81 71 61 51 41 31 2 1 191'813"!,°1 ::.--J 1711611511411311211111°1 91 81 71 61 51 41 31 'I '"1'61 39
1 401
MC6847 Mode Control & MIse 110 connects here

23
4-652
 SN74LS783-MC6883

183 and MC8847 COMPUTER

VIDEO
ENCODER
.10 MODULATOR
.5V CONNECTS

+
~l
r--- Vee
12-NC
23 36 A15 .JV
A'5 _ 9 -
22 Vee 6 ";'-10,
A" :r1 At.
2'
A'3 38 A13 5~-'Ol v~
2.
A12
21
18 19
A12 39 A12
S,~ A2'"
.- ~,-
10.
All
19 ,. All 1 A11
~3
12. RoM, .... ~
A'.
22 '7 A9
A'. 2 AtO
3AS
SI~ A' _ , ~ROMl
Iii _ To
Chip
23 16
AS • AS S.~ AQ"-
1
w
~ROM'!J
Selects
<,.A..!.!;.
1 15 24 A7
A7
2 23 1i~
3
"'3 A6
22
AS
Vee- 16
AS A5 2.
Gnd-8 CHB -4
• 12
A4
21
Gnd
"+
,.
A4 EN EN
5 11 '9 A3
A3 5 •

•
6 lB
A2 A2 ~

7 9 17
~
A' AI
6 15 k
8 8
AD
16
AD s:
~ROMO s:
OSCQUI

50 pF ~ c6- 1431818

iC
~
32
Riii
15
OSCIn
5 -'T MHZ
37
;;OS

f9-35 pF
FS
8
BA
TO PIA
5
BS
33 H5 9 t38H5
BUSY
38 OA.f.'8'-_ _ _ _ _ _ _+_---=24
2 DAD
s:
39
Lie
TSC"G
• C VClk f.'7'---_ _ _----._ _ _ +_---=3~3 elk g~
s:
34
35
E
a Ii
m
i 1--__----""-1
13
r-----'-j0
4 E
;...
4_
FIRQ
3
iRO eAS
40 Z7 Z6 Z5 Z4 Z3 Z2 Zl ZO RASO WE
HALT
2 35 34 33 32 3~ 30 29 28 12 11 10
NMI
I
. . 37
RESET

24
~ ~
~
~
~
~f 7
~Inv
,
12
Vee
Gnd
----0+5 V

~
. As AS A4 A3 A2 At AO

RAM', MCM4116A
RAS CAS WE
r--=19
E2~
I ~
elk r AS

f'--+-~I,",
J
17 2.
07
2 07 3 E117 07 14 3 0 0 2 0 007
"-"1.
'8 26 2 06 5 15 06 14
• 5
P--+--4' ~
..
OB 006 "G
'"...Z '" p-_ _ _,8 DDS GM2~
•
as '4
ii:!
'5 28 2 05 7 13 7
os
7 004 GMl ~
14 27
D4
2 D4 9
Iiit 11 A. I. 8 9
P-----'-t
13 28 2 03 12 8 03 13 12 6 003 GM. ~
OJ
,. " ,. ,.
f'-O-----"1

I.
11 29
30

3'
02
01
2 02
2 0'
2DO
"
16
18
Vcc=zo 6
Gnd=10 4

2
02
01 ,.
co ,.
17 Gnd

18 0
Vee- 20
1-"'-----'1
I. f.!"-_
18
5 002
_ _-"1
o p19 _ _ _,3 DO.
ess
4 DOl EXT ~
~
DO --<I-

fl
'------- 1 ClEAR
VOO Vee VSS VBB
L!!!o Gnd

'5~
'---

f1~r
11

-;-4X01 ... F

+12 V +6V -5V

24
*Thls pin number on 8 different RAM chips IS connected to thiS point

4·653
 SN74LS783-MC6883

FIGURE 20 - EQUIVALENT OF OSCILLATOR INPUT AND OUTPUT FIGURE 23 - E AND Q OUTPUTS

Vee OSCOut Vee Vee

FIGURE 21 - DAO INPUT

I Vee Vee Vee

FIGURE 24 -

Vee
TYPICAL INPUT

Vee

= =

FIGURE 22 - VClk INPUT/OUTPUT

FIGURE 25 - TYPICAL OUTPUT
Vee velk Vee Vee
Vee

25

4-654
® MOTOROLA
MC6889
MC8T28
This device may be ordered under
either of the above type numbers.

NON·INVERTING
QUAD THREE·STATE BUS TRANSCEIVER
This quad three-state bus transceiver features both excellent MOS NON·INVERTING
or MPU compatibility, due to its high impedance PNP transistor BUS TRANSCEIVER
Input, and high-speed operation made possible by the use of Schottky
diode clamping. Both the -48 mA driver and -20 mA receiver outputs MONOLITHIC SCHOTTKY
are short-circuit protected and employ three-state enabling inputs. INTEGRATED CIRCUITS
The device IS useful as a bus extender in systems employing the
M6800 family or other comparable MPU devices. The maximum
Input current of 200 J1A at any of the device input pins assures
proper operation despite the limited drive capability of the MPU
chip. The Inputs are also protected with Schottky-barrier diode
clamps to suppress excessive undershoot voltages.
Propagation delay times for the driver portion are 17 ns maximum
while the receiver portion runs 17 ns. The MC8T28 is identical to
the N E8T2B and it operates from a single +5 V supply.
L SUFFIX

•
• High Impedance Inputs CERAMIC PACKAGE
• Single Power Supply CASE 620
_ I
• High Speed Schottky Technology 16 ,

1
• Three-State Drivers and Receivers
P SUFFIX
• Compatible with M6800 Family Microprocessor
PLASTIC PACKAGE
• Non-Inverting CASE 648

MICROPROCESSOR BUS EXTENDER APPLICATION PIN CONNECTIONS - MC6889

(Clock) MC8T28
GND +5 V 111 1>2

Receiver
Enable
Vec
Input
R eee Iver Driver

,
Output 2 Enable
Input

Receiver
Output
4
Bus 4

Receiver Driver
Output 5 Input
2 4
Receiver
Bus 2 Output
3
Driver
Input 7 Bus 3
2

Gnd

ORDERING INFORMATION

Temperature
Device Alternate Rlngl Plckagl
MC6889L MC8T28L 0 to +7SoC Ceramic DIP
MC6889P MC8T28P 0 to +75 C PI.'tlc DIP

4-655
 MC68891 MC8T28

MAXIMUM RATINGS IT A = 25"C unle •• otherwise noted.)

Rating Symbol Valul Unit
Power Supply Voltage VCC B.O Vdc
Input Voltage VI 5.5 Vdc
Junction Temperature TJ °c
Ceramic Package 175
Pla.tic Package 150
Operating Ambient Temperature Range TA o to +75 °c
Storage Temperature Aange T stg -65 to+150 uc

ELECTRICAL CHARACTERISTICS 14.75 V" VCC" 5.25 V and OoC" TA" 75°C unl ... otherwise noted.)
Characteristic Symbol Min Typ Max Unit
Input Current - Low LogiC State
I Aecelver Enable Input, VllIAE) = 04 V) IlllREI - - -200 IJA
I Dnver Enable Input, VlllDEI = 0.4 VI IIUDEI - - -200
IDnver Input, VlllDI = 04 VI IlllDI - -200
IBus I Aecelverl Input, VILIBI = 0.4 VI IIUBI - - -200
Input Disabled Current - Low LogiC State
IlllDI DIS

I
IDriver Input, VI liD) =0.4 V) - - -25 itA
Input Current-High LogiC State
IAecelver Enable Input, VIHIAEI = 525 VI IIHIREI - - 25 IJA
IDnver Enable Input. VI HIDEI = 5 25 VI IIHIDEI - - 25
IDnver Input, VI HIDI = 525 VI IIHIDI - - 25
Input Voltage - Low logiC State
f~ Ernibiel npud VlllREI - - 085 V
(Driver Enable Input VIUDEI - - 085
(Driver Input) VIL(DI - - 085
(ReceIVer Input) VI liB) - - 0.85
I nput Voltage - High LogiC State
(Receiver Enable Input) VIHlREI 20 - - V
(Dnver Enable Input) VIHIDEI 20 - -
(Driver Input) VIHIDI 20 - -
IRecelver Input! VIHIBI 2.0 - -
Output Voltage - Low LogIC State
IBus Driver) Output, 10l1B) = 48 rnA) VOllBI - - 05 V
IRecelver Output, 10l1A) = 20 rnA) VOllAI - - 0.5
Output Voltage - High logiC State
IBus IDnver) Output, 10HIB) = -10 mAl VOHIBI 2.4 31 - V
IAeceiver Output, 10HIRI = -2.0 mAl VOHIAI 2.4 3.1 -
IAecelver Output, 10HIRI = -10ofIJA, VCC = 5.0 VI 3.5 - -
Output Disabled Leakage Current - High LogiC State
IBus Driver) Output, VOHIB) = 2.4 VI 10HUBI - - 100 IJA
IRecelver Output, VOHIR) = 2.4 V) 10HliAI - - 100
Output Disabled Leakage Current - low logiC State
IBus Output, VOlIB) = 0.5 VI 10ll1B) - - -100 IJA
IRecelver Output, VOlIR) = 0.5 V) 10ll1R) - - -100
Input Clamp Voltage
IDriver Enable Input IIDIDE) = -12 rnA) VICIDEI - - -10 V
IRecelver Eneble Input IICIRE) = +12 rnA) VICIAEI - - -10
IDriver Input IICID) = -12 rnA) VICIDI - - -10
Output Short·Corcull Current, VCC = 525 V III
I Bus I DrIVer) Output! 10SIBI -50 - -150 rnA
I Aeceiver Output! 10SIAI -30 - -75
Power Supply Current ICC - - 110 mA
IVCC = 5.25 V)
(1) Only one output may be .hort-clrculted .t a lime.

4·656
MC68891 MC8T28

SWITCHING CHARACTERISTICS (Unle.. otherwise noted VCC = 50 Vend TA· 250C)

Characteristic Symbol Min Max Unit

Propagation Delay Time-Receiver (CL • 30 pF) tPLH(R) - 17 nl

tpHL(R) 17

Propegation Delay Time-Driver (CL = 300 pF) tPLH(D) - 17 nl

tpHL(D) 17

Propagation Delay Time-Enable (CL = 30 pF) tPZL(R) - 23 nl

- Receiver tPLZ(R) - 1B

- Driver Enable (CL 300 pF) tpZL(D) - 2B

tpLZ(D) - 23

FIGURE 1 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION OELAY FROM

BUS (RECEIVER) INPUT TO RECEIVER OUTPUT, tpLH(R) AND tpHL(R)
I
tTHL';;;;: 5 0 ns
26 V
Input

o v--------11'o='------='-'r1

ir.--
Input Pulse Frequency = 10 MHz
tPHUR)----..j Duty Cycle = 50%
VOH
Output 15 V "-
VOL-----------,--------------__- - J

26V
To Scope ~r To Scope
(I nput} ~ ( In{'Jut)
Input T
92
Receiver 1N916
Output or Equlv.

Driver
Input
Pulse 51 1.3 k 30 pF
Driver
Generator
Enable
Input

4-657
 MC68891 MC8T28

FIGURE 2 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
DRIVER INPUT TO BUS (DRIVER) OUTPUT, tpLH(D) AND tpHL(D)

tTHL ~ 5.0 ns

26V---:="'\I
Input
OV-----
Input Pulse Frequencv = 10 MHz
tpHL!D) Duty Cycle = 50%
VOH-----~

Output
VOL - - - - - - ' - - - - - - - - '

26 V 26V
To Scope Orlver To Scope
( Input) (Output)
Enable
Input

Driver 30
Driver (Bus) lN9.6
Input Output or EqUlv.

I 51
Receiver
Output

~
Enable
Input
260 300 pF

FIGURE 3 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
RECEIVER ENABLE INPUT TO RECEIVER OUTPUT, tPLZ(RE) AND tpZL(RE)

tTLH ~ 5.0 ns tTHL =0;; 5.0 ns

Input

Output
26 V

~3 5 V
----+-J:=-----=,.,...,L
oV----",
tpLZ(REI
-----+-____ ....- - - - - - .
VOL-----"
r-
15 V
tPZL(REI
Input Pulse Frequency = 5 0 MHz
Duty Cycle = 50%

To Scope OV 50 V
To Scope
(Input)
(Output)

24k 240
Receiver
Output

Pulse 51
Generator
lN9.S
SOk 30 pF or Equiv.

4-658
MC68891 MC8T28

FIGURE 4 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIMES FROM
DRIVER ENABLE INPUT TO DRIVER IBUS) OUTPUT, tPLZIDE) AND tPZLIDE)

tTHL~50ns

26 V ---+-j,,=,,-------,t
Input
011 _ _ _.71 Input Pulse Frequency - 50 MHz
Duty Cycle = 50%
tpZLiDE)
~35V---~

Output
VOL------,----------~

OV

I
50 V
To Scope
To Scope Driver Enable (Output)

(I npu.~''-I--4----+---'n.(p,...u_'__--------1
24 k 70
Driver
Input

Driver (Bus)
Pulse .I1.. 51 Receiver Output
Generator Output
lN916
50 k 300 pF or EqU1V
~
Enabi8
Input

FIGURE 5 - BIDIRECTIONAL BUS APPLICATIONS

Receiver
Outputs Receiver
Outputs

Driver Driver
Inputs Inputs

To Other
Drivers/Receivers

Driver Receiver
Enable Enable

4·659
 MC68891 MC8T28

P SUFFIX
PLASTIC PACKAGE
CASE 648-05

L SUFFIX
CERAMIC PACKAGE
CASE 620-02

OPTIONAL LEAD
\ CONFIG. (1,8,9,& 16)

~_ _ _ _ _ _ _---.~TE 5 r, L ~

-"'"-JCo ~.~ 11
PLANE

•
NOTES NOTES
1 LEADS WITHIN 0 13 mm (0 005) RADIUS
1. LEADS WITHIN 0.13 mm 3. DIMENSION "8" DOES NOT
OF TRUE POSITION AT SEATING PLANE
(0.005) RADIUS OF TRUE INCLUDE MOLD FLASH.
AT MAXIMUM MATERIAL CONDITION
POSITION AT SEATING 4. "F" DIMENSION IS FOR FULL
PKG INDEX NOTCH IN LEAD
PLANE AT MAXIMUM LEADS. "HALF" LEADS ARE
NOTCH IN CERAMIC OR INK DOT
MATERIAL CONDITION. OPTIONAL AT LEAD POSITIONS
DIM "L" TO CENTER OF LEADS
WHEN FORMED PARALLEL 2. DIMENSION "L" TO 1,8,S,and 16)
CENTER OF LEADS 5. ROUNDED CORNERS OPTIONAL.
WHEN FORMED
PARALLEL.
MILLIMETERS
DIM MIN MAX
MILLIMETERS
1905 1981 DIM MIN MAX
G22 698
A 18.80 21.34
406 508
038 051
B 6.10 6.60
4.06 5.08
140 1 65
254 8SC 0 0.38 0.53
051 1 14 F 1.02 1.78
J 020 G30 G 254 BSC
K 318 4 06 H 0.38 2.41
L 737 787 J 0.20 .38
M 15' 3.43
N 051 101 0020 L 7.628SC
M 0 10'
CASE 620-02 N 051 1.02

THERMAL INFORMATION

The maximum power consumption an Integrated ClfCUlt the sum of the products of the supplv voltages and supply
can tolerate at a given operating ambient temperature, can currents at the worst case operating condition
be found from the equation
T J(max) = MaXimum Operating Junction Temperature
TJ(max) -TA
as listed In the MaXimum Ratings Section
PD(T A) = ROJAITyp)
T A = MaXimum DeSIred Operating Ambient
Where PD(T A) = Power DISSipation allowable at a given Temperature
ROJA(Typ) = TYPical Thermal ReSistance Junction to
operating ambient temperature ThiS must be greater than
Ambient

4-660
 MC68000L4
® MOTOROLA
(4 MHz)
MC68000L6
(6 MHz)
MC68000LS
Advance InforIDation (8 MHz)
MC68000L10
16-BIT MICROPROCESSING UNIT (10 MHz)
Advances In semiconductor technology have provided the capability
to place on a single Silicon chip a microprocessor at least an order of
magnitude higher In performance and CircUit complexity than has been HMPS
previously available The MC68000 IS the first of a family of such VLSI (HIGH-DENSITY, N-CHANNEL,
microprocessors from Motorola It combines state-of-the-art SILICON-GATE DEPLETION LOADI
technology and advanced circuit design techniques with computer
sCiences to achieve an' architecturally advanced 16-blt microprocessor. 16-BIT
The resources available to the MC68000 user consist of the follOWing. MICROPROCESSOR
• 32-81t Data and Address Registers
• 16 Megabyte Direct AddresSing Range
• 56 Powerful Instruction Types
• Operations on Five Main Data Types
• Memory Mapped 1/0
• 14 AddreSSing Modes L SUFFIX
As shown In the programming model, the MC68000 offers seventeen CERAMIC PACKAGE

II
32-blt registers In addition to the 32-blt program counter and a 16-bit CASE 746
status register The first eight registers (00-07) are used as data
registers for byte (S-blt) , word (l6-blt), and long word (32-bit) data
PIN ASSIGNMENT
operations The second set of seven registers (AO-A6) and the system
stack pOinter may be used as software stack pOinters and base address
registers In addition, these registers may be used for word and long
word address operations All seventeen registers may be used as Index
registers

PROGRAMMING MODEL
31 1615 87 o
- I I - 01
DO

- I I -
- I I - 02 Eight
- I I 03
- 04 Data
l- I I - 05 Registers A22
l- I I - 06 A21
l- I I - Vee
I 07
A20
31 1615 0 A19
l- I - AO A18
l- I - AlA2 A17
t-
t-
- A3
- A4
Seven
Address
A16
A15
Registers
:-. - A5 A14
..... - A6 A13
A12

r ----
L
-U~ Sta"cl;
_______________
Pollu;'r- - -
SupervISor Stack POinter
--~
~
Two Stack
A7 POinters
~ 0
Program
I I Counter
15 ~7 0
ISystem Bvt8 User Byte I Status
Register

4-661
 MC68000L4·MC68000L6·MC68000L8·MC68000L 10

MAXIMUM RATINGS
Rating Symbol Value Un~ This device contains circuitry to protect the
Supply Voltage -0:510 +70 Inputs agamst damage due to high static
Vee V
voltages or electnc fields, however, It IS advIs-
Input Voltage V in -03 to + 70 V ed that normal precautions be taken to avoid
Operating Temperature Range TA o to 70 'e application of any voltage higher than
Storage Temperature Tstg -55tol50 'e maximum-rated voltages to this hlgh-
Impedance CirCUit Rehability af operation IS
enhanced If unused Inputs are tied to an ap-
THERMAL CHARACTERISTICS propriate logic voltage level Ie 9 , either VSS
Characteristic or VCC
Thermal Resistance
Ceramic Package

POWER CONSIDERATIONS

The average chlp-Iunctlon temperature, T J, 111°C can be obtained from

•
T J = TA + IPDoOJAI (1)

Where
T A'" Ambient Temperat,;re, °c
OJA'" Package Thermal Resistance, Junctlon-to-Amblent, °C/W
PD'" PINT + PliO
PINT'" ICC x VCC, \II/atts - Chip Internal Power
PI/o",Power DIssipation on Input and Output Pins - User Determined
For most applicatlors PliO"" PINT and can be neglected

An approximate relationship between PD and T J Ilf PliO IS neglected) IS

PD=K-ITJ+273°CI (2)
SolVing equations 1 and 2 for K gives
K = PDolT A + 273°C) + OJA o PD 2 (3)
Where K IS a constant pertaining to the particular part K can be determined from equation 3 by measuring PD lat eqUilibrium)
for a known T A USing thiS value of K the values of Po and T J can be obtained by solVing equatIOns (1) and (2) IteratIVely for any
value of T A

- 5%, VSS = 0 Vdc, T A = aoc to

DC ELECTRICAL CHARACTERISTICS IVCC= 50 Vdc + 7a c e, See Figures 1,2, anc 3)
Characteristic Symbol Min Max Unit
Input High Voltage VIH 20 Vce V
Input Low Voltage VIL VSS - a3 08 V
Input leakage Current @ 5 25 V BERR,BGACK,BR,OTACK,
ClK, IPlO-IPL2, VPA lin - 25 ~A
HALT, RESET - 20
Three-State 10ff Statellnput Current@ 2 4 V/O 4 V AS, A l-A23, 00-015
ITSI - 20 ~A
FCO-FC2, lOS, RiIN, UOS, VMA
Output High Voltage IIOH = -400~A) E* VCC--O 75 -
AS, Al-A23, BG, 00-015 VOH V
FCO-FC2, lOS, R/W, UOS, VMA 24 -
Output Low Voltage
II0l = 16 mAl HALT - 05
II0l =32 mAl Al-A23, BG, FCO-FC2 - 05
VOL V
II0l = 350 mAl RESET - 05
1I0l = 53 mAl E, AS, 00-015, lOS, R/IN - 05
UOS, VMA
Power DISSipation (Clock Frequency=8 MHz) Po - 15 W
Capacitance IV In - 0 V, T A - 25'C, Frequency - 1 MHz) e ln 100 pF

* With external pullup resistor of 470 0

4-662
MC68000L4-MC68000L6-MC68000L8-MC68000L10

FIGURE 1 - RESET TEST LOAD FIGURE 2 - HALT TEST LOAD FIGURE 3 - TEST LOADS
+5V

1.. .
RO=7400

To."
Test

~I 130pF
~I 70PF
CL=130 pF
MMD7000
or Equivalent

(Includes all Parasltlcs)

- RL=60kOfor
i<S, A 1-A23, fiG, OO-D15, E
FC()'FC2, LDS, R/TN, UDS, VMA
°R=1 22 kO for A1-A23,fiG,
E, FC()'FC2

CLOCK TIMING (See Figure 4)

Characteristic Symbol
4 MHz 6 MHz 8MHz 10 MHz
MC68000L4 MC68000L6 MC68000L8 MC68000L10 Unit
Min Max Min Max Min Max Min Max
II
Frequency of Operation F 2.0 40 20 6.0 20 80 20 10.0 MHz
Cycle Time tcvc 250 500 167 500 125 500 100 500 ns
tCL 115 250 75 250 55 250 45 250
Clock Pulse Width ns
tCH 115 250 75 250 55 250 45 250
tCr 10 10 10 10
Rise and Fall Times ns
tCf - 10 - 10 10 - 10

FIGURE 4 - INPUT CLOCK WAVEFORM

~-------tcyc------i~

tCH

4-663
 MC68000L4· MC68000L6· MC68000L8· MC68000L10

AC ELECTRICAL SPECIFICATIONSIVCC= 50 Vdc ± 5% VSS = 0 Vdc T A = O'C to 70'C See Figures 5 and 61
4 MHz 6 MHz 8 MHz 10 MHz
Number Characteristic Symbol MCtBJOL4 MCtBJOL6 MCtBJOL8 MCtBJOL10 Unit
Min Max Min Max Min Max Min Max
1 Clock Period tcyc 250 500 167 500 125 500 100 500 ns
2 Clock Width Low tCL 115 250 75 250 55 250 45 250 ns
3 Clock Width High tCH 115 250 75 250 55 250 45 250 ns
4 Clock Fall Time tCf - 10 - 10 - 10 - 10 ns
5 Clock Rise Time tCr - 10 - 10 - 10 - 10 ns
6 Clock Low to Address tCLAV - 90 - 80 - 70 - 55 ns
6A Clock High to FC Valid tCHFCV - 90 - 80 - 70 - 80 ns
Clock High to Address Data High Impedance
7 tCHAlx - 120 - 100 - 80 - 70 ns
(Maximum)
8 Clock High to Address/ FC Invalid IMlnlmuml tCHAln 0 - 0 - 0 - 0 - ns
91 Clock High to AS, DS Low IMaxlmuml tCHSLx - 80 - 70 - 80 - 56 ns
10 Clock High to AS, DS Low IM,nlmuml tCHSLn 0 - 0 - 0 - 0 - ns
112 Address to AS, DS IReadl Low/AS Write tAVSL 55 - 35 - 30 - 20 -- ns
11A2 FC Valid to AS, DS, IReadl Low/ AS Write tFCVSL 80 - 70 - 60 - 50 - ns
121 Clock Low to AS, DS High tCLSH - 90 - 80 - 70 - 55 ns
132 AS, DS High to Address/FC Invalid tSHAZ 80 - 40 - 30 - 20 - ns
142,5 AS, DS Width Low IReadl/AS Write tSL 535 - 337 - 240 - 195 - ns
14A2 DS Width Low IWrltel - 285 - 170 - 115 - 95 - ns
152 - 180 - -

I
AS, DS Width High tSH 285 150 - 105 ns
16 Clock High 10 AS, DS High Impedance tCHSZ - 120 - 100 - 80 - 70 ns
172 AS, DS High to R/W High tSHRH 80 - 50 - 40 - 20 - ns
181 Clock High to R/W High IMaxlmuml tCHRHx - 90 - 80 - 70 - 80 ns
19 Clock High to R/W High IM,nlmuml tCHRHn 0 - 0 - 0 - 0 - ns
20 1 Clock High to R/W Low tCHRL - 90 - 80 - 70 - 60 ns
212 Address Valid to R/W Low tAVRL 45 - 25 - 20 - 0 - ns
21A2 FC Valid to R/W Low tFCVRL 80 - 70 - 80 - 50 - ns
222 R/W Low to DS Low IWrltel tRLSL 200 - 140 - 80 - 50 - ns
23 Clock Low to Data Out Valid tCLDO - 90 - 80 - 70 - 55 ns
252 DS High to Data Out Invalid tSHDO 80 - 40 - 30 - 20 - ns
262 Data Out Valid to DS Low IWrltel tDOSL 55 - 35 - 30 - 20 - ns
27 6 Data In to Clock Low I Setup T,mel tDICL 30 - 25 - 15 - 15 - ns
282 AS, DS High to DTACK High tSHDAH 0 240 0 180 0 120 0 90 ns
29 DS High to Data Invalid IHoid T,mel tSHDI 0 - 0 - 0 - 0 - ns
30 AS, DS High to BERR High tSHBEH 0 - 0 - 0 - 0 - ns
31 2,6 DTACK Low to Data In ISetup T,mel tDALDI - 180 - 120 - 90 - 65 ns
32 HALT and RESET Input TranSition Time tRHrf 0 200 0 200 0 200 0 200 ns
33 Clock High to BG Low tCHGL - 90 - 80 - 70 - 60 ns
34 Clock High to BG High tCHGH - 90 - 80 - 70 - 60 ns
35 BR Low to BG Low tBRLGL 15 30 15 30 15 30 15 30 Clk Per
36 BR High to BG High tBRHGH 15 30 15 30 15 30 15 30 Clk Per
37 BGACK Low to BG High tGALGH 15 30 15 30 15 30 15 30 Clk Per
36 BG Low to Bus High Impedance IW,th AS Hlghl tGLl - 120 - 100 - 80 - 70 ns
39 BG Width High tGH 15 - 15 - 15 - 15 - Clk Per
46 BGACK Width tBGL 15 - 15 - 15 - 15 - Clk Per
476 Asynchronous Input Setup Time tASI 30 - 25 - 20 - 20 - ns
48 BERR Low to DTACK Low INote 31 tBELDAL 50 - 50 - 50 - 50 - ns
53 Data Hold from Clock High tCHDO 0 - 0 - 0 - 0 - ns
55 R/W to Data Bus Impedance Change tRLDO 55 - 35 - 30 - 20 - ns
56 Halt/ RESET Pulse Width INote 41 tHRPW 10 - 10 - 10 - 10 - Clk Per

NOTES
1 For a loading capacitance of less than or equal to 500 picofarads, subtract 5 nanoseconds from the values given In these columns
2 Actual value depends on clock penod
3 If #47 IS satisfied for both Di'ACK and BERR, #48 may be 0 ns
4 After VCC has been applied for 100 ms
5 For T6E, BF4, and R9M mask sets #14 and #14A are one clock period less than the given number
6 If the asynchronous setup time (#47) requirements are satisfied, the DTACK low-ta-data setup time (#31) requirement can be Ignored The
data must only satisfy the data-In to clock-low setup time (#27) for the following cycle

4-664
MC68000L4- MC68000L6- MC68000LS- MC68000L 10

FIGURE 5 - READ CYCLE TIMING

51 52 53 54 55 56 57

AS HH--H--+-iI4l-------114~---_W.U,..-::"-----
--+./~-t---'

R/W

FCO-FC2

Asynchronous
Inputs
INote 11
--------~~.~~-+-+------~------+_H_--------
•
BERR/BR - - - - - - - - - - - - - - - - ,
INote 21

Data In - - - - - - - - - - - - - -

NOTE5

1 Setup time for the asynchronous mputs BGACK, IPLO-IPL2, and VPA guarantees their recognition at the next falling edge of the clock
2 "BR need fall at this time only In order to Insure being recognized at the end of this bus cycle
3 Timing measurements are referenced to and from a low voltage of 0 8 volts and a high voltage of 2 0 volts, unless otherwise noted

4-665
 MC68000L4e MC68000LSe MC68000L8e MC68000L 10

FIGURE 6 - WRITE CYCLE TIMING

so Sl S2 S3 S4 S5 S6 S7 so

ClK

-=
r-,t'~
~~6 ~ ~ n-r
A1-A23 ~ f-_ ~@ J
-1+ ~® -;.. ~ 14
1- ~-®
r+- I--@)
-
-
@-;.. r- f- Cc
J
~p- ~ ~ {V

J
I'-

- ~ f'L ®
@
"

I
I+@~ ~ +-@-

1- ~@ f-- t-@
R/IN

~ ~8- ~- f----- @
Data Out

FCO-FC2
@ f--
P -- ~@

Asynchronous
Inputs
)

®-~
f--1r-=:-;..~ ~ @
I-@ ®--
~-- f-@-
"!.- J

~ t-@ --@--------
Ie""-
1'5 J

@ f---
NOTE TIming measurements are referenced to and from a low voltage of 08 volts and a high voltage of 2 a volts, unless otherwise noted

4-666
MC68000L4-MC68000LS-MC68000L8-MC68000L 10

AC ELECTRICAL SPECIFICATIONS - BUS ARBITRATIONIVCC=5 0 Vdc ±5% vSS=O Vdc TA=OoC to 70°C See Figure 7)
4 MHz 6MHz 8MHz 10 MHz
Number Charactenstlc Symbol MC68000L4 MC68000LB MC68000LB MC68000Ll0 Unit
Min Max Min Max Min Max Min Max
33 Clock High to BG Low tCHGL - 90 - SO - 70 - 60 ns
34 Clock High to BG High tCHGH - 90 - SO - 70 - 60 ns
35 BR Low to BG Low tBRLGL 15 35 15 35 15 35 15 35 Clk Per
36 BR Hloh to BG Hloh tRR>-I(;1 15 30 15 30 15 30 15 30 Clk Per
37 BGACK Low to BG High tGALGH 15 30 15 30 15 30 15 30 Clk Per
36 BG Low to Bus High Impedance Iwlth AS High) tGLZ - 120 - 100 - SO - 70 ns
39 BG Width High tGH 15 - 15 - 15 - 15 - Clk Per
46 BGACK Width tBGL 15 - 15 - 15 - 15 - Clk Per

FIGURE 7 - AC ELECTRICAL WAVEFORMS - BUS ARBITRATION

These waveforms should only be referenced in regard to the edge-to-edge measurement of the timing specifications. They are not
intended as a functional description of the input and output signals. Refer to other functional descriptions and their related
diagrams for device operation.
II
Strobes
and R/IN - - - - - - - - - - '

'-----II@
--~----------------~

CLK

NOTES
Setup time for the asynchronous Inputs BERR. EiGACi(:, SR, DTACK, IPLO-IPL2, and VPA guarantees their recognitIOn at the next falling
edge of the ciock
2 Waveform measurements for all Inputs and outputs are specified at logic hlgh=2 0 volts, logic 10w=O 8 volts

4-667
 MC68000L4. MC68000L6. MC68000LS· MC68000L 10

SIGNAL DESCRIPTION

The following paragraphs contain a brief description of the Upper And Lower Data Strobes IUDS, LOS). These
Input and output signals A discussion of bus operation dur- Signals control the data on the data bus, as shown In Table
Ing the various machine cycles and operations IS also given 1 When the RiVii line IS high, the processor Will read from
the data bus as Indicated When the R/Vil line IS low, the
SIGNAL DESCRIPTION processor Will write to the data bus as shown
The input and output signals can be functionally organized
Into the groups shown In Figure 8. The following paragraphs TA8LE 1 - DATA STROBE CONTROL OF DATA BUS
provide a brief description of the signals and also a reference
(,f applicable) to other paragraphs that contain more detail ODS LOS R/W 08-015 00-07
about the function being performed. High High - No valid data No valid data
Valid data bits Valid data bits
Low Low High
FIGURE 8 - INPUT AND OUTPUT SIGNALS 8-15 0-7
Valid data bits
High Low High No va)ld data
Vc(2) Address 0-7
GNO(2) Bus A1-A23
Valid data bits
ClK Low High High No valid data
8-15
DO-015
Valid data bits Valid data bits
Low Low Low
8-15 0-7

O~"'
II
Valid data bits Valid data bits
High Low Low
FCO },",,,"
Bus
0-7* 0-7
processor{ FC1 Valid data bits Valid data bits
Status
Control Low High Low
FC2 8-15 8-15*
*These conditions are a result of current Implementation and may
M6S0D { }BUS Arbitration not appear on future deVices
Perrpheral
Control
Control

syste~{
Control
},nterrupt
Control
Data Transfer Acknowledge (DTACK). ThiS Input In-
dicates that the data transfer IS completed When the pro-
cessor recognizes DTACK dUring a read cycle, data IS
latched and the bus cycle terminated When DT ACK IS
recognized dUring a write cycle, the bus cycle IS terminated
An active transition of data transfer acknowledge,
ADDRESS BUS IAl THROUGH A23). This 23-blt,
DTACK, indicates the termination of a data transfer on the
unidirectional, three-state bus IS capable of addressing 8
bus
megawords of data. It provides the address for bus operation
If the system must run at a maximum rate determined by
dUring all cycles except Interrupt cycles DUring Interrupt
RAM access times, the relationship between the times at
cycles, address lines A 1, A2, and A3 provide Information
which DT ACK and DATA are sampled are Important
about what level Interrupt IS being serviced while address
All control and data lines are sampled dUring the
lines A4 through A23 are all set to a logic high
MC68000's clock high time The clock IS Internally buffered,
which results In some slight differences In the sampling and
DATA BUS 100 THROUGH 015), ThiS 16-blt, bidirec-
recognition of variOus Signals. MC68000 mask sets prior to
tIOnal, three-state bus is the general purpose data path It
CCl IR9M and T6E), allowed DTACK to be recognized as
can transfer and accept data In either word or byte length
early as S2 Ibus state 2), and all deVices allow BERR or
DUring an Interrupt acknowledge cycle, an external deVice
DT ACK to be recognized In S4, S6, etc, which terminates
supplies the vector number on data lines 00-07.
the cycle The DT ACK signal, like other control Signals, IS In-
ternally synchronized to allow for valid operation In an asyn-
ASYNCHRONOUS BUS CONTROL. Asynchronous data
chronous system. If the reqUired setup time (#47) IS met dur-
transfers are handled uSing the following control signals' ad-
Ing S4, DTACK Will be recognized dUring S5 and S6, and
dress strobe, read/write, upper and lower data strobes, and
data Will be captured dUring S6 The data must meet the re-
data transfer acknowledge These signals are explained in
qUired setup time 1#27).
the following paragraphs.
If an asynchronous control Signal does not meet the re-
qUired setup time, It IS pOSSible that It may not be recognized
Address Strobe lAS). ThiS Signal ,ndicates that there IS a dUring that cycle. Because of thiS, asynchronous systems
valid address on the address bus_
must not allow DT ACK to precede data by more than
parameter #31
Read/Write (R/W). ThiS Signal defines the data bus Asserting DTACK (or BERR) on the rising edge of a clock
transfer as a read or write cycle. The R/W Signal also works
(such as S4) after the assertion of address strobe Will allow a
in conjunction with the upper and lower data strobes as ex-
MC68000 system to run at ItS maximum bus rate If setup
plained in the following paragraph.
times #27 and #47 are guaranteed, #31 may be Ignored.

4-668
MC68000L4-MC68000L6-MC68000LS-MC68000L 10

BUS ARBITRATION CONTROL. These three signals form Halt (HALT). When thiS bidirectional line IS driven by an
a bus arbitration CirCUit to determine which device will be the external device, It will cause the processor to stop at the
bus master device completion of the current bus cycle. When the processor has
been halted uSing thiS Input, all control signals are inactive
Bus Request (BR). This Input IS wire ORed With all other and all three-state lines are put In their high-Impedance state
devices that could be bus masters This Input ,nd,cates to the Refer to BUS ERROR AND HALT OPERATION paragraph
processor that some other device desires to become the bus for additional information about the interaction between the
master halt and bus error signals
When the processor has stopped executing instructions,
Bus Grant (BG). This output ,nd,cates to all other potential such as In a double bus fault condition, the halt line IS driven
bus master devices that the processor will release bus con- by the processor to Indicate to external devices that the pro-
trol at the end of the current bus cycle cessor has stopped

Bus Grant Acknowledge (BGACK). This Input Indicates M6800 PERIPHERAL CONTROL. These control signals are
that some other device has become the bus master This used to allow the interfaCing of synchronous M6800
signal cannot be asserted until the following four conditions peripheral devices With the asynchronous MC68000 These
are met Signals are explained In the follOWing paragraphs
I a Bus Grant has been received
2. Address Strobe IS inactive which indicates that the Enable (E). ThiS Signal IS the standard enable Signal com-
microprocessor IS not uSing the bus mon to all M6800 type peripheral devices The period for thiS
output IS ten MC68000 clock periods (SIX clocks low, four
Data Transfer Acknowledge IS inactive which in-
clocks high!

•
dicates that neither memory nor peripherals are uSing
the bus
Valid Peripheral Address (VPA). ThiS Input indicates that
4 Bus Grant Acknowledge IS inactive which indicates the device or region addressed IS a M6800 family device and
that no other device IS stili claiming bus mastership that data transfer should be synchronized With the enable (E!
signal ThiS Input also indicates that the processor should
INTERRUPT CONTROL (lPLO, IPL1, IPl2). These Input use automatic vectoring for an Interrupt Refer to INTER-
pinS indicate the encoded Prlonty level of the device re- FACE WITH M6800 PERIPHERALS
questing an Interrupt Level seven IS the highest Priority
while level zero ,nd,cates that no Interrupts are requested Valid Memory Address (VMA). ThiS output IS used to in-
The least Significant bit IS given In IPLO and the most Signifi- dicate to M6800 peripheral devices that there IS a valid ad-
cant bit IS contained In IPL2. dress on the address bus and the processor IS synchrOnized
to enable. ThiS Signal only responds to a valid peripheral ad-
SYSTEM CONTROL. The system control Inputs are used dress (VPA) Input which Indicates that the peripheral IS a
to either reset or halt the processor and to Indicate to the M6800 family device
processor that bus errors have occurred The three system
control Inputs are explained In the following paragraphs. PROCESSOR STATUS (FCO, FC1, FC2). These function
code outputs indicate the state (user or supervisor) and the
Bus Error (BERR). This Input Informs the processor that cycle type currently being executed, as shown In Table 2
there IS a problem With the cycle currently being executed. The Information Indicated by the function code outputs IS
Problems may be a result of. valid whenever address strobe (AS! IS active
1 nonrespondlng devices
2. Interrupt vector number acquIsition failure TABLE 2 - FUNCTION CODE OUTPUTS
3. Illegal access request as determined by a memory FC2 FC1 FCO Cycle Type
management unit Low Low Low (Undefined, Reserved!
4 other application dependent errors Low Low High User Data
The bus error signal Interacts With the halt signal to deter- Low High Low User Program
mine If exception processing should be performed or the cur- Low High High (Undefined, Reserved!
rent bus cycle should be retried. High Low (Undefined, Reserved!
Low
Refer to BUS ERROR AND HALT OPERATION paragraph
High Low High Supervisor Data
for additional information about the interaction of the bus er-
ror and halt signals. High High Low Supervisor Program
High High High Interrupt Acknowledge
Reset (RESET), ThiS bidirectional signal line acts to reset
(,nit,ate a system Initialization sequence) the processor In
response to an external reset signal An Internally generated CLOCK (ClK)' The clock Input IS a TTL-compatible Signal
reset (result of a RESET Instruction) causes all external that IS Internally buffered for development of the Internal
devices to be reset and the internal state of the processor is clocks needed by the processor The clock Input shall be a
not affected. A total system reset (processor and external constant frequency
devices! IS the result of external HALT and RESET signals
applied at the same time Refer to RESET OPERATION SIGNAL SUMMARY. Table 3 IS a summary of all the
paragraph for additional Information about reset operation Signals discussed In the prevIous paragraphs.

4-669
 MC68000L4-MC68000L6-MC68000L8-MC68000L 10

TABLE 3 - SIGNAL SUMMARY

Signal Name Mnemonic InputlOutput Active State Three

State
Address Bus A1-A23 output high yes
Data Bus 00-015 Inputloutput high yes
Address Strobe liS output low yes
read-high
Read/Write R/W output yes
wrlte-Jow
Upper and Lower Data Strobes om, TIiS output low yes
Data Transfer Acknowledge i5TACK Input low no
Bus Request im Input low no
Bus Grant BG output low no
Bus Grant Acknowledge BGi\Ci( Input low no
Interrupt Priority Level ll'm, IPl1, iPI2 Input low no
Bus Error BERR Input low no
Reset RESET Inputloutput low no*
Halt HALT Inputloutput low no*
Enable E output high no
Valid Memory Address VMA output low yes
Valid Peripheral Address VPA Input low no

II Function Code Output

Clock
Power Input
Ground
FCQ, FC1, FC2
CLK
VCC
GND
output
Input
Input
Input
high
high
-
-
yes
no
-
-

*open drain

REGISTER DESCRIPTION AND DATA ORGANIZATION

The following paragraphs describe the registers and data Address registers do not support byte Sized operands
organization of the MC68000 Therefore, when an address register IS used as a source
operand, either the low order word or the entire long word
OPERAND SIZE operand IS used depending upon the operation size When
Operand sizes are defined as follows' a byte equals 8 bits, an address register IS used as the destination operand, the
a word equals 16 bits, and a long word equals 32 bits The entire register IS affected regardless of the operation size If
operand size for each Instruction IS either explicitly encoded the operation size IS word, any other operands are sign ex-
In the instruction or Implicitly defined by the Instruction tended to 32 bits before the operatIOn IS performed.
operation All explicit Instructions support byte, word or long
word operands Implicit instructions support some subset of
all three sizes STATUS REGISTER
The status register contains the Interrupt mask (eight
DATA ORGANIZATION IN REGISTERS levels available) as well as the conditIOn codes, extend (X),
The eight data registers support data operands of 1,8, 16, negative (N), zero (Z), overflow (V), and carry (C)' Addi-
or 32 bits. The seven address registers together with the ac- tional status bits ,nd,cate that the processor IS In a trace (T)
tive stack pOinter support address operands of 32 bits mode andlor In a supervisor (5) state.

DATA REGISTERS, Each data register IS 32 bits Wide. STATUS REGISTER

Byte operands occupy the low order 8 bitS, word operands
the low order 16 bitS, and long word operands the entire 32 System Byte User Byte
bits The least Significant bit IS addressed as bit zero; the
most Significant bit IS addressed as bit 31
When a data register IS used as either a source or destina-
tion operand, only the appropriate low-order portion IS
changed; the remaining high-order portion IS neither used
nor changed.
Interrupt
ADDRESS REGISTERS, Each address register and the Mask
stack pOinter IS 32 bits Wide and holds a full 32 bit address.

4·670
MC68000L4eMC68000L6eMC68000LSeMC68000L 10

DATA ORGANIZATION IN MEMORY The follOWing paragraphs explain the read, write, and
Bytes are individually addressable with the high order byte read-modlfy-wrlte cycles The ,nd,v,s,ble read-modlfy-wnte
having an even address the same as the word, as shown In cycle IS the method used by the MC68000 for Interlocked
Figure 9 The low order byte has an odd address that IS one multiprocessor commUnications
count higher than the word address Instructions and
multlbyte data are accessed only on word (even byte) boun-
NOTE
daries If a long word datum IS located at address n (n even),
then the second word of that datum IS located at address The terms assertion and negation Will be used extensively
n+2 ThiS IS done to aVOid confusion when dealing with a mixture
The data types supported by the MC68000 are bit data, in- of "active-low" and "active-high" Signals. The term assert or
teger data of 8, 16, or 32 bitS, 32-blt addresses and binary assertion IS used to ,nd,cate that a Signal IS active or true In-
coded decimal data Each of these data types IS put In dependent of whether that voltage IS low or high The term
memory, as shown In Figure 10 negate or negation IS used to indicate that a Signal IS inactive
or false.
BUS OPERATION
The following paragraphs explain control Signal and bus
operation dUring data transfer operations, bus arbitration, Reed Cycle. DUring a read cycle, the processor receives
bus error and halt conditions, and reset operation data from memory or a peripheral device The processor
reads bytes of data In all cases If the instruction speCifies a
DATA TRANSFER OPERATIONS. Transfer of data be- word (or double word) operation, the processor reads both
tween devices Involves the following leads. bytes When the Instruction speCifies byte operation, the
processor uses an Internal AO bit to determine which byte to

II
e Address Bus A 1 through A23
read and then Issues the data strobe required for that byte
e Data Bus DO through D15 For byte operations, when the AO bit equals zero, the upper
e Control Signals data strobe IS Issued When the AO bit equals one, the lower
The address and data buses are separate parallel buses used data strobe IS Issued. When the data IS received. the pi [J
to transfer data uSing an asynchronous bus structure In all cessor correctly positions It Internally
cycles, the bus master assumes responsibility for deskewing A word read cycle flow chart IS B,von In I ''It'''' 11 IIllyl"
all Signals It Issues at both the start and end of a cycle In ad- read cycle flow chart IS given In Figuro 17 110,1(1 eyel" tll!IIt1'1
dition, the bus master IS responsible for deskewing the IS given In Figure 13 Figure 14 details word "tid by to ",.. d ( y
acknowledge and data Signals from the slave device. cle operations

FIGURE 9 - WORD ORGANIZATION IN MEMORY

15 14 13 12 11 10 9 B 6 5 4 0
Word 00000o
Byte 00000o 1 Byte 000001
Word 1000002
Byte 000002 Byte 000003
7
{
Byte FFFFFE
wordrFFFE
Byte FFFFFF I

4·671
 MC68000L4- MC68000LS- MC68000L8- MC68000L 10

FIGURE 10 - DATA ORGANIZATION IN MEMORY

Bit Data
1 Byte=8 Bits

6 5 4 0

Integer Data
1 Byte = 8 Bits

15 14 13 12 11 10 9 8 5 0

Byte 0 Byte 1
M
1 " Byte 2
"'I
1 Word = 16 Bits
Byte 3

15 14 13 12 11 10 9 4 3 0

Word 0

"'I
1 M" Word 1

Word 2

I 15
MSB

-
14 13

-Long Word 0- -
12 11

-
10
1 Long Word = 32 Bits
9

- -
High Order
-- ---------
4 3 0

Low Order
LSB

- -Long Word 1- - - - - - - - - - - - - - - - - - - - -

- - Long Word 2 - - - - - - - - - - - - - - - - - - - - -

Addresses
1 Address = 32 Bits
15 14 13 12 11 10 9 B 4 3
MSB
High Order
--_~o---------------------
Low Order
LSB

- - Address 1 - - - - - - - - - - - - - - - - - - - - -

- - Address 2 - - - - - - - - - - - - - - - - - - - - -

MSB= Most Significant Bit

LS B = Least Significant Bit
DeCimal Data
2 Binary Coded DeCimal DlgltS= 1 Byte
15 14 13 12 11 10 9 8 6 5 4 3 2 o
MSD
BCD 0 BCD 1 LSD BCD 2 BCD 3

BCD 4 BCD 5 BCD 6 BCD 7

MSD= Most Significant DI91t
LSD = Least Significant Digit

4-672
MC68000L4- MC68000LS- MC68000LS- MC68000L 10

FIGURE 11 - WORD READ CYCLE FLOW CHART FIGURE 12 - BYTE READ CYCLE FLOW CHART

BUS MASTER SLAVE BUS MASTER SLAVE

Address Device
Address Device 11 Set R/Vii to Read
11 Set R/W to Read 21 Place Address on A l-A23
21 Place Address on Al-A23 31 Place Function Code on FCO-FC2
31 Place FunctIOn Code on FCO-FC2 41 Assert Address Strobe (ASI
41 Assert Address Strobe (ASI 51 Assert Upper Data Strobe (UDSI or Lower
51 Assert Upper Data Strobe (UDSI and Low- Data Strobe (LDSI (based on AOI
er Data Strobe (LDSI I
t
Input Data
11 Decode Address
21 Place Data on 00-07 or 08-015 (based on
11 Decode Address UDS or IDSI
21 Place Data on 00-015 31 Assert Data Transfer Acknowledge
3) Assert Data Transfer Acknowledge (DTACK)
(Di'ACK1

+ •
•
AcqUire Data
ACqUIre Data 11 Latch Data
rns

,
11 Latch Data 2) Negate UDS or
2) Negate iJI5S and TI5S 3) Negate AS
31 Negate AS

Terminate Cycle
Terminate Cycle
11 Remove Data from 00-07 or 08-015
11 Remove Data from 00-015
21 Negate Di'ACK
21 Negate DTACK

+
Start Next Cycle
t
Start Next Cycle

FIGURE 13 - READ AND WRITE CYCLE TIMING DIAGRAM

SO S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 w w w w S5 S6 S7
CLK

H H ==______________
__________
~
~=r
~r_
AS \ I \ r - - \______..Jr_
UDS \ I ~
IDS \ I \ r--\ I
R/Vii \ I
i5'TACK \ I \ I \ r
~~~~~r
08-015 ( ) ( ) {
00-07

FCO-2
=:=
::J<X
(
X __________________
>- ) ( )
~
(
~r

~- - -Read- - -J.- -Write - --.k- -Slow Read- -.I

4-673
 MC68000L4-MC68000LS-MC68000L8-MC68000L 10

FIGURE 14 - WORD AND BYTE READ CYCLE TIMING DIAGRAM

50 51 52 53 54 55 56 57 50 51 52 53 54 55 56 57 50 51 52 53 54 55 56 57
ClK

AO*

AS '--______I
Ui5S \ \ r-
lD5 \ r--\ I
RiW
DTACK \ r-\,-_ _~I \ {
D8-D15 ( ) (
>--
DO-D7 ) ( ~
FCO-2 =x'--_____ ---iX\.._ _ _ _ _ _~
X >-
*Internal 51gnal Only

•
j.. - -Word Read- -..\.- - Odd Byte Read- .j. -Even Byte Read - .j

Write Cycle_ DUring a write cycle, the processor sends BUS ARBITRATION_ Bus arbitration IS a technique used
data to memory or a peripheral device The processor writes by master-type devices to request, be granted, and
bytes of data m all cases If the Instruction specifies a word acknowledge bus mastership In ItS simplest form, It consists
operation, the processor writes both bytes When the m- of
structlon specifies a byte operation, the processor uses an 1 Asserting a bus mastership request
Internal AO bit to determine which byte to write and then 2 Receiving a grant that the bus IS available at the end
Issues the data strobe reqUIred for that byte For byte opera- of the current cycle
tions, when the AO bit equals zero, the upper data strobe IS
3 Acknowledging that mastership has been assumed.
Issued When the AO bit equals one, the lower data strobe IS
Issued. A word write cycle flow chart IS given m Figure 15 A Figure 20 IS a flow chart shOWing the detail Involved m a
byte wnte cycle flow chart IS given In Figure 16 Write cycle request from a smgle device Figure 21 IS a tlmmg diagram
tlmmg IS given m Figure 13 Figure 17 details word and byte for the same operations ThiS technique allows processmg of
write cycle operation bus requests dUring data transfer cycles.
The tlmmg diagram shows that the bus request IS negated
at the time that an acknowledge IS asserted ThiS type of
operation would be true for a system conslstmg of the pro-
cessor and one device capable of bus mastership In systems
Havmg a number of devices capable of bus mastership, the
Read-Modify-Write Cycle_ The read-modlfy-wrlte cycle bus request hne from each device IS wire ORed to the pro-
performs a read, modifies the data m the arithmetic-logic cessor In thiS system, It IS easy to see that there could be
Unit, and writes the data back to the same address In the more than one bus request bemg made The tlmmg diagram
MC68000 thiS cycle IS ,nd,v,s,ble m that the address strobe IS shows that the bus grant signal IS negated a few clock cycles
asserted throughout the entire cycle The test and set IT AS) after the transition of the acknowledge IBGACK) signal
Instruction uses thiS cycle to provide meanmgful com- However, If the bus requests are stili pending, the pro-
mUnication between processors m a multiple processor en- cessor will assert another bus grant Within a few clock cycles
VIronment. ThiS Instruction IS the only Instruction that uses after It was negated ThiS additional assertion of bus grant
the read-modlfy-wrlte cycles and smce the test and set m- allows exte",al arbitration CirCUitry to select the next bus
structlon only operates on bytes, all read-modlfy-wrlte cycles master before the current bus master has completed ItS re-
are byte operations. A read-modlfy-wrlte cycle flow chart IS qUirements. The following paragraphs proVide additional m-
given In Figure 18 and a timing diagram IS given In Figure 19. formation about the three steps m the arbitration process

4-674
MC68000L4- MC68000L6- MC68000LS- MC68000L 10

FIGURE 15 - WORD WRITE CYCLE FLOW CHART FIGURE 16 - BYTE WRITE CYCLE FLOW CHART

BUS MASTER SLAVE BUS MASTER SLAVE

Address Device
Address Device 11 Place Address on A 1-A23
11 Place Address on A 1-A23 21 Place Function Code on FCO-FC2
21 Place FunctIOn Code on FCO-FC2 31 Assert Address Strobe (ASI
31 Assert Address Strobe (ASI 41 Set RiiN to Write
51 Place Data on 00-07 or DB-D15 (according
41 Set R/W to Write
51 Place Data on 00-015 to AOI
61 Assert Upper Data Strobe (UDSI and 61 Assert Upper Data Strobe (UDSI or Lower
Lower Data Strobe (LDSI Data Strobe (LDSI (based on AOI

t
Input Data
~
11 Decode Address
11 Decode Address
21 Store Data on 00-07 If LOS IS asserted
21 Store Data on 00-015
Store Data on 08-015 If UDS IS asserted
31 Assert Data Transfer Acknowledge
31 Assert Data Transfer Acknowledge
IDTACKI

"~
11
21
31
41
Negate UDS and LOS
Negate AS
f
Terminate Output Transfer

Remove Data from 00-015

Set R/iN to Read
11
21
31
41
Terminate Output Transfer
Negate UDS and LOS
Negate AS
Remove Data from 00-07 or 08-015
Set R/iN to Read
•
Terminate Cycle
1
Terminate Cycle
11 Negate DT ACK 11 Negate DT ACK

f
Start Next Cycle
t
Start Next Cycle

FIGURE 17 - WORD AND BYTE WRITE CYCLE TIMING DIAGRAM

SO S1 S2 S3 S4 S5 S6 S7 SO 51 S2 S3 S4 S5 S6 S7 50 S1 S2 53 54 55 5657
ClK

AO*
--------~-=========~~~--------~
I
AS==:=:::;~-----;:~--
UD5---==~'----1----Jr--~======~----~~~----~
LOS -----.'----1 '--I
R/wF\ 1\ 1\ r
DTACK \ I \ I \ r
D8-D15==r-<~~~
DO-D7~ ) { }
(
)
) ( )
(
)

FCO-2 :X~ ______-'X X

*Internal Signal Only

I+----Word Wrlte---+--- Odd Byte Wrlte-~- Even Byte Wnte--..f

4-675
 MC68000L4eMC68000L6eMC68000L8eMC68000L 10

FIGURE 18 - READ-MODIFY-WRITE CYCLE FLOW CHART

8US MASTER SLAVE

Address Device
11 Place Address on A 1-A23 Input Data
21 Set RIW to Read 11 Decode Address
31 Assert Address Strobe IASI 21 Place Data on 00-07 or 08-015
41 Assert Upper Data Strobe IUDSI or Lower 31 Assert Data Transfer Acknowledge
Data Strobe IlDSI IDTACKI

1
AcqUire Data
11 latch Data
21 Negate UDS or lOS
31 Start Data ModiflcaMn Terminate Cycle
11 Remove Data from 00-07 or 08-015
21 Negate DTiiCi<

f
•
Start Output Transfer
11 Set R/W to Wnte
21 Place Data on 00-07 or 08-015 Input Data
31 Assert Upper Data Strobe IUDSI or lower 11 Store Data on 00-07 or 08-015
Data Strobe lLOSI 21 Assert Data Transfer Acknowledge
IDTACKI

T
Terminate Output Transfer
11 Negate UDS or lOS
21 Negate AS
31 Remove Data from 00-07 or 08-015
41 Set RIW to Read
Terrnlnate Cycle
11 Negate DTACK
I
Start Ne" Cycle
FIGURE 19 - READ-MODIFY -WRITE CYCLE TIMING DIAGRAM

SO 51 S2 53 54 5556 57 5859510511512513514515516517518519
ClK

Al-A23

AS \
UDS or lD5 --""'"'\ I \\..-----
R/W \
DTACK
\ I \
08-015 ( ) (
FCO-2 ::x'--___________________
1-<------------- ·Ind,v,s,ble Cycle' -----------+1

4-676
MC68000L4- MC68000L6- MC68000LS- MC68000L10

FIGURE 20 - BUS ARBITRATION CYCLE FLOW CHART Requesting the Bus. External deVices capable of becoming
bus masters request the bus by asserting the bus request
PROCESSOR REQUESTING DEVICE
(BRI signal ThiS IS a wire ORed signal (although It need not
Request the Bus be constructed from open collector devlcesl that ,nd,cates to
11 Assert Bus Request IBRI the processor that some external deVice reqUIres control of
I the external bus The processor IS effectIVely at a lower bus

f Priority level than the external deVice and Will relinqUIsh the

,
Grant Bus Arbitration
bus alter It has completed the last bus cycle It has started
When no acknowledge IS received before the bus request
11 Assert Bus Grant IBGI
I signal goes inactive, the processor will continue processing
when It detects that the bus request IS Inactive ThiS allows
ordinary processing to continue If the arbitration CIrcuitry
Acknowledge Bus Mastership responded to nOise Inadvertently
1) External arbitration determines next bus
master Receiving the Bus Grant. The processor asserts bus grant
2) Next bus master walts for current cycle to IBGI as soon as possible Normally thiS IS Immediately after
complete Internal synchrOnization The only exception to thiS occurs
31 Next bus master asserts Bus Grant when the processor has made an Internal deCISion to execute
Acknowledge I BGACKI to become new
the next bus cycle but has not progressed far enough Into
master
the cycle to have asserted the address strobe (ASI signal In
41 Bus master negates BR
I thiS case, bus grant Will not be asserted until one clock after

t address strobe IS asserted to ,nd,cate to external deVices that

II
a bus cycle IS being executed

,
Termln8te Arbitration The bus grant signal may be routed through a daiSY-
11 Negate BG land wall for BGACK to be chained network or through a specific Prlorlty·encoded net·
negatedl work. The processor IS not affected by the external method
of arbitration as long as the protocol IS obeyed
Acknowledgement of Mastership. Upon receiving a bus
Operate as Bus Master
grant, the requesting deVice walts until address strobe, data
11 Perform Data Transfers IRead and Wnte transfer acknowledge, and b~nt acknowledge are
cycles) according to the same rules the pro~
negated before Issuing Its own BGACK The negation of the
cessor uses ,

,
address strobe indicates that the previous master has com-
pleted ItS cycle, the negation of bus grant acknowledge In-
Release Bus MastershiP dicates that the prevIous master has released the bus (While
11 Negate BGACK address strobe IS asserted no deVice IS allowed to "break in-
to" a cycle.) The negation of data transfer acknowledge in-
dicates the prevIous slave has terminated ItS connection to
the prevIous master. Note that In some applications data
Re-Arbltrate or Resume Processor
transfer acknowledge might not enter Into thiS function.
Operation
General purpose deVices would then be connected such that

FIGURE 21 - BUS ARBITRATION CYCLE TIMING DIAGRAM

elK

AS
LDS/UDS

Riw

00-015

~________~\==~__-JI
BG _ _ _~\~---JI ,..._ _ _ _ _ _~\::::;---...JI
BGA"CKI \. / \.
~------~ ~-------------

Processor- ~ -DMA Devlce- -+I+- - -Processor- - ~ -DMA DeVice' - -

4-677
 MC68000L4eMC68000LSeMC68000LS·MC68000L10

they were only dependent on address strobe When bus been met (see Figure 23) The Input signal IS sampled on the
grant acknowledge IS Issued the device IS bus master until It failing edge of the clock and IS valid Internally after the next
negates bus grant acknowledge Bus grant acknowledge failing edge
should not be negated until after the bus cycle(s) IS (are) As shown In Figure 22, Input Signals labeled R and A are
completed Bus mastership IS terminated at the negation of Internally synchronIZed on the bus request and bus grant
bus grant acknowledge acknowledge pinS respectively The bus grant output IS
labeled G and the Internal three~state control Signal T If T IS
The bus request from the granted device should be drop~ true, the address, data, and control buses are placed In a
ped after bus grant acknowledge IS asserted If a bus request hlgh~lmpedance state when AS IS negated All Signals are
IS stili pending, another bus grant will be asserted within a shown In positive logiC (active high) regardless of their true
few clocks of the negation of bus grant Refer to Bus
active voltage level
ArbitratIOn Control sectIOn Note that the processor does not State changes (valid outputs) occur on the next rising
perform any external bus cycles before It re~asserts bus
edge after the Internal Signal IS valid
grant
A timing diagram of the bus arbitration sequence dUring a
BUS ARBITRATION CONTROL. The bus arbitratIOn con~ processor bus cycle IS shown In Figure 24 The bus arbltra~
tral unit In the MC68000 IS Implemented With a finite state tlOn sequence while the bus IS inactive (, e , executing mter-
machine A state diagram of thiS machine IS shown In Figure nal operations such as a multiply instruction) IS shown In
22 All asynchronous signals to the MC68000 are synchronlZ~ Figure 25
ed before being used Internally ThiS synchronIZation IS ac~ If a bus request IS made at a time when the M PU has
compllshed In a maximum of one cycle of the system clock, already begun a bus cycle but AS has not been asserted (bus
assuming that the asynchronous Input setup time (#47) has state SO), BG Will not be asserted on the next rising edge In~
stead, BG Will be delayed until the second rising edge follow~

•
mg It'S Internal assertion ThiS sequence IS shown In Figure
FIGURE 22 - STATE DIAGRAM OF MC68000 BUS 26
ARBITRATION UNIT
BUS ERROR AND HALT OPERATION. In a bus archltec~
lUre that reqUires a handshake from an external deVice, the
RA pOSSibility eXists that the handshake might not occur Since
different systems Will require a different maximum response
time, a bus error Input IS proVided. External circuitry must be
used to determine the duration between address strobe and
data transfer acknowledge before ISSUing a bus error Signal
When a bus error Signal IS received, the processor has two
options' initiate a bus error exception sequence or try runn~
Ing the bus cycle again

FIGURE 23 - TIMING RELATIONSHIP OF EXTERNAL

ASYNCHRONOUS INPUTS TO INTERNAL SIGNALS

Internal Signal Valid -------~l

External Signal Sampled + .

elK

BR IExternal1 ------~

RA
@
R= Bus Request Internal Bii IInternall
A = Bus Grant Acknowledge Internal
G= Bus Grant
T = Three-State Control to Bus Control LogiC
X= Don'l Care Asychronous
Input Delav*
* State machrne Will not change state If bus IS rn SO Refer to
BUS ARBITRATION CONTROL for additional Information *Thls delay time IS equal to parameter #33,tCHGl

4-678
MC68000L4- MC68000L6- MC68000L8- MC68000L 10

FIGURE 24 - BUS ARBITRATION DURING PROCESSOR BUS CYCLE

Bus three s t a t e d - - - - - - - , Bus released from three state and

BG asserted-------, Processor starts next bus cycle
BR valid Internal~ BGACK negated Internal~
BR samPled==:-l
BR asserted+ t
BGACK samPled:==;-l
BGACK negated + t
ClK
50 51 52 53 54 55 56 57 50 51 52 53 54 55 56 57 50 51
BR
iiG
\ I
\ I
BGACK \ I
A1-A23 ) ( >--C
AS \ r r--"\, r--
UD5 \ r r---"\ r--
L05 \ r r--"\, r--
==x

•
FCO-FC2 )C
R/W
DTACK '---l \ r--
00-015 (

- Processor
-I-
Alternate Bus Master
-I-
Procps<.,or
•

FIGURE 25 - BUS ARBITRATION WITH BUS INACTIVE

Bus released from three state and processor starts next bus c y c l e - - - - - - - - - - - - - - ,
BGACK n e g a t e d - - - - - - - - - - - - - - - - - - - - - - - - ,
BG asserted and bus three statedl---------,
BR valid Internall----------,

CLK
50 51 52 53 54 55 56 57 50 51 52 53 54
BR
BG
\ I
BGACK
\ I
\ /
A1-A23--< (
A5
U05
\ I ~
\ I \
~
lDS
\ I ~
FCO-FC2 =::x )
R/WI
OTACK
L-J '--
00-015
. Processor
(
.. \- Bus Inactive
-\ .. Alternate Bus Master • I• Processor _

4-679
 FIGURE 26 - BUS ARBITRATION DURING PROCESSOR BUS CYCLE SPECIAL CASE

BR,
8G
SO S1 S2 S3 S4 S5 S6 S7

/
SO S1 S2 S3 S4 S5 S6 S7 SO S1

8GACK
\ /
\ I
A1-A23 ) < >--C
AS
\ I' ~ r--
UOS
\ f' ~ r--
LOS
\ I' ~ r--

• FCO-FC3~
R/WI
OTACK

00-015

.. Processor
'---...J

- I-
Alternate Bus Master
(

-\-
\
Processor
r--
x=

Exception Sequence. When the bus error signal IS 3 Reading the bus error vector table entry
asserted, the current bus cycle IS terminated If BERR IS 4 Executing the bus error handler routine
asserted before the falling edge of S4, AS will be negated In
S7 In either a read or write cycle As long as BERR remains The stacking of the program counter and the status
asserted, the data and address buses will be In the hlgh- register IS the same as If an Interrupt had occurred Several
Impedance state When BER R IS negated, the processor will additional Items are stacked when a bus error occurs These
begin stacking for exceptIOn processing Figure 27 IS a timing Items are used to determine the nature of the error and cor-
diagram for the exception sequence The sequence IS com- rect It, If pOSSible. The bus error vector IS vector number two
posed of the following elements located at address $000008 The processor loads the new
program counter from this location A software bus error
1 StaCKing the program counter and status register handler routine IS then executed by the processor Refer to
2 Stacking the error information EXCEPTION PROCESSING for additional Information

4-680
MC68000L4· MC68000LS. MC68000L8. MC68000L 10

Re-Runmng the Bus Cycle. When, dUring a bus cycle, the the same address, the same function codes, the same data
processor receives a bus error Signal and the halt Pin IS being I for a write operatlonl, and the same controls The bus error
driven by an external device, the processor enters the re~run signal should be removed at least one clock cycle before the
sequence Figure 28 IS a timing diagram for re--runnlng the halt signal IS removeo
bus cycle
NOTE
The processor will not re-run a read-modlfy-wrlte cycle
The processor terminates the bus cycle, then puts the
ThiS restriction IS made to guarantee that the entire cycle
address and data output lines In the high-Impedance state runs correctly and that the write operation of a Test-and-Set
The processor remains "halted," and will not run another operation IS performed Without ever releasing AS If BERR
bus cycle until the halt signal IS removed by external logiC and HALT are asserted dUring a read-modlfy-wrlte bus cycle,
Then the processor will re-run the prevIous bus cycle uSing a bus error operation results

FIGURE 27 - BUS ERROR TIMING DIAGRAM

AS ~'- _ _ _ _ _ _ _ _ _ _ _--'/
\'-----
LOS "iJD5 - - - " " ' \ /,---- -----\
'-----

•
R/W
OTACK-------------------------------------
\
00.015::~::::::~(~~~~~~~~~~~~~~~~~~~::~
FCO·2
BERR
=J=::.=========::::::;:\ _______-----;
HAIT-------------~================~
I _ Initiate _ I _ _ 1_ Imtlate Bus
,.... Read~ - -Response Fallure- - - Bus Error Detection --~-----
Error Stacking

FIGURE 28 - RE-RUN BUS CYCLE TIMING INFORMATION

ClK
A1·A23

\ I \\..._____1
AS
LDS/UOS \ ,-------------------~\
I r----
Riw
DTACK
00·015 ( )
FCO·2 .:J( X
BERR
\ /
HALT \ /
~ - - Read- - ~- -- - - - Halt- - - - -- -t- -- Rerun- - - --+l

4-681
 MC68000L4- MC68000L6- MC68000L8- MC68000L 10

The processor terminates the bus cycle, then puts the ad- ThiS IS reqUired for correct performance of the re-run bus cy-
dress, data and function code output lines In the hlgh- cle operation
Impedance state The processor remainS "halted," and will
not run another bus cycle until the halt signal IS removed by While the processor IS honoring the halt request, bus
external logic Then the processor will re-run the prevIous arbitration performs as usual That IS, halting has no effect
bus cycle uSing the same address, the same function codes, on bus arbitration It IS the bus arbitration function that
the same data Ifor a write operatlonl, and the same controls removes the control signals from the bus
The bus error signal should be removed before the halt signal
IS removed The halt function and the hardware trace capability allow
the hardware debugger to trace Single bus cycles or Single in-
Halt Operation with No Bus Error. The halt Input signal to structions at a time These processor capabilities, along With
the MC68000 performs a Halt/ Run/Single-Step function In a a software debugging package, give total debugging fleXibili-
Similar fashion to the M6800 halt function The halt and run ty
modes are somewhat self explanatory In that when the halt
signal IS constantly actIVe the processor "halts" Idoes Oouble Bus Faults. When a bus error exception occurs,
nothlngl and when the halt signal IS constantly inactive the the processor will attempt to stack several words containing
processor "runs" Idoes something) information about the state of the machine If a bus error ex-
The Single-step mode IS derived from correctly timed tran- ception occurs during the stacking operation, there have
sitions on the halt signal Input It forces the processor to ex- been two bus errors In a row ThiS IS commonly referred to as
ecute a Single bus cycle by entering the "run" mode until the a double bus fault When a double bus fault occurs, the pro-
processor starts a bus cycle then changing to the "halt" cessor will halt Once a bus error exception has occurred,

•
mode Thus, the Single-step mode allows the user to pro- any bus error exception occurring before the execution of
ceed through land therefore debug) processor operations the next Instruction constitutes a double bus fault
one bus cycle at a time Note that a bus cycle which IS re-run does not constitute a
Figure 29 details the timing reqUired for correct Single-step bus error exception, and does not contribute to a double bus
operations Some care must be exercised to aVOid harmful fault Note also that thiS means that as long as the external
Interactions between the bus error signal and the halt pin hardware requests It, the processor will continue to re-run
when uSing the Single cycle mode as a debugging tool ThiS the same bus cycle
IS also true of Interactions between the halt and reset lines The bus error Pin also has an effect on processor operation
since these can reset the machine after the processor receives an external reset Input, The pro-
cessor reads the vector table after a reset to determine the
When the processor completes a bus cycle after recogniz-
address to start program execution If a bus error occurs
Ing that the halt signal IS active, most three-state signals are
while reading the vector table lor at any time before the first
put In the high-Impedance state These Include'
instruction IS executed), the processor reacts as If a double
1 address lines bus fault has occurred and It halts Only an external reset will
2 data lines start a halted processor.

FIGURE 29 - HALT SIGNAL TIMING CHARACTERISTICS

ClK

AS \ I \...___--.J

----~\~------~/r--------------------~\
LOS/UOS ________~.==========~.~ ______________________________~.==========~.Ir----
________
R/W

OTACK-::::;~;;;;;\;~~~~/~::::::::::::::::::::::::::::::::::::::::::::::::::==:::::~\~~~~;----
00-015 ) (>---
FCO·2 :::x x::::
RATI \~-----------------'I
~ -Read- - - -- +- -- -- Halt - - - -- + -- - Read - - - ~

4·682
MC68000L4- MC68000L6- MC68000LS- MC68000L 10

THE RELATIONSHIP OF DTACK, BERR, AND HALT

In order to properly control termination of a bus cycle for a may precede HALT on all except R9M and T6E < early mask
re-run or a bus error condition, DTACK, BERR, and HALT sets> which allows fully asynchronous assertlonl.
should be asserted and negated on the rising edge of the Table 4 details the resulting bus cycle termination under
MC68000 clock ThiS Will assure that when two signals are various combinations of control signal sequences The nega-
asserted Simultaneously, the required setup time (#471 for tion of these same control signals under several conditions IS
both of them Will be met dUring the same bus state shown In Table 5 (DTACK,S assumed to be negated normal-
ThiS, or some equivalent precaution, should be deSigned ly In all cases, for best results, both DTACK and BERR
external to the M C68000. Parameter #48 IS Intended to en- should be negated when address strobe IS negated I
sure thiS operation In a totally asynchronous system, and Example A: A system uses a watch-dog timer to ter-
may be Ignored If the above conditions are met minate accesses to un-populated address space The timer
The preferred bus cycle terminations may be summarized asserts DTACK and BERR Simultaneously after time-out
as follows (case numbers refer to Table 41 (case 41
Normal Termination: DTACK occurs first (case 11 Example B: A system uses error detection on RAM con-
Halt Termination: HALT IS asserted at same time, or tents. DeSigner may (al delay DTACK until data verified, and
precedes DTACK (no BERRI cases 2 and 3 return BER R and HALT Simultaneously to re-run error cycle
Bus Error Termination: BERR IS asserted In lieu of, at same (case 61, or If valid, return DTACK, (bl delay DTACK until
time, or preceding DT ACK (case 41, BER R negated at same data verified, and return BERR at same time as DTACK If
time, or after DT ACK data In error (case 41, (cl return DTACK poor to data verifica-
Re-Run Termination: HALT and BERR asserted at the tion, as described In prevIous section If data invalid, BERR IS
same time, or before DT ACK (cases 6 and 71 , HALT must be asserted (case llln next cycle Error-handling software must
negated at least 1 cycle after BERR (Case 5 indicates BERR know how to recover error cycle

TABLE 4 - i5TAIT 'SmA' 'FiArr ASSERTION RESULTS

I
Assertad on RiSing
Case Control
Edge of State Result
No. Signal _N _II!+
DTACK A S Normal cycle terminate and continue
1 BERR NA X
HALT NA X
DTACK A S Normal cycle terminate and halt Continue when HALT removed
2 BERR NA X
HALT A S
DTACK NA A Normal cycle terminate and halt Continue when HALT removed
3 BERR NA NA
HALT A S
DTACK X X Termmate and take bus error trap
4 BEAR A S
HALT NA NA
DTACK NA X R9M, T6E, BF4: Unpredictable results, no re-run, no error trap,
5 BERR A S usually traps to vector number 0
HALT NA A All others: term mate and re-run
DTACK X X Termmate and re-fun
6 BERR A S
HALT A S
DTACK NA X Terminate and re-run when HALT removed
7 BERR NA A
HALT A S
Legend
N - the number of the current even bus state (e 9 , S4, S6, etc)
A - signal IS asserted In thiS bus state
NA - signal IS not asserted In thiS state
X - don't care
S - signal was asserted In prevIous state and remains asserted In thiS state

TABLE 5 - BERR AND HALT NEGATION RESULTS

Conditions of Negated on Rising
Control
Termination in Edge of State Resuits - Next Cycle
Signal
Table A N N+2
BERR • or • Takes bus error trap
Bus Error
HALT • or
•
Re-run
BERR
HALT
•• or • Illegal sequence, usually traps to
vector number a

Re-run
BERR
HALT
• •
Re-runs the bus cycle

Normal
BERR
HALT
•• or •
May lengthen next cycle

Normal
BERR
HALT • or
• If next cycle IS started It Will
none be terminated as a bus error

4-683
 MC68000L4-MC68000LS-MC68000LS-MC68000Ll0

RESET OPERATION. The reset signal 15 a bidirectional registers are affected by the reset sequence.
signal that allows either the processor or an external signal to When a RESET sequence IS executed, the processor
reset the system Figure 30 15 a timing diagram for reset drives the reset pin for 124 clock pulses. In thiS case, the pro-
operations Both the halt and reset lines must be applied to cessor IS trying to reset the rest of the system. Therefore,
ensure total reset of the processor there IS nO effect on the Internal state of the processor All of
When the reset and halt lines are driven by an external the processor's Internal registers and the status register are
device, It 15 recognized as an entire system reset, Including unaffected by the execution of a RESET Instruction All ex-
the processor The processor responds by reading the reset ternal deVices connected to the reset line should be reset at
vector table entry (vector number zero, address $000000) the completion of the RESET Instruction
and loads It into the supervisor stack pOinter (SSP) Vector Asserting the Reset and Halt PinS for 10 clock cycles Will
table entry number One at address $000004 IS read next and cause a processor reset, except when VCC IS Initially ap-
loaded Into the program counter. The processor initializes plied to the processor In thiS case, an external reset must
the status register to an Interrupt level of seven No other be applied for 100 milliseconds

FIGURE 30 - RESET OPERATION TIMING DIAGRAM

ClK
Plus 5 Volts

VCC
t->l00Mllloseconds ~r---------------
RESET 1 I
HALT 1
~-*t<4

I Bus Cycles

NOTES
11 Internal start-up time
21 SSP High read In here
31 SSP low read In here
41 PC High read In here
51 PC low read ,n here
61 First Instruction fetched here
Bus State Unknown')¢OOO(

>---<
All Control Signals Inactive
Data Bus In Read Mode

PROCESSING STATES
The MC68000 IS always In one of three processing states The halted processing state 15 an indication of catastrophic
normal, exception, or halted The normal processing state 15 hardware failure For example, If dUring the exception pro-
that associated With instruction execution, the memory cessing of a bus error another bus error occurs, the pro-
of the bits In the supervisor portion of the status register are cessor assumes that the system IS unusable and halts Only
covered: the supervisor/user bit, the trace enable bit, and an external reset can restart a halted processor Note that a
the processor interrupt Priority mask. Finally, the sequence processor In the stopped state IS not In the halted state, nor
of memory references and actions taken by the processor On vice versa
exception conditions is detailed.
PRIVILEGE STATES
The MC68000 15 always In one of three processing states The processor operates In one of two states of priVilege
normal, exception, or halted. The normal processing state 15 the "user" state or the "supervisor" state The priVilege state
that assOCiated With Instruction executIOn; the memory determines which operations are legal, IS used by the exter-
references are to fetch instructions and operands, and to nal memory management deVice to control and translate ac-
store results. A speCial case of the normal state 15 the cesses, and 15 used to choose between the supervisor stack
stopped state which the processor enters when a STOP in- pOinter and the user stack pOinter In Instruction references
struction is executed. In thiS state, no further memory The priVilege state IS a mechanism for proViding secUrity In
references are made. a computer system Programs should access only their own
The exception processing state 15 associated With Inter- code and data areas, and ought to be restricted from access-
rupts, trap Instructions, tracing and other exceptional condi- mg mformatlon which they do not need and must not
tions. The exception may be internally generated by an In- modify.
struction or by an unusual condition arising dUring the ex- The priVilege mechanism prOVides security by allowmg
ecution of an instruction. Externally, exception processing most programs to execute m user state In thiS state, the ac-
can be forced by an Interrupt, by a bus error, or by a reset. cesses are controlled, and the effects on other parts of the
Exception processing is deSigned to proVide an effiCient con- system are limited The operatmg system executes In the
text switch 50 that the processor may handle unusual condi- supervisor state, has access to all resources, and performs
tions. the overhead tasks for the user state programs

4-684
MC68000L4· MC68000L6· MC68000LS. MC68000L 10

SUPERVISOR STATE. The supervISor state IS the higher TABLE 6 - REFERENCE CLASSIFICATION
state of privilege For Instruction execution, the supervlsm Function Code Output
state IS determined by the S-blt of the status register, If the Reference Class
FC2 FC1 FCO
S-blt IS asserted (hlghl, the processor IS In the supervisor
state All Instructions can be executed In the supervisor 0 0 0 (Unassigned)
state The bus cycles generated by instructions executed In 0 0 1 User Data
the supervisor state are classified as supervisor references 0 1 0 User Program
While the processor IS In the supervIsor privilege state, those 0 1 1 (Unassigned)
instructions which use either the system stack pOinter Im- 1 0 0 (Unassigned)
plicitly or address register seven expliCitly access the super- 1 0 1 Supervisor Data
Visor stack pOinter
1 1 0 Supervisor Program
All exception processing IS done In the supervisor state,
regardless of the setting of the S-blt The bus cycles 1 1 1 Interrupt Acknowledge
generated dUring exception processing are classified as
supervisor references All stacking operations dUring excep- EXCEPTION PROCESSING
tion processing use the supervisor stack pOinter
Before discussing the details of Interrupts, traps, and trac-
rng, a general description of exception processrng IS In order
USER STATE. The user state IS the lower state of
The processing of an exception occurs In four steps, With
privilege For instruction execution, the user state IS deter-
variations for different exception causes DUring the first
mined by the S-blt of the status register, If the S-blt IS
step, a temporary copy of the status register IS made, and
negated (Iowl, the processor IS executing instructions In the
the status register IS set for exception processing In the sec-
user state

•
ond step the exception vector IS determined, and the third
Most Instructions execute the same In user state as In the
step IS the saving of the current processor context In the
supervisor state However, some Instructions which have
fourth step a new context IS obtained, and the processor
Important system effects are made privileged User programs
SWitches to instruction processing
are not permitted to execute the STOP Instruction, or the
RESET instruction To ensure that a user program cannot EXCEPTION VECTORS. Exception vectors are memory
enter the supervIsor state except In a controlled manner, the locations from which the processor fetches the address of a
Instructions which modify the whole status register are routine which Will handle that exception All exception vec-
privileged To aid In debugging programs which are to be tors are two words rn length (Figure 311. except for the reset
used as operating systems, the move to user stack pornter vector, which IS four words All exception vectors lie In the
(MOVE USPI and move from user stack pOinter (MOVE from supervisor data space, except for the reset vector which IS In
USPI instructions are also privileged the supervisor program space A vector number IS an elght-
The bus cycles generated by an Instruction executed In bit number WhiCh, when multiplied by four, gives the
user state are classified as user state references ThiS allows address of an exception vector Vector numbers are
an external memory management device 10 translate the ad- generated Internally or externally, depending on the cause of
dress and to control access to protected portions of the ad- the exception In the case of Interrupts, dUring the Interrupt
dress space While the processor IS In the user privilege acknowledge bus cycle, a peripheral prOVides an B-blt vector
state, those instructions which use either the system stack number (Figure 321 to the processor on data bus lines DO
pOinter ImpliCitly, or address register seven explicitly, access through D7 The processor translates the vector number Into
the user stack pOinter a full 24-blt address, as shown In Figure 33 The mernory
layout for exception vectors IS given In Table 7
PRIVILEGE STATE CHANGES. Once the processor IS rn As shown In Table 7, the memory layout IS 512 words
the user state and executing Instructions, only exception long (1024 bytesl. It starts at address 0 and proceeds
processing can change the privilege state DUring exception through address 1023. ThiS proVides 255 unique vectors,
processrng, the current setting of the S-blt of the status some of these are reserved for TRAPS and other system
register IS saved and the S-blt IS asserted, putting the pro- functions Of the 255, there are 192 reserved for user Inter-
cessing In the supervisor state Therefore, when Instruction rupt vectors. However, there IS no protection on the first 64
execution resumes at the address speCified to process the entries, so user Interrupt vectors may overlap at the discre-
exception, the processor IS In the supervisor privilege state tion of the systems deSigner

REFERENCE CLASSIFICATION. When the processor KINDS OF EXCEPTIONS. Exceptions can be generated by
makes a reference, It claSSifies the krnd of reference being either Internal or external causes The externally generated
made, usrng the encoding on the three lunctlon code output exceptions are the interrupts and the bus error and reset re-
Irnes ThiS allows external translation of addresses, control of quests. The Interrupts are requests from peripheral deVices
access, and differentiation of speCial processor states, such for processor action while the bus error and reset Inputs are
as Interrupt acknowledge Table 6 lists the claSSification of used for access control and processor restart The Internally
references generated exceptions come from Instructions, or from ad-

4-685
 MC68000L4-MC68000L6- MC68000L8-MC68000L 10

FIGURE 31 - EXCEPTION VECTOR FORMAT

Word 0 New Program Counter IHlgh! AO=O, Al =0

Word 1 New Program Counter ILow! AO=O, Al = 1

FIGURE 32 - PERIPHERAL VECTOR NUMBER FORMAT

Ignored

Where
v7 IS the MSB of the Vector Number
vO IS the LSB of the Vector Number

FIGURE 33 - ADDRESS TRANSLATED FROM a-BIT VECTOR NUMBER

All Zeroes

I
TABLE 7 - EXCEPTION VECTOR ASSIGNMENT

Vector Address
Assignment
Number(s! Dec Hex Space
0 0 000 SP Reset· IMlal SSP
- 4 004 SP Reset· Initial PC
2 8 008 SO Bus Error
3 12 OOC SO Address Error
4 16 010 SO Illegal Instruction
5 20 014 SO Zero D,v,de
6 24 018 SO CH K Instruction
7 28 01C SO TRAPV Instruction
8 32 020 SO PriVilege Violation
9 36 024 SO Trace
10 40 028 SO line 1010 Emulator
11 44 02C SO Line 1111 Emulator
12· 48 030 SO IUnasslgned, reserved!
13" 52 034 SO IUnasslgned, reserved!
14· 56 036 SO IUnasslgned, reserved!
15 60 03C SO Unmltlallzed Interrupt Vector
16-23· 64 04C SO IUnasslgned, reserved!
95 05F -
24 96 060 SO SPUriOUS Interrupt
25 100 064 SO Levell Interrupt Autovector
26 '104 068 SO Level 2 Interrupt Autovector
27 108 06C SO Level 3 Interrupt Autovector
28 112 070 SO Level 4 Interrupt Autovector
29 116 074 SO Level 5 Interrupt Autovector
30 120 078 SO Level 6 Interrupt Autovector
31 124 07C SO Level 7 Interrupt Autovector
32-47 128 080 SO TRAP Instruction Vectors
191 OBF -
48-63· 192 OCO SO IUnasslgned, reserved!
255 OFF -
64-255 256 100 SO User Interrupt Vectors
1023 3FF -
·Vector numbers 12, 13, 14, 16 through 23 and 48 through 63 are reserv-
ed for future enhancements by Motorola. No user peripheral deVices
should be assigned these numbers.

4-686
MC68000L4- MC68000LS- MC68000LS- MC68000L 10

dress errors or tracing The trap (TRAPI, trap on overflow priVilege Violation Since only one Instruction can be ex-
ITRAPVI, check register against bounds (CHKI and divide ecuted at a time, there IS no Priority relation Within Group 2.
IDIVI instructions all can generate exceptions as part of their The Priority relation between two exceptions determines
Instruction execution In addition, Illegal instructions, word which IS taken, or taken first, If the conditions for both arise
fetches from odd addresses and privilege violations cause ex- Simultaneously Therefore, If a bus error occurs dUring a
ceptions Tracing behaves like a very high PriOrity, Internally TRAP instruction, the bus error takes precedence, and the
generated Interrupt after each instruction execution TRAP instruction processing IS aborted In another example,
If an Interrupt request occurs dUring the execution of an in-
EXCEPTION PROCESSING SEQUENCE. Exception pro- struction while the T-blt IS asserted, the trace exception has
cessing occurs In four Identifiable steps In the first step, an PriOrity, and IS processed first Before Instruction processing
Internal copy IS made of the status register. After the copy IS resumes, however, the Interrupt exception IS also processed,
made, the S-blt IS asserted, putting the processor Into the and instruction processing commences finally In the Inter-
supervisor privilege state Also, the T-blt IS negated which rupt handler routlr,e. A summary of exception grouping and
will allow the exception handler to execute unhindered by Priority IS given In Table 8
tracing For the reset and Interrupt exceptions, the Interrupt
priority mask IS also updated TABLE 8 - EXCEPTION GROUPING AND PRIORITY
In the second step, the vector number of the exception IS
Group Exception Processing
determined For Interrupts, the vector number IS obtained by
a processor fetch, classified as an Interrupt acknowledge Reset
Exception proceSSing beginS
0 Bus Error
For all other exceptions, Internal logic provides the vector Within two clock cycles
Address Error
number ThiS vector number IS then used to generate the ad-
dress of the exception vector Trace
The third step IS to save the current processor status, ex- Interrupt Exception proceSSing begins before

I
1
cept for the reset exception The current program counter Illegal the next Instruction
PriVilege
value and the saved copy of the status register are stacked
uSing the supervisor stack pOinter The program counter TRAP, TRAPV,
Exception processtrlg IS started by
2 CHK,
value stacked usually POints to the next unexecuted instruc- normal instruction execution
Zero DIVide
tlon, however for bus error and address error, the value
stacked for the program counter IS unpredictable, and may
be Incremented from the address of the instruction which EXCEPTION PROCESSING DETAILED DISCUSSION
caused the error Additional information defining the current Exceptions have a number of sources, and each exception
context IS stacked for the bus error and address error excep- has processing which IS peculiar to 11. The follOWing
tions paragraphs detail the sources of exceptions, how each
The last step IS the same for all exceptions The new pro- arises, and how each IS processed.
gram counter value IS fetched from the exception vector
The processor then resumes instruction execution. The in- RESET, The reset Input proVides the highest exception
struction at the address given In the exception vector IS level The processing of the reset signal IS deSigned for
fetched, and normal instruction decoding and execution IS system Initiation, and recovery from catastrophic failure.
started Any processing In progress at the time of the reset IS aborted
and cannot be recovered The processor IS forced Into the
MULTIPLE EXCEPTIONS. These paragraphs describe the supervisor state, and the trace state IS forced off The pro-
processing which occurs when multiple exceptions arise cessor Interrupt Priority mask IS set at level seven The vector
Simultaneously Exceptions can be grouped according to number IS Internally generated to reference the reset excep-
their occurrence and priority. The Group 0 exceptions are tion vector at location 0 In the supervisor program space.
reset, bus error, and address error These exceptions cause Because no assumptions can be made about the validity of
the instruction currently being executed to be aborted, and register contents, In particular the supervisor stack pOinter,
the execeptlon processing to commence Within two clock neither the program counter nor the status register is saved,
cycles The Group 1 exceptions are trace and Interrupt, as The address contained In the first two words of the reset ex-
well as the priVilege ViolatIOns and illegal Instructions These ception vector IS fetched as the Initial supervisor stack
exceptions allow the current instruction to execute to com- pOinter, and the address In the last two words of the reset
pletion, but preempt the execution of the next Instruction by exception vector IS fetched as the Initial program counter.
forCing exception processing to occur (privilege Violations Finally, Instruction execution IS started at the address in the
and Illegal Instructions are detected when they are the next program counter The power-up/restart code should be
instruction to be executedl The Group 2 exceptions occur as pOinted to by the Inllial program counter
part of the normal processing of Instructions The TRAP, The RESET instruction does not cause loading of the reset
TRAPV, CHK, and zero diVide exceptions are In thiS group vector, but does assert the reset line to reset external
For these exceptions, the normal execution of an instruction deVices. ThiS allows the software to reset the system to a
may lead to exception processing known state and then continue processing With the next in-
struction.
Group 0 exceptions have highest priority, while Group 2
exceptions have lowest PriOrity Within Group 0, reset has INTERRUPTS. Seven levels of Interrupt priorities are pro-
highest PriOrity, followed by bus error and then address er- Vided. DeVices may be chained externally Within interrupt
ror Within Group 1, trace has PriOrity over external inter- PriOrity levels, allOWing an unlimited number of peripheral
rupts, which In turn takes Prlonty over Illegal Instruction and devices to Interrupt the processor Interrupt PriOrity levels

4-687
 MC68000L4e MC68000L6e MC68000LSe MC68000Ll 0

are numbered from one to seven, level seven being the FIGURE 34 - INTERRUPT ACKNOWLEDGE SEQUENCE
highest Priority The status register contains a three-bit mask FLOW CHART
which indicates the current processor PriOrity, and Interrupts
PROCESSOR INTERRUPTING DEVICE
are inhibited for all Prlonty levels less than or equal to the
current processor pnonty
An Interrupt request IS made to the processor by encoding Request Interrupt
the Interrupt request level on the Interrupt request lines, a
zero indicates no Interrupt request Interrupt requests arriv-
Ing at the processor do not force Immediate exception pro-
cessing, but are made pending Pending Interrupts are
detected between Instruction executions If the Priority of
the pending Interrupt IS lower than or equal to the current
t
Grant Interrupt
1) Compare Interrupt level In status register
processor PriOrity, execution continues with the next instruc- and walt for current Instruction to complete
tlon and the Interrupt exception processing IS postponed 21 Place Interrupt level on AI, A2, A3
IThe recognition of level seven IS slightly different, as ex- 31 Set Rlw to read
plained In a following paragraph I 41 Set function code to Interrupt acknowledge
51 Assert address strobe IASI
If the Prlonty of the pending Interrupt IS greater than the
61 Assert lower data strobe IlDSI
current processor Prlonty, the exception processing se-
quence IS started First a copy of the status register IS saved, I
and the privilege state IS set to supervisor, tracing IS sup-
pressed, and the processor Priority level IS set to the level of
the 'nterrupt being acknowledged The processor fetches ProVide Vector Number
the vector number from the Interrupting deVice, classifYing 11 Place vector number of 00-07

r
the reference as an Interrupt acknowledge and displaYing the 21 Assert data transfer acknowledge IDTACKI
level number of the Interrupt being acknowledged on the ad-
dress bus If external logiC requests an automatic vectoring,

I the processor Internally generates a vector number which IS

determined by the Interrupt level number If external logiC In-
dicates a bus error, the Interrupt IS taken to be SpUriOUS, and
the generated vector number references the SpUriOUS Inter-
rupt vector The processor then proceeds With the usual ex-
AcqUire Vector Number
1) Latch vector number
21 Negate lOS
31 Negate AS
ceptlon processing, saving the program counter and status
register on the supervisor stack The saved value of the pro-
gram counter IS the address of the Instruction which would
have been executed had the Interrupt not been present The
content of the Interrupt vector whose vector number was
previously obtained IS fetched and loaded Into the program II Negate DTACK
counter, and normal Instruction execution commences In the
Interrupt handling routine A flow chart for the Interrupt
acknowledge sequence IS given In Figure 34, a timing
diagram IS given In Figure 35, and the Interrupt exception Start Interrupt Processing
timing sequence IS shown In Figure 36

FIGURE 35 - INTERRUPT ACKNOWLEDGE SEQUENCE TIMING DIAGRAM

last Bus Cycle of Instruction Stack lACK Cycle Stack and

I"
IRead or Wrltel \ PCl \ IVector Number Acqursrtlonl
.. orE ISSPI-l"*orE~--'-========-'----)-*,,~e--==':"':':=~-
"\_ Vector Fetch ' \

4-688
 FIGURE 36 - INTERRUPT EXCEPTION TIMING SEQUENCE

Last B us Cycle
of Instruction
(During Which
Interrupt Was
Recognized)
r---
Stack
PCl
ISSPI
- lACK
Cycle
(Vector Number
AcquIsItion)
r---
Stack
Status
(SSPI
r-
Stack
PCH
(SSPI
-
~
Read
Vector
High
IA16-A231
r-
Read
Vector
low
(AO-A151 - Fetch First Word
of Instruction
of Interrupt
Routine

Priority level seven IS a special case Level seven Interrupts PRIVILEGE VIOLATIONS. In order to prOVide system
cannot be inhibited by the Interrupt Priority mask, thus pro- security, various instructions are priVileged An attempt to
viding a "non-maskable Interrupt" capability An Interrupt IS execute one of the priVileged InstructIOns while In the user
generated each time the Interrupt request level changes from state will cause an exception The priVileged Instructions are

I
some lower level to level seven Note that a level seven Inter- STOP AND (word) Immediate to SR
rupt may stili be caused by the level comparison If the re- RESET EaR (word) Immediate to SR
quest level IS a seven and the processor Priority IS set to a
RTE OR (word) Immediate to SR
lower level by an Instruction
MOVE to SR MOVE USP
UNINITIALIZED INTERRUPT. An interrupting deVice
TRACING. To aid In program development, the MC68000
asserts VPA or provides an Interrupt vector dUring an inter-
Includes a faCility to allow Instruction by instruction tracing
rupt acknowledge cycle to the MC68000 If the vector
In the trace state, after each instruction IS executed an ex-
register has not been Initialized, the responding M68000
ception IS forced, allOWing a debugging program to monitor
Family peripheral will provide vector 15, the unltlallzed inter-
the execution of the program under test
rupt vector This provides a uniform way to recover from a
programming error The trace faCility uses the T -bit In the supervisor portIOn of
the status register If the T-blt IS negated (off), tracing IS
SPURIOUS INTERRUPT. If dUring the Interrupt acknowl- disabled, and Instruction execution proceeds from Instruc-
edge cycle no deVice responds by asserting DT ACK or VPA, tion to instruction as normal II the T-blt IS asserted (on) at
the bus error line should be asserted to terminate the vector the beginning of the execution of an Instruction, a trece ex-
acquIsition The processor separates the processing of this ception will be generated after the execution of that instruc-
error from bus error by fetching the SPUriOUS Interrupt vector tion IS completed II the Instruction IS not executed, either
Instead of the bus error vector The processor then proceeds because an Interrupt IS taken, or the instruction IS Illegal or
With the usual exception processing privileged, the trace exception does not occur The trace ex-
ception also does not occur If the instruction IS aborted by a
INSTRUCTION TRAPS. Traps are exceptIOns caused by reset, bus error, or address error exception II the Instruction
Instructions They anse either from processor recognttlon of IS Indeed executed and an Interrupt IS pending on comple-
abnormal conditions dUring instruction execution, or from tion, the trace exception IS processed before the Interrupt ex-
use of Instructions' whose normal behavior IS trapping ception If, dUring the execution of the instruction, an excep-
Some instructions are used speCifically to generate traps tion IS forced by that Instruction, the forced exception IS pro-
The TRAP Instruction always forces an exception, and IS cessed before the trace exception
useful for Implementing system calls for user programs The As an extreme Illustration of the above rules, conSider the
TRAPV and CHK Instructions force an exception If the user arrival of an Interrupt dUring the execution of a TRAP in-
program detects a runtime error. which may be an arithmetiC struction while tracing IS enabled First the trap exception IS
overflow or a subscript out of bounds processed, then the trace exception, and finally the Interrupt
The Signed divide (DIVS) and unSigned divide (DIVU) In- exception Instruction execution resumes In the Interrupt
structions will force an exception If a diVISion operation IS at- handler routine
tempted With a diVISor of zero
ILLEGAL AND UNIMPLEMENTED INSTRUCTIONS. il- BUS ERROR. Bus error exceptions occur when the exter-
legal Instruction IS the term used to refer to any of the word nallogIC;; requests that a bus error be processed by an excep-
bit patterns which are not the bit pattern of the first word of tion The current bus cycle which the processor IS making IS
a legal instruction DUring instruction execution, If such an then aborted Whether the processor was dOing instruction
Instruction IS fetChed, an Illegal instruction exception occurs or exception processing, that processing IS terminated, and
Word patterns With bits 15 through 12 equaling 1010 or the processor Immediately begins exception processing
1111 are distinguished as Unimplemented instructions and Exception processing for bus error follows the usual se-
separate exception vectors are given to these patterns to per- quence of steps The status register IS copied, the supervisor
mit effiCient emulation ThiS faCIlity allows the operating state IS entered, and the trace state IS turned off The vector
system to detect program errors, or to emulate number IS generated to refer to the bus error vector Since
Unimplemented instructions In software the processor was not between instructions when the bus er-

4-689
 MC68000L4- MC68000L6- MC68000L8-MC68000L 10

ror exception request was made, the context of the pro- Ing the exception processing for a bus error, address error,
cessor IS more detailed To save more of this context, addi- or reset, the processor IS halted As shown In Figure 38, an
tional information IS saved on the supervisor stack The pro- address error Will execute a short bus cycle followed by ex-
gram counter and the copy of the status register are of ception processing
course saved The value saved for the program counter IS ad-
vanced by some amount, two to ten bytes beyond the ad-
dress of the first word of the instruction which made the INTERFACE WITH M6800 PERIPHERALS
reference causing the bus error If the bus error occurred
dUring the fetch of the next instruction, the saved program Motorola'S extensive line of M6800 peripherals are directly
counter has a value In the vIcinity of the current Instruction, compatible with the MC68000 Some of these deVices
even If the current instruction IS a branch, a Jump, or a return that are particularly useful are
Instruction BeSides the usual Information, the processor MC6821 Peripheral Interface Adapter
saves ItS Internal copy of the first word of the instruction be-
Ing processed, and the address which was being accessed MC6840 Programmable Timer Module
by the aborted bus cycle SpecifiC Information about the ac- MC6843 Floppy Disk Controller
cess IS also saved whether It was a read or a Write, whether MC6845 CRT Controller
the processor was processing an instruction or not, and the MC6850 Asynchronous Communication Interface Adapter
classification displayed on the function code outputs when MC6852 Synchronous Serial Data Adapter
the bus error occurred The processor IS processing an In-
MC6854 Advanced Data Link Controller
struction If It IS In the normal state or processing a Group 2
exception, the processor IS not processing an Instruction If It MC68488 General Purpose Interface Adapter
IS processing a Group a or a Group 1 exception Figure 37 Il- To Interface the synchronous M6800 peripherals with the

•
lustrates how thiS information IS organIZed on the supervisor asynchronous MC68000, the processor modifies ItS bus cycle
stack Although thiS information IS not suffiCient In general to meet the M6800 cycle requirements whenever an M6800
to effect full recovery from the bus error, It does allow soft- deVice address IS detected ThiS IS pOSSible since both pro-
ware diagnosIs Finally, the processor commences Instruc- cessors use memory mapped I/O Figure 39 IS a flow chart of
lIOn processing at the address contained In the vector It IS the Interface operation between the processor and M6800
the responsibility of the error handler routine to clean up the deVices
stack and determine where to continue execution
If a bus error occurs dUring the exception processing for a DATA TRANSFER OPERATION
bus error, address error, or reset, the processor IS halted, Three Signals on the processor prOVide the M6800 Inter-
and all processing ceases ThiS Simplifies the detection of face They are enable (EI, valid memory address (VMAI,
catastrophic system failure, since the processor removes and valid peripheral address (V PAl Enable corresponds to
Itself from the system rather than destroy all memory con- the E or </>2 Signal In eXisting M6800 systems The bus fre-
tents Only the RESET pin can restart a halted processor quency IS one tenth of the Incoming MC68000 clock frequen-
ADDRESS ERROR. Address error exceptions occur when cy The timing of E allows 1 M Hz peripherals to be used With
the processor attempts to access a word or a long word an 8 MHz MC68000 Enable has a 60/40 duty cycle, that IS, It
operand or an Instruction at an odd address The effect IS IS low for SIX Input clocks and high for four Input clocks ThiS
much like an Internally generated bus error, so that the bus duty cycle allows the processor to do successive VPA ac-
cycle IS aborted, and the processor ceases whatever process- cesses on successive E pulses
Ing It IS currently dOing and begins exception processing M6800 cycle timing IS given In Figures 40 and 41 At state
After exception processing commences, the sequence IS the zero (Sal In the cycle, the address bus and function codes
same as that for bus error Including the information that IS are In the high-Impedance state One-half clock later. In state
stacked, except that the vector number refers to the address 1, the address bus and function code outputs are released
error vector Instead LikeWise, If an address error occurs dur- from the h,qh-,mpedance state

FIGURE'$l - SUPERVISOR STACK ORDER (GROUP 01

15 14 13 ·12 11 10 9 8 7 6 5 4 3 2 1 0
Lower Address /R/wll/N I Function Code

High
- - Access Address - - - - - - - - - - - - - - - - - - ------
Low

Instruction Register

Status Register

High
- - Program Counter - - - ------ -------------
Low
R/W (read/wrltel wnte=O, reed = 1 I/N "nstrucllon/notl Instructlon=O, not= 1

4·690
MC68000L4-MC68000L6-MC68000L8-MC68000L10

FIGURE 38 - ADDRESS ERROR TIMING

so S 1 S2 S3 S4 S5 S6 S7 SO S 1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 S5
ClK

A1-A23=:=======3~~:::=~::~=:~==~~~::~=:::==~~==::~~::========::~~~::==::~
,\8-, 1 ~ ,
UDS--------~,~-----,~~r_-_-_-_~_=_=_\~--------~~,:===~~r'-------------------~-=-=~'~---
lDS - - - - - - - - , •
, I'~
A/W) I'r-·-----"
DTACK - - - - - - - - - - - , '...._ _--'
••

D~D15--------------{==============:=J ..•
1""""1------ Read -------+\+------- I Approx 8 Clocks.. I""
~""ot-'-'-- Idle
- - - - - '.. Wnte Stack-----+j

Dunng state 2, the address strobe (AS) IS asserted to In-

dicate that there IS a valid address on the address bus. If the
bus cycle IS a read cycle, the upper and/or lower data
FIGURE 39 - M6800 INTERFACING FLOW CHART
PROCESSOR SLAVE I
,
Initiate Cycle
strobes are also asserted In state 2 If the bus cycle IS a wnte 11 The processor starts a normal Read or
cycle, the read/wnte (R/W) signal IS sWitched to low (wnte)
dunng state 2 One half clock later, In state 3, the wnte data Wnte cycle LI_ _ _ _ _ _- - .

IS placed on the data bus, and In state 4 the data strobes are
Issued to ,nd,cate valid data on the data bus
The processor now Inserts walt states until It recognizes Define M6800 Cycle
the assertion of VPA The VPA Input signals the processor 11 External hardware asserts Valid Penpheral
that the address on the bus IS the address of an M6800 Address IV PAl
deVice (or an area reserved for M6800 devlcesl and that the
bus should conform to the 1/>2 transfer charactenstlcs of the
M6800 bus Valid penpheral address IS denved by decoding
the address bus, conditioned by address strobe
After the recognition of VPA, the processor assures that SynchronIZe With Enable
the Enable (E) IS low, by waiting If necessary, and subse- 11 The processor mortltors Enable lEI until It IS
quently asserts VMA Valid memory address IS then used as low IPhase 11
part of the chip select equation of the penpheral ThiS en-
I
21 The processor asserts Valid Memory Ad-

'--------',
sures that the M6800 penpherals are selected and deselected dress IVMAI
at the correct time The penpheral now runs ItS cycle dunng
the high portion of the E signal Figures 40 and 41 depict the
best and worst case M6800 cycle timing ThiS cycle length IS
dependent stnctly upon when VPA IS asserted In relationship Transfer Data
to the E clock 11 The penpheral walts until E IS active and
Dunng a read cycle, the processor latches the penpheral then transfers the data
data In state 6 For all cycles, the processor negates the ad-

~
dress and data strobes one half clock cycle later In state 7,
and the Enable signal goes low at thiS time Another half
clock later, the address bus IS put In the high-Impedance
state Dunng a wnte cycle, the data bus IS put In the hlgh-
Impedance state and the read/write signal IS sWitched high Terminate Cycle
The penpheralloglc must remove VPA Within one clock after 11 The processor walts until E goes low IOn a
address strobe IS negated Read cycle the data IS latched as E goes
low Internallyl
DT ACK should not b~ asserted while VPA IS asserted 21 The processor negates VMA
Notice that the MC68000 'i7Mi'i. IS active low, contrasted With 31 The processor negates AS, UDS, and lDS
the active high M6800 VMA ThiS allows the processor to put
ItS buses In the high-Impedance state on DMA requests
Without Inadvertently selecting penpherals
t
Start Next Cycle

4-691
 • ~
n

~
~
FIGURE 40 - M6800 TIMING - BEST CASE
•
~
n

~
SO Sl S2 S3 S4 w w w w w w w w w w w S5 S6 S7 SO

CLK \. Jr \. I \. I + I + I \. I -+ I \. I \. I \. I -'!;: /I \. I
r-
0)

A1-A23 1>---< ) •
~
n
AS \

® ~
Ii)
~
f-@ ® •
~
m
CO
n

~
VPA
I\)

@)
VMA
r-
.-
@ 0
Data Out

Data In _________________________________________ _

NOTE This figure represents the best case M6800 timing where VPA falls before the third system clock cycle after the failing edge of E
 s:

FIGURE 41 - MC6800 TIMING - WORST CASE !

~
SO SI S2 .53 S4 w w w w w w w w w w w w w w w w w w w w w w w w w w w w 55 56 57 50 s:•

~
CLK

Al-A23 ---J L...--tl-- Ii

AS I IJ s:•
E
~If
...
m
VPA
s:
CD
Co)
mA

R/Vii
(Read)
®
!
r.....
o
Data In

(Jl5'S1 rns
Read

R/WWnt8

Data Out
@-1l b =J 1.-@
UDS/LDS
Wnte

•
 MC68000L4-MC68000L6-MC68000L8-MC68000L 10

INTERRUPT OPERATION
DUring an Interrupt acknowledge--El'..cle while the pro- there are SIX normal Interrupt vectors and one NMI type vec-
cessor IS fetching the vector, If VPA IS asserted, the tor. As With both the M6800 and the MC68000's normal vec-
MC68000 will assert VMA and complete a normal M6800 tored Interrupt, the Interrupt service routine can be located
read cycle as shown In Figure 42 The processor Will then use anywhere In the address space This IS due to the fact that
an Internally generated vector that IS a function of the inter- while the vector numbers are fixed, the contents of the vec-
rupt being serviced This process IS known as autovectorlng tor table entries are assigned by the user
The seven autovectors are vector numbers 25 through 31 Since VMA IS asserted dUring autovectorlng, the M6800
Ideclmall peripheral address decoding should prevent unintended ac-
This operates In the same fashion Ibut IS not restricted to) cesses.
the M6800 interrupt sequence. The basIc difference IS that

FIGURE 42 - AUTOVECTOR OPERATION TIMING DIAGRAM

ClK

A1-A3

A4-A23

AS
UOS

I
lOS

R/W

OTACK ~
08-015 ----<:::)-----------------
0~D7 ----<:::)----------------------------
FCO-2 X y 'C
IPlO-2

~~====~------~==~-­
L-.
VPA \ r\......
VMA \ I
~ ~r~I ____-t-- _ _ _ -Autovector Operatlon- _ _ _ _ ~
~ Cycle ---".. ~

4-694
MC68000L4- MC68000L6- MC68000L8- MC68000L 10

AC ELECTRICAL SPECIFICATIONS IVCC= 50 Vdc +

- 5%, VSS =0 Vdc T A =O'C to 70'C refer to Figures 30 and 311
4 MHz 6 MHz 8 MHz 10 MHz
Number Characteristic Symbol MC68000L4 MC68000L6 MC68000LB MC68000L10 Unit
Min Max Min Max Min Max Min Max
24 Clock High to R/W, VMA High Impedance tCHRZ - 120 - 100 - 80 - 70 ns
40 Clock Low to VMA Low tCLVML - 90 - 80 - 70 - 70 ns
41 Clock Low to E TransitIOn tCLC 100 85 70 55 ns
42 E Output Rise and Fall Time tErf - 25 - 25 - 25 25 ns
43 VMA Low to E High tVMLEH 325 - 240 - 200 - 150 - ns
44 AS, OS" High to VPA High tSHVPH 0 240 0 180 0 120 0 90 ns
45 E Low to AddressIVMAI FC Invalid tELAI 55 - 35 - 30 - 10 - ns
49 E Low to AS, OS Invalid tELSI -80 - -80 - -80 - -80 - ns
50 E Width High tEH 900 - 600 - 450 - 350 - ns
51 E Width Low tEL 1400 - 900 - 700 - 550 - ns
52 E Extended Rise Time tCIEHX 80 - 80 - 80 - 80 - ns
54 Data Hold from E Low IWrltel tELDOZ 60 - 40 - 30 - 20 - ns
23 Clock Low to Data Out Valid tCLDO - 90 - 80 - 70 - 55 ns
27 Data In to Clock Low ISetup Tlmel tDICL 30 - 25 - 15 - 15 - ns
47 Asynchronous Input Setup Time tASl 30 - 25 - 20 - 20 - ns

DATA TYPES AND ADDRESSING MODES

Five baSIC data types are supported Thllse data types are.
_ Bits
_ BCD Digits 14-blts)
_ Bytes IB-blts)
TABLE 9 -
Mode
Register Direct Addressing
Data Register Direct
Address Register Direct
Absolute Data Addressing
ADDRESSING MODES

EA=Dn
EA=An
Generation •
Absolute Short EA= INext Wordl
_ Word 116-blts) Absolute Long EA= INext Two Wordsl
_ Long Words 132-bits) Program Counter Relative Addressing
In addition, operations on other data types such as memory Relative with Offset EA=IPCI+d16
addresses, status word data, etc, are proVided for In the in- Relative with Index and Offset EA=IPCI+IXn)+ds
struction set Register Indirect Addressing
Register Indirect EA= IAnl
Postlncrement Register Indirect EA=IAnl, An-An+N
Predecrement Register Indirect An-An-N, EA=IAnl
Register Indirect with Offset EA = IAnl + d16
The 14 addreSSing modes, shown In Table 9, Include SIX
Indexed Register Indirect with Offset EA= IAnl+ IXnl+ dS
baSIC types
_ Register Direct Immediate Data Addressing
Immediate DATA=Next Wordlsl
_ Register Indirect QUick Immediate Inherent Data
_ Absolute
Implied Addressing
_ Immediate Implied Register EA= SR, USP, SP, PC
_ Program Counter Relative NOTES:
- Implied EA = Effective Address de = Eight-bit Offset
An = Address Register Idlsplacement!
Included In the register indirect addreSSing modes IS the
On = Data Register d16 = Sixteen-bit Offset
capability to do postlncrementlng, predecrementlng, offset-
Xn = Address or Data Register used Idlsplacementl
ting and IndeXing. Program counter relative mode can also
as Index Register N = 1 for Byte, 2 for
be modified via IndeXing and offsetting
SR = Status Register Words and 4 for Long
PC = Program Counter Words
I I = Contents of - = Replaces

4-695
 INSTRUCTION SET OVERVIEW
long words and most Instructions can use any of the 14 ad-
The MC68000 instruction set IS shown In Table 10. Some dressing modes. Combining Instruction types, data types,
additional instructions are Variations, or subsets, of these
and addressing modes, over 1000 useful Instructions are pro-
and they appear In Table 11. Special emphasIs has been given
vided These instructions Include signed and unsigned
to the Instruction set's support of structured high-level
multiply and divide, "quick" arithmetic operations, BCD
languages to facIlitate ease of programming. Each instruc-
arithmetic and expanded operations (through trapsl
tion, with few exceptions, operates on bytes, words, and

TABLE 10 - INSTRUCTION SET

Mnemonic Description Mnemonic Description Mnemonic Description

ABCD Add Decimal with Extend EOR Exclusive Or PEA Push Effective Address
ADD Add EXG Exchange Registers RESET Reset External Devices
AND Logical And EXT Sign Extend ROL Rotate Left without Extend
ASL Arithmetic Shift Left JMP Jump ROR Rotate Right without Extend
ASR Arithmetic Shift Right JSR Jump to Subroutine ROXL Rotate Left with Extend
BCC Branch ConditIOnally LEA Load Effective Address ROXR Rotate Right with Extend
BCHG 8,t Test and Change LINK Link Stack RTE Return from Exception
BCLR Bit Test and Clear LSL Logical Shift Left RTR Return and Restore
BRA Branch Always LSR Logical Shift Right RTS Return from Subroutine
BSET Bn Test and Set MOVE Move SBCD Subtract Decimal With Extend

I
BSR Branch to Subroutine MOVEM Move Multiple Registers SCC Set Conditional
BTST Bit Test MOVEP Move Penpheral Data STOP Stop
CHK Check Register Against Bounds MULS Signed Multiply SUB Subtract
CLR Clear Operand MULU Unsigned Multiply SWAP Swap Data Register Halves
CMP Compare NBCD Negate Decimal With Extend TAS Test and Set Operand
DBCC Test Condition, Decrement and NEG Negate TRAP Trap
Branch NOP No Operation TRAPV T rap on Overflow
DIVS Signed D,v,de NOT One's Complement TST Test
DIVU Unsigned DIvide OR Logical Or UNLK Unlink

TABLE 11 - VARIATIONS OF INSTRUCTION TYPES

Instruction Instruction
Variation Description Variation Description
Type Type
ADD ADD Add MOVE MOVE Move
ADDA Add Address MOVEA Move Address
ADDQ Add QUick MOVEQ Move QUick
ADDI Add Immediate MOVE from SR Move from Status Register
ADDX Add With Extend MOVE to SR Move to Status Register
AND AND Logical And MOVE to CCR Move to Condition Codes
ANDI And Immediate MOVE USP Move User Stack POinter

CMP CMP Compare NEG NEG Negate

CMPA Compare Address NEGX Negate With Extend
CMPM Compare Memory OR OR Logical Or
CMPI Compare ImmedIate ORI Or Immediate
EOR EOR ExclUSive Or SUB SUB Subtract
EORI ExclUSive Or Immediate SUBA Subtract Address
SUBI Subtract Immediate
SUBQ Subtract QUick
SUBX Subtract with Extend

4-696
M C68000L4. MC68000L6· MC68000LS. MC68000L 10

The following paragraphs contain an overview of the form The multiply and diVide operations are available for Signed
and structure of the MC68000 Instruction set The Instruc- and unSigned operands uSing word multiply to produce a
tions form a set of tools that Include all tne machine func- long word product, and a long word diVidend With word
tions to perform the follOWing operations diVisor to produce a word quotient With a word remainder
Data Movement Multlpreclslon and mixed size arithmetiC can be ac-
Integer ArithmetiC complished uSing a set of extended instructions These In-
structions are add extended IADDX), subtract extended
Logical
(SUBX), sign extend (EXT), and negate binary With extend
Shift and Rotate (NEGX)
Bit Manipulation A test operand ITST) Instruction that Will set the condition
Binary Coded Decimal codes as a result of a compare of the operand With zero IS
Program Control also available Test and set ITAS) IS a synchronization In-
struction useful In multiprocessor systems Table 13 IS a sum-
System Control
mary of the Integer arithmetiC operations
The complete range of Instruction capabilities combined
With the flexible addressing modes described previously pro-
vide a very flexible base for program development TABLE 12 - DATA MOVEMENT OPERATIONS
Instruction Operand Size Operation
ADDRESSING
EXG 32 Rx-Ry
Instructions for the MC68000 contain two kinds of infor-
LEA 32 EA-An
mation the type of function to be performed, and the loca-
tion of the operand lsi on which to perform that function An-SP@-
LINK - SP-An

II
The methods used to locate laddressl the operand lsi are ex-
plained In the following paragraphs SP+d-SP
Instructions specify an operand location In one of three MOVE 8,16,32 IEAls-EAd
ways lEAl-An, On
MOVEM 16,32
Register Specification - the number of the register IS An,On-EA
given In the register field of the instruction lEAl-On
MOVEP 16,32
Effective Address - use of the different effective On-EA
address modes MOVEa 8 #xxx- On
ImpliCit Reference - the definition of certain Instruc- PEA 32 EA-SP@-
tions Implies the use of specific registers On(31 16]- On[15 0]
SWAP 32

DATA MOVEMENT OPERATIONS UNLK - S:~;~An

The baSIC method of data acquIsition (transfer and NOTES
storagel IS provided by the move (MOVEI Instruction The s=SQurce @ - = Indirect With predecrement
move Instruction and the effective addreSSing modes allow d == destinatIon @ + == Indirect With post decrement
both address and data manipulation Data move Instructions [ ]= bit numbers
allow byte, word, and long word operands to be transferred
from memory to memory, memory to register, register to INSTRUCTION FORMAT
memory, and register to register Address move Instructions Instructlons are from one to five words In length, as
allow word and long word operand transfers and ensure that shown In Figure 43 The length of the Instruction and the
only legal address manipulations are executed In addition to operation to be performed IS speCified by the first word of
the general move Instruction there are several special data the Instruction which IS called the operation word The re-
movement Instructions move multiple registers IMOVEMI, maining words further speCify the operands These words
move peripheral data (MOVEPI, exchange registers (EXGI, are either Immediate operands or extensions to the effective
load effective address (LEAl, push effective address (PEAl, address mode specified In the operation word
link stack (LINK), unlink stack IUNLK), and move qUick
(MOVEO) Table 12 IS a summary of the data movement PROGRAM/DATA REFERENCES
operatIons The MC68000 separates memory references Into two
classes: program references, and data references Program
INTEGER ARITHMETIC OPERATIONS references, as the name Implies, are references to that sec-
The anthmetlc operations Include the four baSIC opera- tion of memory that contains the program being executed.
tions of add (ADD), subtract (SUB), multiply IMULI, and Data references refer to that section of memory that contains
diVide IDIV) as well as arithmetiC compare (CMP), clear data. Generally, operand reads are from the data space. All
ICLR), and negate (NEG) The add and subtract instructions operand wntes are to the data space.
are available for both address and data operations, With data
operations accepting all operand sizes Address operations REGISTER SPECIFICATION
are limited to legal address size operands (16 or 32 bits!. The register field Within an Instruction speCifies the
Data, address, and memory compare operations are also register to be used, Other fields Within the instruction speCify
available The clear and negate Instructions may be used on whether the register selected is an address or data register
all sizes of data operands and how the register IS to be used.

4·697
 MC68000L4-MC68000LS-MC68000LS-MC68000L 10

TABLE 13 - INTEGER ARITHMETIC OPERATIONS EFFECTIVE ADDRESS

Instruction Operand Size Operation Most Instructions specdy the location of an operand by us-
Ing the effective address field In the operatIOn word For ex-
8,16,32 Dn+IEAI-Dn
IEAI+Dn-EA ample, Figure 44 shows the general format of the single
ADD effective address InstructIOn operatIOn word The effective
lEAl + 'xxx - EA
16,32 An+IEAI-An address IS composed of two 3-blt fields the mode field, and
the register field The value In the mode field selects the dif-
8,16,32 Dx+ Dy+X- Dx
ADDX ferent address modes The register field contains the number
16,32 Ax@-Ay@-+X-Ax@
of a register
CLR 8,16,32 O-EA
The effective address field may require addltlonallnforma-
8,16,32 Dn-IEAI
tlon to fully speCify the operand. ThiS additional Information,
lEAl - 'xxx called the effective address extenSion, IS contained In the
CMP
Ax@+-Ay@+
following word or words and IS conSidered part of the in-
16,32 An- lEAl
struction, as shown In Figure 43 The effective address
DIVS 32+16 Dn/IEAI-Dn
modes are grouped Into three categories register direct.
DIVU 32+16 Dn/IEAI-Dn memory addressing, and speCial
8-16 IDn18-Dn16
EXT
16-32 IDn116- Dn32 REGISTER DIRECT MODES. These effective addressing
MULS 16"16-32 Dn"IEAI-Dn modes speCify that the operand IS In one of the 16 multifunc-
MULU 16"16-32 Dn"IEAI- Dn tion registers
NEG 8,16,32 O-IEAI-EA
Data Register Direct, The operand IS In the data register
NEGX 8,16,32 O-IEAI-X-EA

I
speCified by the effective address register field
8,16,32 Dn-IEAI-Dn
IEAI-Dn-EA
SUB Address Register Direct. The operand IS In the address
IEAI-#xxx-EA
16,32 An-lEAl-An register speCified by the effective address register field

Dx- Dy- X- Dx
SUBX 8,16,32 MEMORY ADDRESS MODES. These effective address-
Ax@--Ay@- -X-Ax@
Ing modes speCify that the operand IS In memory and prOVide
TAS 8 IEAI-0,1-EA[7J
the speCifiC address of the operand
TST 8,16,32 IEAI-O
Address Register Indirect. The address of the operand IS In
NOTE. [ J= bit number the address register speCified by the register field The
reference IS claSSified as a data reference With the exception
of the Jump and Jump to subroutine Instructions

FIGURE 43 - INSTRUCTION FORMAT

15 14 13 12 11 10 9 8 6 5 4 3 o
Operation Word
IFirst Word SpeCifies Operation and Modesl
Immediate Operand
IIf Any, One or Two Words I
Source Effective Address ExtenSion
IIf Any, One or Two Wordsl
Destination Effective Address ExtenSion
IIf Any, One or Two Wordsl

FIGURE 44 - SINGLE-EFFECTIVE-ADDRESS
INSTRUCTION OPERATION WORD GENERAL FORMAT

4-698
MC68000L4- MC68000LS- M C68000L8- MC68000L 10

Address Register Indirect With Postincrement. The extension word The reference IS claSSified as a program
address of the operand IS In the address register specified by reference
the register field After the operand address IS used. It IS in-
cremented by one. two. or four depending upon whether the Program Counter With Index. ThiS address mode requires
size of the operand IS byte. word. or long word If the one word of extension ThiS address IS the sum of the
address register IS the stack pOinter and the operand size IS address In the program counter. the sign-extended displace-
byte. the address IS Incremented by two rather than one to ment Integer In the lower eight bits of the extension word.
keep the stack pOinter on a word boundary The reference IS and the contents of the Index register The value In the pro-
classified as a data reference gram counter IS the address of the extension word ThiS
reference IS classified as a program reference
Address Register Indirect With Predecrement. The
address of the operand IS In the address register specified by Immediate Data. ThiS address mode requires either one or
the register field Before the operand address IS used. It IS two words of extenSion depending on the size of the opera-
decremented by one. two. or four depending upon whether tion
the operand size IS byte. word. or long word If the address Byte operation - operand IS low order byte of exten-
register IS the stack pOinter and the operand size IS byte. the sion word
address IS decremented by two rather :han one to keep the
Word operation - operand IS extenSion word
stack pOinter on a word boundary The reference IS classified
Long word operation - operand IS In the two extenSion
as a data reference
words. high-order 16 bits are In the first extenSion
word. low-order 16 bits are In the second extension
Address Register Indirect With Displacement. This
word
address mode requires one word of extension The address
of the operand IS the sum of the address In the address

II
Condition Codes or Status Register. A selected set of In-
register and the sign-extended 16-blt displacement Integer In
structions may reference the status register by means of the
the extension word The reference IS classified as a data
effective address field These are
reference with the exception of the Jump to subroutine In-
structions ANDI to CCR
ANDI to SR
Address Register Indirect With Index. This address mode EaRl to CCR
requires one word of extenSion The address of the operand EaRl to SR
IS the sum of the address In the address register. the slgn- ORI to CCR
extended displacement Integer In the low order eight bits of ORI to SR
the extension word. and the contents of the Index register
The reference IS claSSified as a data reference with the excep- EFFECTIVE ADDRESS ENCODING SUMMARY
tion of the Jump and Jump to subroutine Instruclions Table 14 IS a summary of the effective addreSSing modes
discussed In the prevIous paragraphs
SPECIAL ADDRESS MODE. The special address modes
use the effective address register field to speCify the special
TABLE 14 - EFFECTIVE ADDRESS ENCODING SUMMARY
addreSSing mode Instead of a register number
Addressing Mode Mode Register
Absolute Short Address. This address mode requires one
Data Register Direct 000 register number
word of extension The address of the operand IS the exten-
sion word The 16-blt address IS sign extended before It IS
Address Register Direct 001 register number
used The reference IS classified as a data reference With the Address Register Indirect 010 register number
exception of the Jump and Jump to subroutine instructions Address Register Indirect With
Postlncrement 011 register number
Absolute Long Address. This address mode requires two Address Register Indirect With
words of extension The address of the operand IS developed Predecrement 100 register number
by the concatenation of the extension words The high-order Address Register Indirect with
part of the address IS the first extension word. the low-order Displacement 101 register number
part of the address IS the second extenSion word The Address Register Indirect With
reference IS classified as a data reference With the exceplion Index 110 register number
of the ,ump and Jump to subroutine instructions Absolute Short 111 000
Absolute Long 111 001
Program Counter With Displacement. This address mode
Program Counter with
requires one word of extension The address of the operand
Displacement 111 010
IS the sum of the address In the program counter and the
sign-extended 16-blt displacement Integer In the extension Program Counter With Index 111 011
word The value In the program counter IS the address of the Immediate 111 100

4-699
 MC68000L4- MC68000LS- MC68000L8- MC68000L 10

IMPLICIT REFERENCE TABLE 16 - SHIFT AND ROTATE OPERATIONS

Some instructions make ImpliCit reference to the program
counter IPC), the system stack pOinter ISP), the supervIsor Instruc.. Operand
stack pOinter ISSP), the user stack pOinter IUSP), or the Operation
tion Size
status register (SR)
ASl ~,16, 32 @3+1 IIIi 1+ 0
SYSTEM STACK. The system stack IS used ImpliCitly by
many instructions, user stacks and queues may be created
ASR 8,16,3
dJ • ~
and maintained through the addressing modes Address LSL 8,16,32 @9+-14 /4-0
register seven (A7) IS the system stack pOinter (SP) The
system stack pOinter IS either the supervisor stack pOinter
(SSP) or the user stack pOinter IUSP), depending on the
lSR 8,16,32 0+1 .~

~ IIIi
state of the S-blt In the status register If the S-blt ,nd,cates
supervisor state, SSP IS the active system stack pOinter, and
the USP cannot be referenced as an address register If the
ROl 8.16.32 IJ
S-blt ,nd,cates user state, the USP IS the active system stack
pOinter, and the SSP cannot be referenced Each system
ROR 8,16,32 ~ •~
stack fills from high memory to low memory ROXl 8,16,32 ~ IIIi Hi]J
ROXR 8,16,32 4iH •~

•
LOGICAL OPERATIONS
Logical operation instructions AND, OR, EOR, and NOT
are available for all sizes of Integer data operands. A similar BIT MANIPULATION OPERATIONS
set of Immediate Instructions (ANDI, ORI, and EORIl provide Bit mampulatlon operations are accomplished uSing the
these logical operations With all sizes of Immediate data follOWing instructions bit test IBTSTI, bit test and set
Table 15 IS a summary of the logical operations IBSET), bit test and clear (BClR), and bit test and change
IBCHG) Table 17 IS a summary of the bit manipulation
operations IBlt 2 of the status register IS Z I

TABLE 17 - BIT MANIPULATION OPERATIONS

TABLE 15 - LOGICAL OPERATIONS Instruction Operand Size Operation
Instruction Operand Size Operation BTST 8,32 -bit of IEAI-Z
DnAIEA)-Dn -bit of IEAI-Z
AND 8,16,32 IEAIADn-EA BSET 8,32
I-bit of EA
IEAIAlxxx- EA - bit of IEAI- Z
Dn v IEAI-Dn BClR 8,32
O-blt of EA
OR 8,16,32 lEAl v Dn-EA -bit of IEAI-Z
lEAl v Ixxx- EA BCHG 8,32
- bit of IEAI- bit of EA
IEAleDy-EA
EOR 8,16,32
IEAlelxxx- EA
NOT 8,16,32 -IEAI-EA BINARY CODED DECIMAL OPERATIONS
NOTE - = Invert Multlpreclslon arithmetiC operations on binary coded
decimal numbers are accomplished uSing the follOWing in-
structions add deCimal With extend IABCD), subtract
SHIFT AND ROTATE OPERATIONS deCimal With extend (SBCD), and negate deCimal With ex-
tend (NBCO) Table 18 IS a summary of the binary coded
Shift operations In both directIOns are proVided by the
arithmetiC instructions ASR and ASL and logical shift In- deCimal operations
structions LSR and LSl The rotate instructions (With and TABLE 18 - BINARY CODED DECIMAL OPERATIONS
Without extend) available are ROXR, ROXl, ROR, and ROl
Operand
All shift and rotate operations can be performed In either Instruction Operation
Size
registers or memory Register shifts and rotates support all
operand sizes and allow a shift count specified In the instruc- ABCD 8 DXlO+DYlO+X-Dx
AX@-10+AY@-'0+X-Ax@
tIOn of one to eight bits, or 0 to 63 speCified In a data register
Memory shifts and rotates are for word operands only and SBCD 8 DXlO-0YlO-X-Dx
allow only Single-bit shifts or rotates AX@-'0-AY@-'0-X-Ax@
NBCD B O-IEAllO-X-EA
Table 16 IS a summary of the shift and rotate operations

4·700
MC68000L4e MC68000LS-MC68000L8-MC68000L10

PROGRAM CONTROL OPERATIONS SYSTEM CONTROL OPERATIONS

Program control operations are accomplished uSing a System control operations are accomplished by uSing
series of conditional and unconditional branch InstruCl!ons privileged Instructions, trap generating instructions, and in-
ann return instructions These instructions are summarized structIOns that use or modify the status register These in-
In Table 19 structions are summarized In Table 20
The conditIOnal instructions provide setting and branching
for the following conditions
TABLE 20 - SYSTEM CONTROL OPERATIONS
CC - carry clear LS -low or same
Instruction Operation
CS - carry set LT - less than
Privileged
EQ -- equal MI - minus
RESET Reset external devices
- never true NE - not equal
RTE Return from exception
GE - greater or equal PL - plus
STOP Stop program executDn
GT - greater than T - always true
ORI to SR Logical OR to status register
HI - high VC - no overflow
MOVE USP Move user stack pOinter
LE - less or equal VS - overflow
ANOI to SR Logical AND to status register
EaRl to SR Logical EOR to status register
TABLE 19 - PROGRAM CONTROL OPERATIONS
MOVE EA to SR Load new status register
Instruction Operation Trap Generating

•
Conditional TRAP Trap

Bce Branch conditionally (14 conditions) TRAPV Trap on overflow

8- and 1E>-b,t displacement CHK Check reg1ster agamst bounds
OSee Test condition, decrement, and branch Status Register
16~blt displacement ANDI to CCR Logical AND to condition codes
Sec Set byte conditionally 116 condltlOnsl EORI to CCR Logical EOR to condition codes
Unconditional MOVE EA to CCR Load new condition codes
BRA I Branch always ORI to CCR Logical OR to condition codes

BSR
8- and lE>-b,t displacement
Branch to subroutine
MOVE SR to EA StOl"e status register
I
8- and 16-blt displacement
JMP Jump
JSR Jump to subroutine
Returns
RTR Return and restore condition codes
RTS Return from subroutine I

4-701
 MC68000L4-MC68000LS-MC68000L8-MC68000L10

INSTRUCTION SET

The following paragraphs provide information about the These categones may be combined, so that additional,
addressing categones and Instruction set of the MC68000. more restnctlve, classifications may be defined For exam-
ple, the Instruction descnptlons use such classifications as
ADDRESSING CATEGORIES alterable memory or data alterable The former refers to
Effective address modes may be categonzed by the ways those addressing modes which are both alterable and
In which they may be used. The following classifications will memory addresses, and the latter refers to addreSSing modes
be used In the Instruction definitions. which are both data and alterable
Data If an effective address mode may be
used to refer to data operands, It IS INSTRUCTION PRE-FETCH
considered a data addressing effective The MC68000 uses a 2-word tightly-coupled instruction
address mode. prefetch mechanism to enhance performance This
Memory If an effective address mode may be mechanism IS descnbed In terms of the microcode opera-
used to refer to memory operands, It IS tions Involved If the executIOn of an instruction IS defined to
considered a memory addressing ef- begin when the micro routine for that instruction IS entered,
fective address mode some features of the prefetch mechanism can be descnbed
Alterable 11 When execution of an Instruction beginS, the operation
If an effective address mode may be
word and the word follOWing have already been fetch
used to refer to alterable Iwnteablel
ed The operation word IS In the instruction decoder
operands, It IS considered an alterable
21 In the case of multi-word Instructions, as each addi-

•
addressing effective address mode
tional word of the Instruction IS used Internally, a fetch
Control If an effective address mode may be IS made to the Instruction stream to replace It
used to refer to memory operands 31 The last fetch from the instruction stream IS made
without an associated Size, It IS con- when the operation word IS discarded and decoding IS
sidered a control addressing effective started on the next InstructIOn
address mode 41 If the Instruction IS a Single-word instruction causing a
branch, the second word IS not used But because thiS
Table 21 shows the vanous categones to which each of the word IS fetched by the preceding instruction, It IS Im-
effective address modes belong Table 22 IS the instruction possible to aVOid thiS superfluous fetch In the case of
set summary an Interrupt or trace exception, both words are not
used
The status register addressing mode IS not permitted 51 The program counter usually POints to the last word
unless It IS explicitly mentioned as a legal addressing mode fetched from the InstructIOn stream

TABLE 21 - EFFECTIVE ADDRESSING MODE CATEGORIES

Effective
Addressing Categories
Address
Modes Mode Register Date Memory Control Alterable
Dn 000 register number X - - X
An 001 register number - - - X
An@ 010 register number X X X X
An@+ 011 register number X X - X
An@- 100 register number X X - X
An@ldl 101 register number X X X X
An@(d, IX) 110 register number X X X X
xxxW 111 000 X X X X
xxx L 111 001 X X X X
PC@(d) 111 010 X X X -
PC@(d, IX) 111 011 X X X -
Ixxx 111 100 X X - -

4·702
MC68000L4· MC68000L6. MC68000L8. MC68000L 10

TABLE 22 - INSTRUCTION SET

Condition
Mnemonic Description Operation Codes
X N Z V C
ABCO Add Decimal with Extend (Oestm8tlonll0+ (Source)10- Destination U U
ADD
ADDA
Add Binary
Add Address
(Destmatlon) + (Source) -
(Destination) + (Source) -
Destination
Destination - -
·
- - -
ADD I Add Immediate (Destination) + Immediate Data - Destination
. ·
ADDQ Add QUick (Destination) + Immediate Data - Destination
ADDX Add Extended (Destmatlon) t (Source) + X- Destination
AND AND Logical (Destmatlon) A (Source)- Destination - a a
ANDI AND Immediate (Destination) A Immediate Data - Destmatlon - a a
ASL, ASR Arithmetic Shift (Destination) Shifted by <count> - Destination
BCC Branch Conditionally If CC then PC+ d - PC - - - - -
-«bit number>) OF Oestlnatlon-Z
BCHG Test a Bit and Change -«bit number» OF Oe5tlnatlon-
< bit number> OF Destination
- - · - -

BCLR Test a Bit and Clear

-
0-
« bit number> i OF DestinatIon - Z
< bItnumber> - OF DestInatIon
- - · - -

II
BAA Branch Always PC+d-PC - - - - -
-«bIt number» OF Destlnatlon-Z
BSET Test a Bit and Set - - - -
1 - < bit number> OF DestInatIon
BSA Branch to Subroutine PC-SP@-, PC+d-PC - - - - -
BTST Test a Bit - « bit number» OF Destination - Z - - - -
CHK Check RegIster agaInst Bounds If Dn <Oar Dn> l<ea>1 then TRAP - U U U
CLA Clear an Operand 0 - Destination - a 1 a a
CMP Compare (DestinatIon) - (Source) - ·
CMPA Compare Address IDestlnatlonl-ISourcel - ····
CMPI Compare Immediate (DestInatIon) -ImmedIate Data - ··
CMPM Compare Memory (DestinatIon) - (Source) - ···
DBCC Test CondItIon, Decrement and Branch If-CC then Dn-1-Dn, If Dn .. -1 then PC+d-PC - - - - -
DIVS Signed D,v,de (Destlnatlon)/ (Source) - Destination - 0
DIVU Unsigned DIvIde (Destlnatlon)/ (Source) - DestInation - · a· aa
EOR ExclusIve 0 R Logical (DestinatIon) m (Source) - Destination - ·
EORI
EXG
ExclusIve OR Immediate
Exchange Register
(DestinatIon) m Immediate Data -
Rx-Ay
DestinatIOn -

-
· a -a
- - -
EXT
JMP
Sign Extend
Jump
(Destination) SIgn-extended -
Destination - PC
DestInation -
-
··aa
- - - -
JSR Jump to Subroutine PC- SP@-, Destlnatlon- PC - - - - -
LEA Load Effective Address DestinatIon - An - - - - -
LINK LInk and Allocate An-SP@-, SP-An, SP+d-SP - - - - -
LSL, LSA Logical Shift (DestinatIOn) ShIfted by < count> - DestInatIon · a ·
MOVE Move Data from Source to Destination (Source) - Destination - a a
MOVE to CCR Move to CondItIon Code
MOVE to SA Move to the Status Register
(Source) -
ISourcel- SA
CCR
. ··
• affected o cleared U defined
- unaffected 1 set

4-703
 MC68000L4. MC68000L6. MC68000LS· MC68000L 10

TABLE 22 - INSTRUCTION SET (CONTINUED)

Condition
Mnemonic Description Operation Codes
X N Z V C
MOVE from SR Move from the Status Register SR- Destination - - - - -
MOVE USP Move User Stack POinter USP-An, An-USP - - - - -
MOVEA Move Address (Source) - Destination - - - - -
Registers - Destmatlon
MOVEM Move Multiple Registers - - - - -
(Source) - Registers
MOVEP Move Penpheral Data (Source)- Destination - - - - -
MOVEQ Move QUick Immediate Data- Destination - 0 0
MULS Signed Multiply (Destination)" (Source) - Destination - 0 0
MULU Unsigned Multiply (Destination)· (Source) - Destination - 0 0
NBCD Negate Decimal with Extend 0- (Oestlnatlon}10 - X - Destination U U
NEG Negate 0- (Destination) - Destination
NEGX Negate with Extend 0- (Destination) - X - Destination
NOP No Operation - - - - - -
NOT Logical Complement - (Destlnatlonl- Destination - 0 0
OR Inclusive OR Logical (Destination) v (Source) - Destination - 0 0

II
ORI Inclusive OR Immediate (Destmatlon) v Immediate Data- Destination - 0 0
PEA Push Effective Address Destination - S P@ ~ - - -- - -
RESET Reset External Devices - - - - - -
ROL, ROR Rotate (Without Extend) (Destination) Rotated by < count> - Destination - 0
ROXL, ROXR Rotate with Extend (Destination) Rotated by < count> - Destination 0
RTE Return from Exception SP@+-SR, SP@+-PC
RTR Return and Restore Condition Codes SP@+-CC,SP@+-PC
RTS Return from Subroutine SP@+-PC - - - - -
SBCO Subtract Decimal with Extend (Destination) 10 ~ (Source)1 a~ x- Destination U U
SCC Set According to Condition If CC then 1's- Destination else O's- Destination - - - - -
STOP
SUB
Load Status Register and Stop
Subtract Bmary
Immediate Data- SR, STOP
(Destination) ~ (Source) - Destination .
SUBA Subtract Address (Destination) ~ (Source) - Destination - - - - -
SUBI Subtract Immediate (Destination) -Immediate Data- Destination
SUBQ Subtract QUick (Destination) - Immediate Data - Destination
SUBX Subtract with Extend (Destination) - (Source) - X - Destination
SWAP Swap Register Halves Register [31 16]- Register [150] - 0 0
TAS Test and Set an Operand (DestlnaliOn) Tested - CC, 1 - [7] OF Destination - 0 0
TRAP Trap PC- SSP@-, SR- SSP@-, IVectorl- PC - - - - -
TRAPV T rap on Overflow If V then TRAP - - - - -
TST Test an Operand lDestlnatlOn) Tested- CC - 0 0
UNLK Unlink An-SP, SP@+-An - - - - -

[ ]= bit number

• affected o cleared U defined

- unaffected 1 set

4-704
MC68000L4- MC68000L6- MC68000LS- MC68000L 10

INSTRUCTION EXECUTION TIMES

STANDARD INSTRUCTION CLOCK PERIODS

The following paragraphs contain listings of the instruc-
The nllmber of clock periods shown In Table 26 ,nd,cates
tion execution times In terms of external clock lelKI
the tln18 required to perform the operations, store the
periods In this timing data, It IS assumed that both memory
results, and read the next Instruction The number of bus
read and write cycle times are four clock periods Any walt
states caused by a longer memory cycle must be added to read and write cycles IS shown In parenthesIs as Ir/wl The
the total Instruction time The number of bus read and write number of clock penods and the number of read and write
cycles for each Instruction IS also Included With the timing cycles must be added respectIVely to those of the effective
data ThiS data IS enclosed In parenthesIs follOWing the address calculation where Indicated
In Table 26 the headings have the follOWing meanings
execution periods and IS shown as Ir/wl where r IS the
number of read cycles and W IS the number of write cycles An ~ address register operand, On ~ data register operand,
ea ~ an operand specified by an effective address, and
M ~ memory effective address operand
NOTE
The number of periods Includes Instruction fetch and all IMMEDIATE INSTRUCTION CLOCK PERIODS
applicable operand fetches and stores The number of clock periods shown In Table 27 Includes
the time to fetch Immediate operands, perform the opera-
tions, store the results, and read the next operation The
EFFECTIVE ADDRESS OPERAND CALCULATION TIMING
number of bus read and write cycles IS shown In parenthesIs
Table 231,sts the number of clock periods requlled to com- as ir/wl The number of clock pen ods and the number of

•
pute an Instruction's effective address It Includes fetching read and wllte cycles must be added respectively to those of
of any extension words, the address computatIOn, and the effective address calculation where Indicated
fetching of the memory operand The number of bus read In Table 27, the headings have the follOWing meanings
and Wllte cycles IS shown In parenthesIs as Ir/wl Note there # ~ Immediate operand, On ~ data register operand, An ~
are no wllte cycles Involved In processing the effective ad- address register operand, M ~ memory operand, and
dress S R ~ status register

SINGLE OPERAND INSTRUCTION CLOCK PERIODS

MOVE INSTRUCTION CLOCK PERIODS Table 28 indicates the number of clock penods for the
Tables 24 and 25 indicate the number of clock periods for Single operand instructions The number of bus read and
the move Instruction ThiS data Includes Instruction fetch, wnte cycles IS shown In parentheSIS as ir/wl The number
operand reads, and operand wlltes The number of bus read of clock penods and the number of read and wnte cycles
and write cycles IS shown In parenthesIs as Ir/wl must be added respectively to those of the effective address
calculation where indicated

TABLE 23 - EFFECTIVE ADDRESS CALCULATION TIMING

Addressing Mode Byte, Word Long

Register
On Data Register Direct 010/01 010/01
An Address Register Direct OIOIO} OIOIO}
Memory
An@ Address Register Indirect 41t/0i BI2/0}
An@+ Address Register Indirect with Postincrement 41t/O} BI210}
An@- Address Register Indirect with Predecrement 61tlO} 1012/01
An@ldl Address Register Indirect with Displacement BI2101 1213/01
An@ld, ixl' Address Register Ind".ct with Index 101210} 141310}
xxx.W Absolute Short BI2101 121310}
xxx.L Absolute Long 121310} 1614/01
PC@ld) Program Counter with Displacement BI210} 1213/01
PC@ld, ix)' Program Counter with Index 10121Q) 1413/01
Ixxx Immediate 41tl0i BI2101

-The size of the Index register (IX) does not affect execution time

4-705
 MC68000L4· MC68000LS. MC68000L8. MC68000L 10

TABLE 24 - MOVE BYTE AND WORD INSTRUCTION CLOCK PERIODS

Destination
Source
Dn An An@ An@+ An@- An@ldl An@ld,ixl- xxx.W xxx.L
Dn 411/01 411/01 811/11 811/11 811111 1212/11 1412111 1212/11 1613/11
An 411101 411/01 811/11 811/11 811/11 1212/11 1412111 1212/11 1613/11
An@ 812101 812/01 1212/11 1212/11 1212/11 1613111 1813/11 1613/11 2014/11
An@+ 812101 812/01 1212/11 1212/11 1212/11 1613111 1813/11 1613/11 20141 11
An@- 1012/01 1012/01 1412/11 1412111 1412/11 1813/11 2013/11 1813/11 2214111
An@ldl 1213/01 1213/01 1613/11 1613111 1613/11 2014/11 2214111 2014/11 2415/11
An@ld, ixl- 1413/01 1413/01 1813111 1813/11 1813111 2214/11 2414111 2214111 2615/11
xxx.W 1213/01 1213/01 1613111 1613111 1613/11 2014/11 2214111 2014111 2415/11
xxx.l 1614/01 1614/01 2014111 2014111 2014111 2415/11 2615/11 2415111 2816111
PC@ldl 1213/01 1213/01 1613/11 1613111 1613/11 2014/11 2214111 2014111 2415111
PC@ld, ixl' 1413/01 1413/01 IS13/11 IS13/11 IS13/11 2214111 2414111 2214111 2615.11
'xxx SI2/01 SI2/01 1212/11 1212/11 1212111 1613/11 1813/11 1613111 2014/11

The size of the Index register IIx) does not affect execution time

TABLE 25 - MOVE LONG INSTRUCTION CLOCK PERIODS

•
Destination
Source An An@ An@+ An@- An@ldl An@ld,ixl* xxx.W xxx.L
Dn
Dn 411/01 411/01 1211/21 1211/21 1411/21 1612/21 1812/21 1612/21 2013/21
An 411101 411/01 1211/21 1211/21 1411/21 1612/21 1812/21 1612/21 2013.21
An@ 1213/01 1213/01 2013/21 2013/21 2013/21 2414/21 2614/21 2414121 2815121
An@+ 1213/01 1213/01 2013121 2013/21 2013/21 2414/21 2614/21 2414121 28(5/21
An@- 1413/01 1413/01 2213121 2213/21 2213/21 2614/21 2814/21 2614/21 3015/21
An@ldl 1614/01 1614/01 2414/21 2414/21 2414121 2815/21 3015121 2815/21 3216/21
An@ld, ixl' 1814/01 1814/01 2614/21 2614/21 2614/21 3015/21 3215/21 3015/21 3416/21
xxx.W 1614/01 1614/01 2414/21 2414/21 2414/21 2815/21 3015121 2815/21 3216/21
xxx.L 2015101 2015/01 2815/21 2815/21 2815121 3216/21 3416/21 3216/21 3617/21
PC@ld) 1614/01 1614/01 2414/21 2414/21 2414/21 2815121 3015/21 2815/21 3215121
PC@ld, ix)' 1814/01 1814/01 2614/21 2814121 2614/21 3015121 3215/21 3015121 3416121
Ixxx 1213/01 1213/01 2013/21 2013/21 2013121 2414/21 2614/21 2414121 2815/21

-The size of the mdex register (Ix) does not affect execution time

TABLE 26 - STANDARD INSTRUCTION CLOCK PERIODS

Instruction Size op <9a>, An op <aa>, On op Dn, <M>

Byte, Word 811/01+ 411/01+ 811/11+
ADD
Long 611/01+" 611/01+-' 1211/21+
Byte, Word - 411101+ 811/11+
AND
Long - 611/01+'- 1211/21+
Byte, Word 611101+ 411/01+ -
CMP
Long 611/01+ 611/01+ -
DIVS - - 15811/01+- -
DIVU - - 14011/01+- -

EOR
Byte, Word - 411/01'" 811/11+
Long - 811/01'" 1211/21+
MULS - - 7011/01 +' -
MULU - - 7011/01+' -
Byte, Word - 411101+ 811/11+
OR
Long - 611/01+*' 1211/11+
Byte, Word 811101+ 411/01+ 811/11+
SUB
Long 611/01+" 611/01+" 1211/21+

+ add effective address calculation time •• total of 8 clock periods for instruction If the effective address IS register direct
• Indicates maximum value I ••• only available effective address mode IS data regIster dIrect

4·706
MC68000L4· MC68000LS· MC68000LS. MC68000L 10

TABLE 27 - IMMEDIATE INSTRUCTION CLOCK PERIODS

Instruction Size op #, On op #, An op #, M
Byte, Word 812/01 - 1212/11+
ADDI
Long 1613/01 2013121+
Byte, Word 411/01 811/01' 811/11+
ADDQ
Long 811/01 811/01 1211/21+
Byte, Word 812101 - 1212/11 +
ANDI
Long 1613/01 2013111+
Byte, Word 812/01 812/01 812/01 +
CMPI
Long 1413/01 1413/01 1213/01 +
EORI
Byte, Word 812101 - 1212/11 +
Long 1613/01 2013/21 +
MOVEa Long 411/01 - -
Byte, Word 812101 - 1212/11+
ORI
Long 1613/01 2013/21+
Byte, Word 812101 - 1212/11+
SUBI
Long 1613/01 2013/21 +
Byte, Word 411/01 811101' 811/11 +
SUBO
Long 811/01 811/01 1211/21+-

II
+ add effective address calculation time
·word only

TABLE 28 - SINGLE OPERAND INSTRUCTION CLOCK PERIODS

Instruction Size Register Memory

Byte, Word 411/01 811/11 +
CLR
Long 611/01 1211/21+
NBCO Byte 611101 811111+
Byte, Word 411/01 811111+
NEG
Long 611/01 1211/21+
Byte, Word 411101 811/11+
NEGX
Long 611/01 1211/21+
Byte, Word 411101 811111+
NOT
Long 611/01 1211/21+
Byte, False 411101 811/11 +
SCC Byte, True 611/01 811111+
TAS Byte 411/01 1011111+
Byte, Word 411/01 411/01
TST
Long 411/01 411/01+
+ add effective address calculation time

SHIFT/ROTATE INSTRUCTION CLOCK PERIODS CONDITIONAL INSTRUCTION CLOCK PERIODS

Table 29 ,nd,cates the number of clock periods for the shift Table 31 Indicates the number of clock pen ods 'equlred for
and rotate Instructions The number of bus read and write the conditional instructions The number of bus read and
cycles IS shown In parentheSIS as. (r/wl The number of wnte cycles IS Indicated In parentheSIS as' (r/wi. The number
clock periods and the number of read and write cycles must of clock penods and the number of read and wnte cycles
be added respectively to those of the effective address must be added respectively to those of the effective address
calculation where Indicated. calculation where Indicated.

BIT MANIPULATION INSTRUCTION CLOCK PERIODS JMP, JSR, LEA, PEA, MOVEM INSTRUCTION CLOCK
Table 30 Indicates the number of clock periods reqUired for PERIODS
the bit manipulation Instructions The number of bus read Table 32 Indicates the number of clock penods reqUired for
and write cycles IS shown In parentheSIS as: (r/wl The the Jump, Jump to subroutine, load effective address, push
number of clock penods and the number of read and write effective address, and move multiple registers instructions.
cycles must be added respectively to those of the effective The number of bus read and wnte cycles is shown In paren-
address calculation where indicated. theSIS as: (r/wl.

4-707
 MC68000L4-MC68000LS-MC68000L8-MC68000L 10

TABLE 29 - SHIFT/ROTATE INSTRUCTION CLOCK PERIODS

Instruction Size Register Memory

Byte, Word 6 + 2n(1/01 8(1111+
ASR,ASl
Long 8 + 2n(1/0I -
Byte, Word 6 + 2n(1/01 8(1/11+
LSR, LSL
Long 8 + 2n(1/01 -
Byte, Word 6 + 2nll/01 8(1111+
ROR,ROL
Long 8 + 2n(1/01 -
Byte, Word 6 + 2n(I/01 811111+
ROXR,ROXL
Long 0+ 2n(1/01 -

TABLE 30 - BIT MANIPULATION INSTRUCTION CLOCK PERIODS

Dynamic Static
Instruction Size
Register Memory Register Memory
Byte - 811111+ - 1212/11+

II
BCHG
Long 811101'" - 1212/01* -
Byte - 811111+ - 1212/11+
BCLR
Long 1011/01* 1412/01*
Ii~ - 8(1111+ - 1212/11+
BSET Long 811101* 1212/01*

BTST
Byte - 411/01+ - 012/01+
Long 611/01 - 1012/01 -

+ add effective address calculation time

*' indicates maximum value

TABLE 31 - CONDITIONAL INSTRUCTION CLOCK PERIODS

Trep or Branch Trap or Branch

Instruction Displacement
Taken Not Taken
BCC Byte 1012/01 811/01
Word 10(2/01 1212/01
Byte 1012/01 -
BRA
Word 1012/01 -
Oyte 1012/21 -
BSR
Word 1012/21
cctrue - 12(2/01
DBce
CC false 1012/01 1413/01
CHK - 4015131+ * 011/01 +
TRAP - 34(4/31
TRAPV - 3415/31 411/01
+ add effecwe address calculation lime
* Indicates maximum value

4-708
MC68000L4-MC68000LS-MC68000L8-MC68000L 10

TABLE 32 - JMP, JSR, LEA, PEA, MOVEM INSTRUCTION CLOCK PERIODS

Instr Size An@ An@+ An@- An@ldl An@ld,lxl* xxx.W xxx.L PC@ldl PC@ld, Ixl*
JMf' - 812/01 - - 1012/01 1413/01 1012/01 1213/01 1012/01 1413/01
JSR - 1612/21 - - 1812/21 2212121 1812/21 2013121 1812/21 2212121
LEA - 411101 - - 812/01 1212/01 812101 1213/01 812101 12<2/01
PEA - 1211/21 - - 1612/21 2012121 1612/21 2013121 1612/21 2012121
MOVEM Word 12+40 12+40 - 16+4n 18+40 16+40 20+40 16+40 18+40
13+ n/Oi 13+n/01 - 14+n/01 14+n/0i 14+n/0i 15+ n/Oi 14+ n/OI 14+n/0i
M-R Long 12+80 12+80 - 16+80 18+80 16+80 20+80 16+80 18+80
13+2n/0i 13+2n/01 - 14+ 2n/01 14+ 2n/0i 14+ 2n/0i 15+ 2n/0l 14+2n/01 14+2n/01
MOVEM Word 8+50 - 8+50 12+50 14+50 12+50 16+50 - -
12/nl - 12/nl 13/nl 13/nl 13/nl 14/nl - -
R-M Long 8+1On - 8+1On 12+10n 14+1On 12+100 16+100 - -
12/2nl - 12/2nl 13/2nl 13/2nl 13/2nl 14/2nl - -
n IS the number of registers to move
* IS the size of the Index register hx) does not affect the InstructIOn's execution time

•
MULTI-PRECISION INSTRUCTION CLOCK PERIODS
Table 33 Indicates the number of clock periods for the number of read and write cycles IS shown In parenthesis as:
multi· precISion instructions The number of clock periods In (r/w!.
cludes the time to fetch both operands, perform the opera- In Table 33, the headings have the follOWing meanings
tions, store the results, and read the next instructions. The On = data register operand and M = memory operand

TABLE 33 - MULTI-PRECISION INSTRUCTION CLOCK PERIODS

Instruction Size op On, On opM, M

Byte, Word 411/01 1813/11
ADDX
Long 811101 3015/21

CMPM
Byte, Word - 1213/01
Long - 2015101
Byte, Word 411101 1813111
SUBX
Long 811/01 3015/21
ABCD Byte 811/01 1813/11
SBCD Byte 811101 1813/11

MISCELLANEOUS INSTRUCTION CLOCK PERIODS EXCEPTION PROCESSING CLOCK PERIODS

Table 34 Indicates the number of clock periods for the Table 35 indicates the number of clock peroods for excep-
follOWing miscellaneous instructions The number of bus tion processing The number of clock periods Includes the
read and write cycles IS shown In parenthesIs as· (r/w) The time for all stacking, the vector fetch, and the fetch of the
number of clock periods plus the number of read and wme first Instruction of the handler routine. The number of bus
cycles must be added to those of the effective address read and write cycles IS shown In parenthesIs as: (r/w!.
calculation where Indicated

4-709
 MC68000L4. MC68000L6. MC68000LS· MC68000L 10

TABLE 34 - MISCELLANEOUS INSTRUCTION CLOCK PERIODS

Instruction Size Register Memory Register - Memory Memory - Register

MOVE from SR - 611/0} 811/11 + - -
MOVE to CCR 1212/01 1212/0} +
MOVE to SR - 1212/0} 1212/0} + - -

MOVEP
Word - - 1612/21 1614/0}
Long - - 2412/41 2416/0}
EXG - 611101 - - -
EXT
Word 411/0} - - -
Long 411/0} - - -
LINK - 1612/21 - - -
MOVE from USP - 41110} - - -
MOVE to USP - 411/0} -
NOP - 411/0} - - -
RESET - 13211/0} - - -
RTE - 2015101 - - -
RTR - 2015/0} - - -
RTS - 1614/0} - - -
STOP - 41010} - - -

II SWAP
UNLK
-
-
+ add effective address calculation time
411/0}
1213/01
-
-

TABLE 35 - EXCEPTION PROCESSING CLOCK PERIODS

-
-
-
-

Exception Periods
Address Error 5014171
Bus Error 5014171
Interrupt 4415/31*
Illegal Instruction 3414/31
Privileged Instruction 3414/31
Trace 3414/31
*The Interrupt ac'<.nowledge bus cycle IS assumed
to take four external clock periods

4-710
 MC68120 MC68121
® MOTOROLA
(1.0 MHz)
MC68120·1 MC68121·1
(1.25 MHz)
(1.0 MHz)

(1.25 MHz)

Advance Infor:rn.atlon
HMOS
(HIGH-DENSITY N-CHANNEL
SILICON-GATE)
INTELLIGENT PERIPHERAL CONTROLLER
INTELLIGENT PERIPHERAL
The MC68120/MC68121 Intelhgent Penpheral Controller OPC) IS a CONTROLLER
general purpose, mask programmable peripheral controller. The IPC
provides the Interface between an M68000 or M6800 Family
microprocessor and the final penpheral devices through a system bus
and control hnes. System bus data IS transferred to and from the IPC via

.-
dual-port RAM while the software utlhzes the semaphore registers to
control RAM tasking or any other shared resource. Multiple operating
modes range from a Single chip mode with 21 1/0 lines and 2 control
lines to an expanded mode supporting an address space of 64K bytes.
The MC68120 has 2K bytes of on-chip ROM to make full use of all
operating modes The MC68121 utlhzes only the expanded address
modes, due to the absence of on-chip ROM. , L SUFFIX
A senal commUnications Interface, 16-blt timer, dual-ported RAM CERAMIC PACKAGE
and semaphore registers are available for use by the IPC In all operating CASE 740
modes.

• System Bus Compatible with the Asynchronous M68000 Family

• System Bus Compatible with the MC6809 and Other M6800 Family
Processors! Penpherals
PIN ASSIGNMENT
II
• Local Bus Allows Interface with all M6800 Penpherals Vss RESET
• MC6801 Source and Object Code Compatible iROl P24
• Upward Compatible with MC6800 Source and Object Code HALTI
P23
• 2048 Bytes of ROM (MC68120 Only) BA/NMI
E P22
• 128 Bytes of Dual-Ported RAM
• Multiple Operation Modes Ranging from Single Chip to Expanded, SR/W P21
with 64K Byte Address Space DTACK P20
• SIX Shared Semaphore Registers
CS se2
• 21 Parallel 1/0 Lines and 2 Handshake Lines (5110 Lines on
MC68121) SA7 sel

• Senal Communications Interface (SCII SA6 P30

• 16-Blt Three-Function Timer SA5 P31

• 8-Blt CPU and Internal Bus SA4 P32
• HaitI Bus Available Capablhty Control P33
Vee
• Bx8 Multiply Instruction SA3 P34
• TTL Compatible Inputs and Outputs
SA2 P35
• External and Internal Interrupts
SAl P36

SAO P37
SDO P40
SDI P41
SD2 P42
SD3 P43
SD4 P44

SD5 P45
SD6 P46

SD7 P47

4·711
 M C68120· M C68121. M C68120-1· M C68121-1

MC68120/MC68121 INTELLIGENT PERIPHERAL CONTROLLER - BLOCK DIAGRAM

~N~~~
c...c...o....o...c... cs
I-~«« SR/W
z::>.-J~~ OTACK
f= ~~@~
SOl
o 000
:::::-:::::::::::::::
'OO}
S02
S03 -;::

1+----+.., ~g~ ~ ~

Mode
S06
'"E
S07
*
>
(/)

SAO
SAl
SA2
SA3
SA4
RA[i'ISAINMI SA5
"iiiOl SA6
SA7
RESET CPU Data

II VSS
Vee
Address

OOOOOOOOI"'I'" •
Single Chip { ::::::::::::::::::::::::::::::::::::::: ~ ~
00000000
:::::::::::::::::::::::::::::::::::::::

Expanded Non-MultIPlexedtb~ t:3 2) 8 ~ 0 81~IQ

MAXIMUM RATINGS
Rating Symbol Value Unit ThiS device contains cirCUItry to protect the
Supply Voltage VCC -03to+70 V Inputs against damage due to high static
Input Voltage V,n -0310 +70 V voltages or electnc fields, however, It IS ad-
vised that normal precautions be taken to
Operating Temperature Range TA o to 70 'c avoid application of any voltage higher than
Storage Temperature Range Tstg -55 to + 150 'c maximum rated voltages to thiS hlgh-
Impedance Circuit For proper operation It IS
recommended that Vln and Vout be con-
THERMAL CHARACTERISTICS strained to the range VSSs (V ,n or
Characteristic VoutsVCC
Unused Inputs must always be tied to an
Thermal Resistance
appropnate logic voltage level (e g , either
Ceramic Package
VSS or VCCI

4-712
MC68120- MC68121- MC68120-1-MC68121-1

POWER CONSIDERATIONS

The average chip-Junction temperature, T J, In °c can be obtained from

T J = TA + IPD·OJAI 111
Where
T A'" Ambient Temperature, °c
0JA'" Package Thermal Resistance, Junctlon-to-Amblent, °C/W
PD'" PINT + PPORT
PINT'" ICC x VCC, Watts - Chip Internal Power
PPORT'" Port Power DIssipation, Watts - User Determined
For most applications PPORT"" PINT and can be neglected PPORT may become Significant !f the device IS configured to
drive Darlington bases or sink LED loads
An approximate relationship between Po and T J Ilf PPORT IS neglectedl IS
Po = K - IT J + 273°CI 121
Solving equations 1 and 2 for K gives
K = PO.IT A + 273°CI +OJA"P 0 2 131
Where K IS a constant pertaining to the particular part K can be determined from equation 3 by measuring Po lat equillbrlumi
for a known T A USing this value of K the values of Po and T J can be obtained by solving equations 111 and 121 Iteratively for any
value of T A

II
DC LOCAL BUS ELECTRICAL CHARACTERISTICS IV CC = 50 Vdc ± 5%, VSS = 0, T A = 0° to 70'C unless otherwise noted I
IRefer to Figures 1 and 21
Characteristic Svmbol Min Typ Max Unit
Input High Voltage E VEIH VCC-O 75 - VCC V
Input Low Voltage E VEIL VSS -0 3 - VSS+06 V
Input High Voltage RESET . VSS +40 - VCC
VIH V
Other Inputs' VSS + 20 - VCC
Input Low Voltage All Inputs' VIL VSS-03 - VSS+08 V
Input Load Current Port4 - - 05
lin mA
IVIn=Oto 2 4 VI SCl - - 08
Input Leakage Current
lin - 15 25 ~A
IV,n =Ot0525VI HALT INMI, TiiCi1, RESET
Three-State IOff Statel Input Current
IV,n =05t024VI SOO-SD7, P30-P37 ITSI - 20 10 ~A
P20-P24 - 100 100
Output High Voltage
IIload= -205~A, VCC= mini P30-P37 VSS+24 - -
VOH V
IIload = - 145 ~A, VCC = min I P40-P47, SC1, SC2 VSS + 24 - -
IIload= -l00~A, Vcc=mlnl Other Outputs VSS+24 - -
Output Low Voltage - - V
VOL VSS + 05
IIload=2 0 mA, VCC= mini All Outputs
Internal Power DISSipation (measured at T A - aOC) PINT - - 1200 mW
Input Capacitance
IV In =0, T A = 25°C, fo= 1 0 MHzI P30-P37, P40-P47, SCl Cin - -- 125 pF
Other Inputs - - 100
'Except Mode Programming Levels, See Figure 31

FIGURE 1 - CMOS LOAO FIGURE 2 - TIMING TEST LOAD PORTS 2, 3, 4

Vee

t·
Test Pomt O~--,
RL=20kO
Test Pomt
MMD6150
or EqUiv
o
"
MMD7000
or Equlv

C = 90 pF for P30-P37, P40-P47, sci': SC2

=30 pF for P20-P24, HALT/BA/NliifI
R = 16 5 kll for P40-P47, SCI, SC2
= 12 kll for P30-P37
= 24 kll for P20-P24, HALT lBA/NMT

4-713
 MC68120-MC68121-MC68120-1-MC68121-1

DC SYSTEM BUS ELECTRICAL CHARACTERISTICS

IVcC=5 0 Vdc ±5%, VSS=O, TA=70 o C unless otherwise noted) IRefer to Figure 3)

Characteristic Svmbol Min Tvp Max Unit

Input High Voltage CS, DTACK, SAO-SA7, SDO-SD7, SR/W VIH VSS + 2 0 - VCC V
Input Low Voltage CS, DTACK, SAO-SA7, SDO-SD7, SR/W VIL VSS - 03 - VSS +0 8 V
Output High Voltage IILQad= -400~A, V",,= mini DTACK, SDO-SD7 VOH VSS + 24 - - V
Output Low Voltage IILoad- 53 rnA, VCC- mini DTACK, SDO-SD7 VOL - - VSS+05 V

FIGURE 3 - TIMING TEST LOAD SDO-SD7, DTACK

vee

RL= 750 0

Test POint o-------1I----.--~t_-__. MMD6150

Of EqUiv

MMD7000
C=130pF or EqUiv
R~6kO

PERIPHERAL PORT TIMING IRefer to Figures 4 through 71

Characteristics Symbol Min Max Unit
Peripheral Data Setup Time tPDSU 200 - ns
Penpheral Data Hold Time tPDH 200 - ns
Delay Time, Enable PosItive Transition to OS3 Negative TransItion - 350 ns

•
tOSDI
Delay Time, Enable Positive Transition to 053 Positive Transition tOSD2 - 350 ns
Delay Time, Enable Negative TransItIOn to Penpheral Data Valid IPorts 2, 3, 41 tpWD - 350 ns
Delay Time, Enable Negative Transition to Penpheral CMOS Data Valid tCMOS - 20 ~s

Input Strobe Pulse Width tpWIS 200 - ns

Input Data Hold Time tlH 50 - ns
Input Data Setup Time t(S 20 - ns
Input Capture Pulse Width (TImer function) tpWIC 2 - Ecyc

FIGURE 4 - DATA SETUP AND HOLD TIMES FIGURE 5 - DATA SETUP AND HOLD TIMES
IMPU READ LOCAL BUSI IMPU WRITE LOCAL BUS)

P20-P24
P40-P47
Inputs All Data
Port Outputs _ _ _ _ _ _ _ _....J Data Valid

P30-P37 Notes
Inputs· 1 10 k Pullup resistor required for Port 2 to reach 0 7 Vee
2 Not applicable to P21
'Port 3 Non-Latched Operation ILATCH ENABLE= 01 3 Port 4 cannot be pulled above Vee

FIGURE 6 - PORT 3 OUTPUT STROBE TIMINe:: FIGURE 7 - PORT 3 LATCH TIMING

ISINGLE CHIP MODEl ISINGLE CHIP MODEl

Address
Bus

P30-P37
Inputs

*Access matches Output Strobe Select (OSS=O, a read,

OSS = 1, a wrltel
Note TIming measurements are referenced to and from a low voltage of 0 8 volts and a high voltage of 2 ° volts, unless otherWise noted

4-714
MC68120-MC68121-MC68120-1-MC68121-1

LOCAL BUS TIMING ISee Notes 1 and 21

MC681201 MC68120-11
Ident.
Characteristics Symbol MC68121 MC68121-1 Unit
Number
Min Max Min Max
1 Cycle Time tcyc 10 20 08 20 ~s

2 Pulse Width. E Low PWEL 430 1000 360 1000 ns

3 Pulse Width, E High PWEH 450 1000 360 1000 ns
4 Clock Rise and Fal! Time t r , tf - 25 - 25 ns
9 Non-Muxed Address Hold Time tAH 20 - 20 - ns
11 Address Delay From E Low tAD - 260 - 220 ns
17 Read Data Setup Time tDSR 80 - 70 - ns
18 Read Data Hold Time 'DHR 10 - 10 - ns
19 Write Data Delay Time tDDW - 225 - 200 ns
21 Wnte Data Hold Time tDHW 20 20 ns
23 Muxed Address Delay from AS 'ADM - 90 - 70 ns
25 Muxed Address Hold Time tAHL 20 110 20 110 ns
26 Delay Time E to AS Rise tASD 100 - 80 - ns
27 Pulse Width, AS High PWASH 220 - 170 - ns
28 Delay Time AS to E Rise tASED 100 - 80 - ns
29 Usable Access rime (Note 9} tAce 570 - 435 - ns

II
Enable Rise Time Extended tERE - 80 - 80 ns
Processor Control Setup Time tpcs 200 - 200 - ns
Processor Control Hold Time tpCH 20 40 20 40 ns

FIGURE 8 - LOCAL BUS TIMING

tERE

Riw,105,
Address
---ti1E~~~~~Gf~----------------ti--------------------------------t-~~~
INon-Muxedl

Addr/Data Read Data Muxed

Muxed

f+----{ 19l--~~

AddrlData ---+-:1::1. Write Data Mu><-ed

Muxed

Address
Strobe IASI _ _ _ _ ---"r

NOTES
Voltage levels shown are Vl:S;O 5 V, VH~2 4 V, unless otherwise specIfied
a
rv1easur€noent pOints shown are 08 V and 2 V, unless otherwise specified
Address valid on the occurrence of the latest of 11 or 23
Usable access time IS comp'.Jted by 1- (4+ 11 + 17)' see note 8

4-715
 MC68120e MC68121 e MC68120-1 e MC68121-1

ASYNCHRONOUS SYSTEM BUS TIMING (Refer to FIQures 9, 10 , 11 and 121

Characterisic Symbol Min Typ Max Unit
Cvcle Time tcvc 08 - 20 ~s

Svstenl :~.ddress Setup tSAS 30 - -- ns

System Address Hold tSAH 0 - - ns
System Data Delay Read
Semaphore tSDDR 03 -
o 3 + tcye ~s

RAM tSDDR 315 ns

System Data Valid tSDV 0 ns
System Data Hold Read tSDHR 30 -- 90 ns
System Data Delay Wnte
Semaphore tSDDW
.. - .. ns
RAM tSDDW 60 ns
System Data Hold Write tSDHW 0 - - ns
Data Acknowledge
Semaphore tDAL 05 -
05+ tcye ~s

RAM tDAL 315 ns

Data Acknowledge High tDAH - - 60 ns
Data Acknowledge Three-State tDAT - - 90 os
Data Acknowledge Low to es High toes 60 - - ns

.. Actual value dependent upon clock period

.... Oata need not be valid on wnte to Semaphore Registers

• FIGURE 9 - ASYNCHRONOUS READ OF SEMAPHORE REGISTER FIGURE 10 - ASYNCHRONOUS WRITE OF SEMAPHORE REGISTER

FIGURE 11 - ASYNCHRONOUS READ OF RAM FIGURE 12 - ASYNCHRONOUS WRITE OF RAM

sRiViJ
SAO-SAl

SAOoAl -i-----=I
SOD-SOl ---~'H"-H<I
SDD-SDl

i5TACK--:,--:---J
Three State

Note Timing measurements are referenced to and from a low voltage of 0 8 volts and a high voltage of 2 0 volts, unless otherwise noted

4-716
MC68120e MC68121 eMC68120-1 eMC68121-1

SYNCHRONOUS SYSTEM BUS TIMING ISee Notes 1 and 21

MC881201 MC88120-1
ldent Symbol MC88121 MC88121-1
Characteristic Unit
Number Min Ma. Min Ma.
1 Cycle Time tcyc 10 10 080 10 "s
2 Pulse Width. E Low PWEL 430 9600 360 9600 ns
3 Pulse Width. E High PWEH 40u ~ ;jIj() ~ ns
4 Clock Rise and Fall Time t,.tf 25 25 ns
9 Address Hold Time tAH 10 - 10 - ns
13 Address Setup Time Before E tAS 80 70 ns
14 Chip Select Setup Time Before E tcs 80 70 ns
15 Chip Select Hold Time tCH 10 10 - ns
18 Read Data Hold Time tDHR 30 100 30 85 ns
21 Wrote Data Hold Time tDHW 10 - 10 - ns
30 Output Data Delay Time tDOR - 290 - 240 ns
31 Input Data Setup Time tDSW 166 - 120 - ns
Clock Enable Rise Time Extended tERE 80 80 ns

FIGURE 13 - SYNCHRONOUS SYSTEM BUS TIMING

~------------------~--------~------------------------~~
VEIH
I
1+---0------.1
~-------'CD~------~

R/W.Add,ess--~~~~~~~~rr--------~~~~---+4----------------------------

cs----~-r------------------~

Read Data --+---..... MPU Read Data Non Muxeo

Write Data ----~-~ MPU Wrote Data Non Muxed

~--------~~~~~~~~------------~

Notes
1 Voltage levels shown are VL'sO 5 V, VH~2 4 V, unless otherWise speCified
2 Measurement POints shown are 0 8 V and 2 0 V, unless otherWise speCified

4·717
 MC68120-MC68121-MC68120-1-MC68121-1

INTRODUCTION

The MC6B1ZO/MC68121 IS an 8-bIt Intelligent Penpheral The remaining ports (2, 3. and 4) are 1/0 ports. Each port
Controller (lPC) which can be configured to function In a IS controlled by ItS Data DlrecllOn Register The CPU has
wide variety of applications. This extraordinary flexibility IS direct access to the port PinS of each port through ItS Data
provided by its ability to be hardware programmed into eight Register Port PinS are labeled as PII where I Identifies one of
different operating modes. These operating modes allow the three ports and I indicates the particular bit Port 2 IS a 5-blt
IPC to operate on its local bus and communicate with an ex- port which may be configured for 1/0 or for use of the on-
ternal system bus through the Internal dual-ported RAM chip timer and Senal Communications Interface (SCII Ports
The operating mode controls the configuration of 18 of the 3 and 4 may be used as 16 bits of 1/0 or may form a local ad-
48 pins on the IPC, the available on-chip resources, the dress and data bus With control hnes allOWing communica-
memory map, the location !Internal or externall of Interrupt tions With external memory and penpherals
vectors, and the type of local bus. The configuratIOn of the The IPC contains an enhanced M6800 MPU With addl-
remaining 30 pins is not controlled by the operating mode IIOnal capabilities and greater throughput It IS upward
The dual-ported RAM provides a vahlcle for devices on source and oblect code compatible With the MC6800 and
two seperate buses to exchange data Without directly affect- directly compatible With the MC6801 The programming
Ing the devices on the other bus. The dual-ported RAM IS ac- model IS depicted In Figure 14, where accumulator 0 IS a
cessible from the MC681ZO/MC68121 CPU and acceSSible concatenation of accumulators A and B.
synchronously or asynchronously to the system bus through The MC68121 has all of the features of the MC68120 With
Port 1. Semaphore registers are provided as a software tool the exception of on-chip ROM Thus the MC68121 normally
to arbitrate shared resources such as the dual-ported RAM operates In the modes utlhzlng external ROM (modes 2 and
The semaphore registers are acceSSible from both buses In 3) Therefore, modes 0, I, 4, 5, 6 and 7 should not be used

I the same way each bus accesses the dual-ported RAM.

FIGURE 14 - PROGRAMMING MODEL

b----~---~~7----~----:1 8-Blt Accumulators A and 8

Or 16·BII Double Accumulator D

1'5
)(
01 Index Register IXI

1'5 SP 01 Stack POinter ISPI

1'5 PC 01 Program Counter !PCI

Condition Code Register ICCRI

Carry/Borrow from MSB

Overflow
Zero
Negative
Interrupt
Half Carry IFrom Bit 31

4-718
MC68120-MC68121-MC68120-1-MC68121-1

DUAL-PORTED RAM AND SEMAPHORE

REGISTERS
The dual-ported RAM may be accessed from both the the dual-ported RAM has been relocated In high memory
MC68120/MC68121 CPU and the external system bus The from $coeo through SCOFF thus allOWing use of direct ad-
SIX semaphore registers are tools provided for the program- dreSSing mode on external memory/peripherals Note that
mer's use In arbitrating simultaneous accesses of the same no direct addreSSing of Internal control registers IS possible In
resource mode 3 In mode 4, the Internal RAM IS not fully decoded
and appears In locations $XX80 through $XXFF From the
For the Internal CPU, the dual-ported RAM IS located from external system bus, the dual-ported RAM IS found In loca-
$0080 through $OOFF In all modes except 3 and 4 In mode 3, tions %10000000-11111111, as shown below In Table 1

TABLE 1 - LOCATION OF SEMAPHORE REGISTERS AND DUAL-PORTED RAM

Syatem Bus Add.-
(SA7-SAO) Feature IPCAdd. . .•

%0000 0000 - 0001 0110 Reserved ------

---- ---- - ---- ---- Internal Registers $00-16
0001 0111 - 0001 1100 Semaphore Registers 17-1C
0001 1101 - 0111 1111 Reserved to-IF
---- ---- - ---- ---- External Mem IUnusable" 2O-7F
1000 0000 - 11111111 Dual-Poned RAM BO-FF

I
% = Binary, $ = Hexadecimal
"Mode Dependent

The reserved memory areas %CHlOOl 0110 and %0001 direction of data transfer IS selected by the System
1101-%0111 1111 cannot be written to from the System bus Read/Write (SR/W) hne. The Data Transfer Acknowledge
If read from the System bus these memory locations return a IDTACK) Signal IS the asynchronous handshake reqUired by
value of $FF. an MC68000. Refer to DT ACK under Functional Pin DeSCrip-
The dual-ported RAM IS accessed from the external tion for more Information. DTACK can be used to control a
System bus by way of eight address hnes (SAO-SA7) and Memory Ready Signal on the M6800 Family processor where
eight data hnes (SOO-S071. Three control hnes prOVide for Memory Ready capablhty IS prOVided (sea Figure 17). The lat-
synchronous or asynchronous access to the dual-ported ter would allow the M6800 Family processor to run asyn-
RAM through Port 1. Figure 15 shows an example of a syn- chronously with the MC68120/MC68121. It should be noted
chronous Interface (using MC68(9) and Figure 16 shows an that If the Memory Ready Signal (on M6800 processors) IS to
example of an asynchronous Interface (using MC68000) The be used With the t5TACK Signal, the system clock must be
dual-ported RAM IS selected In each case by address lines faster than or equal to the clock driVing the IPC. Example
SAO-SA7 and Chip Select (CS) from the system bus The clock CirCUitS are shown In Figures 18 and 19

FIGURE 15 - SYNCHRONOUS SYSTEM BUS ACCESS INTERFACE

MC68120 MC6809

Data Lines

Lower Address Lines

'E and Q are InpulS for MC6809E

""Only needed," expanded multiplexed modes

4-719
 MC68120-MC68121-MC68120-1-MC68121-1

FIGURE 16 - ASYNCHRONOUS SYSTEM BUS INTERFACE

MC68120 MC68000

SDO-SD7
Lower Data Lines

SAO-SA7

Lower Address Lines

AI-A8

I • Only needed In expanded multiplexed modes

FIGURE 17 - MEMORY READY - DTACK CONFIGURATION

MC68120 MC6809

·Only needed In expanded multiplexed modes

4-720
MC68120-MC68121-MC68120-1-MC68121-1

FIGURE 18 - CLOCK CIRCUIT EXAMPLE 1 - SCHEMATIC AND TIMING

Schematic

r---------------------------.. O
AS

U1 SN74LS 175
U2 SN75LS08
tRC= 10 I's

8 MHz

OB a
J
•
QD __~______________~

L
The semaphore registers allow arbitration between shared The semaphore bits are test and set bits with hardware ar-
resources, which may be part or all of the dual-port RAM, or bitration dunng simultaneous accesses. BaSically, the
a penpheral The semaphore registers may also be used to in- semaphore bit IS cleared when wntten and set when read,
dicate that non-reentrant code IS In use or that a task IS In dunng a single processor access This IS shown In Table 2
process or IS complete To prevent the writing or reading of
erroneous data from the dual-ported RAM, all simultaneous TABLE 2 - SINGLE PROCESSOR SEMAPHORE
accesses involving a write to the dual-ported RAM should be BIT TRUTH TABLE
aVOided The responsibility for mutual exclusion resides In
O';ginal Data Resulting
software. The semaphore registers are a convenient means R/W
SEM Bit Read SEM Bit
for the software to control the simultaneous accesses involv-
0 R O· 1
Ing a wnte to the dual-ported RAM Each of the SIX
1 R l' 1
semaphore registers consist of a semaphore bit (SEM, bit 71 - 0
0 W
and an ownership bit (OWN, bit 61 The remaining SIX bits 1 W 0
(bO-b51 will read all zeros
SEMAPHORE REGISTER '0 - Resource Available
1 - Resource Not Available
7 6 5 4 3 2 1 0
t SEM laWN I 0 0 0 0 0 0

4-721
 MC68120-MC68121-MC68120-1-MC68121-1

FIGURE 19 - CLOCK CIRCUIT EXAMPLE 2 - SCHEMATIC AND TIMING

Schematic Vcc

AS

CLR PRE
)O----tCLK a o
U2a U2b

'---t----tCLK 01---' "'--.......... 0

U1. U2 - SN74LS74 CLR
U3 - SN74LS02

I TImIng

01

02

03J
04 - - - , ' -_ _---1

EJ '------'I
AS _ _ _ _ _ _~r_l~ ______~~
o--'L..__ ....J

The data wrotten IS dIsregarded and the InformatIon obtaoned In Table 3. the forst four states are consIdered proper and
from the Read may be onterpreted as. 0 - resource avaIlable. they occur In correctly written software. The last four states
1 - resource not avaIlable Thus. any wrote to a semaphore are Improper and only eXIst In Improperly written software
clears the semaphore bIt and makes the assocIated resource The ownershIp bIt IS a read-only bIt that IndIcates whIch
.. avaIlable .. processor sets the semaphore bIt If the semaphore bIt IS set.
An access where both the IPC and system processors at- the ownershIp bIt ,nd,cates whIch processor set It If the
tempt to read or wrote the same semaphore regIster semaphore bIt IS not set. the ownershIp bIt ,nd,cates whIch
sImultaneously IS a contested access Durong a contested ac- processor last set the semaphore bIt. OWN = O. the other
cess. the hardware decIdes whIch processor reads a clear processor set SEM. OWN = 1. thIS processor set SEM
semaphore bIt and whIch reads a set semaphore bIt. Table 3 The reset state of the semaphore and ownershIp bIts IS
descrobes contested operatIon of a semaphore bIt defoned on Table 4 All of the semaphore bIts are set after an
The IPC always reads the actual semaphore bIt. the MC68120/MC68121 reset The IPC owns all of them except
system processor reads the semaphore bIt In all cases except the second semaphore whIch IS owned by the system pro-
the sImultaneous read of a clear semaphore bIt. ThIS arbItra- cessor ThIS confIguratIon should prevent the system pro-
tIon durong a sImultaneous read ensures that only one pro- cessor from readong a clear semaphore and ImplYIng the
cessor reads a clear bIt and therefore controls the resource. system processor set It when the IPC REm IS held low
that processor IS arbItrarily the IPC

4-722
MC68120- MC68121- M C68120-1- MC68121-1

TABLE 3 - DUAL PROCESSOR SEMAPHORE BIT TRUTH TABLE

IPC System
Original Data Data Resulting
-
SEM Bit R/W Read R/W Read SEM Bit
0 A O· A ,.. 1
1 A 1· W - 0
PAOPEA
1 W - A 1· 0
1 A 1 A 1· 1
0 W - W - 0
0 R O· W - 1
IMPAOPEA
1 W - W - 0
0 W - A O· 1
·0 - Aesource Available
1- Aesource Not Available

TABLE 4 - AESET STATE OF SEMAPHORE REGISTEA

SEM IPC System
Reg
No. Sem Own S8m Own
1 1 1 1 0
2 1 0 1 1
3 1 1 1 0

I
4 1 1 1 0
5 1 1 1 0
6 1 1 1 0

PROGRAM STORAGE MEMORY - ROM

The standard MC68120 comes preprogrammed with a decoder for the ROM may be mask programmed as a 0 or a 1
monitor In the ROM. Custom programs are placed In ROM to change the ROM starting address from $FBOO to $CBOO,
by special order (see Appendix AI. $DBOO or $EBOO A12 and A13 may also be "don't cares" In
The MC68120 contains 2048 bytes of on-chip, mask pro- thiS decoder. Address $FFEF IS reserved for the checksum
grammable read-only memory (ROM) In memory locations value for the ROM ThiS value IS the complement of the "Ex-
$FBOO through $FFFF The contents of thiS ROM allows the clusive OR" of the 2047 bytes of mask programmed ROM
IPC to perform a custom function for the user The Interrupt An IPC without ROM IS also available as the MC68121. The
vectors $FFFO-$FFFF are decoded to provide vectors at the MC68121 should only be used In modes 2 and 3 to access ex-
top of resident ROM Address lines A 12 and A 13 of the ternal ROM after reset

FUNCTIONAL PIN DESCRIPTIONS

VCC AND VSS On the positive edge of RESET, the IPC latches the
VCC and VSS provide power and ground to the IPC The operating mode from P22, P21 and P20, and then configures
power supply should provide + 5 volts (± 5%) to V cc and Port 3, Port 4, SC1 and SC2 The restart vector IS then
VSS should be tied to ground Total power dissipation fetched and transferred to the program counter, then In-
should not exceed PD milliwatts struction execution begins.
Reset timing IS Illustrated In Figure 20 The RESET line
RESET must be held low for a minimum of three E-cycles for the IPC
The reset function IS used for three purposes The first IS to complete ItS entire reset sequence. An external RC-
to provide the IPC with an orderly and defined start-up pro- network may be used to obtain the reqUired timing
cedure from a powerdown condition The second IS to return
to start-up conditions without an Intervening powerdown ENABLE - E
condition The third IS to proVide a control signal to latch the The E clock Input IS reqUired for timing to synchrOnize
operating mode Data Bus transfers A "CPU E-cycle" (or bus cycle) consists
DUring reset (low logiC level on RESET Pin), execution of of a negative half-cycle of E followed by a positive half-cycle.
the current instruction IS suspended and the CPU enters a For any given bus cycle, the address IS valid dUring the
"reset state." The register contents are not pushed onto the negative half-cycle of E and the selected deVice must be
stack and their contents become undefined dUring reset The enabled to the Data Bus dUring the next positive half-cycle.
"reset state" Initializes the IPC, as shown In Table 5 The data bus IS active only while E IS high. It should be noted

4-723
 MC68120-MC68121-MC68120-1-MC68121-1

TABLE 5 - STATE OF IPC DURING RESET

Bits or Registers Effective State
CPU I-Bit set IIROl and IR02 disabled I
NMI Interrupt Latch cleared INMI dlsabledl
Halt Control Bit cleared IHALT/BA selected I
All Data DirectIOn Registers cleared
SCI Rate and Mode Control Register cleared
Receive Data Register cleared
Timer Control and Status Register cleared
Free Running Counter cleared
Buffer for LS B of Counter cleared
Port 3 Control and Status' Register cleared
Port 2, 3, 4 Data Registers undefined after Power-up Reset. and not changed after
Reset
SCI Transmltl Receive Control and Status Register Preset to $20
Output Compare Register Preset to $FFFF
Semaphore Bits Preset to 1's
Ownerslllp Sit of Semaphore Register 2 Preset to System Ownership
All other Ownership Sits Preset to IPC Ownership
All Ports 2 and 3 Lines High Impedance (Inputsl
All Port 4 Lines High Impedance (Inputsl with pullup reSistors
SC1· High Impedance With pullup resistors
SC2 Active High

II ·If In mode 5, SCl Will go active high, otherwise It Will remain In

FIGURE 20 - RESET TIMING

the high Impedance state

-,A: mIn
vee ~r-""------Exlernal
E Slart-up Tlme--------i-~:::::s:_- ___-____
RESET __________~~r_______- -______- - -

Internal
AddressBusu..u.u.u..u..:u,....".:u.:u.:u.:u.u.u.....,..J'-;-F~FF:-;E-f'-...~FF:-;F-;'E·H-;F";F7F7E·"·";"F7f;:;FE,.,.''-~FF;:;F-;'F7,'';:N7:e:-:w-;P~C~.~-..''.I\r.....J·'---''--F-FF~E.J'-FF"'F""E

~~-------------~

1!1~tructl(Hl
~NotValid

·Mode 0 - $BFFE. BFFF

Note Timing measurements are referenced to and from a low voltage of 0 8 volts and a high voltage of 2 0 volts, unless otherWIse noted

that thiS Input should have some provIsion to obtain the function IS activated An external pullup resistor to V CC IS re-
specified logical high level which IS greater than standard qUired on pin 3 for ellner function TYPical pullup resistor
TTL levels values range from 3K to 10K depending on the dnve capabili-
Enable IS the pnmary IPC system timing signal and all tim- ty of the external deVice
Ing data specified as cycles IS assumed to be referenced to When the NMI function IS Implemented, pin 3 IS con-
thiS clock unless otherwise noted figured as an Input A negative edge on pin 3 then requests
an IPC non-maskable Interrupt sequence, but the current In-
struction Will be completed before responding to thiS re-
HALT/BUS AVAILABLE/NON-MASKABLE quest. To assure an Interrupt under all conditions, NMI must
INTERRUPT - HALT/BA/NMI be held low for at least one E-cycle N M I may be used to
The HALT /BA/NMI (pin 31 serves one of two functtons. cause the IPC to eXit the Walt instruction For Interrupt tim-
These functions are NMI or Halt/BA and the function Ing specifications, see the Interrupt portion of the Operating
selected IS determined by the Halt Control (HC, bit 2) bit of Mode Section.
the Functional Control Register lIocation $14), If the HC bit IS When configured to utilize the HaitI BA function of thiS
set (to a "1"1. then the NMI function IS activated. Alternate- Pin. such as after reset, the circuit of Figure 21 IS recom-
ly. If HC IS cleared (to a "0" as It IS dunng reset I , the HaitI BA mended to detect and supply continuous HALT and BA

4.. 724
MC68120-MC68121-MC68120-1-MC68121-1

FIGURE 21 - HALT/BA DEMULTIPLEXING CIRCUIT

,..-........f--'V'I/'Ir-.... VCC

SN74LS74 3-10 kO
PRE
DI-+-----_

SA 0 ClK
CLR

MC681201
MC68121

>-....______.:.3-1 HALTJi3A/NMI

E __~____________~~__~__________________~4

signals Figure 22 shows the appropriate timing diagram for

Halt/BA with the recommended CirCUit. The pullup resistor
shown In the CirCUit maintains a high logic level when HALT
IS not active. DUring a positive half-cycle of E, Pin 3 IS an in-
put sampled to determine If the Halt State IS requested (ac-
IPC back on the local bus. DUring the Halt State, the R/iN IS
high, and the address bus displays the address of the next In-
struction
When Single instruction operation IS desired, In program
debug for Instance, It IS advantageous to Single step through
•
tive lowl. During the negative half cycle of E, the BA signal IS Instructions After BA goes low, HALT must be brought
output through pin 3 After the request for Halt State signal high for one E-cycle and returned low again to Single step
IS detected and the processor completes ItS current Instruc- through Instructions. Figure 22 Illustrates the timing Involved
tion, the CPU IS halted and the active low BA signal IS output while Single stepPing through a Single byte, two bus cycle in-
through pin 3 dUring the negative half cycle of E. The local struction, such as CLRA.
bus IS then available for other devices to utilize until the Halt BA IS not output In response to the Walt instruction If in-
State signal has returned to a high level, thus allOWing the terrupts are to be utilized In removing the processor from a

FIGURE 22 - HALT/SA TIMING DIAGRAM

In/Out In
M IL____________~ '---___----'1
R/W~
Add/Data

Add

Note Timing measurements are referenced to and from a low voltaqe of 0 8 volts and a hlqh voltaqe of 20 volts, unless OTherWise noted

4-725
 MC68120-MC68121-MC68120-1-MC68121-1

Wait State while in the Halt/BA mode then, IRQ1 and IRQ2 Expanded Non-Multiplexed Mode - In thiS mode, both
are the only Interrupts which may do so; therefore, their SCl and SC2 are configured as outputs SCl functions as
masks must be cleared before entenng the Walt State. Input/Ol/tput Select (lOS) and IS asserted (active-low) only
when addresses $0100 through $01 FF are accessed. SC2 IS
MASKABLE INTERRUPT REQUEST 1 - IRQ1 configured as Riw and IS used to control the direction of
This level-sensitive input can be used to request an Inter- local data bus transfers. An MPU read IS enabled when R/W
rupt sequence. The IPC will complete the current instruction and E are high.
before it responds to the request. If the Interrupt mask bit
(I-bit! in the Condition Code Register IS clear, the IPC will Expanded Multiplexed Modes - In these modes, SCl IS
begin an interrupt sequence: a vector IS fetched from $FFF8 configured as an input and SC2 IS configured as an output
and $FFF9, transferred to the Program Counter, and Instruc- In the expanded multiplexed modes, the IPC has the ability
tion execution is continued at the new location. ThiS IS ex- to access a 64K byte address space SCl functions as an In-
plained in greater detail in the Interrupt Section. put, Address Strobe, which controls demultlplexlng and
IRQ1 tYPically requires an external resistor (3K to 10K enabling of the eight least Significant addresses and the data
depending on external devices dnve capability) to V CC for buses.
wire-OR applicatIOns. IRQl has no Internal pullup resistor. By uSing a transparent latch such as an SN74LS373 or
MC6882, Address Strobe (AS) can also be used to de-
STROBE CONTROL 1 AND 2 - SC1 and SC2 multiplex the two buses external to the IPC. (See Figure 23.)
The functions of SCl and SC2 depend on the operating SC2 proVides the local Data Bus control Signal called
mode SCl IS configured as an Input In all modes except Read/Write (R/"Wl SC2 IS configured as R/W and IS used to
the Expanded Non-Multiplexed Mode, whereas SC2 IS al- control the direction of local data bus transfers An M PU
ways an output. SCl and SC2 can drive one Schottky load read IS enabled when R/W and E are high

•
and 90 pF
Single Chip Modes - In these modes, SCl and SC2 are SYSTEM BUS INTERFACE
configured as an input and output, respectively, and both Port 1 IS a mode-Independent 8-blt data port which per-
function as Port 3 control lines. SCl functions as an Input mits the external system bus to access the dual-ported RAM
strobe (lS3) and can be used to Indicate that Port 3 Input and semaphore registers either asynchronously or syn-
data is ready or output data has been accepted. Three op- chronously with respect to the E clock In addition to the
tions associated with IS3 are controlled by the Control and eight data lines (SOO-S07), eight address (SAO-SA7l and
Status Register for Port 3 and are discussed In the Port 3 three control lines (SR/Vii, CS, OTACK) are used to access
descnptlon. the dual-ported RAM and semaphore registers
SC2 IS configured as an output strobe (OS3) and can be
used to strobe output data or acknowledge Input data for Port 1 Data Lines (SOC-SD7) - These data lines are bi-
Port 3. It IS controlled by Output Strobe Select (OSS) In the directional data lines which allow data transfer between the
Port 3 Control and Status Register The strobe IS generated dual-ported RAM or the semaphore registers, and the
by a read (OSS=O) or write (OSS=l) to ,he Port 3 Data system bus The data bus output drivers are three-state
Register. OS3 timing IS shown In Figure 6 devices which remain In the high-Impedance state except

FIGURE 23 - TYPICAL LATCH ARRANGEMENT

GND
AS

EN!G
I OCI
D1 01

Port3
Address! Data 1J.... SN74LS373
(TYPical!

r---

I D8 08
I
IIIII
~-
4-726
MC68120-MC68121-MC68120-1-MC68121-1

dunng a read of the IPC dual-ported RAM or semaphore Inputs on P20, P21 and P22 determine the operating mode
registers by the system processor which IS latched Into the Program Control Register on the
positive edge of RESET. The mode may be read from the
System Address Lines (SAG-SA7) - The address lines Port 2 Data Register (PC2 IS latched from pin 45)
together with the Chip Select signal allow any of the 128 Port 2 also prOVides an Interface for the Senal Com-
bytes of RAM or SIX semaphore registers to be uniquely mUnications Interface and Timer Bit 1, If configured as an
selected from the system bus. The address lines must be output, IS dedicated to the Timer Output Compare function
valid before the CS signal goes low for the asynchronous in- and cannot be used to prOVide output from the Port 2 Data
terface and valid before the E signal goes high for the syn- Register.
chronous Interface. The system Interface must be deselected
between reads or between wntes for the asynchronous PORT 3 - P30-P37
operation. Port 3 can be configured as an I/O port, a bl-dlrectlOnal
6-blt data bus, or a multiplexed addressl data bus depending
System Read/Write (SR/W) - This signal IS generated by upon the operating mode. The TTL compatible three-state
the system bus to control the direction of data transfer on output buffers can dnve one Schottky TTL load and 90 pF
the data bus. With the IPC selected, a low on the SR/iN line
enables the Input buffers, and data IS transferred from the Single Chip Modes - In these modes, Port 3 IS an 8-bit
system processor to the IPC. When SRIW IS high and the I/O port where each line IS configured by the Port 3 Data
chip IS selected, the data output buffers are turned on and Direction Register ASSOCiated With Port 3 are two lines, IS3
data IS transferred from the IPC to the system bus and OS3, which can be used to control Port 3 data transfers
Three Port 3 options, controlled by the Port 3 Control and
Chip Select (CS) - ThiS signal IS a TTL compatible Input Status Register and available only In the Single Chip Modes
signal, used to activate the system bus Interface and allows are' 1) Port 3 Input data can be latched uSing IS3 as a control
transfer of data between the IPC and the system processor
dunng synchronous or asynchronous accesses ~ provides
the synchronizing Signal for the Semaphore registers dunng
access by the system bus

Data Transfer Acknowledge (DTACK) - ThiS bidirectIOnal

Signal, 2) OS3 can be generated by either an IPC read or
wnte to the Port 3 Data Register, and 3) an IR01 Interrupt
can be enabled by an IS3 negative edge Port 3 latch timing
IS shown In Figure 7
II
control line IS used to determine synchronous or asyn-
chronous system bus accesses and to prOVide the data $OF
acknowledge Signal for asynchronous data transfers
As an Input, It IS sampled on the falling edge of CS by the
IPC to determine If the system bus IS being accessed syn-
chronously or asynchronously With respect to the E clock Bits 0-2 Not used.
If DT ACK IS low when sampled, the system bus IS syn- Bit 3 LATCH ENABLE ThiS bit controls the Input latch
chronous and data Will be transferred dunng E high as shown for Port 3 If set, Input data IS latched by an I S3
In Figure 13. negative edge The latch IS transparent after a read
If OTACR IS high when sampled, the system bus IS asyn- of the Port 3 Data Register LATCH ENABLE IS
chronous In thiS mode DT ACK becomes an output that IS cleared by Reset
asserted low when data IS on the bus dunng a system read or Bit 4 OSS (Output Strobe Select) ThiS bit determines
when a data transfer IS completed dunng a system wnte whether OS3 Will be generated by a read or wnte of
Refer to Figures 9 through 12 the Port 3 Data Register When clear. the strobe IS
DTACK reqUires an external pullup resistor when the generated by a read, when set, It IS generated by a
system bus IS run asynchronously since It IS then a bidirec- wnte OS S IS cleared by Reset
tional handshake line for Information transfer on the system Bit 5 Not used.
data bus.
Bit 6 IS3-IR01 ENABLE When set, an IR01 Interrupt
Will be enabled whenever IS3 FLAG IS set, when
PORT 2 - P20-P24
clear, the Interrupt IS Inhibited ThiS bit IS cleared by
Port 2 IS a mode Independent 5-bit 1/ 0 port where each Reset
line IS configured by ItS Data Direction Register Dunng Bit 7 IS3 FLAG ThiS read-only status bit IS set by an IS3
reset, all lines are configured as Inputs The TTL compatible negative edge It IS cleared by a read of the Port 3
three-state output buffers can dnve one Schottky TTL load Control and Status Register (With IS3 FLAG set)
and 30 pF, or CMOS deVices uSing external pullup resistors followed by a read or wnte to the Port 3 Data
P20, P21 and P22 must always be connected to provide the Register or by Reset
operating mode

PORT 2 DATA REGISTER Expanded Non-Multiplexed Mode - In thiS mode, Port 3

IS configured as a bl-dlrectlonal data bus (00-07) The direc-
7 6 543 2 I a
I PC2 I PCI I I
PCO P241 P23 I P22 I P21 I P20 I $03 tIOn of data transfers IS controlled by R/IN (SC2) Data
transfers are clocked by E (Enable)

4·727
 MC68120. MC68121. MC68120-1· MC68121-1

Expanded Multiplexed Modes - In these modes, Port 3 IS pullup resistors to more than 5 volts, however, cannot be
configured as a time-multiplexed address IAO-A7) and data used.
bus 100-071. Address Strobe lAS) must be Input on SC1,
and can be used externally to de-multiplex the two buses. Expanded Non-Multiplexed Mode - In thiS mode, Port 4
Port 3 IS held In a high-Impedance state between valid ad- IS configured from reset as an B-blt Input port, where the
dress and data to prevent potential bus confhcts. Data Direction Register can be Written, to provide any or all
of address lines AO-A7. Internal pull up resistors are Intended
PORT 4 - P40-P47 to pull the lines high until the Data Direction Register IS con-
figured.
Port 4 is configured as B-bit I/O port, as address outputs,
or as data Inputs depending on the operating mode. Port 4
Expanded Multiplexed Mode - In all these modes except
can drive one Schottky TTL load and 90 pF and IS the only
Mode 6, Port 4 functions as half of the address bus and pro-
port with Internal pull up resistors.
vides AB to A 15. In Mode 6, the port IS configured from reset
as an 8-bll parallel Input port, the Port 4 Data-Direction
Single Chip Modes - In these modes, Port 4 functions as Register must be wntten to provide any or all of address
an 8-bit I/O port where each line IS configured by the Port 4 hnes, AS to A15. Internal pullup resistors are Intended to pull
Data Direction Register. Internal pull up resistors allow the the hnes high until the Data Direction Register IS configured
port to directly interface With CMOS at 5 volt levels. External lbit 0 controls AB, etc I.

OPERATING MODES

II The IPC provides eight different operating modes which

are selectable by hardware programming and referred to as
Modes 0 through 7. The operating mode controls the
memory map, configuration of Port 3, Port 4, SC1 and SC2
and the address location of the Interrupt vectors
Single Chip Modes 14, 7) -:- In Single Chip Mode, three of
the four IPC ports are configured as parallel Input/output
data ports, as shown In Figure 25. The IPC functions as a
complete microcomputer In these two modes Without exter-
nal address or data buses A maximum of 21 I/O hnes and
two Port 3 control lines are proVided
FUNDAMENTAL MODES In Single Chip Test Mode 141, the RAM responds to ad-
The eight modes of the IPC can be grouped Into three fun- dresses $XXBO IX; don't care) through $XXFF and the ROM
damental modes which refer to the type of bus It supports IS removed from the Internal address map A test program

Single ChiP, Expanded Non-Multiplexed, and Expanded must first be loaded Into the RAM uSing Modes 0, 1,2, or 6
Multiplexed Single Chip Includes Modes 4 and 7, Expanded If the IPC IS reset and then programmed Into Mode 4, execu-
Non-Multiplexed IS Mode 5 and the remaining five are Ex- tIOn Will begin at $XXFE XXFF Mode 5 can be Irreversibly
panded Multiplexed modes A system utilIZing three entered from Mode 4 Without gOing through reset by setting
MC68120's, one In each of the fundamental operating bit 5 of the Port 2 Data Register ThiS mode IS used primarily
modes, IS shown In Figure 24 Table 6 summarizes the to test Port 3 and 4 In the Single Chip and Non-Multiplexed
characteristics of the operating modes Modes

TABLE 6 - SUMMARY OF IPC OPERATING MODES

Common to all Modes Expanded Multiplexed Modes
System Bus Interface Four Memory Space Options I64K Address Spacel
Reserved Register Area 11 I MOOS Compatible
6 Semaphore Registers 121 No ROM
1/0 Port 2 131 External Vector Space
Programmable Timer 141 ROM With Partial Address Bus"
Senal Communications Interface External Memory Space Accessed Through
128 bytes of Dual Ported RAM Port 3 as a Multiplexed Addressl Data Bus
Single Chip Mode" Port 4 as an Address Bus IHlghl
2048 Bytes of ROM Iinternall SCt IS Address Strobe Bus lAS) Input
Port 3 IS a Parallel I/O Port With Two Control Lines SC2 IS Read/Write IR/WI
Port 4 IS a Parallel 110 Port
SCt IS Input Strobe 3 1153) Test Modes
SC2 IS Output Strobe 3 1053) Expanded Multiplexed Test Mode
May be Used to Test RAM and ROM"
Expanded Non-Multiplexed Mode"
Single Chip and Non-Multiplexed Test Mode"
2048 Bytes of ROM Iinternall
May be Used to Test Ports 3 and 4 as 1/0 Ports
256 Bytes of External Memory Space
Port 3 IS an B-B,\ Data Bus
Port 4 IS an Address Bus
SCt IS Input/Output Select 1105)
SC2 IS Read/Write IR/WI "MC68t20 only

4-728
MC68120- MC68121- MC68120-1- MC68121-1

FIGURE 24 - IPC FUNDAMENTAL OPERATING MODES

68000 6808
6809 6803
6801 6800
6802

RAM MC68120 Single Chip Mode

ROM

SSDA Expanded
ADLC Non-Multiplexed
CATC Mode

System Bus

Expanded
Multiplexed
Mode
•
ROM

Local
00
00
Bus
"
-0
"0
ro
ro
0
« RAM

PIA SSDA
ACIA ADLC
GPIA CATC
PTM

Expanded Non-Multiplexed Mode (51 - A modest amount Expanded-Multiplexed Modes (0, 1, 2, 3, 61 - In the Ex-
of external memory space IS provided In the Expanded Non- panded Multiplexed Modes, the IPC has the ability to access
Multiplexed Mode while retaining significant on-chip a 64K-byte memory space Port 3 functions as a tlme-
resources Port 3 functions as an S-blt bl-dlrectlonal data bus multiplexed address/ data bus with address valid on the
and Port 4 IS configured as an Input data port Any combina- negative edge of Address Strobe (AS I and the data bus valid
tion of AO to A7 may be provided while retaining the re- while E IS high In Modes a to 3, Port 4 provides address lines
mainder as Input data lines. Any combination of the eight AS-A 15. However, In Mode 6, Port 4 can provide any subset
least-significant address lines may be obtained by writing to of AS to A 15 while retaining the remainder as Input lines
the Port 4 Data Direction Register Internal pullup resistors Writing l's to the desired bits In the Data Direction Register
are provided to pull Port 4 lines high until It IS configured IDDRI will output the corresponding address lines while the
Figure 26 Illustrates the external resources available In the remaining bits will remain Inputs (as configured from reset or
Expanded Non-Multiplexed Mode. The IPC Interfaces direct- from a's written to the DDRI. Internal pullup resistors are
ly with M6800 Family parts and can access 256 bytes of ex- provided to pull Port 4 lines high until software configures
ternal address space at $100 through $1 FF lOS provides an the port. Initialization of Port 4 in Mode six must be done to
address decode of external memory ($100-$1 FFI and may be obtain any upper address lines externally.
used as an address or chip select line

4-729
 MC68120-MC68121-MC68120-1-MC68121-1

FIGURE 26 - SINGLE CHIP MODE

VCC

AESET MC68120 HALT IBA/NMI

IAOl

Port 3 8 System
81/0 Lines Address Lines

Port 1
8 System
Data Lines System
Bus

SAlVi
CS
Port 4 DTACK
81/0 Lines
Port 2
5110 Lines

•
SenalllO,
16-Blt Timer

-
VSS

FIGURE 26 - EXPANDED NON-MULTIPLEXED MODE

VCC

AESET MC68120 HALT/BA/NMI

IRQl

Port 3 8 System
8 Data Lines Address Lines

Port 1
8 System
A/Vi Data Lmes. System
Bus

lOS SAlVi
CS
Port 4 DTACK
8 Address Lines
Port 2
51/0 Lines
Senoll/O,
16-BIt Timer

VSS

4-730
MC68120-MC68121-MC68120-1-MC68121-1

Figure 27 depicts the external resources available In the after the positive edge of RESET In addition, the Internal
Expanded-Multiplexed Modes. Address Strobe can be used and external data buses are connected together so there
to control a transparent D-type latch to capture addresses must be no memory map overlap (to aVOid potential bus con-
AO-A7, as shown in Figure 23. This allows Port 3 to function filets). Mode a is used primarily to verify the ROM pattern
as a Data Bus when E IS high. and monitor the Internal data bus with automated test eqUip-
In Mode a, the reset vector is external at $BFFE and $BFFF ment

FIGURE Xl - EXPANDED MULTIPLEXED MODE

Vcc

RESET HALT/SA/NMI
MC681201
MC68121 IRQ1

Port 3
S Lines Multiplexed S System
Addressl Data Address Lines

Port 1
R/iN 8 Syslem
Data Lmes System
Sus

Port 4
AS

8 Address Lines
SR/W
CS
DTACK
Port 2
5110 Lines
II
SenalllO,
16-Blt Timer

VSS

MODE PROGRAMMING used, otherwise, the three-state buffers can be used to pro-
The operating mode IS programmed by the levels asserted Vide Isolation while programming the mode
on P22, P2l, and P2a dUring the positive edge of RESET
These are latched Into PC2, PC1, and pca of the program MEMORY MAPS
control register. The operating mode may be read from the The IPC provides up to 64K bytes of address space
Port 2 Data Register and programming levels and timing depending upon the operating mode. A memory map for
must be met as shown In Figure 28 and Table 7 A brief each operating mode IS shown In Figure 30. In Modes 1Rand
outline of the operating modes IS shown In Table 8 6R, the "R" means the ROM has been relocated by a mask
CirCUitry to provide the programming levels IS primarily option. The first 32 locations of each map are reserved for
dependent on the normal system use of the three pins. If the IPC Internal register area, as shown In Table 9, with ex-
configured as outputs, the CirCUit shown In Figure 29 may be ceptions as Indicated.

FIGURE 28 - MODE PROGRAMMING TIMING

See Figure 31
for Diode
VMPDD
tMPH
VMPL
IP20, P21, P221 Mode Latch Level
Mode Inputs
-...It~----'--~~ VMPH Min
IP20, P21, P221 ---<I RESET
l"--'-------'71 VM PL Max

4-731
 MC68120-MC68121-MC68120-1-MC68121-1

TABLE 7 - MODE PROGRAMMING SPECIFICATIONS (See Figure 30)

Charactariatlc Symbol Min Typ Max Unit
Mode Programming Input Voltage Low VMPL - - 18 V
Mode Programming Input Voltaga High VMPH 40 - - V
Mode Programming Diode Differential (,f Diodes are Used) VMPDD 0.6 - - V
mn Low Pulse Width PWRSTL 30 - - E-Cycles
Mode Programmmg Setup Time tMPS 20 - -- E-Cycles
Mode Programming Hold Time
REm Rise Time .. 1 ,.5 tMPH 0 - - ns
RESET Rise Tlme< 1 ,.s 100 - -

TABLE 8 - MODE SELECTION SUMMARY

Pin 4ti Pin 44 PInG

Interrupt BUI Operating
Mode P22 P21 P20 ROM RAM
Mode
Vectors Mode
PC2 PCI PCO
7 H H H I I I I Single Chip
6 H H L I I I MUX(S,6) Multlplexedl Partial Decode(5)
5 H L H I I I NMUX(5,6) Non-Multlplexedl Partial Decode(5)
4 H L L 1(2) ((1) I I Single Chip Test
3 L H H E 1(7) E MUX(4) Multlplexedl RAM(4)

I 2
1
0
Legend'
I - Internal
L
L
L
H
L
L
L
H
L
Notes.
E
I
I
I
I
I

(1) Internal RAM IS addressed at $XXOO'

E
E
E(3)
MUX(4)
MUX(4)
MUX(4)
MultlPlexed/RAM(4)
Multlplexed/RAM and ROM(4)
Multiplexed Test(4)

E - External (2) Internal ROM IS disabled

MUX - Multiplexed 13) Interrupt vectors externally located at $BFFO-$BFFF
NMUX - Non-Multiplexed (4) Addresses associated With Ports 3 and 4 are considered external on Modes 0, 1, 2, and 3
L - LogiC "0" (5) Addresses associated With Port 3 are considered external In Modes 5 and 6
H - LogIC "1" (6) Port 4 default IS user data Input, address output IS optional by writing to Port 4 Data Direction Register
(7) Internal RAM and registers located at $COXX (for use With MDOS)

FIGURE 29 - TYPICAL MODE PROGRAMMING CIRCUIT

V C

MC681201
A2 Al Al Rl MC68121

,..--,
AESET ~~--L-'--4~-+---r-------~~AESET
P20 4i;---~t--1~-+--+-------43., P20 (PCO!
P21 4ir----r-t--1f--......--+------~44::::!.1 P21 (PC 1)
P22 41r---t-t--1f---+---+-------4
,5 P221PC2)
L __ .I
OptIOnal
Three-State
Buffers
Mode
MCI4066B
Control

Notes
1 Mode 7 as shown
2 A2.C = Reset time constant
3 Rl = 10 k (typical)
4 D= lN914, lN4001 (tYPical)

4·732
MC68120e MC68121 e MC68120-1 e MC68121-1

FIGURE 30 - IPC MEMORY MAPS

Multiplexed Test Mode

MC68120
Mode
o
Internal Registers

External Memory Space Notes

1j Excludes the following addresses which may be
used externally $04, $05, $06, $07 and $OF
Internal RAM
2} The Interrupt vectors are externally located at
$BFFO-$BFFF
3) There must be no overlapPing of Internal and ex-
ternal memory spaces to avoid driving the data
External Memory Space
bus with more than one device
41 ThiS mode IS the only mode which may be used
to examine the mterrupt vectors In Internal ROM
$BFFO
External Interrupt Vectors(2l uSing an external RESET vector
$BFFF 51 MC68120 only
External Memory Space

II
$F8OO

Internal ROMI51

MC68120 MC68120
Mode

1 Mode

Multiplexed/RAM and ROM Multiplexed/RAM and ROM

Internal Reglsters( 1) Internal Reglsters{1)

External Memory Space External Memory Space

Internal RAM Internal RAM

External Memory Space

External Memory Space

Internal ROMI21

internal ROM

$FFFOr
'------I~ External Memory Space
External Interrupt Veclors(2) $FFFF External Interrupt Vectors
$FFFF ~ _ _--'

Notes Notes
1) Excludes the following addresses which may be 1) Excludes the following addresses which may be
used externally $04, $05, $06, $07 and $OF used externally $04, $05, $06, $07, and $OF
21 Internal ROM addresses $FFFO to $FFFF are not 2) Starting addresses for the Internal ROM may be
usable $C8OO, $D800 or $E8OO as a mask option
 MC68120-MC68121-MC68120-1-MC68121-1

FIGURE 30 - IPC MEMORY MAPS iCONTINUED)

MC68120/ 3
2
MC68120/
MC68121 MC68121
Mode Mode

Multiplexed/RAM, MOOS Compatible 111

Multiplexed/RAM $0000..-----.

Internal Reglsters l11

External Memory Space External Memory Space

Internal RAM

Internal Reglsters(2)

External Memory Space

External Memory Space

Internal RAM

External Memory Space

II
$FFFO~---t External Interrupt Vectors
External Interrupt Vectors
$FFFF .......--~
Notes
1) Relocating the Internal registers and the Internal
RAM to high memory allows processor to run
Notes MOOS
1) Excludes the following addresses which may be 21 Excludes the following addresses which may be
used externally $04, $05, $06, $07, and $OF used externally $COO4, $C005, $COO6, $C007,
and $CooF

4 5
MC68120 MC68120
Mode Mode

Single Chip Test l21 Non-Multiplexed/Partial Decode 121 131

$O:~ ~W
@}Internal Registers
$ o o o o T \ Internal Reg!sters l51
f
$0060~unusable~
$001F

Internal RAM
$ooFF
$0100
External Memory Space
$01 FF
Unusablel11141

$XX8013Irr7Cn""7-.r1} Internal RAMI41

$XXFF L..:;"'::.L..L.'-4 Internal Interrupt Vectors
"""~}
~
$FFFF
Internal ROM

Internal Interrupt Vectors

Notes Notes
11 The Internal ROM IS disabled 1) Excludes the follOWing addresses which may not
21 Mode 4 may be changed to Mode 5 without hav- be used externally $04, $06, and $OF Ina 10SI
Ing to assert RESET by wrltmg a "1" Into bit 5 (peG) 2) ThiS mode may be entered Without gOing
of Port 2 Data Register through Reset by uSing Mode 4 and subsequent-
31 Addresses AS to A 15 are treated as "don't ly writing a "1" Into bit 5 (peo) of Port 2 Data Register
cares" to decode Internal RAM 3) Address lines AO to A7 Will not contain addresses
41 Internal RAM Will appear at $XX80 to $XXFF until the Data Direction Register for Port 4 has
51 MPU Read of Port 3 Data DirectIOn Register Will been written With "1' s" In the appropriate bits
access Port 3 Data Register Instead These address lines will assert "1'5" until made
outputs by wntlng the Data Direction Register

4·734
MC68120-MC68121-MC68120-1-MC68121-1

FIGURE JO - IPC MEMORY MAPS (CONCLUOEDI

MC68120 MC68120
Mode
& Mode

Multiplexed! Partial Decode

Internal Reglstersl11121 Internal Reglsters(l )(21

$001 F 1-'.L...I.:....c...L...I.I(
External Memory Space External Memory Space

Internal RAM Internal RAM

External Memory Space

External Memory Space

Internal ROMI31

•
External Memory Space
Internal ROM
External Interrupt Vectors
Internal Interrupt Vectors

Notes Notes
1) Excludes the following addresses which may be 1) Excludes the following addresses which may be
used externally $04, $06, $OF used externally $04, $06, $OF
2) Address lines AS-A 15 will not contam addresses 2) Address lines AS-A 15 will not contam addresses
until the Data Direction Register for Port 4 has until the Data Direction Register for Port 4 has
been wntten with" 1's" In the appropriate bits been wntten with "l's" In the appropriate bits
These address lines will assert "l's" until made These address lines will assert "1's" until made
outputs by wntmg the Data Direction Register outputs by writing the Data Direction Register
3} Starting addresses for the Internal ROM may be
$C8OO, $0800 or $EBOO

MC68120
Mode
7
Single Chip

::~} Internal Reglsters l11

$0080~} Internal RAM

'OOCC I Notes
1} MPU reads of Port 3's Data Direction Register
will access Port 3's Data Register Instead

Unusable

7-735
 MC68120-MC68121-MC68120-1-MC68121-1

TABLE 9 - INTERNAL REGISTER AREA

Register
Address...
( Hexadecimal!
··* Register
Address·***
( Hexadecimal!
Reserved 00 SCI Rate and Mode Control Register 10
Port 2 Data Direction Register· ** 01 Transmit/Receive Control and Status Register 11
Reserved 02 SCI Receive Data Register 12
Port 2 Data Register 03 SCI Transmit Data Register 13
Port 3 Data Direction Reglster-·· 04'
Port 4 Data DIrection Reglster-·· 05" Function Control Register 14
Port 3 Data Register 06' Counter Alternate Address IHlgh Byte! 15
Port 4 Data Register 07" Counter Alternate Address (Low Byte) 16
Timer Control and Status Register 08 Semaphore 1 17
Counter IHlgh Byte! 09 Semaphore 2 18
Counter I Low Byte) OA Semaphore 3 19
Output Compare Register (High Byte) OB Semaphore 4 lA
Output Compare Register I Low Byte) OC Semaphore 5 lB
Input Capture Register I High Byte) 00 Semaphore 6 lC
Input Capture Register ILow Byte! OE Reserved 1D-IF
Port 3 Control and Status Register OF'
--
'These external addresses on Modes 0, 1, 2, 3, 5, 6 cannot be ac- '''1 = Output, 0= Input
cessed In Mode 5 Ina lOS) , .. 'These addresses relocated at $COOO-$COI F In Mode 3
··These are external addresses In Modes 0, 1, 2, 3

• The IPC supports two types of Interrupt requests

Maskable and Non-Maskable. A Non-Maskable Interrupt
INMII IS always recognized and acted upon at the comple-
tion of the current Instruction. Maskable Interrupts are con-
trolled by the Condition Code Register I-bit and by Individual
enable bits. The I-bit controls all maskable Interrupts Of the
INTERRUPTS

Single SCI Interrupt and three timer Interrupts are serviced In

a Prioritized order where each IS vectored to a separate loca-
toon All IPC vector locatoons are shown In Table 10, from
highest (topl to lowest (bottoml PriOrity
The Interrupt flowchart IS depicted In Figure 31. The Pro-
gram Counter, Index Register, Accumulator A, Accumulator
maskable Interrupts, there are two types. IRQ1 and IRQ2. B, and Condition Code Register are pushed to the stack. The
The Programmable Ti~and Serial Communications Inter- I-bit IS set to inhibit maskable Interrupts and a vector IS
face use an Internal IRQ2 Interrupt lone, as shown In the fetched corresponding to the current highest Priority inter-
block diagram of the IPC. External deVices land IS31 use rupt. The vector IS transferred to the Program Counter and
iAN An IRQ1 Interrupt IS serviced before an IRQ2 Interrupt Instruction execution IS resumed. The general Interrupt tim-
If both are pending Ing sequence IS shown In Figure 32. The Interrupt HAlT/BA
All IRQ2 Interrupts use hardware priOritized vectors The timing IS Illustrated In Figure 21 and 22.

TABLE 10 - MCU VECTOR LOCATIONS'

MSB LSB Interrupt

$FFFE FFFF RESET"
FFFC FFFD NMI
FFFA FFFB Software Interrupt ISWIJ
FFF8 FFF9 IRQt lor IS31
FFF6 FFF7 ICF Iinput Capturel
FFF4 FFF5 OCF 10utput Compare)
FFF2 FFF3 TOF !Tomer Overflow)
FFFO FFFI SCI IRDRF + ORFE+ TORE!
These )ocatlons are relocated at $BFFO-$BFFF In Mode 0
""Highest PriOrity

4-736
 FIGURE 31 - INTERRUPT FLOWCHART s::
()

~
....
~
s::•
()
~
.....
.....
N

s::•
()

~
.....
!?.....
s::•
()
~
.....
""'"
.!..J
c.v .....
N
-....J .....
I

SCI ~ TIEoTDRE+ RIEoIRDRF+ ORFEI

Vector- PC
Mode 0 Modes 1-7
NMI BFFC-BFFD FFFC-FFFDINon-Maskable Interrupt
SWI BFFA-BFFB FFFA-FFFB I Software Interrupt
IRQl BFF8-BFF9 FFF8-FFF9 I Maskable Interrupt Request 1
ICF BFF6-BFF7 FFF6-FFF7 Iinput Capture Interrupt
OCF BFF4-BFF5 FFF4-FFF5 IOutput Compare Interrupt
TOF BFF2-BFF3 FFF2-FFF3 IT,mer Overflow Interrupt
SCI BFFO-BFFI FFFO-FFFI ISCI Interrupt !TDRE + RDRF + ORFE)

•
 MC68120-MC68121-MC68120-1-MC68121-1

FIGURE 32 - INTERRUPT SEQUENCE

Last In!>tructlon...j
Cycle
#1 #2 #3 #4 #5 #6 #7 #8 #9 #10 #11 #12 I

Op Code OD Code SPIn) SPin - 61 SPin - 7) Vector Vector

Addr Addr+ 1 MSB Addr LSB Addr Address

NMI or IR02 \
---I !--tpcs First Ins! of
Interrupt Routine
Internal -----.r----.,r-~.r--"V"--_v--"""--"""-- .......
r_-~..,_--_V--_V---V_--V_--"--,

DataBUS-----J'---~~a-p-c-O-d~e~a-p-c-Od-e~-PC-O--7~P-C-8---1b~-X-O--7~-X-8--15-/'-A-C-CA~''--A-CC-8-/'-C-C-R-J''-I,-'e-le-va-'-l'~-ve-c-to-,'~-ve-c-to-,~---r
_--==-__________--;+ 1 Data MSB LSB
Internal R/W
\'-------------------------~I

II
PROGRAMMABLE TIMER

The Programmable Timer can be used to perform input when clear, the Interrupt IS inhibited, It IS
waveform measurements while Independently generating an cleared by rese,t,
output waveform, Pulse widths can vary from several Bit 3 EOCI Enable Output Compare Interrupt When set, an
microseconds to many seconds, A block diagram of the IR02 Interrupt IS enabled for an output com-
Timer is shown in Figure 33, pare, when clear, the Interrupt IS Inhibited, It IS
cleared by reset.
TIMER CONTROL AND STATUS REGISTER ($08) Bit 4 EICI Enable Input Capture Interrupt, When set, an
The Timer Control and Status Register (TCSRI IS an 8-blt IR02 Interrupt IS enabled for an Input capture,
register of which all bits are readable while bits 0-4 can be when clear, the Interrupt IS Inhibited, It IS
wntten, The three most significant bits provide the timer cleared by reset
status and they indicate: Bit 5 TOF Timer Overflow Flag, TOF IS set when the
_ a proper level transition has been detected, or counter contains alil's, It IS cleared by reading
- a match has been found between the free-running the TCS R (With TOF setl followed by reading
counter and the output compare register, or the highest byte of the counter ($091, or by
_ the free-running counter has overflowed, reset Reading the counter at $15 Will not clear
TOF
Each of the three events can generate an IR02 Interrupt
and IS controlled by an Individual enable bit In the TCSR Bit 6 OCF Output Compare Flag OCF IS set when the Out-
put Compare Register matches the free-running
TIMER CONTROL AND STATUS REGISTER
counter It IS cleared by reading the TCS R (With
ITSCRI
OCF setl and then wntlng to the Output Com-
6 543 2 1 0 pare Register I$OB or $OCI, or by reset.
ICF I OCF I TOF I EICII EOCII ETO'IIEDG I OLVL I $08 Bit 7 ICF Input Capture Flag ICF IS set to indicate a pra-
per level transition-It IS cleared by reading the
Bit 0 OLVL Output level. OLVL IS clocked to the output level TCSR (With ICF setl and then reading the Input
register by a successful output compare and Will Capture Register High Byte ($001, or by reset,
appear at P21 If Bit 1 of the Port 2 Data DirectIOn COUNTER ($09:0AI
Register IS set It IS cleared by reset
The key timer element IS a 16-blt free-running counter
Bit 1 IEDG Input Edge, IEDG IS cleared by reset and con- which IS Incremented by E IEnablel It IS cleared dunng reset
trols which level transition Will tngger a counter and IS a read-only With one exception' a write to the counter
transfer to the Input Capture Register. 1$091 Will preset It to $FFFB ThiS feature, Intended for
IEDG = 0 Transfer on a negative edge testing, can disturb senal operations because the counter
IEDG = 1 Transfer on a positive edge proVides the SClmternal bit rate clock TOF IS set whenever
Bit 2 ETOI Enable Timer Overflow Interrupt When set, an the counter contains alil's, The counter may also be read at
IR02 interrupt IS enabled for a timer overflow; location $15 and $16 to aVOid the cleanng of the TOF,

4-738
MC68120-MC68121-MC68120-1-MC68121-1

FIGURE 33 - PROGRAMMABLE TIMER - BLOCK DIAGRAM

MC68120/MC68121 Internal Bus

__
Timer 'r'':T~='"'=..., ===~~'''

•
Control 'r---Lr....,r'-.&.;..~~.;..L-r.....-'='-J
and
Status
Register
$08 Bit 1
Port 2
DDR

IRQ2
Output Compare Pulse ___ _ I Output Input
Level Edge
Bit 1 Bit a
Port 2 Port 2

OUTPUT COMPARE REGISTER ($OB:OC) INPUT CAPTURE REGISTER ($OD:OE)

The Output Compare Register IS a 16-blt Read/Write The Input Capture Register IS a 16-blt read-only register
register used to control an output waveform or provide an ar- used to store the free-running counter when a "proper" in-
bitrary timeout flag It IS compared with the free-running put tranSItion occurS as defined by IEDG Port 2, bit 0 should
counter on each E-cycle. When a match IS found, OCF IS set be configured as an Input, but the edge detect CirCUit always
and OLVL IS clocked to an output level register If Port 2, bit senses P20, even when configured as an output. An Input
1 IS configured as an output, OLVL will appear at P21 The capture can occur Independently of ICF the Input capture
Output Compare Register and OLVL can then be changed register always contains the most current value regardless of
for the next compare The compare function IS Inhibited for whether ICF was previously set or not Counter transfer IS in-
one cycle after a wnte to the high byte of the counter I$OBI hibited, however, between accesses of a double byte IPC
to ensure a valid compare The Output Compare Register IS read. The Input pulse Width must be at least two E-cycles to
set to $FFFF by reset ensure an Input capture under all conditions.

SERIAL COMMUNICATIONS INTERFACE (SCI)

A full-duplex asynchronous Senal Communications Inter- beginning of the message. In order to allow uninterested
face ISCllls proVided with two data formats and a chOice of MPUs to Ignore the remainder of the message, a wake-up
Baud rates The SCI transmitter and receiver are functionally feature IS Included whereby all further SCI receiver flag land
Independent, but use the same data format and bit rate Interrupti processing can be Inhibited until the data line goes
Senal data formats Include standard mark/space INRZI and Idle. An SCI receiver IS re-enabled by an Idle stnng of ten
BI-phase. Both formats proVide one start bit, eight data bitS, consecutive l' s or by reset Software must proVide the re-
and one stop bit. "Baud" and "bit rate" are used qUired Idle stnng between consecutive messages and pre-
synonymously In the following descnptlon vent It within messages.

WAKE-UP FEATURE PROGRAMMABLE OPTIONS

In a typical senal loop multi-processor configuration, the The follOWing features of the SCI are programmable:
software protocol Will usually Identify the addresseelsl at the _ format· standard mark/space INRZI or BI-phase

4-739
 MC68120-MC68121-MC68120-1-MC68121-1

_ clock: external or internal clock source RATE AND MODE CONTROL REGISTER IRMCR)
a
_ Baud rate: one of four per E-clock frequency, or one-
eighth of the external clock input to P22
_ wake-up features: enabled or disabled
ex 7
I x
6
I
5
x I
432
x
1
I CCl I CCO I SSl I SSO I $10
Bit1: Bit a SS1.SS0Speed Select. These two bits select
_ interrupt requests: enabled individually for transmitter the Baud rate when usmg the internal clock
and receiver Four rates may be selected which are a function
• clock output: internat bit rate clock enabled or disabled of the IPC input frequency (EI. Table 11 lists bit
to P22 times and rates for three selected I PC frequen-
cies.
SERIAL COMMUNICATIONS REGISTERS Bit 3: Bit 2 CC1. CCO Clock Control and Format Select
The Serial Communications Interface includes four ad- These two bits control the format and select the
dressable registers as depicted In Figure 34. It is controlled senal clock source. If CC11s set. the Data Direc-
by the Rate and Mode Control Register and the tIOn Register (DDRI value for P22 IS forced to
Transmit/Receive Control and Status Register. Data IS the complement of CCO and cannot be altered
transmitted and received utilizing a wnte-only Transmit until CC1 IS cleared. If CC1 IS cleared after hav-
Register and read-only Receive Register. The shift registers Ing been set, Its DDR value IS unchanged Table
are not accessible by software. 12 defmes the format. clock source. and use of
P22
Rate and Mode Control Regiater ($10) - The Rate and If both CC1 and CCO are set, an external TTL compatible
Mode Control Register (RMCR) controls the SCI Baud rate. clock must be connected to P22 at eight times (8XI the
format, clock source, and under certam conditions, the con- deSired Baud rate. but not greater than E. with a duty cycle
figuration of P22. The register consists of four write-only bits of 50% (± 10% I. If Ce1.CCO= 10, the Internal Baud rate

I
which are cleared by reset The two least significant bits con- clock IS proVided at P22 regardless of the values for TE or RE
trolthe Baud rate of the internal clock and the remaining two
bits control the format and clock source. NOTE: The source of SCI Int~rnal baud rate clock IS the
free-running counter of the timer. An IPC write to the
counter can disturb senal operations.

FIGURE 34 - SCI REGISTERS

Bit 7 Rate and Mode Control Register Bit a
I I I
CCl CCO sSllssol $10

Transmit/Receive Control and Status Register

IRDRF IORFEfDREI I I AtE RE TIE TE I

WU 1$11

Receive Data Register

$12

Port 2
(Not Addressable)

Receive Shift Register

45

Transmit Shift Register

47

$13

T ransmtt Data Register

4·740
MC68120-MC68121-MC68120-1-MC68121-1

TABLE 11 - SCI BIT TIMES AND RATES

SSI:SS0 E 614.4 kHz 1.0 MHz 1.2286 MHz
0 0 +16 26 ~s/38,400 Baud 16 ~s/62,500 Baud 13 0 ~sI76,BOO Baud
0 1 +12B 208 ~s/4,BOO Baud 12B ~s17B12 5 Baud 104 2 ~s/9,BOO Baud
1 0 +1024 1 67 ms/BOO Baud 1 024 ms/976.6 Baud B33 3 ~s/ 1,200 Baud
1 1 +4096 6 67ms/ 150 Baud 4 096 ms/244 1 Baud 3 33 ms/300 Baud

TABLE 12 - SCI FORMAT AND CLOCK SOURCE CONTROL will be transmitted only If TORE has been
Clock Port 2 cleared.
CC1:CCO Format Bit 60RFE Overrun Framing Error. If set, ORFE ,nd,cates
Source B~ 2
0 0 B,-Phase Internal Not Used either an overrun or framing error. An overrun
0 1 NRZ Internal Not Used
occurs when a new byte is ready to transfer to
the Receiver Data Register with RDRF stili set.
1 0 NRZ Internal Output
A receiver framing error has occurred when
1 1 NRZ External Input
the byte boundaries of the bit stream are not
synchronized to the bit counter. An overrun
Transmit/Receive Control and Status Register ($11) - can be distinguished from a framing error by
The Transmit/Receive Control and Status Register (TRCSR) the value of RDRF: If RDRF IS set, then an
controls the transmitter, receiver, wake-up features, and two overrun has occurred, otherwise, a framing er-
individual Interrupts and monitors the status of senal opera- ror has been detected. Data IS not transferred

II
tions. All eight bits are readable while only bits 0 to 4 are to the Receive Data Register In an overrun
wntable. The register IS initialized to $20 by reset. condition. ORFE IS cleared by reading the
TRCSR (With ORFE set) then reading the
TRANSMIT / RECEIVE CONTROL AND STATUS REGISTER
Receive Data REl9lster, or by reset.
(TRCSR)
Bit 7 RDRF Receive Data Register FUll. RDRF IS set when
7 654 3 0
IRDRFIORFEITDREI RIE I RE I TIE TE WU $11
the contents of the Input senal shift register IS
transferred to the Receive Data Register. It IS
B,tOWU "Wake-up" on Idle Line. When set, WU cleared by reading the TRCSR (With RDRF
enables the wake-up function, It IS cleared by set), and then reading the Receive Data
ten consecutive 1's or by reset WU will not set Register, or by reset.
If the line IS Idle.
Bit 1 TE Transmit Enable. When set, the P24 DDR bit IS
set, cannot be changed, and will remain set If
TE IS subsequently cleared When TE IS SERIAL OPERATIONS
changed from clear to set, the transmitter IS The SCI IS Initialized by writing the control bytes first to
connected to P24 and a preamble of nine con- the Rate and Mode Control Register and then to the
secutive 1's IS transmitted TE IS cleared by Transmit/Receive Control and Status Register. When TE IS
reset set, the output of the Transmit Shift Register IS connected to
P24 and senal output IS Initiated by the transmiSSion of a
Bit 2 TIE Transmit Interrupt Enable When set, an IR02
9-blt preamble of 1's.
Interrupt IS enabled when TDRE IS set. when
At thiS pOint one of two situatIOns exist: 1) If the Transmit
clear, the Interrupt IS Inhibited. TIE IS cleared
Data Register IS empty (TDRE= 1), a continuous string of 1'5
by reset.
Will be sent indicating an Idle line, or 2) If a byte has been
Bit 3 RE Receive Enable. When set, the P23 DDR bit IS wntten to the Transmit Data Register (TDRE=O), the byte
cleared, cannot be changed, and Will remain
Will be transferred to the Transmit Shift Register (syn-
clear If RE IS subsequently cleared. While RE IS
chrOnized With the bit rate clock), TORE Will be set, and
set, the SCI receiver IS enabled. RE IS cleared
transmission will begin ..
by reset
The start bit (0), eight data bits (beginning With bit Ol and a
Bit 4 RIE Receiver Interrupt Enable. When set, an IR02 stop bit (1), will be transmitted. I! TORE IS still set when the
Interrupt IS enabled when RDRF and/or OR FE next byte transfer should occur, 1's Will be sent until more
IS set; when clear, the Interrupt IS inhibited. data IS proVided. Receive operation is controlled by RE which
RIE is cleared by reset. configures P23 as an input and enables the receiver. In BI-
Bit 5 TDRE Transmit Data Register Empty TDRE IS set phase format, the output toggles at the start of each bit and
when the contents of the Transmit Data at hal! time when a "1" IS sent. SCI data formats are il-
Register IS transferred to the output senal shift lustrated in Figure 35. In receiVing BI-phase, a "1" IS input
register or by reset. It IS cleared by reading the when two transitions occur In less than 3/4 blt-tlme, and a
TRCSR (With TORE set) and then writing to "0" is Input when more than 3/4 bit-time passes after a tran-
the Transmit Data Register Additional data SItIOn on P23.

4·741
 MC68120-MC68121-MC68120-1-MC68121-1

FIGURE 36 - SCI DATA FORMATS

Output
Clock

NAZ
Format

BI-Phase
Format
Bit Bit
Idle Start 0 Stop
2 4 5 6 7
Data 01001101 ($401

INSTRUCTION SET

II
The MC68120/MC68121 is upward source and object code E-cycies Instruction execution times are summanzed In
compatible With the MC6800 processor and directly compati- Ta.ble 17. With an Input frequency (E) of 1 MHz, E-cycles are
ble with the M6801 Family processors. eqUivalent to microseconds. A cycle-by-cycle description of
bus actiVity for each instruction IS provided In Table 18 and a
descnption of selected Instructions IS shown In Figure 38.
PROGRAMMING MODEL
A programming model for the MC68120/MC68121 IS Immediate Addressing - The operand IS contained In the
shown In Figure 14. Accumulator A can be concatenated follOWing byte(s) of the instruction where the number of
with accumulator B and jOintly referred to as accumulator D bytes matches the size of the register. These are two or three
where A is the most significant byte. Any operation which byte Instructions.
modifies the double accumulator will also modify ac-
cumulator A and/or B. Other registers are defined as Direct Addressing - The least Significant byte of the
follows: operand address IS contained In the second byte of the in-
Program Counter - The program counter IS a 16-blt struction and the most significant byte IS assumed to be $00.
register which always pOints to the next instruction. Direct addreSSing allows the user to access $00 through $FF
uSing two byte Instructions and execution time IS reduced by
Stack Pointer - The Stack Pointer IS a 16-blt register eliminating the additional memory access (refer to Table 1)
which contains the address of the next available location In a In most applications, thiS 256-byte area IS reserved for fre-
pushdown/pullup (LiFOI queue The stack resides In ran-
quently referenced data. Note that no direct addreSSing of
dom access memory at a location specified by the software.
Internal control registers IS pOSSible In Mode 3
Index Register - The Index Register IS a 16-blt register
which can be used to store data or provide an address for the Extended Addressing - The second and third bytes of the
Indexed mode of addreSSing instruction contain the absolute address of the operand.
These are three byte Instructions
Accumulators - The IPC contains two 8-bit ac-
cumulators, A and B, which are used to store operands and Indexed Addressing - The unSigned offset contained In
results from the arithmetic logic unit (ALUI. They can also be the second byte of the Instructions IS added With carry to the
concatenated and referred to as the D (doublel accumulator. Index Register and used to reference memory Without
Condition Code Register - The Condition Code Register changing the Index Register These are two byte instruc-
,nd,cates the results of an Instruction and Includes the tions.
follOWing five condition bits' Negative (NI, Zero (ZI,
Overflow (VI, Carry/Borrow from MSB (CI, and half carry Inherent Addressing - The operand(s) are registers and
from bit 3 (H I. These bits are testable by the conditional no memory reference IS reqUired. These are single byte In-
branch Instructions Bit 4 IS the Interrupt mask (I-bltl and In- structions.
hibits all maskable Interrupts when set. The two unused bits
b6 and b7, are read as ones. Relative Addressing - Relative addreSSing IS used only for
branch Instructions. If the branch condition IS true, the Pro-
ADDRESSING MODES gram Counter IS overwntten With the sum of a Signed single
The MC68120/MC68121 provides SIX addreSSing modes byte displacement In the second byte of the Instruction and
which can be used to reference memory A summary of ad- the current Program Counter. ThiS provides a branch range
dressing modes for all instructions IS presented In Tables 13, of - 126 to 129 bytes from the first byte of the instruction
14, 15 and 16 where execution times are provided In These are two byte instructions.

4·742
MC68120·MC68121·MC68120-1·MC68121-1

TABLE 13 - INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS

Condition Codes
Immed Direct Index Extnd Inherent 5 4 3 2 1 0
Pointer Operations Mnemonic Of - # OP- # OP- # OP- # OP-'- # Booleanl H I N Z V C
Arithmetic Operation
Compare Index Reg CPX 8C 4 3 9C 5 2 AC 6 2 BC 6 3 IX-M M +1
•• I , t t
•• •
• • •• •• •
Decrement Index Reg DEX 09 3 1 IX - 1 -X
Decrement Stack Pntr DES 34 3 1 SP - 1 -SP
Increment Index Reg INX OB 3 1 X + I - X
• • •••
Increment Stack Pntr INS 31 3 1 1 SP + 1 -SP
•••••
load Index Reg LOX CE 3 3 DE 4 2 EE 5 2 FE 5 3 M -XH, 1M + I)-Xl
•• R
load Stack Pntr LOS 8E 3 3 9E 4 2 AE 5 2 BE 5 3 M -SPH, 1M + I) -SPl
•• R
Store Index Reg STX OF 4 2 EF 5 2 FF 5 3 XH -M, Xl -1M + I)
•• R
Store Stack Pntr STS 9F 4 2 AF 5 2 BF 5 3 SPH -M, SPl -1M + 1)
•• R
Index Reg Stack Pntr TXS 35 3 1 X-I -SP
•••••
Stack Pntr
Add
Index Reg TSX
ABX
30 3
3A 3
1 SP + I - X
1 B +X-X
•• •• •• •• ••
Push Data PSHX 3C 4 1 Xl -MSp, SP - 1 -SP
XH -MSR SP - 1 -SP
•••••
Pull Data PULX 38 5 1 SP + 1 -SP, MSp -XH
••••••

•
SP + 1 -SP, MSp -XL

TABLE 14 - ACCUMULATOR AND MEMORY INSTRUCTIONS

Accumuiator and Immed Direct Index Extend Inher Boolean Condition Codes
Memory Operations MNE Op # Op - # Op # Op # Op - # Expression H I N Z V C
Add Acmltrs ABA lB 2 1 A + B-A
•
AddBtoX
Add With Carry
ABX
ADCA 89 2 2 99 3 2 A9 4 2 B9 4 3
3A 3 1 OOB+X-X
A+M+C-A
• •• • • • •
Add
ADCB
ADDA
C9 2 2 09 3 2 E9 4 2 F9 4 3
88 2 2 9B 3 2 AB 4 2 BB 4 3
8+M+C--B
A + M--A
••
••
ADDB CB 2 2 DB 3 2 EB 4 2 FB 4 3 B+ M-A
Add Double ADDD C3 4 3 03 5 2 E3 6 2 F3 6 3 0+ M M + 1-0

•• ••
And ANDA 84 2 2 94 3 2 A4 4 2 B4 4 3 A'M-A R
ANDB C4 2 2 04 3 2 E4 4 2 F4 4 3 B'M-B R
Shift Left, ASL 68 6 2 7B 6 3
Arithmetic ASLA 48 2 1
ASLB 58 2 1
Shift Le Obi ASLD 05 3 1
Sh,lt Right, ASR 67 6 2 77 6 3 I
Anthmetlc ASRA 47 2 1
ASRB 57 2 1
Bit Test BITA
BITB
85 2 2 95 3 2 A5 4 2 B5 4 3
C5 2 2 05 3 2 E5 4 2 F5 4 3
A·M
B'M
R
R
••
Compare Acmltrs CBA 11 2 1 A,B I
Clear CLR 6F 6 2 7F 6 3 OO-M R S R R
CLRA 4F 2 1 00 -A R S R R
CLRB 5F 2 1 OO-B R S R R
Compare CMPA 81 2 2 91 3 2 Al 4 2 Bl 4 3 A,M I I
CMPB Cl 2 2 01 3 2 El 4 2 Fl 4 3 B, M I
1 's Complement COM 63 6 2 73 6 3 IM-M R S
COMA 43 2 1 A-A R S
COMB 53 2 1 ii-B R S
DeCimal Ad), A OM 19 2 1 AdJ binary sum to BCD
Decrement DEC
DECA
6A 6 2 7A 6 3 M,I-M
4A 2 1 A, I - A
••
Excl uSlve OR
DECB
EORA B8 2 2 9B 3 2 AB 4 2 BB 4 3
5A 2 1 B,1
A @ M-A
B
R
••
EORB CB 2 2 DB 3 2 EB 4 2 F8 4 3 B @ M-B I R •
- Contlnued-

4-743
 MC68120-MC68121-MC68120-1-MC68121-1

TABLE 14 - ACCUMULATOR AND MEMORY INSTRUCTIONS (CONTINUED)

Accumulator and Immed Diract Index Extend Inher Boolean Condition C odes
MNE # Op # :>p H
Memory Operations Op - # Op - # Op # Expression N Z V C
Increment INC
INCA
16C 16 12 7C 16 3
4C 2
M+ 1-M
1 A + 1-A
\
! •
•
INCB 5C 2 1 B + 1 -B I •
Load Acmltrs LDAA
LDAB
B6 2
C6 2
2 96 3
2 D6 3
2 A6 4
2 E6 4
2 B6 4
2 F6 4
3
3
M-A
M-B
R
R
••
Load Double
Logical Shift,
LDD
LSL
CC 3 3 DC 4 2 EC 5
68 6
2 FC 5
2 78 6
3
3
M M + 1-D R
•
Left LSLA 48 2 1
LSLB 58 2 1
LSLD 05 3 1
Shift Right, LSR 64 6 2 74 6 3 R
Logical LSRA 44 2 1 R
LSRB 54 2 1 R
LSRD 04 3 1 R
Multiply
2's Complement
(Negate)
MUL
NEG
NEGA
60 6

,
2 70 6 3
3D

40
10 1 AXB-D
00 - M-M
2 1 00 - A-A
•! •
T
I
-
j

-•••
NEGB 50 2 1 00 - B-B
No Operation NOP 01 2 1 PC + 1 -PC
• •

•
Inclusive OR DRAA 8A 2 2 9A 3 2 AA 4 2 BA 4 3 A + M--A R
DRAB CA 2 2 DA 3 2 EA 4 Z FA 4 3 B + M-B TT R
Push Data PSHA 36 3 1 A -Stack
•
••• •• ••
••
PSHB 37 3 1 B --Stack

•j ••I ••I
Pull Data PULA 32 4 1 Stack -A

Rotate Left
PULB
ROL 69 6 2 79 6 3
33 4 1 Stack -B
•I
ROLA 49 2 1 I
ROLB 59 2 1 I
Rotate Right ROR 66 6 2 76 6 3 I I
RORA 46 2 1 I
RORB 56 2 1
Subtract Acmltr SBA 10 2 1 A- B-A
Subtract with SBCA 82 2 2 92 3 2 A2 4 2 B2 4 3 A-M C-A
Carry S8CB C2 2 2 02 3 2 E2 4 2 F2 4 3 B - M - C-B
Store Acm Itrs STAA 97 3 2 A7 4 2 B7 4 3 A-M R
•
STAB
STD
D7
DD
3
4
2 E7 4
2 ED 5
2 F7 4
2 FD 5
3
3
B-M
o -MM + 1
R
R
••
Subtract SUBA BO 2 2 90 3 2 AD 4 2 BO 4 3 A- M-A I I
SUBB CO 2 2 DO 3 2 EO 4 2 FO 4 3 B - M-B '\
Subtract Double SUBD B3 4 3 93 5 2 A3 6 2 B3 6 3 D - M M + 1 -D I j I
Transfer Acmltr TAB 16 2 1 A-a R
•
Test, Zero or
TBA
TST 6D 6 2 7D 6 3
17 2 1 B-A
M - 00
R
R
•
R
MinUS TSTA 4D 2 1 A - 00 R R
TSTB 5D 2 1 B - 00 j j R R

The CondItion Code Register notes are listed after table 16

4-744
MC68120· MC68121. MC68120-1. MC68121-1

TABLE 15 - JUMP AND BRANCH INSTRUCTIONS

Condo Code Reg

Direct Relative Index Extnd Inheren 5 4 3 2 1 0
Operations Mnemonic OP -# OP - # OP- # OP - # OP - Branch Test H I N Z V C
Branch Always BRA 20 3 2 None
••••••
Branch Never BRN 21 3 2 None
••••••
Branch If Carry Clear BCC 24 3 2 c-o
••••••
Branch If Carry Set BCS 25 3 2 C- 1
••••••
Branch If - Zero BEQ 27 3 2 Z- 1
••••••
Branch If :? Zero BGE 2C 3 2 N(t)V-O
••••••
Branch If > Zero BGT 2E 3 2 Z + (N(t)V) - 0
••••••
Branch If Higher BHI 22 3 2 C+Z-O
••••••
Branch If Higher or Same BHS 24 3 2 C -0
••••••
Branch If < Zero BLE 2F 3 2 Z + (N (t)V) - 1
••••••
Branch If Carry Set
Branch If Lower Or Same
BLO
BLS
25 3 2
23 3 2
C- 1
C+Z- 1
•• ••••
• • •• ••
Branch If < Zero BLT 20 3 2 N(t)V - 1
••••••
Branch If Mmus BMI 2B 3 2 N- 1
••••••
Branch If Not Equal Zero BNE 26 3 2 Z 0
••••••
••••••

•
Branch If Overflow Clear BVC 28 3 2 v-o
Branch If Overflow Set BVS 29 3 2 V-I
••••••
Branch If Plus BPL 2A 3 2 N=O
••••••
Branch To Subroutine BSR 806 2
} See Special ••••••
Jump JMP 6E 3 2 7E 3 3 Operations -
••••••
Jump To Subroutine JSR 905 2 AD 6 2 BD 6 3 Figure 38
••••••
No Operation
Return From Interrupt
NOP
RTI
01 2 1
3B 0 1
• • •I !,• III
• •,
I
"
!
Return From Subroutine RTS 39 5 1 } See Special
1 Operatlons- ••••••
Software Interrupt SWI 3F 2
Figure 38 • •••• S
Walt For Interrupt WAI 3E 9 1
• •• •••
TABLE 16 - CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS

Inherent 5
Cond Code Reg
4 3 2 , 0
Operations MnemoniC OP - # Boolean Operation H I N Z V C
Clear Carry CLC oe 2 1 o -e
••••• R
Clear Interrupt Mask eLi OE 2 1 0-1
• ••••
R
Clear Overflow CLV OA 2 1 O-V
•• • •• •• • R
Set Carry SEe 00 2 1 1 -e
• • S
Set Interrupt Mask SEI OF 2 1 1-1
• ••••
S
Set Overflow SEV
TAP
OB 2 1 1 -V
•••• • S
Accumulator A --CCR 06 2 1 A-eCR ill I I Ii
CCR --Accumulator A TPA 07 2 1 eCR -A
••••••
LEGEND CONDITION CODE SYMBOLS
OP Operatton Code (Hexadeci mal)
H Half-carry from bit 3
- Number of MPU Cycles
I Interrupt mask
MSp Contents of memory location pOinted to by Stack POinter
N Negative (sign bit)
# Number of Program Bytes Z Zero (byte)
+ Arithmetic Plus V Overflow, 2's complement
- ArithmetIc Mmus C Carry/Borrow from MSB
• Boolean AND R Reset Always
X Arithmetic Multiply S Set Always
+ Boolean InclUSIve OR
@ Boolean ExclusIve OR
I Affected
• Not Affected
iiii Complement of M
-- Transfer Into
OBit = Zero
00 Byte = Zero

4-745
 MC68120·MC68121·MC68120-1·MC68121-1

TABLE 17 - INSTRUCTION EXECUTION TIMES IN E-CYCLES

ADDRESSING MODE ADDRESSING MODE

S ...
.!
"i 1j
"i
...
c
...
II
C
!II ...~ ....1
II 1j
...c
II ...
II
~
C
!II ~
.§
E
is
! ~
III
..."
II

.E
.c
.E
.!!
II
a: .§
E !
is
~
w
....EII .c
.E
.!!
a:"
ABA •• •• •• •• • 2 INX
•• •• •3 • •• •
3

•• •••
ABX 3 JMP 3
ADC
ADD
2
2
3
3
4
4
4
4
JSA
lOA •2 5
3
6
4
6
4
••
ADDD
AND
4
2
5
3
6
4
6
4
•• •••
lDD
lOS
3
3
4
4
5
5
5
5
•
••• •• •• •• • • •
ASL 6 6 2 lOX 3 4 5 5
ASLD
• • 3 • lSl 6 6 2

••• •
ASR 6 6 2 lSlD 3

••• ••• •• • •• •• • •
BCC 3 lSA 6 6 2

•• •••
BCS 3 lSRD 3
BEO
• ••• ••
3 MUl
• • • • 10

••2 ••
BGE 3 NEG 6 6 2

••• •• •• • •
BGT NOP 2

•
3
•• •• •• • •
BHI 3 OAA 3 4 4
BHS • •• 3 , PSH
••• ••• •• 3
BIT
••
2 3 4 4
•3 PSHX 4

••• •• •• •• •• ••
BlE PUl 4
BlO
• ••
3 PUlX
••• •• 5

••• •
BlS 3 AOl 6 6 2
BlT
• 3 AOA
•• •• 6 6 2

••• ••• ••• •••

8MI 3 ATI 10
BNE
BPl
•• 3
3
ATS
SBA •2 •• 5
2

••• ••• • •• •
BAA 3 SBC 3 4 4

••• ••• ••• ••

BAN 3 SEC 2
BSA 6 SEI 2
BVC
••• • 3 SEV
•• • • 2

••• •2 •••
BVS 3 STA 3 4 4
CBA STD 4 5 5
ClC
Cli
•• ••
2
2
STS
STX •• 4
4
5
5
5
5
• •
••2 ••
ClA 6 6 2 SUB 2 3 4 4
ClV • • • • 2 SUBD 4 5 6 6

••• •• •• •••
CMP 3 4 4 SWI 12
COM
• • 6 6 2 TAB 2

•• • • • ••• ••
CPX 4 5 6 6 TAP 2
DAA
DEC
•• 6 6
2
2
TBA
TPA •• • ••
2
2
DES •• •• •• ••
3 TST
• •• 6 6 2

••• •• ••
DEX 3 TSX 3
EOA
••
2 3 4 4
•• TXS •• • •
3

••
INC 6 6 WAI 9
INS • • 3

4-746
MC68120e MC68121 e MC68120-1 e MC68121-1

FIGURE 36 - SPECIAL OPERATIONS

JSR, Jump to Subroutine

PC
{
Direct RTN t=:::~=:;::::::::::::j

PC
{
INDXD RTN t::;:;~~~ft:;=j
PC

{
EXT ND I--:cS'-L_--cS::':uc:.b,--:-Ad::':d:-,--j
RTN Next Main Instr

BSR, Branch 1(0 Subroutine

SP Slack

•
______ SP - 2 ~----~

SP-1

RTN '--'-=~_"--..J
SP

RTS, Return from Subroutine

PC I
Subroutine
$39-ATS
I q ~:EEStack
SP.+-l
______ SP+2
RTNH
RTNL

SWI, Software Interrupt

I q
Main Program SP Stack
SWI ______ SP - 7
$3'
R:: I SP-6
SP-5
Condition Code
Acmltr B
SP-4 Acmltr A
WAI, Walt for Interrupt SP-3 Index Register IXHI

Iq
Main Program SP-2 Index Register (XU

R~: f
$3E WAI SP-l RTNH
SP RTNL

ATI, Return from Interrupt

PC I
Interrupt Program

$38-RTI I q SP
SP
SP+ 1
Stack

Condition Code
SP+2 Acmltr B
SP+3 Acmltr A
SP+4 Index Register (XH)
SP+5 Irldex Register (XL
SP+6 RTNH
--'SP+7 RTNL

JMP, Jump

E Main Program

{'
PC $6E-JMP
K-Offset
Extended
INDXD{

X+K Next Instruction K I Next InstruClion

I
Legend
RTN = Address of next Instruction In Mam Program to be executed upon return from subroutine -.= Stack pOinter after execution
RTNH=MosI significant byte of Return Address K = 8-blt unsigned value
RTNL = Least significant byte of Return Address

4-747
 MC68120-MC68121-MC68120-1-MC68121-1

CYClE-BY-CYClE OPERATION SUMMARY

Table 18 provides a detailed descrlptton of the Information Note that dUring M PU reads of tnternal locations, the
present on the Address Bus, Data Bus, and the R/Vii hne resultant value Will not appear on the external Data Bus ex-
during cycle of each Instructions. cept In Mode 0 "High order" byte refers to the most slgntfl-
The mformation IS useful In comparing actual with ex- eant byte of a 16-blt value.
pected results during debug of both software and hardware The coding of the first (or only) byte correspondtng to an
as the program IS executed. The information is categorized In executable mstructlon IS suffiCient to Identify the tnstructlon
groups according to addressing mode and number of cycles and the addreSSing mode The hexadecimal eqUivalents of
per Instruction. In general, Instructions with the same ad- the binary codes, which result from the translation of the 82
dressing mode and number of cycles execute In the same instructions In all vahd modes of addreSSing, are shown 10
manner. Exceptions are mdlcated In the table. Table 19 There are 220 vahd machtne codes, 34 unassigned
codes and 2 reserved for test purposes

TABLE 18 - CYCLE BY CYCLE OPERATION

Address Mode II
Address Bus
RIW Data Bus
Instructions Line
IMMEDIATE
ADC EOR 2 1 Op Code Address 1 Op Code
2 Op Code Address + 1

•
ADD LOA 1 Operand Data
AND ORA
BIT SBC
CMP SUB
LOS
LOX
3 1
2
Op Code Address
Op Code Address + , ,
1 Op Code
Operand Data (High Order Byte)
LOD 3 Op Code Address + 2 1 Operand Data (Low Order Byte)
CPX 4 1 Op Code Address 1 Op Code
SUBD 2 Op Code Address + 1 1 Operand Data (High Order Byte)
ADDO 3 Op Code Address + 2 1 Operand Data (Low Order Byte)
4 Address Bus FFFF 1 Low Byte of Restart Vector
DIRECT
ADC EOR 3 , Op Code Address 1 Op Code
ADD LOA 2 Op Code Address + 1 1 Address of Operand
AND ORA 3 Address of Operand 1 Operand Data
BIT SBC
CMP SUB
STA 3 , Op Code Address 1 Op Code
2 Op Code Address + , 1 Destination Address
3 Destmatlon Address 0 Data from Accumulator
LOS 4 1 Op Code Address 1 Op Code
LOX 2 Op Code Address + 1 1 Address of Operand
LDD 3 Address of Operand 1 Operand Data (High Order Byte)
4 Operand Address + 1 1 Operand Data (Low Order Byte)
STS 4 1 Op Code Address 1 Op Code
STX 2 Op Code Address,. 1 1 Address of Operand
STD 3 Address of Operand 0 Register Data (High Order Byte)

CPX 5 ,
4 Address of Operand + 1
Op Code Address
0
1
Register Data (Low Order Byte)
Op Code
SUBD
ADOD
2
3
Op Code Address + 1
Operand Address ,
1 Address of Operand
Operand Data (High Order Byte)
4 Operand Address + 1 1 Operand Data (Low Order Byte)

JSR 5 ,
5 Address Bus FFFF
Op Code Address
1
1
Low Byte of Restart Vector
Op Code
2 Op Code Address + 1 1 Irrelevant Data
3 Subroutine Address 1 First Subroutine Op Code
4 Stack Pomter 0 Return Address (Low Order Byte)
5 Stack POinter + 1 0 Return Address (Hloh Order Byte)

- Contmued-

4·748
MC68120-MC68121-MC68120-1-MC68121-1

TABLE 18 - CYCLE BY CYCLE OPERATION (CONTINUED)

Address Mode &

Address Bus
RIW
Instructions Data Bus
line
EXTENDED
JMP 3 1 Op Code Address 1 Op Code
2 Op Code Address + 1 1 Jump Address (High Order Byte)
3 Op Code Address + 2 1 Jump Address (Low Order Byte)
ADC EOA 4 1 Op Code Address 1 Op Code
ADD LOA 2 Op Code Address + 1 1 Address of Operand
AND OAA 3 Op Code Address + 2 1 Address of Operand
(Low Order Byte)
BIT SBC 4 Address of Operand 1 Operand Data
CMP SUB
STA 4 1 Op Code Address 1 Op Code
2 Op Code Address + 1 1 Destination Address
(High Order Byte)
3 Op Code Address + 2 1 Destination Address
(Low Order Byte)
4 Operand Oestln8tlon Address 0 Data from Accumulator
LOS 5 1 Op Code Address 1 Op Code
LOX 2 Op Code Address + 1 1 Address of Operand

II
(High Order Byte)
LDD 3 Op Code Address + 2 1 Address of Operand
(Low Order Byte)
4 Address of Operand 1 Operand Data (High Order Byte)
5 Address of Operand + 1 1 Operand Data (Low Order Byte)
STS 5 1 Op Code Address 1 Op Code
STX 2 Op Code Address + 1 1 Address of Operand
(High Order Byte)
STD 3 Op Code Address + 2 1 Address of Operand
(Low Order Byte)
4 Address of Operand 0 Operand Data (High Order Byte)
5 Address of Operand + 1 0 Operand Data (Low Order Byte)
ASL LSR 6 1 Op Code Address 1 Op Code
ASR NEG 2 Op Code Address + 1 1 Address of Operand
(High Order Byte)
CLA ROL 3 Op Code Address + 2 1 Address of Operand
(Low Order Byte)
COM ROA 4 Address of Operand 1 Current Operand Data
DEC TST 5 Address Bus FFFF 1 Low Byte of Aestart Vector
INC 6 Address of Operand 0 New Operand Data
CPX 6 1 Op Code Address 1 Op Code
SUBD 2 Op Code Address + 1 1 Operand Address
(High Order Byte)
ADDD 3 Op code Address + 2 1 Operand Address
(Low Order Byte)
4 Operand Address 1 Operand Data (High Order Byte)
5 Operand Address + 1 1 Operand Data (Low Order Byte)
6 Address Bus FFFF 1 Low Byte of Restart Vector
JSR 6 1 Op Code Address 1 Op Code
2 Op Code Address + 1 1 Address of Subroutine
(High Order Byte)
/
3 Op Code Address + 2 1 Address of Subroutine
(Low Order Byte)
4 Subroutine Starting Address 1 Op Code of Next Instruction
5 Stack Pomter 0 Return Address
(Low Order Byte)
6 Stack POinter - 1 0 Retum Address
HIQh Order ~~l

- Continued -

4-749
 M C68120- M C68121- M C68120-1- M C68121-1

TABLE 18 - CYCLE BY CYCLE OPERATION (CONTINUED)

Address Mode 8< R/W

Address Bus Data Bus
Instructions Line
INDEXED
JMP 3 1
2
Op Code Address
Op Code Address + 1 ,
1 Op Code
Offset
3 Address Bus FFFF 1 Low Byte of Restart Vector
ADC EOR 4 1 Op Code Address 1 Op Code
ADD LDA 2 Op Code Address + 1 1 Offset
AND ORA 3 Address Bus FFFF 1 Low Byte of Restart Vector
BIT SBC 4 Index Register Plus Offset 1 Operand Data
CMP SUB
STA 4 1 Op Code Address 1 Op Code
2 Op Code Address + 1 1 Offset
3 Address Bus FFFF 1 Low Byte of Restart Vector
4 Index Register Plus Offset 0 Operand Data
LOS 5 1 Op Code Address 1 Op Code
LDX 2 Op Code Address + 1 1 Offset
LDD 3 Address Bus FFFF 1 Low Byte of Restart Vector
4 Index Register Plus Offset 1 Operand Data (High Order Byte)
5 Index Register Plus Offset + 1 1 Operand Data (Low Order Byte)
STS 5 1 Op Code Address 1 Op Code

II STX
STD

ASLLSR
ASR NEG
6
2
3
4
5
1
2
Op Code Address + i
Address Bus· FFFF
Index Register Plus Offset
Index Register Plus Offset + 1
Op Code Address
Op Code Address + 1
1
1
Q
0
1
1
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code
Offset
CLR ROL 3 Address Bus FFFF 1 Low Byte of Restart Vector
COM ROR 4 Index Register Plus Offset 1 Current Operand Data
DEC TST (I) 5 Address Bus FFFF 1 Low Byte of Restart Vector
INC 6 Index Register Plus Offset 0 New Operand Data
CPX 6 1 Op Code Address 1 Op Code
SUBD 2 Op Code Address + 1 1 Offset
AODD 3 Address Bus FFFF 1 Low Byte of Restart Vector
4 Index Register + Offset 1 Operand Data (High Order Byte)
5 Index Register + Offset + 1 1 Operand Data (Low Order Byte)
6 Address Bus FFFF Low Byte of Restart Vector
JSR 6 1 Op Code Address 1 Op Code
2 Op Code Address + 1 1 Offset
3
4
Address Bus FFFF
Index Register + Offset ,
1 Low Byte of Restart Vector
First Subroutine Op Code
5 Stack POinter 0 Return Address (Low Order Byte)
6 Stack POinter - 1 0 Return Address (High Order Byte)

- Contlnued-

4-750
MC68120-MC68121-MC68120-1-MC68121-1

TABLE 18 - CYCLE BY CYCLE OPERATION (CONTINUED)

Address Mode & R/W

Address Bus Data Bus
Instructions Line
INHERENT
ABA OM SEC 2 1 Op Code Address 1 Op Code
ASL DEC SEI 2 Op Code Address +1 1 Op Code of Next Instruction
ASR INC SEV
CBA LSR TAB
CLC NEG TAP
CLI NOP TBA
CLR ROL TPA
CLV ROR TST
COM SBA
ABX 3 1 Op Code Address 1 Op Code
2 Op Code Address +1 1 Irrelevent Data
3 Address Bus FFFF 1 Low Byte of Restart Vector
ASLD 3 1 Op Code Address 1 Op Code
, LSRD 2 Op Code Address +1 1 Irrelevant Data
3 Address Bus FFFF 1 Low Byte of Restart Vector
DES 3 1 Op Code Address 1 Op Code
INS 2 Op Code Address +1 1 Op Code of Next Instruction
3 PrevIOus Reglst~r Contents 1 Irrelevant Data

•
INX 3 1 Op Code Address 1 Op Code
DEX 2 Op Code Address +1 1 Op Code of Next Instruction
3 Address Bus FFFF 1 Low Byte of Restart Vector
PSHA 3 1 Op Code Address 1 Op Code
PSHB 2 Op Code Address +, 1 Op Code of Next Instruction
3 Stack POinter 0 Accumulator Data
TSX 3 1 Op Code Address 1 Op Code
2 Op Code Address +1 1 Op Code of Next Instruction
3 Stack POinter 1 Irrelevant Data
TXS 3 1 Op Code Address 1 Op Code
2 Op Code Address +1 1 Op Code of Next Instruction
3 Address Bus FFFF 1 Low Byte of Restart Vector
PULA 4 1 Op Code Address 1 Op Code
PULB 2 Op Code Address +1 1 Op Code of Next Instruction
3 Stack POinter 1 Irrelevant Data
4 Stack POinter +1 1 Operand Data from Stack
PSHX 4 1 Op Code Address 1 Op Code
2 Op Code Address +1 1 Irrelevant Data
3 Stack POinter 0 Index Reg,ster (Low Order Byte)
4 Stack POinter -1 0 Index Reg,ster (High Order Byte)
PULX 5 1 Op Code Address 1 Op Code
2 Op Code Address +1 1 Irrelevant Data
3 Stack POinter 1 Irrelevant Data
4 Stack POinter +1 1 Index Register (High Order Byte)
5 Stack POinter +2 1 Index Register (Low Order Byte)
RTS 5 1 Op Code Address 1 Op Code
2 Op Code Address +1 1 Irrelevant Data
3 Stack POinter 1 Irrelevant Data
4 Stack POinter +1 1 Address of Next Instruction
(High Order Byte)
5 Stack POinter +2 1 Address of Next 1nstructlon
(Low Order Byte)
WAI 9 1 Op Code Address 1 Op Code
2 Op Code Address +1 1 Op Code of Next Instruction
3 Stack POinter 0 Return Address (Low Order Byte)
4 Stack Pomter -1 0 Return Address
(High Order Byte)
5 Stack POinter -2 0 Index Register (Low Order Byte)
6 Stack POinter -3 0 Index Register (High Order Byte)
7 Stack Pomter -4 0 Contents of Accumulator A
8 Stack POinter -5 0 Contents of Accumulator B
9 Stack Pomter -6 0 Contents of Cond Code Register

- Contlnued-

4-751
 MC68120-MC68121-MC68120-1-MC68121-1

TABLE 18 - CYCLE BY CYCLE OPERATION (CONTINUEDI

Address Mode & R/W

Address Bus Data Bus
Instructions line
INHERENT
MUL 10 1 Op Code Address 1 Op Code
2 Op Code Address +1 1 Irrelevant Data
3 Address Bus FFFF 1 Low Byte of Restart Vector
4 Address Bus FFFF 1 Low Byte of Restart Vector
5 Address Bus FFFF 1 Low Byte of Restart Vector
6 Address Bus FFFF 1 Low Byte of Restart Vector
7 Address Bus FFFF 1 Low Byte of Restart Vector
B Address Bus FFFF 1 Low Byte of Restart Vector
9 Address Bus FFFF 1 Low Byte of Restart Vector
10 Address Bus FFFF 1 Low Byte of Restart Vector
RTI 10 1 Op Code Address 1 Op Code
2 Op Code Address +1 1 Irrelevant Data
3 Stack POinter 1 Irrelevant Data
4 Stack POinter +1 1 Contents of Cand Code Reg
from Stack
5 Stack POinter +2 1 Contents of Accumulator B
from Stack
6 Stack Pornter +3 1 Contents of Accumulator A

•
from Stack
7 Stack Pomter +4 1 Index Register from Stack
(High Order Bytel
B Stack POinter +5 1 Index Register from Stack
(Low Order Bytel
9 Stack POinter +6 1 Next Instruction Address from
Stack (High Order Bytel
10 Stack POinter +7 1 Next Instruction Address from
Stack (low Order Bytel
SWI 12 1 Op Code Address 1 Op Code
2 Op Code Address +1 1 Irrelevant Data
3 Stack POinter 0 Return Address (Low Order Bytel
4 Stack POinter -1 0 Return Address
(High Order Bytel
5 Stack POinter -2 0 Index Register (Low Order Bytel
6 Stack POinter -3 0 Index Register (High Order By tel
7 Stack POinter -4 0 Contents of Accumulator A
B Stack POinter -5 0 Contents of Accumulator B
9 Stack POinter -6 0 Contents of Cond Code Register
10 Stack POinter -7 1 Irrelevant Data
11 Vector Address FFFA (Hexi 1 Address of Subroutine
(High Order Bytel
12 Vector Address FFFB (Hexi 1 Address of Subroutine
(Low Order By tel

RELATIVE
BCC BHT BN E BLO 3 1 Op Code Address 1 Op Code
BCS BlE BPl BHS 2 Op Code Address +1 1 Branch Offset
BEQ BlS BRA BRN 3 Address Bus FFFF 1 Low Byte of Restart Vector
BGE Bll BVC
BGl BMl BVS
BSR 6 1 Op Code Address 1 Op Code
2 Op Code Address +1 1 Branch Offset
3 Address Bus FFFF 1 Low Byte of Restart Vector
4 Subroutine Starting Address 1 Op Code of Next Instruction
5 Stack POinter 0 Return Address (Low Order Byte)
6 Stack POinter -1 0 Return Address(Hlgh Order Bytel

4-752
MC68120-MC68121-MC68120-1-MC68121-1

OP
00
01
MNEM

NOP
MODE

IN ER
-
2
.
1
OP
14
J5
MNEM
DES
TXS
MODE
INHfA
-
3
3
.
TABLE 19 - CPU INSTRUCTION MAP

1
1
OP
.B
69
MNEM
ASL
AOL
MODE
-
6
6
.
2
2
OP
9r
90
MNEM
CPX
JSA
MODE

D1J,
-.
5
5
2
2
OP
DO
01
MNEM
SUBB
(.MPB
MODE
D1A
-3
3
.
2
2

T
02 36 PSHA 3 1 6A DEC 6 2 9E LOS 4 2 02 S~CB 3 2
03 J7 PSHB 3 1 6B 9F STS DA 4 2 03 AOOO S 2
04
Ob
LSAD
ASlO
3
3
1
1
3B
3'
PUlX
ATS
5
S
1
1
6C
60
lNC
TST
6
6
2
2
40
Al
SUBA
rMPA
fNoxa
,,
4 2
2
04
OS
ANOS
81T8
3
3
2
2
06 TAP 2 1 3A ABX 3 1 6E JMP 3 2 A2 serA 2 06 LOAS 3 2
07
08
TPA
lNX
2
3
1
1
3B
3C
An
PSHX ,
10 1
1
SF
70
CLA
NEG
INoxa
EXTND
6
6
2
3
A3
A'
SUBD
ANOA
6
,, 2
2
07
DB
STAB
EORB
3
3
2

,
2
ADce
,,,
09 DEX 3 1 3D MUl 10 1 71 AS BITA 2 D. 3
OA
OB
CLV
SEV ,
2 1
1
JE
JF
WAl
SWl
•
12
1
1
72
7J COM 6 3
A6
A7
LDAA
ST.A,A
2
2
DA
DB
DRAB
ADDS
3

,,
3
2
2
oc
00
CLC
SEC
2
2
1
1
40
41
NEGA 2 1 74
75
LSR 6 3 A8
A9
EORA
AorA ,, 2
2
Dr
DO
LDD
SlD
2
2
OE ClI 2 1 42 76 AOR 6 3 AA OAAA
, 2 DE LDX 4
, 2

,,
OF SEI 2 1 43 COMA 1 1 77 ASR 6 3 A8 ADOA 2 Of STX DIR 2
10 SBA 2 1 44 LSRA 2 1 78 ASL 6 3 AC rpx 6 2 EO SUBS INoxa 2
11
12
CBA 2 1 45
46 RORA , 1
7'
7A
AOL
DEC
6
6
3
3
AD
AE
JSR
LDS
,,
6 2
2
E1
E2
eMP8
serB 4
2
2
13 47 ASRA 2 1 7B Af STS
sus A
INoxa
, , 2 E3 ADOD
,
,
6 2
14 48 ASLA 2 1 7C INC 6 3 80 ~XTNO
, E4 ANDB 2
15
16 TAB 1 1
4'
4A
ROLA
oeCA ,
2 1
1
70
7E
TST
JMP
6
3
3
3
81
82
rMPA
serA , E53
3 E6
BITS
LDAS ,
,
2
2
17 TBA 2 1

,
48 7f rLR EXTND 6 3 B3 sueo 6
, 3 E7 STAB

,
2
18 4C INCA 2 1 80 SUBA IMMED 2 2 8' ANDA
, 3 E8 EORB
ADes
,
4 2

"
DAA INHER 2 40 TSIA 2 1 81 CMPA 2 2 85 BITA
, 3 E9

,
2

,,, ,,
lA 4E T 82 SBCA 2 2 86 LDAA 3 EA DRAB 2
18 ABA INHE~ 2 1 4F CLAA 2 1 83 SUSD 3 87 STAA 3 LB ADDS 2
lC 50 NEGB 2 1 8' ANDA 2 88 FORA
, 3 Er LDD 5 2

•
,,
10 51 85 BITA 2 B9 ADIA 3 ED STD 5 2
S
1E
1F
52
53 COMB
,
2 1
86
87
LOAA 7 2 8A
88
ORAA
AODA " 3
3 Ef
LD'
SlX INoxa S
, 2
20
21
BRA
8RN
AEL 3
3
2
2 "
55
LSAB 1 B8
89
WRA
ADCA ,
2 2
2
8C
80
CPX
J>A
6

, "
6
3
3
fO SUBS
rMPB
EXINO

,,
3
3
22 8HI 3 2
" RORB 2 1 8A ORAA
,
2

,
2 8E LOS 3 F2 SBCS

,
3
2J
24
8LS
BCC
3
3
2
2 "
58
ASAB
ASlS
2
2
I
I
88
8C
ADDA
CPX IMMED
2
3
8f
CO
STS
SUBB
EXTND
IMMEO
S
2 " 3
2 f4
AOOD
ANOB
6

,
3
3

, ,,,
25 BCS 3 2 5. ROlS 2 1 80 BSR REl 6 2 C1 rMPS 2 2 '5 SITS 3
26 BNE 3 2 5A OECS 1 8E LDS IMMED 3 3 C2 SBrs 2 2 f6 LOAS 3
27 BEO 3 2 C3 ADDO 4 3 F7 STAS 3
5B
" ,
,,
28 8VC 3 2 5C INCB 2 I 90 SUBA DIR 3 2 C4 ANDS 2 2 F8 [ORB 1
2. BVS 3 2 TSTB 1 CMPA 3 2 r; BITS F9 ADC8 3
2A
28
8PL
8MI
3
3
2
2
50
Sf
SF
T
CLRB INHER
2

2 1
"
'2
.3
SSCA
SUSD ,
1 2
2
co
C7
LOAS 2 fA
f8
aRAB
ADDS ,
4 3
3
2C 8GE 3 2 C8 EORB 2 2 f(' LOO S 3
BLT
60 NEG INDXD 6 2
" ANDA 3 2
C9 ADeB 2 2 fD STO S 3

I
20 3 2 61 95 SITA 3 2
2E
2F
BGT
BLE AEL
3
3
2
2
62
6J COM 6 2
96
97
LDAA
STAA
3
3
2
2
CA
C8
ORAS
ADDS
2
2
2
2
FE
ff
LD'
STX EXTND ,
S 3
3

'T
30 TSX 3 1 64 LSA 6 2 .8 EORA 3 2 CC LOD 1 3
31
J2
INS
PULA ,
3 I
1
55
66 AOA 6 2
.9
9A
ADCA
ORAA
3
3
2
2
rD
CE LOX IMMED 3 3
UNDUINto OP rODE

JJ PUlB 4 1 67 ASA INDXD 6 2 98 ADOA DIR 3 2 Cf

INHER
NOTES
AddreSSing Modes
INHER" Inherent INDXD=lndexed IMMED .. Immediate
REL" Relative EXTND = Extended DIR5Dtrect
2 Unassigned opcodes are indicated by"·" and should not ba executed
3 Codes marked by "T" force the PC to function as a 16-b!t counter

4·753
 MC68120-MC68121·MC68120-1-MCP8121-1

APPENDIX A
MC68120 CUSTOM ORDERING INFROMATION
A.O MC2708s must be clearly marked to Indicate which PROM
Address $FFEF IS Reserved for the Checksum value for the corresponds to which address space ($X8OQ-$XFFF) See
ROM, to be generated at the factory. Figure A-2 for recommended marking procedure.

A.l CUSTOM MC68120 ORDERING INFORMATION

The custom M C68120 specifications may be transmitted to FIGURE A-2
Motorola In any of the following media:

~ ~
A) EPROM(s)
B) MDOS diskette

~ ~
The specification should be formatted and packaged, as
indicated In the appropriate paragraph below, and mailed
prepaid and Insured with a cover letter (see Figure A-1) to'
Motorola Inc. xxx = Customer 10
MPU Marketing L2787
3501 Ed Bluestein Blvd.
Austin, Texas 78721 After the EPROM(s) are marked, they should be placed In
A copy of the cover letter should also be mailed separately conductive I C carners and securely packed Do not use
styrofoam.

II A.2 EPROMs
MCM2708 and MCM2716 type EPROMs. programmed
with the custom program (positive logiC notation for address
and data). may be submitted for pattern generation. The
A.3 MOOS DISKETTE
The file name and startl end location should be written on
the label

FIGURE A-1

CUSTOMER NAME ________________________________________________________

ADDRESS ______________________________________________________________

ST ATE _________________________ CITY ___________________ ZIP _________

PHONE ________________________________ EXTENSION _________________.

CONTACT MS/MR ________________________________________________________

CUSTOMER PART# _______________________________________________________

ROM START ADDRESS OPTION PATTERN MEDIA TEMPERATURE RANGE

o $C8oo 02708 EPROM 00° to 70 0 e
0$0800 02716 EPROM
o $E8oo o Diskette IMOOSI PACKAGE TYPE
o $F8oo o Cerarnlc
o A 12 and A 13 don't care
MARKING
RAM START ADDRESS OPTION o Standard
o $0080 o SpeCial

INolell _____________________________________________________________

NOTE (1) Other Media ReqUire Prior Factory Approval

SIGNATURE ____________________________________________________________
TITLE ________________________________________________________________

4·754
 ® MOTOROLA
MC68122
(1.0 MHz)
MC68122·1
(1.25 MHz)

Advance InforDl.ation
HMOS
(HIGH-DENSITY N-CHANNEL
MC68122 CLUSTER TERMINAL CONTROLLER SILICON-GATE)

The MC68122 Cluster Terminal Controller (CTC) relieves a host MPU CLUSTER TERMINAL
of the time consuming tasKS related to communicating with devices CONTROLLER
such as terminals and line printers The CTC performs the tasKS
necessary to handle strings of characters and the proper control func-
tions for communicating with asynchronous, commUnicatlons-
compatible components The MC68000 asynchronous bus and the
MC6800/MC6809 synchronous bus are readily supported by the CTC
The CTC prOVides the host MPU with the following features

~
• Automatic Collection of Text Strings DUring Input, Automatic
Transmission of Text Strings DUring Output
• Broadcast Messages Can Be Sent to All Devices
• Notification of Attention, 1/0 Request Termination, and Error
Conditions
CERAMIC PACKAGE
• Wide Range of Control Options Which Can Be Uniquely SpecI- CASE 740

II
fied for Each Device
• Controlled Halting or Ignoring of Output Line Features Available
for Interactive Terminals
• Conversational Protocol Between Host MPU and CTC - Ideal for
Multi-TasKing Implementations PIN ASSIGNMENTS
• Operates In Two Configurations: Stand Alone and Expanded
• Stand Alone - An Internal Serial Communications Interface VSS ~
Performs All Data Transfer to a Single Terminal VCC Cl/SAI
• Expanded - M C6850 Asynchronous Communications Interface
VCC C2
Adapters (ACIA) are Used on the CTC Local Bus
• The Number of Communication Devices May Be SpeCified at E
Power-up SR/Vii C4
~ C5
c:s R/i}}

MAXIMUM RATINGS SA7 AS

Rating Symbol Value Unit SA6 AO/OO
Supply Voltage VCC -03to +70 V SA5 Al/01
Input Voltage V,n -0.3 to + 7.0 V
SA4 A2/02
Operallng Temperature Range TA Oto 70 ·C
VCC
Storage Temperature Range T stg -55 to +150 ·c
SA3
SA2
THERMAL CHARACTERISTICS
Characteristic SAl

Thermal Resistance SAO

Ceramic SOO

SOl
S02
ThiS device contams circuitry to protect the Inputs against damage due to high static
S03
voltages or electnc fields. however, It IS adVised that normal precautions be taken to aVOid
application of any voltage higher than maximum rated voltages to thiS hlgh~lmpedance Cir- SD4
CUit For proper operation It IS recommended that V In and Vout be constrained to the range
S05 A13
VSS s IV,n or Voutl S VCC Reliability of operation IS enhanced If unused Inputs are lied to
an appropriate logic voltage level Ie g , either VSS or VCC) SOB
S07

4·755
 MC68122

FIGURE 1 - CTC FUNCTIONAL BLOCK DIAGRAM

ConftguratlOn
Select Interface

r----- ---,
I I
I I
I
I
I
I
I
I '"
:J
<II

I E
RESET
E *
>
</)

•
Vss
VCC

I
I
I
I
I
l...rT"""'I""T"'T""'--- - - - - - - - J

POWER CONSIDERATIONS

The average chip-Junction temperature. TJ. In °C can be obtained from

TJ=TA+(PooOJA) 11)
Where:
TA-Amblent Temperature. °C
OJA- Package Thermal Resistance. Junctlon-to-Amblent. °C/W
PO-PINT+PPORT
PINT-ICC x VCC. Watts - Chip Internal Power
PPORTEPort Power Dissipation. Watts - User Determined
For most applications PPORT<C PINT and can be neglected PPORT may become significant If the device IS configured to
drive Darlington bases or sink LED loads.
An approximate relationship between Po and T J (If PPORT IS neglected) IS:
PD=K+(TJ+273°C) 12)
Solving equations 1 and 2 for K gives:
K=POO(TA+273°C)+OJAoPD2 (3)
Where K IS a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at eqUilibrium)
for a known T A. Using this value of K the values of PD and T J can be obtained by solving equations (1) and (2) Iteratively for any
value of TA.

4-756
MC68122

LOCAL BUS ELECTRICAL CHARACTERISTICS IVCC=5 0 Vdc +5%, VSS=O, TA=O to 70'C unless otherwise noted 1
(Refer to Figures 2 and 31
Characteristic Symbol Min Typ Max Unit
Input High Voltage E VEIH VCC-O 75 - VCC V
Input Low Voltage E VEIL VSS 03 VSS+06 V
Input High Voltage RESET VSS +40 - VCC
VIH V
Other Inputs· VSS + 20 - VCC
Input Low Voltage All Inputs· VIL VSS 03 VSS+08 V
Input Load Current
lin - - 08 mA
IV In =Ot024VI AS
Input Leakage Current
lin - 15 25 ~A
IV In =Ot0525VI RESET
Three-State (Oft State) Input Current
IV ,n =05t024VI SDO-SD7, ADO-AD7, ITS I - 20 10 ~A
A8-A 15, Cl-C5 - 100 100
Output High Voltage
(ILoad= -205~A, Vcc=Mlnl ADO-AD7 VSS + 24 - -
VOH V
IILoad= -145~A, VCC= Mini A8-A15, R/iN VSS + 24 - -
IILoad= -l00~A, VCC= Mini Other Outputs VSS+24 - -
Output Low Voltage
VOL - - VSS+05 V
IILoad=20mA, Vcc=Mlnl All Outputs
Internal Power DISSipation (Measured at T A - QOC)
Input Capacitance
IVIn=O, TA=25'C,f o =1 OMHzI

"Except Mode Programmmg Levels, See Figure 23

AS
Other Inputs
PINT

C,n
-

-
-
-

-
-
1200

125
100
mW

pF
II
DC SYSTEM BUS ELECTRICAL CHARACTERISTICS
(VCC = 50 Vdc '" 5%, VSS = 0, TA = 70°C unless otherwise notedl (Refer to Figure 2)
Characteristic Symbol Min Typ Max Unit
Input High Voltage CS, DTACK, SAO-SA7, SDO-SD7, SR/W VIH VSS + 20 - Vec V
Input Low Voltage CS, DTACK, SAO-SAl, SDO-SD7, SR/W VIL VSS - 03 - VSS+08 V
Output High Voltage IiLoad- 4OO~A, Vcc-mlnl DTACK, SDO-SDl VOH Vss + 2 4 V
Output Low Voltage Ii Load - 53 mA, VCC - mini DTACK,SDO-SD7 VOL - - VSS+05 V

FIGURE 2 - TIMING TEST LOAD

VCC

MMD6150
Test POint or EqUiv C=90 pF for ADO-AD7, A8-A15, E, AS, R/iN
RL
= 130 pF for SOO-S07, DTACK
R=6 kG for SDO-SDl, DTACK
= 12 kG for ADO-AD7
1
C R MMD7000
or Equlv
= 16 5 kG for A8-A 15, R/iN
RL =2,0 kG for ADO-ADl, A8-A15, R/iN, SAO-SA7
=750 kG for SDO-S07, OTACK

-=- ':'

4·757
 MC68122

LOCAL BUS TIMING IRefer to Figures 4 and 15)

Ident. MC68122 MC68122·1
Characteristics Symbol Unit
Number Min Max Min Max
1 Cycle Time tcvc 10 20 08 20 ~s

2 Pulse Width. E Low PWEL 430 lCXXJ 360 lCXXJ ns

3 Pulse Width. E High PWEH 450 lCXXJ 360 lCXXJ ns
4 Clock Rise and Fall Time tr,tf - 25 - 25 ns
9 Non·Multlplexed Address Hold Time tAH 20 - 20 - ns
11 Address Delay from E Low tAD - 260 - 220 ns
17 Read Data Setup Time tDSR 80 .- 70 - ns
18 Read Data Hold Time tDHR 10 - 10 - ns
19 Write Data Delay Time tDDW - 225 - 200 ns
21 Write Data Hold Time tDHW 20 - 20 - ns
23 Multiplexed Address Delay from AS tADM - 90 - 70 ns
25 Multiplexed Address Hold Time tAHL 20 110 20 - ns
26 Delay Time E to AS Rise tASD 100 - 80 - ns
27 Pulse Width. AS High PWASH 220 - 170 - ns
28 Delay Time AS to E Rise tASED 100 - 80 - ns
29 Usable Access Time (Note 9) tACC 570 - 435 - ns

II
Enable Rise Time Extended tERE - 80 - 80 ns
Processor Control Setup Time tpcs 200 - 200 - ns
Processor Control Hold Time tpCH 20 40 20 40 ns

FIGURE 3 - LOCAL BUS TIMING

tERE
VEIH

R/vv,Address----rt~~~~~~~~--------------------ti------------------------------------t-~~~~
INon·Muxed)

Addr/Data Read Data Muxed

Note 3
MUXE:!d

i+---{ 1911-----l~

Addr/Data Wnte Data Muxed

Muxed

Address
Strobe IASI _____-"r
1+----(

NOTES
1 Voltage levels shown are VLSO 5 V, VH0<2 4 V, unless otherwise specified
2 Measurerrent POints shown are 0 8 V and 20 V, unless otherWise specified
3 Address valid on the occurrence of the latest of 11 or 23
4 Usable access time IS computed by' 1 -14+ 11 + 17)

4-758
MC68122

ASYNCHRONOUS SYSTEM BUS TIMING IRefer to Figures 54, 5, 6, and 7)

Characterlsic Symbol Min Typ Ma. Unit
Cycle Time tcvc 08 - 20 I's
System Address Setup tSAS 30 - - ns
System Address Hold tSAH 0 - - ns
System Data Delay Read
Semaphore tSDDR 03 - a 3+tcyc I's
RAM tSDDR 315 ns
System Data Valid tSDV 0 ns
System Data Hold Read tSDHR 30 - 90 ns
System Data Delay Write
Semaphore tSDDW
.. - .. ns
RAM tSDDW 60 ns
System Data Hold Write tSDHW 0 - - ns
Data Acknowledge
Semaphore tDAL 05 - a 5+tcyc I's
RAM tDAL - 315 - ns
Data Acknowledge High tDAH - - 60 ns
Data Acknowledge Three-State tDAT 90 ns
Data Acknowledge Low to CS High tDCS 60 - - ns

II
• Actual value dependent upon clock penod
.. Data need not be valid on write to Semaphore Registers

FIGURE 4 - ASYNCHRONOUS READ OF SEMAPHORE REGISTER FIGURE 5 - ASYNCHRONOUS WRITE OF SEMAPHORE REGISTER

tSAH;}-

SDO-S07

Three State

FIGURE 6 - ASYNCHRONOUS READ OF RAM FIGURE 7 - ASYNCHRONOUS WRITE OF RAM

SAO-5A7
SRiw ~\..lU-_ _ _ _ _---,IlTu.u

SDD-SD7 ---~'f+f-f<J1

SOO-S07

DT ACK -..,,---:-_ _-,/

Note Timing measurements are referenced to and from a low voltage of a 8 volts and a high voltage of 2 a volts, unless otherwise noted

4-759
 MC68122

SYNCHRONOUS SYSTEM BUS TIMING ISee Notes 1 and 21

Ident MC68122 MC68122-1

Charactenstlc Symbol Unn
Number Min Max Min Max
1 Cycle Time teye 10 10 080 10 "s
2 Pulse Width, E Low PWEL 430 9500 360 9500 ns
3 Pulse Width, E High PWEH 450 9500 360 9500 ns
4 Clock Rise and Fall Time t r , If - 25 - 25 ns
9 Address Hold Time tAH 10 - 10 - ns
13 Address Setup Time Before E tAS 80 - 70 - ns
14 Chip Select Setup Time Before E tcs 80 - 70 - ns
15 Chip Select Hold Time tCH 10 - 10 - ns I

18 Read Data Hold Time tDHR 30 100 30 85 ns

21 Write Data Hold Time tDHW 10 - 10 - ns
30 Output Data Delay Time tDDR - 290 - 240 ns
31 Input Data Setup Time tDSW 165 - 120 - ns
Clock Enable Rise Time Extended tERE 80 80 ns

II FIGURE 8 - SYNCHRONOUS SYSTEM BUS TIMING

~--------------------~--------------------------------------~
-.J",-----------------------------d... V EI H
~--------<D------------~

RIW, Addless--~~~~~~~,,~r-------~~~~----~t---------------------------------~r1~~~

ES----t-~--------------------~

Read Data -----+--~

Write Data -----'---.i- MPU Wnte Data Non-Muxed

Notes
1 Voltage levels shown are VLSO 5 V, VH2:2 4 V, unles~ otherwise specified
2 Measurement pOints shown are a 8 V and 2 0 V, unless otherWise s~eclfled

4-760
MC68122

INTRODUCTION grounded, DTACK configures the system bus Into a syn-

chronous Interface In the asynchronous mode the data
The CTC IS normally used between a host microprocessor transfer acknowledge (DTACK) output proVides the asyn-
(MC68000 or M680X) bus and a local bus consisting of RAM chronous handshake Signal required by the MC68000 pro-
and ACIAs. The number of ACIAs connected to the local bus cessor. It can also be used as a memory ready (MRDY) Signal
IS determined by the number of devices required, and may be for slow memory access on the M6800 Family processors
a maximum of 128. where memory ready capability IS provided. Note that If the
The CTC acts as a "front-end processor" which receives MRDY Signal IS to be used With the DTACK Signal, the
commands and text from a host MPU and then distributes system clock must be faster than, or equal to, the clock driV-
data to and collects data from the appropriate devices con- Ing the CTC.
nected to the local bus. ThiS data transfer IS accomplished by
a dual-port RAM area In the CTC known as the Transfer Area REQUEST REGISTERS
RAM ThiS RAM area IS dual ported In that It may be access- There are four request registers which can be accessed by
ed by both the host MPU and by the CTC execution Unit the host MPU or the CTC. These registers control the owner-
Host M PU commands are written to registers Within the ship of the Transfer Area RAM, Interrupts from the CTC, and
CTC The CTC then asynchronously executes the command other management type functions. The registers are called
Status IS returned to the host MPU when execution of the Lock Register, Parameter Qualification Register, Service Re-
command IS complete qUired Register, and Interrupt Request Mirror Register Each
The CTC operates In one of two configurations· Stand register IS located at a speCifiC location Into the host/ CTC
Alone or Expanded. In the Stand Alone Configuration, no address space (see Table 1) Only the most Significant bit of
external RAM or ACIAs are reqUired. A Single serial port IS each register IS used
proVided for a deVice (terminal, printer, etc.) With baud rates
proVided by the CTC. ThiS configuration IS baSically prOVided
for user evaluation of the CTC. For systems requiring high
data throughput for more than one deVice, the CTC prOVides
an extra amount of system processing power In the Expand-
ed Configuration
The Expanded Configuration proVides servIcing of up to
TABLE 1 - LOCATION OF REGISTERS
AND TRANSFER AREA RAM
Feature
Internal Registers (Reserved)
Lock Register
CTC Address
$QO-$16
$17
II
128 ACIAs located on the local bus These ACIAs can be Parameter Qualification Request $18
connected to any serial-type deVice such as a CRT terminal Service ReqUIred Register $19
or line printer BeSides servIcing the ACIAs, the CTC also Interrupt Request Mirror Request $IA
supports the RAM used to contain deVice parameter Infor- Reserved/Unusable $IB-7F
mation and text distribution areas. Transfer Area RAM $80-FF
$ = HexadeCimal
CTC MPU EXECUTION UNIT
The execution unit of the CTC contains an enhanced TRANSFER AREA RAM AND REQUEST REGISTERS
MC6800 central processing unit. All CTC functions as well as
actual program execution Within the CTC are totally The Transfer Area RAM may be accessed from both the
transparent to the user. CTC execution Unit and the external system bus The request
registers are tools proVided for the progammer's use In ar-
SERIAL COMMUNICATIONS INTERFACE bitrating Simultaneous accesses of the same resource'
A full-duplex asynchronous serial commUnications inter- The CTC's Transfer Area RAM IS located from $0080
face (SCI) IS prOVided In the Stand Alone Configuration With through $ooFF
two data formats and a variety of data rates. The SCI The reserved memory areas $00-16 and $1 B-7F cannot be
transmitter and receiver are functionally independent, but written from the system bus and should not be read.
use the same data format and bit rate. Serial data formats In- The Transfer Area RAM IS accessed from the external
clude standard mark/space (NRZ) and bl-phase and both system bus by way of eight address lines (SAO-SA7) and
proVide one start bit, eight data bitS, and one stop bit. eight data lines (SDO-SD7) Three control lines prOVide for
synchronous or asynchronous access to the Transfer Area
TRANSFER AREA RAM through port 1 Figure 9 shows an example of a syn-
The Transfer Area IS accessed from the system bus by chronous Interface (using MC6809) and Figure 10 shows an
uSing the eight address lines (SAO through SA7) and the example of an asynchronous Interface (using MC680001. The
eight data lines (SDO through SD71. Three control lines (CS, dual-ported RAM IS selected In each case by address lines
SR/W, DTACK) proVide either synchronous or asyn- SAO-SA7 and chip select (CS) from the system bus. The
chronous access to the Transfer Area through the system direction of data transfer IS selected by the system
bus Interface. The Transfer Area IS selected for either type of read/wnte (SR/iiii) line The data transfer acknowledge
access by address lines SAO through SA7 and the chip select (oTACK) signal IS the asynchronous handshake reqUired by
(CS) input. The direction of data transfer is selected by the an MC68000. DTACK can be used to control a memory ready
system bus read/Write (SR/ijij) input. Data Acknowledge Signal on the M6800 Family processor where memory ready
(oT ACK) IS the control line used to configure the system bus capability IS provided (see Figure 11). The latter would allow
In either a synchronous or asynchronous Interface. When the M6800 Family processor to run asynchronously With the
-These request registers are of the "test and set" variety, Ie. If when read, the register IS clear, It Will be automatically set The host processor
software must take thiS Into account, and reset the request register In the scanning routine

4-761
 MC68122

FIGURE 9 - SYNCHRONOUS SYSTEM BUS ACCESS INTERFACE

MC68122 MC6809

Data Lines

Lower Address Lmes

II *E and Q are Inputs tor MC6809E

··Only needed In Expanded Mode

FIGURE 10 - ASYNCHRONOUS SYSTEM BUS INTERFACE

MC68122 MC68000

SOO-S07
Lower Data Lines

SAO-SA7
Lower Address Lines
Al-A8
·Only needed In Expanded Mode

MC68122. It should be noted that If the memory ready signal LOCK REGISTER
(on M6800 processors) IS to be used with the Dr ACK signal, This register, located at $17, IS used in determining owner-
the system clock must be faster than or equal to the clock ship of the Transfer Area. When read, the high-order bit in-
driving the CTC. Example clock cirCUits are shown in Figures dicates one of two results: If set, the Transfer Area was
12 and 13. already claimed by the host MPU or IS currently under

4-762
MC68122

FIGURE 11 - MEMORY REAOY - Di'ACKCONFIGURATION

MCI!8122 MC6809

·Only needed In Expanded Mode

VCC
FIGURE 12 - CLOCK CIRCUIT EXAMPLE 1 - SCHEMATIC AND TIMING

Schematic
II

U1 SN74LS175
U2 SN75LS08
tRC= 10 ~s

Timing

8 MHz

DA

OA J
OB a

Oc
r-
00

AS J L
4·763
 MC68122

FIGURE 13 - CLOCK CIRCUIT EXAMPLE 2 - SCHEMATIC AND TIMING

Schematic Vee

AS

ClR PAE
elK Q o
U2a
L U2b

+---;ClK 0 / - - - . "'--''' 0
U1, U2 - SN74lS74 ClA

•
U3 - SN74lS02

Timing

01

02

'----_. . . .1
AS ______~r_l~ ______~~
o - - ,..._ _--'

ownership of the eTe; If clear, the Transfer Area was free, Area has now been passed to the eTC and that service is re-
but now belongs to the host MPU. quired. The eTC scans thiS register at least once every
The T ransler Area should not be read or written by the millisecond.
host MPU until ownership IS obtained.
INTERRUPT REQUEST MIRROR REGISTER
PARAMETER QUALIFICATION REGISTER This register, located at $1A, IS used to mirror the status of
This register, located at $18, Indicates when set that the the interrupt input. In some systems, where Interrupts are
eTe IS In parameter qualification. either not allowed or not required, a polling routine may be
employed by the host MPU to determine when the eTC re-
SERVICE REQUIRED REGISTER quires servicing. ThiS latch would be the location scanned to
This register, located at $19, is set by the host MPU and IS determine if a returned response is ready In the eTC. A zero
used to Indicate to the eTC that ownership of the Transfer indicates that host service IS required.
MC68122

FUNCTIONAL PIN DESCRIPTIONS

Vcc ANDVSS SYSTEM BUS INTERFACE

VCC and VSS provide power and ground to the CTC. The The system bus Interface IS a configuration-independent
power supply should provide +5 volts (±5%) to VCC and 8-bit data port which permits the external system bus to ac-
VSS should be tied to ground. Total power dissipation cess the Transfer Area RAM and request registers either
should not exceed Po milliwatts. asynchronously or synchronously with respect to the
E clock. The complete system interface consists of eight
RESET data lines (SOO-S07), ~h~ddress hnes (SAO-SA7), and
The reset function IS used for three purposes. The first is three control lines (SR/W, CS, OTACK)'
to provide the CTC with an orderly and defined start-up pro-
cedure from a power-down condition. The second is to DATA LINES (SDO-SD7) - These bidirectional data hnes
return to start-up conditions without an intervening power- allow data transfer between the Transfer Area RAM or the
down condition. The third IS to provide a control signal to request registers, and the system bus. The data bus output
latch the operating mode. drivers are three-state deVices which remain In the hlgh-
On the positive edge of i'iEffi, the CTC latches the Impedance state except during a read of the CTC Transfer
operating mode from Pin C5, the restart vector is fetched Area RAM or request registers by the system processor.
and transferred to the program counter, and instruction ex-
ecution then begins.' ADDRESS LINES (SAO-SA7) - The address lines,
Reset timing IS Illustrated in Figure 14. The RESET hne together With the chip select (CS) signal, allow any of the
must be held low for a minimum of three E-cycles for the 128 bytes of the Transfer Area RAM or the request registers

II
CTC to complete ItS entire reset sequence. An external RC to be uniquely selected. The address lines must be vahd
network may be used to obtain the required timing. before the CS signal goes low for the asynchronous transfer
and vahd before the E signal goes low for the synchronous
ENABLE - E transfer. The system Interface must be deselected between
The E clock Input IS required for timing to synchrOnize reads or writes for the asynchronous operation.
local data bus transfers. A "CPU E-cycie" (or bus cycle) con-
SiStS of a negative half-cycle of E followed by a positive half- SYSTEM READ/WRITE (SR/W) - ThiS Signal IS
cycle. For any given bus cycle, the address IS valid dUring the generated by the system bus to control the direction of data
negative half-cycle of E and the selected device must be transfer on the data bus. With the CTC selected, a low on
enabled to the data bus dUring the next positive half-cycle. the SR/W line enables the Input buffers and data IS transfer-
The data bus IS valid only while E is high. It should be noted red from the system processor to the CTC. When SR/W IS
that this Input shuld have some provIsion to obtain the high and the chip IS selected, the data output buffers are
specified logical high level which is greater than standard turned on and data is transferred from the CTC to the system
TTL levels. bus.
Enable is the primary CTC system timing signal and all tim-
Ing data specified as cycles IS assumed to be referenced to CHIP SELECT (CS) - This signal is a TTL-compatible in-
thiS clock unless otherwise noted. put signal used to activate the system bus Interface and
"If operating In the Stand Alone Mode, the senal communications Interface formats are latched In on PinS 29, 30, 31, and 32 See Tables 3 and4

FIGURE 14 - RESET TIMING

Vee External E Start-up Tlme------<,.~~~~ _______-.:

RESET ~,_-----.....

Internal
Add,ess Bus u...;~~...ulllo,l,.;~~~..ullllllU~-;F":'F~FE~"""~FF";'F';"E"-';"FF~F";'EJ\.-;F";F~F~E'":'~F~F:;:F;cF.-:A:-:Ne~w:-;:P-!e"-_J\.""'~II---J~FF~F":'E-":F"'F";';'FE

Intemal R/VV S\\\\\\\\~,,",\\n\""\,M\S""\"'\\""\\'""\""SSMV""--""""'------------~

~:::'~~s &\\§\\\\\\~\\\\\\\\\\\ PC 8-15 PC 0-7 First

Instruction
~NotValid
NOTE: Timing measurements are referenced to and from a low I/oltage of 0 8 volts and a high voltage of 2 0 volts, unless otherwise noted

4-766
 MC68122

allows transfer of data between the CTC and the system pro- panslon AS IS reqUired only In the Expanded Mode of opera-
cessor dunng synchronous or asynchronous accesses. CS tion. Figure 15 shows how to demultiplex the bus
provides the synchrOniZing signal for the request registers
dunng access by the system bus MULTIPLEXED ADDRESS/DATA BUS
(AO-A15/00-07)
DATA TRANSFER ACKNOWLEDGE (DTACK) - This
signal IS a handshake hne for Information transfer on the These sixteen hnes function as a multiplexed address/data
system data bus In an asynchronous transfer It IS generated bus. These hnes are held In the high-Impedance state bet-
by the CTC as an acknowledge to the CS signal A low out- ween vahd address and data times to prevent potential bus
put Indicates that vahd data IS on the bus for transfer dUring confhcts All hnes can dnve one Schottky TTL load and 90
the system read cycle or that data has been wntten dunng a pF
system wnte cycle The asynchronous operation uses thiS
signal to synchronize the system bus with the CTC processor OPERATING MODES
as Illustrated by Figures 4, 5, 6, and 7 The CTC proVides two different operating modes which
A low Input on Df ACK dunng the failing edge of CS in- are selectable by hardware programming and are referred to
dicates a synchronous system and data will transfer dunng as the Stand Alone Mode, and the Expanded Mode (see
the positive level of the system E clock The timing for thiS Figure 16) The configuration select Interface IS used to
transfer IS shown In Figures 12 and 13. select the operating mode for the CTC. The logiC levels pre-
The output characteristics for DT ACK are the same as sent on C5 when the positive edge of the Reset Input signal
those for the system data bus with allowance for an external occurs are latched Into the CTC and select the appropnate
pull up resistor LogiC charactenstlcs should be such that the mode. See Figure 20.
external pullup resistor IS a holding resistor (, e., dnven to the In the Stand Alone Configuration, the senal communica-

II high level first, then to the high-Impedance state). tIOns Interface of the CTC IS available at pins 45, 46, and 47
of thiS Interface Also, an Interrupt output IS available at Pin
LOCAL BUS INTERFACE 43 See Figure 17
The local bus Interface IS used to connect the CTC to local In the expanded configuration, Pin 45 IS an Interrupt out-
bus components such as RAM, ACIAs, etc, when the CTC put which should be tied to the system Interrupt hne
IS used In the expanded configuratIOn. In the Stand Alone Figures 18 and 21 are examples of how the MC68122 IS to
Configuration, thiS Interface IS left unconnected be used In the Expanded Mode The Expanded Mode
memory map IS denoted In Figure 22
READ/WRITE (R/W)
ThiS signal IS used to control the direction of data transfer MODE PROGRAMMING
on the local bus ThiS pin can dnve one Schottky TTL load The operating mode IS programmed by the level asserted
and 90 pF. on C5 dUring the positive edge of RESET. See Figure 19 and
Table 2.
ADDRESS STROBE (AS) CirCUitry to prOVide the programming levels IS primarily
ThiS Input signal IS used to control the time-multiplexed dependent on the normal system use of the three pins.
address/data hnes AO-A5/DO-D7 Address strobe may also Figure 20 IS an example of how to program the modes of the
be used to de-multiplex the two buses for address map ex- CTC.

FIGURE 15 - TYPICAL LATCH ARRANGEMENT

GND

AS

EN!G
l acI
01 01

31
Port Data
Address!
SN74S373
ITYPlcali

08 08

-
4-766
MC68122

FIGURE 16 - CTC FUNDAMENTAL OPERATING MODES

68000 6808
6809 6803
6801 6800
6802

.,A- Y
RAM
~ -
,.A- -
V- ~
;----
~
ro
U"
"0 0
ro

r-- « I---
ROM I--- I--

k:=
- - - - - - - - - - . - - - - - ------ ------
System Bus

Vv
MC68122
Expanded Mode
•
~ ;.

Local
Bus ro ~
ro

~'\
0 RAM
-
r--
~
MC6850
v
ACIA
.... IMax= 1281

4·767
 MC68122

FIGURE 17 - STAND ALONE MODE

VCC

MC68122
EI

8 System
Address Lines

8 System
Cl
Data Lines System
Senal {
Bus
Data
SR/W
....----CS
DTACK

I
FIGURE 18 - EXPANDED MODE

VCC

RESET - - - . - j
MC68122
EI

8 Lines 8 System
Multiplexed Addressl Data
Address Lines

R/W-----I 8 System
Data Lines System
Bus
AS ---eo! ' - - - - - SR/W
....---CS
8 Address Lines DTACK

Sen.II/O

VSS

4·768
MC68122

FIGURE 19 - MODE PROGRAMMING TIMING

See Figure 23
for Diode

'MPH
VMPL
C5 Mode Latch Level
Ir---~----.L VMPH Min
Mode Input
RESET
IC51 ---< VMPL Max

TABLE 2 - MODE PROGRAMMING SPECIFICATIONS (See Figure 201

Characteristic Symbol Min Typ Max Unit
Mode Programming Input Voltage Low VMPL - - 18 V
Mode Programming Input Voltage High VMPH 40 - - V
Mode ProgrammlnQ Diode Differential (,f Diodes are Used) VMPDD 06 - - V

•
RESET Low Pulse Width PWRSTL 30 - - E-Cycles
Mode Programming Setup Time 'MPS 20 - - E-Cycles
Mode Programming Setup Time
RESET Rise Time;;, 1 ~s tMPH 0 - - ns
RESET Rise T,me< 1 ~s 100 - -

FIGURE 20 - TYPICAL MODE PROGRAMMING CIRCUIT

T
> ~ MC68122
R2: ~ Rl: Rl ~ Rl~

48 RESET
43 C5
44 C4

EI 45 C3/EI

NOTES

D~~
R2. C = Reset Time Constan t Mode Control
Rl = 10 k !Typicali SWitch
D= lN914, lN4001 (TYPical 1

,- ~
~ At R'EsET, C5 H = Stand Alone Mode
L = Expanded Mode

4-769
 FIGURE 21 -
•
MC68122 SYSTEM s:
(')
~
.....
~

MC68122

To
Host
'"'oo~
AS 41

System

A15 25
26
2'i
i
;
30
DevIcE:
AB 32 Buffer
~ Memory
Riw42 1$10001 07'
.!.J
-..j
E4

o
Device
Decode
10k DO

~
+ 5 v-'\I\Ar---,

PQR

Address, E Memory
Decode

INT
ACK
(System)

Por

NOTE Figure shows unbuffered system with only one device Interface (MC6850) and associated memory
MC68122

FIGURE 22 - CTC MEMORY MAP - EXPANDED MODE

~ Reserved or Used
~byCTC

RAM used for buffer storage Amount of RAM reqUIred IS

specified by the following formula
} S,ze= 128+ 1128+ buf S1zel.N
N = number of devices specified
Buf size = device buffer size specIfied In bytes (even numberl

> Maximum of 128 AelAs starting at $EOOO

Device IDs start at 1
EOOO- EOO1 = ID1
EOO2-EOO3=ID2

ThiS memory map IS the entire 64K map of the eTC Note that the buf-
fer sIze should be the maximum data transmitted to or received from a
I
device without host MPU notification required

NOTE As the Stand Alone Mode of the eTC uses no external RAM
or ACIAs, the memory map IS Irrelevant

INTERRUPTS PROGRAMMABLE OPTIONS

The CTC has no user Interrupts, but does have lines which The following features of the SCI are programmble
are connected to the host MPU for a "shoulder tapping" • Format. standard mark/space (NRZ) or bl-phase (see
type of operation. In the Stand Alone Mode, C5 IS an inter- Table 4)
rupt line to the host, while In the Expanded Mode, C3/EI • Clock' external or mternal clock source
should be used as the Interrupt output
• Baud rate' one of four per E-clock frequency, or one-
eighth of the external clock Input to C3 (see Table 3)
• Clock output· Internal bit rate clock enabled or disabled
SERIAL COMMUNICATIONS INTERFACE to C3
In the Stand Alone Mode, a full-duplex asynchronous The programmable options listed above are selected by
senal commUnications mterface IS provided for connection putting speCifiC logiC levels on PinS 29, 30, 31, and 32 at the
to an outside terminal. Two available data formats Include time RES ET IS asserted. Tables 3 and 4 prOVide the logiC level
the standard mark/space (NRZ) and bl-phase Both formats Information reqUired for programming the SCI and Figure 23
provide one start bit, eight data bitS, and one stop bit details two available data formats

TABLE 3 - SCI BIT TIMES AND RATES (STAND ALONE MODE)

Pin 32 Pin 31 E 614.4 kHz 1.0 MHz 1.2288 MHz
0 0 +16 26 "s/38,400 Baud 16 "s/62,500 Baud 130 "sI76,800 Baud
0 1 +128 208 "s/4,800 Baud 128 "sI7812.5 Baud 104 2 "s/9,600 Baud
1 0 +1024 1 67 msl600 Baud 1 024 ms/976.6 Baud B33 3 "s/l ,200 Baud
1 1 +4096 6.67 ms/l50 Baud 4096 ms/244 1 Baud 3.33 ms/300 Baud

TABLE 4 - SCI FORMAT AND CLOCK SOURCE CONTROL

Clock C3
Pin 29 Pin 30 Format
Source (Pin 46)
0 0 SI-Phase Internal Not Used
0 1 NRZ Internal Not Used
1 0 NRZ Internal Output
1 1 NRZ External Input

4-771
 MC68122

FIGURE 23 - SCI DATA FORMATS (STAND ALONE MODEl

Output
Clock

NRZ
Format

BI-Phase
Format
Bit Bit
Idle Start 0 Stop
4 5 7
Data 01001101 ($4DI

MC68122 SYSTEM OPERATION In the Transfer Area at all times. There are no default condi-
tions In thiS configuration. The host must set these values
TRIGGERS before Input or output starts

II Throughout the following paragraphs, the term "trigger"

will appear frequently This explanation of the trigger con-
cept In data handling IS offered to familiarize the CTC user
with the concept
In the trigger concept, the first character IS called the
match character and the remaining characters are called
Offset into
Host/CTC
Address Space Bytes
$80
$81
1
1
Function
Host Request
Error Status Bits (Latched)
replacement characters For triggers associated with Input, $82 1 SCI Status
these characters serve as echoes back to the deVice, and the $83 1 Single Chip Options
echoed characters themselves may activate output triggers. $84 1 Output Termination Null Count
Only the match character IS sent to the host MPU, never the $85 4 Output Echo String
echo character Each non-NULL Incoming character IS com- $89 2 Input Termination Range
pared to the match character, and If matched, the characters $88 1 Input Termination Match Character
following the match are echoed back to the Input deVice For $8C 1 Input" AND" Mask Byte
output, triggers effectively serve as a replacement string. $80 4 Reserved
For example, an Input trigger can be set up to provide a $91 1 Output/Input Text Length
carnage return, line feed, and a prompt character as shown $92 100 Text Buffer
CR - Match Character $F6 10 Internal CTC Use
CR - Carnage Return
LF - line Feed
(> I - Prompt Symbol FUNCTION DESCRIPTION
Whenever a carnage return character IS Input and matched
with the match character of the trigger, the following three $80 - Host Request
Items (CR, LF, > I are automatically echoed to the Input ThiS byte denotes which state the CTC IS to enter:
$00 - Idle mode
deVice.
$01 - Input mode
Some triggers perform more complex functions such as
$02 - output mode
backspace control and padding transmission counts. Also,
some triggers do not have echo strings or may proVide a
range of two characters for match determination The trigger $81 - ERROR STATUS BITS
functions are listed In the follOWing pages. These bits denote any errors which may have occurred on
the serial commUnications Interface ThiS status Information
IS latched for an entire host M PU request.
STAND ALONE CONFIGURATION - $04 - framing error
DETAILED OPERATION $20 - transmitter data register empty
$40 - overrun/framing error'
The CTC, while deSigned for a multi-device system with $80 - SCI reads flag - data register contains data
several ACIAs, can also be used In a Stand Alone Configura-
tion. ThiS configuration gives the deSigner the capability of $82 - SCI STATUS
evaluating the CTC without reqUiring several terminals. ThiS byte IS a mirror Image of the previous byte, only It is
There IS no parameter qualification reqUired in thiS configura- continuously updated rather than line by line. Usually only
tion and the device profile shown below resides completely bits $20 and $80 are used In this byte.

• Framing error turns on two bits to distinguish It from an overrun error

MC68122

$83 - SINGLE CHIP OPTIONS Before examining or changing any parameters, the
The options are: Transfer Area must be owned by setting the Lock Register.
$40 - echo Input termination match character When the host M PU IS ready to allow the eTC to begin nor-
$80 - echo Input to output
mal processing, It sets the Service ReqUired Register.

$84 - OUTPUT TERMINATION NULL COUNT EXPANDED CONFIGURATION -

This byte should be set to the number of nulls required DETAILED OPERATION
after sending of the output echo string.
In the Expanded Mode, there IS a self-test feature which
$85 - OUTPUT ECHO STRING can be used at parameter quahflcatlon Ume. By entenng a
These four bytes represent the output stnng which IS $06 at the Inltlahzatlon Mode SWitch and setting the Service
transmitted at the termination of all output text, and when ReqUired Register, local RAM IS checked starting at address
Input terminates due to a match with an Input termination $1000 The address of the first byte of memory which falls
match tngger The normal stnng IS a CR, LF combination self-check IS returned at offset $81 and $82 within the
host/eTC address space segement ThiS allows functional
$89 - INPUT END-OF-LiNE TERMINATION RANGE venflcatlon of the RAM on the local bus After the RAM self-
These bytes are used to Initiate an end-of-hne response to check IS completed, the host MPU must again obtain control
the host MPU when any character or character within a of the Tran&fer Area to perform whatever functions were
specified range IS encountered. No output echo string IS deSired dunng parameter quahflcatlon. ThiS time when the
sent transfer area IS claimed and the service reqUired register set,
the eTC will then begin normal processing and eXit
parameter quahflcatlon mode. The deflmtlon of the Transfer

II
$8B - INPUT END-OF-LiNE MATCH CHARACTER
ThiS byte IS used to define the end-of-hne match character Area RAM at this time IS:
which IS commonly a CR When thiS character IS matched, Offset into
an output echo stnng will be transmitted and the Input IS ter- Host/CTC
minated. Address Space "VIes Definition
Control $80 1 Inttlallzatlon Mode SWitch
$8C - INPUT "AND" MASK BYTE Parameter $81 2 Result of RAM Self-Test
Each character that IS entered IS automatically ANDed $83 4 Reserved
with thiS byte before further processing. A common value IS $87 2 Number of DeVices
$7F, which IS normally used to strip off panty bits for seven $89 2 Device Buffer Size
bit data characters. $8B 4 Reserved

Device $8F 1 Device Type Options

$80 - RESERVED Profile 1$50= ACIAI
Parameter $90 2 Attribute Bytes
$91 - OUTPUT/INPUT TEXT LENGTH $92 1 ACIA Control Register
ThiS byte represents the number of bytes that are to be Parameter
transmitted to/from the host. The number must be within a $93 1 Input "AND" Character Byte
range from 0 to 100.