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Interview focus areas:

2 – 3 stages:

1. written exam

o verilog, digital design

o aptitude

o SV

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2. Technical interview – 2 rounds

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VLSI Guru interview preparation questions & excel sheet - VLSI Guru https://www.vlsiguru.com/interview-preparation/

o how to explain things

o Digital

o CMOS basics

o Verilog

o SV

o UVM basics

o protocols : AXI, AHB, Ethernet, USB

o Testbench concepts

o testcase development

o Misc: UNIX, scripting, tools

3. HR interview

o soft skills

f(0,6,4,5,12,15,17,20,31,48,61,64)

Digital Design:

1. ASIC, FPGA

▪ PLA

▪ ASIC Flow Course Registration

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o requirements to Post silicon validation

1. combinational logic

o basic gates

o and, or, nand, nor, xor, xnor, buffer, not

o xor’s can also be used as comparator

xor(1,0) = 1, xor(0,1) = 1, xor(0,0)= 0

o truth tables

o karnaguh maps

o used to reduce the logic

o demorgan theorems

o AB + A(~B) = A (A(B+~B)) = (A1) = A

o using a gate to create another gate

– use nand to create and

– use nand to mux2x1

– use and to create nand //NOT POSSIBLE

– use mux to create various gates(and, nand, or, nor, xor, xnor, buffer, inverter)

– use mux to create bigger mux

– ex: 2×1 to create 4×1 mux

o NAND is universal gate Course Registration

o Why NAND is preferred over NOR

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o priority encoder, decoder

o adder, substractor, comparator

o given a code, write the equivalant synthesized gate level diagram

o load, drive streghtnh, fan in, fan out

2. seqeuncetial logic

o flipflop

o latch

o prove that DFF is +latch followed by -latch

o exitation table for flipflops

o D, T, SR, JK

o state machines

o Mealy state machine

o Moore state machine

o given a design requirement, implment it using state machine diagram

o pattern detector

o registers, flipflops

o status registers

o control registers

o bit addressed, byte addressed, word addressed

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o given a design example, how many flipflops are required to implement the design or state machine

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o EX: TLC (RED, YEL, GRN)

o RED: 50 – 150 sec (bits: 8)

o YEL: 10 – 40 sec (bits: 6)

o GRN: 20 – 60 sec (bits: 6)

o total bits required: 8

o 8, 6, 6 are used for counting the time value

o various types of flipflops

o D FF

o T FF

o JK FF

o SR FF

o various types of latches

o SR

o clock, reset

o Crystal, VCO, PLL

o XO frequency (Crystal Oscillator frequency)

o clock distribution, multiplexing

o timing diagram for flipflop, latches

o synchornous reset, asynchornous reset

o synchornous reset : Reset only takes effect at +edge of clock Course Registration

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VLSI Guru interview preparation questions & excel sheet - VLSI Guru https://www.vlsiguru.com/interview-preparation/

o asynchornous reset : Reset takes effect any time it is applied(irrespective of edge of clock)

o setup time, hold time

o how to fix set time violation, hold time violation

o using basic sequential elements, to create bigger sequential circuits

o counter : biffer sequential circuit

o how do decide on number of flops required

o clock generation

o clock freqeuncy, timeperiod

o jitter

o using one clock to generate another clock of different freqeuncy

o ex: use 50MHz clock to generate 100MHz clock

o ex: use 50MHz clock to generate 25MHz clock

o ex: use 50MHz clock to generate 50/3MHz clock

o divided by 3, by 4 clocks

o memories

o ports (clk, rst, addr, data, wr_rd)

o front door access

o back door access

o what is means by hiearchical access

o how do we check if there is a fault in specific location of memory Course Registration

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o ex: fault (address lines are tied wrongly)

o Front door write, back door read

o Back door write, front door read

o clock domain crosssing

o CDC always leads to meta stability

o synchronizers : 2 stage, 3 stage synchronizers are used to address the metastability

o race around condition

o level shifters , isolation cells (voltage domain, clock domain, power domain)

Ex:

1. NAND -> AND (NAND followed by NAND(output of first nand is inputs to both)

NAND -> OR (2 NAND(same A, same B), output is input in 2nd stage of NAND)

NOR -> OR (NOR, followed by NOR, ouptu of 1st stage, is given to both inputs)

otherwsie, tie one of teh inputs to ‘0’

2×1 MUX -> NAND (NAND(A, 0, B(sel)) -> NAND(0,1, NAND_OP(SEL))

2×1 MUX -> AND (NAND(A, 0, B(sel)))

2×1 MUX -> NOR (NAND(1(1), A(0), B(sel)) -> NAND(0,1, NAND_OP(SEL))

2×1 MUX -> OR (NAND(1(1), A(0), B(sel)))

2X1 MUX -> Inverter

2X1 MUX -> Buffer Course Registration

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VLSI Guru interview preparation questions & excel sheet - VLSI Guru https://www.vlsiguru.com/interview-preparation/

2X1 MUX -> XOR

2X1 MUX -> XNOR

4.

What does below code synthesize to. Explain below codes with synthesized diagrams:

#####################################################

interview_preparation_2Feb2019.txt Download

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