P3A9606JK

2
Dual bidirectional I3C/I C-bus and SPI voltage-level translator
Rev. 1.0 — 10 May 2021 Product data sheet

1 General description
The P3A9606JK is a 2-bit, dual supply translating transceiver with auto direction
2
sensing, that enables bidirectional voltage level translation for traditional I C-bus/SMBus
applications, 12.5 MHz I3C-bus applications and also higher speed SPI applications (with
two devices). It features two 1-bit input-output ports (An and Bn), one output enable input
(OE) and two supply pins (VCCA and VCCB). VCCA can be supplied at any voltage between
0.72 V and 1.98 V and VCCB can be supplied at any voltage between 0.72 V and 1.98 V,
making the device suitable for translating between any of the low voltage nodes (0.8 V,
1.2 V and 1.8 V). VCCA must be ≤ VCCB to ensure proper operation.
P3A9606JK can be used for both open drain as well as push-pull application which
2
allows for level translation applications using I3C, I C and SPI protocols.
Pins An are referenced to VCCA and pins Bn are referenced to VCCB. The active HIGH
OE pin is referenced to VCCA and controllable by a signal in either VCCA or VCCB domain.
A LOW level at pin OE causes the outputs to be in a high-impedance OFF-state. This
device is fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing the damaging backflow current through the device when it
is powered down.

2 Features and benefits

• Wide supply voltage range:
– VCCA: 0.72 V to 1.98 V and VCCB: 0.72 V to 1.98 V; VCCA ≤ VCCB
• IOFF circuitry provides partial Power-down mode operation
• Inputs accept voltages up to 1.98 V and are overvoltage tolerant to 1.98 V
2
• Provided voltage level translation for I3C, I C-bus, SMBus and SPI devices
• ESD protection:
– HBM JESD22-A114E Class 2 exceeds 2000 V
– CDM JESD22-C101E exceeds 1000 V
• Latch-up performance exceeds 100 mA per JESD 78B Class II
• Available in X2SON8 package
• Specified from -40 °C to +85 °C and -40 °C to +125 °C
NXP Semiconductors
P3A9606JK
2
Dual bidirectional I3C/I C-bus and SPI voltage-level translator

3 Ordering information
Table 1. Ordering information
Type number Topside Package
marking
Name Description Version
[1]
P3A9606JK Tx X2SON8 super thin small outline package, no leads; 8 terminals; SOT2015-1
0.35 mm pitch; 1.35 mm x 1.0 mm x 0.32 mm body

[1] "x" changes based on date code.

3.1 Ordering options

Table 2. Ordering options
Type number Orderable part Package Packing method Minimum Temperature
number order quantity
P3A9606JK P3A9606JKZ X2SON8 Reel 13” Q1/T1 20000 Tamb = -40 °C to +125 °C
*standard mark SMD
[1]
with SSB

[1] This packing method uses a Static Shielding Bag (SSB) solution. Material should be kept in the sealed bag between uses.

4 Block diagram

GATE
CONTROL
OE

A1

B1

A2

B2

VCCA VCCB

aaa-041094

Figure 1. Block diagram

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NXP Semiconductors
P3A9606JK
2
Dual bidirectional I3C/I C-bus and SPI voltage-level translator

5 Pinning information

5.1 Pinning
pin 1 index P3A9606JK
area

B2 1 8 B1

GND 2 7 VCCB

VCCA 3 6 OE

A2 4 5 A1

aaa-040893

Transparent top view

Figure 2. Pin configuration SOT2015-1

5.2 Pin description

Table 3. Pin description
Symbol Pin Description
B2, B1 1, 8 B port - data input or output (referenced to VCCB)
GND 2 ground (0 V)
VCCA 3 supply voltage A
A2, A1 4, 5 A port - data input or output (referenced to VCCA)
OE 6 output enable input (active HIGH, referenced to VCCA); signal can be from VCCA or
VCCB domain
VCCB 7 supply voltage B

6 Functional description
[1]
Table 4. Function table
Supply voltage Input Input/output
[2]
VCCA VCCB OE
0.72 V to 1.98 V 0.72 V to 1.98 V L disconnected
0.72 V to 1.98 V 0.72 V to 1.98 V H A1 = B1; A2 = B2
[3] [3] disconnected
GND GND X

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care

[2] VIL and VIH are referenced to VCCA. The OE can be controlled by an external device that is powered by either VCCA or VCCB. As VCCB is required to be
greater than VCCA, the OE pin has been designed to withstand a voltage equal to VCCB (up to 1.98 V per recommended functional voltage range).
[3] When either VCCA or VCCB is at GND level, the device goes into Power-down mode.

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NXP Semiconductors
P3A9606JK
2
Dual bidirectional I3C/I C-bus and SPI voltage-level translator

7 Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCCA supply voltage A VCCA ≤ VCCB -0.5 2.5 V
VCCB supply voltage B VCCA ≤ VCCB -0.5 2.5 V
[1]
VI input voltage A port, B port and OE -0.5 2.5 V
[1][2][3]
VO output voltage Active mode -0.5 VCCO + 0.25 V
[1]
Power-down or 3-state mode -0.5 2.5 V
IIK input clamping current VI < 0 V -50 - mA
IOK output clamping current VO < 0 V -50 - mA
[2]
IO output current VO = 0 V to VCCO - ±50 mA
ICC supply current ICC(A) or ICC(B) - 100 mA
IGND ground current -100 - mA
Tstg storage temperature -65 +150 °C
Ptot total power dissipation Tamb = -40 °C to +125 °C - 125 mW

[1] The minimum input and minimum output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] VCCO is the supply voltage associated with the output.
[3] VCCO + 0.25 V should not exceed 2.5 V.

8 Recommended operating conditions

[1]
Table 6. Recommended operating conditions
Symbol Parameter Conditions Min Max Unit
VCCA supply voltage A VCCA ≤ VCCB 0.72 1.98 V
VCCB supply voltage B VCCA ≤ VCCB 0.72 1.98 V
VI input voltage A port, B port and OE 0 1.98 V
VO output voltage Power-down or 3-state mode;
VCCA = 0.72 V to 1.98 V; VCCB =
0.72 V to 1.98 V
A port 0 1.98 V
B port 0 1.98 V
Tamb ambient temperature -40 +125 °C
[2]
TJ junction temperature -40 +125 °C
Δt/ΔV input transition rise and fall rate VCCA = 0.72 V to 1.98 V; VCCB = - <5.3 ns/V
0.72 V to 1.98 V

[1] The A and B sides of an unused I/O pair must be held in the same state, both at VCCI or both at GND.
[2] The TJ limits shall be supported by proper thermal PCB design taking the power consumption and the thermal resistance as listed in Table 7 into account.

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NXP Semiconductors
P3A9606JK
2
Dual bidirectional I3C/I C-bus and SPI voltage-level translator

9 Thermal characteristics
Table 7. Thermal characteristics
Symbol Parameter Conditions Value (typ) Unit
Rth(j-a) Thermal resistance from junction to ambient X2SON8 package 114.9 °C/W
Ψ(j-t) Junction to top characterization X2SON8 package 1.6 °C/W

10 Static characteristics
Table 8. Typical static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C.
Symbol Parameter Conditions Min Typ Max Unit
VOH HIGH-level A port; VCCA = 1.2 V; IO = -20 μA - 1.1 - V
output voltage
VOL LOW-level A port; VCCA = 1.2 V; IO = 20 μA - 0.09 - V
output voltage
II input leakage OE input; VI = 0 V or 1.98 V; VCCA = 0.72 V to 1.98 V; VCCB - - ±1 μA
current = 0.72 V to 1.98 V
[1]
IOZ OFF-state output A or B port; VO = 0 V to VCCO; VCCA = 0.72 V to 1.98 V; - - ±1 μA
current VCCB = 0.72 V to 1.98 V
IOFF power-off A port; VI or VO = 0 V to 1.98 V; VCCA = 0 V; VCCB = 0 V to - - ±1 μA
leakage current 1.98 V
B port; VI or VO = 0 V to 1.98 V; VCCB = 0 V; VCCA = 0 V to - - ±1 μA
1.98 V
[2]
ICC supply current VI = 0 V or VCCI; IO = 0 A
ICC(A); VCCA = 0.72 V; VCCB = 0.72 V to 1.98 V - 0.05 - μA
ICC(B); VCCA = 0.72 V; VCCB = 0.72 V to 1.98 V - 3.3 - μA
ICC(A) + ICC(B); VCCA = 0.72 V; VCCB = 0.72 V to 1.98 V - 3.5 - μA
CI input OE input; VCCA = 0.72 V to 1.98 V; VCCB = 0.72 V to 1.98 V - 1.0 - pF
capacitance
CI/O input/output A port; VCCA = 0.72 V to 1.98 V; VCCB = 0.72 V to 1.98 V - 4.0 - pF
capacitance
B port; VCCA = 0.72 V to 1.98 V; VCCB = 0.72 V to 1.98 V - 4.0 - pF

[1] VCCO is the supply voltage associated with the output.

[2] VCCI is the supply voltage associated with the input.

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P3A9606JK
2
Dual bidirectional I3C/I C-bus and SPI voltage-level translator

Table 9. Static characteristics

[1]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions -40 °C to +85 °C -40 °C to +125 °C Unit
Min Max Min Max
VIH HIGH-level A port or B port
input voltage [1]
VCCA = 0.72 V to 0.9 V; VCCB = VCCI - 0.2 - VCCI - 0.2 - V
0.72 V to 0.9 V
[1]
VCCA = 0.9 V to 1.98 V; VCCB = VCCI - 0.4 - VCCI - 0.4 - V
0.9 V to 1.98 V
OE input
VCCA = 0.72 V to 1.98 V; VCCB 0.65VCCA - 0.65VCCA - V
= 0.72 V to 1.98 V
VIL LOW-level A or B port
input voltage
VCCA = 0.72 V to 1.98 V; VCCB - 0.3VCCA - 0.3VCCA V
= 0.72 V to 1.98 V
OE input
VCCA = 0.72 V to 1.98 V; VCCB - 0.3VCCA - 0.3VCCA V
= 0.72 V to 1.98 V
[2]
VOH HIGH-level IO = -20 μA
output voltage
A port; VCCA = 0.72 V to VCCO - 0.4 - VCCO - 0.4 - V
1.98 V
B port; VCCB = 0.72 V to VCCO - 0.4 - VCCO - 0.4 - V
1.98 V
[2]
VOL LOW-level IO = 20 μA
output voltage
A port; VCCA = 0.72 V to - 0.3 - 0.3 V
1.98 V
B port; VCCB = 0.72 V to - 0.3 - 0.3 V
1.98 V
II input leakage OE input; VI = 0 V to 1.98 V; VCCA - ±2 - ±5 μA
current = 0.72 V to 1.98 V; VCCB = 0.72 V
to 1.98 V
[2]
IOZ OFF-state A or B port; VO = 0 V or VCCO; - ±2 - ±10 μA
output current VCCA = 0.72 V to 1.98 V; VCCB =
0.72 V to 1.98 V
IOFF power-off A port; VI or VO = 0 V to 1.98 V; - ±2 - ±10 μA
leakage VCCA = 0 V; VCCB = 0 V to 1.98 V
current
B port; VI or VO = 0 V to 1.98 V; - ±2 - ±10 μA
VCCB = 0 V; VCCA = 0 V to 1.98 V
[1]
ICC supply current VI = 0 V or VCCI; IO = 0 A
ICC(A)
OE = LOW; - 5 - 15 μA
VCCA = 0.72 V to 1.98 V; VCCB
= 0.72 V to 1.98 V

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NXP Semiconductors
P3A9606JK
2
Dual bidirectional I3C/I C-bus and SPI voltage-level translator

Table 9. Static characteristics...continued

[1]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions -40 °C to +85 °C -40 °C to +125 °C Unit
Min Max Min Max
OE = HIGH; - 6 - 20 μA
VCCA = 0.72 V to 1.98 V; VCCB
= 0.72 V to 1.98 V
VCCA = 1.98 V; VCCB = 0 V - 3.5 - 15 μA
VCCA = 0 V; VCCB = 1.98 V - -2 - -15 μA
ICC(B)
OE = LOW; - 8 - 29 μA
VCCA = 0.72 V to 1.98 V; VCCB
= 0.72 V to 1.98 V
OE = HIGH; - 11 - 36 μA
VCCA = 0.72 V to 1.98 V; VCCB
= 0.72 V to 1.98 V
VCCA = 1.98 V; VCCB = 0 V - -2 - -15 μA
VCCA = 0 V; VCCB = 1.98 V - 6 - 20 μA
ICC(A) + ICC(B)
OE = LOW; - 16 - 56 μA
VCCA = 0.72 V to 1.98 V; VCCB
= 0.72 V to 1.98 V

[1] VCCI is the supply voltage associated with the input.

[2] VCCO is the supply voltage associated with the output.

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NXP Semiconductors P3A9606JK
2
Dual bidirectional I3C/I C-bus and SPI voltage-level translator
11 Dynamic characteristics
[1]
Table 10. Dynamic characteristics for temperature range -40 °C to +85 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 4; for waveform see Figure 3.
Symbol Parameter Conditions VCCB VCCB Unit
1.2 V ± 10 % 1.8 V ± 10 %
Min Typ Max Min Typ Max
VCCA = 0.8 V ± 10 %
tpd propagation delay A to B; CL = 15 pF 2.1 5.6 7.7 1.7 3.9 5.3 ns
B to A; CL = 15 pF 1.2 10.6 19.9 0.5 9.6 17.2 ns
ten enable time OE to A, B; CL = 15 pF 16 125 150 16 120 160 ns
[2] [3]
tdis disable time OE to A; no external load 10 25 10 25 ns
[3]
OE to B; no external load 10 25 10 25 ns
OE to A; CL = 15 pF 50 50 ns
OE to B; CL = 15 pF 50 50 ns
tt transition time A port; CL = 15 pF 2.1 8.5 17.5 1.5 9 15.4 ns
B port; CL = 15 pF 1.1 4 5.8 0.7 1.5 2.1 ns
[4]
tsk(o) output skew time delta between channels 0 0.2 0.4 0 0.2 0.4 ns
tW pulse width data inputs 37 37 ns
fdata data rate 0.064 26 0.064 26 Mbps

[1] tpd is the same as tPLH and tPHL; ten is the same as tPZL and tPZH; tdis is the same as tPLZ and tPHZ; tt is the same as tTHL and tTLH.
[2] Guaranteed by design.
[3] Delay between OE going LOW and when the outputs are actually disabled.
[4] Skew between any two outputs of the same package switching in the same direction. One channel is not always faster than the other.

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2
Dual bidirectional I3C/I C-bus and SPI voltage-level translator
[1]
Table 11. Dynamic characteristics for temperature range -40 °C to +85 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 4; for waveform see Figure 3.
Symbol Parameter Conditions VCCB VCCB Unit
1.2 V ± 10 % 1.8 V ± 10 %
Min Typ Max Min Typ Max
VCCA = 1.2 V ± 10 %
tpd propagation delay A to B; CL = 15 pF 1.5 4.5 6.1 1.0 2.5 3.5 ns
B to A; CL = 15 pF 1.1 3.9 5.3 0.6 2.8 3.9 ns
tpdc propagation delay A to B; CL = 80 pF NA NA NA 2.5 4.9 7 ns
B to A; CL = 30 pF NA NA NA 0.9 3.4 5 ns
ten enable time OE to A, B; CL = 15 pF 10 50 100 10 50 100 ns
[2] [3]
tdis disable time OE to A; no external load 10 25 10 25 ns
[3]
OE to B; no external load 10 25 10 25 ns
OE to A; CL = 15 pF 50 - 50 ns
OE to B; CL = 15 pF 50 - 50 ns
tt transition time A port; CL = 15 pF 0.8 2.6 3.5 0.6 1.5 2.5 ns
B port; CL = 15 pF 1.1 3.6 5.1 0.6 1.3 2.2 ns
ttc transition time A port; CL = 30 pF NA NA NA 1.0 2.2 3.6 ns
B port; CL = 80 pF NA NA NA 2.5 4.3 6.3 ns
[4]
tsk(o) output skew time delta between channels 0.0 0.1 0.2 0.0 0.1 0.3 ns
tW pulse width data inputs 15 13.5 ns
fdata data rate 0.064 52 0.064 52 Mbps

[1] tpd is the same as tPLH and tPHL; ten is the same as tPZL and tPZH; tdis is the same as tPLZ and tPHZ; tt is the same as tTHL and tTLH.
[2] Guaranteed by design.
[3] Delay between OE going LOW and when the outputs are actually disabled.
[4] Skew between any two outputs of the same package switching in the same direction. One channel is not always faster than the other.

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2
Dual bidirectional I3C/I C-bus and SPI voltage-level translator
[1]
Table 12. Dynamic characteristics for temperature range -40 °C to +85 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 4; for waveforms see Figure 3 and Figure 4.
Symbol Parameter Conditions VCCB Unit
1.8 V ± 10 %
Min Typ Max
VCCA = 1.8 V ± 10 %
tpd propagation delay A to B; CL = 15 pF 1 2.5 3.4 ns
B to A; CL = 15 pF 0.7 2.3 3 ns
ten enable time OE to A, B; CL = 15 pF 8 25 50 ns
[2] [3]
tdis disable time OE to A; no external load 10 25 ns
[3]
OE to B; no external load 10 25 ns
OE to A; CL = 15 pF 50 ns
OE to B; CL = 15 pF 50 ns
tt transition time A port; CL = 15 pF 0.5 1.2 1.7 ns
B port; CL = 15 pF 0.7 1.7 2.5 ns
[4]
tsk(o) output skew time delta between channels 0 0.1 0.2 ns
tW pulse width data inputs 13.5 ns
fdata data rate 0.064 52 Mbps

[1] tpd is the same as tPLH and tPHL; ten is the same as tPZL and tPZH; tdis is the same as tPLZ and tPHZ; tt is the same as tTHL and tTLH.
[2] Guaranteed by design.
[3] Delay between OE going LOW and when the outputs are actually disabled.
[4] Skew between any two outputs of the same package switching in the same direction. One channel is not always faster than the other.

[1]
Table 13. Dynamic characteristics for temperature range -40 °C to +125 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 4; for waveform see Figure 3.
Symbol Parameter Conditions VCCB VCCB Unit
1.2 V ± 10 % 1.8 V ± 10 %
Min Typ Max Min Typ Max
VCCA = 0.8 V ± 10 %
tpd propagation delay A to B; CL = 15 pF 2.1 5.6 7.7 1.7 3.9 5.3 ns

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2
Dual bidirectional I3C/I C-bus and SPI voltage-level translator
[1]
Table 13. Dynamic characteristics for temperature range -40 °C to +125 °C ...continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 4; for waveform see Figure 3.
Symbol Parameter Conditions VCCB VCCB Unit
1.2 V ± 10 % 1.8 V ± 10 %
Min Typ Max Min Typ Max
B to A; CL = 15 pF 1.2 10.6 19.9 0.5 9.6 17.2 ns
ten enable time OE to A, B; CL = 15 pF 16 125 150 16 120 160 ns
[2] [3]
tdis disable time OE to A; no external load 10 25 10 25 ns
[3]
OE to B; no external load 10 25 10 25 ns
OE to A; CL = 15 pF 50 50 ns
OE to B; CL = 15 pF 50 50 ns
tt transition time A port; CL = 15 pF 2.1 8.5 17.5 1.5 9 15.4 ns
B port; CL = 15 pF 1.1 4 5.8 0.7 1.5 2.1 ns
[4]
tsk(o) output skew time delta between channels 0 0.2 0.4 0 0.2 0.4 ns
tW pulse width data inputs 37 37 ns
fdata data rate 0.064 26 0.064 26 Mbps

[1] tpd is the same as tPLH and tPHL; ten is the same as tPZL and tPZH; tdis is the same as tPLZ and tPHZ; tt is the same as tTHL and tTLH.
[2] Guaranteed by design.
[3] Delay between OE going LOW and when the outputs are actually disabled.
[4] Skew between any two outputs of the same package switching in the same direction. One channel is not always faster than the other.

[1]
Table 14. Dynamic characteristics for temperature range -40 °C to +125 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 4; for waveforms see Figure 3 and Figure 4.
Symbol Parameter Conditions VCCB VCCB Unit
1.2 V ± 10 % 1.8 V ± 10 %
Min Typ Max Min Typ Max
VCCA = 1.2 V ± 10 %
tpd propagation delay A to B; CL = 15 pF 1.5 4.5 6.2 1.0 2.5 3.6 ns
B to A; CL = 15 pF 1.1 3.9 5.4 0.6 2.8 4.0 ns
tpdc propagation delay A to B; CL = 80 pF NA NA NA 2.5 4.9 7.4 ns

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Dual bidirectional I3C/I C-bus and SPI voltage-level translator
[1]
Table 14. Dynamic characteristics for temperature range -40 °C to +125 °C ...continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 4; for waveforms see Figure 3 and Figure 4.
Symbol Parameter Conditions VCCB VCCB Unit
1.2 V ± 10 % 1.8 V ± 10 %
Min Typ Max Min Typ Max
B to A; CL = 30 pF NA NA NA 0.9 3.4 5.3 ns
ten enable time OE to A, B; CL = 15 pF 10 50 100 10 50 100 ns
[2] [3]
tdis disable time OE to A; no external load 10 25 10 25 ns
[3]
OE to B; no external load 10 25 10 25 ns
OE to A; CL = 15 pF 50 - 50 ns
OE to B; CL = 15 pF 50 - 50 ns
tt transition time A port; CL = 15 pF 0.8 2.6 3.5 0.6 1.5 2.6 ns
B port; CL = 15 pF 1.1 3.6 5.1 0.6 1.3 2.3 ns
ttc transition time A port; CL = 30 pF NA NA NA 1.0 2.2 3.8 ns
B port; CL = 80 pF NA NA NA 2.5 4.3 6.9 ns
[4]
tsk(o) output skew time delta between channels 0 0.1 0.2 0 0.1 0.3 ns
tW pulse width data inputs 15 13.5 ns
fdata data rate 0.064 52 0.064 52 Mbps

[1] tpd is the same as tPLH and tPHL; ten is the same as tPZL and tPZH; tdis is the same as tPLZ and tPHZ; tt is the same as tTHL and tTLH.
[2] Guaranteed by design.
[3] Delay between OE going LOW and when the outputs are actually disabled.
[4] Skew between any two outputs of the same package switching in the same direction. One channel is not always faster than the other.

[1]
Table 15. Dynamic characteristics for temperature range -40 °C to +125 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 4; for waveforms see Figure 3 and Figure 4.
Symbol Parameter Conditions VCCB Unit
1.8 V ± 10 %
Min Typ Max
VCCA = 1.8 V ± 10 %
tpd propagation delay A to B; CL = 15 pF 1 2.5 3.5 ns

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Dual bidirectional I3C/I C-bus and SPI voltage-level translator
[1]
Table 15. Dynamic characteristics for temperature range -40 °C to +125 °C ...continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 4; for waveforms see Figure 3 and Figure 4.
Symbol Parameter Conditions VCCB Unit
1.8 V ± 10 %
Min Typ Max
B to A; CL = 15 pF 0.7 2.3 3.1 ns
ten enable time OE to A, B; CL = 15 pF 8 25 50 ns
[2] [3]
tdis disable time OE to A; no external load 10 25 ns
[3]
OE to B; no external load 10 25 ns
OE to A; CL = 15 pF 50 ns
OE to B; CL = 15 pF 50 ns
tt transition time A port; CL = 15 pF 0.5 1.2 1.7 ns
B port; CL = 15 pF 0.7 1.7 2.6 ns
[4]
tsk(o) output skew time delta between channels 0 0.1 0.2 ns
tW pulse width data inputs 13.5 ns
fdata data rate 0.064 52 Mbps

[1] tpd is the same as tPLH and tPHL; ten is the same as tPZL and tPZH; tdis is the same as tPLZ and tPHZ; tt is the same as tTHL and tTLH.
[2] Guaranteed by design.
[3] Delay between OE going LOW and when the outputs are actually disabled.
[4] Skew between any two outputs of the same package switching in the same direction. One channel is not always faster than the other.

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12 Waveforms
VI
An, Bn
VM
input
GND
tPHL tPLH
VOH
80 %
Bn, An
VM
output
20 %
VOL
tTHL tTLH
aaa-033440

Measurement points are given in Table 16.

VOL and VOH are typical output voltage levels that occur with the output load.
Figure 3. Data input (An, Bn) to data output (Bn, An) propagation delay times

Table 16. Measurement points

VCCI is the supply voltage associated with the input and VCCO is the supply voltage associated with the output.
Supply voltage Input Output
VCCO VM VM VX VY
0.8 V ± 10 % 0.5VCCI 0.5VCCO VOL + 0.08 V VOH - 0.08 V
1.2 V ± 10 % 0.5VCCI 0.5VCCO VOL + 0.12 V VOH - 0.12 V
1.8 V ± 10 % 0.5VCCI 0.5VCCO VOL + 0.18 V VOH - 0.18 V

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tW
VI
80 %
negative
pulse VM VM
20 %
0V
tf tr

tr tf
VI
80 %
positive
pulse VM VM
20 %
0V
tW

VEXT
VCC
RL
VI VO
G DUT

CL RL

aaa-033441

Test data is given in Table 17.

All input pulses are supplied by generators having the following characteristics: PRR ≤ 26 MHz; ZO = 50 Ω; dV/dt ≥ 1.0 V/
ns.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
VEXT = External voltage for measuring switching times.
Figure 4. Test circuit for measuring switching times

Table 17. Test data

Supply voltage Input Load VEXT
[1] [2] [3]
VCCA VCCB VI Δt/ΔV CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ
0.72 V to 0.72 V to VCCI ≤ 1.0 ns/V 15 pF 50 kΩ, 1 MΩ open open 2VCCO
1.98 V 1.98 V

[1] VCCI is the supply voltage associated with the input.

[2] For measuring data rate, pulse width, propagation delay and output rise and fall measurements, RL = 1 MΩ; for measuring enable and disable times, RL =
50 kΩ.
[3] VCCO is the supply voltage associated with the output.

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13 Application information

13.1 Applications
Voltage level-translation applications. The P3A9606JK can be used to interface between
devices or systems operating at different supply voltages. See Figure 5, Figure 6,
Figure 7 and Figure 8 for a typical operating circuit using the P3A9606JK.

1.2 V 1.8 V
0.1 uF 0.1 uF

1.2 V VCCA VCCB 1.8 V

SCLK A1 B1 SCLK

SDATA A2 B2 SDATA

GPIO OE I3C
SoC P3A9606JK
FOLLOWER

GND GND GND

aaa-040892

Figure 5. I3C application block diagram

1.2 V 1.8 V
0.1 uF 0.1 uF
Rp Rp Rp Rp
1.2 V VCCA VCCB 1.8 V

SCL A1 B1 SCL

SDA A2 B2 SDA

GPIO OE I2C
MCU P3A9606JK
FOLLOWER

GND GND GND

aaa-040894
2
Figure 6. I C application block diagram

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1.2 V 1.8 V
0.1 uF 0.1 uF

1.2 V 1.8 V

VCCA VCCB
/CS A1 /CS
B1
SCLK A2
P3A9606JK.1 B2 SCLK
OE

GND

VCCA VCCB
MOSI A1 SPI
MCU B1 MOSI
MISO A2 FOLLOWER
P3A9606JK.2 B2
MISO
OE

Rd
GND

VCCA VCCB

/INT A1 B1 /INT
A2
P3A9606JK.3 B2
GPIO OE

GND GND GND

aaa-040895

Figure 7. SPI application block diagram

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VCCA= 1.2 V VCCB = 1.8 V

1.8 V
A1 B1 CS1
A2 P3A9606JK.1 B2 SCLK
SPI
A1 B1 MOSI FOLLOWER

A2 P3A9606JK.2 B2 MISO

Rd
1.2 V CS1 1.8 V
CS2 A1 B1 CS2
SCLK A2 P3A9606JK.3 B2 SCLK
SPI SPI
LEADER MOSI A1 B1 MOSI FOLLOWER

MISO A2 P3A9606JK.4 B2 MISO

CS4 CS3
1.8 V
1.2 V A1 B1 CS3
CS4
A2 P3A9606JK.5 B2 SCLK
SCLK SPI
SPI FOLLOWER
FOLLOWER MOSI MOSI
MISO
MISO
aaa-040896
Rd

Figure 8. Complex SPI block diagram

13.2 Architecture
The architecture uses edge-rate accelerator circuitry (for both the high-to-low and low-
to-high), N-Channel Pass gate transistor and a pull-up resistor (to provide DC-bias and
drive capabilities) to meet these requirements. The design is directionless and does not
need direction control signal. The implementation supports both low speed Open-drain
operation as well as high speed push-pull operation. The N-Channel Pass device will be
on only during Low input cycle and will be off during High input cycle.

13.3 Input driver requirements

The continuous DC- current sinking or sourcing capability is determined by the external
system-level; open-drain or push-pull drivers that are interfaced to the P3A9606JK IO
pins.
The high bandwidth of these IO circuits used to facilitate this fast change from an input to
an output and an output to an input, they have a modest sourcing capability of hundreds
of micro-amperes, as determined by the pull-up resistor.
The fall time of a signal depends on the edge-rate and output impedance of the external
driving the P3A9606JK data IOs, as well as the capacitive loading at the data lines.

13.4 Power-up and power-down

During operation, ensure that VCCA ≤ VCCB at all times. The sequencing of each power
supply will not damage the device during the power up operation, so either power
supply can be ramped up first. There is no special power-up sequencing required. The

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P3A9606JK includes circuitry that disables all output ports and puts the device into a
power-down mode when either VCCA or VCCB is switched off.

13.5 Enable and disable

An output enable input (OE) is used to disable the device. Setting OE = LOW causes all
I/Os to assume the high-impedance OFF-state. The disable time (tdis with no external
load) indicates the delay between when OE goes LOW and when outputs actually
become disabled. The enable time (ten) indicates the amount of time the user must allow
for one one-shot circuitry to become operational after OE is taken HIGH. To ensure the
high-impedance OFF-state during power-up or power-down, pin OE should be tied to
GND, OE pin should not be left floating in any condition.
OE VIL and VIH are referenced to VCCA. The OE can be controlled by an external device
that is powered by either VCCA or VCCB. As VCCB is required to be greater than VCCA,
the OE pin has been designed to withstand a voltage equal to VCCB (up to 1.98 V per
recommended functional voltage range).

13.6 Layout guidelines

To ensure reliability of the device, the following common printed-circuit board layout
guidelines are recommended:
• Bypass capacitors should be used on power supplies and should be placed as close as
possible to VCCA, VCCB, and GND pins.
• Short trace lengths should be used to avoid excessive loading.
• PCB signal trace-lengths must be kept short enough so that the round-trip delay of
any reflection is less than the one-shot duration, approximately 8 ns, ensuring that any
reflection encounters low impedance at the source driver.

LEGEND
Polygonal
VIA to Power Plane
Copper Pour
VIA to GND Plane (Inner Layer)

P3A9606JK

1 B2 B1 8
To System 0.1 µF To System
Bypass
Bypass 2 7
GND VCCB Capacitor
Capacitor
0.1 µF
Keep OE low until VCCA
3 VCCA OE 6
and VCCB are powered
up
4 A2 A1 5
To Controller To Controller

aaa-040897

Figure 9. P3A9606JK layout example

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14 Package outline

Figure 10. Package outline SOT2015-1

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Figure 11. Package outline SOT2015-1

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15 Soldering

Figure 12. Soldering footprint for SOT2015-1

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Figure 13. Soldering footprint for SOT2015-1

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Figure 14. Soldering footprint for SOT2015-1

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Figure 15. Soldering footprint for SOT2015-1

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16 Abbreviations
Table 18. Abbreviations
Acronym Description
CDM Charged Device Model
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
NMOS N-type Metal Oxide Semiconductor
PMOS P-type Metal Oxide Semiconductor
PRR Pulse Repetition Rate

17 Revision history
Table 19. Revision history
Document ID Release date Data sheet status Change notice Supersedes
P3A9606JK v.1.0 20210510 Product data sheet - -

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18 Legal information

18.1 Data sheet status

[1][2] [3]
Document status Product status Definition
Objective [short] data sheet Development This document contains data from the objective specification for product
development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
18.2 Definitions
Suitability for use — NXP Semiconductors products are not designed,
Draft — A draft status on a document indicates that the content is still authorized or warranted to be suitable for use in life support, life-critical or
under internal review and subject to formal approval, which may result safety-critical systems or equipment, nor in applications where failure or
in modifications or additions. NXP Semiconductors does not give any malfunction of an NXP Semiconductors product can reasonably be expected
representations or warranties as to the accuracy or completeness of to result in personal injury, death or severe property or environmental
information included in a draft version of a document and shall have no damage. NXP Semiconductors and its suppliers accept no liability for
liability for the consequences of use of such information. inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
Short data sheet — A short data sheet is an extract from a full data sheet risk.
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain Applications — Applications that are described herein for any of these
detailed and full information. For detailed and full information see the products are for illustrative purposes only. NXP Semiconductors makes
relevant full data sheet, which is available on request via the local NXP no representation or warranty that such applications will be suitable
Semiconductors sales office. In case of any inconsistency or conflict with the for the specified use without further testing or modification. Customers
short data sheet, the full data sheet shall prevail. are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
Product specification — The information and data provided in a Product accepts no liability for any assistance with applications or customer product
data sheet shall define the specification of the product as agreed between design. It is customer’s sole responsibility to determine whether the NXP
NXP Semiconductors and its customer, unless NXP Semiconductors and Semiconductors product is suitable and fit for the customer’s applications
customer have explicitly agreed otherwise in writing. In no event however, and products planned, as well as for the planned application and use of
shall an agreement be valid in which the NXP Semiconductors product customer’s third party customer(s). Customers should provide appropriate
is deemed to offer functions and qualities beyond those described in the design and operating safeguards to minimize the risks associated with
Product data sheet. their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
18.3 Disclaimers responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
Limited warranty and liability — Information in this document is believed customer’s third party customer(s). NXP does not accept any liability in this
to be accurate and reliable. However, NXP Semiconductors does not respect.
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability Limiting values — Stress above one or more limiting values (as defined in
for the consequences of use of such information. NXP Semiconductors the Absolute Maximum Ratings System of IEC 60134) will cause permanent
takes no responsibility for the content in this document if provided by an damage to the device. Limiting values are stress ratings only and (proper)
information source outside of NXP Semiconductors. In no event shall NXP operation of the device at these or any other conditions above those
Semiconductors be liable for any indirect, incidental, punitive, special or given in the Recommended operating conditions section (if present) or the
consequential damages (including - without limitation - lost profits, lost Characteristics sections of this document is not warranted. Constant or
savings, business interruption, costs related to the removal or replacement repeated exposure to limiting values will permanently and irreversibly affect
of any products or rework charges) whether or not such damages are based the quality and reliability of the device.
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
Terms and conditions of commercial sale — NXP Semiconductors
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
products are sold subject to the general terms and conditions of commercial
liability towards customer for the products described herein shall be limited
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
in accordance with the Terms and conditions of commercial sale of NXP
agreed in a valid written individual agreement. In case an individual
Semiconductors.
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
Right to make changes — NXP Semiconductors reserves the right to applying the customer’s general terms and conditions with regard to the
make changes to information published in this document, including without purchase of NXP Semiconductors products by customer.
limitation specifications and product descriptions, at any time and without

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No offer to sell or license — Nothing in this document may be interpreted such automotive applications, use and specifications, and (b) whenever
or construed as an offer to sell products that is open for acceptance or customer uses the product for automotive applications beyond NXP
the grant, conveyance or implication of any license under any copyrights, Semiconductors’ specifications such use shall be solely at customer’s own
patents or other industrial or intellectual property rights. risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use
Export control — This document as well as the item(s) described herein of the product for automotive applications beyond NXP Semiconductors’
may be subject to export control regulations. Export might require a prior standard warranty and NXP Semiconductors’ product specifications.
authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified, 18.4 Trademarks
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements. Notice: All referenced brands, product names, service names and
NXP Semiconductors accepts no liability for inclusion and/or use of non- trademarks are the property of their respective owners.
automotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive 2
I C-bus — logo is a trademark of NXP B.V.
applications to automotive specifications and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for NXP — wordmark and logo are trademarks of NXP B.V.

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Tables
Tab. 1. Ordering information ..........................................2 Tab. 12. Dynamic characteristics for temperature
Tab. 2. Ordering options ................................................2 range -40 °C to +85 °C ................................... 10
Tab. 3. Pin description ...................................................3 Tab. 13. Dynamic characteristics for temperature
Tab. 4. Function table ....................................................3 range -40 °C to +125 °C ................................. 10
Tab. 5. Limiting values .................................................. 4 Tab. 14. Dynamic characteristics for temperature
Tab. 6. Recommended operating conditions ................. 4 range -40 °C to +125 °C ................................. 11
Tab. 7. Thermal characteristics ..................................... 5 Tab. 15. Dynamic characteristics for temperature
Tab. 8. Typical static characteristics ..............................5 range -40 °C to +125 °C ................................. 12
Tab. 9. Static characteristics ......................................... 6 Tab. 16. Measurement points ........................................14
Tab. 10. Dynamic characteristics for temperature Tab. 17. Test data ..........................................................15
range -40 °C to +85 °C .....................................8 Tab. 18. Abbreviations ...................................................26
Tab. 11. Dynamic characteristics for temperature Tab. 19. Revision history ...............................................26
range -40 °C to +85 °C .....................................9

Figures
Fig. 1. Block diagram ................................................... 2 Fig. 8. Complex SPI block diagram ............................18
Fig. 2. Pin configuration SOT2015-1 ............................ 3 Fig. 9. P3A9606JK layout example ............................ 19
Fig. 3. Data input (An, Bn) to data output (Bn, An) Fig. 10. Package outline SOT2015-1 ........................... 20
propagation delay times .................................. 14 Fig. 11. Package outline SOT2015-1 ........................... 21
Fig. 4. Test circuit for measuring switching times ....... 15 Fig. 12. Soldering footprint for SOT2015-1 .................. 22
Fig. 5. I3C application block diagram ......................... 16 Fig. 13. Soldering footprint for SOT2015-1 .................. 23
Fig. 6. I2C application block diagram ......................... 16 Fig. 14. Soldering footprint for SOT2015-1 .................. 24
Fig. 7. SPI application block diagram .........................17 Fig. 15. Soldering footprint for SOT2015-1 .................. 25

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Contents
1 General description ............................................ 1
2 Features and benefits .........................................1
3 Ordering information .......................................... 2
3.1 Ordering options ................................................ 2
4 Block diagram ..................................................... 2
5 Pinning information ............................................ 3
5.1 Pinning ............................................................... 3
5.2 Pin description ................................................... 3
6 Functional description ........................................3
7 Limiting values .................................................... 4
8 Recommended operating conditions ................ 4
9 Thermal characteristics ......................................5
10 Static characteristics .......................................... 5
11 Dynamic characteristics .....................................8
12 Waveforms ......................................................... 14
13 Application information .................................... 16
13.1 Applications ......................................................16
13.2 Architecture ......................................................18
13.3 Input driver requirements .................................18
13.4 Power-up and power-down ..............................18
13.5 Enable and disable ..........................................19
13.6 Layout guidelines .............................................19
14 Package outline .................................................20
15 Soldering ............................................................22
16 Abbreviations .................................................... 26
17 Revision history ................................................ 26
18 Legal information .............................................. 27

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.

© NXP B.V. 2021. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 10 May 2021
Document identifier: P3A9606JK