UNIVERSITY OF BRISTOL

FACULTY OF ENGINEERING

First-Year Examination for the Degrees

of
Bachelor and Master of Engineering

MAY/JUNE 2008 3 Hours

DIGITAL CIRCUITS & SYSTEMS

EENG 14000

INSERT YOUR CANDIDATE NUMBER:________________

This question paper is to be left on your desk at the end of the examination with any
rough work crossed through.

This paper contains three sections - A, B, and C - and you should attempt all three
sections.

Each question is labelled with its marks value.

Within each section, the questions are arranged in order of increasing value.

In Section A, you should attempt questions with marks labels totalling 50.
In Section B, you should attempt questions with marks labels totalling 25.
In Section C, you should attempt questions with marks labels totalling 25.

The Examiner will not mark any attempts beyond this limit. Credit for the final question
marked in each section will be capped if necessary to respect the limit.

Answer each section in the appropriate printed answer book provided. Do not show
working unless the question asks for it.
Only calculators bearing the Faculty of Engineering Seal of Approval may be used

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SECTION A
This Section contains 18 questions, each labelled to show the marks available for a
completely correct answer. Attempt your own choice of whole questions from this
Section, ensuring that the marks labels add up to 50. The examiner will mark your
attempts in order of question number until the "50 marks attempted" point is reached. If
this point occurs part way through a question, the marks for that question will be capped
as necessary.

QA1 State the number of control input lines needed for a 2:1 multiplexer.
(1 mark)

QA2 One input of a 2-input NOR gate is tied to logic 1. State what logic value
appears at its output.
(1 mark)

QA3 Give the maximum number of states for a sequential system having 4 binary
state variables.
(1 mark)

QA4 State the maximum number of places that the 8-bit 2's complement bit-pattern
11111010 could be shifted arithmetically left without causing overflow.
(2 marks)

QA5 Give (in binary) the ones' complement of the bit pattern 10101010.
(2 marks)

QA6 A gate that provides the NOT function in positive logic is taken to a negative-
logic environment. State what function it provides there.
(2 marks)

QA7 An 8-bit register containing the value 1F16 is shifted cyclically one place to the
right. Give the new value (in hexadecimal).
(2 marks)

QA8 Give the inverse of DEF' + GH.

(2 marks)

QA9 State how many NOT gates are required for a 3:8 decoder constructed from NOT
and AND gates.
(2 marks)

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QA10 Consider a VHDL bit array defined as A(7 downto 0). After a certain shift is
applied, the resulting value is A(7)&A(7)&A(7)&A(7)&A(7)&(7 downto 5).
Give the type of shift, its direction, and the number of places.
(5 marks, split 1 + 1 + 3)
QA11 Consider the following VHDL code:
myvalue <= P&Q;
with myvalue select W = R when "00", '0' when "01", '1' when others;
Give the minimal SOP expression for W in terms of P, Q, R.
(5 marks)

QA12 You are asked to help design a full adder, which takes two input data bits, a and
b, and a carry bit, cin, and generates a sum bit, s, and a carry bit, cout. Suppose
you are told that you can assume that a and b will always be equal to each other.
Give the minimal SOP expression for s and for cout.
(5 marks, split 2.5 + 2.5)

QA13 A certain system stores floating-point numbers in normalised form, such that the
mantissa, m, satisfies 1 ≤ m < 2. It uses the "hidden bit" convention, so that only
the part of the mantissa to the right of the binary point is stored; the "1·" is
simply assumed. If 4 bits are allowed for storing the mantissa and 3 bits for the
exponent, and both are unsigned, give (as integers) the smallest and largest
values that can be represented.
(5 marks, split 2 + 3)

QA14 Using Boolean Algebra or Karnaugh Map, give the minimal POS expression for
the function B = D + EF + FG'.
(5 marks)

QA15 Give the minimal SOP expression for the function Z of inputs P, Q, R, S, which
form an integer when viewed as "PQRS". Z is true if, and only if, the integer is
either 2, 8 or 10, or equals 4 or one of its multiples. The combination
P=Q=R=S=0 can't happen.
(5 marks)

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QA16 A Moore state machine with 7 states is implemented using the smallest necessary
ROM for its combinatorial logic and the minimal necessary number of JK flip-
flops for its state register. The ROM generates the flip-flop driver signals as
well as the system's outputs. It has 8 address lines and it outputs 8 data bits.
a) Give the number of binary "present state" signals.
b) Give the number of 8-bit locations is the ROM.
c) Give the number of binary inputs entering the system.
d) Give the number of flip-flop driver signals.
e) Give the number of binary outputs leaving the system.
(10 marks, split 2 each)

QA17 a) Draw the state-transition diagram for a Moore machine whose output, Z, is
1 if, and only if, the two most recent values received on its input line, X,
are 0 followed by 1. Label the starting state.

b) Most of the documentation for a state machine using two JK flip-flops has
been lost. However, it is known that Ja=Ka=b' and Jb=Kb=1. The machine
is currently in state ab=00. List, in order, the states that will be visited as a
result of the next three clock cycles.
(10 marks, split 6 + 4)
QA18 a) A counter with no inputs and using D-type flip-flops has a PLA as its
combinatorial logic. Its state variables (and outputs) are x, y, z and follow
the sequence 000, 010, 111, 100, 011, 000….The PLA table is as shown in
Table QA18 but has one row missing. Give the missing row.

x y z Dx Dy Dz
1 1 - 1
0 0 - 1
- - 0 1
1 0 0 1
Table QA18
b) The term "- - 0" is equivalent to n separate terms with all three variables
fully defined. Give the value of n.
c) Suppose the machine somehow gets into the unused state 101. Say what
its next state will be.
(10 marks, split 5 + 2 + 3)

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SECTION B
This Section contains 8 questions, each labelled to show the marks available for a
completely correct answer. Attempt your own choice of whole questions from this
Section, ensuring that the marks labels add up to 25. The examiner will mark your
attempts in order of question number until the "25 marks attempted" point is reached. If
this point occurs part way through a question, the marks for that question will be capped
as necessary.

QB1 Name the addressing mode in which the address of the operand is in one of the
CPU's registers.
(1 mark)

QB2 Name the register which is checked by conditional branches to determine

whether or not to branch.
(2 marks)

QB3 Name the mechanism by which a hardware stimulus forces the current
programme to be suspended and a new routine to be executed instead.
(2 marks)

QB4 Consider the instructions
ldaa #mike + jane and ldaa #jane. Say
whether they would take the same time to run on the 68HCS12, or
would take
longer than , or  would take longer than
.
(2 marks)

QB5 A first-year student using the 68HCS12 wants to use the addressing mode
"indirect via register Y" to read values from a table. The table, which happens to
start at address 0x2000, is defined by the following statement:
brian: fcb 0x33, 0xa7, 0x54, 0x2a, 0xc3, 0x44
a) The student tries to initialise Y using the instruction ldy brian. Give the
resulting value of Y.
b) Having amended the error in (a), the student writes a loop in which the
instruction ldab ,y is used correctly to read each table value. At the bottom
of the loop, after incrementing Y, the comparison cpy #brian+4 is done,
followed by a bne to continue the loop if taken, else to quit the loop. Give
the last value read from the table.
(5 marks, split 2 + 3)

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QB6 Say whether each of the following sentences is true or false (assume the
microprocessor and development system used in the DCS laboratory).
a) The machine code of the instruction ldaa ,x when stored in memory
consists of the ASCII code for "ldaa ,x".
b) The machine code of the instruction ldab #0x8A when stored in memory
includes the bit-pattern 10001010.
c) Each use of a jsr instruction should be preceded immediately by an lds
instruction to initialise the stack pointer.
d) The statement sue equ 5 generates a byte with value 5 at the current
position in the machine code of the program.
e) A bne instruction must always be preceded by a compare instruction.
(1 mark for each. If you are not sure of the answer, it’s best to leave it
unanswered so that you avoid losing a mark for the wrong answer).
(5 marks)
QB7 In the 68HCS12, the stack grows towards address 0 and the stack pointer is left
pointing at the top-of-stack item. 16-bit items are stacked as two consecutive
bytes, with the less significant half PUSHed first. For each of the sub-questions
below, assume the following starting register values every time (all values are in
hexadecimal): A=23; B=4A; X=2143; S=3FFF. Note that register D is register
A and Register B joined (A:B) to form a 16-bit register. Show the value of the
requested registers and memory locations at the end of each sequence of
instructions shown. If insufficient information is provided for a value, say
"undefined".

Instruction sequence Show

a) pshd S, 3FFD, 3FFE, 3FFF
b) psha pulb A, B
c) pshx pulx pulb X, B, S
(10 marks, split 1 + 1 + 1 + 2 + 1 + 1 + 1 + 1+ 1)
QB8 (All numbers in this question are decimal (base ten).) You are using a
microcontroller that has a timer comprising an 8-bit register incrementing
continually once per clock tick (one millisecond); whenever it reaches 255 (its
"all ones" value) it overflows to "all zeroes" on the next tick and continues. To
delay for interval ticks, you use the following:
ldaa timer
adda #interval
check: cmpa timer
bne check
a) To avoid "missing" the match between timer and register A, the
instructions must be executed fast enough. Write this requirement as an
inequality (e.g. "the ldaa and the cmpa together must take <5ms").
b) If that requirement could not be met, a programmer might try replacing the
bne by the unsigned bgt (branch if greater than). If t is the timer value
read by the ldaa instruction, and i is the interval, write an inequality
involving t and i to show when this approach would fail.

(10 marks, split 4 + 6)

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SECTION C

This Section contains 9 questions each labelled to show the marks available for a
completely correct answer. Attempt your own choice of questions from this section,
ensuring that the marks labels add up to 25. The examiner will not mark any excess
attempts, and will stop in mid-question if necessary

QC1 Draw the symbol for an n-p-n bipolar junction transistor (BJT) clearly labelled
with c, b, and e to show the collector, base and emitter respectively.
(1 mark)

(ii) G W

D
p+

L (i)
p+
channel
(iii) region

Figure QC2 MOS field effect

transistor.

QC2 Figure QC2 shows the cross section of a MOS FET. State the names of the parts
labelled (i) to (iii) and for (iv) state whether it is a n-type or p-type MOS FET.
(2 marks)
QC3 On the plot given in the answer book show the cut-off, saturation and the active
or linear regions on the output characteristic of the BJT.
(2 marks)
QC4 The figure in the answer book shows the cross section of a BJT. State the names
of the parts labelled (i) to (iii) and for (iv) state whether it is a p-n-p or n-p-n
device. On the diagram show the electron flow from the emitter when base and
collector currents are flowing.
(3 marks)
QC5 The figure in the answer book shows the cross sections of n-type and p-type
MOS FET devices. On each diagram draw the shape of the channel region as
would occur for the given voltage levels. (Hint:- one is in the triode or linear
region, the other is well into saturation.)
(3 marks)

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QC6

F2

Figure QC6 A 3-input CMOS

logic circuit

Write the logic expression for the CMOS circuit in Figure QC6.
(4 marks)

QC7
+4.5V
Vt = 1.5V 900Ω
ID
4.1V g d
s VD
Q1

Figure QC7 n-MOS FET inverter

with load resistor

Figure QC7 above shows a simple n-MOS FET inverter. In the answer book
is shown the output characteristic for the FET used. Using the load line
technique, or any other method, calculate the drain current and voltage ID
and VD respectively. The threshold voltage for the FET is 1.5V.
(4 marks)

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QC8 12V
2.2 kΩ 10kΩ
D1
A
X F
D2 D
B
D6
D3

C Y D5
D4 1.5 kΩ

Figure QC8 A multi-level diode

logic circuit
The circuit in Figure QC8 above is a diode logic function with inputs A, B,
C and D and output F.
i) Determine the voltages at nodes X, Y, and F assuming all the diodes
are ideal and enter the answers in the table given in the answer book.
ii) Hence or otherwise determine the logic function, F, for a positive
logic convention when logic 1 is 2V and logic 0 is 6V.
iii) When A = 2V, B = 6V, C = 1V and D = 6V calculate, using ideal
diodes, the current in diodes D1, D3, D5 and D6.
(10 marks)

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QC9 The CMOS logic circuit in Figure QC9 has inputs W, X, Y and Z. It has an
incorrect p-type network.
i) Prove that the p-network is not consistent with the n-type network.
ii) Draw the correct circuit for the p-type network (in the partly completed
pre-drawn solution).
iii) Determine the logic function, F2.
(10 marks)

F2
Y

Figure QC9 CMOS circuit.

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