Digital CMOS Library Design

João Lucas Munhão

[email protected]

Instituto Superior Técnico, Lisboa, Portugal

October 2017

Abstract
Digital cell characterization is essencial in modern integrated circuits digital design flow. Liberty
files that contain information about propagation time delay, timing constraints in sequencial cells and
both dynamic and static power consumption are the cornerstone of this type of work. They can be
obtained by simulating standard cells with different combinations of supply voltage, temperature,
load capacity and MOS propagation speed (corners) . The simulation time is substantially reduced
with liberty files in backannotation, compared with analog, SPICE, simulations. The goal therefore
is to create a methodology and respective software capable of assisting a digital design engineer in
characterizing digital cell libraries.
Keywords: digital design flow, digital cell library, cell characterization, corner analysis, liberty file

1. Introduction 2. Background
The increased complexity of ICs and the increas- 2.1. Previous Work
ing transistor density per unit area have greatly in- In [9], Sulistyo uses the Non-Linear Delay Model
creased the time needed to simulate this type of (NLDM) for cell characterization, giving detailed
circuits. Therefore a simplified model for delay, description for time delay analysis and power char-
power, capacitance and function was developed on acterization using SPICE testbenches for various
cell/gate level, where simulation with completely types of cells.
modelled transistors is a lot simpler and less time In [4], Goyal and Kumar discuss limitations of
consuming. characterizing sub 90 nm technologies. Increased
By simulating the small building blocks first in wiring delays, interconnect resistances and non-
different conditions, the time needed to create and linearity of waveforms are not taken into account
validate large ICs is reduced considerably, cutting by the NLDM. Cadence’s ECSM models and Syn-
costs and allowing faster development of newer de- opsys’ CCS models are possible solutions which this
signs. The data from this simulations are compiled paper analyzes and compares with SPICE models.
in timing and power characterization files. The smaller cell footprint also meant short chan-
In a partnership with SiliconGate R
, a company nel effects became extremely important as stated
specialized in developing state-of-the-art IPs, a pro- in [1]. With this issue becoming relevant in two di-
posal was made to develop a methodology and a mensional (2D) transistor design, three dimensional
software capable of characterizing standard cell li- (3D) transistor design, FinFETs, with better leak-
braries. age current characteristics were developed, [5]. In
The aim of this work is to develop a powerful [12], Yuan et al. propose a method for characteriz-
tool and respective methodology capable of creating ing this type of cells using a surface potential based
library characterization files. model called BSIM-CMG.
Section 2 discusses previous work done concern- In [3], Kenza and Ouardi describe a methodology
ing library characterization and explains the Synop- based on the so called Scalable Polynomial Delay
sys Liberty file format, section 3 gives an introduc- Model (SPDM), which is a equation based charac-
tion on the developed methodology, section 4 de- terization method, capable of reducing simulation
scribes the testbench design flow, section 5 explains time by staggering values as it only needs to write
the methods’ scripts, section 6 illustrates the pro- a single library for all operating conditions and op-
cess of characterizing a standard cell and discusses erating ranges of a particular technology. However
the validity of the method, and, finally, section 9 it loses accuracy as it models cell delay behaviour
compiles the methods merits, problems and limita- using a very limited number of variables.
tions and discusses future work. In [6], Nareshkumar estimates the setup and hold

1
times of a cell through Statistical Static Timing
Analysis (SSTA), claiming high accuracy and faster
simulations times for the cells tested.
2.2. Synopsys Liberty Format
During digital design flow, the simulation and P%R
software can refer to time characterization files to
estimate propagation delay through the different
critical and non-critical circuit paths. This charac-
terization is done based on process corners, which
are different combinations of input slew rate, out-
put load capacitance, operating temperature, sup-
ply voltage, transistor technology, among others.
Power consumption can also be estimated using the
liberty files. The Synopsys Liberty format is the
most widely adopted by the industry and therefore
is the one chosen for this project. The files have a
very specific syntax that must be respected, as seen Figure 1: Methodology for digital library character-
in Code 1 ization.
Code 1: Liberty file library and general parameters
definition.
library ( name ) { fed into the cell, and each input signal combination
technology ( name ) ; /* library - level attributes will induce a certain behaviour on the cell’s out-
*/ puts. These testbenches have to be designed man-
delay_model : table_lookup ;
bus_naming_ s t y l e : string ; ually, due to their complexity. Therefore, an useful
... feature is reusability. Two cells from two different
time_unit : unit ; digital cell libraries may share the same functional-
voltage_unit : unit ;
current_unit : unit ; ity, input pin name and number, e.g. an inverter,
p u l l i n g _ r e s i s t a n c e _ u n i t : unit ; therefore, the same testbench can be used for both
c a p a c i t i v e _ l o a d _ u n i t ( value , unit ) ; cells. Anytime a new testbench is designed, it is
l ea ka g e_ p ow e r _ u n i t : unit ;
also stored in a repository for future use.
nom_process : value ;
nom_temperat ur e : value ;
After designing the necessary, non-existing, test-
nom_voltage : value ; benches, gen netlist.py makes a matchmaking be-
tween the cell’s netlist and the testbenches in the
o p e r a t i n g _ c o n d i t i o n s ( name ) {
/* operating conditions */
repository directory. If a cell’s schematic is up-
} dated, it’s only necessary to reextract its netlist and
lu _ta ble_ te m p l a t e ( name ) { rerun the script to have the files ready for simula-
/* time lookup table template information */
}
tion.
... Next, a script manages and launches the cor-
cell ( name1 ) {/* cell definitions */
/* cell information */
ners’ HSPICE simulations. The script can launch
} the simulations in multiple Central Processing Unit
... (CPU) cores, speeding up the total simulation time.
This files are primarily constructed by group After obtaining the simulation results,
statements inside curly brackets ({). Each group lib designer.py can be run. The script needs
statement has its own subgroups and attributes. an empty liberty file shell, which is a pre-made file
Example of groups are library, cell and pin. containing keywords that the script identifies and
substitutes with measured data. This facilitates the
3. Liberty File Generation Methodology writing of liberty files, minimizing code complexity.
The developed methodology is capable of character-
izing a cell’s time, power and pin capacitance char- The obtained liberty files can then be verified by
acteristics. It is the direct continuation of the work Synopsys’ Design Vision software, to ensure the files
done in SiliconGate, concerning digital library char- syntax are correct.
acterization. Figure 1 shows the developed method- The following sections give a more in-depth look
ology for characterizing a standard cell library. into the method, section 4 describes the testbench
The first thing needed to characterize a standard design and creation procees, while section 5 goes
cell, is a testbench. The testbench is a test environ- through each created script explaining its function-
ment for the cell, in it, different input pin stimuli are ality.

2
4. Digital Cells Characterization Testbench hold time is the time the input must remain stable
If a new, never before characterized cell is present after a capturing clock edge.
in a digital library. There are two possible ways
to create its testbench. A new one can be created
from scratch, or it can be adapted from an similar
one. The following measures should be included in
a testbench, for full charactetization of the cell.
4.1. Propagation Time Delays and Transition
Times
There are two important timing measurements to
characterize. Timing arcs and timing constraints.
Propagation timing delay refers to the time it takes
an input pin signal to drive the output pin signal
to a certain value.
Figure 2 shows the definition of delay and tran-
sition times for logic circuits. The input rise and
fall times are labeled tr and tf , whereas tLH and
tHL are the output rise and fall time. tP LH and
tP HL are the propagation delay for the rising and Figure 3: Clock to Q delay for different D pin tran-
falling edge respectively. The propagation delay is sitions before and after setup time.
measured from a 50% value change on the input
pin to a 50% value change on the output pin, while
the slew rate or transition time of the output is the
time the signal takes to vary from 10% to 90% on
a rising edge, while on a falling edge it’s from 90%
to 10% [2].

Figure 4: Clock to Q delay dependence with D to

clock time.
Figure 2: Delay and transition times definition.
In Figure 3 clock to Q delay is exemplified for
The propagation delay and slew rate are propor- different time intervals between a D pin transition
tional to the input transition and to the output and the capture clock edge, while in Figure 4 this
load. Due to this reason, the liberty file exhibits dependence is plotted. A safe estimation of setup
propagation delays and timing transitions as a 2 di- time, can be done, by finding the D to CLK edge
mensional table of input net transition versus out- time that causes a 10% increase in CLK to Q de-
put net capacitance. lay, relative to it’s nominal value. As this timing
measurements relate two input pins, their represen-
4.2. Timing Violations tation on liberty format will be a two dimensional
Sequential cells have other important time charac- table of the reference pin input net transition versus
teristics. Minimum pulse width can be defined for the related pin input net transition.
an input pin as the time between rising/falling edge Recovery and removal time are measures that
at 50% VDD till falling/rising edge at 50% VDD, characterize minimum separation times between
that guarantees a logic change at output. It de- asynchronous pins changes and clock edges in se-
pends specifically on the input transition rate, so quential cells. Recovery time is the time an asyn-
its liberty file table is unidimensional. chronous pin signal must be stable before a clock
Setup time is defined as the time the input needs edge, while removal time is the time such signal
to be stable before a capturing edge clock, while must be stable after a clock edge. Their LUT in-

3
dexes are the same ones of setup time
Code 2: Generic testbench directory tree.
4.3. Leakage Power .
‘-- ge ne r ic _n e tl is t
Leakage power is the power a standard cell dissi- | - - _and2
pates when both its inputs and outputs are not | ‘-- comb
making signal transitions. There are three main | | - - footer . cfg
| | - - header . cfg
reasons for leakage power, i) Junction Leakage, | ‘-- input . ckt
which results from the diffused p and n regions | - - _nand2
forming parasitic diodes [8]; ii) Gate-Oxide Leak- | ‘-- comb
| | - - footer . cfg
age, as in CMOS technology below 90nm, gate ox- | | - - header . cfg
ide tunneling is an important player in static power | ‘-- input . ckt
leakage as carriers (electrons) can tunnel from the ...
channel to the gate electrode [10]; iii) Subthreshold
Leakage, became more important with the constant
miniaturization of transistors and the resulting in-
crease in power dissipation per chip unit area, the ED = Esw + EI (5)
supply voltage has been scaled down, which led to
the reduction of the threshold voltage (Vth ) [7]. When an input transition does not cause a varia-
For measuring the static power in a cell, we can tion on the output, power consumption will only de-
use the following formula: pend on the input transition time, meaning a unidi-
mensional table can represent the power consump-
PSP = VDD × IDD (1) tion.
The Liberty files display leakage power values for When an input pin transition leads to an output
every input and output pin combination. transition, the power now will not only depend upon
the rise or fall transition of the input, but also on
4.4. Dynamic Power the load capacitance of the output, therefore a 2
Dynamic power is obtained by adding switching dimension table is required.
power consumption (PSW ) and internal power con-
sumption (PI ). Being this the total power, it can 4.5. Capacitance
be calculated as energy by: The input pin capacitance can be measured on rise
Z t2 and fall transitions that causes output pin transi-
tions, and can be measure using:
Etot = Vdd × IVdd dt (2)
t1 R t2
Switching power concerns the power necessary to Irise/f all dt
C = t1 (6)
charge or discharge an external load. For charac- Vdd
terization purposes the load is replaced by a capac-
Current integration measures made for power cal-
itor whose value during characterization is chosen
culations in 4.4 can again be used. The pin ca-
according to typical cell fan-out. The switching en-
pacitance corresponds to the average value of the
ergy can be written as:
measures, of rise and fall capacitance, through the
Z t2 Z Vdd different input net transitions and output load ca-
1 2 pacitances.
Esw = Vdd Isw = CVdd dv = CVdd (3)
t1 0 2 After creating the testbench for the new cell, its
files can be added to a testbench repository, whose
Internal power not only represents charging and directory tree is similar to code 2. Each testbench
discharging power of the cells’ internal nets, but also is divided in three files. The header contains the
power that is wasted due to momentary turn on of type of simulation. The input contains the stim-
NMOS and PMOS network that connects the cells’ uli, and the footer contains all the time, power and
supply and ground pins. capacitance measurements.
The internal power can be obtained by using Scripts
equations 2 and 3:
5. Method Scripts
Z t2
1 After having the testebenches prepared and in the
2
EI = Etot − Esw = Vdd × IVdd dt − CVdd (4) repository directory, we can now run the scripts re-
t1 2
sponsible for simulating the corners and generating
By summing both switching energy and internal the liberty files.
energy we get the total dynamic energy consumed Figure 5 contains the general steps the script
by a cell: takes to generate the liberty files.

4
 Figure 5: Automatic part of the characterization Flow.

After the creation of the testbench and their in- plained in section 4, requires different parameters
clusion on a testbench repository, gen netlist.py is combinations to produce its corners.
able to match and concatenate a cell netlist with the The script will then prepare the ’execution path’
correct testbench. The script lists all the cells in the folder by populating it with the necessary files for
digital library folder and matches their names with simulation, as in code 3.
the existing testbenches in the repository of code 2.
If a match is found, the script copies the files digital Code 3: Simulation folder directory tree.
library directory and concatenates the cells’ netlist .
|-- alter1_25 . inc
with them. |-- ...
After the testbench matchmaking process, ‘-- hspiceSim
lib maker.py takes over. This is the main script of |-- BA SICLIB_ nand2
| | - - alter1_25
the method, and it’s run in the following manner: | | | - - header . cfg
| | | - - input . ckt
$ ./lib maker.py ’path netlist folder’ | | | - - footer . cfg
| | | - - ...
’path empty lib shells’ ’execution path’ ...
|-- BA SICLIB_ dffnr
| | - - alter1_25
Where ’path netlist folder’ is the digital library
... ... ...
folder, in which its cell’s directories contain the re-
spective netlists, ’path empty lib shells’ is the di- After running the simulations, the cell’s alter di-
rectory containing the empty shell liberty files and rectories will have .mt# files with the simulations
’execution path’ is where the simulations are run results, ready to be written to a liberty file.
and the liberty files are created. The third and last script, lib designer.py is re-
A configuration file must be edited with the cor- sponsible for writing the simulation data into the
ner parameters and other necessary simulation con- liberty file. The script requires that the testbench
figurations, like the number o processors the script uses a standarized variable naming scheme. This is
can use. The script creates different types of alter useful to identify the type of measure, the input pin
files based on the corners parameters on the con- that causes a transition and the output pin that is
figuration file, on the number of processors and on affected. Facilitating the writing of the liberty file.
the type of simulation they shall be used to run. Here empty liberty shells are necessary. Like the
This is necessary as each type of measurement, ex- general testbenches described in section 4. Liberty

5
shells are created manually and can be used across done with the right signal edges at the right time.
similar cells of different technologies as they are cus- It is also necessary to make sure the output signals
tom made for each cell. A keyword system is used to have time to fully change it’s voltage value between
facilitate completion of the liberty file. The script input pin transitions, as slow corners (high load ca-
will look for keywords inside < and >, on the sim- pacitance, slow transistors and high temperature),
ulation results or in a cell configuration file that can lead to wrongful or failed measurements.
contains cell specific parameters. With the testbench created, the next step is to
The simulated data is indexed in three databases, break it apart to form the files that constitute the
one that links the .mt# file number to its specific generic testbench repository. This task can be done
corner, another that groups .mt# files indexes that together with the creation of the empty liberty shell.
contain data that will be part of the same liberty These tasks, together, need around 15 minutes to
file, and the last one that contains the data on each be completed.
.mt# file. This database, together with a digital With the testbench repository updated, the
librariy cells configuration file, containing cell spe- gen netlist.py script can be run anytime changes on
cific information like pin number and name, cell the cell design are made. Ensuring the characteri-
function, among others, are required to successfully zation uses the latest cell netlist.
write a liberty file. After each cell liberty file is Next, preparation to launch the main function,
written, they are concatenated based on the cor- lib maker.py, can start. The first thing to do is
ners they contain. to change the parameters on the configuration file.
After this, execution of the script will create the
6. Evaluation and Validation simulation folder, prepare the simulation files, the
In subsection 7 the characterization of a negative tree structure of code 3 and launch the simula-
edge D flip-flop is described, referring difficulties tions. Simulation time varies with the ammount
and the necessary hours to execute the job, while of CPU processors dedicated to the script and the
in subsection 8 a circuit using standard cells from with number of corners.
a 22nm standard cell library is simulated with Simulations for 25 corners, which corresponds to
HSPICE and a verilog backannotaded with a SDF a liberty file with 5 values of input net transition
file, generated using the liberty files. Both simula- and 5 values of output net capacitance, take around
tions are compared concernign the delay of various 30 minutes to complete.
corners measured.
During script development, a problem appeared
7. Evaluation in the simulation management algorithm. HSPICE
To evaluate the methodology created, the charac- simulations can include .lib files, called library files.
terization of a negative edge D flip-flop was done. HSPICE library files can make high-level state-
This cell was chosen due to the various type of time ments calls, contain netlists, model parameters, test
analysis it requires. vectors, types of analysis and option macros [11]. In
The flip-flop was designed in-house by the engi- characterization jobs, this files are used mainly to
neers of SiliconGate, so no previous characterization include transistors model types.
existed. During corner simulations the libraries to be in-
The following subsection describes the steps cluded can be changed. During characterization, as
taken to characterize the cell and the difficulties the simulations progressed, a new library include
found during the realization of this task. statement can be asserted with each alter. This
haa the unexpected result of gradually leading the
7.1. Negative edge D flip-flop characterization simulations to a halt.
The first step for the characterization is the creation To exemplify this issue, simulations of a corner
of the flip-flop testbench. with typical values were done. An alter with 25
The most time consuming task is designing an combinations of input slew rates and output capac-
stimuli that permits measurements of all the nec- itances was run, while mantaining temperature and
essary cell delay combinations, power consumption voltage constant at 25◦ C and 0.88 V respectively.
and pin capacitance. This usually takes around 9 Each simulation run 10 times to ensure the sim-
hours, as one needs to write the signal input on the ulation time was indeed correlated with the library
testbench, simulate, and then verify the measures inclusion statements. Two libraries, one for a MOS
correctness. Nonetheless, with the system of test- fast-fast model and another for layout characteris-
bench reusability developed, this is, at most, a one tics, were included.
time ocurrence. A signal viewer software and the Tables 1 and 2 display simulation time of the 25
simulation .lis file are the main tools in this phase. corners using two cells, the negative edge D flip flop
A designer will need to be going back and forward and the NAND with 2 inputs. The tables contain
between the two of them, to ensure the measures are two situations of library statement inclusions. On

6
 Table 1: Negative edge D flip-flop simulation time, using different alter files.
dffnr Simulation Time (s) Average
93.049 93.318 93.056 93.213 93.338
1 Inst 93.350 ± 0.129
93.279 93.250 93.665 93.866 93.468
244.168 244.842 249.947 248.267 249.457
25 Inst 244.168 ± 1.105
245.026 250.374 249.359 251.154 249.766

Table 2: NAND2 simulation time, using different alter files.

nand2 Simulation Time (s) Average (s)
46.274 46.419 45.950 46.081 45.862
1 Inst 46.192 ± 0.125
46.071 46.232 46.294 46.089 46.652
166.649 166.649 166.588 166.795 166.976
25 Inst 167.044 ± 0.476
166.626 167.133 168.721 165.709 168.598

the first, the library is only instantiated on the first A B Y

alter, on the second they are instantiated on every 0 0 0
alter statement. Note that temperature and voltage 0 1 1
parameters are the same in each alter file, however 1 0 1
that does not influence simulation time. 1 1 0
The MOS HSPICE models can be extremely com-
plex, even with a low number of corners, adding Table 3: XOR truth table.
the libraries in each alter statement dramatically
increases the simulation time. The solution found cludes an SDF file generated after a digital circuit’s
was to change the way alter files are created, where P&R , this file indicates not only the circuits cell de-
libraries definitions are only included in the first lay, provided by the liberty files, but also the cell’s
corner they appear. This hinted to the possibility interconnections delays. If we edit the file to not
of HSPICE actually mantaining in memory every include the latter, a comparison can be made be-
library included since the first simulation. tween the circuit’s delay with HSPICE and with
With the simulations finished, the last script can the verilog model.
be run. lib designer.py will compile the data and The first step, therefore, is to choose a circuit to
write the liberty file. As this script deals mainly be designed. The logic function XOR is a simple
with reading and writing data on disk, its execu- logic function that can be obtained using NANDs
tion time is minimal compared with creating the and NORs logic gates, table 3 displays the truth
testbench and simulating the corners. table of a XOR. The XOR output changes to high
In the end around 10 hours are needed to charac- exclusively if a single input is high and if both in-
terize the flip-flop. However 90 % of this time was puts are low or high, the outputs is low.
used to create the testbench, its now visible why To synthesize the circuit, Synopsys Design Com-
testbench reusability is so important. Is also im- piler is used. Design Compiler uses the verilog RTL
portant to notice that 25 corners is a small number model of the XOR, as in code 4, and the liberty files
of corners. On typical characterization jobs, thou- of a 22nm digital cell library to generate a gate-level
sands of corners are needed to fully characterize a netlist, which is a completely structural description
standard cell, requiring hours or days of simulation of the circuit using standard cells only.
to generate the necessary data to write the liberty
files for an entire digital cell library. Code 4: XOR logic RTL description.
module XOR_RTL ( y ,
a ,
8. Validation b
To validate the timing characterization done, a );
comparison between a circuit’s analog HSPICE sim-
// PORTS - - - - - - - - - - - -
ulation and the verilog model, with a SDF file back- output y ;
annotaded, can be used. input a ;
input b ;
The HSPICE models the standard cells transis-
tors, with great detail, so its simulations are closely // LOGIC - - - - - - - - - - - -
matched to reality, except the delays, caused by the assign y = ( a & ~ b ) | ( ~ a & b ) ;

circuits interconnections, not being modeled. The endmodule

backannotaded verilog model on the other hand, in-

7
 The resulting circuit is displayed in figure 6. The
circuit can be reextracted into a verilog model that
contains instantiations of the standard cells, code 5
displays the extracted model.

Figure 7: XOR testbench circuit.

layers and design rules, metal capacitances and via

definitions. These files are specific to each tech-
nology so they are provided by the foundry. The
digital library LEF file contains the description of
Figure 6: XOR synthesized circuit. each standard cell layout, for instance, its geome-
try, the different layers needed, the pins layout and
blockages.
Code 5: XOR logic synthesized description. With these files, P&R of the testbench is made.
module XOR_SYNT ( a , b , y , vdd , vss ) ; With the layout, RC extraction and SDF file gen-
output y ;
input a ;
eration is done.
input b ; A verilog and HSPICE testbench is created, fig-
input vdd ; ure 8 exemplifies the stimuli visualized on the pins
input vss ;
of XOR U3.
wire n5 ;
wire n6 ;
wire n7 ;
wire n8 ;

BASICLIB_na nd2 U6 ( . vdd ( vdd ) , . vss ( vss ) , . a (

n5 ) , . b ( n6 ) , . yz ( y ) ) ;
BASICLIB_na nd2 U7 ( . vdd ( vdd ) , . vss ( vss ) , . a ( b
) , . b ( n7 ) , . yz ( n6 ) ) ;
BASICLIB_inv U8 ( . vdd ( vdd ) , . vss ( vss ) , . y (
n8 ) , . yz ( n5 ) );
BASICLIB_nor2 U9 ( . vdd ( vdd ) , . vss ( vss ) , . a (
n7 ) , . b ( b ) , . yz ( n8 ) ) ;
BASICLIB_inv U10 ( . vdd ( vdd ) , . vss ( vss ) , . y ( a
) , . yz ( n7 ) );

endmodule

The Synthesis tool used three different types of

standard cells to generate the design, inverters, Figure 8: HSPICE and verilog stimuli.
NANDs and NORs. This will allow to evaluate the
accuracy of the characterization done using the lib- Four corners are used to compare the analog
erty files of this cells. HSPICE simulations and the backannotaded ver-
At this step a testbench was created for the de- ilog simulations. These corners correspond to com-
signed XOR. To simulate the XOR circuit integra- binations of two types of transitors models, typical-
tion in a larger design, other XOR cells were con- typical and fast-fast and two supply voltages, 1.62
nected to its inputs and output, this resembles the V and 1.8 V. The SDF files generated contain cell
typical driving strengths and output load capaci- delays at 125 ◦ C, so the HSPICE simulations were
tance the cell would receive if included in a larger also run at this temperature. Tables 4 and 5 dis-
circuit. In figure 7 the evaluated cell is U3. plays the delay between input and output pin tran-
After extracting the verilog model from the test- sitions of XOR U3, for the stimuli exemplified in
bench circuit, the next step is to run Cadence SoC figure 8, while table 6 presents the relative error.
Encounter to make the P&R. To run the software, Generally, the backannotaded verilog model
besides the synthesized verilog file and the digi- presents inferior cell delay when compared with the
tal library liberty files, its also necessary two LEF HSPICE simulation, with relative errors around 3.7
files, the technology LEF file and the digital library %. The inferior cell delay in verilog simulations,
LEF file. The technology LEF files contains specific can be a consequence of characterizing the stan-
properties of the technology, i.e. number of metal dard cells with the black box testbench illustrated

8
Table 4: XOR input to output delay in HSPICE Table 6: Relative error between the HSPICE and
simulation Verilog measures
Delay (ps) Relative Error (%)
HSPICE corner Comparison corner
mos-tt mos-ff mos-tt mos-ff
a b y 1.62 V 1.8 V 1.62 V 1.8 V a b y 1.62 V 1.8 V 1.62 V 1.8 V
rise low rise 173 152 156 139 rise low rise 7.5 8.9 8.4 10.3
fall low fall 182 163 167 150 fall low fall 1.8 3.2 2.4 3.1
low rise rise 77.7 67.5 69.8 61.6 low rise rise 3.5 1.6 2.4 1.8
low fall fall 79.2 68.9 70.8 62.6 low fall fall 0.6 0.7 1.3 2.2

Table 5: XOR input to output delay in Verilog sim- quential cells proved to be especially difficult, as op-
ulation timization testbenches need to be designed to char-
Delay (ps)
acterize the cells time constraints. The reusability
Verilog corner
of the testbenches partially solves this problem, but
mos-tt mos-ff
a b y 1.62 V 1.8 V 1.62 V 1.8 V is not the ideal solution.
rise low rise 186 166 169 153 The HSPICE simulation launch and management
fall low fall 185 168 171 155 script completely fulfills the objective of automati-
low rise rise 75.0 66.4 68.1 60.5 cally launching and managing HSPICE simulations
low fall fall 79.7 69.4 71.7 64.0 in a multicore environment. However, it lacked
tools to detect if the simulations failed or if the data
obtained was not valid. This limitation, partially
in figure 6. In real circuits, the drive strength on a hinders the methodology’s flow, as it’s necessary to
cell pin is limited by the current the cells connected manually correct these errors.
to the pin are capable of providing, as this current The liberty file writing script successfully au-
needs to charge the gate and the parasitics capac- tomizes every step needed to write a liberty file,
itante of the input pin. In the testbench, there is being an extremely realiable tool.
no limit to the current the Piece-Wise Linear volt- These scripts are based on a modular structure
age source can provide the cell, therefore the input and this proved to facilitate error detection and cor-
will rise on any specified time leading to shorter rection.
cell delay and consequently affecting also the pin The methodology was successfully validated,
capacitance and dynamic power measures, as this showing an average error of 3.7% in timing anal-
are measured when the cells’ input signals change ysis, when comparing the HSPICE transistor level
their values. With this results, its possible to in- simulation with the logic level simulation.
fer that in situations where supply voltage is even A complete digital cell library designed by Sil-
lower, the relative error will grow, as the supply iconGate was characterized. As a consequence of
voltage directly affects the cell output current, and being fully characterized by the corresponding lib-
therefore its drive strength capabilities. erty file, this digital cell library was the first to be
licensed for use by one of SiliconGate’s clients. This
9. Conclusions
result is an evidence that the present work fully
The aim of this work was to develop a methodology achieved its purposes, defining a new period in Sil-
and respective software capable of facilitating the iconGate’s digital cell characterization capability.
task of characterizing standard cell libraries.
The developed method streamlined the process 9.1. Future Work
of library characterization as much as possible, re- The general workflow suffers from limitations in the
ducing the ammount of manual tasks and maximiz- accuracy of the generated liberty files, therefore,
ing computer run phases. However problems were one of the first things to improve is the black box
encountered during the evaluation and validation test model used to characterize the liberty cells.
processes. A modification that can improve the method’s
The manual creation of testbenches proved to be flow is the automation of testbench creation. The
a laborious task to accomplish, the time and effort ideal software has to be capable of inserting speci-
needed to create a testbench for a cell’s timing arcs, fied input signals, detecting the evaluated cell logic,
power consumption and pin capacitance varies with creating a custom full-fledged test table and ensure
the cell’s logic function, nonetheless, it takes pre- the stimuli covers all the necessary cases needed to
cious time everytime a new digital cell library, with measure. This process becomes increasingly com-
new standard cells, needs to be characterized. Se- plex as one progress from combinational logic, to

9
sequential and tri-state logic. Nonetheless, full au- design based on curve fitting. In 2017 Inter-
tomation can only be obtained going down this national Conference on Wireless Technologies,
path. So future work on this area will seek to grad- Embedded and Intelligent Systems, 2017.
ually automize testbench design.
The NLDM used is also not the best existing de- [4] R. Goyal and N. Kumar. Current based delay
lay model to characterize standard cells. The Com- models: A must for nanometer timing. 2005.
posite Current Source (CCS) model can be the next [5] D. Hisamoto et al. FinFETA Self-Aligned
step in improving the accuracy of the simulations, Double-Gate MOSFET Scalable to 20 nm.
as these models take into account physical effects, IEEE Transactions on Electron Devices,
e.g. the effect of Miller capacitance on input pin 47(12):2320–2325, December 2000.
capacitance and net delay, in technology sizes infe-
rior to 90 nm. The implementation of this model [6] S. Nareshkumar. Probability Measurement of
would require changes on the way the liberty files Setup and Hold Time with Statistical Static
are written. Timing Analysis. Int. Journal of Engineering
The automatic identification of failed simula- Research and Applications, 5(1):38–41, Jan-
tions during characterization and the re-execution uary 2015.
of these simulations with different parameters is a
[7] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-
feature that needs to be implemented. It’s a fea-
Meimand. Leakage Current Mechanisms
ture necessary to facilitate a digital designer’s job
and Leakage Reduction Techniques in Deep-
and that can improve vastly the obtained results.
Submicrometer CMOS Circuits. Proceedings
The liberty file creation script, became rather
of IEEE, 91(2):305–327, February 2003.
complex with the great number of measures it
needed. So simplification of this tool’s workflow is [8] A. Sarwar. CMOS Power Consumption and
necessary. Cpd Calculation, June 1997. Texas Instruments
Scripts that do a relative validation of the gener- Application Report.
ated liberty files can also be designed. These scripts
would go through the look-up tables, comparing [9] J. B. Sulistyo. On the Characterization of Li-
the timing data to ensure it increases with capaci- brary Cells. Master’s thesis, Virginia Poly-
tance and input net transition. This of course, does technic Institute and State University, August
not verify if the results are exact, nonetheless it 2000.
would indicate anomalous deviations through ta-
[10] A. K. Sultania, D. Sylvester, and S. S. Sapat-
bles, indicating wrongful indexing by the software,
nekar. Gate Oxide Leakage and Delay Trade-
mishaps on the alter file creation or unexpected cell
offs for Dual-Tox Circuits. IEEE Transactions
behaviour.
on Very Large Scale Integration (VLSI) Sys-
Furthermore, the ability to display characteriza- tems, 13(12):1362–1375, December 2005.
tion data in other formats besides the Synopsys Lib-
erty would be an important addition. [11] Synopsis Inc. Hspice R User Guide: Basic
Simulation and Analysis, June 2017. Version
Acknowledgements M-2017.03-SP1.
I would like to thank Prof. Marcelino Bicho dos
Santos and the employees at SiliconGate for helping [12] Y. Yuan, C. Martin, and E. Oruklu. Stan-
me through this process. dard Cell Library Characterization for Fin-
FET Transistors using BSIM-CMG Models. In
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10