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•
Standard cell based layouts,✓
Combinational network delay,
Logic and interconnect design,
power optimization.

→ This
chapter focuses on the
design of combinational
logic Mlw's
standard cells ,
a
design technique

8tandardCdl-bayuH

layouts shadowed
→
Cmos are

→
pull up NIW 's and
pulldown nilws between the
and
into placement Which positions Components
> ,
touting
→
divide the
problem _

components
estimate
of
the
finalouting
→ we
generally perform placement using simple
in placement
→
primitives are
logicgates
→ Transistors are too small to be useful as a placement primitive .

Single Row
layout design
-

→ A one sow
layout
can be
designed as a one-dimensional
array of gates
of logic gates
has
→

changing
Ac
placement bolt
delay and area
effects
 Eino
UDD

p-type

V8
[yy)i% n -

type

Routing channel

sails
→
The tsansistoss are all between the
power formed by HDD and Uss

channel below the sails

→ The
major routing runs

→
The
gate ifp's and
ofp's are near the center
of# sow ,
so eternal wires

to the Channel
connect the
gates seating

is in the transistor for feed through to allow

→ sometimes ,
a
space left area a

a wire to be routed
through the middle
of the cell .

between the
→ we
usually avoid
salting wires
p-type and n-type
bean
stretching
apart
the
logic gates add
harmful parasites

logic gates in
the
→ Inba sow
wising
areas are
useful for ghost wires between

same sow

Inba
scouting ofbdrdyot
→ sow is a method
 NBD

IF
intsasow

wising area
+
-0

-11-1
/
§
Ey I
V55

The best
wayisw design
the
layout first ,
then look for interstitial space for short

wires

b a b
I
I 1
1 I 1

I 1

i : I
1 I
I
'
Horizontal track
✓
l

I
'
l

'
I

:
]
is
track
Vertical

The distance between tracks is equal to the minimum

spacing between a wise and
a via

horizontal and
→ wire
segments on Vertical tracks are on
separate layer
in horizontal
→

segregation ensures that vertical wires are

danger of shooting wires

only at Cohoes

→
The width
of the routing channel is determined by the placement of pins along
its bottom
top and
edges
→
The
major Variable is the
height of
the channel -
determined
by density _
man . no .

of horizontal

tracts
onaryilerticdat
 a b C
ce b C
'
\ r
l I
'

' ' '

\ l ,

i
/
- '
i

I
' '
- ' '
:
b C a
ee e
b

=3
density density =L

Density
can be used to determine the
wisability of a channel

Routingndgosiltms
→
Left edge
=
=
-

horizontal
→ uses
only One wire
segment pet net

B B <
A
/ ' ' I

1 ! ; ! tracks
" track
i.
'

; I
track 1
" :
a j ,

horizontal vertical added

placed wires can be
once wire
segments are
,

since
only
2 Hache are needed in this case,
height can be seduced drastically
A B

Problem → → This cannot be routed

in
left
using left edge
-

edge B a

→
Dogleg
=
wire

i
i
Dogleg scouting algorithms are much more
sophisticated

i
 Standard
-
cell
layout Design
→
large layouts
are
composed of several sows

→ standard cell
layout
is
composed of cells taken from a library
combinational
→ cells include logicgates multipliers ,ek
,
.

distance between
→ pitch =
2pA height
,

→ All cells in
library moot have same
pitch
→ Most
of
the cells area cannot be used for wiring
feed Paide
-
through shortcuts
through
which
delay -
csihcal wires can be

routed .

in standard
Transistors cells are
typically much
larger than those in custom

layouts
the cells designed
with
large
acceptable
are
To that ellen loosest case
delay
→ an
ensure ,

transistors

can be mixed
low
high height so
they
.

Bdt and motto same

→
power power cells
of the

ESE
EEEE•,
" ""

connection
through
area
pts .

←
9
transistors @

→
-☒ BEDDED
?⃝
 in
→ Interaction between area and
delay a multi - sow
layout is
complex .

'

Rats nest
plot
↳ show the
position @ each
component
and lines between
straight components ✗ wires

Combinationalntetwoskdday
The
delay
in a combinational network depends in poet on the number
ofgates the

signal mutgoltsough
.

others , the
longer paths will
→
If some
paths ,
are
significantly longer than

the maximum clock rate

determine
.

Fanout
=

Agate sons
slowly when →
Low cwk) in
pulleys
and
pull down
By inc .

size
of transistors
→
gate
can be sped up -

by increasing Transistor size

&

reducing capacitors attached

kit
Large fanouh How
operation
=

To seduce load capacitance

enlarged
in cases
wing buffers
of driving gate
severe
→ transistor can be ,

→
logic can be
redesigned
The above methods CD
may add
delay but seduces load
capacitance

Agate which dsiva more

fanouhgates Can
benefit from buffer insertion

→ Exam load capacitance can also come from He wires between

gate and
its
famous

gates
Palttdeay
from
is
different from /→ ◦
delay
◦→ i

Engender
the
,

critical path
Longest delay path -

time
critical path →
gives system cycle
→ tells what part of the
combinational logic mist be
charged
to improve performance

decreases
Agate on the
csihcdpaltis spedup → critical path
to
Pnc Tseansisws
.
size

cool

reducing
wise
capacitance
(087

redesigning
the
logic

fatsepats
cut short
nilw are
Some paths through
the
logic
in MAN
Dgak
for example
a

Boolean gates can create false paths ,

value is fixed the transition

ofttc
other if doesn't affect the
ofp
if one _

Path through the lower

i/p= False path
will not this
The NIW's combinational
delay be
affected by path

}
( btccdtes) leads to with higher fan in
flattening logic gates
→ a.

= abt acdt ace

delay caused maybe eaten up
by gates
Tsansisbrsizing
transistor circuit can be made to seen much
fester
By varying the
sizeofthe ,
a

in layout (
arbitrarily full custom
-

transistor willbe chosen

sizing

Interconnect design
Logic and

interconnect models
statistic
→ To
design using
in
→ Interconnect comes all
shapes and sizes

in the
↳ New Hoey number
of gates they connect

↳ Can be laid out in different topologies

as well

Assume
gate Elp's and
Mpls to be nodes in a
graph and He wires

them
connecting as
edges connect
gate
He uses wise
segments to directly
spam:@
→

Ttp's and olp's

Interconnection trees nodes that the wires
Steiner Tree
→ Adds to the
graph so

than
sakes
can join at a
Steiner point
at
gate ifp or ofp
meeting
a

structure is fixed
→
we
generally assume
that the
logic
can the
topology of
the wires connecting
the
gates
→ we change
the wires
→ we can
change the sizes
of
→
we can add buffers
transistors
→ we can size
Source

source Steiner point

sink ' § sinkl

sink 2 Sinks

&panning
= =
Tree
=
Delaymodellirg "" ""
& • # tor to determine
decay at each

gate YP
Timing analysis
→
phases
using a
path analyzes to calculate the critical
palt

Delay calculator shld

take into account } -

wiring delay • well as
driving and driven
gates

The Elmore model →

Computationally actable

section
→ wosbs
only for Rc

→
The circuit can be broken into a set
of Rc sections

and elmore model can be used

To evaluate the entire

wising tree → we need numerical techniques

Effectivecapacitanedel
-

0-1
TF
→ consider the interconnect as
single capacitance
a

→ allows to
separate the calculation
of gate and
interconnect
delay
→ Total
delay =
gate delay + interconnect delay
interconnect
Asymptotic waveform → Numerical technique to evaluate delay
evacuation

F- Model
=

→ used to model the Rc interconnect

◦
-1mm-1
-

Values are determined numerically

TT
→

T it model (at the 2nd

waveform at the
ofp of
-

→ The
7
ofp waveform
'

doesn't reflect the wires

to
capture
Capacitance)
→ This model
is
only used

the effect of wires load on

gate
 divides the total into shielded and
capacitance
'

F- model wires
→ The
Unshielded components

wise
-
sizing
→
Delay through
an re line Gente reduced by tapesirgik .

Source
Steiner
point

sink '

sinks

in a tsee, the
sizing problem is to
assign wise widths to each
segment in
the wire
,
wilt each
segment having constant wid Its

since most paths require saved turns 5 Most trees have ample opportunities for
tapering
→ wider wires near the source

and Narrower wires nor Ac sinks to minimize

delay

Buffer
= =
insertion
=

be able are much more complex

handle trees
In practise ,
we must to Rc
,
they
and subtrees exist
may

at
→
Buffers are placed within the tree to minimize departure time
req

8eg.at/tesinbs:-Goeuce--mihiGi-Di)Ti.-
the source that meets the
delay

arrival time at node A

source and sink ?

between
Di =
8cg
. -

delay
Elmore model
→ This algorithm by the
→ This
formula allows us to
recursively
calculate the
delay through Here nelw

MT
-

- - - - --
-
-

F
-
-
.

source .
.
.

"
T
MT
'

sink ?
-

runny
-

_ ,

E
.

nodeii T
- -
-
-
-

.
. _
→
_

my sink ?

I
csosstalkminimizahon
between wires can introduce Csoss talk btw .

edges
Coupling capacitance
to settle down
able
required for
crosstalk at best
increases
delay
elements
Atwood , causes
errors in
dynamic
ebb and
memory

minimize this Risk

we can
design Cbts . to

circuittechniqus
grand Corto VDD )
to whichever is stable
→ to introduce larger capacitance ,

introduce noise
stable if will not
→ Since GMD is at
voltage ,

capacitance
the capacitance to GHB relative to the
coupling
The
larger
→

t ,

add
'
C' to Genis is to interleave UH VDD
smaller the effect of
to
→ one
way wires
coupling
"H

Sigi
btw
sly wires
capacitance
YSS

sigz
Uss suited
→ Best for
Cbt that meet
distances
seen for longer
 will
cannot be provided minimizing coupling capacitance help to
→
If shielding ,

talk Example
→
Pg 242

reduce the
effects of cross

Twitching
correlation btw 2 wires
→ One technique to reduce the
backs so Har
a certain
length
wires
change
together for
,
→
After sunning
adjacent
to different wires
they are

doesn't
→ The total
coupling -
c on each wise
change
→ Howeveg that capacitance can no
longer go to a
single wise ,
but to several

different wires

a b a

b d b

C a c

d c d

Power
=
optimization
is to make it
power consumption
'

→ one
important way to seduce
agates

change
it
ofp as few times as
possible
to
design the
logic Mlw to reduce the number of unecessary
It is
possible
-

'

changes to a
gates ofp

to • < cm in multi-level
logic /
on W 's because
→ Glitches are more
likely
dogs arrive at diff . times to ihegate %'s
sources
-
of Glinting
consider the example of 2 .
Ckts .

of Adders ,

↑ atbtetd
a
atbtctd
+
" attste
d ^

I a
+
^

+ Atb
Ctd

Tatts
c
↑ + +
+
✗ b
a 4,
Tb C
a

Balanced tree
↳%hain

the balance tree whose

to
the
bog chain compared
The
:/ pie of diff dads . are
given to

Adder Thots are similar stg 's .

can be in # Balanced
High glittering
observed
Long chain to
compared wee

signal probabilities
-

in
Gelitching Cannot be eliminated all
→
cases

eliminated
signal probabilities glinting
the can be
→
By estimating ,

Ps = Prob .
that signal s = 1

Kat Ac Sigrid Hewes on clock are independent

Ppg,s a 2ps G- Pg) assuming

to be Zero or /
→ The sly
is
equally likely
 estimation tools
signal probabilities are
generally estimated by power
→
delay dependent
butfest
delay independent less
→
- -
accurate
to errors because it cannot
predict
→☐e6w-iÑpn dent power
estimation is subject

delay dependent filching

-

→
Glitch analysis can also be used to optimize placement and
Routing
their
Nodes that
suffer from high glikhig Should be laid out to minimize routing
capacitance
the
logic
block can be used to stop propagation
→
logic gates at the start
of the

disable signal
of logic sleds
based on a

Logicsynhesis
tedious
into Mlw of gates is

turning logic function

a
:
Logic design
a
→

time
and consuming
random
logic synthesis programs may be used to design logic
→
Logic optimization or

Asa minimization
Logic optimization
[
→

programs
have 2.
gods _
Delay satisfaction
'

minimize are
subject
to
meeting
the
designers specified
→
logic optimizers
Max .

delay
methods
→ These tools can
generate multi-level logic using a
variety of ,
 simplification : tabes advantage of don't Ceres
,
common factor extraction and

structure
collapsing ,
which eliminates the common factors by reducing
logic depth

finding good
common
factors
-

→ cube: product of literals

→ kernels seem of products expression
'

of 6- tools found in
'

a
factor for
a
function f must be made f

to factorize logic is to
generate potential common factors and test
→ one
way
K whether it divides f
each factor ,

Mlw
" "
have how the
→ once we
found a set
of f ,
we can evaluate
they will affect

in than
→A
factor that can be used more 1
place can help reduce
gate Area

factor inc delay and

power consumption
→ .