3/25/2020

FPGA Based System Design

DATA TYPES, SYSTEM TASKS

AND COMPILER DIRECTIVES

Wednesday, March 25, 2020

Data Types in Verilog (11)

 Parameters: Verilog allows constants to be defined in a module by the keyword
parameter. Parameters cannot be used as variables.
parameter port_id = 5; // Defines a constant port_id
parameter cache_line_width = 256; // Constant defines width of cache line
parameter signed [15:0] WIDTH; // Fixed sign and range for parameter
// WIDTH Module definitions may be written in terms of parameters.
 Hardcoded numbers should be avoided. Parameters values can be changed at
module instantiation or by using the defparam statement, Thus, the use of
parameters makes the module definition flexible.
Module behavior can be altered simply by changing the value of a parameter.
 In Verilog HDL localparam keyword is used to define parameters when their
values should not be changed.
 For example, the state encoding for a state machine can be defined using
localparam. The state encoding cannot be changed.
localparam state1 = 4'b0001, state2 = 4'b0010, state3 = 4'b0100, state4 = 4'b1000;

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Data Types in Verilog (12)

 Strings: Strings can be stored in reg. The width of the register variables must be
large enough to hold the string. Each character in the string takes up 8 bits.
 If the width of the register is greater than the size of the string, Verilog fills bits to
the left of the string with zeros.
 If the register width is smaller than the string width, Verilog truncates the leftmost
bits of the string
reg [8*18:1] string_value; // Declare a variable that is 18 bytes wide
initial string_value = "Hello Verilog World"; // String can be stored
 Special characters serve a special purpose in displaying strings, such as newline,
tabs, and displaying argument values. Special characters can be displayed in
strings only when they are preceded by escape characters
Escaped Character Escaped Character
Characters Displayed Characters Displayed
\n Newline \t Tab
%% % \\ \
\" '' \ooo 3 octal digits
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System Tasks (1)

 System Tasks: Verilog provides standard system tasks for certain routine
operations. All system tasks appear in the form $<keyword>. Operations such as
displaying on the screen, monitoring values of nets, stopping, and finishing are
done by system tasks.
 $display: is the main system task for displaying values of variables or strings or
expressions. Usage: $display(p1, p2, p3,....., pn); p1, p2, p3,..., pn can be quoted
strings or variables or expressions. $display is very similar to printf in C.
 A $display inserts a newline at the end of the string by default. A $display without
any arguments produces a newline.
Format Display
%d or %D Display variable in decimal
%b or %B Display variable in binary
%s or %S Display string
%h or %H Display variable in hex
%c or %C Display ASCII character
%m or %M Display hierarchical name (no argument required)
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System Tasks (2)

Format Display
%v or %V Display strength
%o or %O Display variable in octal
%t or %T Display in current time format
%e or %E Display real number in scientific format (e.g., 3e10)
%f or %F Display real number in decimal format (e.g., 2.13)
%g or %G Display real number in scientific or decimal, whichever is shorter
Example : $display Task
$display("Hello Verilog World");
-- Hello Verilog World
$display($time); // Display value of current simulation time 230
-- 230
// Display value of 41-bit virtual address 1fe0000001c at time 200
reg [0:40] v_addr; $display("At time %d virtual address is %h", $time, v_addr);
-- At time 200 virtual address is 1fe0000001c
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System Tasks (3)

// Display value of port_id 5 in binary
reg [4:0] port_id; $display("ID of the port is %b", port_id);
-- ID of the port is 00101
// Display value of 4-bit bus 10xx (signal contention) in binary
reg [3:0] bus; $display("Bus value is %b", bus);
-- Bus value is 10xx
// Display the hierarchical name of instance p1 instantiated under
// the highest-level module called top. No argument is required. This
// is a useful feature)
$display("This string is displayed from %m level of hierarchy");
-- This string is displayed from top.p1 level of hierarchy
// Display special characters, newline and %
$display ("This is a \n multiline string with a %% sign");
-- This is a
-- multiline string with a % sign
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System Tasks (4)

 $monitor: provides a mechanism to monitor a signal when its value changes.
Usage: $monitor(p1,p2,p3,....,pn); The parameters p1, p2, ... , pn can be variables,
signal names, or quoted strings. $monitor continuously monitors the values of the
variables or signals specified in the parameter list and displays all parameters in
the list whenever the value of any one variable or signal changes. Unlike
$display, $monitor needs to be invoked only once.
 Only one monitoring list can be active at a time. If there is more than one
$monitor statement in your simulation, the last $monitor statement will be the
active statement. Two tasks are used to switch monitoring on and off.
 Usage: $monitoron; $monitoroff; The $monitoron tasks enables monitoring,
and the $monitoroff task disables monitoring during a simulation. Monitoring is
turned on by default at the beginning of the simulation and can be controlled
during the simulation with the $monitoron and $monitoroff tasks.
// Monitor time and value of the signals clock and reset
// Clock toggles every 5 time units and reset goes down at 10 time units
initial begin $monitor ($time, " Value of signals clock = %b reset = %b",
clock, reset); end
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System Tasks (5)

 $stop: The $stop task is used whenever the designer wants to suspend the
simulation and examine the values of signals in the design.
 $finish: terminates the simulation.
// Stop at time 100 in the simulation and examine the results
// Finish the simulation at time 1000.
initial // initial block executes once at time = 0
begin
clock = 0;
reset = 1;
#100 $stop; // This will suspend the simulation at time = 100
#900 $finish; // This will terminate the simulation at time = 1000
end

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Compiler Directives (1)

 `define: directive is used to define text macros in Verilog. The Verilog compiler
substitutes the text of the macro wherever it encounters a `<macro_name>.
 Example
// define a text macro that defines default word size
'define WORD_SIZE 32 // Used as 'WORD_SIZE in the code
'define S $stop; // define an alias. A $stop will be substituted wherever 'S appears
// define a frequently used text string
'define WORD_REG reg [31:0]
// you can then define a 32-bit register as 'WORD_REG reg32;
 `include: allows you to include entire contents of a Verilog source file in another
Verilog file during compilation
// Include the file header.v, which contains declarations verilog file design.v.
'include header.v ... <Verilog code in file design.v> ...
... Two other directives, `ifdef and `timescale, are used frequently.

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