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MKF 585 DDR3 3L Us

The document discusses Kingston DDR3/3L DRAM for embedded applications, providing specifications for various part numbers including capacity, package size, configuration, voltage, speed and operating temperature range. It also lists key features of the DDR3/3L DRAM such as double data rate architecture, differential data strobe, differential clock inputs, on-die termination and more.

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43 views1 page

MKF 585 DDR3 3L Us

The document discusses Kingston DDR3/3L DRAM for embedded applications, providing specifications for various part numbers including capacity, package size, configuration, voltage, speed and operating temperature range. It also lists key features of the DDR3/3L DRAM such as double data rate architecture, differential data strobe, differential clock inputs, on-die termination and more.

Uploaded by

luci fer
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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KINGSTON.

COM

Kingston DDR3/3L DRAM


for embedded applications
Kingston DDR3/3L

Kingston on-board DRAM is designed to meet the needs of embedded applications and offers a
low-voltage option for lower power consumption.

DDR3/3L Part Numbers and Specifications


30nm DDR3/3L Package Configuration VDD, Operating
Capacity Description Speed
Part Number Size (words x bits) VDDQ Temperature
96 ball FBGA
1866
D1216ECMDXGJD 2Gb DDR3/3L 7.5x13.5x1.2 128Mx16 1.35V 0°C ~ +95°C
Mbps
I-Temp
78 ball FBGA
1866
D2568ECMDPGJD 2Gb DDR3/3L 7.5x13.5x1.2 256Mx8 1.35V 0°C ~ +95°C
Mbps
I-Temp
96 ball FBGA 1866
D2516ECMDXGJD 4Gb 7.5x13.5x1.2 256Mx16 1.35V* 0°C ~ +95°C
DDR3L Mbps
78 ball FBGA 1866
D5128ECMDPGJD 4Gb 7.5x10.6x1.2 512Mx8 1.35V* 0°C ~ +95°C
DDR3L Mbps
96 ball FBGA 2133
D2516ECMDXGME 4Gb 7.5x13.5x1.2 256Mx16 1.35V* 0°C ~ +95°C
DDR3L Mbps

*Backward compatible to 1.5V VDD, VDDQ

Key Features
• Double-data-rate architecture: two data transfers per clock cycle
• The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
• Bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for
capturing data at the receiver
• DOS is edge-aligned with data for READS; center-aligned with data for WRITES
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DOS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both
edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for better command and data bus efficiency
• On-Die Termination (ODD for better signal quality
— Synchronous ODT
— Dynamic CDT
— Asynchronous ODT
• Multi Purpose Register (MPR) for pre-defined pattern read out
• ZQ calibration for DO drive and ODT
• Programmable Partial Array Self-Refresh (PASR)
• RESET pin for Power-up sequence and reset function
• SRT range: Normal/extended
• Programmable Output driver impedance control

THIS DOCUMENT SUBJECT TO CHANGE WITHOUT NOTICE


©2020 Kingston Technology Corporation, 17600 Newhope Street, Fountain Valley, CA 92708 USA.
All rights reserved. All trademarks and registered trademarks are the property of their respective owners.  MKF-585.2US

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