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Embedded System Weeks 10

This chapter discusses general-purpose timers in microcontrollers. Timers can be used for input capture, output compare, pulse-width modulation (PWM) generation, and one-pulse mode output. They contain a free-running counter that is independent of the processor clock. The timer clock frequency can be divided by a prescaler value. In output compare mode, the timer output is determined by comparing the counter value to a compare register value. PWM mode generates a pulse train where the duty cycle is set by the compare register value. Timers support multiple channels and counting modes like up-counting, down-counting, and center-aligned.

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Abdulloh Asatullayev
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54 views

Embedded System Weeks 10

This chapter discusses general-purpose timers in microcontrollers. Timers can be used for input capture, output compare, pulse-width modulation (PWM) generation, and one-pulse mode output. They contain a free-running counter that is independent of the processor clock. The timer clock frequency can be divided by a prescaler value. In output compare mode, the timer output is determined by comparing the counter value to a compare register value. PWM mode generates a pulse train where the duty cycle is set by the compare register value. Timers support multiple channels and counting modes like up-counting, down-counting, and center-aligned.

Uploaded by

Abdulloh Asatullayev
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 38

Embedded Systems with ARM Cortex-M

Microcontrollers in Assembly Language and C

Chapter 15
General-purpose Timers

2
Timer
 Free-run counter (independent of processor)
 Functions
 Input capture
 Output compare
 Pulse-width modulation (PWM) generation
 One-pulse mode output

3
Timer: Clock

Reload Value ARR

Reload

fCL_PSC fCL_CNT
Timer
PSC ISR
Counter
clock Prescaler Interrupt

𝑓𝑓𝐶𝐶𝐶𝐶_𝑃𝑃𝑃𝑃𝑃𝑃
𝑓𝑓𝐶𝐶𝐶𝐶_𝐶𝐶𝐶𝐶𝐶𝐶 =
𝑃𝑃𝑃𝑃𝑃𝑃 + 1

4
Timer: Output

Reload Value ARR

Reload

fCL_PSC fCL_CNT
Timer
PSC ISR
Counter
clock Prescaler Interrupt

Timer Output
= (OCREF)

Compare &
Capture
Register (CCR)

5
Timer: Input Capture

Reload Value ARR

Reload

fCL_PSC fCL_CNT
Timer
PSC ISR
Counter
clock Prescaler Interrupt

Compare &
Capture
Register (CCR)

6
Multi-Channel Outputs

7
Output Compare

Output Compare Mode (OCM) Timer Output (OCREF)


000 Frozen
001 High if CNT == CCR
010 Low if CNT == CCR
011 Toggle if CNT == CCR
100 Forced low (always low)
101 Forced high (always high)
8
PWM Mode

Mode Counter < Reference Counter ≥ Reference


PWM mode 1
Active Inactive
(Low True)
PWM mode 2
Inactive Active
(High True)

9
Edge-aligned Mode (Up-counting)
ARR = 6, RCR = 0

clock
6 6 6 6
5 Counter
5 Counter
5 Counter
5
4 overflow 4 overflow 4 overflow 4
3 3 3 3
counter 2 2 2 2
1 1 1 1
0 0 0 0

Counter overflow
Update event (UEV)

Period = (1 + ARR) * Clock Period


= 7 * Clock Period

10
Edge-aligned Mode (down-counting)
ARR = 6, RCR = 0

Clock
6 6 6 6
5 5 5 5
4 4 4 4
3 3 3 3
Counter 2 Counter 2 Counter 2 Counter 2
1 underflow 1 underflow 1 underflow 1
0 0 0 0

Counter underflow
Update event (UEV)

Period = (1 + ARR) * Clock Period


= 7 * Clock Period

11
Center-aligned Mode
ARR = 6, RCR = 0

Clock
6 6
5 5 5 5
4 4 4 4
3 3 3 3
Counter 2 2 2 2
1 1 1 1
0 0 0
Counter Counter Counter Counter
overflow underflow overflow underflow

Update event (UEV)

Period = 2 * ARR * Clock Period


= 12 * Clock Period

12
Mode 1
PWM Mode 1 Timer Output =
High if counter < CCR
Low if counter ≥ CCR
(Low-True)
Upcounting mode, ARR = 6, CCR = 3, RCR = 0

Clock
6 6 6 6
5 5 5 5
4 4 4 4
CCR = 3 3 3 3 3
Counter 2 2 2 2
1 1 1 1
0 0 0 0

OCREF

CCR
Duty Cycle = Period = (1 + ARR) * Clock Period
ARR + 1
= 7 * Clock Period
3
=
7
13
Mode 2
PWM Mode 2 Timer Output =
Low if counter < CCR
High if counter ≥ CCR
(High-True)
Upcounting mode, ARR = 6, CCR = 3, RCR = 0

Clock
6 6 6 6
5 5 5 5
4 4 4 4
CCR = 3 3 3 3 3
Counter 2 2 2 2
1 1 1 1
0 0 0 0

OCREF

CCR
Duty Cycle = 1 - Period = (1 + ARR) * Clock Period
ARR + 1
= 7 * Clock Period
4
=
7
14
Mode 2
PWM Mode 2 Timer Output =
Low if counter < CCR
High if counter ≥ CCR
(High-True)
Upcounting mode, ARR = 6, CCR = 3, RCR = 0

Clock
6 6 6 6
CCR = 5 5 5 5 5
4 4 4 4
3 3 3 3
Counter 2 2 2 2
1 1 1 1
0 0 0 0

OCREF

CCR
Duty Cycle = 1 - Period = (1 + ARR) * Clock Period
ARR + 1
= 7 * Clock Period
2
=
7
15
Mode 2
PWM Mode 2 Timer Output =
Low if counter < CCR
High if counter ≥ CCR
(High-True)
Center-aligned mode, ARR = 6, CCR = 3, RCR = 0

Clock
6 6
5 5 5 5
4 4 4 4
CCR = 3 3 3 3 3
Counter 2 2 2 2
1 1 1 1
0 0 0

OCREF

CCR
Duty Cycle = 1 - Period = 2 * ARR * Clock Period
ARR
= 12 * Clock Period
1
=
2
16
Mode 2
PWM Mode 2 Timer Output =
Low if counter < CCR
High if counter ≥ CCR
(High-True)
Center-aligned mode, ARR = 6, CCR = 3, RCR = 0

Clock
6 6
5 5 5 5
4 4 4 4
3 3 3 3
Counter 2 2 2 2
1 1 1 1
CCR = 1 0 0 0

OCREF

CCR
Duty Cycle = 1 - Period = 2 * ARR * Clock Period
ARR
= 12 * Clock Period
5
=
6
17
Auto-Reload Register (ARR)

 Auto-Reload Preload Enable (ARPE) bit in TIMx_CR1

ARPE = 1 (Syn Update)


Write to ARR Preload Auto-reload
Read from ARR Register Register (ARR) If UDIS bit in TIMx_CR1 is 1,
UEV event is disabled.

Triggered by Update Event (UEV)

ARPE = 0 (Asyn Update)


Write to ARR Auto-reload
Read from ARR Register (ARR)

18
Repetition Counter Register (PCR)

19
Repetition Counter Register (PCR)

20
Repetition Counter Register (PCR)

21
Repetition Counter Register (PCR)

22
Repetition Counter Register (PCR)

23
PWM Output Polarity

Counter ≥
Mode Counter < CCR
CCR
PWM mode 1
Active Inactive
(Low True)
PWM mode 2
Inactive Active
(High True)

Output Polarity:
• Software can program the CCxP bit in the TIMx_CCER register

Active Inactive
Active High High Voltage Low Voltage
Active Low Low Voltage High Voltage

24
Counting up, down, center

25
Up-Counting: Left Edge-aligned
Upcounting mode, ARR = 6, CCR = 3, RCR = 0

Clock
6 6 6 6
CCR = 6 5 5 5 5
4 4 4 4
CCR = 3 3 3 3 3
Counter 2 2 2 2
1 1 1 1
0 0 0 0

CCR = 3

OC1REF

CCR = 6

OC2REF

Left-aligned
All rising edges occur at the same time! PWM Period

26
PWM Mode 2: Right Edge-aligned
Upcounting mode, ARR = 6, CCR = 3, RCR = 0

Clock
6 6 6 6
CCR = 5 5 5 5 5
4 4 4 4
CCR = 3 3 3 3 3
Counter 2 2 2 2
1 1 1 1
0 0 0 0

OC1REF CCR = 3

OC2REF CCR = 5

Right-aligned
All falling edges occur at the same time!
PWM Period

27
PWM Mode 2: Center Aligned Low if counter < CCR
Timer Output =
High if counter ≥ CCR

Center-aligned mode, ARR = 6, CCR = 3, RCR = 0

Clock
6 6
5 5 5 5
4 4 4 4
CCR = 3 3 3 3 3
Counter 2 2 2 2
1 1 1 1
CCR = 1 0 0 0

CCR = 3
OC1REF

CCR = 1
OC2REF

Center-aligned
PWM signals are center aligned!
PWM Period

28
The devil is in the detail

 Timer output control


 Enable Timer Output
 MOE: Main output enable
 OSSI: Off-state selection for
Idle mode
 OSSR: Off-state selection for
Run mode
 CCxE: Enable of
capture/compare output for
channel x
 CCxNE: Enable of
capture/compare
complementary output for
channel x

29
Input Capture
 Monitor both rising and falling edge

30
Input Capture
 Monitor only rising edges or only falling edge

31
Input Capture

32
Input Filtering

33
Input Capture Diagram

34
Ultrasonic Distance Sensor

𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇 𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇 × 𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 𝑜𝑜𝑜𝑜 𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆


𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 =
2

𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇 𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇 µ𝑠𝑠 ×10−6 ×340𝑚𝑚/𝑠𝑠


=
2

𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅 𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇 𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇 µ𝑠𝑠


=
58

35
Ultrasonic Distance Sensor
The echo pulse width corresponds to
round-trip time.

𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃 𝑊𝑊𝑊𝑊𝑊𝑊𝑊𝑊𝑊 (𝜇𝜇𝜇𝜇)


𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 (𝑐𝑐𝑐𝑐) =
58
or

𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃 𝑊𝑊𝑊𝑊𝑊𝑊𝑊𝑊𝑊 (𝜇𝜇𝜇𝜇)


𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 (𝑖𝑖𝑖𝑖𝑖𝑖𝑖) =
148

If pulse width is 38ms,


no obstacle is detected.

36
Ultrasonic Distance Sensor

37
THANK
YOU

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