Lab No 3 (DLD)
Lab No 3 (DLD)
Lab Reports
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Reg. ID Section
211260 A
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MT-256L Digital Logic Design
Lab No. 3
Verification of DE Morgan’s Law and Implementation of Boolean
Function through logic gates
Objectives: -
• Implementation of Boolean arithmetic.
• Using logic gate ICs verifying DE Morgan’s law.
• Developing a new approach for using logic IC’s.
Equipment: -
• Trainer.
• Connecting wires.
• Power Supply.
• 14 Pin ICs (AND, OR, NOT).
Introduction: -
This lab is about utilizing logic gates IC’s for performing Boolean arithmetic and giving us
about a broad way of how we can use IC’s (AND, OR, NOT) for verifying different laws like DE
Morgan’s. Now, for Boolean algebra it’s the basic form algebra which deals with the binary
variables and logic operations. Binary uses only two values 1 or 0.
De Morgan’s Law: It can be expressed in Boolean logic as: NOT (a AND b) = NOT a OR
NOT b; NOT (a OR b) = NOT a AND NOT b.
(x+y)’ = x’. y’
(x.y)’ = x’+y’
Complement of AND of two gates is equal to the OR of both gate’s negation or complement of OR
of two gates is equal to the AND of both gate’s negation.
Procedure: -
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MT-256L Digital Logic Design
• Then we implement the respective circuit on proteus software. Here are the figures.
Here are the truth tables, which shows the comparison of the left and right hand side of the
DeMorgan’s Law
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MT-256L Digital Logic Design
Practical procedure: -
We implement the gates making circuits according to the equation or functions. First we
make tables for observations then giving them input according to the table we note down the
outcome. Following is a figure from our practical.
Schematic Procedure: -
Step 1: Select all the components from the list which you want to use.
Step 2: Click on the component and place them on the schematic in orderly manner. Step
3: Make the connection according to the circuit diagram you are provided with.
Step 4: Make sure you have made all connections right.
Step 5: Give the source DC and place ground.
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MT-256L Digital Logic Design
showing us there are three inputs x, y and z. Function uses one OR, NOT and AND gate.
Here is the truth table of the following function.
(x+y)’:
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MT-256L Digital Logic Design
x’. y’:
0 1 1 0 1 1 1
1 0 0 1 0 0 0
1 0 0 0 1 1 0
0 1 1 1 0 0 0
(x.y)’ :
x’+y’ :
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MT-256L Digital Logic Design
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MT-256L Digital Logic Design
We have used logic gates for verifying a mathematical equation transformed into Boolean
function, this opens a new door way in our knowledge to look at same old mathematical equations
and functions from a new perspective. We also learned: