c8 SAMSUNO ·

Linear Ie k (VOL. 2)
Data Boo

1988
• Telecom
• Industrial
• Data Converter
Copyright 1987 by Samsung Semiconductor
All rights reserved. No part of this publication may be reproduced, stored in a retrieval
system, or transmitted in any form or by any means, electronic, mechanical, photo
copying, recording, or otherwise, without the prior written permission of Samsung
Semiconductor.
The information contained herein is subject to change without notice. Samsung
assumes no responsibility for the use of any circuitry other than circuitry embodied in
a Samsung product.
No other circuit patent licenses are implied.
SAMSUNG SEMICONDUCTOR
DATA BOOK LIST
I. Semiconductor Product Guide
II. Transistor Data Book
III. Linear IC Data Book
IV. MOS Product Data Book
V. High Performance CMOS Logic Data Book
. VI. MOS Memory Data Book
VII. SFET Data Book
LINEAR Ie DATA BOOK

VOLUME 1.
AUDIO ICs
VIDEO ICs

VOLUME 2.
TELECOM ICs
VOLTAGE REGURATORs
VOLTAGE REFERENCEs
OPERATIONAL AMPLIFIERs
COMPARATORs
TIMERs
. DATA CONVERTER ICs
MISCELLANEOUS ICs
 TABLE OF CONTENTS
(VOLUME 2)

I. QUALITY AND RELIABILITY ........................................................ 19

II. PRODUCT GUIDE ............................................................................... 49

1. Function Guide ....................................................................................... 51
2. Cross Reference Guide ........................................................................... 60 .
3. Ordering Information ...........•.................................................................. 66

III. TELECOMMUNICATION ICs, ......................................................... 67

IV. INDUSTRIAL ICs ............................................................................... 275

1. Voltage Regulators ............................................................................... 277
2. Voltage References .............................................................................. 393
3. Operational Amplifiers.•......................................................................... 407
4. Comparators ............... :........................................... :.............................. 468
5. Timers ......................... :.......................................................................... 496

V. DATA CONVERTER ICs .................. ~ ............................................ 519

VI. MISCELLANEOUS ICs ..........................................................:........ 593

VII. PACKAGE DIMENSIONS ............................................................. 617

VIII. SALES OFFICES and MANUFACTURER'S'

REPRESENTATIVES ;....................................................................... 629
 (VOLUME 1) .

I. QUALITY AND RELIABILITY

II. PRODUCT GUIDE

1. Function Guide
2. Cross Reference Guide
3. Ordering Infonnation .

III. AUDIO ICs

IV. VIDEO ICs

V. MISCELLANEOUS ICs

VI. PACKAGE DIMENSIONS

VII. SALES OFFICES and MANUFACTURER'S

REPRESENTATIVES
ALPHANUMERIC INDEX
Device Function Package Page

KA33V Silicon Monolithic Bipolar Integrated Circuit Voltage TO-92 595

Stabilizer for Electronic Tuner
KA201A Single Operational Amplifier 8 DIP/8 SOP 407
KA301A Single Operational Amplifier 8 DIP/8 SOP 407
KA319 Dual High Speed Voltage Comparator 14 DIP/14 SOP 468
KA336-5_0 Voltage Reference Diode TO-92 393
KA350 3 AMP Adjustable Positive Voltage Regulator TO-3P 277
KA361 High Speed Voltage Comparator 14 DIP/14 SOP 472
KA385-1.2 Micropower Voltage Reference Diode TO-92 397
KA431 Programmable Precision Reference TO-9218 DIP/8 SOP 401
KA710C High Speed Voltage Comparator 14 DIP/14 SOP 474
KA733C Differential Video Amplifier 14 DIP/14 SOP 412
KA1222 Dual Low Noise Equalizer AMP 8 SIP Vol.1 .
KA2101 TV Sound IF AMP 14 DIP Vol. 1
KA2102A TV Sound System 14 DIP HIS Vol. 1
KA2103L Sound Mute System for TV 8 SIP Vol. 1
KA21 04 Auto Power off and Sound Mute System for TV 9 SIP Vol. 1
KA2105 Limiter AMP and Detector for a TV SIF 9 SIP Vol. 1
KA2106 Dual Sound Multiplex for a TV SIF 16 DIP Vol. 1
KA21 07 DC Volume, Tone Control Circuit 12 SIP Vol. 1
KA2130A TV Vertical Deflection System 10 SIP HIS Vol. 1
KA2131 TV Vertical Output Circuit 10 SIP HIS Vol. 1
KA2133 1 Chip Deflection System 16 DIP HIS Vol. 1
KA2134 Color TV Deflection Signal Processing IC 18 DIP Vol. 1
KA2135 Horizontal Signal Processing IC 12 SIP Vol. 1
KA2136 Low Noise TV Vertical Deflection System 12 ZDIP/F Vol. 1
KA2137 TV Horizontal Processor 16 DIP Vol. 1
KA2153 Video-Chroma Deflection System for a Color TV 42 DIP Vol. 1
KA2154 Video-Chroma Deflection System for a Color TV 42 DIP Vol. 1
KA2181 Remote Control Pre-AMP 8 SIP Vol. 1
KA2182 Remote Control Pre-AMP 8 SIP Vol. 1
KA2183 Remote Control Pre-AMP 8 SIP Vol. 1
KA2201B 0.5W Audio Power AMP 8 DIP Vol. 1
KA2201/N 1.2W Audio Power AMP 8 DIP Vol. 1
KA2206 2.3W Dual Audio Power AMP 12DIP/F Vol. 1
KA22062 4.5W Dual Power AMP 12 SIP HIS Vol. 1
KA2209 Dual Low Voltage Power AMP 8 DIP Vol. 1
KA2210 5.5W Dual Power AMP 12 SIP HIS Vol. 1
KA2211 5.8W Dual Power AMP 12 SIP HIS Vol. 1
KA2212 0.5W Audio Power AMP 9 SIP Vol. 1
KA2213 One Chip Tape Recorder System 14 DIP HIS Vol. 1
KA22131 Dual Pre-Power AMP for Auto Reverse 24 SOP Vol. 1
KA22135 Dual Pre-Power AMP and DC Motor Speed Controller 22 SDIP Vol. 1
KA2214 1W Dual Power AMP 14 DIP HIS Vol. 1
KA2220 Equalizer AMP with ALC 9 SIP Vol. 1
KA2221 Dual Low Noise Equalizer AMP 8 SIP Vol. 1
KA22211 Dual Low Noise Equalizer AMP 8 SIP Vol. 1
KA2223 5 Band Graphic Equalizer AMP 16 DIP Vol. 1
KA22233 3 Band Dual Graphic Equalizer AMP 22 DIP Vol. 1
KA22235 5 Band Graphic Equalizer AMP 18 ZIP Vol. 1
KA2224 Dual Equalizer AMP with ALC 14 DIP Vol. 1
ALPHANUMERIC INDEX (Continued)

Device Function Package Page

KA22241 Dual Equalizer AMP with ALC 9 SIP Vol. 1

KA22251D Dual Pre-AMP for 3V Using 16· DIP/16 SOP Vol. 1
KA22261 Dual Equalizer AMP with REC AMP 16 DIP Vol. 1
KA2230 9-Program Music Selector 22 DIP Vol. 1
KA22421/D AM 1 Chip Radio 16 DIP/16 SOP Vol. 1
KA22424 AM/FM 1 Chip Radio 16 DIP Vol. 1
KA2243 AM/FM I F System 16 DIP Vol. 1
KA2244 FM IF System for Car Radio 9 SIP Vol. 1
KA22441 FM IF System for Car Stereo 16 ZIP Vol. 1
KA2245 FM IF System for Car Radio, ' 7 SIP Vol. 1
KA22461 Electronic ,Tuning AM Radio Receiver for Car Stereo 19 ZIP Vol. 1
'KA2247 FM IF/AM Tuner System 16 DIP Vol. 1
KA22471 FM IF/AM Tuner System 16 DIP' Vol. 1
KA2248A/D 3V FM IF/AM Tuner System 16 DIP/16 SOP Vol. 1
KA2249/D FM Front End for Portable Radio 7 SIP/8 SOP Vol. 1
KA2261 FM Stereo Multiplex Decoder 16 DIP Vol. 1
, KA2262 FM Stereo Multiplex Decoder for Car Stereo 16 ZIP Vol. 1
KA2263 FM Stereo Multiplex Decoder 9 SIP Vol. 1
KA2264/D FM Stereo Multiplex Decoder 9 SIP/16 SOP Vol. 1
KA2265 VCO Non-Adjusting FM Stereo Multiplex Decoder 16 DIP Vol. 1
, KA22682 1 Chip TV MPX Demodulator 28 DIP Vol. 1
KA2268N 1 Chip TV Sound MPX 28 DIP Vol. 1
KA2281 5 DOT Dual LED Level Meter Driver 16DIP Vol. 1
KA2283 5 DOT Dual LED Level Meter Driver 16 DIP Vol. 1
KA2284 5 DOT LED Level Meter Driver 9 SIP Vol. 1
KA2285 5 DOT LED Level Meter Driver 9SIP Vol. 1
KA2286 5 DOT LED Linear Level Meter Driver 9 SIP Vol. 1
KA2287 5 DOT LED Linear Levei Meter Driver 9 SIP Vol. 1
KA2288 7 DOT LED Level Meter Driver 16 DIP Vol. 1
KA2303 Toy Radio COntrol Actuator 9 SIP Vol. 1
KA23Q4 Toy Radio Control Actuator 9 SIP Vol. 1
KA2401 DC Motor Speed Controller 8 DIP - Vol. 1
KA2402 Low Voltage DC Motor Speed Controller 8 DIP Vol. 1
KA2404 DC Motor Speed Controller TO-92L Vol. 1
KA2407 DC Motor Speed Controller ' TO-126 Vol: 1
KA241 0 Tone Ringer 8 DIP 69
KA2411 . Tone Ringer 8 DIP 69
KA2412A Telephone Speech Circuits 14 DIP 75
KA2413 Dual Tone Multi Frequency Generator 16 DIP 83
KA2418 Tone Ringer with Bridge Diode 8 DIP 108
KA2419 Tone Ringer with Bridge Diode 8 DIP 108
KA2425A/B Telephone Speech Network with Dialer Inteiiace 18 DIP 122
KA2580A 8-Channel Source Drivers 18 DIP 599
KA2588A 8-Channel Source Drivers 20 DIP 599
KA2605 SYNC Separator 9 SIP Vol. 1
KA2606 SYNC Separator 9 SIP Vol. 1
KA2615 LED and Lamp Driver 9 SIP, Vol. 1
KA2616 LED and Lamp Driver 9 SIP Vol. 1
ALPHANUMERIC INDEX (Continued)

Device Function Package Page

KA2617 LED and Lamp Driver 9 SIP Vol. 1

KA2618 LED and Lamp Driver 9 SIP Vol. 1
KA2651 Fluorescent Display Drivers 18 DIP 604
KA2803 Low Power Consumption Earth Leakage ,Detector 8 DIP 607
KA2804 Zero Voltage Switch 8 DIP 610
KA2911 Video IF System for Color TV 16 DIP Vol. 1
KA2912 Video IF Processor for BIW TV 14 DIP HIS Vol. 1
KA2913A Video and Sound IF AMP for Monochrome TV Receivers 16 DIP Vol. 1
KA2914A Video IF +'SIF System 24 DIP Vol. 1
KA2915 TV VIF & SIF & Deflection System 28 DIP Vol. 1
KA2916 Video IF System for Color TV 16 DIP Vol. 1
KA2917 Video and Sound IF AMP for Monochrome TV Receivers 16 DIP Vol. 1
KA2918 Video IF + SIF System 24 DIP Vol. 1
KA2919 VIF + SIF System for Color TV 30 SSD Vol. 1
KA2944 Write & Read AMP 28 DIP Vol. 1
KA2945 Video AMP 28 DIP Vol. 1
KA2983 Switch less Recording/Play Back AMP 18 DIP Vol. 1
KA2988 Chroma Signal Processor 28 DIP Vol. 1
KA6101 Analog Interface Circuit for Teletex 'System 18'DIP Vol. 1
KA6102 Analog Interface Circuit for'Teletex System 18 DIP ,Vol. 1
KA3524 Regulator Pulse Width Modulator 16 DIP 285
KA78540 Switching Regulator 16 DIP 306
KA78TXX 3A Positive Voltage Regulator TO·220 312
KA8301 Driver for VTR 10 SIP HIS Vol. 1
KA8302 Servo Control AMP 12 SIP Vol. 1
KA8401 VTR Audio Switchless Recording/Play Back AMP 24 ZIP Vol. 1
KA9256 Dual Power Operational Amplifier ' 10 SIP HIS 419
KAD0808 8 Bit I'p·Compatible AID Converter with 8·Channel
28 DIP 549
Multiplexer
KAD0809 8 Bit I'p·Compatible AID Converter. with 8·Channel
28 DIP 549
Multiplexer
KAD0820A/B 8 Bit High Speed I'P Compatible AID Converter with
20 DIP 560
Track/Hold Function
KDA0800 8 Bit D/A Converter 16 DIP 580
KDA0801 8 Bit D/A Converter 16 DIP 580
KDA0802 8 Bit D/A Converter 16 DIP 580
KF351 Single Operating Amplifier 8 DIP/8 SOP 421
KS555 CMOl3 Timer 8 DIP/8 SOP 496
KS555H CMOS Timer 8 DIP/8 SOP 501
KS556' CMOS Timer 14 DIP/14 SOP 505
KS5803A1B Remote Control Transmitter ' 16 DIP/20 SOP Vol. 1
KS5805A1B Telephone Pulse Dialer with Redial 18'DIP 130
KS5808 Dual Tone Multi Frequency Dialer 16 DIP 146
KS5812 Quad Universial Asychronous Receiver and Transmitter 40 DIP 152 ;

KS5819 Tone/Pulse Dialer with Redial 22 DIP/SDIP 162

KS5820 Tone/Pulse Dialer with Redial 18 DIP 172
KS5821 Tone/Pulse Dialer with Redial 22DIP/SDIP 162
KS5824 Universial Asychronous Receiver and Transmitter 24 DIP 180
KS7126 3 1/2 Digit AID Conve,rter 40 DIP 568
KS25C02 8 Bit CMOS Successive Approximation Register 16 DIP/24 SDIP 586
ALPHANUMERIC INDEX (Continued)

Device Function Package Page

KS25C03 8 Bit CMOS Successive Approximation Register 16 DIP/24SDIP 586

KS25C04 12 Bit CMOS Successive Approximation Register 24DIP/24SDIP 586
KSV3100A H,igh-Speed AlD-DA Converter 40 DIP 521
. KSV3110 High-Speed AlD-DA Converter 40 DIP 531
KSV3208 High-Speed AID Converter 28 DIP 541
KT3040J PCM Monolithic Filter 16 CERDIP 191
KT3054J COMBO CODEC 16 CERDIP 200
KT3064J COMBO CODEC 20 CERDIP 214
KT5116J wLaw Companding CODEC 16 CERDIP 226
LM211 Voltage Comparator 8 DIP/8 SOP 476
LM224/A Quad Operational AmplHier 14 DIP/14 SOP 423
LM239/A Quad Differential Comparator 14 DIP/14 SOP 481
LM248 Quad Operational Amplifier 14 DIP/14 SOP 432
LM2581~ Dual Operational Amplifier 8 DIP/8 SOP/9 SIP 438
LM293/A Dual Differential Comparator 8 DIP/8 SOP 489
LM311 Voltage Comparator 8 DIP/8 SOP 476
LM317 3-Terminal Positive Adjustable Regulator TO-220 291
LM323 3-Terminal Positive Voltage Regulator TO-3P 296
LM324/A Quad Operational Amplifier 14 DIP/14 SOP 423
LM339/A Quad Differential Comparator 14 DIP/14 SOP 481
LM348· Quad Operational Amplifier 14 DIP/14 SOP 432
LM3581A/S Dual Operational Amplifier 8 DIP/8, SOP/9 SIP 438
LM3861S/D Low Voltage Audio Power AMP 9 SIP/8 DIP/8 SOP 613
LM393/A1S Dual Differential Comparator 8 DIP/8 SOP 489
LM567C Tone Decoder 8 DIP/S SOP 239
LM567L Micropower Tone Decoder 8 DIPj8 SOP 247
LM723 Precision Voltage Regulator 14 DIP/14 SOP 300
LM741C/ElI Single qperationai Amplifier, 8 DIP/8 SOP 446
LM2901 Quad Differential Comparator 14 DIP/14 SOP 481
LM2902 Quad Operational Amplifier 14 DIP/14 SOP 423
LM2903 Dual Differential Comparator 8 DIP/8 SOP. 489
LM2904 Dual Operational Amplifier 8 DIP/8 SOP/9 SIP 438
LM3302 Quad Differential Comparator 14 DIP/14 SOP 481
MC14581C/SII Dual Operational Amplifier 8 DIP/8 SOP/9 SIP 452
MC1488 Quad Line Driver 14 DIPI14 SOP 257
MC1489/A Quad Line Receiver 14 DIP/14 SOP 264
MC3303 Quad Operational Amplifier 14 DIPI14 SOP 456
MC3361 Low Power Narrow Band FMIF 16 DIP/16 SOP 270
MC3403 Quad Operational Amplifier 14 DIP/14 SOP 456
MC45581C/A/SII Dual Operational Amplifier 8 DIP/8 SOP/9 SIP 463
MC78XX 3-Terminal 1A Positive Voltage Regulator TO-220 323
MC78LXX 3-Terminal Positive Voltage Regulator TO-92 353
MC78MXX 3-Terminal 0.5A Positive Voltage Regulator TO-220 364
MC79XX 3-Terminal Negative Voltage Regulator TO-220 377
MC79MXX 3-Terminal 0.5A Negative'Voltage Regulator TO-220 387
NE555 Timer 8 DIP/8 SOP 509
NE556 Dual Timer 14 DIP/14 SOP 513
NE558 Quad Timer 16 DIP/16 SOP 516
PRODUCT INDEX
1. Audio Application

Device . Function Package Page

KA1222 Dual Low Noise Equalizer AMP 8 SIP Vol. 1

KA2201B O.5W Audio Power AMP 8 DIP Vol. 1
KA2201lN 1.2W Audio Power AMP 8 DIP Vol. 1
KA2206 2.3W Dual Audio Power AMP 12DIP/F Vol. 1
KA22062 4.5W Dual Power AMP 12 SIP HIS Vol. 1
·KA2209 Dual Low Voltage Power AMP 8 DIP Vol. 1
KA221 0 5.5W Dual Power AMP 12 SIP HIS Vol. 1
KA2211 5.8W Dual Power AMP 12 SIP HIS Vol. 1
KA2212 O.5W Audio Power AMP 9 SIP Vol. 1
KA2213 One Chip Tape Recorder System 14 DIP HIS Vol. 1
KA22131 Dual Pre·Power AMP for Auto Reverse 24 SOP Vol. 1
KA22135 Dual Pre·Power AMP and DC Motor Speed Controller 22 SDIP Vol. 1
KA2214 1W Dual Power AMP .14 DIP HIS Vol. 1
KA2220 Equalizer AMP with ALC 9 SIP Vol. 1
KA2221 Dual Low Noise Equalizer AMP 8 SIP Vol. 1
KA22211 Dual Low Noise Equalizer AMP 8 SIP Vol. 1
KA2223 5 Band Graphic Equalizer AMP 16 DIP Vol. 1
KA22233 3 Band Dual Graphic Equalizer AMP 22 DIP Vol. 1
KA22235 5 Band Graphic Equalizer AMP 18 ZIP Vol. 1
KA2224 Dual Equalizer AMP with ALC 14 DIP Vol. 1
KA22241 Dual Equalizer AMP with ALC 9 SIP Vol. 1
KA2225/D Dual Pre·AMP for 3V Using 16 DIP/16 SOP Vol. 1
KA22261 Dual Equalizer AMP with REC AMP 16 DIP Vol. 1
KA2230 9-Program Music Selector 22 DIP Vol. 1
KA22421/D AM 1 Chip Radio 16 DIP/16 SOP Vol. 1
KA22424 AM/FM 1 Chip Radio 16 DIP Vol. 1
KA2243 AM/FM IF System 16 DIP Vol. 1
KA2244 FM IF System for Car Radio 9SIP Vol. 1
KA22441 FM IF System for Car Stereo 16 ZIP Vol. 1
KA2245 FM IF System for Car Radio .7 SIP Vol. 1
KA22461 Electronic Tuning AM Radio Receiver for Car Stereo 19 ZIP Vol. 1
KA2247 FM IF/AM Tuner System 16 DIP Vol. 1
KA22471 FM IF/AM Tuner System 16 DIP Vol. 1
KA2248A1D 3V FM IF/AM Tuner System 16 DIP/16 SOP Vol. 1
KA2249/D FM Front End for Portable Radio 7 SIP/8 SOP Vol. 1
KA2261 FM Stereo Multiplex Decoder 16 DIP Vol. 1
KA2262 FM Stereo Multiplex Decoder for Car Stereo 16 ZIP Vol. 1
KA2263 FM Stereo Multiplex Decoder 9 SIP Vol. 1
KA2264/D FM Stereo Multiplex Decoder 9 SIP/16 SOP Vol. 1
KA2265 VCO Non-Adjusting FM Stereo Multiplex Decoder 16 DIP Vol. 1
. KA2281 5 DOT Dual LED Level Meter Driver 16 DIP Vol. 1
KA2283 5 DOT Dual LED Level Meter Driver 16 DIP Vol. 1
KA2284 .5 DOT LED Level Meter Driver 9 SIP Vol. 1
KA2285 5 DOT LED Level Meter Driver 9 SIP Vol. 1
KA2286 5 DOT LED Linear Level Meter Driver 9 SIP Vol. 1
KA2287 5 DOT LED Linear Level Meter Driver 9SIP Vol. 1
KA2288 7 DOT LED Level Meter Driver 16 DIP Vol. 1
LM386/S/D Low Voltage Audio Power AMP 9 SIP/8 DIP/8 SOP 613
KA2303 Toy Radio Control Actuator 9 SIP Vol. 1
KA2304 Toy Radio Control Actuator 9 SIP Vol. 1
KA2401 DC Motor Speed Controller 8 DIP Vol. 1
PRODUCT INDEX (Continued)
1. Audio Appllcatlori (Continued)

Device Function Package Page

KA2402 Low Voltage DC Motor Speed Controller 8 DIP Vol. 1

KA2404 DC Motor Speed Controller TO-92L Vol. 1
KA2407 DC Motor Speed Controller TO-126 Vol. 1

2. Video Application
Device Function Package Page

KA2101 TV Sound IF AMP 14 DIP Vol. 1

KA2102A TV Sound System 14 DIP HIS Vol. 1
KA2103L Sound Mute System for TV 8 SIP VOl:, 1
KA21 04 Auto Power off and Sound Mute System for TV 9 SIP Vol. 1
KA2105 limiter AMP and Detector for a TV SIF 9 SIP Vol. 1
KA2106 Dual Sound Multiplex for a TV SIF 16 DIP Vol. 1
KA2107 DC Volume, Tone Control Circuit 12 SIP Vol. 1
KA2130A TV Vertical Deflection System 10 SIP HIS Vol. 1
KA2131 TV Vertical Output Circuit 10 SIP HIS Vol. 1
KA2133 1 Chip Deflection System 16 DIP HIS Vol. 1
KA2134 Color TV Deflection Signal Processing IC 18 DIP Vol. 1
KA2135 Horizontal Signal Processing IC 12 SIP Vol. 1
KA2136 Low Noise TV Vertical Deflection System 12 ZDIP/F Vol. 1
KA2137 TV HOrizontal Processor 16 DIP Vol. 1
KA2153 Video-Chroma Deflection System for a Color TV 42 DIP Vol. 1
KA2154 Video-Chroma Deflection System for a Color TV 42 DIP Vol. 1
KA2181 Remote Control Pre-AMP 8 SIP Vol. 1
KA2182 Remote Control Pre-AMP 8SIP Vol. 1
KA2183 j'\emote Control Pre-AMP 8 SIP Vol. 1
KA22682 1 Chip TV MPX Demodulator 28 DIP Vol. 1
KA2268N 1 Chip TV Sound MPX 28 DIP Vol. 1
KA2605 SYNC Separator 9 SIP Vol. 1
KA2606 SYNC Separator 9SIP Vol. 1
KA2615 LED and Lamp Driver 9 SIP Vol. 1
KA2616 LED and Lamp Driver 9 SIP Vol.,l
KA2617 LED and Lamp Driver 9SIP Vol. 1
KA2618 LED and Lamp Driver 9 SIP Vol. 1
KA2911 Video IF System for Color TV 16 DIP Vol. 1
KA2912 Video I F Processor for BIW TV 14 DIP HIS Vol. 1
KA2913A Video and Sound IF AMP for Monochrome TV Receivers 16 DIP Vol. 1
KA29l4A Video IF + SIF System 24 DIP Vol. 1
KA2915 TV VIF & SIF & Deflection System 28 DIP Vol. 1
KA2916 Video IF System for Color TV 16 DIP Vol. 1
KA2917 Video and Sound IF AMP for Monochrome TV Receivers 16 DIP Vol. 1
KA2918 Video IF+SIF System 24 DIP Vol. 1
KA2919 VIF + SIF System for Color TV 30 SSD Vol. 1
KA2944 Write & Read AMP 28 DIP Vol. 1
KA2945 Video AMP 28 DIP Vol. 1
KA2983 Swltchless Recording/Play Back AMP 18 DIP Vol. 1
KA2988 Chroma Signal Processor 28 DIP Vol. 1
KA6101, Analog Interface Circuit for Teletex System 18 DIP Vol. 1
KA6102 Analog Interface Circuit for Teletex System 18 DIP Vol. 1
KA8301 Driver for VTR 10 SIP HIS Vol. 1
KA8302 Servo Control AMP 12 SIP Vol. 1
KA8401 VTR Audio Swltchless Recordlng/Play Back AMP 24 ZIP Vol. 1
KS5803A/B Remote Control Transmitter 16 DIP/20 SOP Vol. 1
PRODUCT INDEX (Continued)
3. Telecommunication Application

Device Function. Package Page

KA241 0 Tone· Ringer 8 DIP 69

KA2411 Tone Ringer 8 DIP 69
KA2412A Telephone Speech Circuits 14 DIP 75
KA2413 Dual Tone Multi Frequency Generator 16 DIP 83
KA2418 Tone Ringer with Bridge Diode 8 DIP 108
KA2419 Tone ·Rlnger with Bridge Diode .- 8 DIP 108
KA2425A/B Telephone Speech Network with Dialer Interface 18 DIP 112
KS5805A/B Telephone Pulse Dialer with Redial 18 DIP 130
KS5808 Dual Tone Multi Frequency Dialer 16 DIP 146
KS5812 Quad Universial Asychronous Receiver and Transmitter 40 DIP 152
KS5819 Tone/Pulse Dialer with Redial 22 DIP/SDIP 162
KS5820 Tone/Pulse Dialer with Redial 18 DIP 172
KS5821 Tone/Pulse Dialer with Redial 22DIP/SDIP 162
KS5824 Universlal Asychronous Receiver and Transmitter 24 DIP 180
KT3040J PCM Monolithic Filter 16 CERDIP 19'
KT3054J COMBO CODEC 16 CERDIP 200 .
KT3064J COMBO CODEC 20 CERDIP 214
KT5116J ,.-Law Companding CODEC 16 CERDIP 226
LM567C Tone Decoder 8 DIP/8 SOP 239
LM567L Mlcropower Tone Decoder 8 DIP/8 SOP 247
MC1488 Quad Line Driver 14 DIP/14 SOP 257
MC1489/A Quad Line Receiver 14 DIP/14 SOP 264
MC3361 Low Power Narrow Band FM IF 16 DIP/16 SOP 270
KA2580A 8-Channel Source Drivers 18 DIP 599
KA2588A 8-Channel Source Drivers 20 DIP 599
KA2651 Fluorescent Display Drivers 18 DIP 604

4. Industrial Application

Device Function Package Page

KA201A Single Operational Amplifier 8 DIP/8 SOP 407

KA301A Single Operational Amplifier 8 DIP/8 SOP 407
KA319 Dual High Speed Voltage Comparator 14 DIP/14 SOP 463
KA336-5.0 Voltage Reference Diode TO·92 393
KA350 3 AMP Adjustable Positive Voltage Regulator TO·3P 277
KA361 High Speed Voltage Comparator 14 DIP/14 SOP 472
KA385-1.2 Micropower Voltage Reference· Diode TO·92 397
KA431 Programmable Precision Reference TO·9218 DIP/S SOP 401
KA710C High Speed Voltage Comparator 14 DIP/14 SOP 474
KA733C Differential Video Amplifier 14 DIP/14 SOP 412
KA3524 Regulator Pulse Width Modulator 16 DIP 285
KA9256 Dual Polt'l(er Operational Amplifier 10 SIP H/S 419
KF351· Single Operating Amplifier 8DIP/8·S0P 421
KS555 CMOS Timer 8 DIP/8 SOP 496
KS555H CMOS Timer 8 DIP/S SOP 501
KS556 CMOS Timer 14 DIP/14 SOP 505
LM211 Voltage Comparator 8 DIP/8 SOP 476
PRODUCT INDEX (Continued)
Industrial Application (Continued)

Device Function Package Page

LM224/A Quad Operational Amplifier 14 DIP/14 SOP 423

LM239/A Quad Differential Comparator 14 DIP/14 SOP 481
LM248 Quad Operational Amplifier 14 DIP/14 SOP 432
LM258/A JDual Operational Amplifier 8 DIP/8 SOP/9 SIP 438
LM293/A Dual Differential Comparator ·8 DIP/8 SOP 489
LM311 Voltage Comparator 8 DIP/8 SOP 476
LM317 3-Terminal Positive Adjustable Regulator TO-220 291
LM323 3-Terminal Positive Voltage Regulator TO-3P 296
LM324/A Quad Operational Amplifier 14 DIP/14 SOP 423
LM339/A . Quad Differential Comparator 14 DIP/14 SOP 481
LM348 Quad Operational Amplifier 14 DIP/14 SOP 432
LM3581A/S Dual Operational Amplifier 8 DIP/8 SOP/9 SIP 438
LM3931A1S Dual Differential Comparator 8 DIP/8 SOP 489
LM723 Precision Voltage Regulator 14 DIP/14 SOP 300
LM741C/ElI Single Operational Amplifier 8 DIP/8 SOP 446
LM2901 Quad Differential Comparator 14 DIP/14 SOP 481
LM2902 Quad Operational Amplifier 14 DIP/14 SOP 423
LM2903 Dual Differential Comparator 8 DIP/8 SOP 489
LM2904 iDual Operational Amplifier 8 DIP/8 SOP/9 SIR 438
LM3302 Quad Differential Comparator 14 DIP/14 SOP' . 481
MC14581C/SII Dual Operational Amplifier 8 DIP/8 SOP/9 SIP 452
MC3303 Quad Operational Amplifier 14 DIP/14 SOP 456
MC3403 Quad Operational Amplifier 14 DIP/14 SOP ·456
MC45581CIAISIl Dual Operational Amplifier 8 DIP/8 SOP/9 SIP 463
MC78XX 3-Terminal 1A Positive Voltage Regulator TO-220 323
MC78LXX 3-Terminal Positive Voltage Rllgulator TO-92 353
MC78MXX 3-Terminal 0.5A Positive Voltage Regulator TO-220 364
MC79XX 3-Terminal Negative Voltage Regulator TO-220 377
MC79MXX 3-Terminal 0.5A Negative Voltage Regulator TO-220 387
KA78540 Switching Regulator 16 DIP 306
KA78TXX 3A Positive Voltage Regulator TO-220 312
NE555 Timer 8 DIP/8 SOP 509
NE556 Dual Timer 14 DIP/14 SOP 513
NE558 Quad Timer 16 DIP/16 SOP 516
KA2803 Low Power Consumption Earth Leakage Detector 8 DIP 607
KA2804 Zero Voltage Switch 8 DIP 610
KA33V Silicon Monolithic Bipolar Integrated Circuit Voltage TO-92 295
Stabilizer for Electronic Tuner

5. Data Converter Application

Device Function Package Page

KSV3100A High-Speed A/D-DA Converter 40 DIP 521

KSV3110 High-Speed AlD-DA Converter 40 DIP 531
KSV3208 High-Speed AID Converter 28 DIP 541
KAD0808 8 Bit I-'p-Compatible AID Converter with 8-Channel 28 DIP 549
Multiplexer
KAD0809 8 Bit I-'p-Compatible AID Converter with 8-Channel 28 DIP 549
Multiplexer
KAD0820A/B 8,Bit High Speed I-'P Compatible AID Converter with
20 DIP 560
Track/Hold Function
KDA0800 8 Bit D/A Converter 16 DIP 580
KDA0801 8 Bit D/A Converter 16 DIP 580
KDA0802 8 Bit D/A Converter 16 DIP 580
KS25C02 8 Bit CMOS Successive Approximation Register 16 DIP 586
KS25C03 8 Bit CMOS Successive Approximation Register 16 DIP 586
KS25C04 12 Bit CMOS Successive Approximation Register 24SDIP 586
KS7126 3 1/2 Digit AID Converter 40 OIP 568
•
.

QUALITY & RELIABILITY 1

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QUALITY and RELIABILITY

INTRODUCTION
Samsung's linear IG products are among the most reliable in the industry. Samsung has always made a commit·

I
ment to achieve the highest possible quality, reliability, and customer satisfaction with its products.
Extensive qualification, monitor and outgoing programs are used to scrutinize product quality and reliability.
·Stringent controls are applied to every wafer fabrication and assembly lot to achieve reproducibility, and therefore
maintain product reliability.
In this chapter, the quality and reliability programs established at Samsung will be discussed. In addition, a description
of reliability theory, reliability tests and various support efforts provides a broad framework from which to compre·
hend Samsung quality and reliability. .
To better understand the Quality Department's role in product develoment and manufacturing, Ii detailed diagram
is listed below. As can be noted, Quality Engineering is involved in all phases, save that of initial product planning.

STEP PRODUCTION
SALES PROCESS ENG'S OC/OA PRODUCTION CONTROL

~ 1 MARKET SURVEY 1
z
~
"-
I SPEC. REVIEW I
1 COUNCIL FOR 'DEVELOPMENT 1

Cl
II.
I DESIGN 1
:II!
~ I DESIGN REVIEW
I
.....a:
z
1

1
QUALIFICATION FOR RAW MATERIAL
1

m
Q
l TRIAL MFG
I
I' EVALUATION & QUALIFICATION
1
z
~
STANDARDIZATION
1 1
~
~
"-
APPROVAL ·II-----------------------l P.P
J
III
a: QUALIFICATION
"- 1 1

1 INCOMING INSP.

z I PROCESS CONTROL MASS PRODUCTION I

S
u
:>
CI
0
I~=P=R=O=C~==S=M=O=N=IT=OR==~~
a: RELIABILITY TEST
"- 1
:g
c·
:II!
I LOT ACCEPTANCE TEST

I FAILURE ANALYSIS 1 SHIPPING 1

Iii
1 CLAIM INITIATE CORRECTIVE ACTION I CUSTOMER 1
":II!a:
C

Figure 1. Quality Assurance During Develop~ent

c8 SAMSUNG SEMICONDUCTOR 21
QUALITY and RELIABILITY

QUALITY AND RELIABILITY PROGRAM

Since Samsung manufactures many different products using a variety of fab and assembly technologies, close
attention must be paid to avariety of (potential) reliability hazards. The Samsung quality and reliability department
has established a variety of procedures and programs to assess, understand, control, and eliminate reliability
problems.
The major categories of reliability program management are: '
a. Qualification program
b. Monitor program
c. Outgoing quality program

QUALIFICATION PROGRAM
Samsung' qualification procedures are used mainly to confirm the major characteristics and reliability attributes
of new technologies or products for introduction to Samsung manufacturing. The program is also utilited to
evaluate changes to existing technologies or raw materials. The purpose of this program is to simulate all relevant
user conditions, via accelerated and standard methods, prior to product shipment. The stresses used for qualifica-
tion are detailed in following sections.

MONITOR PROGRAM
Twice per year, devices duplicate their qualification tests to obtain long-term reliability data for Linear ICs.
In this way historical data is collected and analyzed over all part types and thus assures the customer of ongoing
device quality.
These results are summarized in reliability reports issued periodically by Samsung Semiconductor.

OUTGOING QUALITY PROGRAM

All wafer lots are required to pass a "QC-reliability-gate" prior to product shipment. The purpose is to track "Lot·
by-lot" quality and reliability to catch any potential product anomaly at the factory site.
The customer can then expect only quality material to be delivered, from Samsung. Any lot that fails the procedure
l,isted below is scrutinized heavily, to make sure that corrective action takes place immediately.
By paying such close attention to every lot, product costs are kept at a minimum. Samsung's customer return rate
is extremely low, which is where our tough outgoing policy is most powerful. Such a tight clamp to protect our
customers is how we can assure that all Samsung's products are released with the highest confidence level possible.

HOPL 168HR
PCT 48HR

REJECT

(Corrective Action Required)

WAREHOUSE INCOMING INSPECTION

Figure 2. Linear Ie Outgoing Flow

c8 SAMSUNG SEMICONDUcroR 22
 QUALITY and RELIABILITY

RELIABILITY TESTS
Samsung has established a comprehensive reliability program to monitor and ensure the ongoing reliability of the
linear IC family. This program involves not only reliability data collection and analysis on existing parts, but also
rigorous in-line quality controls for all products.
Listed below are details of tests performed to ensure that manufactured product continues to meet Samsung's
stringent quality standards. In line quality controls are reviewed extensively in later sections.
The tests run by the quality department are accelerated tests, serving to model "real world" applications through
boosted temperature, voltage, and/or humidities. Accelerated conditions are used to derive device knowledge through
means quicker than that of typical application situtations. These accelerated conditions are then used to assess
I
differing failure rate mechanisms that correlate directly with ambient conditions. Following are summaries of various
stresses (and their conditions) run by Samsung on linear IC products.
HIGH TEMPERATURE OPERATING LIFE TEST (HOPL)
(TJ=125°C, Vee = Vee max, static)
High temperature operating life test is performed·to measure actual field reliability. Life tests of l000HR to 2000HR
durations are used to accelerate failure mechanisms by operating the device at an elevated ambient temperature
(125°C). Data obtained from this test are used to predict product infant mortality, early life, and random failure
rates. Data are translated to standard operating temperatures via failure analysis to determine the activation
energy of each of the observed failures, using the Arrhenius relationship as previously discussed.
WET HIGH TEMPERATURE OPERATING LIFE TEST (WHOPL)
(Ta=85°C, R.H.=81%, Vee = Vee opt, statiC)
Wet high temperature operating life test is performed to evaluate the moisture resistanr.e characteristics of plastiC
encapsulated componenots. Long time testing is performed under static bias conditions at 85°C/81 percent relative
humidity with nominal voltages. To maximize metal corroSion, the biasing configuration utilizes low power levels.
INTERMITTENT OPERATING LIFE (IOPL)
(Pmax, 25°C, 2min on/2 min off)
This test is normally applied to scrutinize die bond thermal fatigue. A stressed device undergoes an "ON" cycle,
where there is thermal heating due to power dissipation, and an "OFF" cycle, where there is thermal cooling due
to lack of inputted power. Die attach (between die and package) and bond attach (between wire and die) are the
critical areas of concern.
HIGH TEMPERATURE STORAGE TEST (HTS)
(Ta = 125°C, UNBIASED)
High temperature storage is a test in which devices are subjected to elevated temperatures with no applied bias.
The test is used to detect mechanical instabilities such as bond integrity, and process wearout mechanisms.

PRESSURE COOKER TEST (PCT)

(121°C, 15PSIG, 100% R.H., UNBIASED)
The pressure cooker test checks for resistance to moisture penetration. A highly pressurized vessel is used to
force water (thereby promoting corrosion) into packaged devices located within the vessel.

TEMPERATURE CYCLING (TIC)

(-65°C to + 150°C, AIR, UNBIASED)
This stess uses a chamber with alternating temperatures of - 65°C and + 150°C (air ambient) to thermally cycle
devices within it. No bias is applied. The cycling checks for mechanical integrity of the packaged device, in
particular bond wires and die attach, along with metallpolysilicon microcracks.

THERMAL SHOCK (TIS)

(-65°C to + 150°C, LIQUID, UNBIASED)
This stress uses a chamber with alternting temperatures of - 65°C to + 150°C (liquid ambient) to thermally cycle
devices within it. No bias is applied. The cycling is very rapid, and primarily checks for die/package compatibility.

c8 SAMSUNG SEMICONDUCTOR 23
. QUALITY and RELIABILITY

RELIABILITY TEST RESULTS·

This section is divided into two parts-actual and predicted test results. Actual test results are those derived via
accelerated stressing done by the ac
department. Predicted results are calculated by taking actual test results
and derating them using statistical and mathematical models to determine device performance in "real-time" user
conditions.

ACTUAL TEST RESULTS

(KA2102A)
% Failures per
Number of Number of Device Number of
Stress Conditions l000HRS (Cycles)
Devices Hours/Cycles Failures
(60% UCL)
Tj = 125°C
HOPL 100 100,000 0 0.91%/1K HR
. Vcc = Vee max
85° C/81 % R.H.
WHOPL 100 100,000 0 0.91%I1K HR
Vcc = Vee opt
Ta=25°C
·IOPL 100 100,000 0 0.91%/1K HR
Vee = Vee max
Ta= 125°C
HTS 100 100,000 0 0.91%/1K HR
Unbiased.
121°C
PCT 100 16,800 0 5.4 %/1K HR
15 PSIG
-65°C to 150°C
TIC 100 10,000 0 9.1 %/1K CL
Air to Air
:... 65°C to 150°C
TIS 100 10,000 0 9.1 %/1K CL
Liquid to Liquid

PREDICTED .TEST RESULTS

The Arrhenius equation, which is reviewed in another seotion of this chapter, can be applied to derive typical "user-
conditio(l" device failure rates.
STESS: HOPL
100,000 Device Hours at 125°C
Average Activation Energy: 1.(> eV.
De-Rating to User Conditions Yields:
70°C Operation 55°C Operation

% Failures Per % Failures Per

Equivalent ""MTBF. Equivalent ""MTBF
1000 Hours "FITs 1000 Hours "FITs
Device Hours (Years) Device Hours (Years)
(60% UCL) (600% UCL)·
10.7 x 1()6 0.0084 84 1359 50.4 x 106 0.0018 18 6342

• FIT: Failure in time or failure unit. Represents

the number of failures expected for 109 (one
billion) device hours.
•• MTBF: Mean time between failures.

c8 SAMSUNG SEMICONDUCTOR 24
QUALITY and RELIABILITY

RELIABILITY AND PREDICTION THEORY

RELIABILITY
Reliability can be loosely characterized as long term product quality.
There are two types of reliability tests: those performed during design and development, and those carried out
in production. The first type is usually performed on a limited sample, but for long periods or under very accelerated
conditions to investigate wearout mechanisms and determine tolerances and limits in the design process. The
second type of tests is performed periodically during production to check, maintain, and improve the assured quality
and reliability levels. All reliability tests performed' by Samsung are under conditions more severe than those
encountered in the field, and although accelerated, are chosen to simulate stresses that devices will be subjected
to in actual operation. Care is taken to ensure that the failure modes and mechanisms are unchanged.

FUNDAMENTALS
'A semiconductor device is very dependent on its conditions of use (e.g., junction temperature, ambient tempera-
ture, voltage, current, etc.). Therefore, to predict failure rates, accelerated reliability testing is generally used. In
accelerated testing, special stress conditions are considered as parametrically related to actual failure modes.
Actual operating life time is predicted using this method. Through accelerated stresses, component failure rates
are ascertained in terms of how many devices (in percent) are expected to fail for every 10pD hours of operation.
A typical failure rate versus time of activity graph is shown below (the so-called "bath tub curve")

(t)

Reduction due to
Failure ...._......l. . ._ _ _ _ _-,:-_ _ _ _....",,_-,-_ _ preventive maintenance
rate m 1 =
S " .. ' Specified
emlcond- - - - -
oct Failure Rate
(m:::: o.5_o%feVlces

Initial Random Failure period Wear-Out Failure period

Failure period
Figure 3_ Failure Rate Curve ("Bath Tub Curve")
During their initial time period, products are affected by "infant mortality," intrinsic to all semiconductor technologies.
End users are ,very sensitive to this parameter, which causes early assembly/operation .failures in their own
system. Perl~dically, Samsung reviews and publishes life time resultll. The goal is a steady shift of the limits as
shown below.

=~;:m \1'": ---,Ir-/::,.-t-----/

J /::,.: failure rate

I I

I I
!---t --TIME

Figure 4. Failure Rate

c8 SAMSUNG SEMICONPUCTOR 25
QUALITY and RELIABILITY

ACCELERATED HUMIDITY TESTS

To evaluate the reliability of products assembled in plastic packages, Samsung performs accelerated humidity
stressing, such as the Pressure Cooker, Test (PCT) and Wet High Temperature Operating Life Test (WHOPL).
Figure 5 shows some results obtained with these tests, which illustrate the improvements in recent years. These
'improvements result mainly from the intro.Quction of purer molding reSins, new process methods, and improved
cleanliness.

10- 5
--

~ VI
I

-.10- 6 R-

·I~
~ 5
,,'":1 ~
~~'
5
~10- 7 ~
ff.~
~
'"
[@ t;0
f;j
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fi:
5 'I. 'ff. rl
R: r,;,0"
ILj
"R:~
."
-lt'J ""
W

10- 8
~'S.
5
rl .,
~

10- • 25 40 60 ao 100 125 150 1ao 1200 Til C)

Figure 5. Improvement In Humidity Reliability

ACCELERATED TEMPERATURE TESTS

Accelerated temperature tests are carried out at temperatures ranging from 75°C to 200°C for up to 2000 hours.
These tests allow Samsung to evaluate reliability rapidly and economically, as failure rates are strongly dependent
on temperature.
The validity of these tests is demonstrated by the good correlation betw~n data collected in the field and laboratory
results obtained using the Arrhenius model. Figure 6 shows the relationship between failure rates and temperatures
obtained with this model.

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99.9
,99

90

1982

1985
~ 1988

L L
If V.....-: iI'

0,1
10 10' HOURS

Figure 6. Failure Rate Versus Temperature

c8 SAMSUNG SEMICONDUCTOR 26
QUALITY and RELIABILITY

FUNDAMENTAL THEORY FOR ACCELERATED TESTING

Accelerated life testing is powerful because of its strong relation to failure physics. The Arrhenius model, which
is generally used for failure modelling, is explained below.

1. Arrhenius model
This model can be applied to accelerated Operating Life Tests and uses absolute (Kelvin) temperatures.
L = A + EalK·Tj
I
L : Lifetime
A : Constant
Ea : Activation Energy
K : Boltzman's constant
Tj : Absolute Junction temperature
If Lifetimes L1 and L2 correspond to Temperatures T1 and T2:
Ea 1 1
L1 = L2 exp K (1'1 - T2 )

Lifetime(L)

Temperature 11T (OK-1)

Actual junction temperature should always be used, and can be computed using the following relationship.
Tj=Ta+(Px Bja)
Where Tj = Junction temperature
Ta = Ambient temperature
, P = Actual power consumption
Bja=Junction to Ambient thermal resistance (typica"y 100 degrees celsius/watt for a 16-Pin PDIP).
2. Activation Energy Estimate

Clearly the choice of an appropriate activation energy, Ea, is of paramount importance. The different mechanisms
which could lead to circuit failure are characterized by specific activation energies whose values are published
in the literature, The Arrhenius equation describes the rate of many processes. responsible for the degradation
and failure of electronic components. It follows that the transition of an item from an initially stable condition to
a defined degraded state occurs by a thermally activated mechanism. The time for this transition is given by an
equation of the form:
MTBF = B EXP (EalKT)
MTBF = Mean time between failures
B = Temperature-independent constant
MTBF can be defined as the time to suffer a device degradation. The dramatic effect of the choice of the Ea va!ue
can be seen by plotting the MTBF equation. The acceleration effect for a 125°C device junction stress with respect
to 70°C actual device junction operation is equal to 1000 for Ea=1eV and 7 for Ea=0.3eV.

c8 SAMSUNG SEMICONDUCTOR 27
. QUALITY and RELIABIUTY

Some words of caution are needed about published values of Ea:

A. They are often related to high-temp tests where a single Ea (with high value) mechanism has become dominant.
B. They are specifically related to the devices produced by that supplier (and to Its technology) fo~ a given period
of time ..
C. They could be modified by the mutual action of other stresses (voltage, mechanical, etc.)
D. Field device-application conditlon(s) should be considered.

(Activation energy for each failure mode)

THE CORRECT PROCEDURE
Failure Mechanism Ea
Contamination
Polarization
1-1.4 eV
1 eV
. ACCELERATED TEST I
Aluminum Migration 0.5 -1 eV CALCULATED AT TEST CONDITIONS
Trapping 1 eV AND WITH A CERiAiN CONFIDENCE
Oxide Breakdown 0.3 eV LEVEL
Silicon Defects 0.3-0.5 eV
FAILURE ANALYSIS

I
CHOICE OF Ea---CALCULATED AT OTHER
TEMPERATURES

Time

1.4 e"r -leV

1()6

0.8e~
1()6 / /
l;
./ ./
~c 104
0 .O.5~
~ 1()3 J V 0.4 eY:lii!!
~
""
-< 0.3eV-
/ ./ ./ ",
102

.... ~

II
10' '/ ./

l()1l
. 250 200 175 150125. 100 75 50 T("C)
Junction 1;emperature
Figure 7. Life Hours

c8 SAMSUNG SEMICONDUCTOR 28
QUALITY and RELIABILITY

Failure Rate Prediction

AccEllerated testing defines the failure rate of products. By derating the data at different conditions, the life
expectancy at actual operating conditions can be predicted. In its simplest form the failure rate (at a given temperatlJre)
is:

Where FR
N
FR=1)H

=Failure Rate
I
N =Number of failures
o = Number of components
H = Number of testing hours
If we intend to determine the FR at different temperatures, an acceleration factor must be considered. Some failure
modes are accelerated via temperature stressing based upon the accelerations of the Arrhenius Law.
For two different temperatures:
Ea 1 1
FR (T1) = FR (T2) exp If ( T2 - T1 )

FR (T1) is a point estimate, but to evaluate this data for an interval estimate, we generally use a X2 (chi square)
distribution. An example follows: .

Failure Rate Elaluation

Unit: %/1000HR

Dev. x Hours
Fail Failure Rate at 60% Confidence Level
at 125°C

1.7x1OS 2
Point Estimate I 85·C I 70·C I 55·C
0.18 I 0.0068 I 0.0018 I 0.00036

The activation energy, from analYSis, was chosen as 1.0 eV based upon test results. The failure rate at the lower
operating temperature can be extrapolated by an Arrhenius plot. .

c8 SAMSUNG SEMICONDUCTOR 29
QUALITY and RELIABILITY

PROCESS CONTROL
GENERAL PROCESS CONTROL
. ' , .
The general process flow in Samsung is shown in Figure 8. This illustration contains the standard process flow
from incoming parts and materials to customer shipment.

Acceptance inspection (according to acceptance inspection plan)

Process quality control

• Check of each condition by process quality control procedures
• Process insPection
• Lot control
• Equipment calibration and maintenance

100% Electrical Die Sorting

Process Quality Control and screening of infant mortality defects

• Mechanical screen
• Thermal shock
• Burn·in

100% package sorting of electrical characteristics and marking

Reliability monitoring
1. PRT (Process Reliability Testing)
2. DRT (Device Reliability Testing)

• High Temperature Operating Life Test

• Environmental test
• Life Test

Finished Goods Sampling Inspection

Incoming • Dimensions
Inspection • Visual
• Electrical characteristics
• Periodic calibration of measuring equipment

Stock control
• Age control

Sampling Inspection (when applicable)

Shipment

Figure 8. General Process Flow CharI

c8 SAMSUNG SEMICONDUCTOR 30
QUALITY and RELIABILITY

WAFER FABRICATION
Process Controls
The Quality Control program utilizes the following methods of control to achieve its previously stated objectives:
process audits, environmental monitors, process monitors, lot acceptance inspections, and process integrity audits.
Definitions
The essential method of the Quality Control Program is 'defined as follows:
1. Process Audit-Performed on all operations critical to product quality and reliability.
I
2_ Environmental Monitor-Monitors concerning the process environment, i.e., water purity, temperature, humidity,
particle counts.
3. Process Monitor-Periodic inspection at designated process steps' for verification of manufacturing inspection
and maintenance of process average. These inspections provide both attribute and variable data.
4. Lot Acceptance-Lot-by-Iot sampling. This sampling method is reserved for those operations deemed as critical,
and require special attention.
Environmental Monitor

Process Control Item Spec_ Limit Insp_ Frequency

Clean Room • Temperature • Individual Spec. 24 Hrs.

• Humidity • Individual Spec. 24 Hrs.
• Particle • Individual Spec. 24 Hrs .
• Air Velocity • Individual Spec. 24 Hrs.
0.1. Water • Particle • 5 ea/50ml (0.81') 24 Hrs.
• Bacteria • 50 colonies/100m I (0.451') Weekly
• Resistivity • Main (Line): More than 24 Hrs.
16 Mohm-cm
• Using pOint: More than 24 Hrs.
14 Mohm-cm
• Instruments
• FMS (Facility Monitoring System) HIAc/ROYCO
• CPM (Central Particle Monitoring System-Dan Scientific)
• Liquid Dust Counter Etch Rate
• Filtration System for Bacterial check
• Air Particle counter
• Air Velocity meter
Process Monitor

Process Control Item Spec_ Limit Insp_ Frequency

Photo • Aligner N2 Flow Rate • Individual Spec. Once/Shift

• Aligner Vacuum • Individual Spec. Once/Shift
• Aligner Air • Individual Spec. Once/Shift
• Aligner Pressure • Individual Spec . Once/Shift
• Aligner Intensity • Individual Spec. Once/Shift
• Coater Soft Bake • Individual Spec. Once/Shift
Temperature • Individual Spec. Once/Shift
Vacuum • Individual Spec. Once/Shift
Etch • Etchant Temp. • Individual Spec. Once/Shift
• Etch Rate • Individual Spec. Once/Shift
• Spin Dry~r N2 Flow • Individual Spec. Once/Shift
RPM • Individual Spec. Once/Shift
• Hard Bake Temp .. • Individual Spec. Once/Shift
N2 Flow • Individual Spec. Once/Shift

c8 SAMSUNG SEMICONDUCTOR 31
QUALITY and RELIABILITY

Process Monitor (Continued)

Process Control Item Spec. Limit Insp. Frequency

Thin Film • Cooling Water Temp. ·26±3°C Once/Shift

• .Thickness ., Individual Spec. Once/Shift
CVD • Pin Hole • Individual Spec. Once/Shift
• Thickness • Individual Spec. Once/Shift
Diffusion • Tube Temp. • Individual Spec. Once/Shift
• C·V Plot Run • Individual Spec. Once/Shift
Tube • Individual Spec. Oncel1Odays
• Sheet Resistance • Individual Spec. Once/Shift
• Thickness • Individual Spec. Once/Shift

Raw Material Incoming Inspection

1. Mask Inspection
, Defect Detection • Pinhole & Clear-extension All Masks • Defect Size::s;1.5,.m
• Opaque Projections & • Defect Density
SpOtS .' ::s;O.124EA1cm 2
• Scratch/Particle/Stain
• Substrate Crack/Glass·chip
• Others
Registration • Run·out ±O.75,.m
(X-Y Coordinate) 20%
• Orthogonality ±O.75,.m
• Drop-in Accuracy '. All New Masks ±O.50,.m'
• Die Fit/Rotation ±O.50,.m
Critical
Dimension • Critical Dimension AI,I Masks Purchasing Spec.
• Instrument
• Auto mask Inspection system for defect-detection (NJS 5MD-44)
• Comparator for registration (MVG 7X7)
• Automatic IInewidth measuring system for CD (MPV-CD)

2. Wafer Inspection

Purpose Insp. Items Sample Remarlts

Structural • Crystal'lographic; Defect All Lots • Sirtl Etch

Electrical • Resistivity All Lots • Monitor Water
• Conductivity
Dimensional • Thickness All Lots TTV, NTV, Epi-thickness
• Diameter
• Orientation
• Flatness TIR (FPD)
Local Slope
Visual • Surface Quality All Lots Purchasing Spec.
• Cleanliness
• Instrument,
• 4 point probe for resistivity (Kokusai VR40A, Tencor sonogage, ASM 4FPP)
• Flatness measuring system (Siltec)
• Epi. layer thickness gauge (Digilab FTG-12, Qualimatic S-1OO)
• Automatic Surface Insp. System (Aeronca Wis-150)
• Non-contact thickness gauge (ADE6034) ,

c8 SAMSUNG SEMICONDUCTOR 32
QUALITY and RELIABILITY

In·Process Quality Inspection (FAB)

1. Manufacturing Section

Process Step Process Control Insp. Frequency

Oxidation Oxide Thickness All Lots

Diffusion Oxide Thickness All Lots
Sheet Resistance All Lots
Visual All Lots
Photo Critical Dimension All Lots (MaS)
Visual All Lots
Mask Clean Inspection All Masks with Spot Light (MaS)
or Microscope (BIP)
Etch Critical Dimension All Lots
Visual All Wafers
Thin Film Metal Thickness All Lots
Visual All Lots
Ion Implant Sheet Resistance All Lots (Test Wafer)
Low Temp. Thickness All Lots
Oxide Visual All Lots
E·Test Electrical ~haracteristics All Lots
Fab. Out Visual All Wafers

2. FAB, QC Monitor/Gate

Process Step FAB, QC Insp. Frequency

Oxidation Oxide Thickness Once/Shift

C·V Test on Tubes Once/10 Days and After CLN
Visual Once/Shift
Diffusion Oxide Thickness Once/Shift
C·V Test on Tubes Once/10 Days and After CLN
Visual Once/Shift
Photo Critical Dimension All Lots (MaS)
Visual Once/Shift
Mask CLN Inspection All Masks After 10 Times Use
Etch Critical Dimension All Lots (MaS)
Visual All Lots
Thin Film C·V Test on Tubes Once/10 Days and After CLN
on Lots Once/Shift
Reflectivity Once/Shift
Low Temp. Refractive Index, 1 Test Wafer/Lot
Oxide Wt% of Phosphorus 1 Test Wafer/Lot
Visual 1 Test Wafer/Lot
E·Test Measuring Data All Lots
Calibration Instrument for Thickness Once/week
and C.D. Measuring

c8.SAMSUNG SEMICONDUCTOR 33
.QUALITY and RELIABILITY

3. Photo/Etch process quality control

Process Flow Process Step MFG. Control Item ac Monitor/Gate

Prebake Oven PM, Temperature Oven Particle Temp.
Time N2 Flow Rate
Photo Resist {PRJ Thickness Machine PM
-spin
Soft Bake Oven PM, Temperature Temp. N2 Flow Rate
Time
Align/Expose Light Uniformity Ught Intensity
Alignment, Focus Test Mask Clean Insp.
Mask Clean Inspection
Mask Clean Exposure
Light Intensity
Develop . Equipment PM Vacuum
Solution Control
. Develop PRIC.D.'S Alignment
Check Particles
Mask and Resist Defects

QC Inspection Critical Dimension (CD)

Hard Bake Oven PM, Temperature Temp.

Time N2 Flow Rate
Etch Etch rate, Equipment Etchant Temp.
PM & Settings, Etch Etch Rate
Time to Clear

Inspection Over/Under

PR Strip Machine·PM

Final Check C.D.'S Over and under

Etch, Particles;
PR Residue, Defects,
Scratches
QC Inspection Same as Final Check,
However, More Intense
on limited Sample
Basis. (AQL 6.5%)
Note: PM represents Preventive Maintenance
4. Reliability·related Interlayer Dielectric, Metallization, and Passivation Process Quality Control Monitor

Item Frequency

Wt% Phosphorus Content of the Dielectric Glass 1/Shift

Metallization Interconnect 1/Month
AI Step Coverage 1/Month
Metallization Reflectivity 1/Shift
Passivation Thickness and Composition 1/Shift
Thin Film Defect Density 1/Shift

c8 SAMSUNG SEMICONDUCTOR 34
QUALITY and RELIABILITY

Figure 9. General Wafer Fabrication Flow

Process Flow Process Step Major Control Item

Wafer and Mask

Input
I
Starting Material Mask: (See mask Inspection)
Incoming Inspection Wafer: (See wafer Inspection)

Wafer Sorting and

Resistivity
Labelling·

Initial Oxidation Oxide Thickness

• (See manufacturing section)

Photo
• (See FAB, QC Monitor/gate)

Inspection • Critical Dimension

• Visual/Mech - Major: AQL 1.0%
- Minor: AQL 6.5%

QC Gate • Critical Dimension

Diff'n
Metal
Etch • (See manufacturing section)
• (See FAB, QC Monitor/gate)

Inspection • Critical Dimension

• Visual/Mech - Major: AQL 1.0%
- Minor: AQL 6.5%

QC.Gate • Critical Dimension

• Visual/Mech

Diffusion • (See in·process Quality Inspection)

Metalizatlon

9 E·test • Electrical Characteristics

ciS SAMSUNG SEMICONDUCTOR 35

 QUALITY and RELIABILITY

Figure 9. General Wafer Fabrication Flow (Continued)

Process Flow Process Step Major Control Item

<> OC Gate • Electrical Characteristics

Back-Lap • Thickness

Back Side Evaporation • Thickness, Time

Evaporation Rate

Final Inspection • All Wafers Screened

(Visual/Mech)

OC Fab. Final Gate • Visual/Mech.

- Major: AOL 1.0%
/ ' - Minor: AOL 6.5%

EDS
(Electrical Die Sorting)

OC Gate • Function Monitor

Sawing
"

Inspection • Chip Screen

OC Final Inspection • AOL 1.0%

• Fab. Defect
• Test Defect
• Sawing Defect
Die Attach

c8 SAMSUNG SEMICONDUCTOR 36
QUALITY and RELIABILITY

ASSEMBLY
The process control and inspection points of the assembly operation are explained and listed below:

1. Die Inspection:
Following 100% inspection by manufacturing, in-process Quality Control samples each lot according to internal
or customer specifications and standards.

2. Die Attach Inspection:

I
Visual inspection of samples is done periodically on a machine/operator basis. Die Attach techniques are monitored
and temperatures are verified.

3. Die Shear Strength:

Following Die Attach, Die Shear Strength testing is performed periodically on a machine/operator basis. Either
manual or automatic die attach is used.

DIE ADHESIVE THICKNESS MONITOR RESULTS. (JEOL SEM, JSM IC845)

4. Wire Bond Inspection:

Visual inspection of samples is complemented by a wire pull test done periodically during each shift. These
checks are also done on a machine/operator basis and XR data is maintained.

5. Pre-SeaIfPre-Encapsulation Inspection:
Following 100% inspection of each lot, samples are taken on a lot acceptance basis and are inspected
according to internal or customer criteria.

WIRE LOOP MONITOR RESULTS. CROSS SECTION INSPECTION FOR BALL BOND.

ciS SAMSUNG SEMICONDUCTOR 37

 QUALITY and RELIABILITY

6. Seal Inspection:
Periodic monitoring of the sealing operation checks the critical temperature profile of the sealing oven for both
glass and metal seals.·

7. Post·Seal Inspection:
Subsequent to a 100% visual inspection, In-Process Quality Control samples each for conformance to visual
criteria. '

X-RAY MONITOR RESULT.'tPHILIPS MG161)

8. General Assembly Flow is shown in Figure 11.

Sampling Plans

1. Sampling plans are based on an AQL (Acceptable Quality Level) c,oncept and are determined by internal or by
customer specifications.

2. Raw Material Incoming Inspection. (continued)

Material Inspection liem Acceptable Quality Level

\ 1) Vjs,ual Inspection LTPD 10%, C=2
2) Dimension Inspection LTPD 20%, C=O
Lead Frame
3) Function Test LTPD 20%, C=O
4) Work Test LTPD 20%, C=O
,
Wafer 1) Visual Inspection AQL 0.65%
1) Visual Inspection n:5, C=O
2) Bond Pull Strength Test n: 13, C=O
AulAI 3) Bondability Test Critical Defect: 0.65%
\
Wire Major Defect: 1.0%
Minor Defect: 1.5%
4) Chemical Composition Analysis n: 5, C=O
1) Visual Inspection. n: 5, C=O
,2) Moldability Test Critical Defect: 0.15%
Molding Compound Major Defect: 1.0%
Minor Defect: 1.5%
3) Chemical Composition Analysis n: 5, C=O

c8 SAMSUNG SEMICONDUCTOR 38
 QUALITY and RELIABILITY

I
MOLDING COMPOUND INCOMING INSPECTION
(THERMAL ANALYSER, DUPONT 9900)
(Continued)

Material Inspection Item Acceptable Quality Level

1) Visual Inspection LTPD 15%, C=2

Packing Tube 2) Dimension Inspection LTPD 15% C=2
& Pin 3) Electro-Static Inspection n: 5, C=O
4) Hardness Test n: 5, C=O
1) Visual Inspection LTPD 20% C=O
Solder 2) Weight Inspection LTPD 20% C=O
3) Chemical Composition Analysis LTPD 20% C=O
1) Acidity Test LTPD 20% C=O
Flux 2) Specific Gravity Test LTPD 20% C=O
3) Chemical Composition AnalYSis LTPD 20% C='U
1) Visual Inspection AOL 1.0%
Solder Preform 2) Work Test AOL 1.0%
3) Chemical Composition Analysis' AOL 1.0%
1) Visual Inspection AOL 1.0%
Coating Resin 2) Work Test AOL 1.0%
3) Chemical Composition Analysis AOL 1.0%
1) Work Test Critical Defect: 0.15%
Major Defect: 1.0%
Marking Ink
Minor Defect: 1.5%
2) Mark Permanencx Test n: 5, C=O
1) Visual Inspection LTPD 15% C=2
2) Dimension Inspection LTPD 15% C=O
Chip Carrier
3) Electro-Static Inspection n: 5, C=O
4) Hardness Test n: 5, C=O
.. 1) Visual Inspection LTPD 20% C=O
Vinyl Pack 2) Work Test LTPD 20% C;=O
3) Electro-Static Inspection LTPD 15% C=O
1) Work Test n:8, C=·O
Ag Epoxy
2) Chemical Composition Analysis n:8, C=O
1) Visual Inspection
Letter Marking
2) Work Test
Spare Parts 1) Dimension Inspection n:5, C=O
& Others 2) Visual Inspection n:5, C=O

c8 SAMSUNG SEMICONDUCTOR 39
QUALITY and RELIABILITY

3. In·Process Quality Inspection'

A. Assembly Lot Acceptance Inspection
(1) Acceptance quality level for wire bond gate inspection

Defect Class Inspection level Type 01 Defect

- Missing Metal - Diffusion Defect

- Chip Crack ' - Ink Die
- No Probe - Exposed Contact
Critical Defect AQL 0.65% - Epoxy on Die - Bond Short
- Mixed Device - Die Lift
- Wrong Bond - Broken Wire
- Missing Bond
- Metal Missing - Oxide Defect
- Metal Adhesion - Probe Damage
Major Defect AQL 1.0% - Pad Metal Discolored - Metal Corrosion
- Tilted Die - Incomplete Wetting
- Die Orientation - Weakened Wire
- Partial Bond
- Adjacent Die - Contamination
- Passivation Glass - Ball Size
Minor Defect AQL 1.5% - Die Attach Defect - Wire Clearance
- Wire Loop Height - Bond Deformation
- Extra Wire

(2) Acceptance quality level for Mold/Trim gate inspection

Defect Class Inspection Level Kind of Delect

- Incomplete Mold - Deformatior)

Critical Defect AQL 0.15% - Void, Broken Package - No Plating
- Misalignment - Broken Lead
- Ejector Pin Defect - Crack, Lead Burr
Major Defect AQL 0.4% - Package Burr - Rough Surface
- Flash on Lead - Squashed Lead,
- Lead Contamination - Bent Lead
Minor Defect AQL 0.65% - Poor Plating
- Package Contamination

B. In·process monitor inspection

Inspection Item Frequency ReJerence

• Die Shear Test Each Lot MIL·STD·883C, 2019·2

• Bond Strength Test Each Lot MIL·STD·883C, 20114
• Solderability Test Weekly MIL·STD·883C, 2003·3
.' Mark Permanency Test Weekly MIL·STD·883C, 2015·4
• Lead Integrity Test Weekly MIL·STD·883C, 2004·4
• In·Process Monitor 4 Times/Shift/Each Process' Identify for Each -ontrol Limit
Inspection for Product
• X·Ray Monitor 2 Times/Shift/Mold Press Identify for Each Control Limit
Inspection for Molding
• Monitor Inspection 2 Times/Shift/Each Unit of Identify for Each Control Limit
for Production Equipment Equipment

cIS SAMSUNG ~EMICONDUCTOR 40

QUALITY and RELIABILITY

4. Outgoing quality inspection plan (LTPD)

Defect Class Discrete LSI Kind of Defect

Critical Defect

Major
electrical
visual
Defect
1% 2%
Open, short
Wrong configuration, no marking I
electrical 1.5% 3% Items which affect reliability most strongly
visual
Minor Defect Items which minimally or do
electrical 2% 5% not affect rei iabil ity at all
visual (cosmetic, appearance, etc.)

c8 SAMSUNG SEMICONDUCTOR 41
QUALITY and RELIABILITY

Figure 10. \leneral Assembly Flow

Process· Flow Process Step Major Control Item

Wafer

Wafer Incoming Q.C. Wafer Incoming Inspection AQL 4_0%

Inspection

Tape Mount

Sawing Q.C. Monitor Q.C. Monitoring:

- Chip-out - Scratch
- Crack - Sawing Discoloration
- Sawing-speed - Cut Count
- 0.1. Purity - CO2 Bubble Purity
Visual Inspection 100% Screen:
- FAB Defect
- EDS Test Defect
- Sawing & Scratch Defect

Q.C. Gate 1st AQL 1.0%

Reinspection AQL: 0.65%

Lead Frame (UF)

Lead Frame Incoming *Q.C.UF Incoming Inspection

1. Acceptance Quality Level
- Dimension LTPD 20%, C=O
- Visual & Mechanical: LTPD 10%, C=2
- Functional Work Test: LTPD 10%, (:;=2

R>
Die Attach (D/A)

Q.C. Monitor *Q.C.D/A Monitor Inspection

1. Bond force
2. Frequency: 4 Times/Station/Shift
3. Sample: 24 ea Time
4. Acceptance Criteria

Defect Acceptance Reject

Critical 0 1
Major 1 2

~l Cure

c8 SAMSUNG SEMICONDUCTOR 42
 QUALITY and RELIABILITY

. Figure 10. General Assembly Flow (Continued)

Process Flow Process Slep Major Conlrol Ilem

<>
Q.C. Monitor 'Q.C. Cure Monitor Inspection
1. Control Item
- Temperature
- In/out Time
2. Frequency
I
- 1 Time/Shift

Au Wire

Bonding Wire 'Q.C Au Wire Incoming Inspection

=
1. Visual Inspection: N 5, C = 0
Incoming Inspection 2. Bond Pull Test Strength Test: N = 13, C = 0
3. Bondability Test
- Critical Defect: AQL 0.65%
- Major Defect: AQL 1.0%
- Minor Defect: AQL 1.5%

Wire Bonding (W/B)

r 100% Visual
Inspection

Q.C. Monitor 'Q.C. W/B Monitor Inspection

1. Frequency: 6 Times/Mach/Shift
.-
Q.C. Gate 1. Q.C. Acceptance Quality Level
- Critical Defect: AQL 0.65%
- Major Defect: AQL 1.0%
- Minor Defect: AQL 1.5%

Mold Compound

'Moldability Test
Incoming Inspection - Critical Defect: AQL 0.15%
Mold - Major Defect: AQL 1.0%
- Minor Defect: AQL 1.5%

Mold

Q.C. Monitor 'Q.C. Mold Monitor Inspection

1. In·Process Monitor Inspection
- Frequncy: 4 Times/Station/Shift
- Sample: 200 UnitslTime
2. Acceptance Quality Level
- Critical Defect: AQL 0.25%
- Major Defect: AQL 0.4%

c8 SAMSUNG SEMICONDUCTOR 43
QUALITY and RELIABILITY

Figure 10. General Assembly Flow (Continued)

Process Flow Process Step Major. Control Item

n
Cure

a.c. Monitor 'a.c. Cure Monitor Inspection

1. Control Item
- Temperature
- In/out Time
2. Frequency
- 1 Time/shift

6
Deflash

a.c. Monitor 'a.c. Deflash Monitor Inspection

1. Control Item
'- Pressure
- Belt Speed
~ Visu"aliMechanical Inspection
2. Frequency: 4 Times/Mach/Shift
3. Identify each Defect Control Limit

6
TRIM/BEND

'a.c. Trim/Bend Monitor Inspection

a.c. Monitor 1. Visual Inspection
2. Frequency: 4 Times/Station/Shift

}- Solder 100% Visual Inspection

a.c. Monitor 'a.c. Solder Monitor Inspection

1. Frequency: 4 Times/Mach/Shift
2. Criteria
- Critical Defect: AaL 0.65%
- Major Defect: AaL 1.0%
a.c. Gate 'a.c. Mold Gate
- Acceptance Criteria
Critical Defect: AaL 0.15%
Major Defect: AaL 0.4%
Minor Defect: AaL 0.65%
I

Test 100% Electrical Test

a.c. Monitor Correlation Sample Reading for Initial

Device Test

"91 Mark 100% Visual Inspection

c8 SAMS~NG SEMICONDUCTOR 44
QUALITY and RELIABILITY

Figure 10. General Assembly Flow (Continued)

I
Process Flow Process Step Major Control Item

0 PRT Monitoring
(Process Reliability
Testing)
1. PRT
- HOPL (168 HRS), PCT (48 HRS)
- Other (when applicable)
2. Acceptance Criteria: LTPD 10%

0 Q.C. Monitor "Q.C. Marking Monitor Inspection

- Frequency: 4 Times/Station/Shift
- Sample: 24 UnitslTime
- Identify for Each C.L.
- Acceptance Criteria

Defect Acceptance Reject

Critical 0 1
Major 1 2
I

Q.C. Gate "Q.C. Final Acceptance Level

- Critical Defect: AQL 0.15%
- Major Defect: AQL 0.4%
- Minor Defect: AQL 0.65%

Q.A. Gate "Q.C. Incoming Inspection

1. Critical Defect:
- Electrical Test: LTPD 2% (N=116; C=O)
- Visual Test: LTPD 2% (N=116, C=O)
2. Major Defect:
- Electrical Test: LTPD 3% (N = 116, C = 1)
- Visual Test: LTPD 3% (N=116, C=1)
3. Minor Defect:
- Electrical Test: LTPD 5% (N=116, C=2)
- Visual Test: LTPD 5% (N=116, C=2)

I I Stock "Age Control

0 Q.A. Gate "Q.A. Outgoing Inspection

1. Quantity
2. Customer
3. Packing
4. Sampling Inspection (when applicable) .
- Sampling plan is same as incoming
Inspection

. Shipment

c8 SAMSUNG SEMICONDUCTOR 45
QUALITY and RELIABILITY·

SST's BEST PROGRAM

The SST Best Program has been designed to offer the customer an alternative to standard off-the-shelf plastic
encapsulated LINEAR circuits. The Best Program will significantly reduce incoming inspection requirements as
well as early device failures (infant mortalify). These results are achieved by a tightened AQL inspection plan and
a burn-in of each unit for 160 + 8, - 0 hours at 125°C or equivalent conditions established from a time/temperature
regression curve. -

The AQL Plan. Acceptable Quality Levels (AQL) are a measure of the ql\ality of outgoing LINEAR circuits. These
levels are established by the manufacturer to show the process percent defective being produced and to ensure
that the customer is receiving material tl:1at meets his requirements. The SST Best Program has tightened these
AQL levels to a point at which incoming inspection by the customer is no longer a necessity. Best product quality
is monitored significantly more closely than standard product; those lots which fall the AQL level are 100% reworked -
before resubmission to the AQL gate.

The Reliability Plan. Reliability is the statistical probability that a product will give satisfactory performance for
a specified period of time when used under specified conditions. A typical rate curve is shown below:

INFANT
MORTALITY

w
~
w
a:
::::I
...J
RANDOM FAILURES AT A
~ LOW CONSTANT FAILURE RATE
I
I
o I
BURNINI - OPERATING L l F E - - - -
PERIOD I

Reliability theory assumes that devices fail according to the above curve. When a group of devices is manufac·
tured a small portion of the units will be inherently weaker than the average. These weak units will probably fail
during the first few hours of operation-hence the term "infant mortali!y." If the units are burned-in however, thereby
allowing the weak units to fail, there is a much lower probability that those finally put into system use will fail.

The SST Best Row. in order to achieve an extremely high quality unit and reduce infant mortality failures the following
flow has been established:

c8 SAMSUNG SEMICONDUCTOR 46
QUALITY and RELIABILITY

Process Flow

FLOW CHART

I I
WAFER FABRICATION
LINEAR PROCESS
CV PLOTS
DESCRIPTION

OXIDE THICKNESS MEASUREMENTS

II
OPTICAL INSPECTIONS
SEM ANALYSIS
ENCAPSULATION
I I MOLDING COMPOUND ULTRA PURE FOR LINEAR
APPLICATIONS
POST MOLD BAKE
6 HOURS AT 175 DEG. C .
1 . 1 CURES PLASTIC
STRESSES ALL WIRE BONDS AND DIE
O/S FUNCTIONAL ELECTRICAL
I I 100% TESTING
OPENS/SHORTS AND INTERMITTENTS REMOVE
HIGH TEMPERATURE BURN-IN
160 HOURS AT 125 DEG. C. OR EQUIVALENT
I I CONDITIONS ESTABLISHED FROM A TIME/
TEMPERATURE REGRESSION CURVE. 0.96 eV
FULL FUNCTIONAL AND PARAMETRIC
ELECTRICAL TESTING
I I 100% ELECTRICAL TESTING AC, DC

§
88 DEG. C.
TIGHT AQL SAMPLING PLAN
ELECTRICAL-0.05% AQL AT 88 DEG. C.
MECHANICAL-O.o1% AQL CRITICAL & MAJOR
SHIP UNITS

c8 SAMSUNG SEMICONDU~R 47
NOTE
LINEAR ICs FUNCTION GUIDE

1. TELECOMMUNICATION APPLICATION
Application Type Package Circuit Function

Adjustable warbling and 2 frequency tone

KA241 0 External triggering or ringer disable (KA2410)
Tone Ringer 8 DIP
KA2411 Adjustable supply initiating current (KA2411)
Built-in hysteresis
Protect against over voltage
Low current consumption
Tone Ringer
Allow the parallel operation of 4 devices
with
Built-in hysteresis
Bridge tKA2418 8 DIP
External components are minimized
Rectifier High output voltage
Included bridge diode
Direct telephone line operation
Standard 2 of 8 key board use
KS5808 16 DIP
Tone output: Bipolar output
Mute output: N-CH open drain
DTMF Dialer
Wide operating line voltage and current range
Short start 'up time
tKA2413 16 DIP
External components are minimized
Internal protection of all inputs
KS5805A: Pin 2; Vref
KS5805B: Pin 2; Tone output
PULSE Dialer KS5805A/B 18 DIP RC oscillator used as frequency reference
Pulse output: "0" true,
Mute output: "0" true
tKS58A/B/C/D19 22 DIP Tone/pulse switchable dialing, touch key or slide switch
DTMF/Pulse
32 digit redialing & PABX auto pause time
Switchable tKS58A/B20 18 DIP
Make/break ratio pin selectable
Dialer ttKS58A1B/CID21 22 DIP KS5821 (Telephone lock function)
t New Product
tt Under Development

c8 SAMSUNG SEMICONDUCTOR 51
LINEAR ICs FUNCTION GUIDE

TELECOMMUNICATION APPLICATION (Continued)

Application Type Package Circuit Function

DTMF/Pulse 10 No. x 18 digit memory including a redial memory

Switchable Including PABX auto pause time
ttKS5823 18 DIP
with 10 No. 10 pps/20 pps pin selectable
Memory Make/break ratio: 40%/60%
Transmit/Receiver amplifier
Speech Network KA2412A 14 Dip Side tone control
On chip regulator
Low Voltage Operation (1.5V)
Tx, Rx & side tone gain set by external resistors
Low Voltage
Loop length equalization for Tx, Rx & sidetone
Speech Network tKA2425A/B 18 DIP
Provides regulated voltage for CMOS dialer
with Dialer Interface
DTMF level adjustable with a singre resistor
A: Mute active low B: Mute active high
Touch tone decoding
Sequential tone decoding
8 DIP
Tone, Decoder LM567C/L Commu"nication paging'
8 SOP
High stable center frequency
LM567L: Micropower (4mW at 5V) dissipation
"
,
Small current dissipation (Typ. 3.5mA: Vee 4.0V)
Excellent input sensitivity
16 DIP
FM IF Amplifier MC3361 Minimum number of external parts required
16 SOP
Used to cordless telephone parts required
Work from 1.8V to 7.0V
w255 companding law
± 5V operation
wLaw Codec tKT5116J 16 DIP
Synchronous or Asynchronous'operation
On-chip sample and hold.
Exceeds' all D3/D4 and CCITT spec.
± 5V operation
Law power consumption
Codec Filter tKT3040J 16 DIP
20dB gain adjust range
Sin X/X correction in receive filter
TTL and CMOS compatible logic
ttKT3054J 16 DIP Exceeds all 03/04 and CCITT spec.
Complete CODEC and filtering system including
wLaw Combo ± 5V operation
Codec ttKT3064J 20 DIP Low power consumption
TTL and CMOS compatible logic
Receive push-pull power amp (KT3064)
t New Product
tt Under Development

c8 SAMSUNG SEMICONDUCTOR 52
LINEAR ICs FUNCTION GUIDE

TELECOMMUNICATION APPLICATION (Continued)

Application Type Package Circuit Function

Conformance EIA standard No. RS-232C & V28 (CCITI)

Quad line driver
Interface between data terminal equipment (DTE) and
14 DIP data communication equipment (DCE)
Line Driver MC1488
14 SOP Current limited output: ± 10mA typo
Power-off source impedance 300 ohms min.
Compatible with DTL and TTL, HCTLS families
Flexible operating supply range
Conformance EIA standard No. RS-232C & V-28 (CCITI)
Quad line receiver
Interface between data terminal equipment (DTE) and
14 DIP data communication equipment (DCE)
Li ne Receiver MC1489/A
14 SOP Input signal range ± 30 volts
Input threshold hysteresis built in
Response control
a) Logic threshold shifting
b) Input noise filtering
Consisting of 8 NPN darlington output stages and
associated common-emitter input stages
Fluorescent Digit or segment drivers
ttKA2651 18 DIP
Display Driver Low input current, internal output pull-down resistors
High output breakdown voltage
Single or split supply operation
TTL, CMOS, PMOS, NMOS compatible
High output current ratings
KA2580A 18 DIP Internal transient suppression
8-Channel Efficient input/output pin structure
Source Driver Low voltage LEDs and incandescent lamp
KA2588A 20 DIP KA2588A: Separated logic and driver supply line
The data formatting and control to interface serial
asynchromous data communications between main
system and subsystems.
Low power, high speed CMOS process
Universial
ttKS5824 24 DIP Serial/parallel conversi?n of data 8 and 9 bit
Asynchronous
tKS5812 4n DIP transmission
Receiver and
Programmable control register
Transmitter (UART)
Optional .,. 1, .,. 16, and .,. 64 clock modes
Peripheral/modem control functions
Double buffered
Included 4 UART in one chip (KS5812)

t New Product
tt Under Development

c8 SAMSUNG SEMICONDUCTOR 53
LINEAR ICs FUNCTION GUIDE

2. VOLTAGE REGULATOR
A. 3-Tenninal Fixed Positive Voltage Regulator
Function - Type Package Features Application

Maximum output current 1A 5V, 6V, 8V, 8.5V, 9V, 10V

High output- External components are minimized 11V, 12V, 15V, 18V
. MC78XX
Current TO-220 Internal protection circuit fo~ output short and 24V fixed
series
(lo =1A) Positive voltage regulator output voltage
Variable application control
Maximum output current 500mA 5", 6V, 8V, 10V,
Medium·
Extemal c.omponen-ts are minimized 12V, 15V, 18V
output MC78MXXC
TO-220 Internal protection circuit for output short and 24V fixed
current AC Series
_POSitive voltage ;egulator output voltage
(/s=500mA)
Variable application circuit
Output current in excess of 100mA
2.6V, 5V, 6.2V;
Low External componerit minimized
8V, 8.2V, 9V, 12V,
Output MC78LXXAC Internal protection circuit for
TO-92 15V, 18V arid 24V
Current series output short .
fixed output
(l o =100mA) Positive voltage .regulator
voltage
Variable application circuit
Maximum output. current 3A 5V, 6V, 8V, 12V
3A Output tKA78TXX No external components required 15V, 18V, 24V-
TO-220
Current Series Internal protection circuit for output short fixed output
Power dissipation: 25W voltage
3A, 5V Maximum output current 3A
Positive LM323 TO-39 Intemal current and thermal limiting. 5V
Regulator Positive voltage regulator

B. 3~Tenninal Fixed Negative Voltage Regulator

Function Type Package Features Application

Output current in excess of 1A . -2V, -5V, -6V,

High output Internal thermal overload protection -8V, -10V, -12V,
MC79XXC TO-220
Current Internal short circuit current -15V, -18V, and
series
(/0=1A) limiting -24V, fixed
, output voltage
Medium Oiltput't:urrent in excess of 500mA -2V, -5V, -6V, -8V,
Output MC79MXXC Internal overload protection - -10V, -12V, -15V,
TO:220 -18V and 24V fixed
Current Series Internal short circuit current
(10 = 500mA) limiting output voltage -
Low Output Output current In excess of 100mA -5V, -12V, -15V,
Current ttMC79LXXAC TO-92 Internal short circuit current limiting -18V and - 24V fixed
(/0=100mA) External component minimized output voltage
- t New Product
. tt Under Development

c8 SAMSUNG SEMICONDUCTOR: ~4
LINEAR ICs FUNCTION GUIDE

C. Precision Voltage Regulator

Function Type Package Features Application

Positive or negative supply operation Output voltage

Series, shunt, switching or floating adiustable
Precision
Regulator
LM723 14 DIP
operation
0.01 % line and load regulation
,
from 2 to 37V

Output current to 150mA without external

33V
Regulator
KA33V ITO-92
pass transistor
Low temperature coefficient
Low dymic resistance

Output current in excess of 1.5A

Electronic tuning
system
Floating operation for
I
high voltage operation
Output adjustable from 1.2V to 37V
ttLM317 TO-220 Eliminates stocking
Internal short circuit current limiting
many fixed voltage
Adjustable 3-terminal negative Output voltage
vqltage regulator adjustable from
Adjustable Line regulation typically 0.01 %/V -1.2V to -37V
ttKA337 TO-220
Regulator Load regulation typically 0.3%
Internal thermal overload protection
1.5A output current
Adjustable 3-terminal positive Output voltage
voltage regulator adjustable from
ttKA350 TO-3P
3A output current 1.2V to 25V
Guaranteed, thermal regulation

D. Switching Voltage Regulator

Function Type Package Features Application

Peak output current of 1.5A Step-down converter

Adjustable
16 DIP without ex~ernal transistor Step-up converter
1.25V'to KA78S40
tt16 SOP BOdB line and load regulation Inverter
40V
, Operation from 2.5V to 40V
PWM power control circuitry Switching regulator
Frequency adjustable to greater than Trans DC-DC converter
PWM
tKA3524 16 DIP 100KHz Inverting v~ltage
100KHz
Total supply current is less than 10mA regulator
Single ended or push·pull output

.
3 PRECISION VOLTAGE REFERENCE
Function Type Package ' Features Application'

Programmable output voltage from Switching regulator

TO-92
Adjustable Vref to 36V Constant current
KA431 t8 DIP
Reference Voltage reference tolerance: ± 1.0% source
t8 SOP,
Low output noise voltage Constant current sink
Adjustable 4V to 6V Adjustable shunt
5V Low temperature coefficient regulator
tKA336 TO-92
Reference 0.60 dynamic impedance Precision power
Fast Turn-on regulator
Low temperature coefficient Micropower
1.235V
KA385 TO·92 operating current of 10ILA to 20mA reference
Reference
10 dynamic impedance

c8 SAMSUNG SEMICONDUCTOR 5,5

 LINEAR ICs FUNCTION GUIDE

4. OPERATIONAL AMPLIFIER
Function Type Package Features Application

LM741
• 8 DIP Internal frequency compensation
Comparator, DC amp,
Multivibrator, 'Summing
8 SOP Short circuit protection amp, Integrator or differen-
tiator Narrow band or BPF
Slew·rate of 10V/p,s as a summing Variable capacitance
r· 8 DIP
KA301A amplifier Multiplier
8 SOP
External frequency compensation Sine wave oscillator
OPAMP JFET input
High speed intergrators
8 DIP Low input bias current
ttKF351 Fast D/A converters
8 SOP High slew rate 13V/p,s
Sample arid hold c1rcuits
Wide gain bandwidth
120MHz band width Disk file memories
14 DIP
KA733 Selectable gains of 10, 100, 400 Magnetic tape systems
14 SOP
No frequency compansation Wide band video amplifiers
Phone pre-amplifier
MC4558 8 DIP Internal frequency compensation
Tape playback amplifier
MC1458 8 SOP Low noise operation
Schmitt trigger,
Internal frequency compensation DC summing amplifier
Dual LM358/A for unit gain Power amplification
8 DIP
OPAMP LM258/A Large DC voltage gain RC active bandpass filter
t8 SOP
LM2904 Wide power supply range Compatible with all forms
of logic
Internal current limiting: Isc = 350mA
High power amplifier
tKA9256 . 10 SIP HIS Internal frequency compensation
CD driver
Minimal cross over distortion'
Internal frequency compensation Audio power booster
LM324/A
14 DIP. Wide supply voltage range DC amp, Multivibrator
LM224/A
14 SOP Single supply: DC 3V - 30V Switch, Comparator
LM2902
Dual .supply: DC ± 1.5V - ± 15V Schmitt trigger
Each amplifier is functionally
Comparator with
Quad LM348 14 DIP equivalent to the LM741
hysteresis
OPAMP LM248 14 SOP Pin compatible with LM324
Voltage reference
Short circuit protection
Class AB output stage for minimal
Comparator with
MC3403 14 DIP crossover distortion
hysteresis
tMC3303 14 SOP Single or split supply operation
Bi-Quad filter
Internal frequency compensation

t New Product
tt Under Development

c8 SAMSUNG SEMICONDUCTOR 56
LINEAR ICs FUNCTION GUIDE

5. VOLTAGE COMPARATOR
Function Type Package Features Application

Operates from single 5V supply Multivibrator output is

Maximum input current: 250nA compatible with DTL and
ILM311 8 DIP
Maximum offset current: 50nA as well as MOS circuits

II
tLM211 t8 SOP
Differential input voltage range: ± 30V voltage controlled
Power consumption: 135mW at + 15V oscillator
independent strobes High speed analog
Single ttKA361
14 DIP Guaranteed high speed: 20nS max. to digital converter
Comparator ttKA261
Complementary TTL outputs Zero-crossi ng detectors
Interface between
Low offset and thermal drift
14 DIP logic types
KA710C t14 SOP Compatible with practically
Level detector
all types of integrated logic
with lamp
High precision comparators Output voltage compatible
Reduced Vos drift over temperature with TTL, DTL, ECL and
Eliminates need for dual supply CMOS logic system
Allows sensing near ground Basic comparator
LM393/A
Compatible with all forms of logic Pulse generator
Dual LM2903 8 DIP
Power drain suitable for battery MOS clock driver
Comparato"r LM293 8 SOP
operation
Low input biasing current: 25nA
Low output saturation voltage 250mV
at 4mA
Two indepentent comparators
KA319 14 DIP Relay driver
Operates from a single 5V
KA219 t14 SOP Window detector
High common mode slew rate
Wide single supply voltage Compatible with all forms
range or dual supplies of logic
Very low supply current drain Bi-stable multivibrator
LM339/A (0.8mA)-independent of supply One-shot multivibrator
Quad LM2901 14 DIP voltage (2mW/Comparator at + 5V DC) Time deiilY generator
Comparator LM239 14 SOP Low input biasing current: 25nA Square wave oscillator
LM3302 Input common-mode voltage range Pulse generator
includes GND Limit comparator
Low output saturation volti!lge 250mV Crystal controlled
at 4mA oscillatgor

t New Product
tt Under Development

c8 SAMSUNG SEMICONDUCTOR 57
LINEAR ICs FUNCTION GUIDE

6. TIMER
Func;tlon Type Package Features Application

Maximum operating PreCision timing

8 DIP
NE555 frequency: 500KHz Pulse generator
t8 SOP
Adjustable ~uty cycle

Single Low power consumption by using

Timer CMOS process
KS555 8 DIP High speed operation Precision timing
tKS555H t8S0P Wide operation supply voltage: Pulse generator
2 to 18 volts
Pin compatible. with NE555
14 DIP TTL Compatible Time delay generation
NE556
t14 SOP Dual NE555
Dual Low· power consumption Time delay' generation
Timer 14 DIP by using C-MOS process
tKS556
t14 SOP Pin compatible with NE556
Wide supply voltage range: Quad monostable
Quad 4.5 to·.16V Sequential timing
tNE558 16 DIP
Timer 100mA output current per section Precision timing
Time period equal RC

7. DATA CONVERTER les

Functions Type Package Features Applications

High speed 8-bit AID and 10-bit D/A Image processing

A/D,D/A tKSV3100A 40 DIP
converter on the single chip construction Video/Graphics
Converter
ttKSV311Q 40 DIP Enhanced version of KSV3100A
Image processing
ttKSV3208 28. DIP High speed 8,bit AID converter
Video/G raphics
8-bit I'P-compatible AID converter with
8-channel multiplexer linearity error
tKAD0808/9 28 DIP
AID KAD0808: ± 1/2 LSB
Converter KAD0809: ± 1 LSB General purpose and
I'P-interface system
8 bit I'P-conipatible AID converter with
Track/Hold function linearity
ttKAD0820AiB 20 DIP
KAD0820A: ± 1/2 LSB
KAD0820B: ± 1 LSB
DMM A/D tKS7126 40 DIP 3-1/2 digit LCD driver AID converter Digital multi-meter
ttKSV3404 High speed quad 4-bit DIA converter Video/Graphics
D/A
ttKDAOadO 16 DIP 8-bit D/A converter General purpose and
Converter
ttKDA0808 16 DIP 8-bit D/A converter I'P-interface system
ttKS25C02 8-bit CMOS successilie app~oximation
16 DIP
ttKS25C03 registers
S.A.A. SAR of AID converter
12-bit CMOS successive approximation
ttKS25C04 24 SDIP
registers

t New Product tt Under Development

c8 SAMSUNG SEMICONDUcroR 58
LINEAR ICs FUNCTION GUIDE.

8. MISCELLANEOUS ICs
Function Type Package Features Application

KA2303 9SIP High gain amplifier, Peak detector, 3 Function

T flip-flop, comparator with
Toy Radio tKA2304 9SIP hysteresis, regulator, motor driver 2 Function

I
Control
Actuator ttKA2307 16 DIP Receiver 5 Function
ttKA2308 14 DIP Transmitter 5 Function
KA2401 8 DIP Stable voltage reference
Vcc =4-12V
DC Motor KA2404 TO-92L VreI = 1.27V (Typ.)
Speed
KA2402 8 DIP Stable current source Vcc =1.8-8V
Controller
Stable voltage reference
tKA2407 TO-126 Vee = 3.5-14.4V
VreI = 1.0V (Typ.)
Earth Low power consumption
Leakage KA2803 8 DIP High noise immunity Earth leakage detector
Detector Few external components
Easy operation either through
the AC line or a DC supply
Zero Supply. voltage control ON, OFF temperature control
Voltage KA2804 8 DIP External component are Time proportional
Switch minimized temperature control
Negative output current pulse up
to 250mA (short circuit protection)
t New Product
tt Under Development

c8 SAMSUNG SEMICONDUCTOR 59
LINEAR ICs CROSS REFERENCE GUIDE

1; TELECOMMUNICATION ICs
A. Dialer
Application SAMSUNG MOSTEK AMI UMC SHARP Othel'$

KS5805A *MK50992 ·S2560A/B *T40992 *LR40992

Pulse Dialer
KS5805B *MK50993 *T40993 *LA40993
KS5808 'MK5089 'S25089 'UM95089 'LA4089 'SBA5089
DTMF Dialer KA2413 *PBD3535 UM95087 LA4087 SBA5091
(RIFA) SBA5099
Tone/Pulse tKS5819 *UM91230 LR48081 *S7230A/B
Switchable with tKS5820 MK5370 'UM91210 LR48082 • LC7360
Redial Memory ttKS5821
Tone/Pulse ttKS5823 . MK5380 UM91250 LR4803 PCD3315
Switch able with MK5375/6 UM91260
10 No. Memory

B. Tone Ringer

Application SAMSUNG MOTOROLA SGS MITEL CHERRY Others

KA241 0 *ML8204 'CS8204 *TA31001

Tone Ringer
KA2411 'ML8205 *CS8205 *TA31002
1 Chip Tone Ringer tKA2418 MC34012/7 • LS1240

C.~peech Network

Application SAMSUNG SGS RIFA ITT ERSO Others

Subset Amplifier KA2412A • LS285/A PBL3726 TEA1045 *CIC9185

Speech Network tKA2425A *MC34014
with Dialer tKA2425B LS356 PBL3781 (MOTOROLA)
Interface

D. Tone Decoder

Application SAMSUNG NATIONAL SHARP SIGNETICS Others

LM567 *LM567 *IR3N05 'NE567 *XR567 (EXAR)

Tone Decoder
LM567L *XAL567 (EXAR)
t New Product
tt Under Development

c8 SAMSUNG SEMICONDUCTOR 60
LINEAR ICs CROSS REFERENCE GUIDE

E. FM IF Amplifier
Application SAMSUNG MOTOROLA SHARP SPRAGUE Others

FM IF Amplifier MC3361 " MC3361 IR3N06 ULN3859 "LM3361

I
F. Codec, Codec Filter, Combo Codec

Application SAMSUNG N/S FAIRCHILD SGS Others

. wLaw Codec tKT5116J *TP5116 */LA5116 *M5116 2910 *MK5116
Codec Filter tKT3040J *TP3040 */LA5912 *M5912 *2912 *ETC5040
wLaw Combo Codec ttKT3064J *TP3064 2913 MC14400·5 *ETC5064
wLaw Combo Codec ttKT3054J " TP3054 *2916

G. Interfaces
Application SAMSUNG MOTOROLA FAIRCHILD TI N/S EXAR SIGNETICS

Line Driver MC1488 *MC1488 */LA1488 "SN75188 *DS1488 *XR1488 *MC1488

MC1489 *MC1489 */LA1489 *SN75189 *DS1489 XR1489 *MC1489
Line Receiver
MC1489A * MC1489A */LA1489A *SN75189A * DS1489A *XR1489A * MC1489A

H. Driver

. Application SAMSUNG SPRAGUE Others

Fluorescent Display Driver ttKA2651 *UCN5815A

KA2580A *UDN2580A
8CH Source Driver
KA2588A *UDN2588A

I. UART

Application SAMSUNG HITACHI MOTOROLA Others

_ Single UART ttKS5824 . *HD6350 * MC6850

Quad UART tKS5812

t New Product
tt Under Development
* Direct Replacement

c8 SAMSUNG SEMICONDUCTOR 61
LINEAR ICs CROSS REFERENCE GUIDE

2. VOLTAGE REGULATOR
A. 3-Terminal Fixed Positive Voltage Regulator

Description SAMSUNG MOTOROLA FAIRCHILD NEC MATSUSHITA Package

MC7805AC/C MC7805AC/C I'A7805 I'PC7805 AN7805

MC7806AC/C MC7806AC/C I'A7806 AN7806
MC7808AC/C MC7808AC/C I'A7808 I'PC7808 AN7808
MC7885AC/C I'A7885
MC78XXAC/C MC7809AC/C
Series MC7810AC/C T0-22O
(lo=1A) MC7Q11AC/C
MC7812AC/C MC7812AC/C ,.A7812 I'PC7812 AN7812
MC7815AC/C MC7815AC/C I'A7815 I'PC7815 . AN7815
MC7818AC/C MC7818AC/C I'A7818 I'PC7818 AN7818
MC7824AC/C . MC7824AC/C I'A7824 I'PC7824 AN 7824
MC78M05C MC78M05C ,.A78M05C I'PC78M05 AN 78M05
MC78M06C MC78M06C I'A78M06C AN78M06
MC78M08C MC78M08C I'A78M08C I'PC78M08 AN78M08
MC78MXXC
MC78M10C I'PC78M10 AN78M10
Series TO-22O
MC78M12C MC78M12C ,.A78M12C I'PC78M12 AN78M12
(lo=0.5A)
MC78M15C MC78M15C ,.A78M15C I'PC78M15 AN38M15
MC78M18C MC78M18C I'PC78M18 AN78M18
MC78M24C MC78M24C I'A78M24 I'PC78M24 AN78M24
MC78L26AC
MC78L05AC MC78L05AC I'A78L05AC
MC78L62AC I'A78L62AC
MC78L08AC MC78L05AC
MC78LXXAC MC78L82AC I'A78L82AC
TO-92
(lo=0.1A) MC78L09AC I'A78L09AC
MC78L12AC MC78L12AC ,.A78L12AC
MC78L15AC MC78L15AC I'A78L15AC
MC78L18AC MC78L18AC
~C78L24AC' MC7.8L24AC
KA78T05AC/C MC78T05AClC
KA78T06C MC78T06C
KA78TXXAC/C .KA78TOBC MC78T08C
Series KA78T12AC/C MC78T12AC/C TO-220
(10 = 3A) KA78T15AClC MC78T15AC/C
KA78T18C MC78T18C
KA78T24C MC78T24C
LM323 LM323 LM323 SH323
=
(10 3A) (TO-3P) (T0-3/T0-220) (TO-3)

c8 SAMSUNG SEMICONDUCTOR 62
LINEAR ICs CROSS REFERENCE GUIDE

B. 3·Terminal Fixed Negative Voltage Regulator

Description SAMSUNG MOTOROLA FAIRCHILD NEC MATSUSHITA Package

MC7902C
MC7905C MC7905C ,.A7905· ,.PC7905 AN7905
MC7906C MC7906C AN7906
MC79XXC
Series
(10= 1A)
MC7908C
MC7910C
MC7912C
MC7915C
MC7918C
MC7924C
MC7908C

MC7912C
MC7915C
MC7918C
MC7924C
,.A7908

,.A7912
,.A7915
,.PC7908

,.PC79t2
,.PC7915
,.PC7918
,.PC7924
AN7908

AN7912
AN7915
AN7918
AN 7924
·TO-220.
II
MC79M02C
MC79M05C MC79M05C ,.A79M05
MC79M06C
MC79M08C ,.A79M08
MC79MXXC TO-22O
MC79M10C
(l o =0.5A)
MC79M12C MC79M12 ,.A79M12
MC79M15L MC79M15 ,.A79M15
MC79M18C
MC79M24C
MC79L05AC MC79L05AC
MC79L12AC MC79L12AC
ttMC79LXXAC TO-92
MC79L15AC MC79L15AC
(l o =0.1A)
MC79L18AC MC79L18AC
MC79L24AC MC79L24AC

c. Precision Voltage Regulator

Description SAMSUNG MOTOROLA FAIRCHILD N/S NEC Package

Adjustable LM723 MC1723 p.A723 LM723 14 DIP

Voltage ttLM317 LM317 ,.A317 LM317 TO-220
ttKA337 LM337 LM337 LM337 TO-220
Adjustable
Voltage ttKA350 LM350 LM350 LM350 TO-220

33V Regulator KA33V ,.PC574 TO-92

D•.Switching Voltage Regulator

Qescription SAMSUNG MOTOROLA FAIRCHILD N/S TI Package

Adjustable
1.25V to 40V ,.A78S40 ,.A78S40 ,.A78S40 16 DIP
(fo = 100KHz)
PWM 100KHz tKA3524 LM3524 SG3524 16 DIP.
t New Product
tt Under Development

c8 SAMSUNG SEMICONDUCTOR 63
LINEAR ICs CROSS REFERENCE GUIDE

3~_ PRECISION VOLTAGE REFERENCE

Description SAM$UNG MOTOROLA FAIRCHILD N/S TI Package

Adjustable KA431 TL431 ",A431 TL431 TO-92

Reference t8 DIP
(2.5V-36V) t8 SOP
5V Reference-· - tKA336 LM336 TO-92
1.235V
ttKA385 LM385 LM385 TO-92
Reference

4. OPERATIONAL AMPLIFIER
Description SAMSUNG MOTOROLA NATIONAL FAIRCHILD MATSUSHITA Others

LM741 MC1741 LM741 - ",A741

KA301/A LM301/A LM301/A ",A301/A
Single OP Amp ",PC301C
KA733C MC1733C LM733C -",A733C
ttKF351 LF351 LF351
LM358/A LM358JA LM358JA AN6562 TA75358
LM258JA L.M258 LM258JA
LM2904 LM2904 LM2904
Dual OP Amp
MC1458 MC1458 LM1458 ,..A1458
MC4558 MC4558 ",A4558 AN4558 NJM4558
tKA9256 "TA7256
lM324JA LM324JA lM324JA ,..A324 AN6564 TA75324
lM224JA LM224 lM224JA ",A224
LM2902 lM2902 lM2902 ",A2902
Quad OP Amp
lM348 lM348 LM348 ,..A348
LM248 LM248 lM248 ,..A248
MC3403 MC3403 ,..A3403 NJM3403A
ttMC3303 MC3303 ,..A3303

5. VOLTAGE COMPARATOR
Description SAMSUNG MOTOROLA NATIONAL FAIRCHILD TI Others

lM311 LM311 lM311 LM311 LM311 LM311

LM211 LM211 LM211 LM211
Single Comparator tKA361 lM361
ttKA261 LM261
tKA7.10C LM710 ,..A710C JZA710C
LM393JA LM393JA LM393JA lM393JA TA75393
LM2903 LM2903 LM2903 lM2903 AN6914
Dual Comparator lM293 lM293 LM293 LM293
KA319 LM319 LM319 NJM319
ttKA219 LM219 LM219
LM339JA lM339JA LM339JA ,..A339 LM339 TA75339
LM2901 LM2901 LM2901 ",A2901 LM2901 AN6912
Quad Comparator-
lM239 LM239 LM239 ",A239 LM239
LM3302 LM3302 ,..A3302 LM3302

c8 SAMSUNG SEMICONDUCTOR 64
LINEAR ICs CROSS REFERENCE GUIDE
6. TIMER
Description SAMSUNG MOTOROLA NATIONAL SIGNETICS TI Others

NE555 MC1455 LM555 NE555 NE555 TA75555

Single Timer
tKS555H TLC555
KS555 ICM7555
NE556 LM556 NE556 NE556
Dual Timer
tKS556 TLC556 ICM7556
Quad Timer

7. DATA CONVERTER ICs

Application
tNE558

SAMSUNG NATIONAL TI
NE558

I
INTERSIL ITT Others

UVC31 00
tKSV3100A
UVC3100
A/D·D/A Converter
KSV3100A
ttKSV3110
up·date version
High-Speed 8·Bit AID ttKSV3208
tKAD0808l9 A DC0808/9 ADC0808J9
8·Bit AID Converter
ttKAD0820 ADC0820 ADC82A
TSC7126
3·1/2 DMM AID KS7126
ICL7126
4·Bit Triple
ttKSV3404
D/A Converter
DAC82
ttKDA0800 DAC0800
8·Blt D/A Converter DAC08
ttKDA0808 DAC0808 AD1408 MC1408
ttKS25C02 OM 2502
SAR. ttKS2503 DM2503
ttKS2504 DM2004

8. MISCELLANEOUS ICs
Application SAMSUNG SEGNETICS NATIONAL MITSUBISHI NEC Others

KA2303 3 Function
Toy Radio tKA2304 2 Function
Control Actuator ttKA2307 5 Function .(RX)
ttKA2308 5 Function (TX)
KA2401 ",PC1470H

DC Motor Speed tKA2402 AN6612 *LA5521D

Controller KA2404 AN6610 ",PC147QH
ttKA2407 *AN6651
Earth Leakage
KA2803 LM1851 ·M54123 A7390
Detector"
Zero Voltage SW KA2804 *",PC1701C

t New Product tt Under Development * Direct Replacement

c8 SAMSUNG SEMICONDUCTOR 65
LINEAR ICs ORDERING INFORMATION

KSV 3100A C N A+

~T BURN-IN (OPTIONAL)
(SEE BURN-IN PR~GRAM) .

PACKAGE TVP,E

L-----------------TEMPERATURERANGE

'---------------------------DEVICE NUMBER AND SUFFI~ (OPTIONAL)

A: IMPROVED VERSION

'------------------------------------ DEVICE FAMILY

TEMPERATURE RANGE PACKAGE TYPE

BLANK SEE INDIVJDUAL S'PEC CODE PKG.TYPE
C COMMERCIAL 0 - + 70°C D SOIC
J CERAMIC DIP
I INDUSTRIAL - 25 - + 85°C
-40-+!WC N PLASTIC DIP (300/600 mil)
S SIP
M MILITARY -55 -+125°C
0 FOP
E SD (400 mil)
SSD (Skinny Shrink DIP)
B (400 mil. Small Pitch)
SHD (Shrink DIP)
P (300 mil. Small Pitch)
INTEGRATED CIRCUIT W ZIP
U PGA
KA LINEAR IC
L LCC
KS CMOS IC PL PLCC
KT TELECOM IC M TO-3
LM NATIONAL H TO-3P
MC MOTOROLA Z TO-92
V TO-92L
NE S[GNETICS
A TO-126
KSV A/D-DIA CONVERTER
T TO-220
KAD AID CONVERTER X TO-247
KDA D/A CONVERTER G BARE CHIP

c8 SAMSUNG. SEMICONDUCTO~ 66
 ,/

"~t,:;,?'hl~rP\i~~0~ :~,"/;; ,
ft
PRODUCT INDEX (Continued)

3. Telecommunication Application

Device Function Package Page

KA2410 Tone Ringer 8 DIP 69

KA2411 Tone Ringer 8 DIP 69
. KA2412A Telephone Speech ·Circuits 14 DIP 75
KA2413 Dual Tone Multi Freque~cy Generator 16 DIP 83
KA2418 Tone Ringer with Bridge Diode 8 DIP 108
KA2419 Tone Ringer with Bridge Diode 8 DIP 108
KA2425A1B Telephone Speech Network with Dialer Interface 18 DIp· 112
KS5805A1B Telephone Pulse Dialer with Redial 18 DIP 130
KS5808 Dual Tone Multi Frequency Dialer 16 DIP 146
KS5812 Quad Universial Asychronous Receiver and Transmitter 40 DIP 152
KS5819 Tone/Pulse Dialer with Redial 22 DIP/SDIP 162
KS5820 Tone/Pulse Dialer with Redial 18 DIP 172
KS5821 Tone/Pulse Dialer with Redial 22 DIP/SDIP . 162
KS5824 Universial Asychronous Receiver and Transmitter 24 DIP . 180
KT3040J PCM Monolithic Filter 16 CERDIP 191
KT3054J COMBO CODEC 16 CERDIP 200
KT3064J COMBO CODEC 20 CERDIP 214
KT5116J ,...Law Companding CQDEC 16 CERDIP 226
LM587C Tone Decoder 8 DIP/8 SOP 239
LM587L Micropower Tone Decoder 8 DIP/8 SOP 247
MC1488 Quad Line Driver 14 DIP/14 SOP 257
MC1489/A Quad Line Receiver 14 DIP/14 SOP 264
MC3361 . Low Power Narrow Band FM IF 16 DIP/16 SOP 270
KA2580A 8-Channel Source Drivers 18 DIP 599
KA2588A 8-Channel Source Drivers 20 DIP 599
KA2651 Fluorescent Display Drivers 18 DIP 604
KA24101KA2411 LINEAR INTEGRATED CIRCUIT

TONE RINGER
8 DIP
The KA2410iKA2411 is a bipolar integrated circuit designed for telephone
bell replacement.

.FUNCTIONS
• Two oscillators
• Output amplifier
• Power supply control circuit

FEATURES
• Designed for telephone bell replacement
• Low current drain.
• Small size 'MINI DIP' package.
• Adjustable 2-frequency tone.
• Adjustable _rbling rate. •
• Built-In hysteresis prevents false triggering and rotary dial
'CHIRPS'
• Extension tone ringer modules
• Alarms or other alerting devices.
• External triggering or ringer disable (KA2410).
• Adjustable for reduced supply initiation current (KA2411)

APPLICATION CIRCUIT 1·(KA2410)

o--t bC:T'1."".,.,..---,
. O.9~F

100K-200K ohm

C.
22,.FI35V

R2

165K±1%

C2
o.47pF±5%

Note: 1. Output amplifier

2. High frequency oscillator.
3. Low frequency oscillator
4. Hysteresis regulator
Fig. 1

c8 SAMSUNG SEMICONDUCTOR 69
KA2410/KA2411 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Ta =25°C)

Characteristic Symbol' Value Unit

Supply Voltage Vee 30 V

Power Dissipation Po 400 rrm
Operating Temperature Top' -45 to 65 °C
Storage Temperature TS!lI -65to 150 DC·

ELECTRICAL CHARACTERISTICS (Ta 25°C) =

(All voltage referenced to GND unless otherwise specified)

Characteristic Symbol Test Condition Min Typ Max Unit

Operating Supply Voltage Vee 29.0 V

Initiation Supply Voltage l VSI See Fig. 2 17 19 21 V
Initiation Supply Current l lSI KA2411-6.8K-Pin 2 to GND 1.4 2.5 4.2 mA
Sustaining Voltage2 Vsus See Fig. 2 9.7 11.0 12.0 V
Sustaining Current2 Isus No Load Vee=Vsus, See Fig. 2 0.7 1.4 2.5 mA
Trigger Voltage3 VTA KA2410 Only Vee =15V 9.0 10.5 12.0 V
Trigger Current3 ITA KA24100nly 20.0 10005 pA
Disable Voltage' VDlS KA24100nly 0.5 V
Disable Current' lOIs KA24100nly -40 -50 pA
Vee=21V, la=-15mA
Output Voltage High VOH 17.0 19.0 21.0 V
Pin 6=6V, Pin 7=GND
Vee=21V,la=15mA
Output Voltage LOw VOl 1.6 V
Pin 6=GND, p'in 7=6V
liN (Pin 3) Pin 3=6V, Pin 4=GND - - 500 nA
liN (Pin 7) Pin 7=6V, Pin 6=GND - - 500 nA
High Frequency 1 fHl R3=191K,C3=68oopF 461 512 563 Hz
High Frequency 2 fH2 R3=191K,C3=6800pF .576 640 704 Hz
Low Frequency fL R2 =165K, C2 =0.47"F 9.0 10 11.0 Hz

• NOTE (see electrical characteristics sheet)

1. Initiation supply voltage (Vs~~ is the supply voltage required to start the tone ringer oscillating.
2. Sustaining voltage (Vsus) is the supply voltage required to maintain oscillation.
3. VTA and irA are the conditidhs applied to trigger in to start oscillation for Vsus ~Vee ~VSI
4. VOIS and lOIS are the conditions applied to trigger in to inhibit oscillation for VSI~Vee
5. Trigger current must be limited to this value externally.

c8 SAMSUNG SEMICONDUCTOR 10
KA2410/KA2411 LINEAR INTEGRATED CIRCUIT

CIRCUIT CURRENT-5UPPLY VOLTAGE (No Load)

4.0

3.5

~3.0
B
12.5
.iI
;t2.o
S V
.II ,.5 i-'"

II
~
,.0

0.5

10 14 18 22 26 30 34
Vee (V), Supply """ge

Fig. 2

APPLICATION NOTE
The application circuit illustrates the use of the KA2410/KA2411 devices in typical telephone or extension tone ringer
application.
The AC ringer signal voltage appears across the TIP and RING inputs of the circuit and is attenuated by capacitor C, and
resistor R,.
C, also provides isolation from DC voltages (48V) on the exchange line.
After full wave rectification by the bridge diode, the waveform is filtered by capacitor C4 to provide a DC supply for the tone
ringer Chip.
As this voltage exceeds the initiation voltage (Vsl),osciliation starts.
With the components shown, the output frequency chops between 512 (f~,) and 640Hz·(fh2) at a 10Hz (fl ) rate.
The loudspeaker load is coupled through a 13000 to 80 transformer.
The output coupling capacitor Cs is required with transformer coupled loads.
When driving a piezo-ceramic transducer type load, the coupling C 5 and transformer (13000: 80) are not required.
However, a current limiting resistor is required.
The low frequency oscillator oscillates at a rate (fl ) controlled by an external resistor (R2) and capacitor (C2).
The frequency can be determined using the relation fl =111.289 R2 • C2. The high frequency oscillates at a fH" fH2 controlled
by an external resistor (R3) and capacitor (C3). The frequency can be determined using the relation fHI=111.504 R3. C 3.
fH2=1/1.203 R3 , C 3 • .
Pin 2 of the KA2411 allows connection of an ex~ernal resistor RSl , which is used to program the slope of the supply cur-
rent vs supply voltage characteristics (see Fig 4); and hence the supply current up to the initiation voltage (Vsi). This initia-
tion voltage remains constant independent of Rsl .
The supply current drawn prior to triggering varies inversely with RSl.· decreasing for increasing value of resistance. Thus,
increasing the value of RSl• will decrease the amount of AC ringing current required to trigger the device. As such, longer
sucribser loopS are possible since less voltage is dropped per unit length of loop wire due to the lower current level. RSl
can also be used to compensated for smaller AC coupling capacitors (Cs on Fig 3) (higher impedance) to the line which can
be used to alter the ringer equivalence number of a tone ringer circuit.
The graph in Fig. 4 illustrates the variation of supply current with supply voltage ofthe KA2411. Three curves are drawn to
show the variation of i~itiation current with Rsl . Curve B (RSl =6.81<) shows the I-V characteristic for the KA2411 tone ringer.
Curve A is a plot with RSl <6.8KO and shows an increase in the current drawn up to the initiation voltage Vsi. The W charac,
teristic after initiation remains unchanged. Curve C iIIurates the effect of increasing RSL above 6.8K Initiation current decreases
but again current after triggering is unchanged.

c8 SAMSUNG SEMICONDUCTOR 71
KA2410/KA2411 LINEAR INTEGRATED CIRCUIT

APPLICAnQN CIRCUIT 2 (KA2411)

8 I------U-_.__----.
101(0
VOL
...---+---+------0----1 2
KA2411

2'JV
Ro--+----'

RSL

c.

Fig. 3

LINEAR INTEGRATED CIRCUIT

KA2411 Supply Current (No Load) Vs. Supply Voltage

1-1- ---- -- , -- ,- -
75

as

.. A)R".SKO I :
I ,
2.5
8) R,.-& iKcr.-1/ •
C)R... 'Sko ) I ~,
,
1.1;

o.s
~
i41i~
• ,
;"'1-
~
610141822263034
Supply _go (V)

Fig. 4,

,c8 Sj'MSUNG SEMICONDUCTOR ,72

KA2410/KA2411 LINEAR INTEGRATED CIRCUIT

EQUIVALENT CIRCUIT INHIBITING OSCILLATION

(Pin 2 Input)
+Vcc

KA2410

Pin 2

O<Vo<O.5V
V[).\/I
10= - - .. 40pA
RI

Fig. 5 Fig.S

PROGRAMMING THE KA2410 INITIATION SUPPLY VOLTAGE

+VCC . Vsi

vz
RE

RE

VT
VT

VSI =VT +VZ +20RE

Vcc-11.5 (REin MO)
20K ohm< RE< - - Mohm
10

Fig. 7 Fig. 8

c8 SAMSUNG SEMICONDUCTOR 73
KA2410/KA2411 LINEAR INTEGRATED CIRCUIT

TRIGGERING KA2410 FROM CMOS OR TTL LOGIC

+1210 +24V
+12 to +15V

+5V
SOK
5
10K
Ring'T'
Inhibil "H"
KS74HCTLS06 KA2410

Fig. 9 Fig. 10

cIS ~AMSUNG SEMICONDUcrOR 74

KA2412A LINEAR INTEGRATED CIRCUIT

TELEPHONE SPEECH CIRCUITS

14 DIP
The KA2412 A! is designed for replacement of the hybrid circuit (2 - 4
wire interface) in conventional telephone.

FEATURES
• Adjustable sending and receiving gain to compensate for line
attenuation by sensing the line current.
• The same type of transducer can be used for both transmitter
and receiver, usually a 3500 dynamic type.
• Output impedance can be matched to the line, independent of
transducer impedance.
• Minimum number of external parts required
• Parallel operation with pulse dialer IC (KS5805A/B,
KS5806) as well as DTMF IC (KA2413, KS5808)
I
BLOCK. DIAGRAM

r---'
I r+--------------------~~
I
I
I
I
I
I
I
I
I
I
I
I

I
I ____
L ~

Fig. 1

c8 SAMSUNG SEMICONDUcrPR 75
KA2412A LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Ta =25°C)

Characteristic Symbol value Unit '

Line Voltage
VL 22 V
(3 msec pulse duration)
Forword Line Current tF 120 mA
Reverse Line Current ILA -150 rnA
Power Dissipation Po 1.0 W
Operating Temperature Topr -20-+70 OC
Storage Temperature Tota -55-+150 OC

ELECTRICAL CHARACTERISTICS
(T.=:"'15OC- +45OC, f=300Hz-3400Hz unless otherwise specified. Referto the test circuit.)

' Test
Characteristic Symbol Test Conditions Min ~p Max Unit
Circuit

t-80mA 10.0 11.5

Line Voltage VL Fig 2 t=20mA 5.0 5.8 V
t=10mA 3.8 4.6
T.=25°C, f= 1KHz
IL=10mA 46.5 50.5
Sending Gain Gs Fig 3 t=2OmA 46.5 50.5 dB
IL=60mA 39.0 43.0
t=80mA 39.0 48.0
Sending Gain Variation vs temp .1Gsr Fig 3 -15°C<Tamb< + 45°C ±0.8 dB
Gs=OdB at f-1KHz
.Sending Gain Flatness .1GsF Fig 3 ±0.5 dB
t .. 10-80mA
t=20mA
2.0 %
Vso= 1Vp.p
Sending Distortion THDs Fig 3
IL=80mA
2.0 %
Vso= 400mVrms
Sending Noise VNs VM1=O, t=60mA 130 p.V
IL=10
Maximum Sending Output Vs(max) Fig 3 6.0 Vp.p
VM1 = 707mVrms
T.=25°C,f=1KHz
IL=10mA -12.6 -10.4
Receiving Gain GR Fig 4 t=20mA )
-12.6 -10.6 dB
t=60mA -19.9 -17.4 '
t=80mA -20.1 -17.4
Receiving Gain variation vs temp .1GRT Fig 4 -15OC<Tamb< 450C ±0.8 dB
Gil .. OdB at f=1KHz
Receiving Gain 'Flatness .1GRF Fig 4 ±0.5 dB
IL=10-SOmA

c8 SAMSUNG SEMICONDUCTOR 76
 KA2412A -LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS (Continued)

(T. = -15"C - +45°C, f=300Hz - 3400Hz, unless otherwil!e specified refer to the test circuit)

Test
Characteristic Symbol Test Conditions Min lYP Max Unit
Circuit
IL=20mA-SOmA
Receiving Distortion THOR Fig 4 2.0 %
VRO =200mVrms
VRI =OV, Ie =60mA
Receiving Noise VNR Fig 4 75 p.V
Posphometric
IL=10mA
Max Receiving Output Current 10m 2.0 mA
VRI =707mVrms
f=1KHz, T.=25°C
5ideTone ST Fig 5 IL=20mA 7.0 dB
IL=60mA 0.0
52ina 14
Return Loss RL Fig 6 dB
52inb 14

PIN DESCRIPTION
1. PIN 1, PIN 14 : Recevier output
2. PIN 2: Line impedance adjust
3. PIN 3 : Ground
4. PIN 4 : DC regulator
5. PIN 5 : Bias
6. PIN 6 : AC loop opening
7. PIN 7 : No connection
S. PIN 8 -: No connection .
9. PIN 9, PIN 10: Mic input
10. PIN 11 : InputreceiveAmp(-)
11. PIN 12: Input receive Amp (+)
12. PIN 13: Vee

c8 SAMSUNG SEMICONDUCTOR n
<f KA2412A LINEAR INTEGRATED CIRCUIT

TEST GIRCUIT
~------------------~
100nF

4.22K!I

7511

22nF
E 1--+_IoIP--+------,
.1000

KA2412A
RECEIVER

F }--+_w--f-----I
1000

LINE

Fig. 2
Sending Gain Receiving Gain

350

VRO
GR=--
VRI
VSO
GS=-
VM1
Fig. 4

Side Tone Return Loss

30nF

VRO
Sldelons=-
VMI
35011
Fig. 6

c8 SAMSUNG SEMICONDUCTOR 78
KA2412A LINEAR INTEGRATED CIRCUIT

APPLICATION INFOMRATION
The following table shows the recommended for the Fig 1. Different values can be used and notes are added in order to
help designer.

Recommended
Component Purpose Note
value

R, 2.05K Balance network In order to optimize the sidetone

it is possible to change R, and R2
R2 9.09K
values. In any case:
Ze. = Rs
Rs where Ze=R, +RJIC.

I
ZL
---- -
R3 16.2K Bias resistor Changing R3 value, it is possible to
shift the gain characteristics. The
value can be chosen from 15K to 20K.
The recommended value assures the
maximum swing
-
Rs 536 The ratio Rs/R. fixes the amount of
Bridge resistors
R. 75 the signal delivered to the line.

Receiver impedance R7 and R7' must be equal; 1000 is a

R7, R7' 100
matching typical value for dynamic capsules
Rs, Rs' 250 Microphone impedance Rs and Rs' must be equal; 2500 is a
matching typical value for dynamic capsules.
Furthermore, they determine a sending
gain variation according to;
Rx
Gs =2010g
850
where Rx =As +Rs' +RMIC
C, 10uF AC loop opening Ensures a high regulator impedance for
AC signals (=20KO). This capacitor
should not be higher than 10uF in order
to have a short response time of
the system.
DC decoupling for
C2 1uF
receiving input
High frequency C3 determines the high frequency
C3 82nF
roll-off response of the circuit.
It also acts as RF by pass.
C. 22nF Balance network See note for R, and R2

c8 SAMSUNG SEMICONDUCTOR 79
KA2412A' LINEAR INTEGRATED CIRCUIT

,DESCRIPTION
1. Circuit Description:

The KA2412A is based on a bridge configuration. The KA2412A contains a regulator block, a sending amplifier and a receiv-
ing amplifier. The regulator monitors the line current and adjusts the amplifier gain to compensate for the line length.
The transmiUreceiver amplifiers are connected to the line via an external bridge to provide side tone attenuation. When
the subscriber Is talking, A controlled amount of the sending signal is allowed to reach the receiver to give a feedback to the
subscriber. The phenomenon is caused by mismatching of the wheastone. bridge and is called the signal of side tone.
The line current compensation ensures that when ·the subscriber is talking, the signal delivered to the line is increased
in according to the line length. When he is hearing, the signal level on the receiver capsule is constant.
Gain variation over the operating temperature range is less than ±1dB. The impedance to the line can be adjusted; without
any change in circuit parameters; by changing an external resistor (6.8KO at Pin 2).
The KA2412A works with the same type of transducers for both transmitter and receiver (typically 3500 Dynamic units).

2. Two to four wires conversion

1) In the case of the traditional telephone set: .

microphone

receiver
Fig. 10

A treditional speech circuit is equivalently equal to the circuit as described in Fig. 7. The microphone is cOmposed of carbon
powder. it converts the sound presure into the variation of resistance and so a AC Signal is generated when the bias current
flows through the microphone and a subscriber is talking. The current actuated by microphone does not affect receiver because
it Is compensated by the coil polarity.
But the incoming signal is transferred to receiver, so and this circuit is called 2 - 4 wires conversion, which is incoming
2 wires and Mic, Receivers 4 wires.

c8 SAMSUNG SEMICONDUCTOR 80
KA2412A LINEAR INTEGRATED CIRCUIT

2) In the case of the KA2412 A

KA2412A performs the two wires (Telephone line) to four wires (Microphone, Receiver) conversion by means of a wheastone
bridge configuration so obtaining the proper decoupling between sending and receiving signals (see Fig. 8)

RECEIVER

4
I
+

Mic

Fig. 8

Z R5
For a perfect balancing of the bridge Z~ = R6

• In sending lTiode;
The N:; signal from the !T1icrophone is sent to one diagonal of the bridge (pin 3 and pin 4). A small percentage of the signal
power is lost on Ze (being Ze> >Zt.); the main part is sent to the line Via R6.
The imPedance At. is defined as.fu
1..3

V (R6+Ze)II(R5+Zt.) (~
R= ~+(R6+ZB)II(R5+Zt.) R6+Zt

To reduce the receiving input Signal,

also, In order to reduce power loss in R5 & Ze and to transfer the maximum power to the line via R6.

R5+ZB> >R6+ZL
R6+ZM=ZL

c8 SAMSUNG SEMICONDUCTOR 81
KA2412A LINEAR INTEGRATED CIRCUIT

Then the line impedance ZL grows lrom SOO ohm up to 900 ohm when the line length Increases. '
The voltage driven to the line is

V - ZL x'"
L - RS+Zu +4 _IT

In order to maximize sending Gain

ZL»RS

Therefore, in the case 01 the KA2412 test circuit:

RS= 75, ZM =S.8K111, ZL =SOO

·VL .. 4 Z xZuh=28S.82h
Zu+R8+ L

• In receiving mode: ' ,

The J!C signal coming from the line is sensed across the secon<!l diagonal of the wheastone bridge (pin 11 and pin 13).
Alter amplification it is applied to the receiver.

VR - V, (Re +Rs + Za)/lZu (1- ~»

ZL+Ra+(Rs+Za)/lZM ' Za+Rs

V, . (Ra+ ZuRs )
4+Rs+(Rs+Za)/lZM Zu+Rs+Ra
To avoid the reflection
4=Re+Zu,10ZM",Rs +Za
Therefore

VR = V, (Re+~
2 Re +1.91 Zu 11
In the case 01 the KA2412A test circuit
4-6000, Rs=750, Zu=6.8KO/11=S.80
Rs=536O, Za=S.076KO (fREF=1KHz)
VR
,-=0.Q93
V,

3. Automatic Gain Control.

The KA2412A automatically adjusts the gain 01 the sending and receiving amplifiers to compensate lor line attenuation
Maximum gain is reached for a Iinecurrent 01 range 10 - 20mA and minimum gain can also be reached for a line current
01 range 60 - 100mA. "

c8 SAMSUNG SEMICONDUCTOR 82
KA2413 LINEAR INTEGRATED CIRCUIT

DUAL TONE MULTI FREQUENCY GENERATOR

18 DIP
The KA2413 is a monolithic integrated DrMF generator designed for use
in a telephone set in parallel with an electronic speech circuit. The DC
characteristic to the line is set ~ the speech circuit.

FEATURES
• Wide operating line voltage and current range
• Operates with a standard crystal at 3.58MHz
• Operates with a single contact or matrix key-board
• Levels from the high and loIN frequency group can be adjusted
aeparately.
• No individual level adjustment Is neceasary for every circuit
• The signal levels are stabilized against variations in tempera-
ture and line voltage.
• Short start-up time
• All tones can be generated separately for testing.
• Easy PCB layout; all keyboard connections on one side of the
chip
• Internal protection of all inputs
• Minimum number of external parts required.

BLOCK DIAGRAM

Mute

Rl
1-----( I}-t--'W\r-1r--o T
330

Rl C24.7nF
47KIl Line

Cl3.3nF

~--------~-------*----~----~--oR

Fig. 1

c8 SAMSUNG SEMICONDUCTOR 83
KA2413 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Ta =25°C)

Characteristic Symbol Value Unit

!p=2 sec 20 V
Line Voltage (Peak) VL (peak)
!p=20msec 22 V
Line Voltage (Conditions) VL (cont) 15 V
Power Dissipation Po 400 mW'
Operating Temperature Topr -20- +70 °C
Storage Temperature Tstg . -55- +150 °C

ELECTRICAL CHARACTERISTICS (Ta =25°C)

(VL =4.3 - 9V, unless otherwise specified)
"

Characteristic Symbol Test Conditions Min Typ Max Unit

Tone Generation
Operating Line Voltage VL(opr) 4.3 9.0 V
1.3 Vp Signal
Stand-By
Stand-By Line Voltage VL (std) 4.3 9.0 V
2.0 Vp Signal
Operating Line Current IL (opr) VL=4.3V 10.0 mA
No Key Pressed
Stand-By Line Current t (SId) 250 pA
VL=4.3V
Mute Current 1M One or More Keys Pressed 125.0 pA
Key Resistance RK Key Circuit Closed 1.0 kG
Tone Output Frequency
f,=697Hz -1.0 -0.32 . +1.0 %
Low f2=770 Hz -1.0 +0.02 +1.0 %
(Row) fa =852 Hz -1.0 +0.03 +1.0 %
f.=941 Hz Af fosc=3.5795 MHz -1.0 -0.11 +1.0 %
f 5 -1209 Hz -1.0 -0.03 +1.0 %
High f6=1336 Hz -1.0 -0.03 +1.0 %
(Column) f7=1477 Hz -1.0 -0.68 +1.0 %
., f6=1633 Hz -1.0 -0.36 +1.0 %

c8 SAMSUNG SEMICONDUCTOR 84
KA2413 LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS (Continued)

Characteristic Symbol Test Conditions Min Typ Max Unit

High VH RH=46.4KO -9.0

dBm
Low Vl Rl =69.8KO -11.0

Signal High VH RH=33.0KO -8.0 -6.0 -4.0

dBm
level Low Vl Rl =47.0KO -10.0 -8.0 -6.0
High VH RH=26.1KO -4.0
dBm

I
Low Vl Rl =39.2KO -6.0
Ratio Signal Level VHNl 1.0 2.0 3.0 dB
Tone Generation 6.0
Impedance to Line Zl KO
Stand-By 50.0
Total Harmonic Distortion THD Tone Generation -31.0 dBm
Output Noise VNO Stand-By -80.0 dBm
300-3400Hz -33.0 dBm
Harmonics 3.4-50KHz -33.0 dBm
",50KHz -80.0 dBm

Start-up Time Output level within 3 5

ts mS
1dB from final level

R1
TEST CIRCUIT
3311

RlOAO
30011

Vl

1M

C2
4.7nF

MUTE
+

Rl
RH
33KIl
. 47KII

. Fig. 2

c8 SAMSUNG SEMICONDUCTOR 85
 KA2413 LINEAR INTEGRATED CI~CUIT

• Component function:
R1: Protecting resistor
RL: Signal Level (Low), RH: Signal Level (High)
C1: Low pass filter
C2: Radio frequency suppression

• To find suitable resistor values for RH and RL to get the desired tone levels the following formula can be used for a
preliminary calculation.
Note that in RLolid (f=1.4KHZ) and RLoa(f.{f=800HZ) both the impedance of the line and the impedance of the speech
circuit are include. VH and VL are the desired high and low frequency levels, in dBm
YH
RH -56.2xRIDAD (f=1.4KHi) x.10- 20"

Y.
RL=65.2xRLOAO (f=800Hz)b<10"2O"

• The current consumption within KA2413 cim be reduced with a resistor connected in parallel with C1. (see Fig. 3)
If the current reduction is made too large, the output signal can be distorted by Clipping.
- - - - ------:.. --------- ---- -------- - - --
pinS

0.3M-3MO c.

Fig. 3
• In application where a DTMF generator directly powered from the telephone line is wanted (the generator is not
working in parallel with any kind of speech network),KA2413 can be used with a DC regulator as described in fig 4.
This schematic gives a DC regulator for the range 16 - 100mA.

DC regulator schematic

<r ,;. +
1K' ~~5B1
KA2413. KSC1()()9.Y
As In Fig. 3

1800

470
=~ 22,.F

(~
" v
DC Regulator
,
-
Fig. 4

c8 SAMSUNG SEMICONOUCl'OA 86
KA2413 LINEAR INTEGRATED CIRCUIT

• KA2413 can also be controlled by a microprocessor (see Fig 5). The negative branch of the microprocessor- voltage
supply is connected to pin 7 of KA2413 and the inputs (8) are connected with resistors.
For tone-generating one input of the low group (pin 13 - 16) is connected to the positive voltage and one input of
the high group (pin 9 - 12) is connected to the negative voltage, then KA2413 is activated and the mute output is put
in High state.

Microcomputer interface

R9
9
I
R10
10
R11
11
R12
12
microprocessor R13 KA2413
13
R14
14
R15
15
R,1!
16

I 1
Fig. 5

1) R9, R10, R11, R12 (ooK - 80K)

The resistorS have two functions are:
- To raise the OFF/ON voltage
- To limit the current when the input levels are high. Too high current will interfere with the functions of the other
three inputs (the resistors can be exchanged with diodes directly away from KA2413)

High-frequency group resistors to microcomputer

TOO1her
Inputs (3)

one of I
R9-R12 12
microprocessor

---+:J------:

Fig.6 '.

c8 SAMSUNG SEMICONDUCTOR 87
KA2413 LlENAR INTEGRATED CIRCUIT

2) R13, R14, R15, R16 (20K - 3OK)

The two functions of the resistors are:
- To raise the OFF/ON voltage
- To limit the current when the input levels are high.

Low-frequency group resistors for microcomputer

I
I. I
I
I
I
1
131 KA2413
MICROPROCESSOR I
141 lK
oneot I
R13-R1S 151

16 I
"I : (2-10),.A
1 I
1 I
I I

------- -m----~
I I
L _______________________________ _

Fig. 7

c8 SAMSUNG SEMICONDUC1'OR 88
KA2414/KA2417 (DELETIO~ LlNEARlI2L INTEGRATED CIRCUIT

ONE CHIP TELEPHONE

40 DIP
The KA2414/KA2417 eleCtronic telephone circuits (ETC) provide all the
necessary elements of a tone dialing telephone in a Single IC. The func-
tional blocks of the ETC include the DTMF dialer, speech network, tone
ringer, and.DC line interface circuit (Fig. 1). The KA2417 also provides
a microprocessor interface port that facilitates automatic dialing features.
Low voltage operation is a necessity for telephones in networks where
parallel telephone conneClions are common. An electronic speech net-
work operating in parallel with a conventional telephone may receive line
voltage below 2.5 volts. DTMF dialers operate at similary low-line voltages
when signaling through battery powered station carrier equipment.
These low voltage requirements have been addressed by realizing the
KA24141KA2417 in a bipolarll"L technology with appropriate circuit tech-
niques. The resulting speech and dialer circuits maintain specified per-
formance with instantaneous input voltage as low as 1.4 volts.
II
FEATURES
o Provides all basic telephone station apparatus functions in a single
IC, including DTMF dialer, tone ringer, speech network and line
voltage regulator.
o DTMF generator uses Low-Cost ceramic resonator with accurate
frequency synthesis technique.
o Tone ringer drives piezoelectric transducer and satisfies EIA RS-
470 impedance signature requirements.
o Speech network provides two-four wire conversion with adjustable
sidetone utilizing an electret transmitter.
o On-cl\ip regulator insures stable operation over wide range of loop
lengths.
o 12L technology provides low 1.4 volt operation and high static dis-
charge immunity.
o KA2417 provides microprocessor interface port for automatic Hook Switch
dialing features.

/--~
Piezo
Sound

BLOCK DIAGRAM
Tip

1 2 3 A
4 5 6 B Tone
7 8 9 C Ringer
0#0
Line
Keypad Voltage I-+----<j~-+
Regul- Ring
ator
Interiace Speech
MPU (KA2417 Network
,only)

Receiver

Electret
Microphone

ciS SAMSUNG SEMICONDUCTOR 89

KA24141KA2417 (DELETION) LlNEARII2L INTEGRATED CIRCUIT

ABSOWTE MAXIMUM RATINGS (Ta =25°C)

Characteristic Symbol Value Unit

V' Terminal Voltage (Pin 34) Vee -1.0- +18 V

VR Terminal Voltage (Pin 29) VR -1.0- +2.0 V
RXO Terminal Voltage (Pin 27) RXO -1.0- +2.0 V
TRS Terminal Voltage (Pin 37) TRS -1.0-+35 V
TRO (with Tone Ringer Inactive
TRO -1.0- +2.0 V
Terminal Voltage)
R,-A. Terminal Current (Pins 1-4) IR ±100 mA
C,-C. Terminal Current (Pins 5-8) Ic ±100 mA
er:,10;/00.110. A+ (KA2417 Only)' -1.0- +12. V
Operating Ambient
Temperature Range
Topr -20- +60 OC
Storage Temperature Range Tstg -65- +150 °C

ELECTRICAL CHARACTERISTICS
(T.=25OC. Vee-5V Unless Otherwise Specified)
KEYPAD INTERFACe CIRCUIT

Characteristic Symbol Test Conditions Min lYP Max Unit

Row Input Pullup Resistance

RRM 5.0 8.0 11 KO
m'" Row Terminal: m=1. 2. 3, 4
Column Input Pulldown Resistance
RCN VI=1.0V 5.0 8.0 11 KO
nth Column Terminal: n=1, 2. 3, 4
Ratio of Row-to-Column
KM.N 0.88 1.0 1.12 K(l
Input Resistanc;:e
. RRM m-1. 2. 3, 4
~N=-
RCN n=1. 2. 3, 4
Row Terminal Open Circuit Voltage VROC 950 1100 1200 rmloc
Row Threshold Voltage for mth Decrease from V,=1.ov to
Row Terminal: m=1. 2. 3, 4
VRM
O.7VROC
O.7VROC - - V

Column Threshold Voltage for nth. Increase from VI ..OV to

Column Terminal: n-1. 2. 3, 4
VCN
O.39VROC - - O.39VROC V

·VI: Input voltage of key board pins.

c8 SAMSUNG SEMICONDUCTOR 90
KA24141KA2417 (DELETION) LlNEAR/l2 L INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS (Continued)

MICROPROCESSOR INTERFACE (KA2417 only)

Characteristic Symbol rest Conditions Min 1'yp Max Unit

Voltage Regulator Output VR/A+ Vcc=O.SV 0.95 1.1 1.3 V

A+ Rgulator A+=2.4V
A+ Input Current Off-Hook IA (Off) Vcc"1.4V, A+=5V 50 150 JA
A+ Input Current On-Hook IA(On) Vcc=0.6IJ, A+=5V 4.0 6.0 9.0 mA
Input Resistance (DO, TO, Cl)

Input Current (I/O)

Input High Voltage (DO, TO, Cl, I/O)

RIN

liN

VIH
A+=5V
A+=5V,
V"o=OB<J, Voo='ZV
50

2.0
100

80
150

200

A+
KO

JA
V
II
Input Low Voltage (DD, TO, Cl, I/O) Vil 0.8 V
Output High Voltage (MS, DP, I/O) VOH A+=5V 2.4 4.0 V
Output Low Voltage (MS, DP, I/O) VOL A+=5V 0.1 0.4 V

LINE VOLTAGE REGULATOR

Characteristic Symbol rest Conditions Min 1'yp Max Unit

Voltage Regulator Output VR Vcc=1.7V 1.0 1.1 1.2 V

V+ Current in DTMF Mode lor Vcc =11.5V,R+ .. 6000 8.0 12 14.5 mA
Change in lor with
410T Vcc=11.5-26IJ, R+ .. 600 0.8 2.0 mA
Change in V+ Voltage
V+ Current in Speech Mode
V+=1.7V Isp 3.5 5.0 7.0 mA
V+=5DV 8.0 11 15 mAo
Speech to DTMF Mode Current V+=11.5V 2.0 .
4hR -2.0 3.5 mA
Difference R+=60Q0
lR Level Shift
V+=5.OV,llR =10mA 4VlR 2.4 2.9 3.5 V
V+=18V,llR=110mA 2.6 3.3 4.0 V
lC Terminal Resistance RLC 30 50 75 Kfl
V+=1.7v
Load Regulation 4VR
Isp =0-150pA
-20 -6.0 20 rrWN;

c8 SAMSUNG SEMICONDUCTOR 91
KA2414/KA2417 (DELETION) LlNEARlI2L INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS (Continued)

SPEECH NETWORK

Characteristic Symbol Test Conditions Min Typ Max Unit

MIC Terminal Saturation Voltage VMIC iMlc =500pA, VMM =0.8V - 6Q 125 mVoc
MIC Terminal Leakage Current IMlc VMM =2V, VMIC =1V - 0.0 5.0 pA
MM Terminal Input Resistance RMM VMM =5V . 50 100 170' KO
TXO Terminal Bias BTxo BTxo =VTxo +VR 0.48 0.53 0.68 -
TXI Terminal Input Bias Current ITXI ITXI = (VTXO-VTXI) + 200KO - 50. 400 nA
TXO Terminal Positive SWing VTXO(+) i TXI =-10pA - 25 60 mVoc
TXO Terminal Negative Swing VTXO (-) hXI=10pA 130 1200 mVoc
Transmit Amplifier Closed-Loop Gain GTX V, =3.0mVRMS 16.5 19 20 VN
Sidetone Amplifier Gain GSTA f=1.0KHz 0.40 0.45 0.54 VN
STA Terminal Output Current ISTA VSTA =0.3V 50 100 250 pA
AXO Terminal Bias BRxo BRxo=VRxo+VR 0.48 0.52 0.68 -
RXI Terminal Input Bias Current IRxl IRXI = (VRXO-VRXI) + 100KO - 100 400 nA
IRxl = -'10pA
RXO Terminal Positive Swing VRXO(+)
VRXO (+ )=VR-VRXO
- 1.0 20 . mVoc

IRxl =+10pA
RXO Terminal Negative Swing VRXO(-)
VRXO(-)=VRXO
- 40 100 mVoc

TXL Terminal Off Resistance Rm (Off) . VTXL =0.4Voc 125 200 300 KO
TXL Terminal On ReSistance RTXL (On) - 20 100 0
RM Terminal Off Resistance RRM(Off) VRM =0.4Voc· 125 180 300 KO
RM Terminal On Resistance RRM(On) 410 570 770 0

DTMF GENERATOR (V+=15V, R+=6000)

Characteristic Symbol Test Conditions Min Typ Max .Unit

Row Tone Frequency Row 1 fRI 692.9 696.4 699.9 Hz

Row 2 fR2 V+=15V 765.3 769.2 773.0 Hz
Row 3 fR3 R+=6000 848.9 853.2 857.5 Hz
Row 4 fRO 935.1 939.8 944.5 Hz
Column Tone Frequency Column 1 fCI 1201.6 1207.7 1213.7. Hz
GOlumn2 fC2 V+=15V 1330.2 1336.9 1343.6 Hz
Column 3 fC3 R+=6000 1471.9 1479.3 1486.7 Hz
Colomn4 fco 1625.2 1633.4 1641.5 Hz
Row Tone Amplitude VRCJoN V+=15V, R+=6000 0.38 0.45 0.55 VRMS
Column Tone Amplitude VC01 V+=15V, R+=6000 0.48 0.55 0.67 VRMS
Column Tone Pre-emphasis dBcR V+=15V, R+=6000 0.5 1.8 3.0 'dB
DTMF Distortion THD - 4.0 6.0 %
DTMF Output Resistance Ro VFs=1.8-2.8V 1.0 2.5 3.0 KO

c8 SAMSUNG SEMICONDUCTOR 92
KA2414/KA2417 (DELETION) LlNEARlI2L INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTCS (Continued)

TONE RINGER (VTRI =20V)

Characteristic Symbol Test Conditions Min lYP Max Unit

TRI Terminal Voltage VTAI hAC + hAS =1.0mA 20 21.5 23 Voc

TRS Terminal Input Current
VTRs =24V IrAS VTAI =20V 70 120 170 ~
VTRs =30V
TRF Threshold Voltage
TRF Threshold Hysteresis
TRF Filter Resistance
VTAF
t:.VTAF
RTAF
VTAI =20V
VTRI =20V
VTAF =21V, RTAF=1.0.;.hAA
0.4
1.2
100
30
0.8
1.6
200
50
1.5
1.9
400
75
mA
Voc
mVoc
KO
II
High Tone Frequency IH 920 1000 1080 Hz
Low Tone Frequency IL 736 800 864 Hz
Warble Frequency Iw 11.5 12.5 13.5 Hz
Tone Ringer Output Voltage Vo(p-p) VTAS =22V, VTAI =20V 18 20 22 Vp.p

TEST CIRCUIT

TRF

TAO

TRI

TAS

TRC

FB

v+

BP

LR

TO ~C

v-

A+ VR

I/O CAL

DO, (ES") RXO

CL,(EV") RXI

RM Notes:
CR'
1. "Selected ceramic resonator: 500KHz±2.0KHz
STA
2. Capacitances in I'F unless noted.
MM TXO 3 .. All resistances in ohms.
4 .. ""KA2414 only
AGC TXI

MIC

Fig. 2

c8 SAMSUNG SEMICONDUCTOR 93
KA24141KA2417'(DELETION) LlNEAR/l2L INTEGRATED CIRCUIT
PIN DESCRIPTION
(See Fig. 12 for external component identifications.)

, Pin DesIgnation Function

1-4 R1-R4 Keypad inputs for Rows 1 through 4. When open, internal8.0kO resistors pull up the rf1N inputs
to a regulated ( .. 1.11101t) supply. In normal operation, a rf1N and a column input are connected
through a SPST switch by the telephone keyped, Row inputs can also be activated by a Logic
"0" ( < 500mV) from a microprocessor port.
5-8 C1-c4 Keypad Inputs for Columns 1 through 4. When open, internalS.OkO resistors pull down the
column inputs to V-.ln n9rmal operation, connectin'g any column input to any row input
produces the I'$spective row and column DTMF tones. In addition to being connected to a
row input, column inputs can be activated by Ii Logic "1" (> 600mV and < 3.0 VOlt).
9 ,DP* Depressed Pushbutton (Output) - Normally low: A Logic "1" indicates one and only one,
button of the DTMF keypad is depressed.
10 m* Tone output (Input) When a Logic "1", disables the DTMF generator. Keypad is not
disabled.
1.1 MS* ' Mute/Single tone (Output) - A Logic "1" indicates a'row and/or column tone is being
generated. A Logic "0" indicates tone generator is disabled.
12 A+* MPU Power Supply (input) - Enables pullups 'on the microprocessor section outputs,
Additionally, this voltage will power the entire circuit (except tone Ringer) in the absence of
voltage at V--,
13 110* Input/Output - Serial Input or Output data (determined by DO input) to or from the
microprocessor for storing or retrieving telephone numbers. Guaranteed to be a Logic "1"
on powerup if 00= Logic "0".
14 00* Data Direction (Input) - Determines direction of data flow through 110 pin. As a Logic "1",
I/O is an input to the DTMF generator. As a Logic "0". I/O outputs keypad entires to the
microprocessor.
ES** Sidetorie Equalization terminal connects an external resistor between the junction of RS, R9
and V-, At loop currents greater than the equalization threshold this resistor is switched in
to reduce the sidetone level.
15 CL* Clock (Input) - Serially shifts data in or out of 110 pin. Data is transferred on negative edge
typically at 20kHz.
EV** Voice equalization terminal connecis an external resistor between V+ and V-, for loop length
equalization. At loop currents greater than the equalization threshold this resistor is switched
in by the equalization circuit to reduce the transmit and receive gains.
16,17 CR1,CR2 Ceramic Resonator oscillator input and feedback terminals, respectively. The DTMF dialer
is intended to operate with a 500kHz ceramic resonator from which row and coJumn tones
are synthesized.
28 CAL Amplitude CALibration terniinal for DTMF dialer. Resistor R14 from the CAL pin to V -
controls the DTMF output signal level at Tip and Ring.
35 FB Feed Back terminal for DTMF output. Capacitor C14 connected from FB to V+ provides ac
. feedback to reduce the output impedance to Tip and Ring when tone dialing.
29 VR Voltage Regulator output terminal. VR is the output of a 1.1 volt voltage regulator which
supplies power to the,speech network amplifiers and DTMF generator during signaling. To
improve regulator efficiency at low lin!l,current conditions, an external PNP pass-transistor
T1 is used in the regulator circuit. Capacitor C9 frequency compensates the VR regulator
to prevent o s c i l l a t i o n . '
33 BP Base of a PNP Pass-transistor. Under long-loop conditions where low line voltages would
cause VR to fall below 1.1-volts, BP drives the PNP transistor T1 into saturation, thereby ,
minimizing the voltage drop across the pass transitor. At line voltages which maintain VA'
above. 1.1 volts, BP biases T1 in the linear region thereby regulating the VR voltage. Transistor
T1 also couples the ac speech signals from the transmit amplifier to Tip anti Ring at V+.
*KA2417 only **KA2414 only

c8 SAMSUNG SE~ICONDUCTOR 94
KA2414/KA2417 (DELETION) LlNEARII2L INTEGRATED CIRCUIT

PIN DESCRIPTION (Continued)

(See Fig. 12 for external component identifications.)

Pin Designation Function

34 V+ The more positive input to the regulator, speech, andDTMF sections connected to Tip and Ring
through the polarity guard diode bridge.
30 V- The dc common (more negative input) connected to Tip and Ring through the polarity guard
bridge. ,
32 LR DC Load Resistor, ResiStor R4 from LR to V- determines the dc input resistance at Tip and Ring.
This resistor is external not only to enable programming the dc resistance but also to avoid high
on-chip power dissipation with short telephone lines. It acts as a shunt load conducting the excess
dc line current. At low line voltages « 3.0 volts), no current flows through LA.
31 LC DC Load CapaCitor. CapaCitor C11 from LC to V- forms a low-pass filter which prevents the resis-
tor at LR from loading ac speech and DTMF signals.
20 MIC Microphone negative supply terminal. The dc current from the electret microphone is returned
to V- through the MIC terminal which is connected to the collector of an on-chip NPN transis-
tor. The base of this transistor is controlled either internally by the mute signal from the DTMF
generator, or externally by the logic input pin MM.
18 MM Microphone Mute. The MM pin proVides a means to mute the microphone and transmit
amplifier in response to a digital control signal. When this pin is connected to a Logic "1" '
(> 2.0V) the microphone dc'return path through the MIC terminal is disabled.
22 TXI Transmit amplifier Input. TXI is the input to the transmit amplifier from an electret microphone.
AC coupling c<lpacitors allow the dc offset at TXI to be maintained approximately 0.6V above
V- by feedback through resistor R11 from TXO.
21 TXL Transmit Input Limiter. An internal variable resistance element at the TXL terminal controls the
transmitter input level to prevent clipping with high signal levels. Coupling capacitors C4 and
C5 preilent dc curent flow through TXL. The dynamiC range pf the transmit peak limiter is
controlled by resistors R12 and R13.
23 TXO Transmit Amplifier Output. The transmit amplifier output drives ac current through the voltage
regulator pass-transistor T1 via resistor R10. The dc bias voltage at TXO is typically 0.6 volts above
V-. The transmit amplifier gain is controlled by the R11/(R12+R13) ratio.
19 AGC Automatic Gain Control low-pass filter terminal. CapaCitor C3 connected between AGC and VA.
sets the attack and decay time of the transmit limiter circuit. This capacitor also aids in reduc-
ing clicks in the receiver due to hook-switch transients and DTMF on/off transients. In conjunc-
tion with internal resistors, C3 (1.01'F) forms a timer which mutes the receiver amplifier for
approximately 20 milliseconds after the user goes off-hook or releases a DTMF Key.
27 RXO Receiver Amplifier Output. This terminal is connected to the open-collector NPN output tran-
sistor of the receiver amplifier. DC bias current for the output device is sourced through the
receiver from VA. The bias voltage at RXO is typically 0.6 volts above the V-. Capacitor C10
from RXO to VR provides frequency compensation for the receiver amplifier.
26 RXI Receiver Amplifier Input. RXI is the input terminal of the receiver amplifier which is driven by
ac signals from V+ and STA.lnput coupling capacitor C8 allows RXI to be biased approximately
0.6 volts above the V- via feedback resistor R6.
25 RM Receiver Amplifier MU,te. A switched resistance at the RM terminal attenuates the receiver
amplifier input signal produced by DrMF dialing tones at V+, RM also mutes clicks at the receiver
which result from keypad or hook switch transitions. The ac resistance at RM is typically 5400
in the mute mode arid 200kO otherwide. Coupling capacitors C7 and C8 prevent dc current flow

.KA2417 only
through RM.
(continued)

c8 SAMSUNG SEMICONDUCTOR 95
KA2414/KA2417 (DELETION) LlNEARII2L INTEGRATED CIRCUIT

PIN DESCRIPTION (Continued)

(See Fig. 12 for external component identifications.)

Pin DesIgnation Function

24 STA Side Tone Amplifier output STA is the output of the sidetone inverter amplifier whose input is.
driven by the transmit signal at TXO. The inverted transmit signal from STA subtracts from the
receiver amplifier input current from V+. thus reducing the receiver sidetone level. Since the
transmitted signal at V+ is phase shifted with respect to TXO by the reactive impedance of the
phone line, the signal from STA must be similarly phase-shifted In order to provide adequate
sidetone reduction. This phase relationship between the transmit signal at TXO and the side-
tone cancellation signal from STA is contro)(~_ by R8, R9. and C6.
37 TRS Tone Ringer Input Sense. TRS is the most positive input terminal of the tone ringer and the refer-
ence for the threshold detector.
38 TAl Tone Ringer Input terminal. TAl is the positive supply wltage terminal for tone ringer Circuitry.
Current is supplied to TAl through resistor R2. When the average wltage across R2 exceeds
an internal reference wltage (typically 1.6 wits) the tone ringer output is enabled.
40 TRF Tone Ringer Input filter capacitor terminal. Capacitor Cl connected from TRF to TRS forms
a low-pass filter. This filter averages the signal across resistor R2 and presents this dc wltage
to the input of the threshold detector. Line wltage transients are rejected if the duration is
insufficient to charge Cl to 1.6 wits.
36 TRC Tone Ringer oscillator Capacitor and resistor terminal. The relaxation oscillator frequency fo is
set by resistor R3 and capacitor C13 connected from TRC to V-. Typically.
fa =(R3C13+8.0pS) -•.
39 TAO Tone Ringer Output terminal. The frequency of the square wave output signal at TAO alternates
from f0f8 to f0l10 at a warble rate of fof64O. Typical output frequencies are 1000 Hz and 800 Hz
with e 12S Hz warble rate. TAO sources or sinks up to 20 rnA to produce an output wltage swing
of 18 wits peak-to-peak across the piezo transducer. Tone ringer wlume control can be
implemented by a variable resistor in series with the piezo transducer.

c8 SAMSUNG SEMICONDUCTOR 96
 KA2414/KA2417 (DELETION) LlNEARlI2L INTEGRATED CIRCUIT

GENERAL CIRCUIT DESCRIPTION

LINE VOLTAGE REGULATOR
The DC line interface circuit (Fig 3) determines the DC input characteristic of the telephone. At low input voltage (less than
3 Volts) the ETC draws only the speech and dialer bias currents through the VR regulator. As input voltage increase, 0,
conducts the excess DC line current through resistor R•. The 1.5 Volt level shift prevents saturaiion of O 2 with telephone line
signals up to 2.0 Volts peak (+5.2 dBm). A constant current (dummy load) is switched off when the DTMF dialer is activated
to reduce line current transients. Figure 4 illustrates the DC voltage/current characteristic of a KA2414/KA2417.

DC LINE INTERFACE BLOCK DIAGRAM DC V-I CHARACTERISTIC OF ETC

Line Voltage (V)

II

Fig. 3

SPEECH NETWORK
LINE CURRENT (mA)
The speech network (Figure 5) provides the two-to· Fig. 4
four wire interface between the telephone line and
.the instrument's transmitter and receiver. An elec·
SPEECH NETWORK BLOCK DIAGRAM
tret microphone biased from VR drives the transmit
amplifier. For very loud talkers, the peak limiter
circuit reduces the transmit input level to maintain
low distortion. The transmit amplifier output signal
is inverted at the STA terminal and driven through
an external R·C network to control the receiver side-
tone level. The switched AC resistance at the RM
terminal reduces receiver signal when dialing and §.~
i...J
suppresses clicks due to hook or keypad switch
transitions. When transmitting, audio signal cur· ,!!
rents (irxo and iRxo) flow through the voltage regu·
1
lator pass transistor (T1) to drive the telephone line.
This feature has two consequences: 1) in the trans·
mitting mode the receiver sidetone current iRxo
contributes to the total signal on the line along with
iTxo : 2) The AC impedance of the telephone is de·
termined by the receiver impedance and the volt·
age gain from the line to the receiver amplifier
output.
Fig. 5

c8 SAMSUNG SEMICONDUCTOR 97
KA2414/KA2417 (DELETION) LlNEARII2L INTEGRATED CIRCUIT

EQUALIZATION CIRCUIT (KA2414 ONLY)

The equalization circuit varies the transmit, receive and sidetone gains with loop current to compensate for losses in
long lines. The LR terminal Voltage varies directly ,as the dc loop current. The equalization circuit senses this voltage and
switches in external resistors between V+ and V- and across capacitor C6 (Figure 5) when the loop current exceeds a
threshold level. The speech network operates with full t~ansmit, receive and sidetone gains for long loops. On short loops
the LR voltage exceeds the threshold and these,gains are reduced. The threshold detection circuit has a dc hysteresis to
prevent distortion of speech signals when the telephone is operated at the threshold curr~nt.

DTMFDIALER
Keypad interface comparetors activate the DTMF row and column tone generetors (Figure 6) when a row and column input
are connected through a SPST keypad. The keypad interface is designed to function with contact resistances up to 1.0 kO
and leakage resistances as low a!l150 kO. Single tones may be initiated by depressing two keys in the Slime row or column.
The programmable counters employ a novel design to produce non-integer frequency ratios. The. various DTMF tones are
synthesized with frequency division errors less than ±0.16% (Table 1). Consequently an inexpensive ceramic resonator ca~be
used instead of a quartz crystal as the DTMF frequency reference. Total frequency error less than ±0.8% can be achieved
with to.3% ceramic resonator. The row and column D/A converters produce 16-step. approximations of sinusoidal wave-
forms: Feedback through terminal FB reduces the DTMF output impedance to approximately 2.0 kO to satisfy return loss
specifications.

DTMF DIALER BLOCK DIAGRAM

C1
c. FB
Ca
C4 Keypad C14
R1 Comparators
& Logic
R.
4 5 6
Ra
7 8 9 R4
0 # 0
Keypad
+-_____---;~_ Mute Signal to
Speech Network

ETC

V-

TONE RINGER
The tone ringer (Figure 7) generates a warbling square wave output drive to a piezo sound element when the AC line volt-
age exceeds a predetermined threshold level: The threshold detector uses a current mode comparator to prevent onloff chatter
when the output current reduces the voltage available at the ringer input. When the average current into the tone ringer exceeds
the threshold level, the ringer output TRO commences driving the piezo transducer. This output current sourced from TRI
increases the average current measured by the threshold detector. As a rasuH, hysteresis is produced between t~e tone ringer
on and off thresholds. The output frequency at TRO alternates between f0l8 and f0l10 at a warble nite of f0l640, where fo is
the ringer oscillator frequency.

c8 SAMSUNG SEMICONDUCTOR 98
KA2414/KA2417 (DELETION) LlNEARlI2L INTEGRATED CIRCUIT

TONE RINGER BLOCK DIAGRAM

C15
R2 + ~TiP
c. R.

r _____4;!;TR~'_~tT:R;F::2T~R~S~""':;;;;;;;;;;;;;;;;;;;;;i-----<> Rinp

TRC
I
Piem.
Tone
Ringer

Fig. 7

MICROPROCESSOR INTERFACE (KA2417 ONLy)

The MPU interface connects the keypad and OTMF sections of the ETC to a microprocessor for storing and retrieving
numbers to be dialed. Figure 8 shows the major blocks of the MPU interface section and the interconnections between the
keypad interface, OTMF generator and microprocessor. Each button of a 12 or 16 number keypad is represented by a four-
bit code (Figure 9). This four-bit code is used to load the programmable counters to generate the appropriate rr:JN and column
tones. The code is transferred serially to or from the microprocessor when the shift register is clocked by the microproces- .
sor. Data is transferred through the 110 terminal, and the direction of data flow is determined by the Data Direction (~O) input
terminal. In the manual dialing mode, DO is a logic "0" and the four-bit code from the keypad is fed to the OTMF generator
by the digital multiplexer and also output on the 1/0 terminal through the four-bit shift register. The data sequence on the
1/0 terl)1inal is 83, 82, 81, 80 aQd is transferred on the negative edge of the clock input (CL). In this mode the shift register
load enable circuit cycles the register between the load and read modes such that multiple read cycles may be run for a single-
key closure. Six complete clock cycles are required to output data from the ETC and reload the register for a second look.
In the automatic dialing mode, DO is a Logic "1" and the four-bit code is serially entered in the sequence 83, 82, 81, 80
into the four-bit shift register. Thus, only four clock cycles are required to transfer a number into the ETC. The keypad is dis-
abled in this mode. A Logic "1" on the Tone Output (TO) will disable tone outputs until valid data from the microprocessor
is in place. Subsequently 10 is switched to a Logie "0" to enable the OTMF generator. Figures10 and 11show the timing wave-
forms for the manual and automatic dialing modes and Table 2 specifies timing limitations.
The keypad decoder's exclusive OR circuit generates the OP and MS output signals. The OP output indicates (when at
a logic "1 ") t~at one, and only one, key is depressed, thereby indicating valid data is available to the MPU. The OP output
can additionally be used to initiate a data transfer sequence to the microprocessor. The MS output (when at a Logic "1") indi-
cates the OTMF generator is enabled and the speech network is muted.
Pin A+ is to be connected to a source of 2.5 to 10 volts (generally from the microprocessor circuit) to enable the pullup
circuits on the microprocessor intel'fitce outputs (OP, MS, 1/0). Additionally, this voltage will pOwer the entire Circuitry (except
Tone Ringer) in the absence of voltage at V+. This permits use ofthe transmit and receive amplifiers, keypad interface, and
OTMF generator for non-typical telephone functions.

c8 SAMSUNG SEMICONDUCTOR 99
KA24141KA2417 (DELETION) LlNEARlI2L INTEGRATED CIRCUIT

MICROPROCESSOR INTERFACE BLOCK DIAGRAM (KA2417 ONLY)

r-----------~~~~~ID
Excluslve-OA }-=---,
8 DP
MS

Keypad 8 Keypad
1-+""+'-I-..A'Comparators Decoder 1---.:~r---'-'-""1

Shift
~":~sterl--_---I
Enable

Fig.S

MPU INTERFACE CODES

Key Row Column Code (B3 - BO)

[Q 0 0 0 ~ A1

1 .' 1 1 1111
2 1 2 '0111

0 0 0 0 - A2 3
4
1
2
3
1'
1011
1101
5 2 2 0101
6 2 3 1001
~ 0 0 ~ - As 7
S
3
3
1
2
1110
0110 '
9 3 3 1010
[] 0 0 G f- A4 0
A
4
1
2
4
0100
0011
B 2 4 0001
I I I I C 3 4 0010
C1 C2 Cs C4 0 4 4 0000
* 4 1 1100
# 4 3 1000

Fig. 9

c8
, ,

sAMSUNG SEMICONDUCTOR 100

KA2414/KA2417 (DELETION) LlNEARlI2L INTEGRATED CIRCUIT

OUTPUT DATA CYCLE FROM KA2417

NOTE: 'ro may be low (Tone generator enabled) if desired.

00 ~____t~~
__D_ep___se_d_________________________~
__R_ele_as_ed-rl_

- 11111////1
1O~

MS~_ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

DP

_. CL
_ _ _ _ _ _--!tOPCl

H
L I
Fig. 10

INPUT DATA CYCLE TO KA2417

00 .--J Tone generation interval

~1·__~loo_o_o________~~~
roJ ! W~------~W L
,
MS~
I
DP I
I

_ H tOOCl I--i tCllO tH f--+-l tl

CL ---11.IlnfL...,~J1Jl.1UL
tos --II-- H tOH

IK)~~~ 1st Digit 2nd Digit 3rd Digit

Fig. 11

c8 SAr-tSUNG SEMICONDUCTOR 101

· KA2414/KA2417 (DELETION) LlNEARlI2L INTEGRATED CIRCUIT

TABLE 1 - FREQUENCY SYNTttEStZER ERRORS

DTMF Tone Output

% Deviation
Standard Frequency with
from Standard
(Hz) 500KHz Oscillator

Row 1 697 696.4 -0.086

Row 2 770 769.2 -0.104
Row 3 852 '853.2 +0.141
Row 4 941 939.8 -0.128
Column 1 1209 1207.7 -~.108
Column 2 1336 1336.9 +0.067
Column 3 1477 1479.3 +0.156
Column 4 1633 1634.0 +0.061

TABLE 2 - TIMING LIMITATIONS

Symbol Parameter Min Typ Max Unit Ref

fel Clock Frequency 0 20 30. kHz

Figs.
t,:, Clock High Time 15 p.S
10, 11
Figs.
tl Clock Low Time 15 p.S
10,11
t r, tf Clock, Rise, Fall Time 2.0 p.S
Clock Transition to
toy 10 p.S Fig. 10
Data Valid
Time from DPHigh
tOPCl 20 p.S Fig. 10
to CL Low
Time from DO High
tOOCl 20 p.S Fig. 11
toCLLow
tos Data Set-up Time 10 p.S Fig. 11
tOH Data Hold Time 10 "s Fig. 11
Time from cL Low
tclTO
toro Low
10
"s Fig. 11

Time from TO High

tTOOO 20 "s Fig. 11
to DO High

c8 SAMSUNG SEMICONDUC1"()R 102

KA2414/KA2417 (DELETION) LlNEARII2L INTEGRATED CIRCUIT

APPLICATIONS INFORMATION
Fig 12 specifies a typical application circuit for the KA2414 and KA2417.
Complete listing of external components are provided at the end of this section along with nominal component values.
The hook switch and polarity guard bridge configuration in Fig. 12 is one of several options. If two bridges are used, one
for the tone ringer and the other for speech and dialer circuits, then the hook switch can be simplified. Component values
should be varied to optimize telephone performance parameters for each application. The relationships between the appli-
cation circuit components and certain telephone parameters ,are briefly described in the following:

On-Hook Input Impedance.

R1, C15, and Z3' are significant components for on-hook impedance. C15 dominates at low f~uencies, R1 at high

II
frequencies and Z3 provides the non-linearity required for 2.5V and 10V impedance signature tests. C15 must generally
be s1.01'F to satisfy 5.0Hz impedance specifications. (EIA RS-470)

Tone Ringer Output Frequencies

R3 and C13 control the frequency (fo) of a relaxation oscillator.
Typically fo= (R3 C13 + S.OpS) -1. The output tone frequencies are fof10 and fo/8. The warble rate is fo/64O. The tone ringer
will operate with fo from 1.0KHz to 10KHz. R3 should be limited to values between 150K and 300K.

Tone Ringer Input Threshold

After R1, C15. and Z3 are chosen to satisfy on-hook impedance specifications, R2 is chosen for the desired ring start
threshold.
Increasing R2 reduces the ac input voltage required to activate the tone ringer output. R2 should be limited to values between
O.8K and 2.0KO.

Off-Hook DC Resistance
R4 conducts the dc line current in excess of the speech and dialer bias current. Increasing R4 increases the input resistance
of the telephone for line currents above 10mA. R4 should be selected between 300 and 1200.

Off-Hook AC Impedance
The ac input impedance is equal to the receive amplifier load impedance (at RXO) divided by the receive amplifier gain
(voltage gain from V+ to RXO). Increasing the impedance of the receiver increases the impedance of the telephone.
Increasing the gain of the receiver amplifier decreases the impedance of the telephone.

DTMF Output Amplitude

R14 controls the amplitude of the row and column DTMF tones. Decreasing R14 increases the level of tones generated
at V+. The ratio of row and column tone amplitudes is internally fixed. R14 should be greater than 200to avoid excessive
current in the DTMF output Amplifier.

Transmit Output Level '

R10 controls the maximum signal amplitude produced at V+ by the transmit amplifier. Decreasing R10 increases the transmit
output signal at V+. R10 should be greater than 2200 to limit current in the transmit amplifier output.

c8 SAMSUNG SEMICONDUCTOR 103

KA2414/KA2417 (DELETION) LlNEARlI2L INTEGRATED CIRCUIT

Transmit Gain
The gain from the microphone to the telephone line varies directly with R11. Increasing R11 increases the signal applied
to R10 and the ac current driven through R10 to the telephone line. The closed loop-gain from the mi,crophone to the TXO
terminal should be greater than 10 to prevent transmit amplifier oscillations.

Note: Adjustments to transmit level and gain are complicated by the addition of receiver sidetone current to the transmit
amplifier output current at V+. Normally the sidetone current from the receiver will increase the transmit signal (ifthe
current in the receiver is in phase with that in R10). Thus the transmit gain and sidetone levels cannot be adjusted
independently.

Receiver Gain
Feedback resistor R6 adjusts the gain at the receiver amplifier. Increasing R6 increases the receiver' amplifier gain.

Sidetone Level
'Sidetone reduction is achieved by the cancellation of receiver'amplifier input signals from ~9 and R5. R8, R15, and C6
determine the phase of the sidetone balance signal in R9. The ac voltage at the junction of R8 and R9 should be 1800 out
of phase with the voltage at V+. R91s selected such that the signal current in R9 is slightly greater than that in R5. This insures
that the sidetone current in the receiver adds to the transmit amplifier output current.

Microprocessor Interface (KA2417 Only)

The six microprocessor interface lines (DP, TO, MS, DO, 1/0, and cr.) can be connected directly to a port, as shown in
Figure 13. The DP line (Depressed Pushbutton) is also connected to an interrupt line to signal the microprocessor to be-
gin a read data sequence when storing a number into memory. The KA2417 clock speed requirement is slow enough
(typically 20kHz) so that it is not necessary to divide down the processor's system clock, but rather a port output can be
toggled. This facilitates synchronizing the clock and data transfer, eliminating the need for hardware,to generate the clock.
The DO pin must be maintained at a Logic "0" when the microprocessor section is not in, use, so as tei permit normal
operation of the keypad.
When the microprocessor interface section is not in use, the supply voltage at Pin 12 (A+) may be disconnected to con-
serve power. Normally the speech circuitry is powered by the voltage supplied at the V+ terminal (Pin 34) from the telephone
lines. During this time, A+ powers only the active pullups on the three microprocessor outputs (DP, MS, and VOl. When
the telephone is "on-hook," and V+ falls below 0.6cvolts, power is then supplied to the telephone speech and dialer circuitry
from A+. Powering the circuit from the A+ pin permits communication with a micrpprocessor, andlor use of the transmit
and receiver amplifiers" while the telephone is "on-hook."

Equalization of Speech Network (KA2414 Only)

Resistors R17 and R18 are'switched into the circuit when the voltage at the LR terminal exceeds the equalization threshold
voltage (iypically 1.65V). R17 reduces the transmit and receive gains for loop currents greater than the threshold (short loops)
by attenuating signals at tip and ring. R18 reduces the sidetone level which would otherwise increase when R17 is switched
into the circuit. The voltage VLR at LR terminal is given by ,
VLR =(lL-ls)xR4.
where IL =Ioop current
Is=dummy load current (6.0 mA)+speech network current (4.0 mAl.
Thus resistor R4 is selected to activate the equalization circuit at the desired loop current, However, R4 must be select-
ed keeping in mind the fact that it also controls the dc resistance of the telephone. CapaCitors C18 and C19 prevent dc current
flow into the EV and ES terminals. This reduces cliCks alld also prevents changes in the dc characteristic of the telephone
when the EV andES terminals are switched to low impedance.

i8 SAMSUNG SEMICONDUCTOR 104

KA2414/KA2417 (DELETION) LlNEARlI2L INTEGRATED CIRCUIT

APPLICATION CIRCUIT 1

DTMF Pad
Row-Column Switch Clolsure 4 5
7 8
S2

I
SI, S2, controlled
by hook switch; Illustrated
in "on-hook"
condition.

Rt8
RING

C17
Electret
Microphone

'Rx used with

2-terminal mike only_

Fig_ 12
APPLICATION CIRCUIT 2
DTMF Pad
Row-Column Switch Clolsure

SI, S2, controlled

by hook switch; Illustrated
in "on-hook"
condition.

MC6800
System

vss

'Rx used with

2-termlnal mike only.
Fig_ 13

c8 SAMSUNG SEMICONDUCTOR 105

KA2414/KA2417 (DELETION) LlNEARII2L INTEGRATED CIRCUIT

EXTERNAL ,COMPONENTS
(Component labels referenced to Fig. 12, Fig. 13)

Capacitors Nominal value I Description'

C1 1.0"F,1OV Tone ringer filter capacitor: integrates the voltage from current sense resistor R2
at the input of the threshold detector.
C2 4.7"F,25V Tone ringer input capacitor: filters the rectified tone ringer input signal to smooth
the supply potential for oscillator and output buffer.
C3 1.0"F,3.OV Transmit limiter'low-pass filter capaqitor: controls attack and decay time oftransmit
peak limiter.
C4,C5 O.1/IF Transmit amplifier input capacitors: prevent dc current flow into TXL pin and
attenuates low-frequency noise on microphone lead.
C6 O.05"F Sidetone network capacitor: provides phase-shift in sidetone path to match that
caused by telephone line reactance.
C7,C8 O.05"F Receiver amplifier input capacitors: prevent dc current flow into FM terminal and
attneuates low frequency noise on the telephone line.
C9 2.2"F,3.0V VR regulator capacitor: frequency compensates the VR regulator to prevent
oscillation.
C10 O.Q1,.F Receiver amplifier output capacitor: frequency compensates the receiver amplifier
to prevent oscillation.
C11 O.1,.F DC load filter capacitor: prevents the dc load circuit from a:ttenuating ac signals
onV+.
C12 O.01,.F Telephone line by pass capacitor: terminates telephone line for high frequency
signals and preVents oscillation in the VR regulator.
C13 620pF Tone ringer oscillator capacitor: determines clock frequency for tone and warble
frequency synthesizers.
C14 O.1,.F DTMF output feed back capacitor: ac couples feed back around the DTMF output
amplifier which reduces output impedance.
C15 1.0"F, 250vac tone ringer line capacitor; ac couples the tone ringer to the telephone line partially
NoncPoiarized <lontrols the on-hook input impedance of telephone.
C16 25pF,25V Speech equalization coupling capacitor, prevents dc current flow into SPE terminal
(optional)
C17 5.0"F,3.OV Side tone equalization coupling capacitor, prevents dc currents flow into STE
terminal (optional)

c8 SAMSUNG SEMICONDUCTOR 106

KA2414/KA2417 (DELETION) LlNEAR/l2 L INTEGRATED CIRCUIT

EXTERNAL COMPONENTS (Continued)

(Component labels referenced to Fig. 12)

Resistors Nominal Value Deserlption

R1 6.8K Tone ringer input resistor: limits current into the tone ringe from transients on the
telephone line and partially controls the on-hook impedance of the telephone.
R2 1.8K Tone ringer current sense resistor: produces a voltage at the input of the threshold
detector in proportion to the tone ringer input current.
R3 200K Tone ringer oscillator resistor: determines the clock frequency for tone and warble
frequency synthesizers.
R4

. RS.R7
82.1.0W

1S0K. S6K
DC load resistor: conducts all dc line current in excess of the current required for
speech or dialing circuits; controls the off·hook dc resistance of the telephone.
Receiver amplifier input resistors: couple ac input signals from the telephone line
to the receiver amplifier; signal in RS subtracts from that in R9 to reduce sidetone
in receiver.
II
R6 200K Receiver amplifier feedback resistor: controls the gain of the receiver amplifier.
R8.R9 1.SK.30K Sidetone network resistors: drive receiver amplifier input with the inverted output
signal from the transmitter; phase of signal in R9 should be opposite that in RS.
R10 270 Transmit amplifier load resistor: converts output voltage of transmit amplifier into
a current that drives the telephone line; controls the maximum transmit level.
R11 200K Transmit amplifier feedback resistor: controls the gain of the transmit amplifier.
R12. R13 4.7K.4.7K Transmit amplifier input resistors: couple signal from microphone to transmit
amplifier; control the dynamic range of the transmit peak limiter.
R14 36 DTMF calibration resistor: controls the output amplitude of the OTMF dialer.
R1S 2.0K Sidetone network resistor (optional): reduces phase shift in sidetone network at high
frequencies.
R17 600 Speech equalization resistor. Reduces transmit and receive gain when EV terminal
switches on (optional)
R18 3.0K Sidetone equalization resistor. Reduces sidetone level when ES terminal switches
on. (optional)
Rx 3.0K Microphone bias resistor: sources current from VR to poWer a 2·terminal electret
microphone;. RX is not used with 3·terminal microphones.

Semiconductors Electret Mic Receiver

B1= MDA101A. or equivalent. 2 Terminal. Primo Prime Model DH·34 .

or4·IN400S EM·9S (use Rx) (3000) or equivalent
T1=KSA733 or equivalent or equivalent
Z1=18V. 1.5W. INS931A 3 Terminal. Primo
Z2=30V.1.5W.INS936A 07A 181P (RemoVe Rx)
Z3=4.7V. 1/2W. IN750 or equivalent
XR - Murata Erie CSB 500KHz
Resonator or equivalent
Piezo - PBLS030BC TOKO Buzzer
or equivalent

c8 SAMSUNG SEMICONDUCTOR 107

KA2418 LINEAR INTEGRATED CIRCUIT

TONE RINGER WITH BRIDGE DIQDE

8 DIP
The KA2418 is a monolithic'integrated circuit designed to replace
tlie mechanical bell in telephone sets, in connection with an electro
acoustical converter. The supply voltage Is obtained from the ftC ring
signal aRd the circuit is designed so that noise on the line or variation
of the ringing signal cannot affect correct operation of the device.

FUNCTIONS
• Two oscillators
• Output amplifier
• Power supply control circuit.

FEATURES
• Low current consumption, In order to allow, the parallel operation
of 4 device..
• On-chip diode bridge and transient protection
• Little extemal circuitry
• Tone and switching frequenclea adjustable by external
components
• 'Integrated voltege and current hysteresis
• Activation voltage adjustable

BLOCK DIAGRAM
RECfIFIER
CAPACllOR IMTIAL VOL'OOE ADJUSTABLE

POWER
SUPPLY'
CONTROL
CIRCUIT
>------{,5
NON INVERTING
OllTPUT
WWFREQ HIGHFREQ OUTPUT
osc osc AMP

~------------------------------------~3~----------------~4~------------~--------------------____------------~
GND SWEEP RATE ' OUTPUT FREQUENCY
CONTROL CAPACllOR CONTROL RESISlOR

Fig. 1

c8 SAMSUNG SEMICONDUCTOR 108

KA2418 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Ta 25°C) =

Characteristic Symbol Value Unit

Calling Voltage (f=50Hz) Continuous VAB 90 Vrms

Calling Voltage (f=50Hz)
VAe 110 Vrms
5 Sec ON/10 Sec OFF
Supply Current Icc 22 mA
Operating Temeprature Top -20- + 70 °C
Storage and Junction Temeprature TSIg -65-+150 °C

ELECTRICAL CHARACTERISTICS
(T. = 25°C unless otherwise specified)

Characteristic Symbol Test Condition Min Typ Max Unit

Supply Voltage Vee 26 V

Current Consumption without Load Ie Vs=8.8 to 26V 1.5 1.8 mA
Activiation Voltage VON 12.2 13 V·
Activiation Voltage Range VONR RA=1kll 8 10 V
Sustaining Voltage VOFF 8 8.8 V
Differential Resistance in
Ro 6.4 kll
Off Condition
Output Voltage Swing VOUT , Vcc-3 V
Short Circuit Current lOUT 35 mA

AC OPERATION

Characteristic Symbol Test Condition Min lYP Max Unit

Output Frequencies Vee =26V, R, =14kll

fOUT' Vce=OV 1,900 Hz'
fouT2 Vcc=6V 1,300 Hz
fouT' Range R, =27kll to 1.7kll 0.1 15 KHz
Sweep Frequency R,=14kll,C,=100nF 10 Hz

c8 SAMSUNG SEMICONDUCTOR 109

KA2418 LINEAR INTEGRATED CIRCUIT

TEST AND APPLICATION CIRCUIT

r------------------~w_-__,
I R.
I

TIP 1"F, 25(11//>C 1 2.2KO O.22,.F

.----"1'"-----U------l
C2 R2 I
I
I

8 6 10K 10K~
I
I
I
I
I
I
VAS TEL LINE I
I
Vour I

~i~
I
I
I
Cl R,
RING
100nF 12Kll I
I
I
I
I
'-______ --'_~--_---_+_----- ....------------..J
. 2.67-10" 1000
h = R,(KO) 12= ~h fsweep=·--
7 C,(nF)
Fig. 2

DESCRIPTION
The KA2418 tone ringer derive its powen supply by rectifying the AC ringing signal. It uses this power to activate two tone
generators. The two tone fraquencies generated ara switched by an internal oscillator in a fast· sequence and made audible
across an output amplifier in the loudspeaker; both tone fnequencies and the switching frequency can be externally adjusted.
The device can drive either dineclly a piezo ceramic converter (buzzer) or small loudspeaker. In case of using a loudspeaker,
a transfonmer is needed.
An internal shunt voltage Regulator provides DC voltage to output stage, low fraquency oscillator, an High fnequency oscil-
lator. To protect the IC from telephone line transients, a zener Diode· is included.

EXTERNAL CC;>MPONENTS (refer to test circuit)

R, : Output fnequency control nesistor
C, : Sweep nate control capacitor
R2 : Line input rasistor. R~ffects the tone ringer·input impedance. It also influences ringing threshold voltage and
limits currant from line transients. .
C2 : Line input capacitor. C2AC couples the tone ringer to the telephone line and controls ringer input impedance at
low fnequencies.
C3 : Ringer supply capacitor, C3 filters supply voltage for the tone generating circuits.
R. : Activation voltage adjustable resistor

c8 SAMSU~G SEMICONDUCTOR 110

 KA2420 (DELETION) LINEAR INTEGRATED CIRCUIT

VOICE SWITCHED SPEAKER-PHONE

28 DIP
The KA2420 speaker phone chip includes amplifiers, attenuators, and
control functions necessary to design a high quality speaker phone
system. It also includes a.microphone amplifier and audio power
amplifier for speaker, background sound level monitoring system, at-
tenuation control svstem, and the necessary regulated voHages for
internal and the external circuits. This will permit operation from the
mains with no additional power supply required.
The chip select pin will facilitate power down 'when the chip is not 28 SOP~
selected. The volume control may be implemented by using an external
potentiometer. The KA2420 can be used in a wide variety of applications
such as; intrecom systems, business, automotive or household
telephones.

FEATURES
• Level detection and attenuation controls on single chip
• Monitoring for background noise level with large time constant
• On-chip regulation for supply and reference' voltages
,• Wide range of operation due to signal compression
• Very low output power (10mW typ.) with peak limiting for minimiz-
ing distortion
• Chip Select allowing standby mode of operation ORDERING INFORMATION
• Volume can be controlled linearly
• 28 pin' plastic DIP & SOP package Device Package Operating Temperature
KA2420N 28 DIP
-20_+60°C
KA2420D 28 SOP
BLOCK DIAGRAM

r--------------------,I
I TRANSMIT CHANNEL

SPEAKER I

~I~-R...E-C-EI-VE-C-H-A-N-NE<L
vt: :~:RPHONE IC SYSTEM
L ____________________ ...J
DC INPUT TELEPHONEr
LINE rf7
RECEIVE VOLUME CONTROL 4-- 1.. ENABLE
INPUT

c8 SAMSUNG SEMiCONDUCTOR 111

KA2420 (DELETION) LINEAR INT~GRATED CIRCUIT

PIN DESCRIPTION·
Pin Name Description
1 RR A resistor to ground provides a reference current for the transmit and receive attenuators.
A resistor to ground determines the nominal gain of the transmit attenuator. The transmit channel
2 AT)(
gain is. inversely proportional to the RTX resistance.
3 TXI Input to the transmit attenuator. Input resistance is nominally 5.0KO.
Output of the transmit attenuator. The TXO output signal drives the input of the transmit level
4 TXO
detector, as well as the external circuit which drives the telephone line.
Input of the transmit level detector. An external resistor ac coupled to the TLI pin sets the detection
5 TLI
level. Decreasing this resistor increases the sensitivity to transmit channel signals,
Output of the transmit level detector. The external resistor and capacitor set the time the
6 TLO
comparator will hold the system in the transmit mode after speech ceases.
Input of the receive level detector. An external resistor ac coupled to the RLI pin sets the detection
7 RLI
level. Decreasing this resistor increases the sensitivity to receive channel signals.
Output of the receive level detector. The external re~istor and capacitor set the time the
8 RLO
comparator will hold the system in the receive mode after the receive signal ceases.
Microphone amplifier input. Input impedance is nominally 10KO and the dc bias voltage is
9 MCI
approximately equal to VB.
10 MCO Microphone amplifier output. The. mic amp gain is internally set at 34dB (50 VN)
A parallel resistor and capaCitor connected between this pin and Vee holds a voltage
11 CP1 corresponding to the background noise level. The transmit detector compares the CP1 voltage
with the speech signal from CP2.
A capaCitor at this pin peak detects the speech signals for comparison with the background noise
12 CP2
level held at CP1.
Input to the transmit detector system. The microphone amplifier output is ac coupled to the XDI pin
13 XDI
through an external resistor.
High current ground pin for the speaker amp output stage. The SKG voltage should be within 10mV
14 SKG
of the ground voltage at pin 22.
Speaker amplifier output. The SKO pin will source and sink up to 100mA when ac coupled to the
15 SKO
speaker. The speaker amp gain is internally set at 34dB (50 VN)
Input DC supply voltage. V+ can be powered from Tip and Ring if an ac decoupling induct9r is used
16 V+
to prevent loading ac line signals. The required V+ voltage is 6.0 to 11V (7.5V nominal) at 7.0mA.
A capacitor from this pin. to VB stabilizes the speaker amp ·gain control loop, and additionally con-
17 AGC trois the attack and decay time of this circuit. The gain control loop limits the speaker amp input to
prevent dipping at SKO. The internal resistance at the AGC pin is nominally 110KO.
Digital chip select input. When at a logic "0" «0.7V) the Vee regulator is enabled. When.at a logic
18 CS "1" (> 1.6V), the chip is in the standby mode drawing O.5mA. An open CS pin is a logic "0 ". Input
impedance is nominally 140KO. The input voltage should not exceed 11V.
19 SKI Input to the speaker amplifier. Input impedance is nominally 20KO.
A 5.4V regulated output which powers all circuits except the speaker amplifier output stage. Vee
can be used to power external circuitry such as a microprocessor (3.0mA max.). A filter capaCitor
20 Vee
is required. The KA2420 can be powered by a separate regulated supply by connecting V+ and
Vee to a voltage between 4.5V and 6.5V while maintaining CS at a logic "1".

c8 SAMSUNG SEMICONDUCTOR 112

KA2420 (DELETION) LINEAR INTEGRATED CIRCUIT

PIN DESCRIPTION (Continued)

Pin Name Description

An output voltage equal to approximately Vcc12 which serves as an analog ground for the
21 VB speakerphone system. Up to l.5mA of external load current may be sourced from VB. Output
impedance is 2500. A filter capacitor is required.
22 Gnd Ground pin for the IC (except the speaker amplifier)
Transmit detector output. A resistor and capacitor at this pin hold the system in the transmit mode
during pauses between words or phrases. When the XDC pin vohage decays to ground. the
23 XDC attenuators switch from the transmit mode to the idle mode. The internal resistor at XDC is
nominally 2.6KO (see Fig. 1) •
Volume control input. Connecting this pin to the slider of a variable resistor provides receiVe mode
24 VLC volume control. The VLC pin voltage should be less than or equal to VB.
Attenuator control filter. A capacitor connected to this pin reduces noise transients as the
25 ACF
attenuator control switches levels of attenuation.
Output of the receive attenuator. Normally this pin is ac coupled to the input of the speaker
26 RXO
amplifier.
27 RXI Input of the receive attenuator. Input resistance is nominally 5.oKO.
A resistor to ground determines the nominal gain of the receive attenuator. The receive channel
28 RRX
gain is directly proportional to the RRX resistance. .

ABSOLUTE MAXIMUM RATINGS (Voltages referred to Pin 22, T.=2S0C)

Ch~racteristic Value Unit

Speaker Amp Ground (Pin 14) +3.0. -1.0 V

V + Terminal Voltage (Pin 16) +12. -1.0 V
CS (Pin 18) +12. -1.0 V
VLC (Pin 24) Vee. -1.0 V
Storage Temperature -65-150 ·C

"Maximum Ratings" ~re those values Ileyond which the safety of the device cannot be guarariteed. They are not meant
to imply that the devices should be operated at these limits. The "Electrical Characteristics" tables provide conditions
for actual device operation.

RECOMMENDED OPERATING CONDITIONS

Characteristi~ Value Unit
Microphone Signal (Pin 9) O-S.O mVrrns
Speaker Amp Ground (Pin 14) -10-10 mV
V+ Terminal Voltage (Pin 16) +6.0-11 V
CS(Pin 18) 0-11 V
lee (Pin 20) 0-3.0 mA
VLC(Pin24) 0.5SVB-VB V
Receive Signal (Pin 27) 0-2S0 mVrrns
Ambient Temperature -20:"'6(l OC

c8 SAMSUNG SEMICONDUCTOR 113

 . .
KA2420.(DELETION) LINEAR INTEGRATED CIRCUIT

. . ELECTRICAL CHARACTERISTICS (Refer-to Fig. 1)

Characteristic Symbol Test Condition Min lYP Max Unit
SUPPLY VOLTAGE
V+ Supply Current Iv + V+=11V, Pin 18=0.7V . 9.0 mA
V+=11V, Pin 18=1.6V 800 Ji'..
Vee Voltage Vee V+=7.5V 4.9 5.4 5.9 V
Vcc Line Regulation IlVC9 6!5V<V+ <11V. 65 150 mV
VC9 Output Resistance Ro lee=3.0mA 6.0 20 G
Vee Drop Voltage VccD' V+=5.0V 80 300 mV
Va Voltage Va V+=7.5V 2.5 2.9 3.3 V
Va Output Resistance Ro la=1.7mA 250 0
ATTENUAlORS
Receive Attenuator Gain
RxMode Arx
100KHz
Pin 24=Ve, Pin 27=250mVrms 2.0 6.0 10
.
dB
Range IlArx '.Ax to Tx Mode 40 44 48 dB
Idle Mode Arxi Pin 27=250mVrms -20 -16 -1~ dB
RxoVoltage Vrxo RxMode 1.8 2.3 3.2 V,
( Rxo Voltage Change IlVrxo From Rx to Tx Mode 100 mV
Rxo Sink Current IRsink RxMode 75 pA
Rxo Source Current . IRsource RxMode 1.0 3.0 mA
Rxi Input Resistance Rrxi 3.5 5.0 8.0 KG
Volume Control Range Veon Rx Attenuator Gain, 24.5 32.5 dB
Rx Mode, O.6Va<Pin 24<Ve
Transmit Attenuator Gain 1KHz
TxMode Atx Pin 3=250mVrms 4.0 6.0 8.0 ,dB
Range IlAtx
, TxtoRx Mode 40 44 48 dB
,
Idle Mode Atxi Pin 3=250mVrms -16.5 -13 -8.5 dB
TxoVoltage Vtxo TxMode 1.8 2.3 3.2 V
Txo Voltage Change .,o.Vtxo From Tx to Rx Mode 100 mV
Txo Sink Current Irsink TXIMode 75 p.A
Txo Source Current Jrsource TxMode 1.0 3.0 mA
Txi Input Resistance' Rtxi 3.5 5.0 8.0 KG
ACFVoltage Vacl Vcc·Pin 25 Voltage
RxMode 150 mV
TxMode 6.0 mV
Idle Mode 75 mV
SPEAKER AMPLIFIER
. Speaker Amp Gain Aspk Pin 19=20mVrms 33 34 35 dB
SKI Input Resistance Rski 15 22· 37 KG
SKOVoltage Vsko CapaCitor Tied 2.4 3.0 3.6 V
toGND
SKO High Voltage Vskoh Pin 19=0;1V, 5.5 V
-1QOmA Load at Pin 15

c8 SAMSUNG SEMICONDUCTOR. 114

KA2420 (DELETION) LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS (Continued) /

Cm-racterlstlc Symbol Test Condition Min Typ Max Unit
SKO Low Voltage Vskol Pin 19=-0.1V, 600 mV
+100mA Load at Pin 15
MICROPHONE AMPLIFIER
Mike Amp Gain Amci Pin 9=10mVrms 1KHz 32.5 34 35 .dS
Mike Amp Input Resistance Rmci 6.5 10 16 KO
LOG AMPLIFIER
RLO Leakage Current IIkrlo Pin 8=Va+1.OV 2.0 ,A
TLO Leakage Current IIktlo Pin 6"'Va+1.OV 2.0 ,A'
Tx-Rx Switching S, Th. . Ratio of hLI to IRLI 0.8 1.2
Threshold at 20pA to Switch
Tx-Rx Compara,tor
TRANSMIT DETEC10R
XDCVoltage Vxdc Idle Mode 0 V
Tx Mode 4.0 V
CP2 Current Source Icp2 5.0 10 13 /loA
DISTORTION
Rx Mode-RXI to SKO Rxd Pin 27=10mVrms, 1KHz 1.5 %
Tx Mode-MCI to TXO Txd Pin 9=5.0mVrms, 1KHz 2.0 %

Note: 1. V+=7.5V, CS=O.7V except where noted. .

2. Rx Mode: Pin 7=-100pA, Pin 5=+100pA except where noted.
Tx Mode: Pin 5, 13= :"100pA, Pin 7 = + 1OOpA, Pin 11 = OV
Idle Mode: Pin 5=-100pA, Pin 7, ·13=+100pA
3. Current into a pin designated as +: current out of a pin designated as-
4. Voltage referred to Pin 22, Ta=+25°C.

TEMPERATURE CHARACTERISTICS (-20 to +60°C)

Characteristic Pin Typical Change Unit
V+ SupplyCurrent(V+=11V, Pin· 18=O.7V) 16 -0.2 %fOC
V+ Supply Current (V+=11V, Pin 18=1.6V) 16 -0.4 %fOC
Vee Voltage 01+ = 7.5V) . 20 +0.1 %fOC
Atte':!uator Gain (Max and Min Settings) ±0.003 dSfOC
Delta RXO, TXO voltage 4,26 ±0.24 %fOC
Speaker Amp Gain H~, 19 ±0.003 . dSfOC
Microphone Amp Gain 9, 10 .. ±0.001 dSfOC
Microphone Amp Input Resistance 9 +0.4 %fOC
Tx-Rx Switching Threshold (@20pA) 5,7 ±0.2 nAfOC

c8 SAMSUNG SEMICONDUcroR 115

db TEST CIRCUIT ~
ic
.0
t
Q .

~
am
r-
Kt
~
TRANSMIT
OUTPUT vee
RECEIVE !!I
6
8z
-
INPUT

z
g
~
cz
m
l>
:D
Z
-t
m
C)

~
~
m
c
-o.
0
:D

·1 §i
...... Fig. 1
......
0>
KA2420 (DELETION) LINEAR INTEGRATED CIRCUIT
TRANSMIT ATTENUATOR Vs RTX RECEIVE ATTENUATOR Vs RRX

+10
-~ JaxGl.n +10
1

....... <:.6·~l MaJG~innU

- - &V8cf.l50mV /,'

-10 i'.. \
r--., -10

-20 .... "lr-.. " -20

/
I""
~
~-30
~
e -30

~
Max Attenuation
&V8cf·l50mV
-40 -40

-50
~ -50 ./ ~Max Attenuation
I' &V8cf-6.OmV
.,
'

II
RJ.JK
-60

-70
f-vLf"la " -80

-70
r-- RR• 3OK
VLC·VB Usable Range -

10K lOOK 1M lK 10K lOOK

RTX(OHMS) RRX(OHMS)
Fig. 2 Fig. 3

GAIN AND ATTENUATION

ATTENUATOR GAIN Vs VLC
Vs RESISTOR RATIOS

~T) R~x/bR
VB JRX~l~K !
+10 r-- ..:1Vacf= 6.0mV +5 t--RTX.91K
l""'r--. RR·3OK r-.. GTX :
:
,,
V
-10
l/~ -5 t--LCUi1
\ , GRy'"

-20 ~::~ RRXlRR~ V Receive

-10 t - - Modo Li, .i.
'II -30
&V8cf-l50mV
i)(
f8 -15
: I\. V
-40
I"roo... -20
i, ~
I<' ~ i) 1,\
-50

-60
ARX vs. ARXIRR
&V8cf·6.0mV
ATX vs. RTXlRR
&V8cf·150mV -30
v: r\
I 1111 JL : Minimum ,

~
:-- Recommended
-35
, Level
1 VLC.va
-40
~ : -.l I
0.1 0.5 1.0 5.0 10 0.2 0.4 D.6 DB 1.0
RATIO . YLCIV.
Fig. 4 Fig. 5

ATTENUATOR GAIN Va aYacf LOG AMP TRANSFER CHARACTERISTICS

250
. i

I--......
+5
"- (ID( GRX . / "
200 ,...... ~
V

18
-5

-10 f--

-15

-20
"
RR=3OK
RTX-91K
RRX.18K
f'..
~
~~
/
/
L
J
/"

-25
/
"' INPUT~
+
-30

-35 , /
./

40 60 80 100
&YacI (MILUVOLTS)
Fig. a
" f'-
120 140
~
180
50 -

0
CURRENT
(RLI, TLI. XOI)

I Vi
-20 -40
I I VOLjE
-80
DC INPUT CURRENT (foA)
Fig. 7
(RLO. TLO, CP2)-
OUTPUT,

-80

c8 SAMSUNG SEMICONDUCTOR 117

KA2420 (DELETION) LINEAR INTEGRATED CIRCUIT
SPEAKER AMP OUTPUT
LOG AMP TRANSFER CHARACI'ERISTICS
,. Va SUPPLY VOLTAGE

120
".,.. ~
k": No load
I
V 250 Load

/ I
/ '/ --
VL ,
. '~r t--
30 I-I--+-+- 2D / .V
0
4.05.06.07DS.o 9.\..1011
V+ (VOLTS)
fig. I

RESPONSE AT CP2 AND CPt

600

500

,...
I ",vepl (Pin 1'1)

-~...-
~ -
./
/
V
/
I AVCP2(Pin 12)
I
100
V
fl
0
1O!J 150 200
YMCO (rrN RMS)
Fig. 1.

TRANSMIT DETECTOR OPERATION

Inpu~i:~1111111~1111111111111111111111111111111111~I---~m~llilllllllllllllllll~

J1 .
CP2 (Pin 12) .1
I.
..IV, (~200mV)

.
. \ dV ~ c(~'ZV/s.ec)
. Cit 10pA
.
r ~ ~.
I·
Solid ~~~~~Pl r-r-------------- I 36rnV

Don.dLine=.
Noninverting
:1' 2.7xav, 7
~~~~~rT~;~~'t __ ~ Slope = O.5V/sec

4 Volts NOTE: Above values are typical based

XDC (Pin 23) ,~ on components shown in Fig. 1.
Fig. 11

c8 SAMSUNG SEMICONDUCTOR 118

 KA2420 (DELETION) LINEAR INTEGRATED CIRCUIT

SUPPLY CURRENT Vs SUPPLY VOLTAGE

SUPPLY CURRENT Vs SUPPLY VOLTAGE
Vs SPEAKER POWER
ao 35

71J
V1 100.1-
\ I I
6.0
'I
/ OS=o
30
8Oi-
5.0
25 5OJ-
'i+ 4.0
VSKOa OVrms ~
.§.
..! ..!
20

I
3.0
~ 20rriW . ---
21J
15
,A I
1.0
./ :...t 10rriW,
CS=1
I 10
./ 6IJi
4.0 5.0 6.0 71J 8.0 9.0 10 11 41J 5.0 6.0 7.0 6.0 9.0 10 11
V+(VOLTS) V+(VOLTS)
Fig. 12 Fig. 13
SUPPLY CURRENT Vs SUPPLY
VOLTAGE (see Fig. 14)
25
i I
I
i
ALTERNATE POWER SUPPLY CONFIGURATION I

,i--
Allowahle J-------!
Operating Range ... I
20 , ,'
-cs
,,
,
I I
18 KA2420
15
,,
,,,
iI
I
II
20 16 22 . , i
,
,, ,,
Is
Vee V+
10 ,,
, /
,/
I .......-;
Vs ,/

(Regu lated supply)

1i7
5.0
L--- V-
,
i
,
Zl1000.F ~ ,, :
r.'7
,,,
I
Fig. 14 I
I
o I
4.0 5.0 61J 7.0 6.0
V.(VOLTS)
Fig. 15
SWITCHING TIME
The switching times of the speakerphone depends on the external components and the instantanious operating conditions
at the time when a change takes place. For example, the switching time for changing between transmit ~nd receive modes
is much longer than that from idle to transmit.
The components connected at pin 5 "transimit turn-on': pin 6 "transmit-turn-off': pin 7 '~receive-turn-on" and pin 8 "receive-
turn·off" have major influence on the timing between the transmit and receive modes. The Tx·Rx comparator compares
the relative and not the absolute values so the above referenced four timing functions interact with each other. The timing
from transmit to idle is affected by the components at pins 11, 12, 13 and 23. The timing from idle to transmit is faster and
hence the components have no major influence on it.

c8SAMSUNG SEMICONDUCTOR 119

KA2420 (DELETION) LINEAR INTEGRATED CIRCUIT

The table below indicates the degree of influence of various components on the switching time, including the volume
cont.rol;
Additionally, the following should be noted:
1) The RCs at'Pin 5 and Pin 7 affect the sensitivity of the respective log amplifiers, or how loud the speech must be for
gain control of the speakerphone circuit.
2) The RC at Pin 13 controls the sensitivity of the transmit detector circuit.
3) The switching speed and the relative response to transmit signal are affected by the volume control, in manner as follows:
When the \/OIume control reduces, the signal at TXO increases, and consequently the signal to the TLI pin in the receive
mode circuit.

Components Rxto1X Tx to Rx Txtoldle

RC at Pin 5 , high medium no influence
RC at Pin 6 medium high . no influence

I AC at Pin 7
AC at Pin 8
medium
high
high
medium
no influence
noinlluence
AC at Pin 11 low no influence medium
I C at Pin 12
AC at Pin 13
low
low
I no inlluence
no influence
high
low
AC at Pin 23 low no influence high
V at Pin 24 medium no influence ·noinlluence
C at Pin 25 medium medium low

. Switching response times for the circuit of Fig. 1 are shown in the photographs of Fig. 16 and Fig. 17.
In Fig. 16, the circuit is supplied a continuous receive signal of 1.1mVp.p at AXI as shownTrace #3. Mel as shown. Trace
#1 openites a repetitiVe signal of 7.2rriVp.p for 120msec, and repeated every 1sec. Trace #2 is the TXO output being about
650mVp.p at its maximum. Trace #4 is the RXO output being about 2.2mVp.p at its maximum.
The switching time from the receive mode to transmit mode is about 40msec required for TXO to turn on, and for RXO
to tum off. After the signal at MCI is turned off, the switching time back to the receive mode is about 210msec.
In Fig. 17 a continuous signal of 7.6rriVp.p is supplied to MCI as shown Trace #1, and a repetitive burst signal of 100rriVp.p
is supplied to AXI as shown Trace #3 for 12Omsec;and repeated every 1sec. Trac~ #2 is the TXO output and is about
9OrriVp.p at its, maximum, and Trace #4 shows the AXO outpufbeing about 150rriVp.p at its maximum, In this sequence, the
circuit switches between the idle mode\and the receive mode. The required 'switching time from idle to receive modeS is
about 70msec as shown in the first part of Trace #2 and Trace #4. After the receive signal is turned off, the switching time
back to the idle mode is about 100msec.
All of above mentioned switching times can change significantly not only by varying the external components but also
by varying the amplitude of input signals. .

TRANSMIT-RECEIVE SWITCHING IDLE-RECEIVE SWITCHING

Burst Input @ MCI

Inpul@ Mel

2 OUlpul@TXO
2 Oulpul @ TJ(O

3 Inpul@RXI Bursllnput @ RXI

4 Output@RXO OUlpUI- RXO

Time Base=30msJOiv

Fig. 16 Fig. 17

c8 SAMSUNG SEMICONDUCTOR 120

KA2420 (DELETION) LINEAR INTEGRATED CIRCUIT

BASIC LINE POWERED SPEAKERPHONE

S1
.----------..--<Y'O----Tlp
Hook

0.001 471jK 22K

47
IT 1.0
47K

TLI CP1 ACFIAGC V+

Speaker SKO
KA2420
(25 OHMS)
SKG

VLC VB AA

VB 47
30K 18K

1. Diodes are IN4001 unless otherwise noted.

2. 4 Transistors are KSC945-Y
3. Recommended Transformer: Seoul Jupa SJ-019-2040
Fig. 18

DIGITAL TRANSMIT/IDLE/RECEIVE INDICATION

KA2420
ALO TLO

56K 56K

'.>--+__ rTXIIDLE ".._~_ rTx

'--_---'1-:...- ..J Ax _ _--. _" :..J Idle
Compartors A & B=LM393 (Dual)

Fig. 19

qs'SAMSUNG SEMICONDUCTOR 121

 "
KA2425A1B LINEAR INTEGRATED CIRCUIT

TELEPHONE SPEECH NETWORK WITH

18 DIP
DIALER INTERFACE
The KA2425AiB is a Telephone Speech Network Integrated Circuit.
which Incorporates adjustable transmit, receive, and sldetone functions,
a dc loop interface Circuit, tone dialer Interface, and a regulated output
voltage for a pulse/tone dialer. Also included is an equalization amp
which compensates gains for line length variations. The conversion from
2 to 4 wire Is accomplished with a supply voltage as low as 1.5 volts.

FEATURES
• Transmit, Receive, and Sidetone Gain Set by External Resistors
• Loop Length Equalization for Transmit, Receive, and Sidetone
Functions
• Low Voltage Operates Down to 1.5 volts (V+) in Speech Mode
• Provides Regulated Voltage for CMOS Dialer
• MUTE: KA2425A, MUTE: KA2425B
• DTMF Output Level Adjustable with Single Resistor
• Compatible with 2·Termlnal Electric Microphones (ECM)
• Compatible with Receiver Impedance. of 1500 and Higher

BLOCK DIAGRAM
Tip

.-----} ~~elver
Ring 0 - - - - '
(Mute)

voo To
Regulator Dialer
Circuit

Mute
Logic
DTMF
Driver

DTMF From Mute PulseiTone

Input
• Microphone Input Select

c8 SAMSUNG SEMICONDUCTOR· 122

KA2425A1B LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

(Voltage referred to V-, Ta=25·C) (see Note 1.)

Characteristic Value Unit

V+ Voltage -1.0, +18 Vdc

Voo (externally applied, V + =0) -1.0 +6 Vdc
VLR - 1.0, V + - 3.0 Vd
MT, MS Inputs -1.0, Voo +1.0 Vdc
Storage Temperature . -65, +150 ·C

I
Note 1: . Devices should not be operated at these values. The "Recommended Operating Conditions" provide
conditions for actual device operation:

RECOMMENDED OPERATING CONDITIONS

Characteristic Value Unit

V + Voltage (Speech Mode) +1.5 to +15 Vdc

(Tone Dialing Mode) +3.3 to + 15 Vdc
Irxo (Instantaneous) o to 10 mA
Ambient Temperature -20 to +60 ·C

ELECTRICAL CHARACTERJSTICS (Refer to Figure 1) (Ta=25·C)

Characteristic Symbol Test Conditions Min Typ Max Unit

LINE INTERFACE
V+Voltage V+ Vdc
Speech/Pulse Mode IL= 2O rn A 2.6 3.2 3.8
Speech/Pulse Mode IL=30mA 3.0 3.7 4.4
Speech/Pulse Mode IL= 120mA 7.0 8.2 9.5
Tone Mode. IL=20mA 4.1 4.9 5.7
Tone Mode IL=30mA 4.6 5.4 6.2
V +Current (Pin 12 Grounded) 1+ mA
Speech Mode V+=1.7V 4.5 7.1 9.0
Speech/Pulse Modes V + = 12V 5.5 8.4 12.5
Tone Mode V + = 12V 6.0 8.8 14.0
LR Level Shift 6.VLR VdC
Speech/Pulse Mode V+ -VLR - 2.7 -
Tone Mod.e V+ -VLR - 4.3 -
LC Terminal Resistance. RLe 36 57 94 KG
VOLTAGE REGULATORS
VR Voltage VR (V+=1.7V) 1.1 1.2 1.3 V dC
Load Regulation 6.VRLO OmA<IR<6.0mA - 20 - mV
Line Regulation 6.VRLN 2.0V<V + <6.5V - 25 - mV
Voo Voltage Voo (V+=4.5V) 3.0 3.3 3.8 Vdc
Load Regulation(Dialing Mode) 6. VOOLO . 0<100< 1.6mA - 0.25 - Vdc
Line Regulation (All Modes) . 6. VOOLN 4.0V<V+ <9.0V - 50 - mV
Max. Output Current Ioosp Speech Mode 375 550 1000 pk
Max. Output Current loooL Dialing Mode 1.6 2.0 3.6 mA
Voo Leakage Current IOOLK V+ =0, Voo =3.0V - 1.5 p.A

ciS SAMSUNG SEMICONDUCTOR 123

KA2425A1B LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS (Continued) .

Characteristic Symbol Test Conditions Min Typ Max Unit

SPEECH AMPLIFIERS
Transmit Amplifier
Gain ATxo TXI to TXO 22 24 26 dB
TXO Bias Voltage VTXosP Speech/Pulse Mode 0.45 0.52 0.60 x VR
TXO Bias Voltage VTXODL Tone Mode V~-25 VR-5.0 - mV
TXO High Voltage VTXOH Speech/Pulse Mode VR-25 VR-5.0 - mV
TXO Low Voltage VTXOL Speech/Pulse Mode - 125 250 mV
TXI Input Resistance RTX1 - 10. - KO
Receive Amplifier
RXO Bias Voltage VRXO All Mode 0.45 0.52 0.60 x VR
RXO Source Current IAXOSP Speech Mode 1.5 2.0 - rnA
RXO Source Current IRXODL PulselTone Mode 200 400 - p.A
RXO High Voltage VRXOH All Mode VR-1oo VR-50 - mV
RXO Low Voltage VRXOL All Mode - 50 150 mV
MICROPHONE, RECEIVER CONTROLS
MIC Saturation Voltage VOl.MIC Speech Mode, I = 500p.A - 50 125 mV
MIC Leakage Current IM1cLK Dialing Mode, Pin 1 = 3.0V - 0 5.0 p.A
RMT REsistance RRMTSP Speech Mode - 8.0 15 0
RRMTDL Dialing Mode 5.0 10 18 KO
RMT Delay tRMT Dialing to Speech 2.0 4.0 20 ms
SIDETONE AMPLIFIER
Gain (TXO to STA) ASTA .dB
Speech Mode @V LR =0.5V - -15 -
Speech Mode @VLR=2.5V - -21 -
Pulse Mode @VLR =0.2V - -15 -
Pulse Mode· @VLR =1.0V - -21 -
STA Bias Voltage VSTA All Modes 0.65 0.8 0.9 x VR
EQUALIZATION AMPLIFIER
Gain (V + to EO) AEa dB
. Speech Mode @VLR =0.5V - -12 -
. Speech Mode @VLR =2.5V - -2.5 -
Pulse Mode @VLR =0.2V - -12 -
Pulse Mode @VLR=1.0V - -2.5 -
EO Bias Voltage VEa Vdc
Speech Mode @VLR =0.5V - 0.66 -
Pulse Mode @V LR =0.5V· - 1.3 -
Speech, Pulse Mode @VLR=2.5V - 3.3 -

c8 SAMSUNG SEMICONDUCTOR 124

 KA2425A1B LI~EAR INTEGRATEO CIRCUIT

ELECTRICAL CHARACTERISTICS (Continued)

Characteristic Symbol Test Conditions Min Typ Max Unit

DIALING INTERFACE
MT Input Resistance RMT 58 100 - KO
MT Input Resistance - 50 - KO
MT, MT Input High Voltage V1HMT Voo -0.3 - - VdC
MT, MT Input Low Voltage V1LMT - - 1.0 Vdc

I
MS Input Resistance RMs 280 600 - KO
MS Input High Voltage V1HMS 2.0 - - Vdc
MS Input Low Voltage V1LMS - - 0.3 Vdc
TI Input Resistance RTI - 1.25 - KO
DTMF Gain AOTMF See Figu.re 2 (V +iV1N) 3.2 4.8 6.2 dB
SYSTEM SPECIFICATIONS (Refer to Fig. 1- Fig. 4)
Tip-Ring Voltage (including polarity guard
bridge drop 01 1.4V) (Speech Mode) IL=5.0mA - 2.4 - VdC
IL= 10mA - 3.9 -
IL=20mA - 4.6 -
IL=40mA - 5.6 -
IL=60mA - 6.6 -
Transmit
Gain Irom Vs to V + Figure 3 (lL = 20mA) 28 29.5 31 dB
Gain Change IL=60mA -6.0 -4.5 -3.6 dB
Distortion - 2.0 - %
Output Noise' - 11 - dBmc
Rece'ive
VRxoIVs 1= 1.0KHz, IL = 20mA -16 -15 :"13 dB
Receive Gain Change (See Figure 4)i1L= 60mA -5.0 -3.0 -2.0 dB
Distortion - 2.0 - %
Sidetone Level dB
VRXo!V + (Figure 3) IL=20mA - -36 -
IL=60mA - -21 -
Sidetone Cancellation 20 26 - dB
{ ~R:O (Figure 4)} dB _ { ~R:O (Figure 3)}dB
IL=20mA

DTMF Driver 3.2 4.8 6.2 dB

V + V1N (Figure 2) IL= 20mA
AC Impedance 0
Speech mode (incl. Ca, See Figure 4) IL=20mA ,- 750 -
z,., = (600)V +/(Vs -V +) IL=60mA - 300 -
Tone Mode (including Ca) 20mA<I L<60mA - 1650 -
Note: Typicals are not tested or guaranteed.

,c8 SAMSUNG SEMICONDUCTOR 125

KA2425A1B LINEAR INTEGRATED CIRCUIT

PIN DESCRIPTION (See Fig. 1)

Pin No. Name Description ,

1 MIC Microphone negative supply. Bias current from the electric

microphone Is returned to V - through this. pin, through an open
collector NPN transistor whose base is controlled by an. internal
mutE;! signal. DuringdialilJl;" the transistor is off disabling the
microphone.
2 TXI Transmit amplifier .input. Input impedance Is 10KO. Signals from the
microphone are input through capacltro C5 to TXI
3 TXO Transmit amplifier output. The AC Signal current from this output
flows through the VR series pass transistor via R. to drive the line at
V +. Increasing Re will decrease the signal at V +. The output is
biased at::::O.65V to allow for maximum swing of AC signals.
The closed loop from TXI to TXO is Internally set at 26dB.
4, STA Sidetone amplifier output. Input to this amplifier is TXO. The signal
at STAcancels the sidetone signals in the receive amplifier. The
, signal level at STA increases ,with loop length.
,
5 CC Compensation capacitor. A capacitor from CC to GND will
compensate the loop length equalization circuit when additional
stability Is required. In most applications, CC remains open.
6 EQ Equalization amplifier output. A portion of the V + signal is present
on this pin to provide negative feedback around the transmit
amplifier. The feedback decreases with increasing loop length,
causing the AC impedance of the circuit to increase.
7 RXI Receive amplifier input. Input impedance is >100KO. Signals from
the line and sidetone amplifier are summed at RXI.
8 RXO Receive amplifier output. RXO is biased by a 2.5mA current source.
Feedback maintains the DC bias voltage at:::: O.65V. Increasing R4
(between RXO and RXI) will increase the receive gain. C4 stabilizes
. the amplifier. C3 couples the signals to the receiver. The 2.5mA
current source is reduced to O.4mA when dialing.
9 RMT Receiver Mute. The AC receiver current is retumed to V - through
an open collector NPN transistor and a parallel 10KO resistor. The
base of the NPN is controlled by'an internal mute signal. During
dialing the tr.ansistor is off, lel!ving the 10KO resistor in series with
the receiver.
10 V- Negative supply. The most negative input connected to Tip and Ring
, through the polarity guard diode bridge.
11 VR Regulated voltage output. The VR voltage is regulated at 1.2V and
biases the microphone ,and the speech circuits. An internal series
pass 'PNP' transistor allows for regulation with a line voltage as low
as 1:5V. Capacitor Cs stabilizes the regulator.
12 LC DC load capacitor. An external capacitor C7 and an internal resistor
form a low pass filter between V + and LR to prevent AC signals
from being loaded by the DC load resistor R5• Forcing LC to V - will
turn off the DC load current and increase the V + voltage.

c8 SAMSUNG SEMICONDUCTOR 126

KA2425A1B LINEAR INTEGRATED CIRCUIT

PIN DESCRIPTION (See Fig. 1) (Continued)

Pin No. Name Description

13 LR DC load resistor. Resistor R5 from LR to V - determines the DC

resistance of the telephone, and removes power dissipation from the
chip. The LR pin Is biased 2.8 volts below the V + voltage (4.5 volts
in the tone dialing mode)
14 V+ Positive supply. V + Is the positive line vol1age (from Tip & Ring)
through the polarity guard bridge. All sections Qf the KA2425A/B are
powered by V + .
15 Voo Voo regulator. Voo Is the output of a shunt type regulator with a
nominal voltage of 3.3V. The nominal output current is Increased
from 550I'A to 2mA when dialing. Capacitor Cg stabilizes the
regulator and sustains the Voo voltage during pulse dialing.
II
~6 TI Tone input. The DTMF signal from a dialer circuit Is input at TI
through an external resistor R7. The current at TI is amplified to drive
the line at V +. Increasing R7 will reduce the DTMF output levels.
The Input Impedance at TI is nominall 1.25KO.
17 MS Mode select. This pin is connected through an internal 6OOKO
resistor to base of an NPN transistor. A logic "1" (>2.0V) selects
the pulse dialing mode. A logic "0" «0.3V) selects the tone dialing
mode.
18 Ml Mute input for KA2425A. MT is connected through an internal 100KO
resistor to the base of a PNP transistor, with the emitter at Voo. A
logic "0" «1.0V) will mute the network for either pulse or tone
dialing. A logic "1" (>Voo -0.3V) puts the KA2425A into the speech
mode.
MT Mute input for KA2425B. MT Is connected through an internal 5OKO
to the base of a NPN transistor, with the collector to the base of a
PNP transistor. A logic "1" (>Voo-0.3V) will mute the network for
. either pulse or tone dialing. A logic "0" « 1.0V) puts the KA2425B
into the speech mode.

c8 sAMSUNG SEMICONDUCTOR 127

KA2425A1B LINEAR INTEGRATED CIRCUIT

Fig. 1 Test Circuit

'Tip 0-------_
C8
2.0

~ Rlngo-----------

Rl
lOOK

R7
22K
DTMF Input >-.J\I\/v----J

Voo Voo
Output---~-{15}---1r-----.J
C9
o.l;h

Mute>-----'~

Pulse/Tone
Select

c8 SAMSUNG SEMICONDUCTOR 128

KA2425A/B LINEAR INTEGRATED CIRCUIT

Fig. 2 DTMF Driver Test

22K
TI v+

400mVrms
,+; 0.02
KA2425A1B Iloop
1.0KHz
LR
M'f
.:.1.0V
MS

1
V- LC 47

Fig. 3 Transmit and Sidetone Level Test

I
0.05
TXI VR

'---II1II11---1 EQ
Txe
v+
III
8.2K ..,
<
('II
LR
~
c(
lo: LC

Voo
Mf
v-

Fig. 4 AC Impedance, Receive and Sidetone Cancellation Test

150K
v+
8.2K
STA
V+
0.05
RXI
33K hoop
LR

f'
Rxe III
10 ..,< 47 6000

'~f·~l
('II

~
lo:
0.2
250mVrms (VS)
1,OKHz

c8 SAMSUNG SEMICONDUCTOR 129

KS5805A1KS5805B CMOS INTEGRATED CIRCUIT

TELEPHONE PUlSE DIALER WITH REDIAL

18 DIP
The KS5805AJB is a monolithic CMOS integrated circuit and provide!j I

all the features required for implementing a pulse dialer with redial.

FUNCTIONS
• Muie output logic "0"
• Pulse output logic "0"
• RC oscillation for reference frequency
• Designed to operate directly from the telephone line
• Used CMOS technology for low voltage, low power operation
• PoWer up clear circuitry
• KS580SA pin 2: V REF
• KS5805B pin 2: Tone out

FEATURES
• Uses either a standard 2 of 7 matrix keyboard with negative true
common or the inexpensive form A·type keyboard
• Make/Break ratio can be selected
.• Redial with· or ff
• Continuous MUTE .
• Tone signal output or on-chip reference Voltage by bonding option
on chip
• 10 ppS/20 pps can be selected

. TEST CIRCUIT
GND vee

vee~~--------------------------~--------~--------,

1Mil

KS5805 AlB

66% Break

20pps

10pps
Fig. 1

c8 SAMSUNG SEMICONDUCTOR 130

KSS80SAlKSs80SB CMOS INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Ta=25°C)

Characteristic Symbol value Unit

DC Supply Voltage Vee 6.2 V

Voltage on Any Pin Y'N Vee +0.3. Gnd-0..3 V
Power Dissipation Po SOO.O mW
Operating Temperature Topr -30-+60 "C
Storage Temperature Tstg -6S-+1S0 °C

DC ELECTRICAL CHARACTERISTICS
(T. =2SoC unless otherwise specified)
II
Characteristic Symbol Test Conditions Min Typ Max Unit Notes

Supply Voltage Vee 2.S '6.01 V

Key Contact Resistance RKI 1 KP
1
Keyboard Capacitance CKI 30 pF

K'H 2 of 7 input 0.8Vee Vee

Key Input Voltage V 1
K'l mode Gnd O.2Vce
Key Pull-Up Resistance K,Au Vcc =6.0V 100 KO
Key Pull-Down Resistance K'AD V'N=4.8V 4.0 KO
Vee=2.SV
Mute Sink Current 1M SOO p.A 2
Vo=O.SV

Pulse Output Sink Current Ip Vce=2.SV 1.0 3

Vo=O.SV mA

Vec=2.SV
Tone Output Sink Current Irl
Vo=O.SV
2S0 JA 4

Vce=2.SV
Tone Output Source Current IrH
Vo=O.SV
.2S0 JA 4
-
..
All outputs under
Memory Retention Current IMA 0.7 p.A 6
no load
All outputs under
Operating Current . lop 100 1S0 p.A
no load
Vcc =6.0V
Mute or Pulse Off Lelikage IlKG . 0.001 1.0 JA 2,3
Vo=6.0V
VAEF Output Source Current IAEF Vec-VAEF=6.0V 1.0 7.0 mA S

Note 1) Applies to key input pin. (R,-R•• C,-C 3)

2) Applies to MUTE output in.
3) Applies to J50rsE output pin.
4) Applies to TONE pin (KSS80S8)
S) Applies to VAEF pin (KSS80SA)
6) Current necessary for memory to be maintailled. All outputs unloaded .

• Typical values l!.re to be used as a design aid are not subject to production testing.

131
KS5805AIKS5805B CMOS INTEGRATED CIRCUIT

AC ELECTRICAL CHARACTERISTICS (Ta 25°C) =

Charactistic Symbol Min 1\'p Max Unit Notes

Oscilator Frequency Fose 4 KHz 1

Key Input Debounce Time Toe 10 ms 3,4
Key Down Time for Valid Entry TKO 40 ms 4,5
Key Down Time During
tKR 5 ms 4
Two-Key Roll Over
Oscillator Stat-Up Time (Vee =2.5V) tos 1 ms
Mute Valid After Last Outpulse tMO 5 ms 3,4
Pulse Output Pulse Rate PR 10 PPS 2
On-Hook Time Required to
Clear Memory
IoH 300 ms 4

Pre-Digital Pause Tpop 800 ms 3,4

Inter-Digital Pause T,op 800 ms 3,4
Frequency Stability .
Af ±4 %
Vee=2.5-3.5V
Frequency Stability Vee =3.5 - 6.0V Af ±4 olb
Tone Output Frequency FlONE 1 KHz 4,6

Note: 1) Rs=2MO, R=220KO, C=390pF.

2) If pin 10 is tied to Vee, the output pulse rate will be 20pps.
3) If the 20pps option is selected, the time will be 1/2 these shown.
4) These times are directly proportional to the oscillator frequency.
5) Debounce plus oscillator start-up time s 40ms.
6) If the 20pps option is selected, the tone output frequency will be 2KHz. (KS5805B ONLY)

. PIN CONNECTIONS·
Pin 1: Vee Pin 10: 10/20pps Select
Pin 2: Vref (KS5805A)/Pacifier tone (KS5805B) Pin 11: Make/Break Select
Pin 3: Column 1 Pin 12: Mute Output
Pin 4: Column 2 Pin 13: ROW 4
Pin 5: Column 3 Pin 14: ROW 3
Pin6:GND Pin 15: ROW 2
Pin 7: RC Oscillator Pin 16: ROW 1
Pin 8: RC Oscillator Pin 17: On-Hook/Test
Pin 9: RC Oscillator Pin 18: Pulse Output

c8 SAMSUNG SEMICONDUCTOR 132

KS5805AIKS5805B CMOS INTEGRATED CIRCUIT

TIMING CHARACTERISTICS
Digit Digit Redial
Key Input
----~L2-Jr-----,~r-------------,~r--~--------------

Tone output
Column scan
- nnnn .- (only KSS80SB)

. ---utrUlIUl- -soo'H;-----.IUl.J""LJlf -------:------uu----

Row scan ~-----------lIlfL..IlIl----------W-
r
o_n.HOOk input

MUTE output
~
_--l-!i---1!H!
"'~.
PULSE output --I~-II-i!--~/
1,
,I,
r
r n
1
r+-H'fo------, r---_,
1.r
I II
I II' I I I .
OSCoutput I, I I 4KH I I : I ~ I I: I

(pin 8) 'rin-----~*-- ______ L~+-~---------------------J.nr

I
I
~~l
---t ....... T08
II
I TIOP
T8 1 I!
-t H- i ITMC':
I: : I I
I
:
:
•
I
II
I
110ms I Ii --tl~rl I I I I I
i !I i
i TPDP 800ms 800ms
Normal dialing
l/PR I ""
II Redial mode I~
I I. .

On hook I I _ Test mode

Off hook mode Off hook mode

Fig. 2

PIN DESCRIPTIONS
1. Vcc(Pin 1)
This is the positive supply pin. The voltage on this pin is measured relative to Pin 6 and is supplied from a 150pA current
source. This voltage muS! be regulated to less than 6.0 volts using on external form or regulation.

2. Tone signal outputNREF (Pin 2)

Tone signal out pin is CMOS comperementaly output and drive on external bipolar transistor. This pin generates a tone
signal when a key is depressed as its recognition. Tone signal frequency is 1KHz when 10pps pulse rate is selected. (the
frequency is 2KHz when 20pps pulse rate is selected). Only the pin 2 of KS5605A is VREF (on-chip reference voltage).

TYPICAL I-V CHARACTERISTICS

The VREF output provides a reference voltage that tracks internal
7.0
parameters of the KS5805A. VREF provides a negative voltage reference
6.0
to the Vee supply. Its magnitude will be approximately 0.6 volt greater
than the minimum operating voltage of each particular KS5805A
S.O The typical application would be to connect the V REF pin to theGND pin
IREF (Pin 6). The supply to the Vee pin (Pin 1) should then be regulated to
MA 4.0 150pA (lop max). With this amount of supply current, operation of the
KS5805A is guaranteed.
3.0
The internal circuit of the VREF function. is shown in Figure 3 with its
associated I-V characteristic.
2.0
VREF

1.0

1.0 2.0 3.0 4.0 5.0 Fig. 3

vee -VREF VOLTS

c8 SAMSUNG SEMICONDUCTOR 133

KS5805A1KS5805B CMOS INTEGRATED CIRCUIT

3. Keyboard inputs (Pin 3, 4, 5, 13, 14, 15, 16,)

The KS5805AIB incorporates an innovative keyboard scheme that allows either the standard 2-of-7 keyboard with nega-
tive common or the inexpensive single contact (form A) keyboard to be used.
A valied key entry is defined by either a Single row being connected to a single column or GND being sjmutaneously
presented to both a Single row and column. When in the on-hook mode, the row and column inputs are held high and no
keyboard inputs are accepted.
When off-hook, the keyboard is completely static until the initial valid key input is sense<;l. The oscillator is,then enabled
and the rows and columns are alternateiy scanned (pulled high, then low) to verify the input is varied. The input must remain
valid continuously for 10msec of debounce time to be accepted .
• Form A type keyboard • 2 of 7 keyboard (negative common)

G~'-----_______'·1.
~
COL

COL
------------~ -.~---------- ---------------ROW
ROW '
• 2 of 7 keyboard

. - - - - - ".±~
• Electronic input

vcc
'H
COL - _.:.__-,-_-_-_..,_u
~-~-~-----.
L-_______----A ••
~ ____________
ROW .vc_c____________,

4. GND (Pin 6)
KEY BOARD CONFIGURATIONS ~!?------------U
This is the negative supply pin and is connected to the common part in the general applications.

5. OSCILLATOR (Pins 7, 8, 9)
The KS5805AIB contains on-chip inverters to provide an oscillator which will operate with a minimum of external components.
FollOWing figure shOWS the on-Chip configuration with the necessary external components. Optimum stability occurs with
the ratio K=RsIR equal to 10. '
The oscillator period is given by;
T=RC (1.386+(3.5KCs)IC-(±KI(K+1» In (K1(1.5K+0.5»
Where Cs is the stray capacitance on Pin 7.
Accuracy and stability will be enhanced with this capacitance minimized.

RS

+---U----<l>----.-.1 8
KS5805 AlB
C

,R

c8 SAMSUNG SEMICONDUCTOR
, I
134
KS5805AIKS5805B CMOS INTEGRATED CIRCUIT

6. 20/10 pps (Pin 10)

Connecting this pin to GND (pin 6) will select an output pulse rate of 10pps.
Connecting the pin Vee (pin 1) will select an output pulse rate of 20pps.

7. MAKE/I;IREAK (Pin 11)

The MAKE/BREAK pin controls the MAKE/BREAK ratio of the pulse output. The MAKE/BREAK ratio is controlled by con·
necting Vee or GND to this pin as shown in the following table.

Input Make Break

vee (Pin 1)

GND (Pin 6)
34%

40%
66%

60% II
8. MUTE OUTPUT (Pin 12)
The mute oiJtput is an open-drain N-channel transistor designed to drive an external bipolar transistor.
This circuitry is usually used mute the receiver during outpulsing. As shown in Fig. 2 the KS5805 mute output turns on
(pulls to the VGNo-supply) at the beginning of the predigital pause and turns off (goes to an open circuit) following the last
break.
The delay from the end of the last break until the mute output turns off is mute overlap and is specified as tMO.

9. ON-HOOKITEST (Pin 17)

The "ON-HOOK" or "Test" input of the KS580SA/B has a 100K{J pull~up to the positive supply. A Vee input or allowing the
pin to float sets the circuit in its on-hook or test mode while a VGND input sets it in the off-hook or normal mode. When off-hook
the KS5805AIB will accept key inputs and outputs the digits in normal fashion .. Upon completion of the last digit, the oscillator
is disabled and the circuit stands by for additional inputs.
Switching the KS5805AIB to on-hook while it is outpulsing causes the remaining digits to be outpulsed at 100x the nor-
mal rate (M/B ratio is then 50/50). .
This feature provides a means of rapidly testing the device and is also on efficient method by which the circuitry is reset.
When the outpulsing in this mode, which can take up to 300msec, is completed, the circuit is deactivated and will require
only the current necessary to sustain the memory and power-up-clear detect ·ci.rcuitry (refer to the electrical specifications).
Upon retuning off-hook, a negative transistion on the mute output will insure the speech network is connected to the line.
If the first key entry is either a • or #, the number sequence stored on-Chip will be outpulsed. Any other valid key entrieS will
clear the memory and outpulse the new number sequence.

10. PULSE OUTPUT (Pin 18)

The pulse output is an open drain N-channel transistor designed to drive on external bipolar transistor. These transistor
would normally be used to pulse the telephone line by disconnecting and connecting the network. The KS5805AIB pulse
output is an open circuit during make and pulls to the GND supply during break.

c8 SAMSUNG SEMICONDUCTOR 135

KS5806(DELETION) . CMOS INTEGRATED CIRCUIT

TEN NUMBER REPERTORY DIALER

WITH PACIFIER TONE 18 DIP

The KS5806 is a monolithic integrated ten-number repertory dialer

manufactured using CMOS process. The circuit aCcepts keyboard inputs
and provides the pulse and mute logic levels required for loop discon-
nect signaling.

FEATURES
o Low-voltage (2 to 1OV) and low power operation
o Low memory retention currant of 1II.
o Auto-dlals Ten 16 digit-numbers Including Last Number Dialed
(LND)
o Pacifier Tone Output
o Osclllstor Selectable In pulse mode (RC or ceramic resonator)
o Stand-alone pulse dialer
o PABX pause key Input
o Last number dialed memory
o Last number dialed may be copied Into any one of nine other
locations.
o MakelBreak ratio Is pin selectabls in pulse mode
o Uses slther the Inexpensive Form-A type keyboard or the stan.
dard 2·of·7 matrix keyboard with common Gnd
o Optional use of 13th key Input to control repertory functions in
tone mode /
o Power up circuit Initializes RAM and logic
i

c8 SAMSUNG SEMICONDUCTOR 136

KS5806 (DELETION) CMOS "INTEGRATED CIRCUIT

BLOCK DIAGRAM
vee

18 J5UiM!113 KEY

II
STATIC
CMOS
RAM

DIGITDEMUX

}---------------~10r_--------~

PACIFIER
TONE
HKS GND

DESCRIPTION
The KS580S is a ten-number repertory dialer manufactured using silicon Gate CMOS process. Pin 2, the "Mode select"
input determines whether "signaling will be pulse or tone. The interpretation of several inputs and outputs is dependent upon
the mOde selected. .
In the pulse mode the time base for the circuit is selectable between a ceramic resonator and RC oscillator. In tone mode
the circuit can· only use the RC oscillator. An on chip RAM is capable of storing ten 1S-digit telephone numbers including
the laSt number dialed.
When used in a PABX system, a pause (# key) may be stored in the number sequence. The repertory dialer will recognize
this pause when automatically dialing and stop until another key input is received.

ciS SAMSUNG SEMICONDUCTOR 137

KS5806 (DELETION) 'CMOS INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Ta =25°C)

Caracteristic Symbol value Unit

DC Supply Voltage Vee 10.5 V

Maximum Power Dissipation (25°C) Po 500 mW
Maximum Voltage on Any Pin
Operating Temperature
Y,N
Topr
Vee-l;O.3, GND-0.3
-30-60
. V
°C
Storage Temperatu're Tstg -55-125 °C

DC ELECTRICAL CHARACTERISTICS
(Ta =25°C)

Characteristic Symbol Test Conditions Min Typ Max Units

Supply Voltage' Vee 2.0 10.0 'V

Operating Current (Tone)2 lop Vee=2.5V 50 100 pA
Operating Current (Pulse)2 lop Vee=2.5V 100 200 pA
Standby Current (Vee =2,5V)3 ISB No load 1.0 2.0 pA
Memory Retention Current' IMR 0.3 1.0 pA.
Memory Retention Voltage' VMR 1.3 1.5 V
Mute Sink CUffent' IML Vee=2.5V, Vo=0.5V 0.5 2.0 mA
Pulse Sink Current' Ip Vee=2.5V, Vo=0.5V 1.0 4.0 mA
Pacifier Tone Source/Sink' IPT Source Vo =2.OV 200 500 pA
Mute and Pulse leakageS ILKG Vo=10V 0.001 1.0 pA.
Key Contact Resistance6 RKI 1.0 KG
Keyboard Capacitance 6 CKI 30 pF
"0" LOgic Level K,L ' GND 0.2Vee V
"I" Logic Level K'H 0.8 Vee Vee V
Keyboard Pull Up7 KRu 100 KG
Keyboard Pull Down 7 KRo 1.0 KG
CNT Pull Up (Pin 11)8 ReNT Tone mode only 100 KG

Notes:
1. The memory will be retained at a lower voltage level than that required for circuit operation. If either IMR or VMR is
maintained the memory contents will not be cleared.
2. Operating current with a valid key input at 2.5 volts.
3 .. Standby current on hook or off hook with all inputs unloaded.
4. For V+ =2.5, Sink Vo =0.5 Volts, Source Vo =2.0 volts.
5. Leakage with V+, Vo=10.0 Volts
6. Keyb9ard contact resistance and parasitic capacitance, maximum values., . _ .
7. Keyboard 110 pins will scan 250 Hz with oscillator enabled pulse mode and dunng DD I"'tone mode.
8. Tone mode only.

c8 SAMSUNG SEMICONDUCTOR 138

KS5806 (DELETION) CMOS INTEGRATED CIRCUIT

AC ELECTRICAL CHARACTERISTICS (Ta=25°C)

Characteristic Symbol Min Typ Max Unit

Oscillator (Cer, Res)' FCR 480 KHz

Oscillator (RC)2 FRe 8 16 KHz
Oscillator Stability" tlFRc -3 +3 %
Debounce Time4 Toe 32 mS
Valid Key Down Time TKO 40 mS
Oscillator Start Up Time Tos 8 mS
Key Rollover OVLP Time 5 TRoL 4 mS
Pulse Rate PR 10 PPS
Break Time (Pin 11 VedGND) Te 60/68 mS
Predigital Pause Times Tpop 170 mS
Mute Overlap Time TMoL 2 mS
Tone Rate TR 5 TPS
Pacifier ToneBurst Time7 TPT 28 mS
Pacifier Tone Frequency· FPT 500 Hz
Interdigital Pause Time T,op 940 mS
Notes:
1. Ceramic Resonator should 'have the tOtlowing equivalent values: R<20 Ohms. RA >70k Ohms, Co < 500pF.
2. The RC values chosen determine frequency. The nominal frequency is 8kHz. To accelerate dialing the frequency may
be increased to twice the nominal value. This would double signalling rate and half most timing specifications.
3. Voltage range of 2.5 to 6.0 volts, over temperature, and unit to unit variations.
4. Key entry must be present after 32 ms to be valid.
5. Rollover is the time key inputs must be invalid for successive entries to be recognized.
6. Time from initial key input till first break or tone output.
7. Tone burst will terminate if key released before 28 ms.
8. This is a square wave output.

PIN CONNECTION

vee - - 1 - '- PUL5E113KEY

MOOE--. 2 --HKS

COL1-- 3

Ccii2'-- 4 --R0W2

COi:3-- 5 KS5800 --R0W3

--i'IOWI

OSC/RC-- 7

11 - - MB/CNTI.

OSC
SELECT - - 9 - - PACIFIER lONE

c8 SAMSUNG SEMICONDUCTOR 139

 KS5806 (DELETION) CMOS INTEGRATED CIRCUIT

PIN DESCRIPTION
1. VccCPln 1)
Pin 1 is the positive supply input to the part and is measured relative to GND (pin 6). The voltage on this pin should not
el«:eed 10 VoIIS. On chip Zener diodes will provide protection from supply transients In most applications. Alow voltage detect
circuit will perform a power up initialization whenever the supply voltage at thi!; pin falls below a level necessary to guarantee
proper circuit operation.

2. Mode (Pin 2)
The KS5806will function In either tone or pulse mode, dependent upon the logic level presented to pin 2. For pulse mode
operation, this pin must be tied to GND (pin 6). For tone mode, it should be tied to Vee (pin 1). The interpretation of pins
7,8;11,12, and 18 are dependent upon the mode selected.

3. Keyboard Inputs (Pins 3, 4, 5, 13, 14, 15; 16)

The KS5806 incorporates a keyboard scheme that allows either the standard 2-of-7 keyboard with negative common or
the inexpensive single-contact (Form A) keyboard to be used, as shown in Fig. 1. '
A valid key entry is defined by either a single row being connected to single column or V - being simultaneously presented
to both a single row and column.
In the tone mode, the KS5806 features a bidirectional keyboard scheme. As the KS5806 passively monitors the key inputs
, (using the scan provided by the tone dialer), they are debounced, decoded, and stored in the on chip LND (last Number
Dialed) buffer. The keyboard inputs in tone mode are normally high impedance allowing the tone chip to scan the keyboard
lines and begin signaling immediately upon detecting a key entry. A command key entry disables the tone chip and scanning
is then controlled by the repertory dialer until the key is released. In tone mode auto-<lialing is performed by the KS5B06 which
simulates key contact closures. The tone generator accepts these inputs as valid keyboard information and generates the
proper DTMF frequencies. ~"
In the pulse mode, the KS5806 keyboard inputs are static until an initial valid key input is sensed. The oscillator is then
enabled and the rows and columns-are alternately scanned (pulled high, then low) to verify the input is valid. Keyboard'bounce
is ignored for 32 ms after the initial key down is detected. A key input is accepted if it is valid after this initial debounce time.
This scheme guarantees any valid key input to be recognized in less than 40 ms after the initial key closure.

• Form A type of keyboard

• 2m? _m ("'-j :_m_o_n)_ _ _ _ COL

--------~.
COL
...~-------
ROW GND -1. ______:. ." '- ______ ROw

• 2 of 7 keyboard • Electric input

r----:----~:_-~-:
H
:::----~-----------------------'~~--------------

Fig. 1

c8 SAMSUNG SEMICONDUCTOR 140

KS5806 (DELETION) CMOS INTEGRATED CIRCUIT

4. GND (Pin 6)
This is the negative supply pin and is connected to the common part in the general applications.

5. Oscillator. (Pin 7 and Pin 8)

a
The RC oscillator (Figure 2a) requires resistor and capacitor to provide the frequency reference for the KS5806. The resistor
should be connected from Pin 7 (Osc/RC) to Pin 1 (Vee') and the capacitor from Pin 7to Pin 6 (GND). Pin 8 should be connected
to Vee for normal operation. The nominal frequency for standard operation is 8kHz. This provides for a tone rate of 100ms
on and 100ms off and pulse rate of 10pps. The frequency of oscillation is approximated by the equation.
Fose =1/(1.45 RC).

I
The value suggested for the capacitor- (C) should be 410pF or lower and resistor (R) may be adjusted for the desired signalling
rate. 10PPS and 5TPS operation is achieved by selecting a 390 pF capacitor and a 220K Ohm resistor.
A more accurate and constant frequency reference in pulse mode is obtained using a 480 kHz ceramic resonator as shown
ih Figure 2b. The ceramic resonator is connected in parallel with an on·chip inverter. Two external capacitors to ground are
also required.

a, RCOSC b, CERAMIC RESONATOR

vee
,-----------Iosc

CR

D. . . -~-----l osc

GND
GND
NOMINAL FREQUENCY 8KHz FREQUENCY 480 KHz
Fig. 2

6. Oscillator Select. (Pin 9)

This pin d'etermines the mode of oscillation used by the repertory dialer when in pulse mode. The ceramic resonator is
chosen by tying this pin to Pin 1 (!Vee;). The RC oscillator is chosen by tying this pin to Pin 6 (GND).
In tone mode this input must be tied either high or low but it will not affect the mode of oscillation which is always RC. The
timing of the repertory dialer is independent of the tone chip which uses a 3.5795 MHz crystal as its frequency reference.

7. Pacifier Tone (Pin 10)

The pacifier tone consists of a burst of a 500 Hz square wave. The burst is initiated with the acceptance of a valid key input
(following the debounce time) and terminates after 28ms or with the release of the key, whichever comes first. The output
is high impedance when not active.

c8 SAMSUNG SEMICONDUCTOR 141

KS5806,(DELETION) CMOS INTEGRATED CIRCUIT

8. MB/CNTL (Pin 11),

The level on pin 18 determines the control key inputs required to implement the repertory dialer function. In the 13 key tone
mode, Pin 18 can be used to "control" the repertory dialer functions of the phone with a momentary SPST switch to the negative
supply connected to this input.This feature allows the basic keyboard to operate the same as in a standard telephone and
only the closure of the 13th key will initiate a repertory dialer function. The' and # key inputs will be accepted as normal ,
DTMF inputs (however they will not be stored in the LND buffer). In 12 key mode this pin should be connected to the positive
supply (Vee), . '
In pulse mode, the make break ratio may be selected by connecting this pin to either the Vee or GND supply. Table 1
indicates the two ratios available. .

9. Mute/Dialer Disable (Pin.12)

Pin 12 is the output of an open drain N-channel transistor. In the tone mode, it is used to provide the tone dialer with a Dialer
Disable signal which inhibits the generation of tones during command key entries. The timing characteristics in tone mode
are shown in 'Figure 3a.
In the pulse mQde, Pin 12 is the Mute output. It provides the logic necessary to mute the receiver while the telephone line
is being pulsed. Figure 3b shows the timing characteristics of the Mute output.

MB Input % Break % Make

Vee 60 40
GND 68 32

Table 1

10. HKS (Pin 17)

The HKS (hook switch) input determines how the repertory dialer will handle key entries. When in the off-hook state (pin tied
to GND) signalling is enabled and all entries will be stored in the LND buffer. A control key input in this state initiates the
AUTODIAL function. '
In the on-hook state (Pin 17 tied to Vee), the diater stores. key information in the LND buffer as they are entered but will not
pulse out or allow the DTMF generator to tone. A control key input is interpreted as a STORE command causing the information
present in the LND buffer to be copied into the indicated location.
A hook switch transition terminates all dialer operatiof.1s immediately and initializes all counters and latches. The dialer
is then ready to accept a key entry which will be stored over previous data in the LND buffer.

11. Pulse/13Key (Pin 18)

In the tone mode, a V+ level at Pin 18 allows the KS5806 to accept inputs from a control key (n.o. SPST) connected from
CNTL (Pin 11) to GND. It is used to initiate all repertory functions~ This is referred to as 13 key tone mode. With Pin 18 tied
to GND, the KS5806 is set in the 12-key tone mode and the' and # keys are used in control functions. Pulse mode defaults
to 12 key mode. Both 12 and 13 key tone modes are discussed in more, detail in the Operations section of this data sheet.
In the pulse mode, Pin 18 is the Pulse output. It consists of an ,open drain N-channel transistor and provides the necessary
timing for make, break, interdigital delay, and pulse rate to meet dialer specifications worldwide. The timing characteristics
of the PulseOiJtpUtare shown in Figure 3b.

c8 SAMSUNG SEMICONDUcroR 142

 KS5806 (DELETION) \CMOS INTEGRATED CIRCUIT

GENERAL OPERATION
During normal dialing, each digit is stored in tne LND (Last Number Dialed) buffer, location O. The telephone number dialed
can be left in this temporary LND buffer for later use or it can be copied into any of the other nine permanent memory locations
(1-9).
The wrap-around feature of the buffer allows more than 16 digits to be dialed. Entries follOWing the sixteenth input will be
stored beginning with the first buffer location replacing the information originally stored there. "Any number of digits may be
entered and dialed correctly. In pulse mode, the user should not get more than 15 entries ahead of the digit being pulsed.
Keys entered while auto-dialing in pulse mode will be ignored and not affect the number dialed. In tone mode, if a key is
entered while auto-dialing it will interfere with the keyboard outputs generated by the KS5806. The key entry is detected and .
auto-dialing is interrupted until the key is released. The keyboard entry generates a DTMF signal if valid ..
The KS5806 repertory dialer will not store either a • or # entry in the buffer but will allow the tone generator to signal these
digits as described below.

12. KEY OPERATION

.

II
Normal Dialing
In pulse mode di.gits 0-9 will result in the pulSing of that digit at the standard rate of 10 pps. If the RC oscillator is utilized
this rate can be varied achieving a pulse rate of up to 20pps. The' and # keys enable the repertory functions listed below.
In tone mode operation, digits 0-9 causes the generation of respective DTMF signal. In order to tone a • or.# key it must
be entered twice. The second entry will generate the desired DTMF tone, although it will not be stored in memory.

Storage
Telephone numbers may be entered into the LND buffer while either on-hook or off-hook. However, the KS5806 must be
in the on-hook mode for a number to be copied into a permanent memory location. The LND is copied by entering the key
sequence ", followed by the address (1-9) of the desired lJ1emory location. This operation requires 300 ms before going off .
hook Oi initiating another store and does not change the data in the LND buffer. Information present in the LND buffer when
new data is entered is replaced.and cannot be recalled.
The storage operation may be performed with the telephone off-hook. If requires the addition of an additional switch providing
an excellent "Scratchpad Memory". Numbers may be entered and copied without signalling the line making use of line curre.nt
rather than battery current. Scratchapd memory is useful whenever the user has a need to record a telephone number such
as when calling information.

Automatic Dialing
The automatic dialing function is implemented by going off-hook and entering a " followed by the address (1-9) of the desired
telephone number. Dialing will begin with the release of the address key and can be interrupted by initiating a new redial
. command or with a transition on the HKS pin. The LND buffer will contain the information last entered. A key sequence of
• 0 will cause the last number entered to be redialed. More than one number sequence may be automaiically dialed from
memory without returning on-hook.

Pause/Continue Entries
The KS5806 has a feature "!"hich allows an indefinite pause to be programmed into the first 15 digits of a number sequence
by entering a # key at the point in the sequence where a pause is desired. As the number is automatically dialed, the circuit
will stop dialing when the pau$e is encountered. Any key entry, except for a * key, will cause the KS5806 to continue dialing
the remainder of the number. If more than one pause was originally programmed into the number sequence, a corresponding
number of continue commands must be made in order for the number to be completely dialed.
The continue input will not be recognized until one lOP period following the signalling of the digit preceeding the pause.
This is approximately 940 ms in pulse mode and 100 ms in tone mode.

c8 SAMSUNG SEMICONDUCTOR 143

 KS5806 (DELETION) CMOS INTEGRATED CIRCUIT

13. KEY MODE OPERATION

Normal Dialing
An additional mode of operation (tone mode only) is the ability to use the entire keyboard for normal signalling such that
. when any key is depressed once, including * or #, the proper DTMF signal is generated. This feature is activated by connecting
Pin 18 to Vee. The repertory dialer functions are then initiated by an extra control key (n.o. SPST) connected.from Pin.11
(MB/CNiL) to GND. This key will be referred to as "C".

Storage
The information in the LND buffer may be "copied" or stored into one of the nine permanent memory locations when the
input to HKS is high. The control sequence for this function is CoN. The information will be copied yet leave the LND buffer
information intact.

Automatic Dialing
Information stored in any of 10 memory locations may be autodialed by entering CoN when the input to HKS (Pin 17) is low.
Autodialing may be initiated immediately following a hookswitch transition, manual key entries, or after the completion of
a pr8l!ious auto-dial number.

Pause/Continue
. An indefinite pause may be inserted into the number sequence with a C # entry. This feature is quite useful when dialing
through a PABX. When a number sequence with a pause is autodialed, signalling will stop when the pause is reached and
will continue only when a valid key input is detected.

TONE MODE TIMING

r-------MANUAL KEY ENTRY I ON HOOK SlORE---tr-----AUTO.DI!'-L - - - - - - - I

I DI~IT PAUSE DIGIT DIGIT SlORE ,LOCATION AUTO DIAL LOCATION CONTINUE
KEYINPUT~~ 5 5..----"-
HKSINPUT.., r '1L_ _ _ _ _ _ _ _ _ _ _ _ _ _ __
- ---
DIALER DISABLE----,L.J..- - - - -....

COL1~~

COL2 UUl250 Hz SCAN FREQUEN~·'".'""111111.'_--,

COL3~~ ........r--____...,

ROWI ~ L.....r"~-.....--..,I ..
_.......-......,liIl11111"d--L...r
R0W2 WIIIrL.....J ~

ROW3~~'''''--'I1111''-''.
ROW4------,L.Jr------~,~

PACIFIER TONE -----W- - - -1-- --1- - --111- -;""--111----11--- -111- -.;1- ---1-- --- 0------ -1----- - -- --

Fig.3a

c8 SAMSUNG SEMICONDUcroR 144

KS5806 (DELETION) CMOS INTEGRATED CIRCUIT

PULSE MODE TIMING

AUlD
DIGIT
KEYINPUT~------...
DIGIT 'SlORE'LOCArION
I
DIAL LOCATION
I , . - - - -... 1-----
ROWSCAN.......
SCAN
~SCAN~·.r.==~SCA~N~I'C~~~~
Ii ACTIVE ___
ACTIVE

."""1..-___. . .
SCAN

SCAN 1==-
ACTIVE

I~-
~:::§=x--~·----+-~+--T··e.:~
OSCILLAlOR·

·llose ~TIDP
~
~~T~O j
NORMAL DII,\L
W-TS
T~pL
0' LII U IL:JI

eopy ~!ri~~NATE
~PT~ L
.
JTPDP
L ::J II
AUTO-DIAL
.

Fig3b

c8 SAMSUNG SEMICONDUCTOR 145

KS5808 CMOS INTEGRATED QRCUIT

DUAL TONE MULTI FREQUEt4CV DIALER 18 DIP

The KS5808ls a monolithic Integrated circuit fabricated using CMOS
process and Is designed specifically for Integrated tOne dlmer applI-
cations.

FUNCTIONS
• Fixed.supply operation
• Negative-true keyboard Input
• Tone disable input .
• Stable-output level

FEATURES
• MInimum number of external perla required.
• High accul1lCY tones. .
• DIgItal cIMder logic, nIIIIalIw\adder netwarkand CMOS 0pIII1III0r..
al amplifier on slngl. chip.
• U888lnexpenelve 3.57H45 MHz tHwf8Ion color bunt cry8llll.
• Invalid key entry can ....... In either slngl. tone 'Or no tone.
• Tone diu" allowe any key down output to func:llon fnIm ..,.
board Input without generating tonee.

BLOCK DIAGRAM

~
'-'---t-+-+--MRI
I- 1-_+-H~i4)R'

+-......_-GND GND

=1bne _DIubIe 'lbne0Ul Fig. 1

c8 SAMSUNG SEMICONDUCTOR 146

 KS5808 CMOS INTEGRATED CIRCUIT

. ABSOLUTE MAXIMUM RATINGS (Ta =25°C)

Charactertstic Symbol value Unit

Supply Voltage Vee 10.S V

Any Input Relative to Vee
VN 0.3 V
(Except Pin 10)
Any Input Relative to GND
.VN -0.3 V
(Except Pin 10)
Power Dissipation Po SOO mW
Operating Temperature Topr -3O-+S0 OC
Storage Temperature

ELECTRICAL CHARACTERISTICS
Tstg -65-+1SO OC

I
(-3OOC<T.<6O"C unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

Supply Voltage Vee 3 10 V

Input "0" V,L 0 0.3Vee V
Input "1" V,H 0.7Vee Vee V
Input Pull-Up Resister R, 20 .100 KO
Tone Disable m Note 4 0 0.3Vee V
Tone Output . Vour' Note 1 -10 -7 dBm
Preemphasis, High Band 2.4 2.7 3 dB
Output Distortion, Measured
in Terms of Total Out-of-Band
Note 2 -20 dB
Power Relative to RMS sum of
Row and Column fundamental Power
Rise Time T RISE Note 3 2.8 S mS
Any R8Y Down Sink Current to GND IAKD At Vour-O.SV SOO uA
ADK Off Leakage Current IAKDO MVour=SV 2 uA
At Vee=3£N
Supply Current Operating Iso 2 mA
NoteS
AtVee =1OV
Supply Current Standby ISST 200 uA
NoteS
Tone Output-No Key Down NKD -80 dBm

Note: 1. Single-tone, low-group. Any Vee between 3.4V and 3.6V, odBm=O.nSV, RLOAO =10K see test circuit Fig 2.
2. Any dual-tone. Any Vee between 3.4V to 10.OV.
3. Time from a valid keystroke with no bounce to allow the waveform to go from min to 90% of the final magnitude of
either frequency. Crystal parameters defined as Rs=100n L=96mH, C=0.02pF, and Ch=SpF,' Vee~3.4V.
f,,3.579S4MHz±0.02%.
4. Only tones will be disabled when TD is taken to logical "0': Other chip functions may activate. Pull-up resistor on
TD input will meet same spec as other inputs. Logic O=GND
S. Stand-by condition is defined as no keys activated, Tl5=LogicaI1, Single Tone Inhibit=Logical O.
S. One key depressed only. Outputs unloaded.

c8 SAMSUNG SEMICONDUCTOR 147

KS5808 CMOS INTEGRATED CIRCUIT

PIN CONNECTIONS
PIN 1: Supply Voltage Vee ,PIN 19: Column Input C.
PIN 2: Tone Disable Input PIN 10: Any KeY Down
PIN 3: Column Input C, PIN 11: Row Input R.
PIN ,4: Column Input C2 PIN 12: Row Input Ra
PIN 5: Column Input Ca PIN 13: Row Input R2
PIN 6:GND PIN 14: Row Input R,
PIN 7:0SCIN PIN 15: Single Tone Inhibit
PIN 8: OSC OUT PIN 16: Tone Output'

Tone Output Test Circuit

vee 3- 10V
1

4 5

7 8 '9
lONE OUTPUT
o 0

-----l-------J I

Fig. 2
FUNCTION DESCRIPTION
1. Oscillator
The network contains an on·board inverter with sufficient loop gain to provide oscillation when used with a low cost tele-
7i
vision color-burst crystal. The inverter's input is osc in (pin and output is osc out (pin 8)., The circuit is designed to work
with a crystal cut to 3.579545MHz to give the frequencies in table 1. The oscillator is disabled whenever a keyboard input is
not sensed.
Table 1: Standard DTMF and output frequencies of the KS5808

~
Standard Tone Output Frequency Deviation
f DTMF using 3.57954MHz Crystal from Standard
Key Hz Hz %

f1 697 . 701.3 +0.62

f2 770 771.4 +0.19
ROW'
f3 852 857.2 +0.61
f4 941 9;35.1 . -0.63
f5 1209 1215.9 +0.57
f6 1336 1331.7 -0.32
COL
f7 1477 1471.9 -0.35
f8 1633 1645.0 +0.73

Most crystals don't vary more than 0.02%.ll).ny crystal frequency deviation from 3.5795MHz will be reflected in the tone
output frequency.

c8 SAMSUNG SEMICONDUCTOR 148

KS5808 CMOS INTEGRATED CIRCUIT

2. Output Waveform
The raw and column output waveforms are shown in Figure 3. These waveforms are digitally synthesized using on-chip
D/A converters. Distortion measurement of these unfiltered waveforms will show a typical distortion of 7% or less. The on-
chip operational amplifier of the KS5808 mixes the row and column tones together to result in a dual-tone waveform.
Spectral analysis of this waveform will show that typically all harmonic and intermodulation distortion components will be-
-30dB down when referenCed to the strongest fundamental (column tone): Figures 6 and 7 show a typical dual tone waveform
and its spectral analysis.

Typical Sinewave Output

a) Row Tones b) Column Tones

Fig. 3

3. Output Tone Level

The output tone level of the KS5808 is proportional to the applied DC supply voltagE!. Operation will normally be with a
requlated supply. This results in enhanced temperature stability, since the supply voltage may be made temperature stable.

4. Keyboard Configuration
Each keyboard input is standard CMOS with a pull-up resistor to Vee. These inputs may be controlled by a keyboard or
electronic means. Open collector TTL or standard CMOS (operated ciff same supply as the KS5808) may be used for electronic
control.
The switch contacts used in the key!loards may be void of precious metals, due to the CMOS network's ability to recog-
nize resistance up to 1KO as a valid key closure.

2 of 8 DTMF keyboard Electronic Input Pulses

' - - - - - - ' - ,7", COL :: ______ ~ _Ur,------COL

vee ,.-----ROW
'------ROW
GNO - - _______ U
Fig. 4 Fig. 5

C8 SAMSUNG SEMICONDUCTOR 149

 KS5808 CMOS INTEGRATED CIRCUIT

TYPICAL DUAL TONE WAVEFORM SPECTRAL ANALYSIS OF WAVEFORM

~1,_1) ~ _ _ :1ICIIoIIII¥I

, !
,
,
i

,
I, '\
•• .
I
•• • " I \
I
I
.
I

\,
•
I
I ./ I

"
.
, II• •
, \'. I .• \/i
I I
I
,.lJLlttl A IJ. ft. JLA'J'
r~w
~J
~
I
-- I'U', , ,
~1
-
\ 11'11'
1
i I

IIJO
~
I\.
\
1"-
I\.
Safe
I-- I-- Operatln! f-- f-
Pangs

1110

o
o 10 10 10 1110
T.rq. _ _
_ f _

Fig,S

c8 SAMSUNG SEMICONDUCIOR 150

KS5808 CMOS INTEGRATED CIRCUIT

PIN DESCRIPTIONS
1. Row and Column Input (Pin 3,4,5,9,11,12,13,14)
With Single Tone Inhibit at Vee. connection of GND to a single column will cause the generation of that column tone. Con-
nection of GND to more than one column will result in no tones being generated. The application of GND to only a row pin
or pins has no effect on the circuit. There must always be at least one column connected to GND for row tones to be gener-
ated. If a Single row tone Is desired. it may be gen!trated by tying any two column pins and the desired row pin to GND. Dual
tones will be generated if a single row pin and a single column pin are connected to GND.

2. Any Key Down Output (Pln10)

II
The any key down output is used·for electronic control of receiver and/or transmitter switching and other desired functions.
It switches to GND when a keyboard button is pushed and is open circuited when not. The AKD output switches regardless
of the tone disable and single tone inhibit inputs.

3. Tone Disable Input (Pin 2)

The Tone Disable input is used to defeat tone generation when the keyboard is used for other functions besides DTMF slg-
naing: It has a pull-up to Vee and when tied to GND tones are inhibited. All other chip functions operate normally.

4. Single Tone Inhibit Input (Pin 15)

The Single Tone Inhibit input is used to inhibit the generation of other than dual tones. It has a pull-<lown to GND and when
floating or tied to GND. any input situation that would normally result in a single tone will now result in no tone. with all
other chip functions operating normally.
When forced to Vee single or,dual tones may be generated as described in the paragraph under row and column inputs.

5. Tone Output (Pin 16)

The10ne output pin is connected internally in the KS5808 to the emitter of an NPN transistor whose collector is tied to V(X;.
The input to this transistor is the on-chip operational ampifier which mixes the row and column tones together and provides
output level regulation.

c8 SAMSUNG SEMICONDUCTOR 151

 KS5812 CMOS INTERGRATED CIRCUIT

QUAD UNIVERSIAL ASYNCHRONOUS

40 DIP
RECEIVER AND TRANSMITTER
The KS5812, QUAD-UART, is a SI-Gate CMOS IC which provides the
data formatting and control to interface serial asynchronous data com- '
. municatlons between main system and subsystems.
The parallel data of the bus system is serially transmitted and by .the
asynchronous data interface with proper formatting and error check·
ing. The KS5812. includes Transmit part, Receive part, Programmable
control part, Status check part, and Select part. The control register that
is programmed via the data bus during system initialization, provides
variable word lengths, clock division ratios, transmit control, receive con-
trol, and interrupt control.

FEATURES '."
• Low power, High speed CMOS process.
• Serial/Parallel conversion of Data
• 8-and 9-blt Transmission
• Optional Even and Odd Parity
• Parity, Overrun and Framing Error Checking
• Programmable Control Register
• Optional + 1, + 16, and + 64 Clock Modes
• Peripheral/Modern Control Functions
• Double Buffered
• One-or Two-Stop Bit Operation

BLOCK DIAGRAM PIN CONFIGURATION

CSoI - CE,
cs ,-
CS2,- SELECTION CE2
CS3,-
,-
AND
I LCE
TXDo
RXOo
os.,- CONTROL
LOGIC
E§.....
,......, UART, . Rffii
E CfSO .
RS; -
RNif -
£54 '- AF RXTXCLKO

RX,
TXD,
'-- ' - CE RXD,
'---C.J\ RTS,
r----y UART2
CTS,
.... AF f-:-
RXTXCLK,

( 8

L- l-
~
CE
TX02
RX02
m'S2
-rv AF' UART3
CTS2
RXTXCLK2
f- r----

TX03
~
r-- l- CE RXD3
'--~ R'fS3
UART4
CTS3
RESE T 1 AF RXTXCLK3

c8 SAMSUNG SEMICONDUCTOR 152

KS5812 CMOS INTERGRATED CIRCUIT

UART BLOCK DIAGRAM

DATA
DATA BUS BUS TRANSMIT DATA
BUFFERS

RECEIVE DATA

ADDRESS
CONTROL
AND
INTERRUPT
I
ABSOLUTE MAXIMUM RATINGS
Characteristic Symbol Value Uhit

Supply Voltage' Vee -0.3 to +.7.0 V

Input Voltage' Vin -0.3 to 7.0 V
Maximum Output Current" Ie 10 mA
Operating Temperature Top, -20 to +75 ·C
Storage Temperature T" g -55 to +150 ·C

·With respect to Vss (System GND)

"Maximum output current is the maximum current which can flow out from one output terminal or 1/0 common
terminal (00 - 0 7, RTS, Tx Data, IRQ) .
(Note) Permanent IC damage may occur if maximum ratings are exceeded. Normal operation should be under
recommended operating conditions are exceeded, it could affect reliability of IC.

RECOMMENDED OPERATING CONDITIONS

. Characteristic Symbol Min Typ Max . Unit

Supply Voltage 'Vee

, 4.5. 5.0 5.5 V
Input "Low" Voltage Vil' 0 - O.B V
Input "High" I 0 0 -07, RS, CTSi, RXPi
ViH '
2.0 - Vee
V
Voltage I CSa, CS2, 9S, RIW, E, CS3• CS., RXTXCLKi 2.2 - Vee
Operating Temperature Top, -20 25 75 ·C

, With respect to Vss (System GND)

c8 SAMSUNG SEMICONDU~R 153

KS5812 ' CMOS INTERGRATED CIRCUIT

DC' CHARACTERISTICS/Ycc= +5V±5%, Vss=ov, Ta= -20_+75°C, unless otherwise noted.)

. Characteristic Symbol Test Conditions . Min Typ Max Unit

Do-~, RS, CTSi, 2.0 - Vcc

Input "High" Voltage CSo, CS;, CS lo RtW, E, VIH 2.2 - Vcc V
CS3, CS; RXTXCLKi
Input "Low" Voltage Ali inputs VIL -0.3 - 0.8 V
Input Leakage Current Rm, CSo, CSlo CS2, E, CS3, CS. liN VIN=O-VCC -2.5 - 2.5 ~
Three-State (Off State)
Input Current
Do-D7 ITSI VIN=0.4-Vcc -10 - 10 ~

Do-D7
IOH= -400~ 4.1 - -
Output "High" Voltage VOH
IOH::S -10~ Vcc-O.1 - - V
IOH= -400 4.1 - -.
TXDi, RTSi
IOH::S -10~ Vcc-O.1 - -
Output ."Low" Voltage All outputs VOL IOH= 1.6mA - - 0.4 V
Output Leakage
Current (off state)
IRQ ILOH VOH=VCC - - 10 p.A

Do-D7 - - 12.5
VIN=OV, Ta=25°C
Input Capacitance E, RXTXCLKi, Rm, RS, RXDi, CIN pF
CSo, CS lo CS;, CTS, CS3, CS.
f= 1.0 MHz - - 7.5

Output Capacitance
RTS, TXDi
Coul
VIN=OV, Ta=25°C - - 10
pF
iRa f= 1.0 MHz - - 5.0
• Under transmitting and E=1.0 MHz - - 3
Receiving operation
• 500 kbps
E=1.5 MHz - - 4 mA
• Data bus in Rm operation E=2.0 MHz - - 5
• Chip is not selected
Supply Current • 500 kbps Icc E=1.0 MHz - - 200
• Under non transmitting
and receiving operation
• Input level (except E)
E= 1.5 MHz - - 250 p.A

VIH min = Vcc-0.8V

VIL max = O.SV
E;;2.0 MHz - - 300

c8 SAMSUNG SEMICONDUCTOR 154

KS5812 CMOS INTERGRATED CIRCUIT

'I I,"~

AC CHARACTERISTICS (Vcc=5.0V±5%, Vss=ov, Ta= -20 -+75~C, unless otherwise noted.)

1. TIMING OF DATA TRANSMISSION

KS5812
. Characteristic Symbol Test Conditions Unit
Min Max

+1 Mode
PWCL Fig. 1
900 - ns
+ 16, + 64 Modes 600 - ns
Minimum Clock Pulse Width
+1 Mode
PWCH Fig. 2
900 - ns
+ 16, + 64 Modes 600 - ns
+1 Mode - 500 KHz
Clock Frequency Ic
+ 16, + 64 Modes - 800 KHz
Clock-to-Data Delay lor Transmitter troD Fig. 3 - 600 ns
Receive Data Setup Time +1 Mode tRDSU Fig. 4 250 - ns
Receive Data Hold Time +1 Mode tROH Fig. 5 250 - ns
IRQ Release Time t'R Fig. 6 - 1200 ns
RTS Delay Time tATS Fig. 6 - 560 ns
Rise Time and Fall Time Except E tr, t, - 1000· ns

• 1.0/-ls or 10% 01 the pulse width, whichever is smaller.

2. BUS TIN!ING CHARACTERISTICS

1) READ

KS5812
Characteristic Symbol Test Conditions Unit
Min Max

Enable Cycle Time teveE Fig. 7 1000 - ns

Enable "High" Pulse Width PWeH Fig. 7 450 - ns
Enable "Low" Pulse Width PWeL Fig. 7 430 - ns
Setup Time, Address and RIW Valid
to Enable Positive Transition
tAs Fig. 7 80 - ns

Data Delay Time tOOR Fig. 7 - 290 ns

Data Hold Time tH Fig. 7 20 100 ns
Address Hold Time tAH Fig. 7 10 - ns
Rise and Fall Time lor Enable Input ter, tel Fig. 7. - 25 ns

c8 SAMSUNG SEMICONDUCTOR 155

KS5812 CMOS INTERGRATED CIRCUIT

t---tcycE----I
ENABLE
O.SV
tASf----++-,PWeH RWeL
IATS -ENABLE 2.2V
O.BV
VcC-2.0V
0.4V
te, tet
tODR

IRQ
____________________- J
tIR'--i

r- 2.0V
RS,CS;RiW

DATA BUS
• (1) IRQ Release Time applied to RxDi Register read
operation
(2) IRQ Release Time applied to TxDi Register write Fig. 7 Bus Read Timing Characteristics
operation . (Read Information from UART)
(3) IRQ Release Time applied to control Register
write TIE=O, RIE=O operation . 1----tcycE----i

•• IRQ Release Time applied to Rx Data Register PWeH

read operation right after read status register,
ENABLE
when IRQ is asserted by DCD rising edge.
Note: Note that following take place when IRQ is
asserted by the detection of transmit data register RS,cs,RiW
empty status. IRQ is released to "High"
asynchronously with E signal when CTSi goes
"High". (Refer to Figure 14)
DATA BUS
Fig. 6 R'fSi Delay and IRQ Release Time
Fig. 8 Bus Write Timing Characteristics
LOAD A LOAD B (Write information into UART)
(00- 07, ATSi, TXDi) (IRQ ONLY)

~
'OV

3KIl

TEST POINT o-~-t'-"""f---~ TEST POINT

C= 130pF for 0 0- 0 7
= 30pF for ATS and TXDi
A = 10KIl for 00- 07, i'iTS and TXDi
All diodes are 1S2074(8)0r Equivalent.
1 100pF

Fig. 9 Bus Timing Test Loads

MAAKING

SPACING

BIT TIME
1J r--T--T--TI--1--T--T--l
I I I I I
I___ 1.I __ .J.I __ --1I __ ...lI __ ..l..
9.09msec~
I
II
I.__ ..J....
I
I __
_ _ ..L
I
I
I
I
. II
I
I
I
I
I
I
L._

STAAT DO 01 02 03 04 05 D6 PAAITY STOP STOP

BIT BIT BIT BIT
I - - - - - - - - - - - - C H A A A C T E A TIME @10CPS(11 B I T S ) - - - - - - - - - - - t
100msec

Fig. 10 110 Baud Serial ASCII Data Timing

c8 SAMSUNG SEMICONDUCTOR 157

 KS5812 CMOS INTERGRATED CIRCUIT

DEVICE OPERATION character will

be automatically transferred into the Shift
Register when the first character transmission is,
At the bus interface, the UARTi appears as two completed. This sequence continues until all the
addressable memory locations. Intemally, there are four characters have been transmitted,
registers: two read-only and two write-only registers. The
read-only registers are Status and Receive Data; the RECEIVE
write-only registers are Control and Transmit Data. The
serial Interface consists of serial input and output lines Data is received from a peripheral by means of the
with independent clocks, and three peripheral/modem Receive Data input. A divide-by-one clock ratio is
control lines. provided for an extemally synchronized clock (to its data)
while the divid-by-16 and 64 ratios are provided for
internal synchronization,BIt synchronization In the
POWER ON/MASTER RESET dlvide-by-16 and 64 modes is Initiated by the detection
The master reset (CRO, CR1) should be set during of 8 or 32 low samples on the receive line in the divide-
system initialization to insure the reset condition and by·16 and 64 modes respectively. False start bit deletion
prepare for programming the UARTi functional confi- capability insures that a full half bit of a start bit has
guration when the communications channel is required. been received before the intemal clock is synchronized
During the first master reset, the IRQ and RTSI outputs to the bit time. As a character is beinll received, parity
are held at level 1. On all other master resets, the RfSj (odd or even) will be checked and the error indication
output can be pro.grammed high or low with the iRa will be available in the Status Register along with
output held high. Control bits CR5 and CAS should also framing error,overrun error, and Receive Data Register
be programmed to define the state of RfSj whenever full. In a typical receiving sequence, the Status Register
master reset is utilized. The UARTI also contains internal is read to determine if a character has been received
Power-on reset logic to detect the power line tum-on from a peripheral. If the Receiver'Data Register is full,
transition and hOld the chip In a reset state to prevent the character is placed on the 8-bit UARTi bus when a
erroneous output transitions prior to initialization. "fhis , Read Data command is received from the MPU. When
circuitry depends on clean power tum-on transitions. parity has been selected for a 7-bit word (7 bits plus
The power-on reset Is released by means of the bus- parity), the receiver strips the par.ity bit (07 = 0) so that
programmed master reset which must be applied prior data alone is transferred to the MPU. This feature
to operating the UARTi. After master resetting the reduces MPU programming. The Status Register can
UARTi, the programmable Control Register can be set continue to be read to determine when another
for a number of options such as variable clock divider character is available In the Receive Data Register. The
, ratiOS, variable word length, one or two stop bits, parity receiver is also double buffered so that a character can
(even, odd, or none), etc. be read from the data register as another character is
being received In the shift register. The above sequence
continues until all characters have been received,
TRANSMIT
A typical transmitting sequence consists of reading
.the UARTi. Status Register, either as a result of an
INPUT/OUTPUT FUNCTIONS
interrupt or in the UARTi's tum in a polling sequence. UART INTERFACE SIGNALS FOR MPU
A character may be written into the Transmit Data'
The KS5812 interfaces to the MPU with an 8-bit
Register if the status read operation has indicated that
bidirectional data bus, five chip select lines, a register
the Transmit Data Register is empty. This character is
select line, an interrupt request line, read/write line, and
transferred to Shift Register where it is serialized and
enable line, These signals permit the MPU to have
transmitted from the Transmit Data output preceded by
complete control over the KS5812.
a start bit and followed by one or two stop bits. Internal
parity (odd or even) can be optionally added to the UART Bidirectional Data (DO-07) - The bidirectional
character and will occur between the last data bit and data lines (00-07) allow for data transfer between the
the first stop bit. After the first character is written in KS5812 and the MPU. The data bus output drivers are
the Data Register, the Status Register can be read again three-state devices that remain in the high-impedance
to check for a Transmit Data Register Empty condition (off) state except when the MPU performs an UARTi read
and current peripheral status. If thelReglster is empty, operation.
another character can be loaded for transmission even
_ UART Enable (E) - The Enable signal, E, is a high-
though the first character is i,n the process of being ,
impedance TTL-compatible input that enables the bus
transmitted (because of double buffering). The second

c8 SAMSUNG SEMICONDUCTOR 158

KS5812 CMOS INTERGRATED CIRCUIT

inputloutput data buffers and clocks data to and from Receiver Interrupt Enable is set and the Receive Data
the KS5812. Register Full (RDRF) status bit Is high, an Overrun has
occurred. An interrupt resulting from the RDRF status
ReadlWrite (R/W') - The Read/Write line Is a high·
bit can be cleared by reading data or resetting the
impedance input that is TTL compatible and is used to
UARTi. Interrupts caused by Overrun is cleared by read-
control the direction of data flow through the UARTi's
ing the status register after the error condition has
input/output data bus Interface. When Read/write Is high
occurred and then reading the Receive Data Register
(MPU Read cycle), KS5812 output drivers are tumed on
or resetting the UARTi. The receiver interrupt Is masked
and a selected register is read, When It is low, the
by resetting the Receiver Interrupt Enable.
KS5812 output drivers are tumed off and the MPU writes
into a ~elected register. Therefore, the Read/write signal
is used to select read-only or wrlte-only registers within
CLOCK INPUTS
the KS5812. High-Impedance TTL-compatible inputs is provided
for clocking of transmitted and received data. Clock
Chip Select (CSO, CS1, CS2, CS3, CS4) - These five frequencies of 1, 16, or 64 times the data rate may be
high-impedance TTL-compatible input lines are to select selected.
and address the KS5812. Each UART can be enabled
when CS2 and CS3 are high and CS4 is low. CSO and RECEIVE AND TRANSMITTER CLOCK
CS1 are used 'to select individual UART.
(RXTXCLKI)
CSO CS1 CS2 CS3 CS4 UARTi -The RXTXCLKi input are both used for the clocking
of transmitted data and for synchronization of received
0 0 1 1 0 UART1
data. (In the 11 mode, the clock and data must be
0 1 1 1 0 UART2 synchronized extenally.) The transmitter initiates data
1 0 1 1 0 UART3 on the negative transition of the clock and the receiver
samples the data on the "positive transition of the clock.
1 1 1 1 0 UART4

Register Select (RS) - The Register Select line is a SERIAL INPUT/OUTPUT LINES
high-impedance input that is TTL compatible. A mgh Receive Data (RXDI) - The Receive Data line is a
level is used to select the Transmit/Receive Data high-impedance TTL-compatlble Input through which
Registers and a low level the Control/Status Registers. data is received in a serial format. Synchronization with
The Read/write signal line Is used In conjunction with a clock for detection of data Is accomplished intemally
Register Select to select the read-Only or write-only when clock rates of 16 or 64 times the bit rate are used.
register in each register pair. Transmit Data (TXDI) - The Transmit Data output
Interrupt Request (IRQ) - Interrupt Request is a TTL· line transfers serial data to a modem or other peripheral.
compatible, open-drain (no internal pullup), active low
output that is used to interrupt the MPU. The ma output PERIPHERAUMODEM CONTROL
remains low as long as the cause" of the Interrupt is
- The UARTI includes several functions that permit
present and the appropriate Interrupt enable within UTe limited control of a peripheral or modem. The functions
KS5812 is set. The iRQ status bit, when high, indicates
included are Clear-to-Send, Request-to-Send and Data,
the IRQ output is in the active state. Carrier Detect.
Interrupts result from conditions in both the
transmitter and receiver sections of the UARTi. The Clear-to-5end (CTSI) - This high-impedance TTL-
transmitter section causes an Interrupt when the compatible Input provides automatic control of the
Transmitter Interrupt Enabled condition is selected transmitting end of a communications link via the
(CR5-CR6), and the Transmit Data Register Empty modem Clear-to-Send active low output by inhibiting the
(TORE) status bit is high. The TORE status bit indicates Transmit Data Register Empty (TORE) status bit.
the current staWs of the Transmitter Data Register
Request·to-Send (RTSI) - The Request-to-Send
except when inhibited by Clear-to-Send (Ci'Sl) being
output enables the MPU to control a peripheral or
high or the UARTi being' maintained in the Reset
modem via the data bus. The R'i'Si output corresponds
condition', The interrupt is cleared by writing data into
to the state of the Control Register bits CR5 and CR6.
the Transmit Data Register. The Interrupt is masked by
disabling the Transmitter Interrupt via CR5 or CR6 or
= =
When CAS 0 or both CR5 and CAS 1, the RTSi output
is low (the active state). This output can also be used
by the loss of CfSi which Inhibits the TORE status bit.
for Data Terminal Ready (DTR).
The Receiver section causes an interrupt when the

c8 SAMSUNG SEMICONDUCTOR ,159

 KS5812 CMOS INTERGRATED CIRCUIT

TRANSMIT DATA REGISTER (TDR) CR1 CRO Function

Data is written in the Transmit Data Register during a a +1
the negative transition of the enable (E) when the UARTi a 1 +16
has been addressed with RS high and RiW low. Writing 1 a +64
data into the register causes the Transmit Data Register 1 1 Master Reset
Empty bit in the Status Register to go low. Data can then
be transmitted. If the transmitter is idling and no Word Select Bits (CR2, CR3, and CR4) - The Word
character Is being transmitted, then the transfer will take Select bits are used to select word length, parity, and
plaoe within 1-bit time of the trailing edge of the Write the number of stop bits. The encoding format is as
, command. If a character is being transmitted, the new follows;
data character will commence as soon as the previous
character is complete. The transfer of data causes the CR4 CR3 CR2 Funcfl(m
Transmit Data Register Empty (TORE) bit to Indicate
empty. . a a a 7 Bits + Even Parity + 2 Stop Bits
a a 1 7 Bits + Odd Parity + 2 Stop Bits
a 1 a 7 Bits + Even Parity + 1 Stop Bit
RECEIVE DATA REGISTER (RDR) a 1 1 7 Bits + Odd Parity + 1 Stop Bit
1 a a 8 Bits + 2 Stop Bits
Data is automatically transferred to the empty Receive
1 a 1 8 Bits + 1 Stop Bit
Data Register (RDR) from the receiver deserializer (a
1 1 a 8 Bits + Even Parity + 1 Stop Bit
shift register) upon receiving a complete character. This
1 1 1 8 Bits + Odd Parity + 1 Stop Bit
event causes the Receive Data Register Full bit (RDRF)
in the status buffer to go high (full). Data may then be
Word length, Parity Select, and Stop Bit changes are
read through the bus by addressing the UARTi and
not buffered and therefore become effective
selecting the Receive'Data Register with RS and RIW
immediately.
high when the UARTi is enabled. The non-destructive
read cycle causes the RDRF bit to be cleared to empty Transmitter Control Bits (CR5' and CR6) - Two
although the data is retained in the RDR. The status is Transmitter Control bits provide for the control of the
maintained by RDRF as to whether or not the data is interrupt from the Transmit Data Register Empty
current. When the Receive Data Register is full, the cOndition, the Request-to-Send (RTSi) output, and !he
automatic transfer of data from the Receiver Shift transmission of a Break level (space). The follOWing
Register to the Data Register is inhibited and the RDR , encoding format is used:
contents remain valid 'with its current status stored in
CR6 CR5 Function
the Status Register.
a a RTSi = low, Transmitting Interrupt
Disabled.
CONTROL REGISTER RTSi = low, Transmitting Interrupt
a ,1
The UARTi Control Register consists of eight bits of Enabled.
write-only buffer that are selected when RS and Rm are 1 a RTSi = high, Transmitting Interrupt
low. This register controls the function of the receiver, Disabled.
transmitter, interrupt enables, and the Request-to-Send 1 1 RfS1 = low, Transmits Break level on
peripheral/modem control output. the Transmit Data Output.
Transmitting Interrupt Disabled.
Counter Divide Select Bits (CRO and CR1) - The
Counter Divide Select Bits (CRa and CR1) determine the Receive Inten-upt Enable Bit (CR7) - The following
divide ratios utilized in both the transmitter and receiver interrupts will be enabled 'by a high level in bit position
sections of the UARTi. Additionally, these bits are used 7 of the Control Register (CR7). Receive Data Register,
to provide a master reset for the UARTi which clears the
Full Overrun.
Status Register (except for external conditions on CTSi
and DCD) and initializes both the receiver and
transmitter. Master reset does not affect other Control STATUS REGISTER
Register bits. Note that after power-on or a power Information on the status of the UARTi is available
. fail/restart; these bits must be set high to reset the to the MPU by reading the UARTi Status Register. This
UARTi. After resetting, the clock divide ratio may be read only register is selected when RS is low and RiW
selected. These counter select bits provide for the is high. Information stored in this register indicates the
following clock divide ratios:

c8 SAMSUNG SEMICONDUCTOR 160

/ .
 KS5812 CMOS INTERGRATED CIRCUIT

status of the Transmit Data Register, the Receive Data available.

Register and error logic, and the peripheral/modem Receiver Overrun (OVRN), Bit 5 - Overrun is an error
status inputs of the UARTi flag the indicates that one or more characters in tlie data
Receive Data Register Full (RDRF), Bit 0 - Receive stream were lost. That is, a character or a number of
Data Register Full indicates that received data has been characters were received but not read from the Receive
transferred to the Receive Data Register. RDRF Is Data Register (RDR) prior to subsequent characters
cleared after an MPU read of the Receive Data Register being received. The overrun condition begins at the
or by a master reset. The cleared or empty state midpoint of the last bit of the second character re?eived
indicates that the contents of the Receive Data Register in succession without a read of the HDR having
are nof current. Data Carrier Detect being high also occurred'. The Overrun does not occur 'in the Status
causes RDRF to indicate empty. Register until the valid character prior to Overrun has

II
been read. The RDRF bit remains set until the Overrun
Transmit Data Register Empty (TORE), Bit 1 - The Is reset. Character synchronization Is maintained during
Transmit Data Register Empty bit being set high the Overrun condition.' The Overrun indication is reset
indicates that'the Transmit Data Register contents have after the reading of data from the Receive Data Register
been transferred and that new data may be entered. The or by a Master Reset.
low state indicates that the register is full and that
transmission of a new character has not begun since Parity Error (PEl. Bit 6 - The parity error flag indicates
the last write data command. that the number of highs (ones) in the character does
not agree with the preselected odd or even parity. Odd
Clear-to-Send (eft), Bit 3 - The Clear-to-Send bit parity is defined to be when the total number of ones
indicates the state of the Clear-to-5end input from a Is odd. The parity error indication will be present as long
modem. A low CTS indicates that there is a Clear-to- as the data character ,is in the RDR. If no parity is
Send from the mOQem. In the high state, the Transmit ,selected, then both the transmitter parity generator
Data Register Empty bit is inhibited and the Clear-to- output and the receiver parity check results are
Send status bit will be high. Master reset does not affect inhibited.
the Clear-to-5end status bit.
Interrupt Request (IRQ), Bit 7 - The IRQ bit indicates
Framing Error (FE), Bit 4 - Framing error indicates the state of the IRQ output. Any interrupt condition with
that the received character, is improperly framed by a its applicable enable will be indicated in this status bit.
'start and a stop bit and is detected by the absence of Anytime the IRQ output is low the IRQ bit will be high
the first stop bit. This error indicates a synchronization to indicate the interrupt or service request status. IRQ
error, faulty transmission, or a break condition. The is cleared by a read operation to the Receive Data
framing error flag is set or reset during the receive data Register or a write operation to the Transmit Data
transfer time. Therefore, this error indicator Is present Register.
throughout the time that the associated character is

c8 SAM~UNG SEMICONDUCTOR 161

 PRELIMINARY
KS5819/KS5821 CMOS INTEGRATED CIRCUIT

TONE/PULSE DIALER WITH REDIAL

The KS5819121 is a DTMFIPULSE switchable dialer with a 32-digit
redial memory. Through pin selection, switching from pulse to DTMF
mode can be done using slide switch or by depressing IT] key. All
necessary dual-tone frequencies are derived from a 3.579545MHz TV
crystal, providing very high accuracy and stability. The required
sinusoidal wave form for each individual tone is digitally synthesized
on the chip. The wave form so generated has very low total harmonic
distortion (7%). A voltage reference is generated on the chip which is
stable over the operating voltage and temperature range and regulates
the signal levels of the dual tones to meet telephone industry
specifications. CMOS technology is used to produce this device, resulting
in very low power requirements high nOise. immunity, and easy interface
to a variety of telephones requiring few external components.

22 SHRINK DIP
FEATURES
• Tone/Pulse switchable (touch key or slide switch).
• 32 digit capacity for redial
• Automatic mix redialing (last number. dial) of PULSE--DTMF with
multiple auto access pause
• Key-in-tone output for valid key entry in pulse mode
(Fkf= 1_8KHz, Tkf = 25mS).
• Low power CMOS process (2.0 to 5.5V)
• Numbers dialed Manually after redial are cascadable and stored as
additional numbers for next rediallng
• Uses inexpensive TV crystal (3.579545MHz)
• Make/Break ratio (33 1/3-166 213 or 40/60) pin selectable
• Touch key hooking (580ms)
• Low standby current
• KS5821 Includes Telephone Locking Function

ORDERING INFORMATION PIN 'CONFIGURATION

Package KS5819 KS5821 Dial Pulse PPS
300mil KS58A19N KS58A21N DP 10
Width KS58B19N KS58B21N DP 20
Normal KS58C19N KS58C21N DP 10
Size KS58D19N KS58D21N DP 20
400mil KS58A19E KA58A21E DP 10
Width KS58B19E KA58B21E DP 20 MUTE, n: (KS5821 ONLY)
Size KS58C19E KA58C21E DP 10 iYlOl5EOiJ'i' 7
KS58D19E KA58D21E .DP 20 MODE SELECT 8
Shrink KS58A19P KA58A21P DP 10 14 OPERATION SELECT
Package KS58B19P KA58B21P DP 20 OSC OUT
Type KS58C19P KA58C21P DP 10
KS58D19P KA58D21P DP 20

c8 SAMSUNG SEMICONDUCTOR 162

 PRELIMINARY
KS5819/KS5821 CMOS INTEGRATED CIRCUIT·

BLOCK DIAGRAM

R1

R2 MQ5E6[j'f

R3 KEY IN TONE

R4
KEYBOARD
,----
I
... OUTPUT
LOGIC
X'MIT MUTE
REDIAL I
I
I
LOGIC MUTE (KS5819)
C1 1----.--1 MEMORY TELEPHONE
LOCK IT (KS5821)
32 DIGIT
C2 I(KS5821 ON Ly)1 DP
I I
C3 L_T-_..J
C4

Voo
DTMF
GENERATOR

TONE OUT

OSC IN OSC OUT

TONE DURATION & PAUSE IN TONE FREQUENCIES

REDIAL
Input Specified Actual % Error.
Characteristic Symbol Typ Unit R1 697 699.1 +0.31
Tone Duration To 74 mS R2 770 766.2 -0.49
Minimum Pause ITP 110 mS R3 852 847.4 -0.54
Cycle Time Tc 184 mS R4 941 948.0 +0.74
C1 1209 1215.7 +0.57
C2 1336 1331.7 -0.32
C3 1477 1471.9 -0.35

ARRANGMENT OF KEYBOARD

[2]000 - R1

0QJ0~ - R2 rn PULSE·DTMF SWITCHING

. IHKl HOOKING (580ms)
IE
0000 - R3 [ftQI
PAUSE (3.6 second)
REDIAL

~~[]]§] - R4
I I I I
C1 C2 C3 C4

c8 SAMSUNG SEMICONDUCTOR 163

 PRELIMINARY
KS5819/KS5821 CMOS INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Ta=25°C)

Chllracteristics Symbol Value Unit

Supply Voltage Voo 6.0 V

Input Voltage VIN Vss-0.3, Voo+0.3 V
Output Voltage Your Vss-0.3, Voo +0.3 V
Output Voltage Your 1.2 V
Tone Output Current hONE 50 mA
Power Dissipation Po 500 mW
Operating Temperature Topr -20-+70 °C
Storage Temperature Tstg -40 -+ 125 °C

ELECTRICAL 'CHARACTERISTICS
(Vss.= ov, Voo = 3.5V, fx'tal = 3.579545MHz, Ta = 25°C, unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

Operating Voltage VooP Pulse Mode All inputs connected 2.0 5.5
V·
Range VooT Tone Mode I to Voo or Vss 2.0 5.5
Memory Retention 'Voltage VOR 1.0 V

looP MODE=Voo One key. selected 0.4 1.0

Operating Supply Current HS=v ss. All outputs mA
looT MODE = Vss unloaded 1.0 2.0

1801 HS=Voo= 1.5V No key selected. 0.03 0.05

Standby Current All outputs p.A
Is02 HS=Vss unloaded 70 140

Output Gurrel)t
IOL1 DP, MUTE)I
. VOL =O.4V
I Voo=3.5V 1.7 5.0
mA
IOL2 XMUTE, iT(KS5821) I V = 2.5V
DO 0.5 1.5
Input Leakage Current IOFF MODE OUT, KT Vour= 2.5V 1.0 p.A
VIH R1-R4, 'C1-C3, HS, MIB 0.8Voo Voo
Input Voltage V
VIL OPERATION SELECT, MODE SELECT Vss 0.2Voo
hN1 Voo =3.5V VIN=OV 116
Input Current R1-R4 p.A
IIN2 .voo=2.5V VIN=OV 50
Valid Key Entry Time Tkd 23 25.3 mS
Column and. Row
Fer 445 Hz
Scanning Frequency
Key-In Tone Output D~ration Tkt 23 mS
Key-In Tone Frequency Fkt 1.8 KHz
Auto Access Paulle Time Tap 3.6 sec
Voo=2.5V, RL=5K ROW TONE -16.0 -12.0
Tone Output Vor dBV
Voo =3.5V RL=5K ONLY -14.0 -11.0
Ratio of Column to Row Tone dBer Voo=3.5V 1.0 2.0 3.0 dB
Distortion %DIS Voo= 3.5V 10 %
Tone Output Delay Time Tpad 1.5 mS

c8 SAMSUNG SEMICONDUCTOR 164

 PRELIMINARY
KS5819/KS5821 CMOS INTEGRATED CIRCUIT

PIN DESCRIPTION
Pin Name Description

1-4 R1-R4 Keyboard (R1, R2, R3, R4, C1, C2, C3, C4)
15-22 C1-C4 These inputs can be interfaced to an XV matrix keyboard. C,- C. & R, - R. are
set to low at On Hook (HS = high). C,- C. key inputs are set to low and R1-R4
are set to high at OFF HOOK (HS = low) which enables the key-input operation.
Oscillator starts running when a key press is detected.
Scanning signals are presented at both column and row inputs (TYP: 445Hz)
until the input key is released. Key inputs are compatible with standard 2-of-8

5 HS
form or single-contact keyboard. Debouncing is provided to avoid false entry
(TVP: 23mS).
Hook Switch
This input detects the state ot" the hook switch contact.
"Off Hook" corresponds to Vss condition.
I
"On Hook" corresponds to Vo~ condition.
6 M/B Make/Break Ratio
This input provides the selection of the Make/Break ratio (33.3: 66.6/40:60) when
M/B is connected to VoolVss.
7 MODE OUT Mode Output
This output indicate whether the chip is operating in pulse or tone mode.
PulselTone mode corresponds to OFF/ON state (N channel open drain). Mode
state is controlled with Operation Select, Mode Select and ITl key inputs.
8 MODE SELECT Mode Select Input
Pulse/DTMF mode is selected as shown in the following table.
Initial Mode means the state after going Off Hook (HS .... "Vss")

OPERATION MODE INITIAL SWITCHING

NOTES
SELECT SELECT MODE ENTRY MODE

IT] Key-In MODE SELECT

Voo Pulse
defines only initial mode
Voo after going Off Hook and is
Vss Tone N/A latched at first key entry.
MODE SELECT IT] key is disabled under
Voo Pulse
Vss inpuf=Vss this condition.
Vss Tone N/A

If choice of switching method is desire~ (either IT! key or MODE SELECT).

Operation select should be connected to MODE SELECT in order to avoid false
operation.
9 OSCIN Oscillator Input/Output
10 OSC OUT These pins are provided to connect an external 3.58MHz crystal. Oscillator starts
(at Off Hook) and is sustained until pulse or DTMF single are finished.
11 Voo Power
12 Vss These are the power supply inputs. This device is designed to operate on 2.0V
to 5.5V.

c8 SAMSUNG SEMICONDUCTOR 165

 PRELIMINARY
·KS5819/KS5821 CMOS INTEGRATED CIRCUIT

PIN DESCRIPTION (Continued)

Pin N~me Description

13 KEY IN TONE Key In Tone Output

Key in tone signal is provided only in pulse mode for all Key-ins except IT! key-
-'.
in. No KEY IN TONE generated in DTMF mode. Fkt: 1.8KHz, Tkt: 23mS.
(N channel open drain)
14 OPERATION Operation Select Input
SELECT Mode switching. (from Pulse to DTMF) entry is selectable with this input, i.e.
whethere IT] key entry or MODE SELECT input entry is selectable via this pin.
15 TONE OUT DTMF Signal Output
When a valid keypress is detected in DTMF mode Appropriate low group and
high group frequenGies are generated which hybrided the Dual Tone Output
Tone out is Off State in pulse mode.
16 X'MIT MUTE X'mit Mute Output

HS X'mit Mute Output

Voo "OFF."
Normally "OFF"
Vss
"ON" during pulse and DTMF dialing
(N channel open drain)
17 MUTE Mute OutputiTelephone Lock Output (KS5821)
TL (KS5821)
HS (KS5819) MUTE OUTPUT (KS5819)
Telephone (KS5821) Telephone Lock Output (KS5821)
V OD OFF (KS5819)
Locked (KS5821) ON (KS5821)
Normally "OFF" in DTMF mode.
- Vss
"ON" during pulse dialing (KS5819)
Unlocked (KS5821)
Normally "OFF" (KS5821)
(N channel. open drain)
18 DP, DP Dial Pulse Out DP: C/O, DP: AlB

c8 SAMSUNG SEMICONDUCTOR 166

 PRELIMINARY
KS5819/KS5821 CMOS INTEGRATED CIRCUIT

KEYBOARD OPERATION
1. SINGLE MODE OPERATION
• Pulse Mode Operation

I Off Hook lB··· B

Pulse mode is defined by the initial mode after going Off Hook and latched at IQ1I key entry. This is the condition
under Mode Select - Voo .

• Tone Mode Operation

I Off Hook I· B ~ .. B
Tone mode is defined by the initial mode after going Off Hook and latched at [Q1J key entry. This condition is under
Mode Select = Vss.
II
Off Hook I8 B···8
If initial mode is at pulse mode after going Off Hook and Mode Select - Voo, Operation Select= Voo. Switching
mode from pulse to tone can be done by IT] key entry and latched at IQ1] key entry.

• Manual Dialing with Automatic Access Pause

I Off Hook I G [~] B··:B

Multiple Pause key entries can be accepted and stored in the redial memory, each as on digit. Each lEI key provides
3.5 sec;:onds pause time, but lEI key entry as first digit after going Off Hook is ignored. 0 key can also be used
as pause key in pulse mode. Pause (s) can be cancelled with le], rn m or key during pause time in redialing.
[Q] = Any numeric key.

• Redialing

I Off Hook I EJ
Up to 32 digits can be dialed with ~ key. IBQJ key is disabled while pulse or DTMF signals are transmitting.
When more then 32 digits are stored in redial memory. Redial is also inhibited.
00 key can be used as ~ key in pulse mode.
• Inhibiting Redial

I Off Hook I EJ .. ·8 EJ EJ
Redial can be inhibited by depressing [BQJ IBQJ keys after DTMF or pulse signals are transmitted.

• Inhibiting Dial (KS5821 only)

I Off Hook I B 8 EJ EJ
m
EJ EJ EJ
Dial can be inhibited by depressing lIm! lIm! keys after the just for digit keys's signals are transmitted. You
must remember the four digit keys to release the Lock State. If you want to release the Lock State, you must depress
IQj] ~ ~ IIMI keys which are the same sequence as the four digit keys. Otherwise, You must applyS(rising
edge pulse) to the MIS input.

c8 SAMSUNG SEMICONDUCTOR 167

 PRELIMINARY
KS5819/KS5821 CMOS INTEGRATED CIRCUIT

2. PULSEITONE SWITCHABLE OPERATION

• Mode Switching by MODE SELECT Input (OPERATION SELECT=Vss)

Off Hook I 8··· [3 [:J Switching MODE SELECT to Vss B···lon+ml

I Pulse Mode I f-- OTMF MOde---i

Pulse mode is initially defined MODE SELECT = Voo , mode switching to DTMF can be accepted by MOOE
mEaT"= Vss, OTMF mode will be set up after pulse mode is finished. In this mode, digits ~ ... IDn + ml are
transmitted from Tone Out as OTMF signals by depressing corresponded keys.
If no lEl·key is contained serially before or after' mode switching.

Off Hook B....G ISwitching MODE SELECT to Vssl B·· ·1 On + m I

I Pulse Mode I I-- OTMF Mode ~
(On, On + I :/= Pause) .

It results the next condition.

If digit IOn + 11 is depressed after pulse mode is finished, OTMF mode will be set up after last pulse Signal ( On )
is output. In this mode, digits ~ ... ~ are transmitted from Tone Out as OTMF signals by depressing
corresponded keys. If digit IOn + 11 is depressed during'dialing pulse signals. OTMF mode but in Hold State will
be set up after last pulse signal ~ is finished. MODE OUT will flash to indicate this Hold Statel:Dii±] ... IOn + ml
are stored in redial memory as OTMF data and not transmitted from Tone Out. When 'it is ready to transmit OTMF
data in redial memory, Ill, IID2l or [eJ ,keys is depressed to reset this Hold State and IQil±] '" IOn + ml data are
serially t r a n s m i t t e d . ' ,

• Mode Switching by II] key,(OPERATION SELECT=Voo)

,Off Hook I B · .. B EJ ~ B .. ·I on+ml

I Pulse Mode I f.------- Tone MOde---1

Pulse mode is initially defined with MODE SELECT = VOD • Mode switching to OTMF can be accepted by,IT] key.
In OTMF mode, digits IOn + 11 ... IOn + ml are transmitted from Tone Out as OTMF signals by depressing corresponded
key. If no IfI key is contained serially before or after IT! key.

1 Off Hook lB··· B ~ B··

r--
l--- Pulse Mode --j
·1
Tone, Mode
On+m

---l
I (On, on+1*[~}

It results the next condition:

If digit IOn + 11 is depressed after pulse mode is finished OTMF mode will be set IJP after last pulse signal. ~ is out.
In this mode, digits ~ ... IOn + ml are transmitted from TONE OUT as OTMF Signals by depressing corresponded
key.

c8 SAMSONG SEMICONDUCTOR' 168

 PRELIMINARY
KS5819/KS5821 CMOS INTEGRATED CIRCUIT

If digit [Jm:±] is depressed during dialing pulse signal. DTMF mode but in Hold State will be set up after last
pulse signal ~ Is finished. When DTMF MODE is set up. MODE OUT will be flash to Indicate this Hold State.
Digits IOn + 11 ... IOn + ml are stored in redial memory as DTMF data and not transmitted from Tone Out.
When it is ready to transmit DTMF data in redial memory. rn. m or IPl keys is depressed to reset this Hold State
, and IOn + 11 ... IOn + ml data are serially transmitted.

• Redial with Hold State Cancell

, Off Hook "8 0 G. B (or key)

. Pause time can be cancelled with 1Pl. IIJ or [BQJ keys during pause time in redialing. Any pause in series with
corresponding pause is also cancelled. When any pause is not stored before or after mode switching. chip will
go into the Hold 'State when DTMF mode is set up. MODE OUT will flash to indicate this Hold State. DTMF data
are stored in redial memory and not transmitted from tone out.
I
rn. [Bt!I or IPl keys is depressed to reset this Hold State and DTMF data are serially 'transmitted.

Single Tone Operation in DTMF Mode (Test mode)

The MIS pin is used to trig the chip Into test made by applying a positive or negative pulse to this input after "Off
t:look." Test mode is sustained until On Hook. The Single tone is shown in the following table which contrast with
normal mode.

Normal mode Single tone mode.

R1 1 2 3 R1 R1 C2 C3
R2 4 5 6 R2 C1 C2 R2
R3 7 8 9 R3 R3 C2 C3
R4 • 0 #I R4 C1 R4 C3
C1 C2 C3

c8 SAMSUNG SEMICONDUCTOR 169

 PRELIMINARY
KS5819/KS5821 CMOS INTEGRATED CIRCUIT

TONE MODE TIMING (MODE SELECT=Vss)

~1~~________~r1~ __________
-----1Df--
KEY INPUT ~'---"""'IIIIII 31 ~~

OSC -------D------_-~---.-------illllllllllllllllllllllill1IIIIIIIIIIIIIIIIIIIIr-------
MUTE~ U
MODE OUT I r~L....--'-________
D:TITP:Debounci
146mSngToultime:: 146mS
23mS
PULSE MODE TIMING (MODE SELECT = Voo)

~~~----------------------
.
KEYINPUT---,m~

~
----1U
---.---
D

3
. _ . _ - - - - -

KEY TONE --"""'IITII!_--_r-'."---.:...--------....:...-----

=ll=TKT mil
UUUU'----·TIDP----<1 LJULJ
DP nf1JU!--TIDP-~1
--------1--lB ~ --j M~
nnn ----

X'MITMUTE ...J"I. . ._.-.--____________......J

F.IDTE
r-l .1
--I J ' - - - - - - - - -_ _ _ _ _---J.
(KS5819 only)

osc ------11111111111111,1--1·---FOSC = 3.579545MHz --------Imlllllllllll~--------

D
TID(Debounci
P: 823mSng Ti1.m7e):5KHz23mS TKT: 25mS
'KT:

·-cR SAMSUNGSEMICONDUCTOR 170

 PRELIMINARY
KS5819/KS5821 CMOS INTEGRATED CIRCUIT

TIMING DIAGRAM
(for Switching Mode Operation by ITl key) (OPERATION SELECT, MODE SELECT - =V oo)

HS~~ _______________________________________________
KEY INPUT -----"mi

MODEOUT--------------------------------------~

5P -----...,LJlj
TONE OUT ---------------------iJ,
U---TAP,------!i

ilL.rLPL
~
TOUT
II
X'MIT MUTE
rI'--_ _ _ _ _ _ _ _---'FTMOP~
--.I L . . .
.---....,' T,OP
I
(KS5S19 only)

osc -------i.IIIIIIII.IIIIIII====~FO~SC3~.5795~45~MHz~===311111Imllllll~II.IIIIIIIt----
·TIMING DIAGRAM
(for Switching Mode Operation by MODE SELECT Input) (OPERATION SELECT=Vss)

KEY INPUT - - o W
Switching MS =Vss

MODEOUT-------------------~

I
5P---""'LJU LJlJlJ=TAP~ 1
I

i
TONEOUT--------------------f',
I
i"L.rLr"l 1....----

X'MIT MUTE ~~_ _ _ _ _ _ _ _ _ _ _ _.J_-T-MO-pL_ _ _ _ _...I

MUTE~"'-------------~ (KS5S19 only)

MODE SELECT---_ _ _ _ _ _ _ _ _ _ _' - - - .

osc -------IIIIIIIIIIIIIIIIIt-------FOSC=3.579MHZ-----t11111111IIIIIIIr-----

c8 SAMSUNG SEMICONDUCTOR 171

 PRELIMINARY
1<S582O CMOS INTEGRATED CIRCUIT

TONE/PULSE DIALER WITH REDIAL

18 DIP
The KS5820 is a DTMF/PULSE switchabledialer with a 32-diglt redial
memory. Through pin selection, switching from pulse to DTMF mode
can be done using slide switch. All necessary dual-tone frequencies are
derived from a 3.579545MHz TV crystal, providing very high accuracy
and stability. The required sinusoi.dal wave form for each individual tone
is digitally syntheSized on the chip. The wave form so generated has
very low total harmonic distortion (7% Max). A voltage reference is
generated on the chip which Is stable over the operating voltage al)d
temperature range and regulates the Single levels of the dual tone to
. meet telephone industry specification. CMOS technology is used to
produce this device, resulting very low power requirements high noise
immunity, and easy Interface to a variety of telephones requiring extemal
components.

FEATURES ORDERING INFORMATION

• Tone/Pulse swltchable (slide switch). Dial
Dial
• 32 digit capacity for redial Type Pulse Tklp Make/Break Ratio
Pulse
• Automatic mix redlallng (last number dial) of Rate
PULSE .... DTMF with multiple auto access pause
• PABX auto·pause for 3.6 sec. 10 823 Voo: 33.3166.6
KS58A2ON DP
• 4 lC 4 or (2 of 8) keyboard available
(PPs) (mS) Vss: 40/60
• Low power CMOS process (2.0 to 5.5V) 20 823 Voo: 33.3/66.6
• Numbers dialed Manually after redial are cascadable KS58B2ON DP
(PPs) (mS) Vss: 40/60
and stored as additional numbers for next redlaling
• Uses inexpclnsive TV crystal (3.579545MHz) 10 823 Voo: 33.3/16.6
• Make/Break retlo (33 1/3 - 66 213 or 40/60) pin selectable KS58C20N DP
(PPs) (mS) Vss: 40/60
• Touch key hooking (580ms)
• Low standby current 20 823 Voo: 33.3/66.6
KS58D20N DP
(PPs) (mS) Vss: 40/60

PIN CONFIGURATION ARRANGEMENT OF KEYBOARD.

[~]00 R1

GJ00~ R2

0000 R3

KS5620 8G0~ R4

C1 C2 C3 C4
MODE SELECT 7

IHBI : HOOKING (580ms)

IE] :. PAUSE (3.6 second)
IEQI : REDIAL

'cR SAMSUNG SEMICONDUCTOR 172

 PRELIMINARY
KS5820 CMOS INTEGRATED CIRCUIT

BLOCK DIAGRAM
liS MIB MODESE[

R1

R2 x'MITMUTE

R3
OUTPUT
R4 KEYBOARD I----i LOGIC
LOGIC REDIAL
C1 MEMORY
32 DIGIT
C2

C3

C4

Voo
DTMF
GENERATOR

TONE OUT

OSC IN OSC OUT

TONE DURATION ·&PAUSE IN TONE FREQUENCIES

REDIAL
Input Specified Actual % Error
Characteristic Symbol Typ Unit R1 697 699.1 +0.31
Tone Duration To 74 mS R2 770 766.2 -0.49
Minimum Pause ITP 110 mS R3 852 847.4- -0.54
Cycle Time Tc 184 mS R4 941 948.0 +0.74
C1 1209 1215.7 +0.57
C2 1336 1331.7 -0.32
C3 1477 1471.9 -0.35

c8 SAMSUNG SEMICONDUCTOR 173

 . PRELIMINARY
KS5820 CMOS INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Ta=25·C)

Characteristics Symbol Value Unit

Supply Voltage Voo 6.0 V

Input Voltage V,N Vss - 0.3, Voo + 0.3
V
Output Voltage VOUT Vss-0.3, Voo+O.3
Output Voltage VOUT 1.2 (DP, X'MITMUTE) V
Tone Output Current hONE 50 mA
Power Dissipation Po 500 mW
Operating Temperature Topr -20-+70
·C
Storage Temperature Tstg -40 -+ 125

ELECTRICAL CHARACTERISTICS
(Vss= OV, Voo = 3.5V, fx'tal = 3.579545MHz, Ta = 25·C, unless otherwise specified)

Characteristic Sym.bol Test Conditions· Min Typ Max Unit

Operating Voltage VooP Pulse Mode All inputs connected 2.0 5.5
V
Range VooT Tone Mode to Voo or Vss 2.0 5.5
Memory Retention Voltage VO R 1.0

looP MODE·=Voo One key selected 0.4 1.0

Operating Supply Current HS = Vss. All outputs mA
looT MODE=Vss unloaded 1.0 2.0

Is01 HS=Voo =1.5V No key selected. 0.03 0.05

Standby Current All outputs ,.A
Is02
-HS=Vss unloaded 70 140

IOL1 . DPi [ Voo=3.5V 1.7 5.0

Output Current VOL =O.4V mA
IOL2 X'MIT MUTE [ Voo=2.5V 0.5 1.5
V ,H Rf-R4. C1-C3. HS. MIB O.BVoo Voo
. Input Voltage V
V,L MODE SELECT Vss 0.2Voo
I'N1 . Voo = 3.5V Y'N = OV 116
Input Current R1-R4 ,.A
I'N2 Voo = 2.5V Y'N = OV 50
Valid Key Entry Time Tkd 23 25.3 mS
Column and Row
Fer 445 Hz
Scanning Frequency
Auto Access Pause Time Tap 3.6 sec

ROW TONE [ Voo = 2.5V RL = 5K -16.0 -12.0

Tone Output Vor dBV
ONLY [. Voo =3.5V RL=5K -14.0· -11.0
Ratio of .Column to Row Tone dBer Vo~=3.5V 1.0 2.0 3.0 dB
Distortion %DIS V oo =3.5V 10 %
Tone Output Delay Time TPSd 1.5 mS

c8 SAMSUNG SEMICONDUCTOR 174

 PRELIMINARY
KS5820 CMOS INTEGRATED CIRCUIT

PIN DESCRIPTION
Pin Name Description

1-4 R1-R4 Keyboard (R1, R2, R3, R4, C1, C2, C3, C4)
15-18 C1-C4 These inputs can be interfaced to an XY matrix keyboard_
=
C1-C4 & R1-R4 are set to low at On Hook (HS high)_ C1-C4 key inputs are set
=
to low and R1-R4 are set to high at OFF HOOK (HS low) which enables the
key-input operation_ Oscillator starts running when a keypress is detected_
Scanning signals are presented at both column and row inputs (TYP: 445Hz)
until the input key is released_ Key inputs are compatible with standard 2-of-8

I
form or single-contact keyboard_ Debouncing is provided to avoid false entry
(TYP: 23mS)_
5 HS Hook Switch
This input detects the state of the hook switch contact "Off Hook"
corresponds to Vss condition_
·"On Hook" corresponds to Voo condition.
6 M/B Make/Break Ratio
This input provides the selection of the Make/Break ratio (33.3: 66.6/40:60) when
M/B is connected to VoolVss.
7 MODE SELECT Mode Select Input
PuiselDTMF mode is selected as shown in the following table.
Initial Mode means the state after going Off Hook (HS-+"Vss")

MODE INITIAL SWITCHING

SELECT MODE ENTRY MODE
MODE SELECT
Voo Pulse
Input Vss=
Vss Tone N/A

8-9 OSGIN Oscillator Input/Output

OSC OUT These pins are provided to connect an external 3.58MHz crystal. Oscillator starts
(at Off Hook) and is sustained until pulse or DTMF Single are finished.
10-11 Voo, Vss Power
These are the power supply inputs. This device is designed to operated on 2.0V
to 5.5V.
12 TONE OUT DTMF Signal Output
When a valid keypress is detected in DTMF mode Appropriate low group and
high group frequenc;:ies are generated which hybrided the Dual Tone Output
Tone out is Off State in pulse mode.
13 X'MIT MUTE X'mit Mute Output

HS X'mit Mute Output

Voo "OFF"
Normally "OFF"
Vss
"ON" during pulse and DTMF dialing
(N channel open drain)
14 DP, DP Dial Pulse Out

c8 SAMSUNG SEMICONDUCTOR 175

 PRELIMINARY
KS5820 CMOS INTEGRATED CIRCUIT

KEYBOARD OPERATION
1. SINGLE MODE OPERATION
• Pulse Mode Operation

I Off Hook lB· ~ .B

Pulse mode is defined by the initial mode after going Off Hook and latched at lID] key entry. This is the condition
under Mode Select = Voo.

• tone Mode Operation

I Off Hook lB··· B

Tone mode is defined by the initial mode after going Off Hook and latched at [Q1] key entry. This condition is under
Mode Select = Vss. .

• Manual Dialing with Automatic Access' Pause

I Off Hook I G G B···B

Mu!tlple Pause key entries can be accepted and stored in the redial memory, each as on digit. Each If] key provides
3.5 seconds pause time, but ~ key entry as first digit after gOing Off Hook is ignored. [!J key can also be used
m
as pause key in pulse mode. Pause (s) can be cancelled with rei, or key durin'g pause time in redialing.
[Qj=Any numeric key .

• Rectlallng

I Off Hook IB
Up to 32 digits can be dialed with IBQI key. IBQI key is disabled while pulse or DTMF signals are transmitting.
When more then 32 digits are stored in redial memory, Redial is also inhibited.
[i] key can be used as IBQI key in pulse mode.

• Inhibiting Rectlal

I Off Hook I B···B B B

Redial can be inhibited by depressing m [BDJ keys after DTMF or pulse signals are transmitted.

c8 SAMSUNG SEMICONDUCTOR
. 17&
 PRELIMINARY
KS5820 CMOS INTEGRATED CIRCUIT

2. PULSEITONE SWITCHABLE OPERATION

• Mode Switching by MODE SELECT Input

Off Hook I8··· 8 G Switching MODE SELECT to Vss B··· EJ

t - I- - - - - Pulse Mode r---- OTMF Mode-----i

Pulse mode is initially defined MODE SELECT _ Voo , mode switching to OTMF can be accepted by MODE
=
SELECT Vss , OTMF mode will be set up after pulse mode is finished. In this mode, digits IOn + 11 ... IOn + ml are
transmitted from Tone Out as DTMF signals by depressing corresponded keys.
If no [f] key is contained serially before or after mode switching.
I
Off Hook
8···8 Switching MODE SELECT to Vss B··· EJ
I Pulse Mode I----- DTMF MOde-----l
*"
(On + 1 Pause)
It results the next condition.
"If digit IOn + 11 is depressed after pulse mode is finished, DTMF mode will be set up after last pulse signal (1Q!j])
is output. In this mode, digits IOn + 11 ... IOn + ml are transmitted from Tone Out as OTMF signals by depressing
corresponded keys. If digit ~ is depressed during dialing pulse signals. When DTMF mode is set up Hold
State will be set up after last pulse signal fimI is finished. MODE OUT will flash to indicate this Hold State
IOn + 11 ... IOn + ml ·are stored in redial memory as DTMF DATA and not transmitted from Tone Out. When it is
ready to transmit OTMF data in redial memory, IBQ] or [f] keys is depressed to reset this Hold State and
IOn + 11 ... IDn + ml data are serially transmitted.

Single Tone Operation in DTMF Mode (Test mode)

The M/B pin is used to trig the chip into test made by applying a positive or negative pulse to this input after "Off'
Hook." Test mode is sustained until On Hook. The Single tone is shown in the following table which contrast with
normal mode.'

Normal mode Single tone mode

R1 1 2 3 R1 R1 "C2 C3

R2 4 5 6 R2 C1 C2 R2
R3 7 8 9 R3 R3 C2 C3

R4 * 0 # R4 C1 R4 C3

C1 C2 C3 C1 C2 C3

c8SAMSUNG SEMICONDUCTOR 177

 PRELIMINARY
KS5820 CMOS INTEGRATED CIRCUIT

TONE MODE TIMING (MODE SELECT - Vss)

HSl ~~L-_~ _ _

KEY INPUT =tit I 1IIIIIImi 3 I l1li11111 • r-n 1111111111 AD I _

,~,,,"-- __JL __ M _____ r'\L1l-_____rLh--Pt-

X'MIT OUT s--JI r-
ose - - - - _ _ ~---~IIIIIIIIIIIIIIIIIIIIII~-----_--------~IIIIIIIII11111
D: Debouncing Time: 23mS Tout: 146mS
1""I""""r--
T'TP: 146mS RD .

PULSE MODE TIMING (MODE SELECT =Voo)

~~~------~--------------~-----------
--1 Dr---
KEY INPUT-'~mmm
4 ~~-------------------------

~~~------------------------~
osc ----~III~IIIIIIII~---FOSC=3.5j954sMHZ------lIIIIIIIII~-------

D: Debouncing Time: 23mS

T,op: ~nter Digit Pause: 823mS
.~

c8 SAMSUNG SEMICONDUCTOR 178

 PRELIMINARY
KS5820 CMOS INTEGRATED CIRCUIT

TIMING DIAGRAM (for Switching Mode Operation by MODE SELECT Input)

~~~------------------------
KEYINPUT----------4m
P Switching MS =Vss

llP-----.LJU LJUlJ=TAP===1
DP _ _

TONE OUT
nJl_nJlJl::::'~=
' ~~----
II
I lI_ _ _ _ _ _ _ _ _ _ _....J.FTMOF=j
MODE SELECT----.J ------I
L...

X'MIT MUTE

osc------~IIIIIII"111--1--FOSC=3,579545MHZ------IIIII"III~-------
TAP: Auto Pause Time

. "c8 SAMSUNG SEMICONDUCTOR 179

KS5824 CMOS INTERGRATED CIRCUIT

UNIVERSIAL ASYNCHRONOUS RECEIVER

24 DIP
AND TRANSMITTER
The KS5824 UART, is a Si-gate CMOS IC which provides the data
formatting and control to interface serial asynchronous data communi-
cations between main system and subsystems_
The bus interface of the KS5824 includes select, enable, read/write,
interrupt and bus interface logic to allow data transfer over an 8-bit bi-
directional data bus. The parallel-data of the bus system is serially,
transmitted and received by the asynchronous data interface, with proper
formatting and error checking. The functional configuration of the UART
is programmed via the data bus during system initialization. A program-
mable control register provides variabie word lengths, clock division
ratios, transmit control, receive control, -and interrupt control. For
peripheral or modem operation, three control lines are provided.
Excee(:ling Low Power dissipation is realized due to adopting CMOS
process.

FEATURES
• Low-power, high-speed, CMOS process
• Seriallparallel conversion of data
• 8-and 9-blt transmission
• Optional even and odd parity
• Parity, overrun and framing error checking
• Programmable control register
• Optional + 1, + 16, and + 64 clock modes
• Peripheral/modem control functions
• Double buffered
• One-or two-stop bit operation

BLOCK DIAGRAM PIN CONFIGURATION

CTS
!iCD
DATA TRANSMIT DO-
DATA BUS BUS DATA 01
BUFFERS

RECEIVE
DATA

ADDRESS SELECTION
CONTROL AND
AND CONTROL
'INTERRUPT
t-_ _ _ _ ~~:r~gt"'UMODEM
1-----'

c8 SAMSUNG SEMIC()NDUCTOR 180

KS5824 CMOS INTERGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Supply Voltage Vee" -0.3 to -7.0 V

Input Voltage Y,N" .-0.3 to +7.0 V
Maximum Output Current 10 • * 10 mA
Operating Temperature Top, -20 to +75 ·C
Storage Temperature T.,g -55 to +150 ·C

" With respect to Vss (SYSTEM GND) ,

I
"" Maximum output current is the maximum current which can flow out from one output terminal or 1/0 common
termin!!1 (0 0 - 0 7, RTS, Tx Data, IRQ).
Note: Permanent IC damage may occur if maximum ratings are exceeded. Normal operation should be under
recommended operating conditions are exceeded, it could affect reliability of IC.

RECOMMENDED OPERATING CONDITIONS

Characteristic Symbol Min Typ Max Unit

Supply Voltage Vee " 4.5 5.0 5.5 V

Input "low" Voltage V,L" 0 - 0.8 V
Input "High" I 0 0 -07, RS, Tx ClK, DCD, CTS, Rx Data
V,H "
2.0 - Vee
V
Voltage
I CSo, CS2 , CS" RIW, E, Rx ClK 2.2 - Vee
Operating Temperature Top, -20 25 75 ·C

" With respect to Vss (SYSTEM GND)

ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vee =5V±5%, VSs=OV, Ta= -20-+75·C, unless otherwise noted.)

Characteristic Symbol Test Conditions Min Typ Max Unit

0 0 - 0 7, RS, Tx ClK,
DCD, C'fS, Rx Data
2.0 - Vee
Input "High" Voltage V,H V
eso, CS2, CS" RIW, E,
2.2 - Vee
Rx ClK
Input "low" Voltage All inputs V,L -0.3 - 0.8' V
Input leakage Current RIW, eso, es" es2, E liN V'N=O-Vee -2.5 - 2.5 p.A
Three·Stah~ (Off State)
Input Current
0 0 -07 IrSI V,N =O.4-Vee -10 - 10 p.A

0 0 -07
10H= -400p.A 4.1 - -
Output "High" Voltage VOH
10H:!> -10p.A Voc·O.1 - - V
Tx data, RTS
10H = - 400p.A 4.1 - -
10H:!> -10p.A Vee·0.1 - -
Output "low" Voltage All outputs VOL IOH=1.6mA - - 0.4 V
, .

c8 SAMSUNG SEMICONDUCTOR 181

KS5824 CMOS INTERGRATED CIRCUIT

DC CHARACTERISTICS (Continued)

Characteristic Symbol Test C~nditlons Min Typ Max Unit

Output leakage
(Off State)
Cur~ent
IRQ ILOH VOH=VCC ,- - 10 pA

0 0 -0 7 - - 12.5
E, Tx ClK, Rx ClK, VIN=OV, Ta=25°C,
Input Capacitance CIN pF
Rm, RS, Rx Data, CSo, f=1.0MHz - - 7.5
CS" CS2, CTS, DCD

Output Capacitance
RTS, Tx Dat~
COUT
V,N =OV:Ta=25°C - - 10
pF
iRa f=1.0MHz - - 5.0
• Under transmitting and E=1.0MHz - - 3
receiving operation
• 500 kbps
E=1.5MHz - - 4 mA
• Data bus in Rm operation E=2.0MHz - - 5
Supply Current • Chip is not selected Icc
.500 kbps
E= 1.0MHz - - 200
• Under non transmitting
and receiving operation E= 1.5MHz - - 250 p.A
• Input level (Except E)
VIH min = Vcc - 0.8V
VIL max = 0.8V
E=2.0MHz - - 300

AC CHARACTERISTICS (Vcc=5.0V±5%,Vss =OV, Ta= -20-+75°C, unless otherwise noted.)

1. TIMING OF DATA TRANSMISSION

Characteristic Symbol Test Conditions Min Max Unit

+1 Mode
PWCL Fig. 1
,900 - ns

Minimum Clock Pulse Width

+16, +64 Modes 600 - ns
, +1 Mode
Fig. 2
900 - ns
PWCH
+16, +64 Modes 600 - ns

Clock Frequency
+1 Mode
fc
- 500 KHz
+ 16, + 64 Modes - 800 KHz
Clock-to-Data Delay for Transmitter trOD Fig. 3 - 600 ns
Receive Data Setup Time +1 Mode tRoSU Fig. 4 250 - ns
Receive Data Hold Time +1 Mode tRoH Fig. 5 250 - ns
IRQ Release Time tlR Fig. 6 - 1200 ns
i1fS Delay Time tRTS Fig. 6 - 560 ns
Rise Time and Fall Time Except E t" tl - 1000' ns

• 1.0p.s or 1Q% of the pulse width, whichever is smaller.

c8 SAMSUNG SEMICONDUCTOR 182

KS5824 CMOS INTERGRATED CIRCUIT

2. BUS TIMING CHARACTERISTICS

1) READ

Characteristic Symbol Test Conditions Min Max Unit

Enable Cycle Time teycE Fig. 7 1000 - ns

Enable :'High" Pulse Width PweH Fig. 7 450 - ns
Enable "Low" Pulse Width PWEL Fig. 7 430 - ns
Setup Time, Address and 'Rm Valid
to Enable Positive Transition
tAS Fig. 7 80 - ns

Data Delay Time

Data Hold Time
Address Hold Time
tOOR
tli
tAH
Fig. 7
Fig. 7
Fig. 7
-
20
10
290
100
-
ns
ns
ns
I
Rise and Fall Time for Enable Input te" te, Fig. 7 - 25 ns

2) WRITE

Characteristic Symbol Test Conditions Min Max Unit

·Enable Cycle Time teyeE Fig. 8 1000 - ns

Enable "High" Pulse Width PWEH Fig. 8 450 - ns
Enable "Low" Pulse Width PWEL Fig. 8 430 """"' ns
Setup Time, Address and RIW
Valid to Enable Positive Transition
tAS Fig. 8 80 - ns

Data Setup Time tosw Fig. 8 165 - ns

Data Hold Time tH Fig. 8 10 - ns
Address Hold Time tAH Fig. 8 10 - ns
Rise and Fall Time for Enable Input tE" te, Fig. 8 - 25 ns

PWCL Tx elK
OA 2.2V
Tx ClK Ax ClK
OA
Ax ClK o.sv
PWCH
• Tx elK Is V'H=2.0V
Fig. 1 Clock Pulse Width, "Low" State Fig. 2 Clock Pulse Width, "High" State

Tx elK
Ax DATA

Vcc-2.0V

O.4V Ax elK _ _ _-'I

Fig. 3 Transmit Data Output Delay Fig. 4 Receive Data Setup Time (+ 1 Mode)

c8 SAMSUNG SEMICONDUCTOR 183

·KS5824 CMOS INTERGRATED CIRCUIT

Rx ClK ENABLE

Vcc- 2.OV
O.4V

. -FV;;
iRCl _ _ _ _ _ _ _ _ _ _ _ _~/:...2.0V
Fig. 5 Receive Data Hold Time ( ... 1 Mode)

•. (1) i'RCi Release Time applied to Rx Data Register

read operation.
i----tcycE----I (2) IRQ Release Time applied to Tx Data Register
write ope~ation
(3) IRQ Release Time applied to control Register
write TIl: = 0, RIE = 0 operation.
ENABLE
•• IRQ Release Time applied to Rx Data Register
read operation right after read status register,
when IRQ is asserted by DCD rising edge.
RS.CS.RIW
Note: Note that following take place when IRQ is
asserted by the detection of transmit data register
empty status. IRQ is released to "High"
DATA BUS asynchronously with E signal when CTS goes
"High". (Refer to Figure 14)

Fig. 7 Bus Read Timing Characteristics Fig. 6 m Delay and i1m Release Time
(Read information from UARn

(~~=1\Y)'5.0V
lOAD A
(00-07. RiS. Tx DATA)

f----tcycE - - - - - I RL =2.4KIl 3KIl

PWEH
TEST POINT
TEST POINT

c= 130pF for 00-07

= 30pF for FITS and.IlLData
=
R 10KIl for 00-07. RTS and Tx Data
r"
All diodes are lS2074@or Equivalent.

Fig. 8 Bus Write Timing Characteristics Fig. 9 Bus Timing Test Loads
(Write information into UARn

c8SAMSUNG SEMICONDUCTOR 184

 KS5824 CMOS INTERGRATED CIRCUIT

START BIT DO 01 02 03 04 05 06 PARITY STOP STOP

II
BIT BIT BIT
f---------- CHARACTER TIME @10CPS (11 BITS) 1 0 0 m s e c - - - - - - - - - - - i

Fig. 10 110 Baud Serial ASCII Data Timing

TRANSMIT
CLOCK 4
ENABLE 14

READIWRITE 13 CHIP
CHIP SELECT 0 8 SELECT
AND TRANSMIT 6 TRANSMIT
CHIP SELECT 1 10 READI DATA DATA
CHIP SELECT 2 9 WRITE REGISTER
REGISTER SELECT 11- CONTROL

·24 CLEAR
TO SEND

DO 22
STATUS
01 21 REGISTER
7 INTERRUPT
02 20
REQUEST
DATA BUS
03 19 BUFFERS 23 DATA
04 18 CARRIER
DETECT
05 17
5 REQUEST
06 16 TO SEND

07 15 . CONTROL
REGISTER

Vcc=Pin 12 RECEIVE· RECEIVE

Vss=Pin 1 DATA SHIFT 1------+-- 2 ~!~!IVE
REGISTER REGISTER

RECEIVE
CLOCK 3
-------------------t....::.~.:...J

Fig. 11 Expanded Block Diagram

,

c8 SAM$UNG SEMICONDUCTOR 185

KS5824 CMOS INTERGRATED CIRCUIT

DEVICE OPERATION transmitted (because of double buffering). The second

character will be automatically transferred into the Shift
At the bus interfl[lCe, the UART appears as two Register when ·the first character transmission is
addressable memory locations. Internally, there are four completed. This sequence continues until all the
registers: two read-only and two write-only registers. The characters have been transmitted.
read-only registers are Status and Receive Data; the
write-only registers are Control and Transmit Data. The
serial interface consists of serial input and output lines
RECEIVE
with independent clocks, and three peripheral/modem Data is received from a peripheral by means of the
control lines. Receive Data input. A divide-by-one clock ratio is
provided for an extemally synchronized clock (to its data)
while the divid-by-16 and 64 ratios are provided for
POWER ON/MASTER RESET
internal synchronization. Bit synchronization in the
The master reset (CRO, CR1) should be set during divide-by-16 and 64 modes is initiated by the detection
system initialization to insure the reset condition and of B or 32 low samples on the receive .Iine in the divide-
prepare for' programming the UART functional confi- by-16 and 64 modes respectively. False start bit deletion
guration when the communications channel is required. capability insures that a full half bit of a start bit has
During the first master reset, the IRQ and RTS outputs been received before the internal clock is synchronized
are held at level 1. On all other master resets, the RTS to the bit time. As a character is being received, parity
output can be programmed high or low with the IRQ (odd or even) will be checked and the error indication
output held high. Control bits CR5 and CR6 should also will be available in the Status Register along with
be programmed to define the state of RTS whenever framing error, overrun error, and Receive Data Register
master reset is utilized. The UARTalso cQntains internal full. In a typical receiving sequence, the Status Register
power-on reset logic to detect the power line turn-on is read to determine if a character has been received
transition and hold the chip in a reset state to prevent from a peripheral. If the Receiver Data Register is full,
'erroneous output transitions prior to initialization. This the character is placed on the B-bit UART bus when a
circuitry depends on clean power turn-on tranSitions. Read Data command is received from the MPU. When
The power-on reset is released by means of the bus- parity has been selected for a 7-bit word (7 bits plus
programmed master reset which must be applied prior =
parity), the receiver strips the parity bit (07 0) so that"
to operating the UART. After master resetting the UART, data alone ia transferred to the MPU. This feature
the programmable Control Register can be set for a reduces MPU programming. The Status Register can
number of options such as variable clock divider ratios, continue to be read to determine when another
variable word length, one or two stop bits, parity (even, character is available in the Receive Data Register. The
odd, or none), etc. receiver is also double buffered so that a character can
be read from 'the data register as another character is
being received in the shift register. The above sequence
TRANSMIT continues u'ntil all characters have been received.
A typical transmitting sequence consists of reading
the UART. Status Register either as a result of an
interrupt or in the UART's turn in a polling sequence. INPUT/OUTPUT FUNCTIONS
A character may be written into the Transmit Data
Register if the status read operation has indicated that UART INTERFACE SIGNALS FOR MPU
the Transmit Data Register is empty. This character is
The KS5B24 interfaces to the MPU with an B-bit
transferred to a Shift Register where it is serialized and
bidirectional data bus, three chip select lines, a register
transmitted from the Transmit Data output preceded by
select line, an interrupt request line, read/write line, and
a start bit. and followed by one or two stop bits. Intemal
enable line. These signals permit the MPU to have
parity (odd or even) can be optionally added to the
complete control over the KS5824.
character and will occur between the last data bit and
the first stop bit. After the first character is written in UART Bidirectional Data (00-07) - The bidirectional
the Data Register, the Status Register can be read again data lines (00-07) allow for data transfer between the
to check for a Transmit Data Register Empty condition KS5B24 and the MPU. The data bus output drivers are
and current peripheral status. If the register is empty, three-state devices that remain in the high-impedance
another character can be loaded for transmission even (off) state except wh~n the MPU performs an UART read
though the first character is in the process of being operation.

c8 SAMSUNG SEMICONDUCTOR' .186

 KS5824 CMOS INTERGRATED CIRCUIT

UART Enable (E) - The Enable signal, E, is a high- reading data or resetting the UART. Interrupts caused
impedance TTL-compatible input that enables the bus by Overrun or loss of DCD are cleared by reading the
input/output data buffers and clocks data to and from status register after the error condition has occurred and
the KS5824. then reading the Receive Data Register or resetting the
UART. The receiver interrupt is masked by resetting the
ReadlWrite (R/W) - The ReadlWrite line is a high-
Receiver Interrupt Enable.
impedance input that is TTL compatible and is used to
control the direction of data flow through the UART's
input/output data bus interface. When ReadlWrite is high CLOCK INPUTS
(MPU Read cycle), KS5824 output drivers are tumed on
and a selected register is read. When it is low, the Separate high-impedance TTL-compatible inputs are
KS5824 output drivers are turned off and the MPU writes provided for clocking of transmitted and received data.

II
into a selected register. Therefore, the ReadlWrite signal Ciock frequencies of 1, 16, or 64 times the data rate may
is used to select read-only or write-only registers within be selected.
the KS5824. Transmit Clock (Tx ClK) -The Transmit Clock input
Chip Select (CSO, CS1, CS2) - These three high- is used for the clocking of transmitted data. The
impedance TTL-compatible input lines are used to transmitter initiates data on the negative transition of
address the KS5824. The KS5824 is selected when CSO the clock.
and CS1 are high and CS2 is low. Transfers of ,data to Receive Clock (Rx ClK) - The Receive Clock input
and from the KS5824, are then performed under the is used for synchronization of received data (In the + 1
, control of the Enable Signal, ReadlWrite, and Register mode, the clock and data must be synchronized
Select. extemally.) The receiver samples the data on the positive
Register Select (RS) - The Register Select line is a trans,ition of the clock.
high-impedance input that is TTL compatible. A high
level is used to select the Transmit/Receive Data SERIAL INPUT/OUTPUT LINES
Registers and a low level the Control/Status Registers.
The ReadlWrite signal line is used in conjunction with Receive Data (Rx Data) - The Receive Data line is
Register Select to select the read-only or write-only a high-impedance TTL-compatible input through which
register in each register pair. data is received in a serial format. Synchronization with
a clock for detection of data Is accompiished internally
Interrupt Request (IRQ) - Interrupt Request is a TTL- when clock rates of 16 or 64 times the bit rate are used.
compatible, open-drain (no internal pull up), active low
output that is used to interrupt the MPU. The IRQ output Transmit Data (Tx Data) - The Transmit Data output
remains low as long as the cause of the interrupt is line transfers serial data to a modem or other peripheral.
present and the appropriate interrupt enable within the
UART is set. The IRQ status bit, when high, indicates PERIPHERAUMODEM CONTROL
the IRQ output is in the active state.
Interrupts result from conditions in both the The UART includes several functions that permit
transmitter and receiver sections of the UART. The limited control of a peripheral or modem. The functions
transmitter section causes an interrupt when the included are Clear-to-Send, Request-to-Send and Data
Transmitter Interrupt Enabled condition is selected Carrier Detect.
(CR5 o CR6), and the Transmit Data Register Empty Clear-ta-Sand (CTS) - This high-impedance TTL-
(TORE) status bit is high. The TORE status bit indicates compatible input provides automatic control of the
the current status of the Transmitter Data Register transmitting end of a communications link via the
except when inhibited by Clear-to-Send (CTS) being high modem Clear-to-Send active low output by inhibiting the
or the UART being maintained in the Reset condition. Transmit Data Register Empty (TORE) status bit.
The interrupt is cleared by writing data into the Transmit
Data Register. The interrupt is masked by disabling the Request:to-Sand (RTS) - The Request-to-Send output
Transmitter Interrupt via CR5 or CR6 or by the loss of enables the MPU to control a peripheral or modem via
CTS which inhibits the TORE status bit. The Receiver the data bus. The FITS; output corresponds to the state
section causes an interrupt when the Receiver Interrupt of the Control Register bits CR5 and CR6. When CR6 = 0
, Enable is set and the Receive Data Register Full (RDRF)' =
or both CR5 and CR6 1, the RTS output is low (the
status bit is high, an Overrun has occurred, or Data active state). This output can also be used for Data
Carrier Detect (DCD) has gone high. An interrupt Terminal Ready (DTR).
resulting from the RDRF status bit can be cleared by

c8 SAMSUNG SEMICONDUCTOR 187

KS5824 CMOS INTERGRATED CIRCUIT

Data Carrier Detect (!)CO) - This high-impedance character is being transmitted, then the transfer will take
TIl-compatible input provides automatic control, such place within 1-bit time of the training edge of the Write
as in the receiving end of a communications link by command. If a character is being transmitted, the new
means of a m9dem Data Carrier Detect output. The DCD ' data character will commence as soon as the previous
input rnhibits and initializes the receiver section of the character is complete. The transfer of data causes the
UART when high. A low-to-high transition of the Data Transmit Data Register Empty (TORE) bit to indicate
Carrier Detect initiates an interrupt to the MPU to empty.
indicate the occurrence of a loss of carrier when the
Receive Interrupt Enable bit is set. The Rx ClK must RECEIVE DATA REGISTER (RDR)
be running for proper DCD operation. Data is automatically transferred to the empty Receive
'Data Register (RDR) from the receiver deserializer (a
UART REGISTERS shift register) upon receiving a complete character. This
The expanded block diagram for the UART indicateS event causes the Receive Data Register Full bit (RDJ:lF)
the Internal registers on the chip that are used for the in the status buffer to go high (full). Data may then be
status, control, receiving, and'transmitting of data ThEi read through the bus by addressing the UART and
content of each of the registers is summarized in Table selecting the Receive Data Register with RS and RIW
1. high when the UART is enabled. The non-destructive
read cycle causes the RDRF bit to be cleared to empty
TRANSMIT DATA REGISTER (TOR) although the data is retained in the RDA. The status is
Data is written in the Transmit Data Register during maintained by RDRF as to whether or not the data is
the negative transition of the enable (E) when the UART current. When the Receive Data, Register is full, the '
has been addressed with RS high and RiW low. Writing automatic transfer of data from the Receiver Shift
data into the register caul$es the Transmit Data Register Register to the Data Register is inhibited and the RDR
Empty bit in the Status Register to go low. Data can then contents remain valid with its current status stored in
I:;le transmitted. If the transmitter is idling and no the Status Register.

DEFINITION OF UART REGISTER CONTENTS

Buffer Address
Data RS. RiW RS. RIW RS. iWi RS. RiW
Bus Transmit Receive
Line Data Data Control Status
Number Register Register Register Register
(Write Only) (Read Only) (Write Only) (Read Only)

0 Data Bit 0' Data Bit 0 Counter Divide Receive Data Register
Select ,1 (CR1) Full (RDRF)
1 Data Bit 1 Data Bit 1 Counter Divide Transmit Data Register
Select 2 (CR1) Empty (TORE)
2 Data Bit 2 Data Bit 2 Word Select 1 Data Carrier Detect
(CR2) (DCD)
3 Data Bit 3 Data Bit 3, Word Select 2 Clear-to-Send
(CR3) (CTS)
4 Data Bit 4 Data Bit 4 Word Select 3 Framing Error
(CR4) (FE)
5 Data Bit 5 Data Bit 5 Transmit Control 1 Receiver Overrun
(CR5) (OVRN)
6 Data Bit 6 Data Bit 6 Transmit Control 2 Parity Error (PE)
(CR6)
7 Data Bit 7'" Data Bit 7" Receive Interrupt Interrupt Request
Enable (CR7) (IRQ)
• leadmg bit = lSB = Bit 0
" Data bit will be zero in 7 bit plus parity modes
, •• Data bit is "don't care" in 7 bit plus parity modes.

c8 SAMSUNG SEMICONDUCTOR
188
KS5824 CMOS INTERGRATED CIRCUIT

CONTROL REGISTER CR6 CRS Function

The UART Control Register consists of eight bits of 0 0 =
RTS low, Transmitting interrupt
write-only buffer that are selected when RS and R/W are Disabled.
low. This register controls the function of the receiver, 0 1 =
RTS low, Transmitting Interrupt
transmitter, interrupt enables, and the Request-to-Send Enabled.
peripheral/modem control output. 1 0 =
RTS high, Transmitting Interrupt
Counter Divide Select Bits (CRG and CR1) - The Disabled.
Counter Divide Select Bits (CRO and CR1) determine the 1 1 =
RTS low, Transmits Break level on
divide ratios utilized in both the transmitter and receiver the Transmit Data Output.
sections of the UART. Additionally, these bits are used Transmitting Interrupt Disabled.
to provide a master reset for the UART which clears the

II
Receive Interrupt Enable Bit (CR7) - The following
Status Register (except for external conditions on CTS
interrupts will be enabled by a high level in bit position
and DC D) and initializes both the receiver and
7 of the Control Register (CR?): Receive Data Register
transmitter. Master reset does not affect other Control
Register bits. Note that after power-on or a power Full Overrun or a low·to-high transition on the Data
fail/restart, these bits must be set high to reset the Carrier Detect (DCD) signal line.
UART. After resetting, the clock divide ratio may be
selected. These counter select bits provide for the
STATUS REGISTER
follo~ing clock divide ratios: Information on the status of the UART is available to
the MPU by reading the UART Status Register. This read-
CR1 CRO Function only register is selected when RS is low and RiW
0 0 +1 is high. Information stored in this register indicates the
0 1 +16 status of the Transmit Data Register, the Receive Data
1 0 +64 Register and error logic, and the peripheral/modem
1 1 Master Reset status inputs of the UART.
Receive Data Register Full (RDRF), Bit 0 - Receive
Word Select Bits (CR2, CR3, and CR4) - The Word Data Register Full indicates that received data has been
Select bits are used to select word length, parity, and transferred to the Receive Data Register. RDRF is
the number of stop bits. The encoding format is as cleared after an MPU read of the Receive Data. Register
follows; or by a master reset. The cleared or empty state
indicates that the contents of the Receive Data Register
CR4 CR3 CR2 Function are not current. Data Carrier Detect being high also
0 0 0 7 Bits + Even Parity + 2 Stop Bits causes RDRF to indicate empty.
0 0 1 7 Bits + Odd Parity + 2 Stop Bits Transmit Qata Register Empty (TORE), Bit 1 - The
0 1 0 7 Bits + Even Parity + 1 Stop Bit Transmit Data Register Empty bit being set high
0 1 1 7 +.
Bits Odd Parity +1 Stop Bit indicates that the Transmit Data Register contents have
1 0 0 8 Bits + 2 Stop Bits been transferred and that new data may be entered. The
1 0 1 8 Bits + 1 Stop Bit low state indicates that the register is full and that
1 1 0 8 Bits + Even Parity + 1 Stop Bit transmission of a new character has not begun since
1 1 1 8 Bits + Odd Parity + 1 Stop Bit· the last write data command.
Word length, Parity Select, and Stop Bit changes are Data Carrler'Detect (DCD), Bit 2 - The Data Carrier
not buffered and therefore become effective Detect bit will be high when the DCD input from a
immediately. modem has gone high to indicate that a carrier is not
Transmitter Control Bits (CRS and CR6) - Two present. This bit going high causes and Interrupt
Transmitter Control bits provide for the control of the Request to be generated when the Reoeive Interrupt
interrupt from the Transmit Data Register Empty Enable is set. It remains high after the DCD input is
condition, the Request-to-Send (RTS) output, and the· returned low until cleared by first reading the Status
transmission of a Break level (space). The following Register and then the Data Register or until a master
encoding format is used: . reset occurs. If the DCD input remains high after read

c8 SAMSUNG SEMICONDUCTOR 189

 <

KS5824 CMOS INTERGRATED CIRCUIT

status and read data or master reset has occurred, the in succession without a read of the RDR having
interrupt is cleared, the DCD status bit remains high and occurred. The Overrun does not occur in the Status
will follow the DCD Input. Register until the valid character prior to Overrun has
Clear·to-5end"(CTS), Bit 3 - The Clear·to-Send bit been read. The RDRF bit remains set until the Overrun
indicates the state of the Clear·to-Send input from a is reset. Character synchronization is mai~tained during
modem. A low CfS indicates that there is a Clear·to- the Overrun condition. The Overrun indication is reset
Send from the mod~m. In the high state, the Transmit after the reading of data from the Receive Data Register
Qata Register Empty bit Is inhibited and the Clear·to- or by a Master Reset.
Send status bit will be high. Master reset does not affect Parity Error(PE), Bit 6 - The parity error flag indicates
the Clear·to-Send status bit. that the number of highs (ones) in the character does
Framing Error (FE), Bit 4 - Framing error Indicates not agree with the preselected odd or even parity. Odd
that the received character is Improperly' framed by a parity is defined to be when the total number of ones
start and a stop bit and is detected by the absence of is odd. The parity error indication will be present as long
the first stop bit. This error indlcate"s a synchronization as the data character Is in the RDR. If no parity is
error, faulty transmission, or a break condition. The selected, then both the transmitter parity generator
framing error flag Is set or reset during the receive data output and the receiver parity check results are
transfer time. Therefore, this error indicator is present inhibited.
throughout the time that the associated character is Interrupt Request (IRQ), Bit 7 - The IRQ bit indicates
available. the state of the IRQ output. Any interrupt condition with
Receiver Overrun (OVRN), Bit 5 - Overrun is an error its applicable enable will be indicated in this status bit.
flag the indicates that one or more characters in the data Anytime the IRQ output is low the IRQ bit will be high
stream were lost. That is, a character or a number of to indicate the interrupt or service request status. IRQ
characters were received but not read from the Receive is cleared by a read operation to the Receive Qata
Data Register (RDR) prior to subsequent characters Register or a write operation to the Transmit Data
being received. The overrun condition begins at the" Register.
midpoint of the last bit of the second character received

c8 SAMSUNG SEMICONDUCTOR 190

KT3040J CMOS INTEGRATED CIRCUIT

PCM MONOLITHIC FILTER.

16 CERDIP
The KT3040J filter is a monolithic circuit containing both transmit and
receive filters specifically designed for PCM CODEC filtering applications
in 8KHz sampled systems ..
The filter is manufactured using double-poly Si-Gate CMOS
technology. Switched capacitor integrators are used to simulate classical
LC ladder filters which exhibit low component sensitivity.
Transmit Filter Stage
The transmit filter is a fifth order elliptic low pass filter in series with

II
a fourth order Chebyshev high pass filter. It provides a flat response in
the passband and rejection of signals below 200Hz and above 3.4KHz.
Receive Filter Stage
The receive filter is a fifth order elliptic lowpass filter designed to
reconstruct the voice signal from the decoded/demultiplexed signal
which, as a result of the sampling process, is a stair-step signal havirig
the inherent sin XiX frequency response. The receive filter approximates
the function required to compensate for the degraded frequency
response and restore the flat passband response.

FEATURES
• Exceeds all 03/04 and CCITT specifications
• + 5V, - 5V power supplies '
• Low power consumption: 45mW (0 dBmO into 6000)
30mW (power amps disabled)
• Power down mode: 0_5mW
• 20 dB gain adjust range
• No extemal anti-aliasing components
• Sin xix correction In receive filter
• 5OI6OHz rejection in transmit filter
• TTL and CMOS compatible logic
• All inputs protected against static discharge due to handling

c8 SAMSUNG SEMICONDUCT()R 191

KT3040J CMOS INTEGRATED CIRCUIT

BLOCK DIAGRAM
PDN GNDA ' GNDD Vee PWRI

CLK

CLKO

VFXO

GSx
Fig. 1

PIN CONFIGURATION

GNDA
CLKO
PDN
KT3040J

~~ VFRI

9J Vee

ABSOLUTE MAXIMUM RATINGS

Chllracterlstlcs Symbol Value Unit

Supply Voltages Vs ±7 V
Power Dissipation Po 1 W/PKG
Input Voltage VIN ±7 V
Output Short-Circuit Duration Ts.e OUT Continuous sec
Operating Temperature Range Ta -25 to + 125 ·C
Storage Temperature T.'g -65 to + 150 ·C
Lead Temperature (Soldering 10 seconds) TL 300 ·C

c8 SAMSUNG SEMICONDUCTOR 192

KT3040J CMOS INTEGRATED CIRCUIT

DC ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, Ta = O·C to 70·C, Vee = + 5.0V ± 5%, Vee = - 5.0V ± 5%, clock frequency is 2.048MHz.
Typical parameters are specified at Ta= 25·C, Vee = +5.0V, Vee = - 5.0V, digital interface voltages measured with
respect to digital ground, GNDD. Analog voltages measured with respect to analog ground, GNDA.)

Characteristic Synibol Test Condition Min Typ Max Unit

Power Dissipation
Vee Standby Current leeo PDN=Voo 400 ".A
Vee Standby Current leBO PDN=Voo 400 p.A

Vee Operating Current

Vee Operating Current

Vee Operating Current

leel

'l ee1

lee2
PWRI = Vee, Power Amp

(Note 1)
Inactive
PWRI = Vee, Power Amp
Inactive
3.0

3.0

4.6
.4.0

4.0

6.4
mA

mA

mA
I
Vee Operating Current leB2 (Note 1) 4.6 6.4 mA
Digital Interface
Input Current, CLK liNe VeeSVINSVee -10 10 ".A
Input Current, PDN IINP VeeSVINSVee -100 ".A
Input Current, CLKO IINo VeeSVINSVee - 0.5V -10 -0.1 ".A
Input Low Voltage, CLK, PDN Vil 0 0.8 V
Input High Voltage, CLK, PDN VIH 2.2 Vee V
Input Low Voltage, CLKO VllO Vee Vee+ 0.5 ' V
Input Intermediate Voltage, CLKO VIIO -0.8 0,8 V
Input High Voltage, CLKO VIHO Vee·0.5 Vee V
Transmit Input OP Amp
Input Leakage Current, VFXI lexl VeeSVFxlSVee -100 100 nA
Input ReSistance, VFXI Rixi VeeSVFxlSVee 10 Mil
Input Offset Voltage, VFXI VOSXI -2.5VSVINS +2.5V -20 20 mV
Common Mode Range, VFXI VCM -2.5 2.5 V
Common Mode Rejection Ratio CMRR -2.5VsVINS +2.5V 80 dB
Power Supply Rejection of Vee or Vee PSRR 60 dB
Open Loop Output Resistance, ·Gsx ROl 1 KIl
Minimum Load ReSistance, Gsx Rl 10 KIl
Maximum Load Capacitance, Gsx Cl 100 pF
Output Voltage Swing, Gsx VOXI Rl~10K ±2.5 V
Open Loop Voltage Gain, Gsx Avol Rl~10K 5\000. VN
Open Loop Unity Gain Bandwidth, Gsx Fc 2 MHz

c8 SAMSUNG SEMICONDUCTOR 193

KT3040J CMOS INTEGRATED CIRCUIT

AC ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, Ta = 25°C. All parameters are specified for a signal level of OdBmO at 1KHz. The
OdBmO level is assumed to be 1.54 Vrms measured at the output, of the transmit or receive filter.)

Characterlst.ic Symbol Test Condition Min Typ Max Unit

TRANSMIT FILTER (Transmit filter input OP amp set to the non-Inverting unity gain mode,
with V,xl-1.09 Vrme unless otherwise noted.)
- 2.5V < VOUT <2.5V 3 KO
Minimum Load Resistance, V,xo RLX
-3.2V<VOUT<3.2V 10 KO
Load Capacitance, V,xo CLX 100 pF
Output Resistance, V,xo Rox 1 3 0
Vee Power Supply Rejection, VFxo PSRR1 f = 1KHz, V'XI + =0 Vrms 30 dB
Vaa Power Supply Rejection, VFXO PSRR2 f=1KHz, VFXI + =0 Vrms 35 dB
Absolute Gain GAX f=1KHz 2.875 3.0 3.125 dB
Below 50Hz -35' dB
50Hz -41 -35 dB
60Hz -35 -30 dB
200Hz -1.5 0.05 dB
Gain Relative to GAX GRX 300Hz to 3KHz -0.15 0.15 dB
3.3KHz -0.85 0.03 dB
3.4KHz -0.70 -0.1 dB
4.0KHz -15 -14 dB
4.6KHz and above -32 dB
Absolute Delay at 1KHz DAX 230 ,.s
Differential Envelope Delay from
Dox 60 ,.s
1KHz to 2.6KHz ;

Single Frequency Distortion Products Dpx1 -48 dB

,0.16 Vrmo , 1KHz signal
Distortion at Maximum Signal Level Dpx2 Applied to V'XI + , -45 dB
Gain = 20dB, RL = 10K
Total C Message Noise at VFXO NCXl 6 dBrncO
Gain setting OP amp at
20dB, non-Inverting,
Total C Message Noise at V~xo NcX2 7 dBrncO
(Note 3)
Ta=O·C to 70·C
Temperature Coefficient of 1KHz Gain GAXT 0.0004 dBf·C
Supply Voltage Coefficient of 1KHz Vee=5.0V :t5%
GAXS 0.01 dBN
Gain Vee= -5.0V :t5%
Receive filter output =
Crosstalk, Receive to Transmit "
2.2 Vrmo VFXI + =0 Vrms,
CTRX -70 dB
20 Log VFXO f = 0.2KHz to 3.4KHz
VFRO
measure VFXO
Output level = + 3 dBmO -0.1 0.1 dB
Gaintracking Relative to GAx GRXL +2 dBmO to +40 dBmO -0.05 0.05 dB
:"'40 dBmO to -55 dBmO -0.1 0.1 dB,

, 194
c8SAMSUNG SEMICONDUCTOR
KT3040J CMOS INTEGRATED CIRCUIT

AC ELECTRICAL CHARACTERISTICS (Continued)

Characteristic Symbol Test Condition Min Typ Max Vnit

Receive Filter (Unless otherwise noted, the receive filter is preceded by a sin xix filter with an input
signal level of 1.54 Vrms.)
Input Leakage Current, VFRI leR -3.2V sVINs3.2V -100 100 nA
,Input Re,sistance, VFRI RIR 10 'MO
Output Resistance, VFRO ROR 1 3 0

II
Load Capacitance, VFRO CLR 100 pF
Load ReSistance, VFRO RLR 10 KO
Power Supply Rejection of Vcc or VFRI connected to GNDA
PSRR3 35 dB
Vee, VFRO f= 1KHz
Output DC Offset, VFRO VOSRO VFRI connected to GNDA -200 200 mV
Absolute Gain GAR f= 1KHz -0.125 0 0.125 dB
Below 300Hz 0.125 dB
300Hz to 3.0KHz -0.15 0.15 dB
3.3KHz -0.35 0.03 dB
Gain Relative to Gain at 1KHz GRR
3.4KHz -0.7 -0.1 dB
4.0KHz -14 dB
4.6KHz and above -32 dB
Absolute Delay at 1KHz DAR 100 p's
Differential Envelope Delay 1KHz to
DOR 100 P.s
2.6KHz
Single Frequency Distortion Products DpR1 f=1KHz -48 dB
2.2 Vrms input to sin xix.
Distortion at Maximum Signal Level DpR2 Ii Iter, f = 1KHz, -45 dB
RL=10K
Total C·Message Noise at VFRO NCR 6 dBrncO
Temperature Coefficient of 1KHz Gain GART 0.0004 dB/·C
Supply Voltage Coefficient 0l,1KHz
GARS 0.01 dBN
Gain
Transmit filter output =
Crosstalk, Transmit to Receive
2.2 V rms, VFRI = 0 Vrms,
20 Log VFRO CTXR -70 dB
f = 0.3KHz to 3.4KHz
VFXO Measure VFRO
Output level = + 3 dBmO -0.1 0.1 dB
Gaintracking Relative to GAR
+ 2 dBmO to - 40 dBmO -0.05 0.05 dB
GRRL
- 40 dBmO to ...: 55 dBmO -0.1 0.1 dB
Note 5

c8 SAMSUNG SEMICONDUCTOR 195

KT304OJ. CMOS INTEGRATED CIRCUIT

AC ELECTRICAL CHARACTERISTICS (Continued)

Charact.rlstlc Symbol Test Condition Min Typ Max Unit

Receive Output Power Amplifier

Input Leakage Current, PWRI . Isp -3.2VSVINS3.2V 0.1 3 p.A
Input Resistance, PwRI RIP 10 MO
Output Resistance, PWRo +, PWRo- Rop, Amplifiers Active 1 0
Load Capacitance, PWRO +, PWRO - CLP 500 pF
Gain, PWRI to PWRO + GAP + RL = 600 ohm connected 1 VN
Gain, PWRI to PWRO - GAP - between PWRO + and -1 VN
PWRO -, input level = 0
dBmO (Note 4)
Gaintracking Relative to 0 dBmO V=2.05 Vrms, RL=6000 -0.1 0.1 dB
Output Level, Including GRPL V = 1. 75 Vrms, RL = 3000 -0.1 0.1 dB
Receive Filter (Notes 4, 5)
V=2.05 Vrms, RL=6000 -45 dB
Signal/Distortion SlOP V=1.75 Vrms, RL=3000 -45 dB
(Notes 4, 5)
Output DC Offset, PWRO +, PWRO - Vosp PWRI connected to GNDA -50 50 mV
Power Supply Rejection of Vee or Vss PSRR5 P\(\'RI connected to GNDA 45 dB

Note 1. Maximum power consumption will depend on the load impedance connected to the power amplifier. The
specification listed assumes OdBm is delivered to 6000 connected from PWRO + to PWRO - .
2. Voltage input to receive filter at OV, VFRO connected to PWRh 6000 from PWRo + to PWRo -, output measured
. from PWRO + to PWAO - .
3. The OdBmO level for the filter is assumed to be 1.54 Vrms measured at the output o(the XMIT or RCV filter. .
4. The OdBmO level for the power amplifiers is load dependent. For RL=6000 to GNDA,the OdBmO level is 1.43
Vrms measured at the amplifier output. For RL=3000 the OdBmO·level is 1.22 Vrms.
5. VFRO connected to PWRh input signal applied to VFRI.

PIN DESCRIPTION
Pin· Name Function

1 VFXI+ . The non-inverting input to the transmit filter stage.

2 VFXI - The inverting input to the transmit filter stage.
3· Gsx The output used for gain adjustments for the transmit filter.
The low power receive filter output.
4 VFRO
This pin can directly drive the receive port of an electronic hybrid.
5 PWAI The input to the receive filter differential power a,mplifier.
The non-inverting output of the receive filter power amplifier.
6 PWRO +
This output can directly interface conventional transformer hybrids.
The inverting output of the receive filter power amplifier. This output
7 PWRO -
can be used with PWRO + to differentially drive a transformer hybrid.
8 Vss The negative power supply pin. Recommended input is -5V.
9 Vee The positive power supply pin. The recommended input is 5V.
10 VFAI The input pin for the receive filter stage.

c8 SAMSUNG SEMICONDUCTOR
196
KT3040J CMOS INTEGRATED CIRCUIT

PIN DESCRIPTION (Continued)

Pin Name Function

11" GNDD Digital ground input pin. All digital signals are referenced to this pin.
Master input clock. Input frequency can be selected as 2.048MHz,
12 ClK
1.544MHz or 1.536MHz.
The input pin used to power down the KT3040 during idle periods.
13 PDN logic 1 (Vee) input voltage causes a power down condition.
An internal pull.-up is provided.
This input pin selects internal counters in accor.dance with the ClK
14 ClKO
input clock frequency:
CLK Connect CLKO to:
2048KHz Vee
1544KHz GNDD
1536KHz V BB
An internal pull-up is provided.
Analog ground input pin. All analog signals are referenced to this pin.
15 GNDA
. Not internally connected to GNOO•
16 VFXO The output of the transmit filter stage.

TYPICAL PERFORMANCE CURVE

TRANSMIT FILTER STAGE RECEIVE FILTER STAGE

10 10

...- ~ ~n.U
I ~
r-..
-10 -10 FILTER+5IN XIX

1- 20 V \
-20 '"
lIi.x.
~ iI
E -30 -30
~
:Ii
C -40 -40
11\
-so
-60 -60 -x=~
-70 -70
I -i
0.1 10 0.1 10
FREQUENCY (KHz) FREQUENCY (KHz!

c8 SAMSUNG SEMICONDUCTOR 197

 .KT3040J CMOS INTEGRATED CIRCUIT

FUNCTION DESCRIPTION
The KT3040 monolithic filter contains four main sections; transmit filter, receive filter, receive filter power
amplifier, and frequency dividerlselect logic (refer to Figure 1). A brief description of the circuit.operation for each
section is provided below.
Transmit Filter
The input stage of the transmit filter is a CMOS operational amplifier which provides an input resistance of greater
than 101\1D, a voltage gain of greater than 10,000 low power consumption (less than 3mW), high power supply
rejection, and is capable of driving a 10K{1'1oad in parallel with up to 25pF. The inputs and output of the amplifier
are accessible for added flexibility. Non-inverting mode, inverting mode, or differential amplifier mode operation
can be implemented with external resistors. It can also be connected to provide a gain of up to 20dB without degrading
the overall filter performance. . .
The input stage is followed by prefilter which is a twoi pole RC active low pass filter designed to attenuate high
frequency noise before the input signal enters the switched-capacitor .high pass and low pass filters.
A high pass filter is provided to reject 200Hz or lower noise which may exist in the Signal path. The low pass
portion of the switched-capacitor filter provides stopband attenuation which exceeds the Ds and D4specifications
as well as the CCITI G712 recommendations. .
The output stage of the transmit filter, the postfilter, is also a two-pole RC active low pass filter which attenuates
clock frequency nOise by at least 40dB. The output of the transmit filter is capable of driving a ±3.2V peak to
peak Signal into a 10KO load in parallel with up to 25pF. '

Receive Filter
The input stage of the receive filter is a prefilter which is similiar to the transmit prefilter. The prefilter attenuates
high frequency noise that may be present on the receive input signal. A switched capacitor low pass filter follows
the prefilter to provide the necessary passband fi'atness, stopband rejection and sin xix gain correction. A
postfilterwhich is simi liar to the transmit posifilter follows the low pass stage. It attenuates clock frequency noise
and provides a low output impedance capable of directly driving an electronic subscriber-line-interface circuit. (SLlC).

Receive Filter Power Amplifiers

Two power amplifiers are also provided to interface to transformer coupled line circuits. These two amplifiers are
driven by the output of the recei:ve postfilter through gain setting lesistors, Rs, R4 (refer to Fig. 2). The power
amplifiers can be deactivated, when not required, by connecting the power amplifier input (Pin 5) to the negat.ive
power supply Vee. This reduces the total filter power consumption by approximately 10mW·20mW depending on
output sign~ amplitude.

Frequency Divider and Select Logic Circuit

This circuit divides the external .clock frequency down to the switching frequency of the low pass and high pass
switched capacitor filters. The divider also contains a TIL-CMOS interface circuit which converts the external TIL
clock level to the CMOS logic level required for the divider logic. This interface circuit can also be directly driven
by CMOS logic. A frequency select circuit is provided to allow the filter to operate with 2.048MHz, 1.544MHz or
1.536MHz clock frequencies. By connecting the frequency select. pin CLKO (Pin 14) to Vee, a 2.048MHz clock
input frequency is selected. Digital ground selects 1.544MHz and Vee selects 1.536MHz.

Power Down Control

A power down mode is also provided. A logic 1 power down command applied on the PDN pin (Pin 13) will reduce
the total filter power consumption to less than 1mW. Connect PDN to GNDD for normal operation.

'. c8 SAMSUNG SEMICONDUCTOR 198

 KT3040J CMOS INTEGRATED CIRCUIT

APPLICATION INFORMATION
R2 R1

INTERFACE CIRCUIT
r--- - - - - - - - - l GNDA

I TRANSFORMERS I
I 600 I 16>O,1~F
8
I VFXO VFXI
DIGITAl.
I 50K
OUTPUT
I
I KT3040J KT5116
GNDA

I
I
I PWAO-
I
I VFA1
10 13
VFAO
12
DIGITAL
I 60011 O,1~F INPUT
I I 50K

L-------'--~

Fig. 2

Note 1: Transmit voltage gain =R';2 R2 x v'2 (The filter itself introduces a 3dB gain), (R, + R2~ HiK)
Note 2: Receive Gai n =R3+R4R4 (R3 + R4 ~ 10K)
Note 3: In the configuration shown, the receive filter amplifiers will drive a 6000 T to R tennination to a maximum
signal level of B.5dBm. An alternative arrangement, using a transformer winding ratio equivalent to 1.414:1
and 3000 lesistor, Rs, will provide a maximum signal level of 10.1dBm across a 6000 termination
impedance.

Gain Adjust
Fig. 2 shows the signal path interconnections between the KT3040 and KT5116 single-channel CODEC. The trans!11it
RC coupling components have been chosen both for minimum passband droop and to present the correct impedance
to the CODEC during sampling. '
. Optimum noise and distortion perfonnance will be obtained from the KT3040 filter when operated with system
peak overload voltages of ±2.5 to ±3.2V at VFXO and VFAO• When interfacing to a PCM CODEC with a peak
overload voltage outside this range, further gain or attenuation may be required. '
For example, the KT3040 filter can be used with the KT3000 series CODEC which has a 5.5V peak overload voltage.
A gain stage following the transmit filter output and an attenuation stage following the CODEC output are required.

Board Layout
Care must be taken in PCB,layout to minimize power supply and ground noise. Analog ground (GNDA) of each filter
should be connected to digital ground (GNDD) at a single point, which should be bypassed to both power supplies.
Further power supply decoupling adjacent to each filter and CODEC is recommended. Ground loops should be
avoided, both between GNDA and GNPD a~d between the 'GNDA traces of adjacent filters and CODECs.

c8 SAMSUNG SEMICONDUCTOR 199

KT3054J CMOS INTEGRATED CIRCUIT

COMBO CODEC·
18 CERDIP
The KT3054 consists of ,..Iaw· monolithic PCM
CODEC/FILTERS utilizing the AID and DIA conversion
and a serial PCM interface. The devices are fabricated
using double-poly CMOS process C/£-process). The
encode portion of each device consists of an input
gain adjust amplifier, an active RC prefilter which
eliminatesNery high frequency noise prior to entering
a switched-capacitor band-pass filter that rejects
signals below 200Hz and above 3.400Hz.
Also Included are auto-zero circuitry and a companding
coder which samples the filtered signal and encodes
it in the companded ,..Iaw PCM format. The decode
portion of each device consists of an expanding
decoder, which reconstructs the analog signal from
the companded ,..Iaw code. a low-pass filter which
corrects for the sin xix response of the decoder output
and rejects signals above 3,400Hz and is followed by
a single-ended power amplifier capable of driving low
impedance loads.
The devices require two 1.536MHz. 1.544MHz or
2.048MHz transmit and receive master clocks, which
may be asynchronous; transmit and receive bit clocks,
which may vary from 64KHz to 2.048MHz; and transmit
and receive frame sync pulses. The timing of the frame
sync pulses and PCM data is compatible with both
industry standard formats ..

FEATURES
• Complete CODEC and filtering system (COMBO)
Including;.
-:- Transmit high-Pass and low-pass filtering
- Receive low-pass filter with sin xix correction
- ,..Iaw compatible COder and DECoder.
- Internal precision voltage reference
- Active RC noise filters
- Serial I/O interface
- Internal auto-zero circuitry
• ,..Iaw without signaling
• Meets or exceeds all DJD. and CCITT
specifications .
• Low operating power: typically 60mW
• Power-down standby mode: typically 3mW .
• Automatic power-down
• :!: 5V operetlon
• TTL or CMOS compatible digital interfaces
• Maximizes line interface card circuit density

c8 SAMSUNG SEMICONolJCTOR 200

KT3054J CMOS INTEGRATED CIRCUIT

BLOCK DIAGRAMS
R2

R1

ANALOG IN

II

TIMING AND
CONTROL

+5V -5V

,--'
a:w
:0::",
--':0::
0--,
<DO
Fig. 1

ABSOLUTE MAXIMUM RATINGS

Characteristic Value Unit

Vee to GNDA 7 V
Vee to GNDA -7 V
Voltage at Any Analog Input or Output Vcc+0.3 to Vee-0.3 V
Voltage at Any Digital Input or Output Vee +0.3 to GNDA-O.3 V
Operating Temperature Range -25 to + 125 ·C
Storage Temperature Range i -65 to +150 ·C
Lead Temperature (Soldering, 10 secs) / 300 ·C

c8 SAMSUNG SEMICONDUCTOR 201

 KT3054J CMOS INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS
(Unless otherwise noted; Vcc=5.0V ±5%, Vae= - 5V ± 5%, GNDA =OV, Ta=O·C to 70·C; typical qharacteristics
. specified ·at Vcc=5.0V, Vae = -5.0V, Ta=25°C; all signals are referenced to GNDA.)

Characteristic Symbol Test Condition Min Typ Max Unit

Digital Interface
Input Low Voltage VIL 0.6 V
Input High Voltage VIH 2.2 V
Dx,IL=3.2mA 0.4 V
Output Low Voltage VOL SIGR, IL= 1.0mA 0.4 V
TSx, IL = 3.2mA, open drain .0.4 V
Ox, IH = - 3.2mA 2.4 V
Output High Voltage VOH
SIGR, IH = - 1.0mA 2.4 V
Input Low Current IlL GNDA~VIN~VIL' all digital inputs -10 10 pA
Input High Current IIH VIH~VIN~VCC -10 10 p.A
Output Current in High Impedance
loz Ox, GNDA~Vo~Vcc -10 10 pA
State (TRI-STATE)
Analog Interface with Transmit Input Amplifier
Input Leakage Current IIXA -2.5V~V~+2.5V, VFxl+ orVFxl- -200 200 nA
Input Resistance RIXA -2.5V~V~ +2.5V, VFxl+ or VFxl- 10 MO
Output Resistance RoXA Closed loop, unity gain 1 3 0
Load Resistance RLXA GSx 10 KO
Load Capacitance CLXA GSx 50 pF
Output Dynamic Range VoXA GSx, RL~10KO ±2.B V
Voltage Gain AvXA VFxl + to GSx 5,000 VIV
Unity Gain Bandwidth FuXA 1 2' MHz
Offset Voltage VosXA c..20 20 mV
Common-Mode Voltage VcMXA CMRRXA>60dB -2.5 2.5 V
Common-Mode Rejection Ratio CMRRXA DC Test 60 dB
Power Supply Rejection Ratio PSRRXA DC Test 60 dB
Analog Interface with Receive Filter
Out out Resistance RoRF Pin VFRO 1 3 0
.Load Resistance RLRF VFRO= ±2.5V 600 0,
Load Capacitance CLRF 500 pF
Output DC Offset Voltage VOSRO, -200 200 . mV
Power Dissipation
Power-Down Current ·lccO No Load 0.5 1.5 mA
Power-Down Current leeO No Load 0.05 0.3 mA
Active Current Icc1 No Load 6.0 9.0 rnA
Active Current lee1 No Load 6.0 9.0 rnA

c8 SAMSUNG SEMICONDUCTOR 202

KT3054J CMOS INTEGRATED CIRCUIT

TIMING CHARACTERISTICS
Characteristic Symbol Test Condition Min Typ Max Unit

Depends on the device used and the 1.536 MHz

Frequency of Master Clocks l/tPM BClK~ClKSEl Pin. 1.544 MHz
MClKx and MClKR 2.048 MHz
Width of Master Clock High tWMH MClKx and MClKR . 160 ns
Width of Master Clock low . tWML MClKx and MClKR. 160 ns
Rise Time of Master Clock tRM MCLKx and MClKR 50 ns
Fall Time of Master Clock
Set-Up Time from BClKx High
(and FSx in long Frame Sync
Mode) to MClKx Falling Edge
tFM

tSSFM
MClKx and MClKR

First bit clock after the leading

edge of FSx
100
50 ns

ns I
Period of Bit Clock tps 485 488 15,725 ns
Width of Bit Clock High tWSH VIH=2.2V 160 ns
Width of Bit Clock low tWBL V1L =0.6V 160 ns
Rise Time of Bit Clock tRS tps = 488ns 50 ns
Fall Time of Bit Clock tFS tps =488ns 50 ns
Holding Time from Bit Clock
tHsFL long frame only 0 ns
low to Frame Sync
Holding Time from Bit Clock .
tHOLD Short frame only 0 ns
High to Frame Sync
Set-Up Time from Frame Sync
tSFS long frame only 80 ns
to Bit Clock low
Delay Time from BClKx High
tDSD load = 150pF plus 2 lSTTl loads 0 180 ils
10 Dala Valid
Delay Time to TSx low tXDP load = 150pF plus 2 lSTTl loads 140 ns
Delay Time from BClKx low to
IDzc 50 165 ns
Data Oulpul Disabled
Delay Time to Valid Data from
FSx or BClKx,Whlchever IDzF CL=OpF 10 150pF 20 165 ns
Comes later
Set-Up Time from DR Valid to
tSDS 50 ns
BClKRIX low
Hold Time from BClKRIX low to
IHsD 50 ns
DR Jnvalid
Delay Time from BClKRIX low
tOFSSG load = 50pF plus 2 lSTTl loads 300 ns
10 SIGR Valid I

Set-Up Time from FSXlR 10 Short frame sync pulse (lor 2 bit
ISF 50 ns
BClKXIR low . clock periods long) (Note 1) ,

.c8 SAMSUNG SEMICONDUCTOR 203

KT3054J CMOS INTEGRATED CIRCUIT

TIMING CHARACTERISTICS (Continued)

Characteristic Symbol Test Condition Min Typ Max Unit

Hold Time from BCLKXIR Low Short frame sync pulse (1 or 2 bit
tHF 100 ns
to FSXlR Low clock periods long) (Note 1)
Hold Time from 3rd Period of
Long frame sync pulse (from 3 to
Bit Clock Low to Frame Sync tHBFI 100 ns
8 bit clock periods long)
(FSx or FS R)
Minimum Width of the Frame
tWFL 64K bitls operating mode 160 ns
Sync Pulse (Low Level)
Note 1: For short frame sync timing. FSx and FSR must go high while their respective bit clocks are high.

TIMING DIAGRAM

TSx -:--------t\

MCLKR
MCLKx

BCLKX

FSx _ _ _ _--'T

SIGx

Dx---------~

tSDB tHBD tHBD

Fig. 2. Short Frame Sync Timing

c8 SAMSUNG SEMICONDUCTOR, 204

KT3054J CMOS INTEGRATED CIRCUIT

TIMING DIAGRAM (Continued)

FSX
----= f--------tSSFB+-------i tHBSF
I
SFX __________~~+---S-I-G-N-A-Ll-N-G-F-R-A-M-E--~--------------------~--------____~+_--~--~------

----- ,---,
tSSFF \ \

f------++---tSSFB--------i

SFR SIGNALING FRAME

----------------------~------_H--------------------~--+_-------
tSDB tHBD
tHBD

SIGR.
------------------------------------------------------------------------~~-----

Fig. 3 Long Frame Sync Timing

c8 SAMSUNGSEMICONDUCTOR 205
·KT3054J CMOS INTEGRATED CIRCUIT

TRANSMISSION CHARACTERISTICS
(Unless otherwise specifiEld: Ta=O·C to 70·C, Vcc=5V±5%, Vaa= -5V±5%, GNDA=OV, f=1.02KHz,
VIN = OdBmO, transmit Input amplifier connected for unity:galn non-inverting.) .

Characteristic Symbol Test Condition Min Typ Max Unit

Amplitude Response
Nominal OdBmO level is 4dBm (6000) 1.2276 Vrms
Absolute Levels AL
OdBmO·

Max Overload Level tMAX Max overload level (3.17dBmO) .2.501 VPK

Ta=25·C, Vcc =5V, Vaa = -5V·

Transmit Gain, Absolute GXA -0.15 0.15 dB
Input at GSx = OdBmO at 1Q20Hz
f=16Hz -40 dB
f=50Hz -30 dB
f=60Hz -26 dB
f=200Hz -1.8 -0.1 dB
f = 300Hz - 3000Hz -0.15 0.15 dB
Transmit Gain, Relative to GXA GXR
f=33OOHz -0.35 0.05 dB
f=3400Hz -0.7 0 dB
f=4000Hz -14 dB
f = 4600Hz and up, measure -32 dB
response. from OHz to 4000Hz
Absolute Transmit Gain Variation
GXAT Ta = O·C to 70·C ±0.1 dB
with Temperature
Absolute Transmit Gain Variation
GXAV Vcc=5V±5%, Vaa= -5V±5% ±0.05 dB
with Supply Voltage
Sinusoidal test method
Reference level = -10dBmO
Transmit Gain Variations with .
GXRL · VFxl + = - 4OdBmO to + 3dBmO -0.2 0.2 dB
Level
VFxl + = -5OdBmOto -40 dBmO -0.4 0.4 dB
VFxl + = - 55dBmO to - 5OdBmO -1.2 1.2 dB
Ta=25·C, Vcc =5V, Vea= -5V
Receive Gain, Absolute GRA Input = Digital code sequence for -0.15 0.15 dB
OdBmO signal at 1020Hz
f = OHz to 3000Hz -0.15 0.15 dB
f=33OOHz -0.35 0.05 dB
Receive Gain, Re·lative to GRA GRR
f=3400Hz -0.7 0 dB
f=4000Hz -14 dB
Absolute Receive Gain Variation
GRAT Ta = O·C to 70·C ±0.1 dB
with Temperature
Absolute Receive Gain Varlation
GRAv Vcc=5V±5%, Vea= -5V±5% ±0.05 dB
with Supply Voltage
. Sinusoidal test method; reference
input PCM code corresponds to an
Re.ceive Gain Variations with Ideally encoded-10dBmO signal
GRRl
Level PCM level = - 40dBmO to + 3 dBmO -0.2 0.2 dB
PCM level = -5OdBmO to -40dBmO -0.4 0.4 dB
PCM level = - 55dBmO to - 5OdBmO -1.2 1.2 dB
Receive Output Drive Level VRO Rl =6001l -2.5 2.5 V

c8 SAMSUNG SEMICONDUCTOR 206

KT3054J CMOS INTEGRATED CIRCUIT

TRANSMISSION CHARACTERISTICS (Continued)

Characteristic Symbol Test Condition Min Typ Max Unit

Envelope Delay Distortion with Frequency

Transmit Delay, Absolute OleA f= 1600Hz 290 315 ILs
f = 500Hz - 600Hz 195 220 ILS
f = 600Hz - 600Hz 120 145 ILs
f = 800Hz - 1000Hz 50 75 ILS
Transmit Delay, Relative to DXA DXR f = 1000Hz -1600Hz 20 40 ILS
f = 1600Hz - 2600Hz 55 75 ILs -
f = 2600Hz - 2800Hz 80 105 ILs
=
f 2800Hz - 3000Hz 130 155 ILS
Receive Delay, Absolute ORA f= 1600Hz 180 200 ILs
f = 500Hz - 1000Hz -40 -25 ILS
f = 1000Hz - 1600Hz -30 -20 ILs
Receive Delay, Relative to ORA ORR f = 1600Hz - 2600Hz 70 - 90· ILS
f = 2600Hz - 2800Hz 100 125 ILs
f = 2800Hz - 3000Hz 145 175 ILs
Noise
Transmit Noise, C Message
Nxe VFxl+ =OV 12 15 d8rnCD
Weighted
Receive Noise, C Message PCM code equals alternating
NRC 8 11 dBrnCD
Weighted positive and negative zero
f=OKHz to 100KHz, loop around
Noise, Single Frequency NRS
measurement, VFxl + = OVrms
-53 dBmO

VFxl + = OV,rms,
Positive Power Supply Rejection,
PPSRx Vee = 5.0Voe + 100mVrms 40 dBC
. Transmit
f = OKHz - 50KHz
VFxl + = OVrms,
Negative Power Supply Rejection,
NPSRx Vee = - 5.0Voe + 100mVrms 40 dBC
Transmit
f = OKHz - 50KHz
PCM code equals positive zero
Vee = 5.0Voc + 100mVrms
Positive Power Supply Rejection,
PPSRR f = OHz - 4000Hz 40 dBC
Receive
f = 4KHz - 25KHz 40 dB
f == 25KHz - 50KHz 36 dB
PCM code equals positive zero
Vee= -5.0Voc + 100mVrms
Negative Power Supply Rejection,
NPSRR f = OHz -:- 4000Hz 40 dBC
Receive
f = 4KHz - 25KHz , 40 dB
f = 25KHz - 50KHz 36 dB

c8 SAMSUNG SEMICONDUCTOR 207

KT3054J CMOS INTEGRATED CIRCUIT

TRANSMISSION CHARACTERISTICS (Continued)

Characteristic Symbol Test Condition Min Typ Max Unit

. Loop around measurement, OdBmO,

300Hz - 3400Hz input applied to
VFxl + , Measure individual image
Spurious Out-of-Band Signals
SOS signals at VFRO
at the Channel Output
4600Hz - 7600Hz -32 dB
7600Hz - 8400Hz -40 dB
8400Hz -100,OOOHz' -32 dB
Distortion
Signal to 'Total Distortion STDx Sinusoidal test method
Level = 3.0dBmO 33 dBC
=OdBmO to 130dBmO 36 dBC
Transmit or Receive = -40dBmO XMT 29 dBC
STDR
Half-Channel RCV 30 dBC
'" - 55dBmO XMT 14 dBC
RCV 15 dBC
Single Frequency Distortion,
SFDx -46 dB
Transmit
Single Frequency Distortion,
SFDR -46 dB
Receive
Loop around measurement,
VFx + = -4dBmO to -21dBmO, two
Intermodulation Distortion IMD -41 dB
frequencies in the range
300Hz - 3400Hz
Crosstalk
Transmit to Receive Crosstalk, f = 300Hz - 3400Hz
CTX.R -90 -75 dB
OdBmO Transmit Level DR = Steady PCM code
Receive to Transmit Crosstalk, -70
OdBmO Receive Level
CTR-x f = 300Hz - 3400Hz, VFxl = OV -90 dB
(Note 1)

Note 1. CTR.X is measured with a - 4OdBmO activating signal applied at VFxl +

ENCODING FORMAT AT DxOUTPUT

V1N (at GSx) = + Full - Scale 10000000
11111111
V1N (at GSx) = OV
01111111
V1N (at GSx) = - Full - Scale. 00000000

c8 SAMSUNG SEMICONDUCTOR 208

KT3054J CMOS INTEGRATED CIRCUIT

PIN DESCRIPTION
Pin No. Symbol Description .

1 Vee Negative power supply pin. Vee = -5V ±5%.

2 GNDA Analog ground. All signals are referenced to this pin.
3 VFRO Analog output of the receive filter.
4 Vee Positive power. supply pin. Vee = + 5V ± 5%.
Receive frame sync pulse which enables BClKR to shift PCM data
5 FSR

I
into DR. FSR is an 8KHz pulse train.
Receive data input. PCM data is shifted into DR following the FSR
6 DR
leading edge.
The bit clock which shifts data into DR after the FSR leading edge.
Many vary from 64KHz to 2.048MHz. Alternatively, may be a: logic
BClKR/
7 input which selects either 1.536MHzl1.544MHz or 2.048MHz for
CLI~SEl
master clock in synchronous mode and BClKx is used for both
·transmit and receive directions.
Receive master clock. Must be 1.536MHz, 1.544MHz or 2.048MHz.
, May be asynchronous with MClKx, but should be synchronous with
MClKR/
8 MClKx for best performance. When MClKRis connected continously
PDN
low, MClKR is selected for all internal timing. When MClKR is
connected continuously high the device is powered down.
Transmit master clock. Must be 1.536MHz, 1.544MHz or 2.048MHz.
9 MClKx
Maybe asynchronous with MClKR.
The bit clock which shifts out the PCM data on Dx. May vary from
10 BClKx
64KHz to 2.048MHz, but must be synchronous with MClKx.
11 Dx The TRI·STATE PCM data output which is enabled by FSx.
Transmit frame sync pulse input which enables BClKx to shift
12 FSx
out the PCM data on Dx. FSx·is an 8KHz pulse train.
13 TSx Open drain ouptut which pulses low during the encoder time slot.
Analog output of the transmit input amplifier.
14 GSx
Used to externally !iet again.
15 VFxl- Inverting input of the transmit input amplifier.
16 VFxl+ Non·inverting input of the trans.mitinput amplifier.

PIN CONNECTION
VFx'+

VFx'-

GSx

TSx
KT3054J FSx

DR 6
BCLKRI
BCLKx
CLKSEL
MCLKRI
PDN

c8 SAMSUNG SEMICONDUCTOR' 209

KT3054J CMOS INTEGRATED CIRCUIT

FUNCTIONAL DESCRIPTION
POWER·UP
When power is first applied, power-on reset circuitry initializes the COMBO and places it into the power-down mode.
All non-essential circuits are deactivated and the Ox and VFRO outputs are put in high impedance states. To power-
up the device, a logical low level or clock must be applied to the MCLKFJPDN pin and FSx and/or FSRpulses must
be 'present. Thus, 2 power-down control modes are available. The first is to pull the MCLKFJPDN pin high; the
alternative is to hold both FSx and FSR inputs continuously low-the device will power-down approximately 2ms
after the last FSx or FSR pulse. Power-up will occur on the first FSx or FSR pulse. The TRI-STATE PCM data
output, Dx, will remain in the high impedance state until the second FSx pulse.

SYNCHRONOUS OPERATION
For synchronous operation, the same master clock and bit clock should be used for both the transmit and receive
directions. In this mode, a clock must be applied to MCLKx and the MCLKFJPDN pin can be used as a power-down
control. A low level on MCLKR/PDN powers up the device and a high level powers down the device. In either case,
MCLKx will be selected as the master clock for both the transmit and receive circuits. A bit clock must also be
applied to BCLKx and the BCLKFJCLKSEL can be used to select the proper internal divider for a master clock of
1.536MHz, 1.544MHz or 2.048MHz. For 1.544MHz operation, the device automatically compensates for the 193rd
clock pulse each frame.
With a fixed level on the BcLKFJCLKSEL pin, BCLKx will be selected as the bit clock for both the transmit and
receive directions. In this synchronous mode, the bit clock, BCLKx, may be from 64KHz to 2.048MHz, but must
be synchronous with MCLKx.
Each FSx pulse begins the encoding cycle and the PCM data from the previous encode cycle .is shifted out of
the enabled Dx output on the positive edge of BCLKx. After 8 bit clock periods, the TRI·STATE Dx output is retumed
to a high impedance state. With an FSRpulse, PCM data is latched via the DR Input on the negative edge of BCLKx
(or BCLKR if running). FSx and FSR must be synchronous with MCLKXlR .
TABLE 1. Selection of Master Clock Frequencies
BCLKR/CLKSEL Master Clock Frequency Selected
Clocked, 1.536MHz or 1.544MHz
0 2.048MHz
1 (or Open Circuit) 1.536MHz or 1.544MHz

ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit and receive clocks may be applied .. MCLKx and MCLKR must be
1.536MHz, 1.544MHz for the KT3054, and need not be synchronous. For best transmission performance, however,
MCLKR should be synchronous with MCLKx, which is easily achieved by applying only static logic levels to the
MCLKFJPDN pin. This will automatically connect MCLKx to all internal MCLKR functions (see Pin Description). For
1.544MHz operation, the device automatically compensates fo~ the 193rd clock pulse each frame. FSx starts each
encoding cycle and must be synchronous with MCLKx and BCLKx. FSR starts each decoding cycle and must be
synchronous with BCLKR. BCLKRmust be a clock, the logic levels shown in Table 1 are not valid in asynchropous
mode. BCLKx and BCLKR may operate from 64KHz to 2.048MHz. .

SHORT FRAME SYNC OPERATION

The COMBO can utilize a long frame sync pulse. Upon power initialization, the device assumes a short frame mode.
In this mode, both frame sync pulses, FSx and FSR, must be one bit clock period long, ""ith timing relationships
specified in Figure 2. With FSx high during a falling edge of BCLKx, the next rising edge of BCLKx enables the
Ox TRI-STATE output buffer, which will output the sign bit. The following seven rising edges clock out the
remainirig seven bits, and the next falling edge c;lisables the Dx Ol,ltput. With FSR high during a falling edge of
BCLKR(BCLKx In synch~onous mode), the next falling edge of BCLKR latches in the sign bit. The following seven
falling edges latgch in the seven remaining bits. All four devices may utilize the short frame sync pulse in synchronous
or asynchronous operating mode. '

c8 SAMSUNG SEMICONDUCTOR 210

KT3054J CMOS INTEGRATED CIRCUIT

LONG FRAME SYNC OPERATION

To use the frame mode, both the frame sync pulses, FSx and FSR, must be three or more bit clock periods
long, with timing relationships specified in Figure 3. Based on the transmit frame sync, FSx, the COMBO will
sense whether short or long frame sync pulses are being used. For 64KHz operation, the frame sync pulse
must be kept low for a minimum of 160ns. The Dx TRI-STATE output buffer is enabled with the rising edge of FSx
or the rising edge of BClKx, whichever comes later, and the first bit clocked out is the sign bit. The following
seven BClKx rising edges clock out the remaining seven bits. The Dx output is disabled by the falling BClKx edge
following the eighth rising edge, or by FSx going low, whichever comes later. A rising edge on the receive frame
sync pulse, FSR, will cause the PCM data at DA to be latched in on the next eight falling edges of BClKR (BClKx
in synchronous mode). All four devices may utilize the long frame sync pulse in synchronous or asynchronous mode.
RECEIVE SECTION

I
The receive section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter
clocked at 256KHz. The decoder is A-law or wlaw (KT3054) and the 5th order low pass filter corrects for the sin x/x
attenuation due to the 8KHz sample/hold. The filter is then followed by a 2nd order RC active post-filter/power
amplifier capable of driving a 6000 load to a level of 7.2dBm. The receive section is unity-gain. Upon the
occurrence of FSR; the data at the DR input is clocked in on the falling edge of the next eight BClKA (BClKx)
periods. At the end of the decoder time slot, the decoding cycle begins, and 10l-ls later the decoder DAC output
is updated. The total decoder delay is -10l-ls (decoder update) plus 110l-ls (filter delay) plus 62.51-1s (1/2 frame), which
gives approximately 180l-Is.

TRANSMIT SECTION
The transmit section input is an operational amplifier with provision for gain adjustment using two external
resistors, see Figure 4. The low noise and wide bandwidth allow gains in excess of 20dB across the audio
passband to be realized. The op amp drives a unity-gain filter consisting of RC active pre-filter, followed by an eighth
order switched-capacitor bandpass filter clocked at 256KHz. The output of this filter directly drives the encoder
sample-and-hold circuit. The AID is of companding type according to wlaw (KT3054) or A-law coding conventions. A
precision voltage reference is trimmed in manufacturing to provide an input overload (tMAxl of nominally 2.5V peak
(see table of Transmission Characteristics). The FSx frame sync pulse controls the sampling of the filter output,
and then the successive-approximation encoding cycle begins. The 8-bit code is then loaded into a buffer and shifted
out through Dx at the next FSx pulse. The total encoding delay will be approximately 1651-1s (due to the transmit
filter) plus 1251-1s (due to encoding delay), which totals 290l-Is. Any offset voltage due to the filters or comparator
is cancelled by sign bit integration.

APPLICATION INFORMATION
POWER SUPPLIES
In applications where the printed circuit board may be plugged into a "hot" socket with power and clocks already
present, an extra long ground pin in the connector should be used.
All ground connections to each device should meet at a common point as close as possible to the GNDA pin.
This minimizes the interaction of ground return currents flowing through a common bus impedance. 0.11-1F supply
decoupling capacitors should be connected from this common ground point to Vee and Vee.
For best performance, the ground point of each CODEC/FllTER on a card should be connected to a common card
ground in star formation, rather than via a ground bus.
This common ground point should be decoupled to Vee and Vee with 10l-lF capacitors.
RECEIVE GAIN ADJUSTMENT
For applications where CO DEC/filter receive output must drive a 6000 load, but a peak swing lower than ± 2.5V
is required, the receive gain can be easily adjusted by inl?erting a matched T-pad or r-pad at the output. Table"
lists the required resistor values for 6000 terminations. As these are generally non-standard values, the equations
can be used to compute the attenuation of the closest practical set of resistors. It may be necessary to use
unequal values for the R1 or R4 arms of the. attenuators to achieve a precise attenuation. Generally it is tolerable
to allow a small deviation of the input impedance from nominal while still maintaining a good return loss. For
example a 30dB return loss against 6000 is obtained if the output impedance of the attenuator is in the range 2820
to to 3100 (assuming a perfect transformer).

c8 SAMSUNG SEMICONDUCTOR 211

KT3054J CMOS INTEGRATED CIRCUIT

'/I"-Pad Attenuator T-Pad Attenuator

r-------.., r-------...,
3001 R3 I 300 I R1 111 I

~ l 1:,.[2,2U600 I
I
R4 R4 IZ2
I
Z1!
I 1
I
IL.. ___ _

N +1
2 N
R1 = Z1 (W-1)-~ (N2-1)
N
R2 = z,J Z1'Z2 (w=-:1)
. I POWER IN
Where: N ='\1 POWER OUT
and

s=~
Also: Z = .JZsc,-Zoc .
Where Zsc, = impedance with short circuit termination.
and Zoe = impedance with open circuit termination

TABLE II. Attenuator Table for Z1 = Z2 = 3000 (All Values in 11)

dB R1 R2 R3 R4

0.1 1.7 26K 3.5 52K

0.2 3.5 .13K 6.9 26K
0.3 5.2 8.7K 10.4 17.4K
0.4 6.9 6.5K 13.8 13K
0.5 8.5 5.2K 17.3 10.5K
0.6 10.4 4.4K 21.3 8.7K
0.7 12.1 3.7K 24.2 7.5K
0.8 13.8 3.3K 27.7 6.5K
0.9 15.5 2.9K 31.1 5.8K
1.0 17.3 2.61 34.6 5.2K
2 34.4 1.3K 70 2.6K
3 51.3 850 107 1.8K
4 68 650 144 1.3K
5 84 494 183 1.1K
6 100 402 224 900
7 115 380 269 785
8 379 284 317 698
9 143 244 370 630
10 156 211 427 527
11 168 184 490 535
12 180 161 550 500
13 190 142 635 473
14 200 125 . 720 450
.15 210 110 816 430
16 218 98 924 413
18 233 77 1.17K 386
20 246 61 1.5K 366

c8 SAMSUNG SEMICON~UCrOR 212

KT3054J CMOS INTEGRATED CIRCUIT

APPLICATION CIRCUITS

Vee VFxl+ FROM SLiC

GNDA VFxl -

Vee GSx
-5V
ANALOG
INTERFACE
KT3054J
______ 1
I
TO SllC VFRO
------ - ----------
FROM TSAC' FSR FSx FROM TSAC I
DIGITAL
DR Ox INTERFACE

5V OR GNDA BClKR/ClKSEl BClKx

PDN MClKR/PDN MClKx BClKx (2.048MHzl1.544MHz)

Note: XMIT gain = 20 x log(R1 :t2),

(R1 + R2) > 10KO.

Fig. 4

c8 SAMSUNG SEMICONDUCTOR 213

KT3064J CMOS INTEGRATED CIRCUIT

COMBO CODEC
20 CERDIP
The KT3064 Vt-Iaw), is monolithic PCM CODECI
FILTERS utilizing the AID and D/A conversion, a serial
PCM interface. The devices are fabricated using
double-poly CMOS process. The device feature an
additional receive power amplifierto'provide push-pull
balanced output drive capability. The receive gain can
be adjusted by means of two external resistors for an
output level of up to ± 6.6V across a balanced 6000
load. The Analog Loopback switch and TSx output is
also included.

FEATURES
• wlaw compatible
• Meets or exceeds all D3JD4 and CCITT
specifications
• :!: 5V operation
• Low operating power: typically 7,OmW
• Active RC noise filters
• Power-down standby mode: typically 3mW
• Automatic power-down
• Transmit high-pass and low-pass filtering
• Internal precision voltage reference
• Serial I/O interface
• Internal auto-zero circuitry
• TTL or CMOS compatible digital interfa,ce
• Maximizes line interface card circuit density

BLOCK DIAGRAM
R2

c8 SAMSUNG SEMICONDUCTOR 214

KT3064J CMOS INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Vee to GNDA Vee 7 V

Vae to GNDA Vee -7 V
Voltage at Any Analog Input or Output Analoge 1/0 Vee+0.3 to VeB -0.3 V
Voltage. at Any Digital Input or Output Digital 1/0 Vee+0.3 to GNDA-0.3 V
Operating Temperature Range Ta -25-+125 ·C

I
Storage Temperature Range T. -65-+150 ·C
Lead Temperature Soldering, 10 secs) TL 300 ·C

ELECTRICAL CHARACTERISTICS
(Unless otherwise noted: Vee=5.0V±5%, Vee= -5V±5%, GNDA=OV, Ta=O·C to 70·C; typical characteristics
specified at Vee = 5.0V, Ta = 25°C; ali signals are referenced to GNDA)

Characteristic Symbol Test Condition Min Typ . Max Unit

Power Dissipation
Active Current led1 Power amplifiers active, VPI = OV 7.0 10.0. mA
Active Current lee1 Power amplifiers active, VPI = OV 7.0 10.0 mA
Power'Down Current leeo 0.5 1.5 . mA
Power·Down Current leBo 0.05 0.3 mA
Digital Interface
Input Low Current hL GNDAsV1NSV1L, Ali digital inputs -10 10 p.A
Input High Current I'H V'HSV'NSVee -10 10 p.A
Output Current in High
loz Ox, GNDASVoSVee -10 10 p.A
Impedance State (TRI·STATE)
Input Low Voltage V'L 0.6 V
Input High Voltage V'H 2.2 V
Dx,IL=3.2mA 0.4
Output Low Voltage VOL SIG R, IL = 1.0mA 0.4 V
Tsx, IL=3.2mA, Open Drain 0.4
Ox, IH = - 3.2mA 2.4
Output High Voltage VOH V
SIG R, IH = - 1.0mA ·2.4
Analog Interface with Transmit Input Amplifier
Input Leakage Current I,XA - 2.5V sV S + 2.5V, VFxl + or VFxl- -200 200 nA
Input Resistance R,XA - 2.5V sV S + 2.5V, VFxl + or VFxl- 10 MO
Output Resistance RoXA Closed loop, unity gain 1 3 MO
Load Resistance RLXA GSx 10 KO
Load Capacitance CLXA GSx 50 pF
Output Dynamic Range VoXA GSx, RL~ 10KO ±2.B V

ciS SAMSUNG SEMICONDUCTOR 215

KT3064J CMOS INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS (Continued)

, Characteristic Symbol Test Conditions Min Typ Max Unit

Voltage Gain Av'XA VFxl + to GSx 5000 VIV

Unit-Gain Bandwidth FuXA 1 2 MHz
Offset Voltage ViJsXA -20 20 mV
Common-Mode Voltage VeMXA CMRRXA>60dB -2.5 2.5 V
Common-Mode Rejection Ratio CMRRXA DC Test 60 dB
Power Supply Rejection Ratio PSRRXA DC Test 60 dB
Analog Interface with Receive Filter (All Devices)
Output Resistance RoRF Pin VFRO 1 3 0
Output DC Offset Voltage VOSRO Measure from VFRO to GNDA -200 200 mV
load Resistance RLRF VFRO= ±2.5V 10 KO
load Capacitance CLAF Connect from VFRO'to GND A 25 pF
Analog Interface with Power Amplifiers (All Devices)
Input Leakage Current IPI -1.0V:s;VPI:s;1.0V:s;VPI:s;1.0V -100 100 nA
Input Resistance RIPI -1.0V :s;VPI:s; 1.0V 10 MO
Input Offset Voltage Vias , -25 25 mV
Inverting unity gain at
Output Resistance ROP 1 0
VPO+ or VPO-
Unit-Gain Bandwidth Fe Open loop (VPO - ) 400 KHz
RL~15000 VPO+ or 100 pF
load Capacitance CLP RL = 6000 VPO- to 500 pF
Rl = 3000 GNDA 1000 pF
RL::: 3000 VPO + to GNDA level at
Gain from VPO - to VPO + GA p + -1 VIV
VPO-::: -1.77Vrms (+3dBmo)
VPO - connected to. VPI
Power Supply Rejection of
PSRR p OKHz-4KHz 60 dB
Vee or VBB
OKHz-50KHz 36 dB

Frequency of Master Clock IltpM

Depends on the device used and
the BClKR/ClKSEl Pin
MClKx and MClKA
1.536
1.544
'2.048
. MHz
MHz
MHz
Width of Master Clock High tWMH MClKx and MClKR 160 ns
Width of Master Clock low tWML MClKx and MClKR 160 ns
Rise Time of Master Cl:ock tRM MClKx and MClKR 50 ns
Fall Time of Master Clock tFM MClKx and MClKR 50 ns
Set-Up Time from BCLKx High
First bit clock after the leading
(and FSx in long Frame Sync' tSBFM 100 ns
edge of FSx
Mode) to MClKx Falling Edge
Period of Bit Clock tps 485 488 15,725 ns
Width of Bit Clock High tWBH V'H= 2.2V 160 ns
Width of Bit Clock low tWBl Vll:::0.6V 160 ns
Rise Time of Bit Clock tRB tPB= 460ns 50 ns
Fall Time of Bit Clock tF8 tPB= 488ns 50 ns

c8 SAMSUNG SEMICONDUCTOR 216

KT3064J CMOS INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS (Continued)

Characteristic Symbol Test Conditions Min Typ Max Unit

Holding Time from Bit Clock

tHBF Long frame only 0 ns
Low to Frame Sync
Holding Time from Bit Clock
tHOLO Short frame only 0 ns
High to Frame Sync
Set-Up Time for Frame Sync
tSFB Long Frame Only 80 ris
to Bit Clock Low

II
Delay Time. from BCLKx High
tOBo Load = 150pF plus 2 LSTIL loads 0 180 ns
to Data Valid
Delay Time to TSx Low txop Load = 150pF plus 2 LSTIL loads 140 ns
Delay Time from BCLKx Low
tOEe 50 165 ns
to Data Output Disabled
Delay Time to Valid Data from
FSx or BCLKx, tOZF CL=OpF to 150pF . 20 165 ns
whichever Comes Later
Set-Up Time from DR Valid to
tSOB 50 ns
BCLKRIX Low
Hold Time from BCLKR/x Low
IHBO 50 ns
to DR Invalid
Delay Time from BCLKRIX Low
tOFSSF Load = 50pF plus 2 LSTIL loads 300 ns
to SIGR Valid
Set-Up Time from FSX1R to Short frame sync pulse
tSF 50 ns
BCLKXlR Low (1 or 2 bit clock periods 10ng)(Note 1)
Hold Time from BCLKx1R Low Short frame sym; pulse
tHF 100 ns
. to FSXlR Low (1 or 2 bit clock periods 10ng)(Note 1)
Hold Time from 3rd Period of
Long frame sync pulse
Bit Clock low to Frame Sync tHBFI 100 ns
(from 3.to 8 bit clock periods long)
(FSx of FSR)
Minimum Width of the Frame .
tWFL 64K bitls operating mode 160 ns
Sync Pulse (Low Level)

Note 1: For short frame sync timing, FSx and FSR must go high while their respective bit Clocks are high.

PIN CONFIGURATION
>
.
.,
+
J'
> >
I
J'
::
..J
u
In
~
'..J
U
:::;;

+ «
0
I
0: 0 u a: a: Ii: z
0 0 a: <) (/) 0 0
>
Il.
>
Z
(!)
Il.
>
IL
>
> IL
"
..J
u
Il.
Ii:
In
"U:::;;
..J

c8 SAMSUNG SEMICONDUCTOR 217

 KT3064J CMOS INTEGRATED CIRCUIT

TIMING DIAGRAM

MClKx
MClKA

BlCKx

FSx

loze

Ox

BClKA

Fig. 2. Short Frame Sync Timing

MClKX
MClKA

BClKx

FSX

Ox

BClKA

FSR ----J["

Fig. 3 Long Frame Sync Timing

c8 SAMSUNG SEMICONDUCTOR 218

KT3064J CMOS INTEGRATED CIRCUIT

PIN DESCRIPTION
Pin Name Function

1 VPO+ The non-inverted output of the receive power amplifier.

2 GNOA Analog ground. All signals are referenced to this pin.
3 vpo- The inverted output of the receive power amplifier.
Inverting input to the receive power amplifier.
4 VPI
Also powers down both amplifiers when connected to Vee.
5 VFAO Analog output of 'the receive filter.
6

7
Vee'

FSA
Positive power supply pin Vee = +5V±5%.
Receive frame sync pulse which enables BClKA to shift PCM data into
OA, FS A is an BKHz pulse train. (refer to Fig 2 and 3 for timing details)
Receive data input. PCM data is shifted into OA following the FSA
II
B OA
leading edge.
The bit clo.ck which shifts data into OA after the FSA leading edge.
,May vary from 64KHz to 2.04BMHz. Alternatively, may be a logic input
BClKFJ
9 which selects either 1.536MHzl1.544MHz or 2.04BMHz for master clock
ClKSEl
in synchronous mode and BClKx is used for both transmit and receive
directions. (see Table 1)
Receive master clock. Must be 1.536MHz or 2.04BMHz. May be
asynchronous with MClKx, but should be synchronous with MClKx
MClKAI
10 for best performance. When MClKA is connected continuously low,
PON
MClKx is selected for ,all internal timing. When MClKA is connected
continuously high, the device is powered down.
Transmit master clock. Must be 1.536MHz, 1.544MHz or 2.04BMHz.
11 MClKx
May be asyncl"jronous with MClKA,
The bit clock which shifts out the PCM data on Ox. May vary from
12 BClKx
64KHz to 2.04BMHz, but must be synchronous with MClKx.
13 Ox The TRI-STATE PCM data output which is enabled by FSx.
Transmit frame sync pulse input which enables BClKx to shift out the
14 FSx
PCM data a on Ox, FSx is an BKHz pulse train. (refer to Fig 2, 3)
1,5 TSx Open drain output which pulses low during t~e encoder time slot.
'Analog loopback control inpu!. Must be set to logic '0' for normal
operation. When pulled to logic '1', the transmit filter input is dis
16 ANlB
connected from the output of the preamplifier and connected to the
VPO+ output of the receive power, amplifier.
Analog output of the transmit input amplifier.
17 GSx
Used to externally set again.
1B VFxl- Inverting input of the transmit input amplifier.
19 YFxl+ Non-inverting input of the transmit input amplifier.
20 Vee Negative power supply pin Vee::: - 5V ± 5%.

c8 SAMSUNG SEMICONDUCTOR 219

KT3064J CMOS INTEGRATED CIRCUIT

.FUNCTIONAL DESCRIPTION
POWER·UP
When. power is first applied, power-on reset circuitry initializes the COMBO and places it into the power-down mode.
All non-essential circuits are deactivated and the Ox, VFRO, VPO - and VPO + outputs are put in high impedance
states. To power-up the device, a logical low level or clock must be applied to the MCli<R/PON pin and FSx and/or
FSR pulses must be present. Thus, 2·power-down control modes are available. The first Is to pull the MClKR/PON -
pin high; the alternative is to hold both FSx and FSRinputs continuously low-the device will power-down approxi-
mately 2ms after the last FSx or FSRpulse. Power-up will occur on the first FSx or FSRpulse. The TRI-STATE PCM
data output, Ox, will remain in the high impedance state until the second FSx pulse.

SYNCHRONOUS OPERATION
For synchronous operation, the same master clock and bit clock should be used for both the transmit and .receive
directions. In this mode, a clock must be applied to MClKx and the MClKR/PON pin can be used as a power-down
controL A low level on MCLKFJPON powers up the device and a high level powers down the device. In either case,
MClKx will be selected as the master clock for both the transmit and receive circuits. A bit dock must also be
applied to BClKx arid the BCLKR/ClKSEl can be used to select the proPer internal divider for a master clock of
1.536MHz, 1.544MHz or 2.048MHz. For 1.544MHz operation, the device automatically compensates for the 193rd
clock pulse each frame.
With a fixed level On the BClKR/ClKSEl pin, BClKx will be selected as the bit clock for both the transmit and
receive directions. In synchronous mode, the bit clock, BClKx, may be from 64KHz to 2.048MHz, but must be
synchronous with MClKx. Each FSx pulse begins the encoding cycle and the PCM data from the previous encode
cycle is shifted out of the enabled Ox output on the positive edge of BClKx. After 8 bit clock periods, the TRI-
STATE Ox output is returned to a high impedance state. With an FSRpulse, PCM data is latched via the DR input
on the negative edge of BClKx (or BClKR if running). FSx and FSR must be synchronous with MClKx/R:

TABLE 1_ Selection of Master Clock Frequencies

BCli<R/ClKSEl Master Clock Frequency Selected
Clocked 1.536MHz or 1.544MHz
0 2.048MHz
1 (or Open Circuit) 1.544MHz

ASYNCHRONOUS OPERATION
. For asynchronous operation, separate transmit and receive clocks maybe applied. MClKx and MClKR must be
1.536MHz, 1.544MHz for the KT3064, and need not be synchronous. For best transmission performance, however,
MClKR should be synchronous with MCLKx, which is easily achieved by applying only static logic levels to the
MClKFJPON pin. This will automatically connect MClKx to all internal MClKRfunctions (refer to pin description).
For 1.544MHz operation, the device automatically compensates for the 193rd clock pulse each frame.
FSx starts each encoding cy.cle and must be synchronous with MClKx and BClKx. FSR starts each decoding
cycle and must I;le synchronous with BCl~, BClKRmust be a clock. BCLKx and BClKR ma~y operate from 64KHz
to 2.048MHz.

SHORT FRAME SYNC OPERATION

The COMBO can utilize either a short frame sync pulse or a long frame sync pulse. Upon power initialization, the
device assumes a short frame mode. In this mode, both frame sync pulses, FSx and FSR, must be one bit clock
period long (refer to Fig. 2). With FSx high during a falling edge of BClKx, the next rising edge of BClKx
enables the Ox TRI-STATE output buffer, which will output the sign bit. The following seven rising edge disables
the Ox output. With FSRhigh during a fallinlJ edge of BClKR (BClKx in synchronous mode), the next falling edge
of BClKRlatches in the sign bit. The following seven falling edges latch in the seven remaining bits. Both devices
may utilize the short frame sync pulse in synchronous or asynchronous operating mode.

c8 SAMSUNG SEMICONDUCTOR . 220

 KT3064J CMOS INTEGRATED CIRCUIT

LONG FRAME SYNC OPERATION

To use the long (KT5116-type) frame mode, both the frame sync pulses, FSx and FSR, must be three or more bit
clock periods long (refer to Fig. 3). Based on the transmit frame sync, FSx, the COMBO will sense whether short
or long frame sync pulses are being used. For 64KHz operation, the frame sync pulse must be kept low for a
minimum· of 160ns. The Ox TRI-STATE output buffer is enabled with the rising edge of FSx or the rising edge of
BClKx, whichever comes later, and the first bit clocked out is the sign bit. The following seven BClKx rising edges
clock out the remaining seven bits. The Ox output is disabled by the falling BClKx edge following the eight
falling edges of BClKR (BClKx in synchronous mode). Both devices may utilize the long frame sync pulse in
synchronous or asynchronous mode.

TRANSMIT SECTION

II
The transmit section input is an operational amplifier with provision for gain adjustment using two external
resistors. The low noise and wide bandwidth allow gains in excess of 20dB across the audio passband to be
. realized. The OP amp drives a unity-gain filter consisting of RC active pre-filter, followed by an eighth order switched·
capacitor bandpass filter clocked at 256KHz. The output of this filter directly drives the encoder sample·and-hold
circuit. The A/D is of companding type according to wlaw (KT3064) coding conventions. A precision voltage
reference is trimmed in manufacturing to provide an input overload (t m..} of nominally 2.5V peak. The FSx frame
sync pulse controls the sampling of the filter output, and then the successive-approximation encoding cycle
begins. The 8-bit code is then loaded into a buffer and shifted out through Ox at the next FSx pulse. The total
encoding delay will be approximately 165i,ts (due to the transmit filter) plus 125jLs (due to encoding delay), which
totals 290jLs. Any offset voltage due to ~he filters or comparator is cancelled by sign bit integration.

RECEIVE S!:CTION
The receive section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter
clocked at 256KHz. The decoder is wlaw (KT3064) and 5th order low pass filter corrects for the sin xix attenuation
due to the 8KHz sample/hold. The filter is then followed by a 2nd order RC active post-filter with its output at VFRO.
The receive section is unity-gain, but gain can be added by using the power amplifiers. Upon the occurrence of
FS R, the data at the DR input is clocked in on the falling edge of the next eight BClKR (BClKx) periods. At the·
end of the decoder time slot, the decoding cycle begins, and 10jLs later the decoder DAC output is updated. The
total decoder delay is 210jLs (decoder update) plus 110jLs (filter delay) plus 62.5jLs· (1/2 frame), which gives approxi-
mately.180jLs.

RECEIVE POWER AMPLIFIERS

Two inverting mode power amplifiers are provided for directly driving a matched line interface transformer. The
gain of the first power amplifier call be adjusted to boost the ± 2.5V peak output signal from the receive filter
upto ±3.3V peak into an unbalanced 3000. load, or ±4.0V into an unbalanced 15KO load. The second power
amplifier is internally connected in unity-gain inverting mode to give 6dB of signal gain for balanced loads.
Maximum power transfer to a 6000 subscriber line termination is obtained by differently driving a balanced trans-
former with a ~:1 turns ratiO, as shown in Fig. 2. A total peak power of 15.6dBm can be delivered to the loac;i
plus termination. Both power amplifiers can be powered down independently from the PDN input by connecting
the ,{PI input to VBB , saving approximately 12mW of power. .

ENCODING FORMAT AT Ox OUTPUT

V,N ", + Full- Scale 10000000
11111111
V,N=OV.
01111111
Y'N = - Full- Scale 00000000

c8 SAMSU~G SEMICONDUCTOR 221

KT3064J CMOS INTEGRATED CIRCUIT

TRANSMISSION CHARACTERISTICS
(Unless otherwise specified: Ta=O·C to 70·C, Vcc=5V±5%, V~e= -5V±5%, GNDA'=OV, f= 1.02KHz,
VIN = OdBmO transmit input amplifier connected for unity-gain non,inverting.)

Characteristic Symbol Test Condition Min Typ Max Unit

Amplitude Response
Nominal OdBmO level is 4dBm (6000) 1.2276 Vrms
Absolute Levels OdBmO
Max transmit overload level
Max-Transmit Overload Level tMAX
(3.17dBmO) 2.501 VPK
Ta=25·C, Vcc =5V, Vee,= -5V
Transmit Gain, Absolute GXA -0.15 0.15 dB
Input at GSx=OdBmO at 1020Hz
f=16Hz -40 dB
f=50Hz -30 dB
f=60Hz -26 dB
f=200Hz -1.8 -0.1 dB
f = 300Hz - 3000Hz -0.15 0.15 dB
Transmit Gain, Relative to GXA GXR
f=3300Hz -0.35 0.05 dB
f=3400Hz -0.7 0 dB
f=4000Hz -14 dB
f = 4600Hz and up, measure -32 dB
Response from OHz to 4000Hz
Absolute Transmit Gain Variation
GXAT Ta=O·C to 70·C ±0.1 dB
with Temperature
Absolute Transmit ,Gain Variation
GXAV Vcc=5V±5%, Vee= -5V±5% ±0.05 dB
with Supply Voltage
Sinusoidal test method
Reference level = -10dBmO
Transmit Gain Variations with
GXRL VFxl + = - 40dBmO to + 3dBmO -0.2 0.2 dB
Level
VFxl + = - 5OdBmO to - 40 dBmO -0.4 0.4 dB
, VFxl + = - 55dBmO to - 5OdBmO -1.2 1.2 dB
Ta=25·C, Vcc =5V, Vee = -5V
Receive Gain, Absolute GRA Input = Digital code sequence for -0.15 0.15 dB
OdBmO signal at 1020Hz
f = OHz to 3000Hz -0.15 0.15 dB
,f=3300Hz -0.35 0.05 dB
Receive Gain, Relative to GRA GRR
f=3400Hz -0.7 0 dB
f=4000Hz -14 dB
Absolute Receive Gain Variation
GRAT Ta=O·C to 70·C ±0.1 dB
with Temperature
Absolute Receive Gain Variation
GRAV Vcc =5V±5%, Vee = -5V±5% ±0.05 dB
with Supply Voltage
Sinusoidal test method; reference
input PCM code 'corresponds to an
Receive Gain Variations with ideally encoded-10dBmO signal
GRRL
Level PCM level = - 4OdBmO to + 3 dBmO -0.2 0.2 dB
PCM level = - 50dBmO to - 40dBmO -0.4 0.4 dB
PCM level = - 55dBmO to - 50d~mO -1.2 1.2 dB
Receive Filter Output at VFRO VRO RL= 10KO -2.5 2.5 V

c8 SAMSUNG ,SEMICONDUCTOR 222

KT3064J . CMOS INTEGRATED CIRCUIT

TRANSMISSION CHARACTERISTICS (Continued)

Characteristic Symbol Test Condition Min Typ Max Unit

Envelope Delay Distortion with Frequency

Transmit Delay, Absolute DXA 1= 1600Hz 290 315 /LS
I = 500Hz - 600Hz 195 220 /Ls
I = 600Hz - 800Hz 120 145 /LS
I = 800Hz - 1000Hz 50 75 /Ls
Transmit Delay, Relative to DXA DXR I = 1000Hz - 1600Hz 20 40 /Ls
I = 1600Hz - 2600Hz 55 75 P.s
I = 2600Hz - 2800Hz 80 105 /Ls
I = 2800Hz - 3000Hz 130 155 /Ls
Receive Delay, Absolute ORA 1= 1600Hz 180 200 P.s
I = 500Hz - 1000Hz -40 -25 P.s
I = 1000Hz -1600Hz -30 -20 /Ls
Receive Delay, Relative to ORA ORR I = 1600Hz - 2600Hz 70 90 /Ls
I = 2600Hz - 2800Hz 100 125 /LS
I = 2800Hz - 3000Hz 145 175 /Ls
Noise
Transmit Noise, C Message
Nxc VFxl + =OV 12 15 d8rneO
Weighted
Receive Noise, C Message PCM code equals alternating
NRC 8 11 dBrnC;O
Weighted positive and negative zero
I = OKHz to 100KHz, loop around
Noise, Single Frequency NRS
measurement, VFxl + = OVrms
-53 dBmO

VFxl + = OVrms,
Positive Power Supply Rejection,
PPSRx Vee = 5.0Voc + 100mVrms 40 dBC
Transmit
I = OKHz - 50KHz
VFxl + = OVrms;
Negative Power Supply Rejection,
NPSRx Vss = - 5.0Voc + 100mVrms 40 dBC
Transmit
1= OKHz - 50KHz
flCM code equals positive zero
Vcc = 5.0Voc + 100mVrms
Positive Power Supply Rejection,
PPSRR I = OHz - 4000Hz 40 dBC
Receive
I = 4KHz - 25KHz 40 dB
I = 25KHz - 50KHz 36 dB
PCM code equals positive zero
Vss= -5.0Voc +100mVrms
Negative Power Supply Rejection,
NPSR A I = OHz - 4000Hz 40 dBC
Receive
I = 4KHz - 25KHz 40 dB
I = 25KHz - 50KHz 36 dB

c8 SAMSUNG SEMICO~DUcrOR 223

KT3064J CMOS INTEGRATED CIRCUIT

TRANSMISSION CHARACTERISTICS (Continued)

Characteristic Symbol Test Condition Min Typ Max Unit

Loop around measurement, OdBmO,

300Hz - 3400Hz input applied to
VFxl +, measure individual image
Spurious Out-of-Band Signals
SOS signals at VFRO
at the.channel Output
4600Hz - 7600Hz -32 dB
7600Hz - 8400Hz -40 dB
8400Hz-100,00OHz -32 dB
Distortion
Signal to Total Distortion STDx Sinusoidal test method
Level = 3.OdBmO 33 dBC
= OdBmO to 13OdBmO 36 dBC
Transmit or Receive = - 40dBmO XMT 29 dBC
STDR
Hall-Channel RCV 30 dBC
= .,.. 55dBmO XMT 14 dBC
RCV 15 dBC
Single Frequency Distortion,
SFDx -46 dB
Transmit
Single Frequency Distortion,
SFDR -46 dB
Receive
Loop around measurement,
VFx + = -4dlilmO to -21dBmO, two
Intermodulation Distortion IMD -41 dB
Irequencies in the range
300Hz - 3400Hz
Crosstalk
I = 300Hz - 3400Hz
Transmit to Receive Crosstalk CTx.R
DR = Steady PCM code
-90 -75 dB

Receive to Transmit Crosstalk CTR•x I = 300Hz - 3000Hz, VFxl = OV

-90 -70
dB
(Note 1)
Power Amplifiers
Balanced load, RL connected
Maximum OdBmO Level lor
Better than ± 0.1 dB Linearity
+
between VPO and VPo-
VOL RL = 6000 3.3 Vrms
Over the Range -1OdBmO to
RL =12000 3.5 Vrms
+3dBmO
RL=3OKO· 4.0 Vrms
Signal/Distortion SlOp RL:; 6000, OdBmO 50 dB

Note 1. CTR.X is measured with a - 4OdBmO activating siqnal applied at VFxl + .

c8 SAMSUNG SEMICONDUCTOR 224

KT3064J CMOS INTEGRATED CIRCUIT

APPLICATION INFORMATION
POWER SUPPLY
While the pins of the KT3064 are well protected against electrical misuse, it is recommended that the standard
CMOS practice be followed, ensuring that ground is connected to the device before any other connections are
made. In applications where the printed circuit board may be plugged into a "hot" socket with power and clocks
already present, an extra long ground pin in the connector should be used.
All ground connections to each device should meet at a common point as close as possible to the GNDA pin. This
minimizes the interaction of ground return currents flowing through a common bus impedance. 0.1!,F supply
decoupling capacitors should be connected from this common ground point to Vee and VBB• For best performance,

II
the ground point of each CODEC/FILTER on a card should be connected to a common card ground in start formation,
rather tha via a ground bus. This common ground point should be decoupled to Vee and VBS with 10!,F capacitors.

APPLICATION CIRCUIT

R2 R1

300

VBS
0.1
600 GNDA KT3064
0.1

+5V Vee

VPI

300 R3 R4

Note 1: Transmit gain =20 x IOg(R1R~ R2),(R1 + R2)~ 10KO

Note 2: Receive gain = 20 x log(2 ~:\R4~ 10KO

c8 SAMSUNG SEMICONDUCTOR . 225

KT5116J , CMOS INTEGRATED CIRCUIT

,wLAW COMPANDING CODEC

16 CERDIP
The KT5116 is a monolithic CMOS companding CODEC which
contains two parts: (1) an 'analog-to-digital converter (2) a digital to-analog
converter which have transfer characteristics conforming to the wLaw
companding code.
These two parts form a coder-decoder function designed to meet the
needs of the telecommunications industry for per-channel voice-
frequency codes used in telephone digital switching and transmission
systems.
Digital input and output are in serial format using sign-plus-amplitude
coding. '
A sync pulse input is provided for reception of multichannel information
being multiplexed and synchronizing transmission over a single
transmission line.
Practical transmission and reception of 8bit data words which contain
the analog information is done from 64Kb/s to 2.1Mb/s rate with analog
signal sampling occuring at an 8KHz rate.

FEATURES
• The simple % 5V power supply operation
• Typically 30mW low power dissipation
• Follows the w255 companding law
• Synchronous ancl asynchronous operation
• On-chip offset null circuit eliminates long term drift, drift error
and need for trimming
• Minimum' extemal circuitry required
• Serial data output 64Kb/s to 2.1Mb/s at 8KHz sampllng'nite
• Separate analog and digital grounding pins reduce system noise
problems
• On·chlp sample and hold.

BLOCK DIAGRAM
RECEIVE (DECODE)

1--------{12
DIGITAL
INPUT

DIGITAL
OUTPUT

TRANSMIT ,TRANSMIT MASTER RECEIVE

CLOCK SYNC CLOCK SYNC

c8 SAMSUNG SEMICONDUCTOR 226

KT5116J CMOS INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristics Symbol Value Unit

DC Power Supply v+ (V-) +S(-S) V

Ambient Operating Temperature T. o to 70 ·C
Storage Temperature T. -55 to 125 ·C
Package Dissipation at 25·C Po 500 mW
Digital Input Voltage VOl -0.5 to S V
Analog Input Voltage VAl -S to S V
Positive Reference Voltage Vref+ -0.5 to S V
Negative Reference Voltage Vref- -S to 0.5 V

DIGITAL OUTPUT CODE wLAW

No Chord Code Chord Value Step Value

1 000 O.OmV 0.S13mV

2 001 10.11mV 1.22SmV
3 010 3O.3mV 2.45mV
4 o1 1 70.8mV 4.90mV
5 100 151.7mV 9.81mV
·S 10 1 313mV 19.51mV
7 110 S37mV 39.2mV
8 111 1284mV 78.4mV

EXAMPLE;
1. Q..1.j 0010 = +70.8mV+ (2x4.90mV)
sign bit chord step bit = 8O.SmV
If the sign ·bit were a zero, then both pulse signs would be changed to minlis signs

PIN CONFIGURATION
ANALOG INPUT 1

ANALOG GROUND

ANALOG OUTPUT
KT5116J
MASTER CLOCK I 5 DIGITAL INPUT

XMIT SYNC 6 11 DIGITAL GROUND

XMIT CLOCK 7 RCV CLOCK

DIGITAL OUTPUT 8

c8SAMSUNG SEMICONDUCTOR 227

KT5116J CMOS INTEGRATED CIRCUIT

DC CHARACTERISTICS
(Condition; V+ =5V, V- = -5V, V"I+.=2.5V, Vrel_ = -2.5V)

Parameter Symbol Min Typ Max Unit

Analog Input Resistance

During Sampling
RINAS 2 KO
Analog Input Resistance
Non-Sampling
RINANS 100 MO
Analog Input Capacitance CINA 150 250 pF
Analog Input Offset Voltage VofflNA ±1 ±8 mV
Analog Output Resistance RouTA 20 50 0
Analog Output Current louliA 0.25 0.5 mA
Analog Output Offset Voltage VOfflO ±20 ±850 mV
Logic Input Low Current (VIN = 0.8V)
IlL ±0.1 ±10 /LA
Digital Input, Clock Input, SYNC Input
Logic Input High Current (VIN = 2.4V) IIH -0.25 -0.8 mA
Digital Output Capacitance COlO 8 12 pF
Digital Output Leakage Current ICOL ±0.1 ±10 /LA
Digital Output Low Voltage VOL 0.4 V
Digital Output High Voltage VOH 3.9 V
Positive Supply"Current 1+ 4 10 mA
Negative Supply Current 1- 2 6 mA
·Positive Reference Current I rei + 4 20 p.A
Negative Reference Current 1..1- 4 20 /LA

c8 SAMSUNG SEMICONDUCTOR. 228

KT5116J CMOS INTEGRATI;D CIRCUIT

AC CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

Master Clock Frequency fm 1.5 1.544 2.1 MHz

RCV, XMIT Clock Frequency fro fx 0.064 1.544 2.1 MHz
Clock Pulse Width (MASTER, XMIT, RCV) PWCLK 200 ns
Clock Rise, Fall Time 25% of
tre, ttc ns
(MASTER, XMIT, RCV) PWCLK

I
25% of
SYNC Rise, Fall Time (XMIT, RCV) t rs, tts ns
PWCLK

8
SYNC Pulse Width (XMiT, RCV) p's
fx(fr)

Data Input Rise, Fall Time

25% of
tOtR, tOIF ns
PWCLK

SYNC Pulse Period (XMIT, RCV) tps 125 p's

50% of
XMIT Clock·to·XMIT SYNC Delay t xcs ns
ttc (t",)
XMIT Clock-to·XMIT SYNC
txcsn 200 ns
(Negative Edge) Delay
XMIT SYNC Set-Up Time tx.. 200 ns
XMIT Data Delay tXdd 0 200 ns
XMIT Data Present txdp 0 200 ns
XMIT Data Three State txd• 150 ns
Digital Output Fall Time tdot 50 100 ns
Digital Output Rise Time tdor 50 100 ns
50%
RCV SYNC-to-RCV Clock Delay tsre ns
tre (tt.)
RCV Data Set-Up Time t",s 50 ns
RCV Data Hold Time t"'h 200 ns
RCV Clock-to-RCV SYNC Delay tres 200 n5
RCV &"YNC Set-Up Time trss 200 ns
RCV SYNC-to-Analog Output Delay tsse 7 p's
Analog Output Positive Slew Rate Slew + 1 V/p.s
Analog Output Negative Slew Rate Slew- 1 V/p.s
Analog Output Drop Rate Droop 25 p.V/p.s

c8 SAMSUNG SEMICONDUCTOR 229

 KT5116J CMOS INTEGRATED CIRCUIT

POWER SUPPLY REQUIREMENTS

Parameter . Symbol Min Typ Max Unit

Positive Supply Voltage V+ 4.75 5.0 5.25 V

Negative Supply Voltage V- -5:25 -5.0 -4.75 V
Positive Reference Voltage v,tt 2.375 2.5 2.625 V
N~ative Reference Voltage V;j -2.625 -2.5 -2.375 V

SYSTEM CHARACTERISTICS
Parameter Test Condition Symbol Min Typ Max Unit

Signal·to-Distortion Analog Input: 0 - - 30dBmo SID 35 39 . dB

Analog Input: -40dBmo .29 34 dB
Analog Input: - 45dBmo 24 29 dB
Gain Tracking Analog Input: + 3 - - 37dBmo GT ±0.1 ±0.4 dB
Analog Input: - 37 - - 50dBmo ±0.1 ±0.8 dB
Analog Input: - 50 - - 55dBmo . ±0.2 ±2.5 dB
Idle Channel Noise Analog Input = OV N1c 10 18 dBrnCD
Transmission Level Point 6000 TLP +4 dB

'. c8 SAMSUNG SEMICONDUCTOR' 230

KT5116J CMOS INTEGRATED CIRCUIT

PIN DESCRIPTION
1. Analog Input (Pin 1)
At this pin, employs voice-frequency analog signals which are bandwidth-limited to 4KHz. Then, they are sampled
at an 8KHz rate. The Analog Input must remain between Vref (+) and V,of (-) for accurate conversion.

2. Positive Supply Voltage and Negative Supply Voltage (Pin 2, 3)

Pin 2, 3 is a pin which employs supply voltage. Typically, the voltages of these pins are ±5V.

3. NC (Pin 4)
This pin is a pin of non-connection.

4. Master Clock (Pin 5)

This signal provides the basic timing and control signals required for all internal conversions. It is not necessary
for synchronizing with RCV SYNC, RCV Clock, XMIT SYNC or XMIT Clock. It is not internally related to them.

5. XMIT SYNC (Pin 6)

This input is synchronized with XMIT Clock. If XMIT SYNC goes High, the Digital Output is activated and the AID
conversion begins on the next positive edge of Master Clock. Otherwise, if XMIT SYNC goes Low, the Digital Out-
put become 3 state. XMIT SYNC must go Low for at least 1 Master Clock prior to the transmission of the next
digital word.

6. XMIT Clock (Pin n

The on·chip 8-bit output shift register of the KT5116 is unloaded at the clock rate present on this pin. Clock rates
of 64KHz to 2.1 MHz can be used for XMIT Clock. When the positive edge of XMIT SYNC occurs after the positive
edge of XMIT Clock, XMIT SYNC will detemline when the first positive edge of the internal clock will occur. In
this event, the hold time
, .
for the
/"
first-clock pulse is measured from the positive edge of XMIT SYNC.

7. Digital Output (Pin 8)

The Digital Outp,ut is composed of a sign bit, 3 chord bits and 4 step bits. The sign bit indicates the polarity of
the Analog Input while the chord and step bits indicate the magnitude. The KT5116 output register stores the 8 '
bit encoded sample of the Analog Input. The 8 bit-word is shifted out under control of XMIT SYNC and XMIT CLOCK.
If XMIT SYNC is Low, the Digital Output is an open circuit, otherwise when XMIT SYNC is High, the state of the
Digital Output is determined by the value of the output bit in the serial shift register.

8. RCV SYNC (Pin 9): Refer to Figure 3

This input is synchronized with RCV CLOCK, and serial data is clocked in by RCV CLOCK. Duration of the RCV
pulse is approximately eight RCV Clock periods. The conversion from digital to analog starts after the negative
edge of RCV SYNC pulse (see Fig. 6). The negative edge of RCV SYNC should occur before the 9th positive clock
edge to insure that only eight bits are clocked in. RCV SYNC must stay low for 17 Master Clocks (niinimum) before
the digital word is to be received (see Fig. 11).

9. RCV Clock (Pin 10): Refer to Figure 3

Valid data should be applied to the digital input before the positive edge of the internal clock. (refer to Fig. 3) This
SYNC pulse is approximately eight RCV CLOCK periods. The conversion from digital to analog starts after the negative
the internal clock transfers the 'data to the slave of the master-slave flip-flop. A hold time, trdh, is required to com-
plete this transfer. If the rising edge of RCV SYNC occurs after the first rising edge of RCV occurs after the first
rising edge of RCV CLOCK, RCV SYNC will determine when the first positive edge of internal clock will occur. In
this event, the set-up and hold times for the first clock pulse should be measured from the positive edge of RCV SYNC.

c8 SAMSUNG SEMICONDUCTOR 231

KT5116J CMOS INTEGRATED CIRCUIT

10. Digital Ground (Pin 11)

11. Digital Input, (Pin 12)'
The KT5116 Input register accepts the B-bit sample of an analog value and loads it uhder control of,RCV SYNC
and RCV CLOCK (refer to Figure 3), When RCV SYNC goes High, the KT5116 uses RCV CLOCK to clock to clock
the serial data into its input register RCV SYNC goes Low to indicate the end of serial input data The eight bits
of the input data have the same functions described for the Digital Output.

12. Analog Output (Pin 13)

The Analog Output is in the form of voltage steps (100% duty cycle) having amplitude equal to the analog samp.le
which was encoded. This w8lle form is then filtered with an external low-pass filter with sin XIX correction to recreate
the sample voice ~ignal. '

13. Analog Ground (Pin 14)

14. Positive and Negative Reference Voltages, (Pin 15, 16) Vrel (-), Vrel (+)
These inputs provide the conversion reference for the digital-to-analog converter in the KT5116. V,., (+) and Vref (-)
must maintain 100ppm/·C regulation over the operating temperature. Variation of the reference directly affects
system again.

RECOMMENDED ANALOG INPUT CIRCUIT

I COOEC
I
I
I
I

""n
I
I TYPICAL

I
I
I

Fig. 1

c8 SAMSUNG SEMICONDUCTOR 232

KT5116J CMOS INTEGRATED CIRCUIT

TRANSMITTER SECTION TIMING

~-------------------------twsx------------------~--~~
2.4V
1.4V
Ir-----------------------------Il
XMIT SYNC O.4V

-~Il-- IRS IFS

I
V
PCM DATA PRESENT

. Fig. 2

RECEIVER SECTION TIMING

~------------------------tWSR------------------------~

2.4V
1.4V
1,...--------------------------.. .1
RCV SYNC V
-~H--tRS

tSRc
tRSS

tRC

DIGITAL INPUT

{#!lIff!!!!/~
tj
IOIR
DAT

----~------------------------------~\.
ANALOG OUTPUT
tSAO
r
Fig. 3
Note: All rise and fail times are measured from O.4V and 2.4V. All delay times are measured from 1.4V:

c8 SAMSUNG SEMICONDUCTOR 233

KT5116J CMOS INTEGRATED CIRCUIT
SID RATIO VS INPUT LEVEL GAIN TRACKING PERFORMANCE

80

70
JJ I

Ii 80
:!!
Ii +1
~.
+0.5
:!!
50
4~ 40 ..:;....
CO I r
~
~
40 -0.1 -0.1 -0.1 0..1 _
40 39~5116
~ ~~5
~4
-0.05
<>
g :k I-
30 z
:c -1 -,
z~
~ANNEL ~"23
-0.5.1
Il!
co 20 r- f-
JANK
SPECIFICATIONS _ _ 22~5-
" 03
-2 _~HANNEL BANK
SPECIFICATIONS

10 I I -3 I I -3
I
-4
+30 -10 -20 -30 -40 -50 -60 +10 -w -20 -30 -40 -50 -80 -70
INPUT LEVEL - dBmO INPUT LEVEL - dBmO
FIg. • Fig. 5

AID, D/A CONVERSION TIMING

f--------------~125~oec---------------i

SAMPLE AND HOLD

SAMPLE TIME
::: 32 MASTER CLOCKS·

ENABLE SAR
SAR REQUIRES
::: 128 MASTER CLOCKS

_____--J/ RCV SYNC

________________ ~ __________ \~<------------------------J;lANALOGOUTPUTUPDATED

Fig. 6
DATA INPUT/OUTPUT TIMING
1-_2OO_n_O_-I REQUIRED FOR DATA TO TRANSFER
FROM MASTER TO SLAVE KT5116
XMIT
INTERNAL
CLOCK DIGITAL
OUT

XMIT SYNC
)(VALID DATA
XMIT CLOCK
------------------' REQUIRED TO TRANSFER DATA
FROM MASTER TO SLAVE
DIGITAL
200n
RCV IN
INTERNAL
CLOCK RCV SYNC

SOns REQUIRED TO LOAD MASTER

RCV CLOCK

VALID INCOMING DATA

. Fig. 7

c8 SAMSUNG SEMICONDUCTOR 234

KT5116J CMOS INTEGRATED CIRCUIT

KT5116 AID CONVERTER (p.·Law Encoder) TRANSFER CHARACTERISTIC

11111111
11110000 -"".....
..-
11100000 l/
1101 0000 /
11000000
I
10110000

10100000

~ 10010000
5
0--

~
Ci
13
1000oooo}
--' 0000 0000
00010000
00100000

0011 0000
II
0100 0000

01010000
j
01100000
./
, V-
01110000
01111111
- ~
~

- VREF
2
Fig. 8 ANALOG INPUT (VOLTS)
0 + VREF
-2-
+VREF

0111 0000 -
D/A CONVERTER (p.·Law Decoder) TRANSFER CHARACTERISTIC
01111111
.........
.......
01100000

01010000

0100 0000
~

,
\.

0011 0000

00100000
00010000

10010000

10100000
1011 0000

1100 0000

1101 0000
11100000
,
\
r"
11110000
~ i"--
11111111
- VREF 0 + VREF
-VREF -2- 2 +VREF

Fig. 9 ANALOG OUTPUT (VOLTS)

c8 SAMSUNG SEMICONDUCTOR 235

KT5116J CMOS INTEGRATED CIRCUIT

64KHz OPERATION, TRANSMITTER SECTION TIMING

1---------------125~.~c ----:-----------1

XMITSYNC
1 MASTER
CLOCK
PERIOD
(MIN)

Fig. 10 PCM DATA PRESENT

Note: All rise and fail iimes are measured from O.4V and 2.4V. All delay times are measured from 1.4V.
64KHz OPERATION, RECEIVER SECTION TIMING
125~.ec------------~--1

. 17 MASTER

-1 .
CLOCK'
PERIODS
(MIN)

tRDS

~ALI fiR,,f;J/ilFlIQ!ifilil.Q/'ifll'.QfiIi!0r,:JlFfl\CJrlli!iJ,QfilW.CJrl
.fi::1:1t:j~ff11:i E7v:t1i~v:t:IJ EJVJ.'t:J ~tJ':ff:J ~tN:Je3~ ~\f11:J~ \
Fig. 11
Note: All. rise and fall times are measured from O.4V and 2.4V. All delay times are measured from 1.4V.

PCM SYSTEM BLOCK DIAGRAM

KT5116

GAIN ADJUST'
BAND 8
PASS TRANSMITIER .
FILTER' DIGITAL . DIGITAL
(AID) MUX TRUNK
FROM {
OTHER
CHANNELS.

---~----
2 WIRE CABLE I
I
I
RECEIVER
I 13
(DIA)
12
I LOW
I PASS DIGITAL
DEMUX DIGITAL
I FILTER TRUNK
I TO
OTHER {
I CHANNELS
LL~~~~~~~~ __ _

c8 SAMSUNG SEMICONDUCTOR 236 .

KT5116J CMOS INTEGRATED CIRCUIT

SYSTEM CHARACTERISTICS TEST CONFIGURATION

r-----------, IDEAL DECODER

I I
I I
I 1.004KHz I
I SIGNAL I----ilf---{
I SOURCE I
I I SYSTEM ENCODER ONLY
I I

II
I I
I
J IL _ _ _ _ _ _ _ _ _ _ _ .,
J I
I J
I 1.004KHz I
I NOUT NOTCH FILTER
I HP3551A FILTER
I .
L ______________ ~ _______ I ~

SOUT+NoUT
Fig. 12
Note: The ideal decoder consists of a digital decomponder and a 13·bit precision DAC.

PERFORMANCE EVALUATION
The equipment connections shOwn in Figure 12 can be used to evaluate tlie performance of the KT5116.
An analog signal provided by the HP3551 a transmission test set is connected to the Analog Input (Pin 1) of the
KT5116. The Digital Output of the CODeC is tied back to the Digital Input and the Analog Output is fed through
a lOW-pass filter to the HP3551A.
Remaining pins of the KT5116 are connected as follows:
1. RCV SYNC is tied to XMIT SYNC.
2. XMIT CLOCK is tied to Master CLOCK. The signal is inverted and tied to RCV clock.
The following timing signals are required:
1. Master CLOCK=2.048MHz
2. XMIT SYNC repetition rate=8KHz
3. XMIT SYNC width=8 XMIT CLOCK periods.
when all the above requirements are met, the set-up of Figure 12 permits the measurement of synchronous system
performance over a wide range of Analog Inputs.
The data register and ideal decoder provide a means of checking the encoder portion of the KT5116 independently
of .the decoder section. To test the system in the asynchronous mode, Master CLOCK should be separated from
RCV CLOCK. XMIT CLOCK and RCV CLOCK are separated also separated.

c8 SAMSUNG S.EMICONDUCTOR 237

KT5116J CMOS INTEGRATED CIRCUIT

ANALOG INPUT ANALOG OUTPUT POWER

AMP
DEMO SET CIRCUIT DIAGRAM R3
2.048MHz
r----IO~~
R6

10MD

'NON
·POLARIZED
2.048MHz

128KHz

5V

2KII±1'10

• Power Supply Ripple Rejection

C7 C6 C5 C4
+5V 0---1I--I--I~-Ic.-lI-.05-~-F-x-4-l'" .05~F
C3
GNDDo--~-~-~--4

GNDAo---------4----~--,
C2 .05~F

-5Vo--------~-----

NOTE: All unused input connected to GNDD or Vee, only in HeT series.

c8 SAMSUNG SEMICONDUCTOR 238

LM567C LINEAR INTEGRATED aRCUIT

TONE DECODER
8 DIP
The LM567C is a monolithic phase locked loop system designed to pr0-
vide a saturated transistor switch to GND. when an input signal is present
within the passband. External components are used to independently
set center frequency bandwidth and output delay.

FEATURES
• Wide frequency range (O.01Hz - 500kHz).
• Bandwidth adJustabl, from 0 to 14% 8 SOP
• logic compatible output wHh 100mA current sinking capability.

II
• Inherant Immunity to fal.. 81gna18.
• High rejection of out..of.band slgnal8 and nolae.
• Frequency range adjustable over 20:1 range by an external
re8lstor.

APPLICATIONS
• Touch Tone Decoder
• Wireless Intercom.
• Communications paging deco,ders
• Frequency monitoring and control. ORDERING INFORMATION
• Ultrasonic controls (remote TV etc.)
• Carrier current remote controls. Device Package Operating Temperature
• Precision oscillator. LM567CN 8 DIP
0- +70·C
LM567CD 8 SOP
SCHEMATIC DIAGRAM

c8 SAMSUNG SEMICONDUCI'OR 239

LM567C LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Ta 25°C) =

Characteristic Symbol 'J value Unit

Operating Voltage Vcc 10 V

Input Voltage V1N -10 -Vee +0.5 V
Output Voltage Vo 15 V
IPower Dissipatlon Pd 300 mW
Operating Temperature Topr 0-+70 "C
Storage Temperature Tstg -65-+150 °C

ELECTRICAL CHARACTERISTICS
Nee =5JJV. T... 25°C unless other wise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

Operating Voltage Range Vcc .4.75 5.0 9.0 V

Supply Current Quiescent Icc-1 7 10 . mA
RL=20K
Supply Current Activated Icc-2 12 15 mA
Quiescent Power Dissipation POD 35 mW
Highest Center Frequency HFO RL=20K 100 500 KHz
Center Frequency Stability Fse OOC to 700C 35±60 ppmfOC
Center Frequency Shift Fcs 0.7 2 %N
With Supply Voltage
Largest Detection Bandwidth B.W 10 14 18 %offo
Largest Detection B.W Skew B.Ws 2 3 OAl of fo
Largest Detection Bandwidth . B.Wv ±1 ±5 oAlN
4.75-6.75V
Variation With Supply Voltage
Largest Detection Bandwidth B.Wt ±0..1 %fOC
Variation With Temperature
Input Resistance RIN 20 Kohm
Smallest Detectable V1N-1 IL =100mA. fi=fo 20 25 mVrms
Input Voltage
Largest No Output V1N-2 10 15 mVrms
Input Voltage
Greatest Simultaneous S1/Sd RL=20k +6 dB
Outband Signal To Inband V IN =300mVRMS
Signal Ratio fi=fo=100KHz
Minimum InPllt Signal to S2/Sd fi 1 =140KHz -6 dB
Wideband Noise Ratio . fi 2 =60KHz
Fastest On-Off Cycling Rate .. FoUT RL=20K f0/20
Output Leakage Current leo V1N =25mVRMS 0.01 25 pA
VSIQ'"1 IL =30mA. V1N =25mVrms 0.2 0.4 V
Output Saturaton Voltage
VSIQ'"2 It =100mA. V1N =25mVrms 0.6 1.0 V
Output Fall Time TF RL=50 30 nS
Output Rise Time TR RL=50 150 nS

c8 SAMSUNG SEMICONDUCTOR 240

LM567C LINEAR .INTEGRATED CIRCUIT

CIRCUIT DESCRIPTION BLOCK DIAGRAM

The LM567C monolithic tone decoder consists of a phase detector, low
pass filter, and current controlled oscillator which comprise the basic Output 1
phase-locked loop, plus an additional low pass filter and quadrature Filter
detector enabling detection on in-band signals. The device has a
low Pass
normally high open collector output capable of sinking 100 mAo Loop Fitte, 2
The input signal is applied to Pin 3 (20 kO nominal input reSistance). Free
running frequency is controlled by an RC network at Pins 5 and 6 and
can typically reach 500 kHz. A capacitor on Pin 1 serves as the output
filter and eliminates out-of-band triggering. PLL filtering is accomplished
with 'a capacitor on Pin 2; bandwidth and skew are also dependant upon
the circuitry here. Bandwidth is adjustable from 0% to 14% of the center
frequency. Pin 41s +Vcc (4.75 to 9V nominal, 10V maximum); Pin 7 is
ground; and Pin 8 is open collector output, pulling loW when an in-band
signal triggers the device.
Fig. 1
I
DEFINITION OF LM567C PARAMETERS
CENTER FREQUENCY fo
fo is the free-running frequency of the C L controlled oscillator with no input signal. It is determined by resistor R, between
pins 5 and 6, and capacitor C, from pin 6 to ground fo can be approximated by

fo=_1_
R,C,
where R, is in ohms and C, is in farads.

LARGEST DETECTION BANDWIDTH

The largest detection bandwidth is the largest frequency range within Which an input signal above the threshold volt-
age will cause a logical zero state at the output. The maximum detection bandwidth corresponds to the lock range of the PLL.

DETECTION BANDWIDTH (BW)

The detection bandwidth is the frequency range centered about fo, within which an input signal larger than the threshold
voltag/il (typically 20mVrms) will cause a logic zero state at the output. The detection bandwidth corresponds to the 'capture
range of the PLL and is determined by the low-pass bandwidth filter. The bandwidth of the filter, as a percent of fo, can
be determined by the approximation

where V; is the input signal in volts, rms, and C~ is the capaCitance at pin 2 in I'F.

DETECTION BAND SKEW

The detection band skew is a measure of how accurately the largest detection band is centered about the center frequency,
fo. It is defined as (fmax +fm;n -2fo)lIo, where fmax and Im;n are the frequencies corresponding to the edges of the detection
band. If necessary, the detection band skew can be reduced to zero by an optional centering adjustment.

241
c8SAMSUNG SEMICONDUCTOR
LMS67C LINEAR INTEGRATED CIRCUIT

PIN DESCRIPTION
OUTPUT FILTER - C3 (Pin 1)
Capacitor C3 connected from pin 1 to ground forms a simple low-pass post detection filter to eliminate spurious outputs
due to out-of-band signals. The time constant of the filter can be expressed as T3 =R3C3, where R3 (4.7kG) is the internal
impedance at pin 1.
The precise value of G3 is not entical for most applications. To eliminate the possibility of false triggering by spurious
signals, it is recommended that C3 be 2: 2 C2, where C2 is the loop filter capacitance at pin 2.
If the value of C3 becomes too large, the turn-on qr turn-off time of the output stage will be delayed until the voltage
change across C3 reaches the threshold voltage. In certain applications, the delay may be desirable as a means of
suppressing spurious outputs. Conversely, if the value of C3 is too small, the beat rate at the output of the quadrature detec-
tor may cause a false logic level change at the output. (Pin 8) .
The average voltage (during lock) at pin 1 is a function of the inband input amplitude in accordance with the given transfer
characteristic.

LOOP FILTER - C2 (Pin 2)

Capacitor C2 connected from pin 2 to ground serves as a single pole, low-pass filter for the PLL portion of the LM567C
The filter time constant is given by T2 =R2C2, where R2 (10 kG) is the impedance at pin 2. .
The selection of C2 is determined by the detection bandwidth requirements. For additional information see section on
"Definition of LM567C Parameters".
The voltage at pin 2, the phase detector output, is a linear function of frequency over the range of 0.95 to 1.05 fa, with
a slope of approximately 20 mVl% frequency deviation.

INPUT (Pin 3)
The input signal is applied to pin 3 through a coupling capacitor. This terminal is internally biased at a dc level 2 volts
above ground, and has an input impedance level of approximately 20 kG

TIMING RESISTOR Rl AND CAPACITOR C1 (Pins 5 and 6)

. The center frequency of the decoder is set by resistor R, between pins 5 and 6, and capacitor C, from 'pin 6 to ground,
as shown in Figure 3.
.pin 5 is the oscillator squarewave output which has a magnitude of approximately Vee - 1.4V and an average dc level
of Vee/2. A 1 kG load may be driven from this point. The voltage at pin 6 is an exponential triangle waveform with a peak-
to-peak amplitude of 1 volt and an average dc level of Vecl2. Only high impedance loads should be connected to pin 6
avoid disturbi.ng the temperature stability or duty cycle of the oscillator. .

LOGIC OUTPUT (Pin 8)

Terminal 8 provides a binary logic output when an input signal is present within the pass-band of the decodef. The logic
output is an uncommitted, "base-collector" power transistor capable of switching high CJrrent loads. The current level at
the output is determined by an external load resistor, RL , connected from pin 8 to the positive supply.
When an in'band signal is present, the output transistor at pin 8 saturates with a collector voltage less than 1 volt (typically
0.6V) at full rated current of 100 mAo If large output voltage swings are needed, Rl can be connected to a supply voltage,
V+, higher than the Vee supply. For safe operation, V+ :s; 20 volts.

c8 SAMSUNG SEMICONDUCTOR 242

LM567C LINEAR INTEGRATED CIRCUIT

OPERATING INSTRUCTIONS
SELECTION OF EXTERNAL COMPONENTS
A typical connection diagram for the LM567C is shown in Figure 3. For most applications, the following procedure will
be sufficient for determination of the external components At, Ct, C2 , and C3 •
1. At and Ct should be selected for the desired center frequency by the expression fa =l/AtCt. For optimum temperature
stability, At should be selected such that 2kO, and the AtC t product should have sufficient stability over the projected
operating temperature range.
2. Low-pass capacitor, C 2 , can be determined from the Bandwidth versus Input Signal Amplitude graph of Figure 7.
One approach is to select an area of operation from the graph, and then adjust the input level and value of C2 accord-
ingly. Or, if the input amplitude variation is known, the required foC2 product can be found to give the desired bandwidth.

II
Constant bandwidth operation requires V,>200mV rms. Then, as noted on the graph, bandwidth will be controlled
solely by the foC2 product.
3. Capacitor C 3 sets the band edge of the low-pass filter which attenuates frequencies outside of the detection band and
thereby eliminales spurious outputs. If C3 is too small, frequencies adjacent to the detection band may switch the output
stage off and on at the beat frequency, or the output may pulse off and on during the turn-on transient. a typical
minimum value of C 3 is 2 C2 • .
Conversely, if C3 is too large, turn-on and turn-off of the output stage will be delayed until the voltage across C3 passes
the threshold value.

PRINCIPLE OF OPERATION
The LM567C is a frequency selective tone decoder system based on the phase-locked loop (PLL) principle. the system
is comprised of a phase-locked loop, a quadrature AM detector, a voltage comparator, and an output logic driver. The four
sections are internally interconnected as shown in Figure 1.
When an· input tone is present within the pass-band of the circuit, the PLL synchronizes or "locks" on the input signal.
The quadrature detector serves as a lock indicator: when the PLL is locked on an input signal, the dc v'oltage at the output of
the detector is shifted. This dc level shift is then converted to an output logic pulse by the amplifier and logic driver. The
logic driver is a "bare collector" transistor stage capable of switching 100 mA loads.
The logic output at pin 8 is normally in a "high" state, until a tone that is within the capture range of the decoder is present
at the input. When the decoder is locked on an input signal, the logic output at pin 8 goes to a "low" state.
The center frequency of the detector is set by the free-running frequency of the current-controlled oscillator in the PLL.
This free-running frequency, fa, is determined by the selection of At and C t connected to pins 5 and 6, as shown in
Figure 3. The detection bandwidth is determined by the size of the PLL filter capacitor, C2; and the output response speed
is controlled by the output filter capacitor, C3

c8 SAMSUNG SEMICONDUCTOR 243

LM567C LINEAR INTEGRATED CIRCUIT

TYPICAL CHARACTERISTICS (Fig. 2)

CENTER FREQ. YS TEMPERATURE TYP. BW YS T~PERATURE

14

-
12

8
.....
6_

4_ .....;

r--..
2

-is 0 25
TEIIPEIW'UIII rei
7&
- 100

BW YS CENTER FREQUENCY

.........

""
--lIII0
o
10 12 14 18 100 11( 101( 1001< 111
aw~allO)

BW (Ca. C3 CHARCt) CURRENT DRAIN VB. w::c

~
~~
~ t': I
JI

f'\ t\-
ea ~ ["-....
f'\ 1'-- 1"---
l"'- t-
2" 4 10 12 14 18

c8 SAMSUNG SEMICONDUCTOR 244

LMS67C' LINEAR INTEGRATED CIRCUIT

OUTPUT SATURATION VOLTAGE

OPERATING CYCLE VB BANDWIDTH VB AMBIENT TEMPERATURE

-t-
1000 1.0

500 ~-

"- v~.5v,L~ 1 _ -- - ' - D.8

"\A II: Bandwidth IImII8d bV c.- -
"\ B: BandWidth Ilmllod bV
external resistor /
50 " ~r'\ ~
f\.

" t\..
(MInimum Ca)
~ r--
L_100mA
V
20

10
"-
I'\.

10
"' 20 50 100
0,2
---,...
, -25 25
IL_30mA

50
---
75
/"

100
II
BANDWIDTH (1Ma 01 10) BANDWIDTH ("C)

AC TEST CIRCUIT
+5V

LM567C

Yin +5V
fi=100KHz
Note: Adjust for fo=1OOKHz

Fig. 2

c8 SAMSUNG SEMICONDUCTOR 245

 (d) Frequency Doubler

AL

6 5 3

lSL10
AL

Al =6.8K to 15K
./ R2-4.7K
A3=20K 'C2~ ~Cl

c8 SAMSUNG SEMICONDUCTOR 246

LM567L LINEAR INTEGRATED CIRCUIT

MICROPOWER TONE DECODER

8 DIP

The LM567L is a micropower phase-locked loop (PLL) circuit designed

for general purpose tone and frequency decoding. In applications re-
quiring very low power dissipation, the LM567L can replace the popu-
lar 567 type decoder with only minor component valu~ changes. The
LM567L offers approximately 1I1Oth the power dissipation of the conven-
tional567 type tone decoder, without sacrificing its key features such as
the oscillator stability, frequency selectivity, and detection threshold.
Typical quiescent power dissipation is less than 4mW at 5 volts.
8 SOP

FEATURES
• Very low power dissipation (4mW at 5V)
..
•
Bandwidth adjustable from 0 to 14% of fo
Logic compatible output with 10mA current sinking capability.
I
• Highly stable center frequency_
• Center frequency adjustable from 0.01 Hz to 60KHz.
• Inherent immunity to false signals.
• High rejection of out-of-band signals and noise.
• Frequency range adjustable over 20:1 range by external resistor.

APPLICATIONS ORDERING INFORMATION

• BaHery-oPllrated tone detection • Touch-tone decoding
Device Package Operating Temperature
• Sequential tone decoding • Communications paging
• Ultrasonic remote-control • Telemetric decoding LM567LN 8 DIP
0-+ 70·C
LM567LD 8 SOP
SCHEMATIC DIAGRAM

·c8 SAMSUNG SEMICONDUCTOR 247

LMS67L LINEAR INTEGRATED CIRCUIT

, ABSOLUTE MAXIMUM RATINGS (Ta 25°C) =

Characteristic Symbol ' value Unit

Power Supply Vee 10 V

Power Dissipation
Plastic Package Pd 300 mW
Derate Above +25°C 2.5 mWfOC
Operating Temperature Topr' 0- +70 °C
Storage Temperature Tstg -65 - +150 °C

ELECTRICAL CHARACTERISTICS
(Vee = +5V, T. = 25°C, unless otherwise specilied.)

Characteristic Symbol Te,st Conditions Min Typ Max Unit

Supply Voltage Range Vee 4.75 8.0 V

Supply Current/Quiescent Icc>, RL=20KO, 0.6 1.0 mA
Supply Current/Activated leC>2 ' RL =20KO, V'N =300mV, I, =10 0.8 1.4 mA
Highest Center Frequency Hlo R1=3KO- 5KO 10 60 KHz
Center Frequency Drift
Temperature
0<T.<70°C See Figures 15 and 16 -150 ppml°C
Supply Voltage 10=,10KHz, Vee =4.75-5.75 0.5 3.0, %N
--
10 =10KHz, V'N =300mV rms
Largest Detection Bandwidth B.w 10 14 18 %0110
RL=20KO
Largest Detection Bandwidth Skew BWs See Figure 4 lor Delinition 2 3 %0110
Largest Detection BWt V'N = 300mV rms, RL = 20KO ±0.1 %/oC
Bandwidth Variation
With Temperature
Largest Detection BWv V'N = 300mVnns, Rl = 20KO ±0.2 '%N
Bandwidth Variation
With Supply Voltage
Input Resistance R'N 100 KO
Smallest Detectable Input Voltage V'N.' Il =10mA, I, =10 =10KHz 20 25 mVnns
Largest No-Output Input Voltage V'N.2 ' IL=10mA,I,=lo=10KHz 10 15 mVrms
Greatest Simultaneous , '
S,/Sd V,N=300mV,I,'1=6KHz +6 -dB
Outband Signal to I, =fo =10KHz
Inband Signal Ratio
Minimum Input Signal to S2/Sd V'N=300mV,I,'2=14KHz -6 dB
Wideband Noise Ratio I, =fo=10KHz
Voo-, IL=2mA, V'N ",25mVrms 0.2 0.4 V
Output Saturation Voltage
VSAT.2 IL= 10mA, V'N= 25mVrm• 0.3 0.6 V
,Output Leakage Current leo 0.01 25 pA
Fastest On/Off Cycling Rate FouT li=lo=10KHz 10120
Output Rise Time T, RL= 1KO 780 nS
Output Fall Time T, RL=1KO 100 nS

c8 SAMSUNG SEMICONDUCTOR' 248

 LM567L LINEAR· INTEGRATED CIRCUIT

BLOCK DIAGRAM
OUTPUT FILTER 1

LOOP FILTER 2

II
INPUT 3 6 TIMING RESISTOR

5 TIMING CAPACITOR

TEST CIRCUIT .
vee
+5V

HL
4
20KII
INPUT
+--4---'-0 OUTPUT

Fig. 1
TYPICAL APPLICATION CIRCUIT
vee

RL

8 1---+--0 OUTPUT

1
fo='1'I1Cl

Fig. 2

c8 .SAMSUNG SEMICONDUCTOR 249

 LM567L LINEAR INTEGRATED CIRCUIT

CIRCUIT DESCRIPTION
The LM567L monolithic circuit consists of a phase detector, low pass filter, and current controlled oscillater which comprise
the basic phase-locked loop, plus an additional low pass filter and quadrature detector enabling detection of in-band signals.
The device has a normally high open collector output.
The input signal is applied to Pin 3 (100KO nominal input resistance). Free running frequency is controlled by an RC network
at pins 5 arid 6. A capacitor on pin 1 serves as the output filter and eliminates out-of-band triggering. PLL filtering is accom-
2;
plished with a capacitor on Pin band-width and skew are also dependent upon the circuitry here. Pin 4 is +Vcc (4.75 to
fN nominal, 10V maximum); Pin 7 is ground; and Pin 8 is the open collector output, pulling low w~en an in-band signal triggers
the device.
The LM567L is pin-for-pin compatible with the standard LM567-type decoder. Internal resistors have been scaled up by a
factor of ten, thereby reducing power dissipation and allowing use of smaller capacitors for the same applications compared
to the standard part. This scaling also lowers maximum device center frequency and load current sinking capabilities.

PRINCIPLES OF OPERATION
The LM567L is a frequency selective tone decoder system based on the phase-locked loop (PLL) principle. The system
is comprised of a phase-locked loop, a quadrature detector, a voltage comparator, and an output logic driver.
When an input tone is present within the pass-band of the circuit, the PLL synchronizes or "locks" on the input signal.
The quadrature deiector serves as a lock indicator: when the PLL is locked on an input Signal, the DC voltage at the output
of the detector is shifted. This DC leve) shift is then converted to an output logic pulse by the amplifier and logic driver.
The logic output at Pin 8 is an "open-collector" NPN transistor stage capable of switching 10mA current loads.
The logic output at Pin 8 is normally in a "high" state, until a tone that is within the capture range of the decoder is present
at the input. When the decoder is locked on an input Signal, the logic output at Pin 8 goes to a "low" state.
Fig 3 shows ihe typical output response of the 'circuit for a tone-burst 'applied to the input, within the detection band.
The center frequency of the detector is set by the free-running frequency of the current-controlled oscillator in the PLL.
This free-running frequency, fo, is determined by the.selection of R1 and C1 connected to Pins 5 and 6, as shown in Fig 2.
The detection bandwidth is determined by the size of the PLL filter capacitor, C2 (see Fig 10); and the output response speed
is controlled by the output filter capacitor, C3.

DEFINITION OF DEVICE PARAMETERS

CENTER FREQUENCY fo
fo is the free-running frequency, of the current-controlled oscillator with no input signal. It is determined by resistor R1
between Pins 5 and 6, and capacitor C1 from Pin 6 to ground, fo can be approximated by

'fo = R1~1 Hz where R1 is in ohms and C1 is in farads.

DETECTION BANDWIDTH (8W)

The largest detection bandwidth is the frequency range centered about fo, within which an input signal larger than the
threshold voltage (typically 20mV,ms) will cause a logic zero state at the output. The detection bandwidth corresponds to
the capture range of the PLL and is determined'by the low-pass loop filter at Pin 2. Typical dependence of detection bandwidth
on the filter capaCitance and the input signal amplitude is shown in Figs 10 and 11, or may be calculated by the approximation.

B·W (%)=338
J V; (RMS)
fo (Hz).C2 (I'F)

LARGEST DETECTION BANDWIDTH

The largest detection bandwidth is the largest frequency range within which an input signal above the threshold voltage
will cause a logical zero state at the output. The maximum detection bandwidth corresponds to the lock range of the PLL.

c8 SAMSUNG SEMICONDUCTOR 250

LM567L LINEAR INTEGRATED CIRCUIT

DETECTION BANDWIDTH SKEW

The detection bandwidth skew is a measure of how accurately the largest detection band is centered about the center fre-
quency fo. This parameter is graphicaUy iUustrated in Fig 4. In the figure, fm,n and fm.. correspond to the lower and the
upper ends of the largest detection band, and f1 corresponds to the apparent center of the detection band, and is defined
as the arithmetic average of fmin and fmax and fa is the free running frequency of the LM567L oscillator section. The band- .
width skew Alx is the difference between these frequencies. Normal.ized to fo, this bandwidth skew can be expressed as:

Bandwidth Skew= ~ = (fmax+fmin-2 fa)

fa 2 fa

INPUT
I
OUTPUT

Response to 100mV,ms tone burst. RL=1Kfl

Fig. 3. Typical Output Response to 100mV Input Tone-Burst

If necessary, the detection bandwidth skew can be reduced to zero by an optional centering adjustment. (see optional
controls.)

OUTPUT LOGIC LEVEL LARGEST DETECTION BAND

1,----· "'v INCREASING FREQUENCY

fmrn fa h fmax

fa =PLL free-running frequency

f1 =Center freq of detection band = (fm.. + f m,n)/2

Fig. 4. Definition of Bandwidth Skew

PIN DESCRIPTION AND EXTERNAL COMPONENTS

PIN 3: INPUT
The input signal is applied to Pin 3 through a coupling capacitor. This terminal is internaUy biased at a DC level 2 volts
above ground, and has an input impedance level of approximately 100Kfl.

PIN 5 and 6: TIMING RESISTOR R1 and CAPACITOR C1

The center freql)ency of the decoder is set by resistor R1 between Pins 5 and 6, and capacitor C1 from Pin 6 to ground,
as shown in Fig 2.-
Pin 5 is the osciUator squarewave output which has a magnitude of approximately Vcc-1.4V and an average DC level of
Vcc/2.A 5Kflload may be driven from this point. The voltage at pin 6 is an exponential triangle waveform with a peak-to-
peak amplitude of=(Vcc-1.3)/3.5 volts and an average DC level of Vccl2. Only high impedance loads should be connected
to Pin 6 to avoid disturbing the temperature stability or duty cycle of the oscillator.

c8 SAMSUNG SEMICONDUCTOR 251

LM567L LINEAR INTEGRATED CIRCUIT

PIN 2: LOOP FIL TER·C2

Capacitor C2 connected from Pin 2 to ground serves as a single pole, low-pass filtE!r for the PLL portion of the LM567L.
The filter time constant is given by T2=R2C2, where R2 (I00KO) is the impedance at Pin 2. .
The selection of C2 is determined by the detection bandwidth requirements, as shown in Fig 10. For additional in-
formation see section on "Definition of Device Parameters."
The voltage at Pin 2, the phase detector output, is a linear function of frequency over the range of 0.95 fa to 1.05 fa. with
a slope of approximately 20mVl% frequency deviation.

PIN 1: OUTPU'T FILTER·C3

Capacitor C3 connected from Pin 1 to ground forms.a simple low-pass post detection filter to eliminate spurious outputs
due to out-of-band Signals. The time constant of the filter can be expressed as T3=R3C3, where R3 (47KO) is the internal
impedance at Pin 1.
If the value of C3 becomes too large, the turn-on or turn-off time of the output stage will be delayed until the voltage change
across C3 reaches the threshold voltage. In certain applications, the delay may be desirable as a means of suppressing
spurious outputs. Conversely, if the value of C3 is toci small, the beat rate at the output of the quadrature detector may cause
a false logic level change at the output (Pin 8).
The average voltage (during lock) at Pin 1 is a function of the in-band input amplitude in accordance with the given transfer
characteristic.

PIN 8: LOGIC OUTPUT

. Terminal 8 provides a binary logic output when an input signal is present within the pass-band of the decoder. The logic
output is an uncommitted, open-collector power transistor capable of switching high current loads. The current level at the .
output is. determined by an external load resistor, RL, connected from Pin 8 to the positive supply.
When an in-band signal is present the output transistor at Pin 8 saturates with .a collector voltage of less than O.W at
full rated output current of 10mA. If large output voltage swings are needed, RL can be connected to a supply voltage, V+,
higher than the Vee supply. For safe operation, V+ :$15 volts.

OPERATING INSTRUCTIONS
SELECTION OF EXTERNAL COMPONENTS
A typical connection diagram for the LM567L is shown in Fig 2. For most applications, the following procedure will
be sufficient for determination of the external components Rl, Cl, C2, and C3.
1. Rl and Cl should be selected for the desired center frequi:lncy by the expression fa'" l/R1C2. For optimum tem-
perature stability, Rl should be selected such that ~OKO:$ Rl :$200KO, and the R1Cl product should have sufficient
stability over the projected operating temperaturE! range.
2. Low-pass capacitor, C2,I can be determined from the bandwidth versus input signal amplitude graph of Fig 10.
One approach is to select an area of operation from the graph, and then adjust the input level and value of C2 ac-
cordingly. Or if the input amplitude variation is known, the required fa C2 product can be found to give the desired
bandwidth. constant bandwidth operation requires Vj >200mVrms. Then, as noted on the graph, bandwidth will be
controlled solely by the fa C2 product. .
3. Capacitor C3 sets the band edge of the low-pass filter which attenuates frequencies outside of the detection band
and thereby eliminates spurious outputs. If C3 is too small, frequencies adjacent to the detection band may switch
the output stage off and on at the beat frequency, or the output may pulse off and on during the turn-on transient.
A typical minimum value for C3 is 2 C2.
Conversely, if C3 is too large, turn-on and turn-off of the output stage will be delayed until the voltage across C3
passes the threshold value.

PRECAUTIONS
1. The LM567L will lock on signals near (2n+l) fa and produce an output for signals near (4n+ 1) fa, for n=O, I, 2 etc.
Signals at 5 fa and 9 fa can cause an unwanted output and should, therefore, be attenuated before reaching the input
of the circuit. .
2. Operating the LM567L in a reduced bandwidth mode of operation at input levels less than.200mVrms results in
maximum immunity to noise and out-band signals. Decreased loop damping, however, causes the worst-case lock-up .
time to increase, as shown by the graph of Fig 13.

c8 SAMSUNG SEMICONDUCTOR' 252

 LM567L LINEAR INTEGRATED CIRCUIT

3. Bandwidth variations due to changes in the in-band signal amplitude can be eliminated by operating the LM567L
in the high input level mode, above 200mV. The input stage is then limiting, however, so that out-band signals or high
noise levels can cause an apparent bandwidth reduction as the in-band signal is suppressed. In addition, the limited
input stage will create in-band components from subharmonic signals so that the circuit becomes sensitive to sig-
nals at fo/3, f0l5 etc.
4. Care should be exerc'ised in lead routing and lead lengths should be kept as short as possible. Power supply leads
should be properly bypassed close to the integrated circuit and grounding paths should be carefully determined to
avoid ground loops and undesirable voltage variations. In addition, circuits requiring heavy load currents should be
provided by a separate power supply, or filter capacitors increased to minimize supply voltage variations.

OPTIONAL CONTROLS
PROGRAMMING
Varying the value of resistor R1 and/or capaCitor C1 will change the center frequency. The value of R1 can be changed
either mechanically or by solid state switches. Additional C1 capacitors can be added by grounding them through saturated
npn transistors.
I
SPEED OF RESPONSE
The minimum lock-up time is inversely related to the loop frequency. As the natural loop frequency is lowered, the turn-on
transients becomes greater. Thus maximum operating speed is obtained when the value of capaCitor C2 is minimum. At
the instant an input Signal is applied, its phase may drive the oscillator away from the incoming frequency rather than toward
it. Under this condition, the lock-up transient is in a worst case situation, and the minimum theoretical lock-up time will not
be achievable.
The follOWing expressions yield the values of C2 and C3, in microfarads, which allow the maximum operating speeds
for various center frequencies where fa is Hz.
13 26
C2= - , C3= Jl.F
fa fa
The minimum rate that digital information may be detected without losing information due to turn-on transient or output
. chatter is about 10 cycles/bit, which corresponds to an information transfer rate of f0/10 baud. In situations where minimum
turn-off is of less importance than fast turn-on, the optional sensitivity adjustment circuit of Fig 5 can be used to bring
the quiescent C3 voltage closer to the threshold Voltage. Sensitivity to beat frequenCies, noise, and extraneous signals,
however, will be increased.

+V
+V

a1I
DECREASE
SNESITIVITY
RA
LM567L 1 R LM567L LM567L 1-'-'-1'-~~-~:
5DK

C3 INCREASE
SENSITIVITY
INCREASE
DECREASE SENSITIVITY
SENSITIVITY , .

SILICON
DIODES FOR
TEMPERATURE
COMPENSATION
(OPTIONAL)

Fig. 5. Adjustable Sensitivity Connections

ciS SAMSUNG SEMICONDUcroR 253

LM567L LINEAR INTEGRATED CIRCUIT

CHATTER
When the value of C3 is small, the lock· transient and ac components at the lock detector output may cause the output
stage to move through its threshold more than once, resulting in output chatter.
Although some loads, such as lamps and relays will not respond to chatter, logic may interpret chatter as a series of output
signals. Chatter can be eliminated by feeding a portion of the output back to the input (Pin 1) or, by increasing the size of
capacitor C3. Generally, the feedback method is preferred since keeping C3 small will enable faster operation. Three
. alternate schemes for chatter prevention are shown in Fig 6. Generally, it is only necessary to assure that the feedback time
constant does not get so large that it prevents operation at the highest anticipated speed.
+v +V +v +V

LM567L
RL

LM567L
8
RL

RI'
i~~·'"
~C3 R
C1 100K 1 10~K RL

~C3 LM567L r8--t~-'

Fig. 6. Methods of Reducing Chatter

SKEW ADJUSTMENT
The circuits shown in Fig 7 can be used to change the position of the detection band (capture range) within the largest
detection band (lock range). By moving the detection band to either edge of the lock range, input signal variations will expand
the detection band in one direction only, since R3 also has a slight effect on the duty cycle, this approach may be useful to
obtain a precise duty cycle when the circuit is used as an oscillator.

+V +V

IL~_I'L
LOWERSfo
R1 R2
51(

LM567L LM567L 50K

RAISES 10

--. 1
A3
lC2 1.0K

RAISESfo

<
SILICON
DIODES FOR
TEMPERATURE
COMPENSATION
(OPTIONAL)

Fig. 7. Detection Band Skew Adjustment

.c8 SAMSUNG SEMICONDU~R 254

LM567L LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS

FIG 8. SUPPLY CURRENT FIG 9. LARGEST DETECTION BANDWIDTH
V. SUPPLY VOLTAGE V. OPERATING FREQUENCY
3. 0 15

2.5
1'\
"'-
~
NO LOAD "ON" CURREN~ ~
I 2. 0

i!§'
u
1. 5
V
,//" /V
~

II
II:
i 1.
°vV ~SCENT CURRENT
o.
5 --

o
• SUPPLY VOLTAGE - VOLTS
10 10Hz 100Hz 1KHz
CENTER FREQUENCY
10KHz 100KHz

FIG 10. DETECTION BANDWIDTH FIG 11. BANDWIDTH Vs INPUT SIGNAL

V. A FUNCTION OF C2 AND C3 AMPLITUDE (C2 IN ~F)

2W~--~~~~---+---+---r---r--~

C3
C2
16 10 12 14 16
BANDWIDTH - % OF to BANDWIDTH - % of to

FIG 12. BANDWIDTH VARIATION FIG 13. GREATEST NUMBER OF

WITH TEMPERATURE CYCLES BEFORE OUTPUT
15.0

12.5
1.

400
1'\ 1'\
12 300
:2 200
~ 10.0

t
i!:
10

100
l:\. '" BANDWIDTH UMITED BY C2
I

"

I
75

5.0
8

6
- --
r-- 50 ~
"I
'\l\.
40
BANDWIDTH LIMITED BY
•
---t---
30 EXTESNAL RESISTOR-

2.5

rOWTTH
2
20 I'Vt l 11 MuM 2J

~ 1
AT!25 0 C
o 10
-75 -50 -25 25 50 75 100 125 1 3 • 5 10 20 30 4050 100
TEMPERATURE,oC BANDWIDTH", 0110)

c8 SAMSUNG SEMICONDUCTOR 255

LM567L LINEAR INTEGRATED CIRCUIT

FIG 14. POWER SUPPLY DEPENDENCE' FIG 15. TYPICAL CENTER FREQUENCY DRIFT
OF CENTER FREQUENCY = =
WITH TEMPERATURE(V cc 5V,Rl 80kIJ,fo 1KHz) =
1.2 100

1.1

1.0
I
0.9
I ..........
I
5'
I
0.8

0.7
f------
1-
Ii
100
'\
I 0.6 ~ -200 f\
~
il
0.5
0.4
~
1/ d
·w
IE
~-309
\
0.3

0.2
I -400
0:1

o -500
0.1 0.2 0.3 0.4 0.5 2 3 45 10 -25. o· 25 50 75
CENTER FREQUENCY - KHz TEMPERATURE, ·C

FIG 16. TYPICAL FREQUENCY DRIFT

AS A FUNCTION OF TEMPERATURE

cti:
r--fo_1KHz
"""';;;:::

f'\ "-
'\I\.
V+=5V

\
-4
-25 25 50 75
TEMPERATURE, ·C I

c8 SAMSUNG SEMICONDUCTO!=I. 256

MC1488 LINEAR INTEGRATED CIRCUIT

QUAD LINE DRIVER

The MC1488 is a monolithic quad line driver designed to interface data
terminal equipment with data communications equipmen,t in con-
formance with the specifications of EIA Standard No. RS-232C.

FEATURES
• Current Limited Output: ± 10mA typ
• Power-Off Source Impedance: 300 Ohms (min)
• Simple Slew Rate Control with External Capacitor
•
•
Flexible Operating Supply Range
Compatible with OTL and TTL, HCTLS Families

SCHEMATIC DIAGRAM (1/4 of Circuit Shown)

I
vee 14

300 ORDERING INFORMATION

OUTPUT
PIN 6,8,11 or3 Device Package Operating Temperature
MC1488N 14 DIP
0- + 70·C
MC1488D 14 SOP

GND7 J 10K
70
VEE 1

ABSOLUTE MAXIMUM RATINGS (Ta = 25°C unless otherwise noted)

Characteristic Symbol value Unit

Vee +15
Power Supply Voltage VDe
VEE -15
~ .
Input Voltage Range V'R -15sV,R s7.0 Voc
Output Signal Voltage VD ::1:15 Voc

Power Dissipation Po 1000 mW'

Derate Above Ta = + 25°C 1/RllJA 6.7 mWJOC
Operating Temperature Range Ta 0-+70 °C
Storage Temperature Range Tstg -65-+150 °C

c8 SAMSUNG SEMICONDUCTOR 257

MC1488 LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS
(Vcc~9.0±1%V, VEE~-9.0 ± 1%V, Ta~0-70°C unless otherwise noted)

Characteristic Symbol Test Conditions Min Typ Max Unit Fig

Input Current 1 I'L ' Low Logic State (V'L ~O) 1.0 1.6 mA 1
I'H High Logic State
Input Current 2 10 /LA 1
(V'H~5.0V)

V'L ~0.8V, RL ~3.0K(l

6 7
Vce~9.0V, VEE~ -9:0V
Output Voltage-High Logic State VOH V 2
V'L ~0.8V, RL ~3.0K(l
9 10.5
Vee~13.2V, VEE~-13.2V

V'H~1.9V, RL~3.0K(l
-6 -7
Vee~9.0V, VEE~-9.0V
Output Voltage-Low Logic State VOL V 2
V,~~1.9V, RL~3.0K(l
-9 -10.5
Vee~13.2V, VEE~-13.2V

Output Short Circuit .current 108+ Positive 6 10 12 mA 3

Output Short Circuit Current 108- Negative -6 -10 -12 mA 3
Output Resistance Ro Vee~VEE~O, Vo~ ±2.0V 300 !l
V'H~1.9V, Vee~+9.0V 15 20
V'L~0.8V, Vcc~ +9.0V 4.5 6
V'H~1,9V, Vce~+12V 19 25
Positive Supply Cur~ent(RL=oo) lee mA 5
V'L=0.8V, Vce=+12V 5.5 7
V'H= 1.9V, Vee = + 15V 34
V'L=0.8V, Vee=+15V 12
V'H=1.9V, VEE=-9.0V -13 -17 mA
V'L =0.8V, VEE = -9.0V -15 p.A
V'H=1.9V, VEE =-12V -18 -23 mA
Negative Supply Curren't (RL=QO) lEE 5
V'L=0.8V, VEE = -12V -15 p.A
V'H=1.9V, VEE =-15V -34 mA
V'L=0.8V, VEE =-15V -2.5 mA
Vee~9.0V, VEE=-9.0V 333
Power Consumption Pe mW
Vee = 12V, VEE,," -12V 576

* MaximLim packa'ge power dissipation may be exceeded if all outputs are shorted simultaneously.

SWITCHING CHARACTERISTICS
(Vee=9.0±1%V, VEE =-9±1%V, Ta=0-25°C)

Characteristic Symbol Test Conditions Min Typ Max Unit Fig

Propagation' Delay Time tpLH ZL =3.0K and 15pF 275 350 nS 6

Fall Time tTHL ZL =3.0K and 15pF 45 75 nS 6
Rise Time trLH ZL =3.0K and 15pF 55 100 nS 6
Propugation Delay Time tpHL ZL =3.0K and 15pF 110 175 nS 6

c8 SAMSUNG SEMICONDUCTOR 258

MC1488 LINEAR INTEGRATED CIRCUIT

DC TEST CIRCUIT

FIGURE 1 INPUT CURRENT FIGURE 2 OUTPUT VOLTAGE

+1.9V

JVIL
3K
II

+5V
1
FIGURE 3 OUTPUT SHORT CIRCUIT CURRENT FIGURE 4 OUTPUT RESISTANCE (POWER OFF)
Vee VEE

+1.9V

L vee
±2Vdc

±6mAMax

ciS SAMSUNG SEMICONDUCTOR 259

MC1488 LINEAR INTEGRATED CIRCUIT

FIGURE 5 POWER SUPPLY CURRENTS

+1.9V

J MC1488

VIL
+0.8V

Vee

FIGURE 6 SWITCHING RESPON~E

VINO~-D---1--3K -"':""""'-i------'OVO
15PF

vo-----
tTHL and ItTLH Measured 10% to 90%

c8 SAMSUNG .SEMICONDUCTOR . 260

MC1488 LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS

FIGURE 7 - TRANSFER CHARACTERISTICS FIGURE 8 - SHORT CIRCUIT OUTPUT CURRENT

V. POWER-SUPPLY VOLTAGE V. TEMPERATURE
+12

+9.0

+6D
r-
V"'r'r-r
Vcc-9V, VEE--9V
--

- - -- - -
--

Vcc=6V, VEE'''''-6V
r-- -

-9D
f-- r- V'~VO
3K

-12~ __~__~__~~__L -__L-__L -__~

II
o 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -55 +25 +75 +125

V", INPUT VOLTAGE (V) T, TEMl>ERATURE ("ell

FIGURe 9 - OUTPUT SLEW RATE V. LOAD FIGURE 10 - OUTPUT VOLTAGE
- CAPACITANCE AND CURRENT LIMITING CHARACTERISTICS

1000____.
__
i
~
10 _ __-
w
Iii
II:

~~
5 === ~ _ V~I,'I~II
10
r m
IIIWI! IIIII
to L--J....l.1J..Lll1111JJ..-.J-J
to 10 10
1111..LU1.lJJL----L.J..LLllJJl------,-J---LJ--WJlI
1,000

_1>., CAPACITANCE (pF)

10DOQ -16 -12 -8.0 -4.0 +4.0
Vo, OUTPUT VOLTAIlE'(V)
+8.0 +12 +16

FIGURE 11 - MAXIMUM OPEATING TEMPERATURE

V. POWER SUPPLY VOLTAGE
,.
14

"
~

I
~ 10

ian
12

Vee'

.&;3 3K
"" ........

OJ
Hi 6.0 ti
.~
~ T ,
iii 4_0
>
i 2D I I

-55 +25 +75 +125

T, TEMPERATURE ("ell

c8 SAMSUNG SEMICONDUCTOR 261

 MC1488 . LINEAR INTEGRATED CIRCUIT

APPLICATION INFORMATION
The Electronic Industries Association (EIA) RS232C specification detail the requirements for the interface between data
processing equipment and data communications equipment. This standard specifies not only the number and type of interface
leads, but also the voltage levels to be used. The MCl488 quad driver and its companion circuit; the MC1489/A quad receiver,
provide a complete interface system between DTL or TTL logic levels and the RS232C defined levels. The RS232C require-
ments as applied to drivers are discussed herein .
• The required driver voltages are defined as between 5 and 15-volts in magnitude and are positive for a logic "0" and negative
for a logic "1". These voltages are so defined when the drivers are terminated with a 3000 to 7000-ohm resistor. The MC1488
meets this voltage requirement by converting a DTUTTL logic level into RS232C levels with one stage of inve~ion.
The RS232C specification further requires that during transitions, the driver output slew rate must not exceed 30 volts per
microsecond. The inherent slew rate of the MC1488 is much too fast for ~his requirement. The current limited output of the
FIGURE 12 - SLEW RATE Vs CAPACITANCE
FORlsc=10mA

1000 _ _

100
._.
l
w
Ii
a:
~
OJ
10

C, CAPACITANCE (PF)

device can be used to control this slew rate by connecting a capacitor to each driver output. The required capacitor can be
easily determined by using the relationship C=los x tSf/AV from which Figure 12 is derived. Accordingly, a 33O-pF capaci-
tor on each output will guarantee a worst case slew rate or 30 volts per microsecond.
The interface driver is also required to withstand an accidental short to any other conductor in an interconnecting cable.
The worst possible signal on any conductor would be another driver using a plus or minus 15-volt, 500-mA source. The MCl488
, is designed to indefinitely withstand such a short to all four outputs in a package as long as the power-supply voltages are
greater than 9.0 volts (Le., Vcc~9.0 V:VEE~-9.0V). In some power-supply deSigns, a loss of system power causes a low
impedance on the power-supply outputs. When this occurs, a low impedance to ground would exist at the power inputs to
the MC1488 effectively shorting the 3OO-ohm output resistors to ground. If all four outputs were then shorted to plus or minus
15' volts, the power dissipation in these resistors would be excessive. Therefore, if the system is designed to permit low
o-....-""'T"----~-~ - ,- -----'1"'----
~ ¢M
: MCl48s-1
: r--, I

o-:-1 __,P-:-<>
I I
o-+-{-~I_-o
o-t-i .._~ 1
o-~--r ••-., :
o-~- {. __,P-t--o
Fig. 13 - Power supply protection to
meet power-off fault conditions
o-~--r"" !
o-i-.L_}>I-o
" ' __ r ___ J

VEE 1 7.~ +,
O-M--':":-'-~-----'-'-'-+--------:~.!-..L- ----

c8 SAMSUNG SEMICONDUCTOR 262

 MC1488 LINEAR INTEGRATED CIRCUIT

impedances to ground at the power-supplies of the drivers, a diode should be placed in each power-supply lead to prevent
overheating in this fault condition. These two diodes, as shown in Figure 8, could be used to decouple all the driver pack-
ages in a system. (These same diodes will allow the MC1488 to withstand momentary shorts to the i25-volt limits specified
in the earlier Standard RS232B.) The addition of the diodes also permits the MC1488 to withstand faults with power-supplies
of less than the 9.0 volts stated above.
The maximum short-circuit current allowable under fault conditions is more than guaranteed by the previously mentioned
10mA output current limiting.

Other Applications
The MC1488 is an extremely versatile line driver with a myriad of possible applications. Several features of the drivers
enhance this versatility:
1. Output Current Limiting - this enables the circuit designer to define the output voltage levels independent of power-
'supplies and can be accomplished by diode clamping of the output pins. Figure 14 shows the MC1488 used as a DTL to MOS
translator where the high-level voltage output is clamped one diode above ground. The resistor divider shown is used to reduce
the output voltage below the 300mV above ground MOS input level limit.
2. Power-Supply Range - as can be seen from the schematic drawing of the drivers, the positive and negative driving
II
elements of the device are essentially independent and do not require matching power-supplies. In fact, the positive sup-.
ply can vary from a minimum seven volts (required for driving the negative pulldown section) to the maximum specified 15
volts. The negative supply can vary from approximately -2.5 volts to the minimum specified the positive or negative sup-
plies as long as the current output limits are not exceeded. The combination of the current-limiting and supply-voltage fea-
tures allow a wide combination of possible outputs within the same quad package. Thus if only a portion of the four drivers
are used for driving RS232C lines, the remainder could be used for DTL to MOS or even DTL to DTL translation.Figure 15
shows one such combination.

FIGURE 14DTLITTL-TO-MOS TRANSLATOR FIGURE 15 LOGIC TRANSLATOR APPLICATIONS

+12V
IJTL D--+-o--,..---r--O RTL OUTPUT
MOSOUTPUT INPUT -O.7V to +3.7V
DTL (WITH VsS~GND)
DTL
TTL
NAND ......... I - l -.....J:H--<,......---,>----'-f'--O DTL OUTPUT
INPUT lK GATE -O.7V 10 +5.7V
10K INPUT
CTL
M.HTL
-12V -12V
INPUT

DTL
MOS
INPUT

TYPICAL APPLICATION
+12V -12V
LINE DRIVER INTERCONNECTING. LINE RECEIVER
MC1488 CABLE MC1489 PIN CONNECTIONS

...r--'~...r--,0- TTLlDTL
TTLlDTL -I
"1- __ " -L __ /

I I
I I
I-- --l
I I
I I
INTERCONNECTING
CABLE

c8 SAMSUNG SEMICONDUCTOR 263

MC1489/MC1489A LINEAR INTEGRATED CIRCUIT

QUAD LINE RECEIVER

'14 DIP
The MC1489 monolithic quad line receivers are designed to interface
data terminal equipment with data communications equipment in con-
formance with the specifications of EIA Standard No. RS-232C.

FEATURES
• Input Resistance - 3.0KO to 7.0KO
• Input Signal Range - ± 30 Volts
• Response Control 14 SOP
a) Logic Threshold Shifting
b) Input Noise Filtering
• Input Threshold Hysteresis Built in

SCHEMATIC DIAGRAM
(1/4 OF CIRCUIT SHOWN)

r---....-~--Ov~
14
9K 1.6K

RESPONSE RF ORDERING INFORMATION

CONTR0lO---_p----...."N\,....-+---;
Pins 2, 5, 9, 12
Device Package Operating Temperature
MC1489N
14 DIP
3.55K
OUTPUT MC1489AN
INPUT
Pins3,S,8,n 0-+ 7Q·C
MC1489D
Pins 1, 4, 10, 13 14 SOP
MC1489AD
10K

ABSOLUTE MAXIMUM RATINGS (Ta =25°C)

Characteristic Symbol Value Unit

~er Supply Voltage Vee .10 Voc

Input Voltage Range V'R ±30 Voe
Output Load Current IL 20 mA
Power Dissipation Po 1000 mW
Derate Above T. = + 25"C 1/IJJA 6.7 mWI"C
Operating Temperature T. Oto +70 °C
Storage Temperature Tstg -65 to +150 °C

ciS SAMS,-!NG SEMICONDUCTOR' 264

MC1489/MC1489A LINEAR INTEGRATED CIRCUITS

ELECTRICAL CHARACTERISTICS
(Vee =5.0± 10%V, Ta =0 _70°C unless otherwise noted)

Characteristic .Symbol Test Conditions Min TYP Max Unit

V,H =25Vdc 3.6 8.3

Positive Input Current I'H r---' 1---- ~--.
mA
V,H =3.0Vdc 0.43
"- - - -1 - - -f---- ~--

V,L =-25Vdc -3.6 -8.3

Negative Input Current- r-' -- mA
I'L
V'L = -3.0Vdc -0.43
Ta=25°C, VOL s 0.45V

II
Input Turn-On Thereshold Voltage V,H
MC1489 1.0 1.5 Vdc
MC1489A 1.75 1.95 2.25
.. "" .. _--- r---- -- I--.
Ta=25°C, VOH 2: 2.5V,
Input Turn-Off Threshold Voltage V'L 0.75 1.25 Vdc
ic=O.5mA
V,H =0.75V,IL=-0.5mA 2.5 4.0 5.0
. Output Voltage High VOH Vdc
Input Open, IL = - 0.5mA 2.5 4.0 5.0
Output Voltage Low VOL V,L =3.0V,IL=10mA 0.2 0.45 Vdc
Output Short Circuit Current los -3.0 -4.0 mA
All gates "on", lOUT =OmA,
Power Supply Current lee 16 26 mA
V'H=5.0V
Power Consumption Pe V'H=5.0V 80 130 mW

SWITCHING CHARACTERISTICS
(Vee=5.0±1%V, Ta =25°C, See Fig. 1)

Characteristic Symbol Test Conditions Min TYP Max Unit

Propagation Delay Time tpLH RL=3.9KO 25 85 nS

Rise Time IrLH RL=3.9KO 120 175 nS
Propagation Delay Time tpHL RL=3900 25 50 nS
Fall Time IrHL RL=3900 10 20 nS'

TYPICAL APPLICATION
PIN CONNECTIONS
LINE DRIVER LINE RECEIVER
MC1488 INTERC0NNEcriNG MC1489
InputA 1
...r---~--""t
TTLlDTL-=!. __ ~> L-/ ~ ... __ ..~ TTLlDTL
Response
ControlA 2
12 Response
Control 0
I I
I I
I I Response
r-- --; ControlB
Inpu1C
! : 9 Response
INTERCONNEcrlNG Comrol C
CABLE
Ground 7 8 OutputC

c8 SAMSUN~ SEMICONDUCTOR 265

MC1489/MC1489A LINEAR INTEGRATED CIRCUIT

TEST CIRCUIT

Fig 1 - SWITCHING RESPO~SE Fig 2 - RESPONSE CONTROL NODE

VR

~----~----~~----VO
C~
Vln

+3V Jr CL RESPONSE NODE

~ O% Von --~1/4-:--1 _ _ . - - - - - - - . Vo
50%
Vin tPHL MCI489A
tPlH ITLH and ITHL C; capacitor is for noise filtering
vo measured R. relstor Is for threshold shifting
10%-90%

. CL _15pF=total parasitic capacitance, which includes

probe and wiring capacitances ,

TYPICAL PERFORMANCE CHARACTERISTICS

(Vcc=5.0 Vdc Ta = + 25°C unless otherwise noted)

Fig. 3 - TYPICAL TURN-ON THRESHOLD V. Fig. 4 - TYPICAL TURN-ON THRESHOLD V.

CAPACITANCE FROM RESPONSE CONTROL PIN 10 CAPACITANCE FROM RESPONSE CONTROL PIN 10
GND GND

MC1489

~ • I------'\---+---+-----'lrl-------\

~
i3~~~~~r+--~

IL-~--=:::~~ 10 100 1000 10,000

10 100 1000 10.000
PW, INPUT PULSE WIDTH (.., PW, INPUT PULSE WIDTH (nl,

c8 SAMSUNG SEMICONDUCTOR 266

MC1489/MC1489A LINEAR INTEGRATED CIRCUIT
MC1489 INPUT THRESHOLD
Fig. 6 -
Fig. 5 -INPUT CURRENT VOLTAGE ADJUSTMENT

+10 6.0

+8.0
5D
+6.0

1./
./ AT AT AT AT

YEO
~
5K 13K 11K

/' V" V,h v"

V +5V +5V -5V AT

if, VIII
./
/'
- -
Y
-6D '- L-

VILH V,HL
-6.0 ::: ~

-10
-25-20 -15 -10 -5.0 0 +5.0 +10 +15 +20 +25 -3.0 -2.0 -1.0 0 +3.0 +2.0 +10

VIN, INPUT VOLTAGE (V) VI, INPUT VOLTAGEi(V)

Fig. 7 - MC1489A INPUT THRESHOLD Fig. 8 - INPUT THRESHOLD VOLTAGE
VOLTAGE ADJUSTMENT VB. TEMPERATURE

- --
8.0 2.

22
5D MC1489A V,LH
... 20
r-- - I -
AT A, AT
iw
~
18

16
,.
-
~r·
g
-
5K 11K

+5V
v" V"
-5V
AT
V"
0
6X
[3
II:
X
....
....
:J
0-
il! 0.6
12

10

DB -
-- r-- ~VIt-l
MC1489V,LH

MC1489A VlI..H
r--

- V,LH
= V'Hl
I--
ii
> 0.4
0.2

-30 -20 -10 0 +10 +20 +30 +40 -60 +120

VI, INPUT VOLTAGE (V) T, TEMPERATURE (Ge)

Fig. 9 -INPUT THRESHOLD VB.
POWER SUPPLY VOLTAGE
2.0
V,HLM 1489A

V,HL MC1489

V,LH MC1489

VllH MC1489A
,.

o
o 'D 6.0 12

Vee POWER SUPPLY VOLTAGE M

c8 SAMSUNG SEMICONDUCTOR 267

MC14891MC1489A LINEAR INTEGRATED CIRCUIT

APPLICATION INFORMATION
General Information
The Electronic Industries Association (EIA) has released the R8-232C specification detailing the requirements for the inter-
face between data processing equipment and data communications equipment. This standard specifies not only the number
and type of interface leads, but also the voltage levels to be used. The MC1488 quad driver and its companion circuit, the
MC1489 quad receiver, provide a complete interface system between OfL or TTL logic levels and the R8-232C defined levels.
The RS-232C requirements as applied to receivers are discussed herein.' .
The required 'input impedance is defined as between,30oo ohms and 7000 ohms for input voltages between 3.0 and 25
volts in magnitude; and any voltage on the receiver input in an open circuit condition must be le,ss than 2.0 volts in magni-
tude. The MC1489 circuits meet these requirements with a maximum open circuits meet these requirements with a maxi-
mum open circuit voltage of one VeE.
The receiver shall detect a voltage between -3.0 and -25 volts as a Logic "1" and inputs between +3.0 and +25 volts
as a Logic "0". On some interchange leads, an open circuit of power "OFF" condition (300 ohms or more to ground) shall
be decoded as an "OFF" condition or Logic "1". For this reason, the input hystereSiS thresholds ofthe MC1489 circuits are
all above ground. Thus an open or grounded input will cause the same output as a negative or Logic "1" input.

Device Characteristics
The MC1489 interface receivers have internal feedback from the second stage to the input stage providing input hystere-
sis for noise rejection. The MC1489 input has typical turn-on voltage of 1.25 volts and turn-off of 1.0 volt for typical hystere-
sis of 250mV. The MC1489A has typical turn-on of 1.95 volts and turn.-off of 0.8 volt for typically t 15 volts of hysteresis.
'Each receiver section has an external response control node in addition to the input and output pins, thereby allowing the
designer to vary the input threshold voltage levels. A resistor can be connected between this node and an external power-
supply. Figures 2, 6 1and 7 illustrate the input threshold voltage shift possible through this technique.
This response node can also be used for the filterin!) of high-frequency, high-energy noise pulses. Figures 3 and' 4 show
typical noise-pulse rejection for external capacitors of various sizes.
These two operations on the response node can be combined or used individually for many combinations of interfacing
applications. The MC1489 circuits are particularly useful for interfacing between MOS circuits and OfLffTL logic systems.
In this application, the input threshold voltages are adjusted (with the appropriate supply and resistor ,values) to fall in the
center of the MOS voltage logic levels. (See Figure 9).
The response node may alSo be used as the receill6r input as long as the designer realizes that he may not drive this node
with a low impedance source to a voltage greater than one diode above ground or less than one diode below ground. This
feature is demonstrated in Figure10 where two receivers are slaved to the same line that must still meet the RS-232C
impedance requirement.

c8 SAMSUNG SEMICONDUCTOR 268

 MC1489/MC1489A LINEAR INTEGRATED CIRCUIT

Fig. 10 - TYPICAL TRANSLATOR APPLICATION - MOS TO DTL OR TTL

+5Vdc
R
.
r---...\
--1L. ___..."
OTL or TIL
r .. - .....
---l ,

+svdclrh'
II
Fig. 11'- TYPICAL PARALLELING OF TWO MC1489/A RECEIVERS TO MEET RS-232C

Vcc
RESPONSE CONTROL PIN" r- - ---------- - - ---
I 1/2 MC1489
i
IN'~PU~T~_;'8:,:K~.Li-'----~+-H_ . . . . .-t<' OUTPUT

vcco--+----------,

OUTPUT
INPUT 8K

RESPONSE CONTROL PIN J

I
I
I I
IL _______________________ JI

ciS SAMSUNG SEMICONDUCTOR 269

MC3361 LINEAR INTEGRATED. CIRCUIT

16 DIP
LOW POWER NARROW BAND FM IF
The MC3361 is designed for use in FM dual conversion communication
equipment. It contains a complete narrow band FM demodulation system
operable to less than 2.SV supply voltage. .

FEATURES
• Includes: Oscillator, Mixer, limiting Amp, Quadrature Discriml· 16 SOP
nator, Active Filter, Squelch, Scan Control, and'Mute Switch
• Stable operation with wide supply voltage (2.5V to 7.0V)
• Low drain current (4.0mA "lYP. at Vcc =4.0V)
• Excellent Input Sensitivity
(-3dB limiting, 2.0"Vrms "lYp.)
• Minimum number of external parts required.

ORDERING INFORMATION
Device Package Operating Temperature
BLOCK DIAGRAM MC3361N 16 DIP
-20 -+ 10·C
MC3361D 16 SOP

SQUELCH TRIGGER WITH

HYSTERESIS

·DEMODUlAlOR

Fig. 1

c8 SAMSUNG SEMICONDUCTOR 270

MC3361 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Ta =25°C)

Characteristic Symbol value Unit

Supply Voltage Vcc 10 V

Detector Input Voltage Vo 1.0 Vp.. p
Input Voltage (Vcc;;,4.0V) V'6 1.0 Vrms
Mute Function V'4 -0.5- +5.0 Vpeak
Operating Temperature Top. -20- +70 °C
Storage Temperature TSIg -65- + 150 °C

ELECTRICAL CHARACTERISTICS
(Vee =4.0V, fo=10.7MHz, .:If= ± 3KHz, fmod =1KHz, Ta =25°C, Unless Otherwise Specified)
II
Characteristic Symbol Test Conditions Min Typ Max Unit

Squelch Off 4.0 mA

Circuit Current lee
Squelch On 6.0
Input Limiting Voltage V,NL -3dB Limiting 2.0 /LV
Detector Output Voltage V7 2.0 V
Detector Output Impedance Zoo 400 ohm
Recovered Audio Output Voltage Vo V,N =10mV 100 150 mVrms
Filter Gain AVF f= 10KHz, V,N:= 5mV 40 48 dB
Filter Output Voltage VOF 1.5 V
Trigger Hysteresis VTH 50 mV
Mute Function Low ROL ·10 ohm
Mute Function High ROH 10 Mohm
Scan Function Low V'31 Mute Off (V'2= 2V) 0.5 V
Scan Function High V'3H Mute On (V'2=GND) 3.0 V
Mixer Conversion Gain AVM 24 dB
Mixer Input Resistance R, 3.3 Kohm
Mixer Input CapaCitance C, 2.2 pF

c8 SAMSUNG SEMICONDUCTOR 271

MC3361 LINEAR INTEGRATED CIRCUIT

PIN CONNECTIONS
Pin 1: Oscillator Pin 2: Oscillator
Pin 3: Mixer Output Pin 4: Vcc
Pin 5: Limiter Input Pin 6: Decoupling
Pin 7: Limiter Output Pin 8: Quad Coil
Pin 9: Recovered Audio Output Pin 10: Filter Input
Pin 11: Filter Output Pin 12: Squelch In
Pin 13: Scan Control Pin 14: Mute
Pin 15: GND Pin 16: Mixer Input

'rEST CIRCUIT
vee

1--;---<> MIXER INPUT

MURATA
CFU 1 - - - - - - < > AUDIO MUTE
4550

1 - - - - - - - 0 SCAN CONTROL
MC3361
l - - - - - - < > SQUELCH IN

~--'-tt---o FILTER OUT

)-+--'II\f¥-'-H--O FILTER IN

1-"""'~1"""---o AF OUTPUT

Quad coil
Tokotype
RMC-2A6597HM

Fig, 2

c8 SAMSUNG SEM,ICONDUCTOR 272

MC3361 LINEAR INTEGRATED CIRCUIT

CIRCUIT DESCRIPTION (see block diagram)

Th~ MC3361 functions include an Oscillator, Mixer, FM IF limiting amplifier, FM demodulator, OP-amp, Scan control and
Mute switch.
The mixer combines the crystal controlled oscillator to convert the input frequency from 10.7MHz to an intermediate fre-
quency of 455KHz, where, after external bandpass filtering, most of the amplification is done. A conventional quadrature
detector is used to demodulate the FM signal. The a of the quad coil, which is determined by the external resistor placed
across it, has multiple affects on the audio output. Increasing the a increases output level because of nonlinearities in the'
tank phase characteristic.
After detection and de-emphasis, the audio output at pin 9 is partially filtered, then buffered by an emitter follower. The
signal still requires voiume control and further amplification before driving loudspeaker.
The op amp inverting input (pin 10) which is internally referenced to 0.7V, receives DC bias from the output of pin 11 through
the external feedback network. It is normally utilized as either a bandpass filter to extrect a specific frequency from th audio
output, such as a ring or dial-tone, or as a highpass filter to detect noise due to no input at the mixer. This information is applied
to pin 12. An external poSitive bias to pin 12 sets up the squelch trigger circuit such that pin 13 is low and the audio mute
(pin 14) is open circuit. If pin 12 is pulled down to 0.5Vdc by the nQise or tone detector, pin 13 will rise to approximately 0.5Vdc
below Vee and pin 14 is internally short circuited to ground. There is 50mV of hysteresis at pin 112 to prevent jitter.;Audio
II
muting is accomplished by connecting pin 14 to a high-impedance ground-reference'point in the audio path between pin 9
and the audio amplifier.

c8 SAMSUNG SEMICONDUCTOR 273

NOTE
 ,>."

-~, ~ -
k'
 Voltage Regulator
Device Function Package Page
KA350 3 AMP Adjustable Positive Voltage Regulator' ' TO-3P 277
KA3524 ' Regulator Pulse Width Modulator 16 DIP 285
LM317 3·Terrninal Positive Adjustable Regulator TO·220 291
LM323 3-Terminal Positive Voltage Regulator 14 DIP/14 SOP 423 '
LM723 Precision Voltage Regulator 14 DIP(14 SOP 300
KA78540 Switching Regulator, 16 ,DIP 306
KA78TXX 3A Positive Voltage Regulator TO·22O 312
MC78XX 3·Terrnihal 1A Positive Voltage'Regulator TO·22O 323
~C78LXX 3·Terrninal Positive Voltage Regulator TO·92 353
MC78MXX 3-Terminal 0.5A Positive Voltage Regulator TO·22O 364
MC79XX 3·Terrnlnal Negative V.olt;lge Regulator TO·22O 377
MC79MXX 3·Terrninal 0.5A 'Negative Voltage Regulator TO·220 387

, Voltage ,Reference
KA336·5.0 • Voltage Reference Diode TO·92 393
KA385-1.2 Micropower Voltage Reference Diode TO·92 397
KA431 Programmable Precision Reference TO·9218 DIP/8 SOP 401

Operational Amplifier
KA201 A Single Operational Amplifier 8 DIP/8 SOP 407
KA301A Single Operational Amplifier 8 DIP/8 SOP 407
KA733C Differential Video Amplifier 14 DIP/14 SOP 412
KA9256 Dual Power Operational Amplifier 10 SIP HIS 419
KF351 Single Operational Amplifier 8 DIP/8 SOP 421
, LM224/A Quad Operational Amplifier 14 DIP/14 SOP 423
L"M248 Quad Operational Amplifier' 14 DIP/14 SOP 432
LM2581A Quad Operational Amplifier 8 DIP/8 SOP/9 SIP 438
LM324/A Dual Operational Amplifier 14 DIP/14 SOP 423
LM348 Dual Operational Amplifier 14 DIP/14 SOP 432
LM3581A/S Quad Operational Amplifier 8 DIP/8 SOP/9 SIP 438 '
LM741C/ElI Single Operational Amplifier 8 DIP/8 SOP 446
.LM2902 Quad Operational Amplifier 14 DIP/14 SOP 423
LM2904 Dual Operational Amplifier 8 DIP/8 SOP/9 SIP 438
MC14581C/S/I Dual Operational Amplifier 8 DIP/8 SOP/9 SIP 452
MC3303 Quad Operational Amplifier 14 DIP/14 SOP 456
MC3403 quad Operational' Amplifier 14 DIP/14 SOP 456
MC4558C/AC/I Dual Operational Amplifier 8 DIP/8 SOP/9 SIP 463

Voltage Comparator
, KA319 Dual High Speed Voltage Comparator ' 14 DIP/14 SOP 468
KA3.61 High Speed Voltage Comparator 14 DIP/14 SOP 472
KAnOC High Speed Voltage Comparator 14 DIP/14 SOP 474
LM211 Voltage Comparator 8 DIP/8 SOP 476
LM239/A Quad Differential Comparator 14 DIP/14 SOP 481
LM293/A Dual Differential Comparator 8 DIPI8 SOP 489
LM311 Voltage Comparato! ·8 DIP/S SOP 476,
LM339/A Quad Differential Comparator 14 DIP/14, SOP 481
LM3931A1S Dual Differential Comparator 8 DIP/8 SOP 489
LM2901 Quad Differential Comparator 14 DIP/14 SOP 481
LM2903 Dual Differential Cpmparator S DIP/S SOP 489
LM3302 Quad Differential Comparator 14 DIP/14 SOP 481

Timer'
KS555 CMOS Timer -8 DIP/8 SOP 496
KS555H CMOS Timer 8 DIP/8 SOP 501
KS556 CMOS Timer 14 DIP/14 SOP 505
NE555 Timer 8 DIP/8 SOP 509
.NE556 Dual Timer 14 DIP/14 SOP 513
NE558 Dual Timer 16 DIP/16 SOP 516
KA350 .LINEAR INTEGRATED CIRCUIT

3 AMP ADJUSTABLE POSITIVE VOLTAGE

1"O-3P
REGULATOR
The KA350 is adjustable 3-terminal positive voltage regulator capable
of supplying in excess of 3.0A over an output voltage range of 1.2V to 33V.
This voltage regulator is exceptionally easy to use and require only two
external resistors to set the output voltage. Further, they employ internal
current limiting, thermal shutdown and safe area compensation, making
them essentially blow-out proof. All overload protection circuitry remains
fully functional even if the adjustment terminal is accidentally
disconnected.

FEATURES
• Output adjustable between 1_2V and 33V
•
•
•
•
•
Guranteed 3A output current
Intemal thermal overload protection
Load regulation typically 0-1 %
Line regulation typically O_005%N
Intemal short-circuit current limiting constant
1: Ad) 2: Output 3: Input II
with temperature., . ORDERING INFORMATION
• Output transistor safe-area compensation
• Floating operation for high voltage application Operating Temperature
• Standard 3-lead transistor package
• Eliminates stoc~ing many fixed voltages
o -J25~C

BLOCK DIAGRAM

VOLTAGE
REFERENCE
PROTECTION
CIRCUITRY

ADJ OUT

c8 ~AM~UNG SEMICONDUCTOR 277

KA350 LINEAR INTEGRATED CIRCUIT

, ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Input-Output Voltage Differential V,-Vo 35 Vee

Soldering Lead Temperature
T 'ead 300 °C
(10 Seconds)
Power Dissipation Po Internally limited
Operating Temperature Range TI 0- + 125 °C
Storage Temperature Range T.,g -65-+150 °C

ELECTRICAL CHARACTERISTICS
(V , - Vo = 5V, 10 = 1.5A, T, = aoc to 125°C; Pmax , unless otherwise speCified)

Characteristic ,Symbol Test Conditions Min Typ Max Unit

Ta=25°C,3V-s.V,-Vo-s.35V
Line Regulation 6Vo 0.005 0.03 %N
(Note 1)
Ta=25°C,10mA-s.lo-s.3A
Load Regulation 6Vo Vo-s.5V (Note 1) 5 25 mV
Vo~5V (Note 1) 0.1 0.5 %N~
Adjustment Pin Current lad! 50 100 tJA,
3V-s.V, -Vo -s.35V,
Adjustment Pin Current Change 61",,; 0.2 5.0 "A
10mA-s.IL-s.3A, PO-s.PMAX
Thermal Regulation VTAG Pulse";20mS, Ta=25°C 0.002 %IW
Reference Voltage ' VAEF 3V-s.V, -Vo -s.35V,10mA-s.lo-s.3A 1.2 1.25 1.30 V
Line Regulation 6Vo 3.0V-s.V,- Vo-s.35V 0.02 0.07 %N
10mA -s.lo-s.3.QA
Load Regulation 6Vo Vo-s.5.0V 20 70 mV
Vo~5.0V 0.3 1.5 %\(0
Temperature Stability Ts Tj=O°C to 125°C 1.0 %Vo
V, -Vo::;10V, PO-s.PMAX 3.0 4.5 A
Maximum Output Current IMAx
V, -Vo=30V, PO-s.PMAX, Ta=25°C 0.25 1.0 A
, Minimum Load Current
ILMIN V,-Vo=35V 3.5 10 mA
to Maintain Regulation
RMS Noise, % of Vo VN 10Hz-s.f-s.10KHz, Ta=25°C 0.003 %Vo
Vo =10V, f=120Hz,
Ripple Rejection , RR without CAOJ 65 dB
CAOJ = 10"F 66 80 dB
Long-Term Stability S Tj =125°C 0.3 1 %

Note 1: Regul'ation is measured at constant junction temperature. Changes in output voltage due to heating effects
must be taken into account separately. Pulse testing with low duty cycle is used.

ciS SAMSUNG SEMICONDUCTOR 278

KA3S0 LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTIC

0.4

tw 0.2
"
i r"",,-

-
t-5OOmA-
w
...!i;.!:5A T,=25:'(;'-

~-O.2 \
g ~~ \
!;-O.4

~
>
05- 0.6

<J
-0.8
." .......... I'--

II
-1.0 0
o 25 50 75 100 125 0 10 20 30 40
T JUNCTION TEMPERATURE (OC) VI- VOl INPUT-OUTPUT VOLTAGE DIFfERENTIAL (V.,J
"
Fig. 1 fig. 2

3.0
I:::.Vo=100mV
i
70 ;g
....
l.... 6/;
Z
w
a: 2.5

....
zw ~
E
'"
u
60

- w
"~

-------
~
.... 65
!'- g 2.0
·z
w
:&
Iii 50 ......'"
!;
~
0

J
45
.'"
....I
;!;
1.5

40 oj
35
,. I

. 0 25 50 75 100 125 25 50 75 100 125

TJ• JUNCTION TEMPERATURE (OC) TJ• JUNCTION TEMPERATURE (0C)
fig. 3 FIC!.4

,260 5.0

--
4.5 .. _-
TJ=25°C
4.0
,250 C
S-
t-:--. -..... ....
...'"
zw
3.5

3.0
u ./
V
,240 2.5
IEw
./
~ 2.0
....,.., ".."
5
a
,230 ~
1.5
,...... i--""'"
1.0

0.5
I I

25 50 75 100 125 o 10 20 30 40
T", JUNCTION TEMPERATURE {0C} V,-V.. INPUT-OUTPUT VOLTAGE DIFFERENTIAL (V,.)
FIg.·S . Fig. 6

c8 SAMSUNG SEMICONDUcrO~ 279

 KA350 LINEAR INTEGRATED CI.RCUIT

100 140

CJ=10lo'F
120
80

' .....
""', ..... WITHOUT CADJ
CAl =10 F
......
NI
20 rVI,-Vo=5V
, V.=15V
~

'" wrt~b

t-~~~~Z
IL =5OOmA
20
r-
f =l2OHz

o
T'=~'C
o TJ:ill
o w ~ 20 ~ ~ ~ 0.01 0.1 , 10
V.. OUTPUT VOLTAGE (V) I.. OUTPUT CURRENT (AI
fig. 7 .
fig.' .
100 10
,

~
'L=LA
VI=15V
r=y,= 15V
I-Vo=IOV
1-1,=5OOmA
Vo=1OV
80
TJ=25-C
TJ = 25°C
~
/ ~
III
V "' 1\
I"r\'\ , C?AD.I= 10"F
V
L
~
L

\ l\CAOJ=
, 10l'F L

\ ~ r-.... ~ V WITHOUT C ADJ

20
WITHOUTC~~
o 10- ,
10 100 lK 10K lOOK 1M 10M 10 100 lK 10K lOOK 1M
f, FREQUENCY (Hz) f, FREQUENCY (Hz)
fig. 8 Fig. 10

tlJV_
IL=5OmA
T'=~iC-
c,,=~"FJ""=IO"F
II
~,
"
11\
1\\ CL = 1",F: CAW =10"F
11/ 'h, = ~ WlT~OUT C,,,
-0.5 .
... -1.0
II $ -3
\
~,= 0: WITHOUT C""
~. -1.5 Ii ·1.5

~€ 11.0 1 I, Vr =15V

~
!!!l!
. 1.0

0.5
V,
~ 0.5
J 1
Vo=1OV .-
IML=5Om~

~3 0 -'1 \ TjC-

10 20 30 40 10 20 ~ 40
I,TIME"",) • f,TIME"",)
. fig. 11 FJg.12

:ciS SAMSUNG SEMICONDU<?",OR 280

KA350 LINEAR INTEGRATED CIRCUIT

APPLICATION INFORMATION
STANDARD APPL.ICATION

,... KA350 OUT

,...
~ IN VOUT

ADJ
I, j
R,

CIN
IAOJ I 120

Co

f" Fig. 13
/,

m
~R2

I" I
Cin : Cln is required if regulator is located an appreciable distance from power supply filter.
Co: Output capacitors in the range of 1!,F to 100!,F of aluminum or tantalum electrontic are commonly used to
provide improved output impedance and rejection of transients.

In operation, KA350 develops a nominal 1.25V reference voltage, Vref, between the output and adjustment
terminal. The reference voltage is impressed across program resistor R, and, since the voltage is constant, a
constant current I, then flows through the output set resistor R2, giving an output voltage of
R2
=
Vou• 1.25V (1 +~) + IAOJ R2

Since IAOJ current (less than 100!,A) from the adjustment terminal represents an error term, the KA350 was
designed to minimize I",OJ and make it very constant with line and load changes. "fo do this, all quiescent operating
current is returned to the output establishing a minimum load current requirement. If there is insufficient load on
the output, the output voltage will rise.
Sinpe the KA350 is a floating reg41ator, it is only the voltage differential across the circuit .which is important
to performance, and operation at high voltage with respect to ground is possible.

c8 SAMSUNG SEMICON~UCTOR 281

KA350 LlN~R INTEGRATED CIRCUIT

TYPICAL APPLICATIONS
LIGHT CONTROLLER . PRECISION POWER REGULATQR WITH
LOW TEMPERATURE COEFFICIENT

IN KA350 .OUT 1----.---:--~_oVOUT

ADJ IN KA350 OUTI-...-----'-OVOUT«4V

IN457 R1
375

_'-~10K

IN457 R2
Fig. 14
• Adjust for 3.75V across R1 L-_--4--_----,-Yl2~Kh
OUTPUT
Fig. 15 ADJUST

ADJUSTABLE REGULATOR WITH SLOW TURN·ON 15V REGULATOR

IMPROVED RIPPLE REJECTION
,VOUT
VIN IN KA350 OUT 15V

11N
KA350
ADJ
OUT
- VOUT C2 ADJ
R1

1·1~F
C2 240

l·1~F
R1
240 "~.D1· 1N4002 •
1M4802
+
=: C3 R3
1~ Ft 50K

C1.~~ VR2
1O~F /,
5K + C1
100~F

t Solid tantalum fi7

• Discharges Cl if output is shorted to ground
Fig. 16
o TO 30V REGULATOR 5V LOGJC REGULATOR WITH
ELECTRONIC SHUTDOWN'

IN KA350 OUT VOUT

VIN IN KA350 OUT VOUT
ADJ 7V- 38V 5V
~ ~~Il ADJ

C1 R1
240

P . . I' w",'
II. 1.2V

R3
680
,..: ~2
2K
C1
i'" 0.1~F

i,'-7
R2
720 2N2(
C2
i'"0.1~F

.....
1K
TIL

-10V
• Min output = 1.2V
Fig. 18 Fig. 19

c8 SAMSUNG SEMICONDUCTOR 282

KA350 LINEAR INTERGRATED CIRCUIT

TYPICAL APPLICATIONS (Continued)

PRECISION CURRENT LIMITER 1.2V-20V REGULATOR WITH MINIMUM

PROGRAM CURRENT

IN
R1* IN KA350 OUTt--~~--oVOUT

* 0.4SR1 S1200
Fig. 20 * Minimum load current =4mA
Fig. 21
SA CONSTANT VOLTAGE/CONSTANT CURRENT REGULATOR
MJ450r2_ _ _ _ _ _ _ _ _ _ _ _~-----~~-~

R1
33
35V o----1f-----'\Io.,.,..--IIN KA350

ADJ
OUT ~----.,__~======t_~~4-=:..:-_- OUTPUT
1.2V- 30

C3
+
I

+ C6
10pF
t Solid tantalum
* Lights in constant current mode -6V TO -15V.
Fig. 22
12V BATTERY CHARGER
500

R6
0.2

LED R2
15

R3
230

R4
15K
Q1
2N2905 ]-~--I*--~ TO 12V
1N457 BATTERY
O.lpF R1
3K

Fig. 23

c8 SAMSUNG SEMICONDUCTOR 283

KA350 LINEAR INTEGRATED CIRCUIT

R2
TRACKiNG PREREGULATOR 720
3A CURRENT REGULATOR

R1
240 VIN IN . KA350 OUT
I
ADJ R1
0.4
O---r- IN. KA350 OUT IN KA350 OUT - 0 V~UT 2W
ADJ
R3
12o

:: ~~~F : ~C2
l~F R4
1K,.:
~OUTPUT
ADJUST

Fig. 25
m Fig. 24

ADJUSTING MULTIPLE ON·CARD REGULATORS WITH SINGLE CONTROL"

VOUT VOUTt VIN

IN KA350 OUT IN KA350 OU'r IN KA350 OUT VOUTt

ADJ ADJ ADJ

1N4002 1N4002

'--____+--____--------'- - - - - - - - - - - - -4-------'

R2
1K
t Minimum load-10mA
• All outputs Within ± 100mV'
Fig. 26

AC VOLTAGE REqULATOR SIMPLE 12V BATTERY CHARGER

Rs'
0.2
0 - - IN KA350 OUT VIN IN KA350 OUT
ADJ ADJ
R1
120
120
...
I
A
'\]
12 Vp-p
,
480
I
r--\
6 VD-o
3A

L.J
,
1000~F"

R2
2.4K l
480

I
ADJ
120
• Rs- sets. output impedance of charger ZooT = As (1
•
+
R
if>
OUT
Use of Rs allows low charging rates with fully 1
0--- IN KA350
charged battery.
•• 1000l'F is recommended to filter
out any input transients.
Fig. 27 Fig. 28

.c8 SAMSUNG S~MICONDUcroR 284

KA3524 LINEAR INTEGRATED CIRCUIT

REGULATOR PULSE WIDTH MODULATOR

16 DIP
The KA3524 regulating pulse width modulator contains all of the
control circuitry necessary to implement switching regulators of either
polarity, transformer coupled DC to DC converters, transformerless
polarity converters and voltage doublers, as well as other power control
applications. This device includes a 5V voltage regulator capable of
supplying up to 50mA to external circuitry, a control amplifier, an
oscillator(a pulse width modulator, a phase splitting flip-flop, dual
alternating output switch transistors, and current limiting and shut-down
circuitry. Both the regulator output transistor"and each output switch
are internally current limiting and, to limit junction temperature, an
internal thermal shutdown 'circuit is employed.

FEATURES
• Complete PWM power control circuitry
• Frequency adjustable to greater than 100KHz
• 2% frequency stability with temperature
• Total quiescent current less than 10mA
• Dual alternating output switchs for both push-pull or slngle-ended
I
applications
• Current limit amplifier provides external component protection
• On-chip protection against excessive junction temperllture and
output current
• SV, SOmA linear regulator output available to user ORDERING INFORMATION
Operetlng Temperature
BLOCK D.IAGRAM 0-70·C
OSCILLATOR
OUTPUT

CURRENT
LIMIT

GROUND
(SUBSTRATE)

Fig_ 1

c8 SAMSUNG SEMICONDUCTOR 285

KA3524 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Input Voltage VIN 40 V

Reference Output Current lrel 50 mA
Output Current (Each Output) 10 100 mA
Oscillator Changing Currerit (pin 6 or 7) Ic~arge 5 mA
Lead Temperature (Soldering, 10 sec) Tlead 300' ·C
Power Dissipation Po 1000 mW
Operating Temperature Topr 0-+70 ·C
Storage Temperature . Tstg -65-+150 ·C

ELECTRICAL CHARACTERISTICS
(YIN = 20V, f = 20KHz, Ta = 0 to 70·C unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

REFERENCE SECTION .
Output Voltage Vref 4.6 5.0 5.4 V
Line Regulation Vlln• VIN =8-40V 10 30 mV
Load Regulation VIOad IL =0-20mA 20 50 mV
Ripple Rejection VRR f = 120Hz, Ta= 25·C 66 dB
Short-Circuit Output Current Isc Vrel=O, Ta=25·C 100 mA
Temperature Stability 0.3 1 %
Long Term Stability Ta=25·C 20 mV/Khr
OSCILLATOR SECTION
Maximum Frequency fMAX CT = 0.001ILF, RT = 2KD . 350 KHz
Initial Accuracy RT and CT constant 5 %
Frequency Change with Voltage 6f . VIN =8-40V, Ta=25·C 1 %
Frequency Change with Temperature 6f Over operating temperature range 2 %
Output Amplitude (Pin 3) VA3 Ta=25·C 3.5 V
. Output Pulse Width (Pin 3) V3PW CT=0.01ILF, Ta=25·C 0.5 ILs
ERROR AMPLIFIER SECTION
Input Offset Voltage VIO VCM=2.5V 2 10 mV
Input Bias Current liB VCM=2.5V 2 10 ~
Open Loop Voltage Gain Avo 60 80 dB
Common·Mode Input Voltage Range VCR Ta=25·C 1.8 3.4 V
Common·Mode Rejection Ratio CMRR Ta=25·C 70 dB
Small Signal Bandwidth BW Av=OdB, Ta=25·C 3 MHz
Output Voltage Swing Vosw Ta=25·C 0.5 3.8 V

c8 SAMSUNG SEMICONDUCTOR 286

KA3524 LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS (Continued)

(V,N=20V, f=20KHz, Ta=0-70°C unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

COMPARATOR SECTION
Maximum Duty Cycle DCm.. % Each output on 45 %
Input Threshold (Pin 9) VTH , Zero duty cycle 1 V
Input Threshold (Pin 9) VTH2 Maximum duty cycle 3.5 V
Input Bias Current Ie 1 ,.A
CURRENT LIMITING SECTION
V(Pin 2) - V(Pin 1)~50mV
'Sense Voltage Vsense 180 200 220 mV
Pin 9=2V, Ta=25°C
Sense Voltage T.C.
Common-Mode Current
OUTPUT SECTION (EACH OUTPUT)
Collector-Emitter Voltage VCEO
0.7

40
0.2
1
mV/oC
V

V
II
Collector Leakage Current ILKQ VcE =40V ,0.1 50 ,.A
Saturation Voltage VSAT IC=50mA 1 2 V
Emitter Output Voltage VE V'N =20V, 17 18 V
Rise Time (10% to 90%) tr RC=2KIl, Ta=25°C 0.2 ,.s
Fall Time (90% to 10%) tf RC=2KIl, Ta=25°C 0.1 ,.s
V'N=40V, PINS 1, 4, 7, 8,11
and 14 are grounded, Pin 2=2V
Total Standby Current ISTD 5 10 mA
All other inputs and
outputs open

APPLICATION INFORMATION
Voltage Reference
An internal series regulator provides a nominal 5 volt output which is used both to generate a reference voltage
and is the regulated source for all the internal timing and controlling circuitry. This regulator may be bypassed
for operation from a fixed 5 volt supply by connecting pins 15 and 16 together to the input voltage. In this configuration,
thE> maximum input voltage is 6.0 volts.
This reference regulator may be used as a 5 volt source for other circuitry. It will provide up to 50mA of current
itself and can easily be expanded to higher current with an external PNP as' shown in Figure 2.

EXPANDED REFERENCE CURRENT CAPABILITY

VREF

+ 10~J ~E~~~~~G ON
CHOICE FOR 0,

GNDo---------------+-------~-o

Fig. 2

i8 SAMSUNG SEMICONDUCTOR 287

 KA3524 LINEAR INTEGRATED CIRCUIT

Oscillator
The oscillator in the KA3524 uses an external resistor (RT) to establish a constant charging c;urr!!nt into an external
capacitor (CT). While this uses more current than a series connected RC, it provides a linear ramp voltage on the
capacitor which ,is also used as a reference for the comparator. The charging current is equal to 3.6V + RT and
should be kept within the range of approximately 30~ to 2mA, i.e., 1.SK<RT<100K. The range ,of vaiues for Cr
also has limits as the discharge time of Cr determines the pulse width. of the oscillator output pulse. This pulse
is used (among other things) as a blanking pulse to both outputs to insure that there is no possibility,of having'
both out'puts on simultaneously during transitions. This output dead time relationship [s shown in Figure 6. A pulse
,width below approximately 0.5 microseconds may allow faise triggering of one output by removing the blanking
pulse prior to the flip-flops reaching a stable state. If smal!" values of Cr must be used, the pulse width may still
be expanded by adding a shunt capacitance ( = 100pF) to ground at the oscillator output. (Note: Although the oscillator
output is a convenient oscilloscope sync input, the cable and input capacitance may increase the blanking pulse
width slightly.) Obviously, the upper limit to the pulse width is determined by the maximum duty cycle acceptable.
Practical values of Cr fall between .001 and 0.1 microfarad. ' .
The oscillator period is approximately t = RrCr where t is in microseconds when RT == ohms and Cr = microfarads.
The use of Figure 7will allow selection of RT and Cr for a wide range of operating frequencies. Note that for series
regulator applications, the two outputs can be connected in parallel for an effective 0-90% duty cyCle and the
frequency of the oscillator is the 'frequency of the output. For push-pull applications, the outputs are separated
,-"' . and the flip-flop divides the frequency such 'that each outputs duty cycle is 045% and the overall frequency is
one-half that of the oscillator. .

External Synchronization
If it is desired to synchronize the KA3524 to an external clock, a pulse of = + 3 volts may be applied to the oscillator
output termi.nal with RrCr set slightly greater than the clock period. The same considerations of pulse width apply.
The impedance to ground at this pOint is approximately 2K ohms. .
" .
If two or more KA3524s must be synchronized together, one must be designated as master with its ArCT set for
the correct period. The slaves should each have an RrCr set for approximately 10% longer period than the master
with the added requirement that CT(slave) = one-half Cr (master). Then connecting Pin 3 on all. units together will
insure that the.master output pulse-which occurs first and has a wider pulse width-,will reset the slave units.

Error Amplifier
This circuit is a simple differential-input, transconductance amplifier. The output is the compensation terminal,
pin 9, which is a high impedance node (Rl = 5MO). The gain is
SleRl .
Av=gmRl= 2KT =.002 Rl

and can easilY.be reduced from a nominal of 10,000 by an external shunt resistance from pin 9 to ground, as shown
in Figure S. .
In addition to DC gain control, the compensation terminal is also the place for AC phase compensation. The frequency
response 'curves of Figure 5 show the uncompensated amplifier with a single pole at approximately 200Hz and
a unity gain cross-over at 5MHz. .
Typically, most output filter deSigns will introduce one or more additional poles at a significantly power frequency.
Therefore, the best stabilizing network is a series R-C combination between pin 9 and ground which introduces
a zero to cancel one of the output filter poles. A good starting point is 5OKO plus .001 microfarad.
One final point on the compensation terminal is that this is also a convenient place to insert any programming
signal which is to override the error amplifier. Internal shutdown and current limit circuits are connected here, but
any other circuit which can SiAk 200l'A can pull. this point to ground thus shutting "ff both outputs.
. .
While feedback is normally applied around the' entire regulator, the error amplifier can be used with conventional
operational amplifier feedback and is stable in either the inverting or non-inverting mode. Regardless of the
connections, however, input common-mode· limits must be observed or output signal inversions may result. For
conventional regulator applications, the 5 volt reference voltage must be divided down as shown in Figure 3. The
error amplifier may also be used in fixed duty cycle applications by using the unity gain configuration shown in
the open loop test c'ircuit.

c8 SAMSUNG SEMICONDUCTOR 288

KA3524 LINEAR INTEGRATED CIRCUIT

Current Limiting
The current limiting circuitry of the KA3524 is shown in Figure 4.
By matching the base·emitter voltages of 01 and 02, and' assuming negligible voltage drop across R,:
Threshold = VBEl01) + I,R2- VBE(02)
=I,R2 =200mV
Although this circuit provides a relatively small threshold with a negligible temperature coefficient, there are some
limitations to its use, the most important of which is the ± 1 volt common mode range which requires sensing
in the ground line. Another factor to consider is that the frequency compensation provided by R,e, and 01 provides
a roll·off pole at approximately 300Hz.
Since the gain of this circuit is relatively low, there is a transition region as the current limit amplifier takes over
pulse width control from the error amplifier. For testing purposes, threshold is defined as the input voltage to get
25% duty cycle with the error amplifier signaling maximum duty cycle.
In addition to constant current limiting, pins 4 and 5 may also tie used in transformer·coupled circuits to sense

II
primary current and shorten an output pulse, should transformer saturati,on occur. Another application is to ground
pin 5 and use pin 4 as an additional shutdown terminal: Le., the output will be off with pin 4 open and on when
it is grounded. Finally, foldback current limitting can be provided with the network of Figure 5. This circuit can
reduce the shortcircuit current {lsc} to approximately onethird the maximum available output current (IMAX)'

ERROR AMPLIFIER BIASING CIRCUITS

r-AM...-- 6~~~~~E
VOLTAGE

Vo 2.5V (R + R2l
R, NEGATIVE
"--..w,,.-- OUTPUT
GND GND VOLTAGES
Note change in input connections for opposite polarity outputs.
Fig. 3
CURRENT LIMITING CIRCUITRY OF THE KA3524

Fig. 4
FOLDBACK CURRENT LIMITING
-O"'C<>-1rr","'-..---~-o Vo = 5V
SA/SB 1 VOR2
IMAx=Rs VTH + R, + R2

Isc = As
VTH
where
VTH =200mV

+
Foldback current limiting can be used to reduce
power dissipation under shorted output conditions
Fig. 5

c8 SAMSUNG SEMICONDUCTOR 289

KA3524 LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS

OUTPUT STAGE DEAD TIME AS A FUNCTION OSCILLATOR PERIOD AS A FUNCTION OF R., AND Or
OF THE TIMING CAPACITOR VALUE

,0

III
8 5
V
I
~ 2
/'
~
" 1.0
~
/
~
§ 0.5 _V/"
0.3

.001 .002 .005 .01 .02 .05 10 20 50 100 200 500 lmS 2mS
TIMING CAPACITOR VALUE(C,~.F OSCILLATOR PERIOD·,.s
Fig•• Fig. 7

AMPLIFIES OPEN·LOOP GAIN AS A FUNCTION

OF FREQUENCY AND LOADING ON PIN 9

80
RL_30m["

RL =1MO

RL=300KO
"'" .....
RL=100KO

'"'""\
R..=30Kll

20

R,=RESISTANCE FROM PIN 9 TO GROUND

10 100 lK 10K
FREOUENCY (liz)
Fig. 8
lOOK ""
1M 10M

c8 SAMSUNG SEM.ICONDUCTOR 290

LM317 . LINEAR INTEGRATED CIRCUIT

3-TERMINAL POSITIVE ADJUSTABLE

TQ.220
REGULATOR
The LM317 is a 3-terminal adjustable positive voltage regulator capable
of supplying in excess of 1.SA over an output voltage range of 1.2V to
37V. This voltage regulator is exceptionally easy to use and requires
only two external resistors to set the output voltage. Further, it employs
internal current-limiting, thermal-shutdown and safe area compensation,
making it essentially blow-out proof. The LM317 serves a wide
variety of applications including local, on-card regulation. This device
also makes an especially simple adjustable switching regulator, and a
programmable output regulator, or by connecting a fixed resistor bet-
ween the adjustment and output, the· LM317 can be used as a preci-
sion current regulator.

FEATURE
•
•
•
•
Output current In excess of 1.SA
Output adjustable between 1.2V and-37V
Internal thermal·overload protection
Internal short·clrcult current·limiting constant with
1: Adj 2: Output 3: Input
II
temperature
~ Output transistor safe·area compensation ORDERING INFORMATION
• Floating operation for high·voltage applications
• Standard 3·pin transistor packages Operating Temperature
Q-12S0C

SCHEMATIC DIAGRAM
3
'---~--~---1---...-- ............-------------r-----r----,...-.Q.v'N

Rll

c8 SAMSUNG SEMICONDUCTOR 291

LM317 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Input-Output. Voltage Differential 'VIN-VOUT 40 Voc

Lead Temperature TIOad 230 °C
Power Dissipation Po Internally limited -
Operating Temperature Range Tj o to +125 °C
Storage Temperature Range T.tg -65 to +150 °C

ELECTRICAL CHARACTERISTICS
(VIN-VOUT=5V, IOUT=0_5A, 0·CsT(:i;;125°C, Imax =1 ..5A, Pmax =2QW, unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

Ta=25°C
Line Regulation /,;Vo 3V S,VIN - VouTs,40V 0.01 0.0,4 %N
3V SVIN - VouT s40V 0.02 0.07 %N
Ta= 25°C, 10mAslouTs,IMAX
VoUT s,5V 5 25 mV
VouT~5V 0.1 0.5 ,%Vo
Load Regulation /,;Vo
10mAs,louTS IMAx
VoUT s,5V 20 70 mV
VouT~5V 0.3 1.5 %Vo
Adjustable Pin Current lAo. 50 100 p.A
2.5V S,VIN - VoUT s,40V
Adjustable Pin Current Change /';IAo. 10mAs, louTs, IMAx 0.2 5 ",A
PSPMAX
• 3V SVIN - VoUTs40V
Reference Voltage VREF 10mAs, louTs, IMAX 1.20 1.25 1.30 V
POS,PMAX
Temperature Stability Ts 0:7 %Vo
Minimum Load Current to
IL(min) VIN-VOUT=40V 3.5 10 mA
Maintain Regulation
VIN-VOUTS15V, POSPMAX 1.5 2.2
Maximum Output Current IMAx A
VIN - VOUT = 40V, POS,PMAX 0.15 0.4
RMS NOise, % of VOUT eN Ta=25°C,10Hzs,fs,10KHz 0.003 %Vo
VouT=10V, f=120Hz
Ripple Rejection RR without CAo. 65 dB
CAOJ = 10p.F 66 80
Ta=25°C for end pOint
Long-TermStability, Tj = Thigh S " 0.3 l' %1KHRS
measurements
Thermal Resistance Junction to Case Rs\Jc 5 °CIW

c8 SAMSUNG SEMICONDUCTOR 292

LM317 . LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS

LOAD REGULATION ADJUSTMENT CURRENT
80

- --- t--..
k -O.5A

1c=1~ /
~
I---" --- ~

VIN=15V
Vwr=1OV
-0.8

-1.0 ~
o 25 50 75 100 125 o 25 50 75 100 125
TEMPERATURE ("C) TEMPERATURE ("C)
fig. 1 fig. 2

DROPOUT VOLTAGE TEMPERATURE STABILITY

1,260

6VQIf=100mV

£~5~---+----~----~---+--~ £
1,250
.
- r--.
I~ -----r----t---~~::~::~~~~ ~cl
>1.240
"- r-.... .........
Ii1.5 ~--~-_=+=-j.,l;=-i!OO""!------:
I 1,230

. 1.0 L-__--L____...1...____L -__-L__- - I

1,2Z
o 25 50 75 100 125 o 25 50 75 100 125
TEMPERATURE ,0Cl TEMPERATURE l°c)
fig. a fig. 4

RIPPLE REJECTION RIPPLE REJECTION

100 l00r----,----,-----,----,----,
I Il =5OOmA
t---------t------t-----j-- VIN = 15V
c..,,=lo,.F
Vwr =10Y
80 eo t------:A="""~
Tj = 25°C

.~ ·1
~ ~O I
I t------t------t------'1~~._t_------J
50

i 40 1----+----+----1I-~rl_~~
f-- V.. -Vaur:5V
Io.~- zl----+----+----1I---~.-~
1= 120Hz
Tp_as-C

o I I
o m ~ Z 25 ~ ~
o1~0-----,,~oo-----:',K:----...J,O':-:K---::,OOK=--~,M
OUTPUT VOLTAGE (VI FREQUENCY (IbI
fig. I fig. •

ciS SAMSlJNG SEMICONDUCTOR 293

LM317 LINEAR INTEGRATED CIRCUIT

RIPPLE REJECTION -OUTPUT IMPEDANCE

100 10'
e V . 15V
!==V"",=lOV
.... ~ t-- 1L =500mA V
80

r-
l()O
T.=25°C
/
~~ f'...CAD.J=10p,'F

III
~CADJ=O
IIi 10- 1
C.r.DJ=o/ /
V

V1N =15V
I 10- 2
,./
/c... =10,F
20 t-- Voor=1OV
f= 120Hz
T. = 25°C

o lllU 10- 3
0.01 0.1 1 10 10 100 lK 10K lOOK 1M
OUTPUT CURRENT (A) FREQUENCY (Hz)
FIg. 7 fig. 8

LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE

1.5

i
~€ 1.0
I
gz
~ ~ 0.5
lit I ~,=0;1... =d~
o ~\ CL=O; CADJ=O
C -1"F; C = 10"F
L ADJ

... =1O/A.F
rr CL = 11'F; CAD.!
CI 0
-1
-0.5
Vour:::: 1OV -2 1\ VIN= 15V
VOUT=10V _
INL=50mA
-1.0 r-- Tk=50mA
=25·C
1 -3
\J T.=25·C

!E 1,5

iil 1.0 1
~ 0.5
L 1\
II \
10 20 30 10 20 30
TIME!..) TIME (oS)
FIg. 8 Fig. 10

c8 SAMSUNG SEMICONDUcrOR 294

LM317 LINEAR INTEGRATED CIRCUIT

TYPICAL APPLICATIONS
AC Voltage Regulator Current Limited 6V Charger

VIN
120 9V TO 60V
6Vp-p
~ .
'L..J

II
• Sets peak current (0.6A for 10)
Fig. 11 •• The 1000,.F is recommended to filter out
12V Battery Charger input transients
Fig. 12

R2
=
• Rs-sets output impedance of charg~r louT Rs (1 + R1)
Use of Rs allows low charging rates with fully
charged battery.
Fig. 13

c8 SAMSUNG SEMICONDUCTOR 295

LM323 LINEAR INTEGRATED CIRCUIT

3~TERMINAL POSITIVE VOLTAGE REGULATOR

T(I.3I'
The LM323 is a three-terminal positive regulator with a preset 5Voutput
and a load driving capability of 3 Amps.
New circuit design and processing techniques are used to provide the
high output current without sacrificing the regulation characteristics of
lower current devices. .

FEATURES
• 3 Amp output current
• Intemal current and thermal limiting
• 0.010 typical output Impedance
• 7.5 minimum Input voltage

1: Input 2: GND 3: Output

ORDERING INFORMATION
Operating Temperature
SCHEMATIC DIAGRAM' 0-125°C

INPUT SERIES OUTPUT

PASS -r-<>3
1

j ELEMENT

CURRENT SOA
GENERATOR PROTECTOR

STARTING
CIRCUIT
t-
REFERENCE
VOLTAGE
ERROR
AMPLIFIER
I
THERMAL
PROTECTION
I---

'[ GND

Fig. 1

c8 SAMSUNG SEMICONDUCTOR , 296

LM323 LINEAR INTEGRATED CIRCUIT

. ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Input Voltage Vc 20 V
Operating Temperature Range Top, 0- +125 °C
Storage Temperature Range TS1g -65- +150 °C

ELECTRICAL CHARACTERISTICS

Characteristic Symbol Test Conditions Min Typ Max Unit

Output Voltage Vo
TJ-25°C
VIN = 7.5V, loUT=O
7.6VsVIN s15V
OsIOUTs3A, Ps30W
4.8

4.75
5 5.2V

5.25 V
I
TJ=25OC
Line Regulation I1Vo 5 25 rmJ
7.5VsVIN s15V

Load Regulation I1Vo

TJ =25°C, VIN =7.5V 25 100 rmJ
Os louTs3A
7.5VsVIN s15V
Quiescent Current Id 12 20 mA
OslouTs3A
TJ=25OC,
Output Noise Voltage VN 40 p.Vrmo
10Hz s f s 100KHz
TJ =25"C, VIN=15V 3 A
Short Circuit Current lac
TJ=25OC, VIN =7.5V 4 A
Thermal Resistance
eJC 3 OCIW
Junction to Case

c8 SAMSUNG SEMICONDUCTOR 297

LM323 LINEAR .INTEGRATED CIRCUIT.

Fig. 2 MAXIMUM AIIEfIAGE POWER OISSIPATION Fig. 3 OUTPUT IMPEDANCE

10'

==\).:'~
cl.,,1'-
t I~

---r~:,,~
-~

~ 'DINTALUM

. r-YIN-15V
I (THE~IAAL EFFECI)
/
r-- V1N - 1

. '0 '00 'K 10K 100K 1M

T.-_ENT~("CI FREQUENCY (HzI

Fig. 4. PEAK _1LABi.E OUTPUT CURRENT Fig. 5 SHORT CIRCUIT CURRENT

......
,.1...., ......
, Tj-,26OC

,
, T,_,25"C ~
............ ~ ~.......
~

o o
6 . 10 15 20 5 10 '6 20
....UTVOLTAIII!(Y) INPUT 1IOLTAGE (Y)

Fig. 6

-
RIPPLE REJECTION Fig. 7 OROPOUT VOLTAGE
80 / 25

VlN.,ovT
IL-O,
7 .....
"
---
CL.lo,.F
-"LUM
saUD I

~N-1(JY,k.':;--
J \ ~ ~ ::- .......
Il-3A

IL-1A
!
.........
E3;;: :::::
(THERMAL EFFECI)
1\

1\
CL.,Y
20 o
1 10 100 lK 10K 100K 1M -75 -SO -25 0 25 50 75 100 125 160
JUNCI'ION TEMPERATURE ("CI

c8 SAMSUNG SEMIC()ND~CTOR 298

LM323 LINEAR INTEGRATED CIRCUIT

Fig. 8 LINE TRANSIENT RESPONSE Fig. 9 OUTPUT VOLTAGE

75 5.15

50
~ IL01501
CL o o.1,F 5.10 I--
VI.JJV
IL_2Or'nA:

\
TI_ZSC'C

I.......
.... -r-. ........
/ ........ ~
V

I
-75 -50 -25 0 25 50 75 100 125 150
TIllE"", TEMPERATURE rei

Fig. 10 QUIESCENT CURRENT Fig. 11 LOAD TRANSIENT RESPONSE

14

1°55"C

~
12 V1N_10\f
r 025'C 1)025'C

~,
1)0125'C
I
/ --!CL 0 1o,.F
SiiLIO 1l\N'1lWJM

I,
I/CL o o.1,F

I
/
o J
o 12 18 20 o
INPUf VllLU. (VI TIlE"",

Fig. 12 OUTPUTNOISEVOLTAGE
1D

.........

01
10 100 1K 10K
FREQUENCY (Hz)

c8 SAMSUNG SEMICONDUCTOR 299

LM723 LINEAR INTEGRATED CIRCUIT,

PRECISION VOLTAGE REGULATOR 14 DIP

The LM723 is a monolithic integrated circuit voltage regulator featuring
high ripple rejection, excellent output and load regulation, excellent
temperature stability, and low standby current.

FEAT,URES
• Poslt,ive or Negative Supply Operation.
• 0.01 % line and load regulation
14 SOP
• Output voltage adjustable from 2 to 37 volts.
• Output current to 150mA without extemal pass transistor

BLOCK DIAGRAM

TEMP,'
COM PENS
ZENER
FREQUENCY
COM PENS
11 Vc

• 1

~~ ORDERING INFORMATION
0.. Ii;
Ulr;;
wz Device Package Operating Temperatura
a:~
~I- LM723CN 14 DIP
O-+70·C
10 LM723CD 14 SOP
+----t-OVo LM7231N 14 DIP
-25-+85°C
LM7231D 14 SOP
3 9
Vre ,
_ Vec NON CURRENT CURRENT Vz
Fig. 1 ' ·INVERT LIMIT SENSE
INPUT
+Vcc .vc

OUTPUT

Vz

FREQUENCY
COMPENSATION
CURRENT
LIMIT
CURRENT
SENSE
Vre, NON - Vee INVERtING
INVERTING INPUT
INPUT '
Fig. 2

c8 SAMSUNG SEMICONDUCTOR 300

LM723 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Pulse Voltage from V + to V - (50ms) VIN(P) 50 Vpeak

Conti nus Voltage from V + to V - VIN 40 V
Input-Ou.tput Voltage Differential VIN-VO 40 V
Maximl!m Output Current 10 150 mA
Differentia) Input Voltage VID ±5 V
Voltage Between Non-Inverting Input and V- VIE 8 V
Current from Vz Iz 25 mA
Current from VREF "IREF 15 mA
Power Dissipation Po 1000 mW
LM7231 ~25-+85 ·C
Operating Temperature Range Top,
LM723C 0-+70 ·C

I
Storage Temperature Range T" g -65-+150 °C

ELECTRICAL CHARACTERISTICS
(unless otherwise specified, Ta=25·C, VI =Vee =Ve=12V, Vo = +5V, IL=1.0mA, Rsc=O, CI=100pF,
Cref=O and devider impedance as seen by error Amplifier:s10KIl connected as shown in figure3)

LM7231/LM723C
Characteristic Symbol Test Conditions Unit
Min Typ Max

VI =12V to 15V 0.Q1 0.1

VI = 12V to 40V 0.1 0.5
Line Regulation 6V o %
TMIN:sTA:sTMAX
0.3
VI =12V to 15V
10= 1mA to 50mA 0.03 0.2
Load Regulation 6Vo TMIN:sTA:sTMAX
0.6 %
10= 1 to 50mA
f = 100Hz to 10KHz, CREF = 0 74
Ripple Rejection RR dB
f = 100Hz to 10KHz, CREF = 5/4F 86
Average Temperature Coefficient of . %/·C
6Vo/6T TMIN:sTA:sTMAl' 0.003 0.Q15
Output Voltage
Short Circuit Current Limit Ise Rse =101l, Vo=O 65 mA
Reference Voltage VREF 6.80 7.15 7.50 V
f = 100Hz to 10KHz, CREF = 0 20
Output Noise Voltage VN /4V rrns
f - 100Hz to 10KHz, CREF - 5/4F 2.5
Long-term Stability VolT 0.1 %/1000HR
Standby Current Drain 10 IL=O, VIN =30V 2.3 4.0 mA
Input Voltage Range VI 9.5 40 V
Output Voltage Range Vo 2.0 37 V
Input-Output Voltage Differential Vo 3.0 38 V

• Note: TMIN = O°C for LM723C TMAX = 70°C for LM723C

= -25°C for LM7231 :; 85°C for LM7231

c8 SAMSUNG SEMICONDUCTOR 301

LM723 LINEAR INTEGRATED· CIRCUIT

Table 1 - Resistor values (KO) for standard output VOltage

Fixed Output Output Adjustable Fixed Output Output Adjustable

Output Applicable :i:5% :i:10% Output Applicable :i:5% :i: 101141
Voltage Figures Voltage Figures
R, Ra R, P, Ra R, '~ R, P, Ra
+3 3,6 4.12 3.01 1.8 0.5 1.2 -6" 5 3.57 2.43 1.2 0.5 0.75
+5 3,6 2.15 4.99 0.75 0.5 2.2 -9 5 3.48 5.36 1.2 0.5 2
+6 3,6 1.15 6.04 0.5 0.5 2.7 -12 5 3.57 8.45 1.2 0.5 3.3
+9 4,6 1.87 7.15 0.75 1 2.7 -15 5 3.65 11.5 1.2 0.5 '4.3
+12 4,6 4.87 7.15 2 2 3 -28 5 3.57 24.3 1.2 0.5 10
+15 4,6 7.87 7.15 3.3 1 3
+28 4,6 21 7.15 5.6 1 2

Note: *Vee must be connected to a +:r.I or greater supply.

Table II - Formulae for Intermediate output voltages

Outputs from + 2 to + 7 volts Foldback Current Limiting

Current Limiting
Fig. 3 IKNEE _ [ Vo ~ + VSENSE (As + ~) I
Vo"[V""X~1 Aae ~ Aoc ~ ILiMIT = VSENSE
A, + R:! Aae
ISHORTCKT = [VSENSE x ~+~l
Roc R.
Outputs from + 7 to + 37 volts Output from - 6 to - 250 volts
Fig. 4,6 Ag.5
Vo = IV"" x A,+A2 ) Vo" [~""x·A'~A21;~ '" ~
A2 .. ,

c8 SAMSUNG SEMiCoNDUCTOR 302

LM723 LINEAR INTEGRATED CIRCUIT

APPLICATION INFORMATION

Basic low voltage regulator (Vo .. 2 to 7V) Basic high voltage regulator (vo,. 7 to 37V)

~r
Fig. 3

Note: R3=R1 0 R21(R1+R2) for ninlmum tamperalur8 drift.

Fig. 4

Note: R1 o R2/(R1+R2)for minimum temperature drift.

I
R3 may be eliminated for minimum component count. R3 may be eliminated for minimum component count.

'JYpIca1 performance ~ical performance

Regulated Output 'obltage .......................................... SV Regulated Output 'obltage............................ :............ 1SV
Line Regulation (4VI=3V) ..................................... O.5mV Line Regulation (4Vi=3V) ..................................... 1.5mV
Load Regulation (4Io .. S0mA) ................................ 1.5mV Load Regulation (4Io-50mA) ................................ 4.5mV

Negative voltage regulator FosItive voltage regulator

(Extenal NPNPass Transistor)
VI

Fig. 5
Fig. 6

lYPIcal performance • ~ical performance

Regulated output 'obltage ................................. :.......-1SV Regulated Output Voltage ...................................... +1SV
Line Regulation (4VI-3V) ........................................ 1mV .Line Regulation (4VI =3V) ..................................... 1.5mV
Load Regulation (4Io-100mA) ................................. 2mV Load Regulation (4Io=1A) ...................................... 1SmV

c8 SAMSUNG SEMICONDUCTOR 303

LM723 LINEAR INTEGRATED QRCUIT

Maximum output current va. voltage drop Current limiting cheracterl8llcs

(

v.
(y)

U I,
111.1211
f - - RSC.101l

~ r-~ g
2r---+-~+++H~---r-+~bH+H
8

I-
.• •• • {!

2r---+-~+++H~---r-+~~+H

"~--~2~-4~~8~8~~~--~2~~4~8~8 0 • 40 80 80 IolmAI
. 'Fig. 7 vw. (y) Fig. 8
Current limiting characterl8llca va. . Load regulation cherecterl8llc8 without
junction temperature current limiting
10 AVtN•

~
........ lmAI ~)
1
f--
T••ooo
r-. ~
0.7

~" -.....;: ~
180
.........
r::::: ~ _ - Ta.25OC

~R
CUmlnt

, --
f - - r--Rae-i 120 -0.'
.~ t---. t-..

--t--'
CUmlnt ......
!
I-- 00;;;;;; Rae-lOll , 80
I i'. -G.2
I ;
~
!
I i
Ii:
40
I i I
I
, , I ; , I i i
I (
,i
I ( I,
I I ! I
U t 0 -u I
-- -•
• FIg. 9 80 ... TJ('C) o • ~g. 1(/'1 .80 1o(mAI

Load regulation charac:terlsllcs with Load regulation cIIerecterIatIc with

current limiting . current limiting
4.VeN.
~)

VO.5V- -
o ..... ""- o
....... ~
111.1211
Rae.101l -
1- -:-
~~
-II1II

-0.1

-0.15
......;

-
~ r--.. Ta.25"C_
...... ~
T._'~ ~
-0.1
~
'\

,
\ '\
.~
VO.5V

-0.2
i-- r-- VI.I211
Rae.101l -o.a \
Ta.l25"C \
-lUll
Ta.
~
-G.4
o 5 10 15 •
Fig. 11
o • 40
Fig. 12
80 80 ,,(mAl

cB SAMSUNG SEMICONDUCTOR 304

LM723 LINEAR INTEGRATED CIRCUIT

LIne regulation - voltage drop Load regulation - voltage drop

lNoN.
~)

0.2
VO-5V
RSC-O 0..
V1_12V
VO-5V
1 1-
IO-lmA Rsc-O
"Vi-~ 10=lmAto~A_

0.1 o
--r-
'- - V -1.1
~
........
........
..
1 -u

Id
(rnA)
111

Quiescent drain current va. Input voltage

IS
Fig. 13
35 Vi.., (VI

IN.
(M/)
5 15

Line transient response

I~PUt~
25
Fig. 14
l1li YIe(VI

IN,
(VI
I
VOJViiiI I--
4
10-0
4 I 2
II
2 o
ra-O'C
........
2

~~
I'
./ -::::: ::::::
ra-25"C
ra-7O"C
o

-
V
/'

V1-12V
........
-
Out ullmltage

-2 --J VO - 5V
lO_lmA
:RSC-O

o
, I
I

10 20 30 5 15 25 t'-l
Fig. 15 Fig. 16
Load transient response Outp.lt Impedance va. frequency
IN. Ao
(M/) ILoadCU~ ( till
VO-5V
~
• II~r
4 V1-12V
I- RSC-O
!\ o
I- IO-SOmA
C~-;
4 II -5
1
8
e
~
CO-l
4

.J '- r- ~ Output~ 2
o
~,jVl-l2V
. \ 0.1 V
•e
-4 ri 10-_
VO 5V
-
'RSC.Q
V
I
4

2
! ! ,
-II l1li1
l!II iii t'-l
100 11( 1CIK
- '(Hz)
Fig. 17 Fig. 18

c8 SAMSUNG SEMICONDUCIOR 305

KA78S40 LINEAR INTEGRATED CIRCUIT

SWITCHING REGULATOR
16 DIP
The KA78S40 is a monolithic switching regulator sub·
system consisting of all the active building blocks
necessary for switching regulator systems.

FUNCTIONS·
• High-currenl,. high·voltage output switch a power tran·
sistor and a diode
• A temperature compensated voltage reference
• A comparator .
• A duty cycle controllable oscillator with an active cur·
rent limit circuit
• Independent operational amplifier.

FEATURES
• Step·up, step-down or inverting switching regulators
• Output current to 1.5A without external transistors
• Output adjustable from 1.3 to 40V ORDERING INFORMATION
.; Operation from 2.5 to 40V Input
• SOdB line and load regulation Operating Temperature
• Low standby current drain 0-70·C
• High gain, high current Indepenclfmt OP Amp.

BLOCK DIAGRAM
COMPARATOR COMPARATOR
NON-INVERTING INVERTING TIMING IpK DRIVER SWITCH
INPUT INPUT GND CAPACITOR SENSE COLLECTOR COLLECTOR
r-----~9r-----~

'------qR
R1

REF;ERENCE INVERTING· . NON- OP AMP OP AMP . SWITCH ANODE· CATHODE

VOLTAGE INPUT INVERTING SUPPLY OUTPUT EMITIER
INPUT
Fig. 1

----
c8SAMSUNG SEMICONDUCTOR 306
/
KA78S40 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)

Characteristic Symbol Value Unit

Power Supply Voltage Vex; 40 V

OP Amp Power Supply Voltage VOP 40 V
Common Mode Input Voltage Range. VICIA -0.3 - Vex; V
Differential Input Voltage Range (Note) VID -30-30 V
Output Short Circuit Duration (OP Amp) Isc Continuous
Current from VREF IREF 10 mA
Voltage from Switch. Collector to GND VCG 40 V
Voltage from Switch Emitter to GND VEG 40 V
'Voltage from Switch Collector to Emitter VCE 40 V
VOltage from Power Diode to GND
Reverse Power Diode Voltage
Current Through Power Switch
Current Through Power Diode
'. VOG
VOR
Isw
10
40
40
1.5
1.5
V
V
A
A
II
Power Dissipation Po 1500 mW
Lead Temperature (Soldering for 10 Sec) TIOad 260 ·C
Operating Temperature Range Too, 0 +70 ·C
Storage Temperature Range T.'g -65 +150 ·C
NOTE: For supply voltage less than 3OV, the absolute maximum voltage is equal to the supply voltage.
ELECTRICAL CHARACTERISTICS
(Vcc=5.0V, VOP Amo= 5.0V, 0·<Ta<70·, unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

General Characteristic
Supply Voltage Vex; 2.5 40 V
Vex; = 5.0V 1.8 3.5
Supply Current Disconnected OP Amp ICCl mA
Vex; = 40V 2.3 5.0
Vex; = 5.0V 4.0
Supply Current Connected OP Amp IcC. mA
VCC= 40V I 5.5
Reference Section I
Reference Voltage VREF IREF=1.0mA 1.180 1.24$ 1.310 V
VCC= 3.0V to 40V
Reference Voltage Line Regulation t;,.V REF 0.04 0.2 mVN
IREF=1.0mA, Ta=25·C
IREF = 1.0mA to 10mA
Reference Voltage Load Regulation t;,.VREF 0.2 0.5 mV/mA
Ta=25·C
Oscillation Section
Vee = 5.0V, Ta=25·C 20 50 p.A
Charging Current ICHG
VCC = 4OV, Ta=25·C 20 70 p.A
Vex;=5.0V, Ta=25·C 150 250 p.A
Discharging Current lOCH
Vex;=40V, Ta=25·C 150 350 p.A

c8 SAMSUNG SEMICONDUCTOR 307

KA78S40 LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS (Continued)'

Characteristic Symbol Test Conditions Min Typ Max Unit

Oscillator Voltage Swing Vose Vee = 5.0V, Ta=25°C 0.5 V

torJtofl t, 6.0 ,.SlpS
Current Limit Section
Current Limit Sense Voltage VSEN Ta=25°C 250 350 mV
Output Switch Section
Isw = 1.0A, step-down 1.1 1.3 V
Output Saturation Voltage VSAT
Isw= 1.0A, step-up 0.45 0.7 V
Ic=1.0A, VCE= 5.0V,
Output Transistor hFE hFE 70
Ta=25°C
Output Leakage Current I'eak VOUT = 4OV, Ta=25°C 10 nA
Power Diode
Forward Voltage Drop Vo lo=1.0A 1.25 1.5 V
Diode Leakage Current I'eak Vo=40V, Ta=25°C 10' nA
Comparator
Input Offset Voltage V,o VCM=VREF 1.5 15 mV
Input Bias Current IB ,VCM'=VREF 35 200 nA
Input Offset Current 1'0 VCM=VREF 5.0 75 nA
Common Mode Voltage Range VCM Ta=25°C 0 Vcc-2 V
Vcc = 3.0V to 40V,
Power Supply Rejection Ratio PSRR 70 96 dB
Ta=25°C
Operational Amplifier
Input Offset Voltage V,o VcM =2'.5V 4.0 15 mV
Input Bias Current I'B VCM=2.5V 30 200 nA
Input Offset Current 1'0 VCM=2.5Y 5.0 75 nA
RL=2.0 kG to GND,
Voltage Gain (Positive) AVOL+ 25 250 V/mV
Vo= 1.0 to 2.5V. Ta= 25°C
RL = 2.0 kG to V + OP Amp
Voltage Gain (Negative) VVOL- 25 250 V/mV
Vo=1.0 to 2.5V, Ta=25°C
Common Mode Voltage Range VCM ' Ta=25°C 0 Vcc-2 V
Common Mode Rejection Ratio CMRR VCM=O to 3.0V. Ta=25°C 76 100 dB
Power Supply Rejection Ratio PSRR Vop =3.0 to 40V. Ta=25°C 76 100 dB
Output Source Current IsouR Ta=25°C 75 150 mA
Output Sink Current IS'NK Ta=25°C 10 35 mA
Slew rate S.R Ta=25°C 0.6 V/,.S
Output Low Voltage VOL IL= -5.0mA. Ta=25°C 1.0 V
Output High Voltage VOH IL=50mA, Ta=25°C Vop-3.0 V

c8 SAMSUNG SEMICONDUCTOR 308

KA78S40 LINEAR INTEGRATED CIRCUIT

APPLICATION INFORMATION
Design Formulas

Characteristic Step Down Step Up Inverting Unit

21 VOUT+VO-Vsa• 21 VIN+!VOUT! +VO-Vsa'

Ipk 2IoUT(Max) QUT(Max)· VIN - Vsat OUT(Maxj- VtN - Vsat A

Rsc 0.33/1 pk 0.33Jl pk 0.33/1 pk !l

~ VOUT+ Vo VOUT+VO-VIN IVOUTI + Vo

toff VIN - Vsa• - VOUT VIN - Vsa. VIN - V.a•

L VOUT + Vo. loff VOUT+VO-VIN I !VoUTI + Vo. I~ff I'H

IPk I'pk • off Ipk .

~ ,. I~k· L I~k. L
toff I'S

II
VOUT+ Vo VOUT + Vo - VIN IVOUTI + Vo
CT (I'F) 45 x 10- 5 loff (I's) 45 x 10- 5 toff (I's) 45 x 10- 5 loff (}.<S) I'F
I~k· (Ion +10ff) .(Ipk -louT)2. toff (I~k - IOUT)2. loff
Co I'F
8 V'IPPI. 2 Ipk • Vnpple 2 I pk • Vripple

Efficiency
VIN-V.at+Vo.
VIN
VOUT
VOUT+ Vo
VIN - Vsat •
VIN
VOUT
VOUT + Vo - V••t ---.
VIN - Va• t
VIN
IVOUTI
VOUT+VO
IIN(Avg)
(Max load ~. VOUT+ Vo ~ ~. IVOUTI + Vo
A
condilion)
2 VIN - V••t + Vo 2 2 VIN + IVOUT I + Vo - Vs•t

RsC
0.3311
VIN o---r-¥o/tr---..,------.-----.
25 V

-...,
I
I

Q1

I'A78840 +-_--'

Fig. 2. Typical step·down operation (Ta =25°C)

~L~3~OO~I'~H~-+---~~UT

R1 55 k
R2
12 k

c8 SAMSUNG SEMICONDUCTOR 309

KA78540 ,LINEAR INTEGRATED CIRCUIT

VIN 10 V RsC 0.50

r. vcfCJF __13___ 1~~5mH -1

I BIAS
I 02
I '
I 0
I L...::i--!'!'..J
I
I
I
I
I
I
[
"--- t ~A78S40 ~__---J

01

Fig. 3. Typical step·up operation (Ta =25°C)

VOUT: 25V
, lOUT: 50mA
Rl
R2 230k
12 k

IBIAS 390pF l
I I
I I
I
I I
I I
I I
I I
,i 011
I I
I I
I I
I
~A78S40 +--__----' II
I
01 I Fig. 4. Typical Inverting ,operation (Ta = 25°C)

L-_l~2~k-r____________-+~~-r~~IO~UT:l00mA
~J,
+--4 VOUT: -15V

144K

c8 SAMSUNG SEMICONDUCTOR 310

KA78S40 LINEAR INTEGRATED CIRCUIT

TYPICAL CHARACTERISTICS

Fig. 5. Cr V. Ion Fig. 6. VrEF V. TJ

470 1,220
VIN=~V VIN~5V
T,,=25-C
L 1,218
\
1\
V -- --
1,216

\
II.
c
47

V >
I
1,214

1,212

iil1,210
"- -
V
I
U >

I
1,208
4.7

/
1,208

1,204

II 1,202

0.47 1,200
1 10 100 1000 -50 -25 25 50 75 100 12E

Fig. 7. Idlscharge V. VIN Fig. 8, V_ V. VIN

250 400
Tl=25"c J T,I=25'b

--
/'" 350

V
. . .V
./
=e
I

>
1300
- ~~

250

150 200
o 10 20 30 40 50 o 10 20 30 40 50
VIN-V

.c8 SAMSUNG SEMICONDUCTOR 311

KA78TXXC/KA78TXXAC SERIES LINEAR INTEGRATED CIRCUIT

T()'220

3A POSIT.IVE VOLTAGE REGULATOR

This family of fixed voltage regulators are monolithic integrated
c"ircuits capable of driving loads in excess of, 3.0 amperes. These three-
terminal regulators employ Internal current limiting, thermal shutdown,
and safe-area compensation. Devices are available with improved
specifications, including a 2% output voltage tolerance on IA- suffix 5,
12 and 15 volts device types.
Although designed primarily as fixed voltage regulators, these devices
can be 'Used with external components to obtain adjustable voltages
and currents.

FEATURES
• Output current In excess of 3_0 ampere
• Output transistor safe-area compensation
1: Input 2: GND 3: Output
• Power dissipation: 25W (To-220)
• Internal short-circuit current limiting ORDERING INFORMATION
• Internal thermal overload protection
• Output voltage offered in 2% and 4% tolerance Device Package Operating Temperature
(2% regulators are available in 5, 12 and 15 volt devices)
• No external components required KA78TXXCT
TO-220
• Thermal regulation Is specified KA78TXXACT
• Output voltage of 5; 6; 8; 12; 15; 18; 24V o-125°C
KA78TXXCH
TO-3P
KA78TXXACH
BLOCK DIAGRAM

INPUT SERIES
PASS
r-~UT

I I
1 ELEMENT 3

CURRENT ,SOA
GENERATOR PROTECTOR

I I

STARTING REFERENCE ERROR

I
CIRCUIT j-- VOLTAGE AMPLIFIER

"

THERMAL
PROTECTION
-

I GND

'cR SAMSUNG SEMICONDUCTOR 312

KA78TXXC/KA78TXXAC SERIES LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Input Voltage (5.0V -12V) V'N 35 Voc

(15V -24V) 40 Voc
Power Dissipation Po Internally limited
Thermal Resistance, Junction to Air
9 JA 65 °C/W
Tc=25°C
Thermal Resistance, Junction to Case 9 JC 2.5 °C/W
Operating ·Temperature Range Top. o to +125 °C
Storage Temperature Range TS'g -65 to + 150 °C

KA78T05C, KA78T05AC ELECTRICAL CHARACTERISTICS

(V,N=10V, 10=3.0A, T,=O°C to 125°C, PoSPmax, unless otherwise specified) .

KA78T05AC KA78T05C
II
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max

5mAs los3.0A, Tj = 25°C 4.9 5 5.1 4.8 5.0 5.2

Output Vortage Vo 5mAslos3A; Voc
4.8 5 5.2 4.75 5.0 5.25
7.3VocsV'Ns20Voc,5mAslos2A
7.2VocSV'NS35Voc, 10=5mA, Tj =25°C
7.2VocSV'NS35V, 10= 1.0A, Tj = 25°C
Line Regulation 6Vo 3.0 10 3.0 25 mV
7.5V sV,Ns20V, 10 = 2.0A
8.0VSV'NS12V,lo=3.0A
5niASloS3.0A, T, = 25°C 10 25 10 30 mV
Load Regulation 6Vo I
5mAsloS3.0A 15 50 15. 80 mV
Pulse = 10mS, P = 20W,
Thermal Regulation Regthe 0.001 0.01 0.002 0.03 %VoIW
Ta=25°C
5mAslos3A, TJ= 25°C 3.5 5.0 3.5 5.0 mA
Quiescent Current I.
5mAslos3A 4.0 6.0 4.0 6.0 mA
7.2VSV'NS35V, 10 = 5mA,
Quiescent Current
Change
61d
Tj = 25°C;
7.5VSV'Ns20V,lo=2A;
. 0.1 0.5 0.1 0.8 mA
5mAslos3A
Ripple Rejection RR 8VSV'NS18V, f=120Hz, 10=2.0A 68 75 65 75 dB
Dropout Voltage Vo 10 = 3A, T,=25°C 2.2 2.5 2.2 2.5 Voc
Output Noise Voltage VN 10HzSfS100KHz, Tj =25°C 10 10 ILVNo
Output Resistance Ro f::;;1.0KHz 2.0 2.0 mil
Short Circuit Current
Isc V'N=35V, Tj =25°C 1.5 2.5 1.5 2.5 A
Limit
Peak Output Current lpeak TJ=25°C 5.0 5.0 A
Average Temperature
Coefficient of 6Vol6T 10 = 5.0mA 0.2 0.2 mV/oC
Output Volt~ge

.c8 SAMSUNG SEMICONDUCTOR 313

KA78TXXC/KA78TXXAC SERIES LINEAR INTEGRATED CIRCUIT

KA78T06C ELECTRICAL CHARACTERISTICS

(VIN=11V, lo=3.0V, Tj=O°C to 125°C, PoSPmax, unless otherwise specified)

KA78T06C
Characteristic Symbol Test Conditions Unit
Min Typ Max

5.0mAslos3A, Tj = +25°C 5.75 6.0 6.25

Output VdltalJe Vo 5.0mAslos3A; 5.7 6.0 6.3 V
8.3VSVINs21V,5mAslos2A
8.25VsVINS35V lo=5.0mA, Tj= +25°C; 4.0 30
8.25VSVINS35V lo=1.0A, Tj = +25°C;
Line Regulation tJ.Vo mV
8.6VSVINS21V lo=2.0A
9.0VSVINS13V lo=3.0A
5mAslos3A, Tj = +25°.C 10 30 mV
Load Regulation tJ.Vo
5mAs los3A 15 80
Thermal Regulation Regthe Pulse=10mS, P=20W, Ta=25°C 0.002 0.03 OfoV"JW
5mAslos:3A, Tj :; +25°C 3.5 5.0
Quiescent Current Id mA
5mAslos3A 4.0 6.0
8.25VSV1N S35V, lo=5mA, Tj = + 25°C; 0.1 0.8
Quiescent 'Current Change tJ.ld 8.6VSVINS21V,lo:;2A; mA
5mAs los3.0A
Ripple Rejection RR 9VSV1N S19V, f=120Hz, lo=2A 61 71 dB
Dropout Voltage Vo lo=3A, Tj = +25°C 2.2 2.5 V
Output Noise Voltage VN 10HzSfS100KHz, Tj = +25°C 10 ,.VNo
Output Resistance Ro f= 1.0KHz 2.0 mO
Short Circuit Current Limit Isc V1N = 35V, Tj = + 25°C 1.5 2.5 A
Peak Output Current lpeak Tj = +25°C 5.0 A
Average Temperature
Cofficient of Output 6VoItJ.T Jo=5.0mA 0.3 mV/oC
Voltage ,

.c8 SAMSUNG SEMICONDUCTOR . . 314

KA78TXXC/KA78TXXAC SERIES LINEAR INTEGRATED CIRCUIT

KA78T08C ELECTRICAL CHARACTERISTICS

(V1N =14V, 10 = 3.0V, Tj=O°C to 125°C, PosPmax, unless otherwise specified)

KA78T08C
Characteristic Symbol Test Conditions Unit
Min Typ Max

5.0mAslos3A, Tj = +25°C 7.7 8.0 8.3

Output Voltage Vo 5.0mAslos3A; I Voc
7.6 8.0 8.4
10.4VsVu·.rs23V,5mAslos2A
10.:,wsV1N s35V, lo=5mA, Tj = +25°C 4.0 35
10.3VSV1N S35V, lo=1.0A, TI = +25°C
Line Regulation I::.Vo mV
10.7VSVINS23V,lo=2.0A
l1VSV1N S17V, 10 = 3.0A
5mAslos3A, Tj = +25°C 10 30

I
Load Regulation I::.Vo mV
5mAslos3A 15 80
Therrnal Regulation Regthe Pulse=10mS, P=20W, Ta=25°C 0.002 0.03 OfoVJW
5mAslos3A, T1= +25°C 3.5 5.0
Quiescent Current I. mA
5mAs los3A . 4.0 6.0
10.3VsV1N S35V, 10 = 5mA, TI = + 25°C 0.1 0.8
QuieScent Current Change 1::.1. 10.7VsVINS23V,lo=2A mA
5mAs los3A
Ripple Rejection RR l1VsVINs21V, f=120Hz, 10=2A 61 71 dB
Dropout Voltage Vo lo=3A, TI = +25°C 2.2 2.5 Vrx;
Output Noise Voltage VN 10HzSfsl00KHz, TI = +25°C 10 p.VlVo
Output Resistance R9 f= 1.0KHz 2.0 mO
Short Circuit Current Limit Isc V1N =35V, TI = +25°C 1.5 2.5 A
Peak Output Current 1- Tj = +25°C 5.0 A
Average Temperature
Cofficient of Output . I::.Vo/I::.T 10=5.0mA 0.3 mV/oC
Voltage

ciS SAMSUNG SEMICO~DUCTOR 315

KA78TXXC/KA78TXXAC SERIES LINEAR INTEGRATED CIRCUIT

KA78T12C, KA78T12AC ELECTRICAL CHARACTERISTICS

(VIN = 19V, 10 = 3.0A, T, = O°C to 125°C, PoS Pm.,., unless otherwise noted)

KA78T12AC KA78T12C
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max

5mAslos3A, Tj = 25°C . 11.75 12 12.25 11.5 12 12.5

Output Voltage Vo Voe
5mAslos3A; 5mAslos2A, 14.5VsVINs27V 11.5 12 12.5 11.4 12 12.6
14.5VocSVINs35Voc, 10 = 5mA, Tj = + 25°C; 6.0 18 6.0 45
14.5VocsVINs35Voc, 10 = 1.0A, Tj = + 25°C;
Line Regulation £::"Vo mV
14.9Voc SV,N s27Voc, 10 = 2.0A;
16VoeSVINS22Voe, 10 = 3.0A
5mAslos3A, Tj = +25°C 10 25 10 30
Load Regulation £::"Vo mV
5mAs los3A 15 50 15 80
Thermal Regulation Regth Pulse=10mS, P=20W, Ta=25°C 0.001 0.01 0.002 0.03 %VJW
5mAslos3A, Tj = + 25°C 3.5 5.0 3.5 5.0
Quiescent Current Id mA
5mA,sIos3A 4.0 6.0 4.0 6.0
14.5VoeSVINS35Voe, 10 = 5mA, TI =25°C; 0.1 0.5 0.1 0.8
Quiescent Current
£::"Id 14.9Voc S VIN S 27Voc, 10 = 2A; rnA
Change
5.0mAs los3.0A
15Voc SVIN s25Voc,
Ripple Rejection RR 61 67 57 67 dB
f = 120Hz, 10 = 2.0A
Dropout Voltage Vo 10 = 3A, Tj = +25°C 2.2 2.5 2.2 2.5 Voc
Output Noise Voltage VN 10Hzsfsl00KHz, Tj = +25°C 10 10 p.VNo
Output Resistance Ro f = 1.0KHz 2.0 2.0 mil
Short Circuit Current
Ise VIN =35V, T, = +25°C 1.5 2.5 1.5 2.5 A
Limit
Peak Output Current Ipeak TI = +25°C 5.0 5.0 A
Average Temperature
Coefficient of £::,.VoI£::,.T 10 = 5.0mA 0.5 0.5 mV/oC
Output Voltage

c8 SAMSUNG SEMICONDUCTOR 316

KA78TXXC/KA78TXXAC SERIES LINEAR INTEGRATED CIRCUIT

KA78T15C, KA78T15AC ELECTRICAL CHARACTERISTICS

(V'N = 23V, 10 = 3.0A, TI = O°C to 125°C, PoS Pmax , unless otherwise noted)

KA78T15AC KA78T15C
Characteristic Symbol Test CondItions Unit
Min Typ Max Min Typ Max

5mAslos3A, T,= +25°C 14.7 15 15.3 14.4 15 15.6

Output Voltage Vo 5mAs los3A; VDC
14.4 15 15.6 14.25 15 15.75
17.5Voc sV'NS30V DC, 5mAs los2A
17.6VSV'NS40V, 10=5mA, TI = +25°C
17.6V SV'Ns40V, 10 = lA, T, = + 25°C;
Line Regulation t:.Vo 7.5 22 7.5 55 mV
18VSV'Ns30V,lo=2.0A;
20V S V'N S 26V, 10 = 3.0A
5mAslos3A, T,= +25°C 10 25 10 30

I
load Regulation t:.Vo mV
5mAslos3A 15 50 15 80
Thermal Regulation Regth Pulse=10mS, P=20W, Ta=25°C 0.001 0.Q1 0.002 0.03 %VofW
5mAslos3A, T,= +25°C 3.5 5.0 3.5 5.0
Quiescent Current Id mA
5mAs los3A 4.0 6.0 4.0 6.0
17.6VSV'NS40V, 10=5mA, T,= +25°C;
Quiescent Current
t:.ld 18VsV'Ns30V,lo=2A; 0.1 0.5 0.1 0.8 mA
Change
5mAs los3A
18.5V DC S V'N S 28.5V DC,
Ripple Rejection RR 60 65 55 65 dB
f = 120Hz, 10 = 2.0A
Dropout Voltage V6 10=3A, T;= +25°C 2.2 2.5 2.2 2.5 Vpc
Output Noise Voltage VN 10Hzsfsl00KHz, TI = + 25°C 10 10 p.vNo
Output Resistance Ro f = 1.0KHz 2.0 2.0 mO
Short Circui,t Current
Isc V,N=40V, T,= +25°C 1.0 2.0 1.0 2.0 A
Limit
Peak Output Current lpeak 1',= +25°C 5.0 5.0 A
Average Temperature
Coefficient of t:.Volt:.T 10 = 5.0mA 0.6 0.6 mVloC
Output Voltage

c8 SAMSUNG SEMICONDUCTOR 317

KA78TXXC/KA78TXXAC SERIES LINEAR INTEGRATED CIRCUIT

KA78T18C ELECTRICAL CHARACTERISTICS

(VIN= 27V, 10 = 3.0V, TJ=O°C to 125°C, PosPmax, unless otherwise specified)

KA78T18C
Characteristic Symbol Test Conditions Unit
Min Typ Max

5.0mAslos3A, T;= +25°C 17.3 18 . 18.7

Output Voltage Vo 5.0mAslos3A; Vric
17.1 18 18.9
2O.6VSVINs33V,5mAslos2A
2O.7VsV1N S40V, 10=5mA, TJ= + 25°C; 9.0 80
2O.7VsV1N:S!40V, 10=1A, TJ= +2SoC; mV
Line Regulation l'1Vo
21.2VsVINS~V, 10=2.0A
24VSV1N S30V,lo=3A
5mAslos3A, T; = + 2SoC 10 30
Load Regulation l'1Vo mV
SmAslos3A 1S 80
Thermal Regulation Regthe Pulse=10mS, P=20W, Ta=2SoC 0.002· 0.03 OfoVJW
SmAslos3A, TJ= + 2SoC 3.S S.O
Quiescent Current Id mA
SmAslos3A 4.0 6.0
2O.7VSV1N S40V, 10=SmA, TJ= +2SoC; 0.1 0.8
Quiescent Current
l'1ld 21.2VsVINS33V,lo=2.oA; mA
Change
SmAslos3.0A
Ripple Rejection RR 22VSV1N S32V, f=120Hz, 10=2.0A 54 64 dB
Dropout Voltage Vo 10=3A, TJ= +2SoC 2.2 2.S. Voc
Output Noise Voltage VN 10Hzsfs100KHz, TJ= +2SoC 10 ,.VNo
Output Resistance Ro f = 1.0KHz 2.0 mO
Output Circuit Current
Isc V1N =40V, T;= +2SoC 1.0· 2.0 A
Limit
Peak Output Current lpeak TJ= +2SoC S.O A
Average Temperature
Coefficient of l'1Vol!::..T 10 = S.OmA 0.7 mV'oC
Output Voltage

c8 $AMSUNG SEMICONDUCTOR 318

 .'
KA78TXXC/KA78TXXAC SERIES LINEAR INTEGRATED CIRCUIT

KA78T24C ELECTRICAL CHARACTERISTICS

(VIN =33V, 10 = 3.0A, T)=O°C to 125°C, PosPmax, unless otherwise specified)

KA78T24C
Characteristic Symbol Test Conditions Unit
Min Typ Max

5.0mAslos3A, Ti= +25°C 23 24 25

Output Volt~e Vo 5.0mAslos3A; Vee
22.8 24 25.2
27.3VsVINs39V,5mAslos2A
27VSVINS40V, 10=5mA, Ti= + 25°C; 12 90
27VSVIN S40V, 10=1.0A, T)= +25°C;
Line Regulation f::,Vo mV
27.5VSVINS39V, 10 = 2.0A;
30VSVIN S36V, 10 = 3.0A
5mAslos3A, Ti= +25°C 10 30
Load Regulation f::,Vo mV

Thermal Regulation

Quiescent Current
Regthe

Id
5mAslos3A
Pulse=10mS, P=20W, Ta=2SoC
5mAslos3A, T)= +25°C
5mAslos3A
27VsVI~S.40V,
10=SmA, Ti= +25°C;
15
0.002
3.5
4.0
0.1
80
0.03
5.0
6.0
0.8
%Vo/W

mA
II
Quiescent Current
f::,l d 27.5VSVINS39V,lo=2A; mA
Change
SmAslos3A
Ripple Rejection RR 28VSVIN S38V, f=120Hz, 10=2.0A 51 61 dB
Dropout Voltage Ve 10 = 3A, Ti= +25°C 2.2 2.5 Vee
Output Noise yoltage VN 10Hzsfs100KHz, Ti= +25°C 10 p.VlVo
Output Resistance Ro f=1.0KHz 2.0 ma
Short Circuit Current
Isc ' VIN =40V, T)= +2SoC 1.0 2.0 A
Limit
Peak Output Current lpeak TI = +2SoC 5.0 A
Average Temperature
Coefficient of f::,Vo/f::,T 10 = 5.0mA 1.0 mV/oC
Output Voltage

c8 SAMSUNG SEMICONDUCTOR 319

KA78TXXC/KA78TXXAC SERIES LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS

Fig. 1 TEMPERATURE STABILITY Fig. 2 OUTPUT IMPEDANCE
1.02 10"

v:,-Vo.\ov Vo=5.0V
w = mOmA -
1I---~T:~'~~
lOUT

~ Co=O
TJ -25°C ~

~ 1.00 .--. !'-"

S ':"" 1/
f'.. !"'.... I
Ioz J
0.98
10- 4
-10 30 70 110 150 10 100 1K 10K tOOK 1M 10M 100M
TJ • JUNCTION ~EMPERATURE (0C) I, FREQUENCY (Hz)

Fig. 3 RIPPLE REJECTION V, FREQUENCY Fig. 4 RIPPLE REJECTION V, OUTPUT CURRENT

100 100

r- !oo;=JmA I
iii 80 iii 80
:!1. :!1.
z lOUT =3.0A ~ z
~ Q

~
0
w
Ul
a: 60 1 Ul
a:
.w
~

ii:
- r
Vo =5.0V
V1N =10V \ ~ 60
Vo=5.0V

'"
a:
40
Co=O
. TJ =25°C
\ ii:

'"
a: rCo=O
VIN= 10V

f=120Hz
TJ=25°C
11 40

20
1.0 10 100 1K 10K lOOK
1 1M 10M 100M
30
0.01
III 0.1 1.0 10
f, FREQUENCY (Hz) JOUT, OUTPUT CURRENT (A)

Fig. 5 QUIESCENT CURRENT V, INPUT VOLTAGE Fig. 6 QUIESCENT CURRENT V. OUTPUT CURRENT
4.0 5.0

TJ -25°C- j-----

C 3.0 f C
4.0

g
...z
w
a:
II g
!<w
a: 3.0
TJ=25°C

a: a:
:> :>
...0z 2.0
...0z
w
0
[fi
I w
0
In
2.0

I
W
5 5
0 0
.l 1.0 .l VIN-VO= 5.0V

I Vo =5.0V

i<>rrT A-
1.0

ill
V 10 20 30 40
III
0.01 0.1 1.0 10
VIM! INPUT VOLTAGE (V1IJ fo~, OUTPUT CURRENT (A)

c8 SAMSUNG SEMICONDUCTOR 320

KA78TXXC/KA78TXXAC SERIES LINEAR INTEGRATED CIRCUIT

Fig. 7 DROPOUT VOLTAGE Fig. 8 PEAK OUl'PUT CURRENT

~ 2.5 B.O

~.
~ 2.0
is
IU

~>
~

r- t--
loor=3.0A

...g
.."
Z
IU

..."
6.0
- -
,... r- ~
'\ ~
-r- r-.. II"" r-
(J

t--
r- t-- ~ r--
1.5 10UT=1.0A_ 4.0

""'~~
.......
Ie r0-
O"", =0:;;::--
'""'-
"
0

.
'"
~

~
1.0
J 2.0 1"'-" TJ=oec -
.;r
.j
"~ I
TJ=25°C
TJ =125 G C
o
oj 0.5 0 J.

I
10 30 70 110 150 0 10 30 40
T,. JUNCTION TEMPERATURE ('C) Vw-V.. INPUT.()UTPUT VOLTAGE (V.,)

Fig. 9 LINE TRANSIENT RESPONSE Fig. 10 LOAD TRANSIENT RESPONSE

IU O.B
CO.
~ I, ,I 1
r-~o=5.OV
.. I

n
0.6 Vo=5.0V -
0 V,N =10V
10IJT=150mA
~~ 0.4 00=0 _ 00=0
~Z r-i-,=25'C
"0
5!;i
TVJ =25·0
\
r
0.2
.jiii 1\
<1<>

-0.2 IV
-·0.4
IU

"~ -0.6
g
.. ~
1.0 1
~IU
;r" 0.5 II II
J~
<16
10 20
t, TIME",")
30 40
~ TIME",") '"
Fig. 11 MAXIMUM AVERAGE POWER DISSIPATION
40

MAXIMUM AMBIENT
TEMPERATURE

50 75
TA• AMBIENT TEMPERATURE (Oe)

c8 SAMSUNG SEMICONDUCTOR 321

KA78TXXC/KA78TXXAC SERIES LINEAR INTEGRATED CIRCUIT

APPLICATION INFORMATIONS
The KA78TOO,A Series of fixed voltage regulators are designed with Thermal Overload Protection that shuts down
t~e circuit when subjected to an excessive power overload condition, Internal Short·Circuit Protection that limits
the maximum current the circuit will pass, and Output Transistor Safe·Area Compensation that reduces the output
short:circuit current as the voltage across the pass transistor is increased. ,
In many low current applications, compensation capacitors are not required. However, it is recommended that
the reg),Jlator input be bypassed with a capacitor If the regulator is connected to the power supply filter with long
wire lengths, or if the output load capacitance is large. An input bypass capacitor should be selected to provided
good high·frequency characteristics to insure stable operation under all load conditions. A O:33"F or larger tantalum,
mylar, or other capacitor having low internal impedance at high frequencies should be chosen. The bypass capacitor
should be mounted with the shortest possible leads directly across the regulator's "nput terminals. Normally good
construction techniques should be used to minimize ground loops and lead resistance drops since the regulator
has no external sense lead. '

Fig. 12-CURRENT REGULATOR Fig. 13-ADJUSTABLE OUTPUT REGULATOR

Input
R Output
Constant
'------''--oCurrent to
t;: Grounded Load
The KA78T05 regulator can also be used as a current
source when connected as above. In order to minimize
10K,
dissipation, the KA78T05 is chosen in this application.
Resistor R determines the current as follows:

Vo, 8.0V to 20V

V1N - Vo~2.5V
6I B=0.7mA over line, load and temperature Changes
IB=3.5mA The addition of an operational amplifier allows
adjustment to higher or intermediate values while
For example, a 2·ampere current source would require
retaining regulation characteristics. The, minimum
R to be a 2.5 ohm, 15W resistor and the output voltage
voltage obtainable with this arrangement is 3.0 volts
compliance would be the input voltage less 7.5 volts.
greater than the regulator voltage.
Fig. 14-CURRENT BOOST REGULATOR Fig. 1S-CURRENT BOOST WITH SHORT·
2N4398 pr Equiv.. CIRCUIT PROTECTION
Input Input ~---.-~_'t-£

J 1.0"F

xx = 2 digits of type number indicating voltage. XX = 2 digits of type number indicating voltage.
The KA78TOO,A series can be current boosted with a The ,circuit of Figure 18 can be modified to provide
PNP transistor. The 2N4398 provides current to 15 supply protection against short circuits by adding a
amperes. Resistor R in conjunction with the VBE of short·circuit sense resistor, Rsc, and an additional
the PNP determines when the pass transistor begins PNPtransistor. The current sensing PNP must be able
conducting; this circuit is not short-circuit proof. Input· to handle the short-circuit current of the three·terminal
output differential voltage minimum is increased by regulator: Therefore, an eight·ampere power transistor
the VBE of the pass transistor. is specified.

c8 SAMSUNG SEMICONDUCTOR 322

MC78XXJMC78XXA LINEAR INTEGRATED CIRCUIT
-------------,
3-TERMINAL 1A POSITIVE TO-220
VOLTAGE REGULATORS
The MC78XX/MC78XXA series of three·terminal positive regulators are
available in TO·220 package and with several fixed output voltages,
making it useful in a wide range of applications. These Regulators can
provide local oncard regulation, eliminating the distribution problems
associated with single pOint regulation. Each type employs internal
current limiting, thermal shut-down and safe area protection, making
it essentially indestructible. If adequate heat sinking is provided, they
'can deliver over 1A output current. Although designed.primarily as fixed
voltage regulators, these devices can be used with external components
to obtain adjustable voltages and currents.

FEATURES
•
•
•
•
•
Output Current up to 1.5A
Output voltages of 5; 6; 8; 8.5; 9; 10; 11; 12; 15; 18; 24V
Thermal Overload Protection
Short Circuit Protection
Output Transistor SOA P~ctlon
L -_ _1:

ORDERING INFORMATION
_ Input
_ 2: GND 3: Output
II
Device Package OPerating Temperature .
MC78XXIT TO·22O - 40°C - + 125°C
MC78XXCT TO·22O
BLOCK DIAGRAM O°C _+125°C
MC78XXACT TO·220

IN PUT SERIES OUTPUT

PASS
1 ELEMENT 3

I
...... ~
CURRENT SOA
GENERATOR PROTECTION

SllIRTING REFERENCE ERROR

1
CIRCUIT
- VOLTAGE AMPLIFIER

THERMAL
'PROTECTION I---

I GN o

2
Fig. 1

c8 SAMSUNG S.EMICONDUCTOR 323 .

MC78XX/MC78XXA LINEAR INTEGRATED CIRCUIT

SCHEMATIC DIAGRAM

.---.------?-----?--~-_,_--_r_--oIN

>-~-~-+---4--~-_oOUT .

R20

R19

Fig. 2

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Input Voltage (for Vo=5V to 18V) Vi 35 V

. (for Vo = 24V) Vi 40 V
Thermal Resistance Junction-Cases 9 JC 5 'CIW
Thermal Resistance Junction-Air 9JA 65 ·CIW
Operating Temperature Range MC78XXI Topr -40-+125 ·C
MC78XXC/AC 0-+ 125 ·C
Storage Temperature Range Tstg -65- +150 ·C

c8 SAMSUNG SEMICONDUCTOR 324

MC78XX1MC78XXA LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7805

(Refer to test circuit, Tm'n<T,<Tmax, 10 = 500mA, V, = 10V, C, = 0.33/LF, Co = 0.1/LF, unless otherwise specified)

MC78051 MC7805C
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max

TJ=25°C 4.8 5.0 5.2 4.8 5.0 5.2

Output Voltage Vo 5.0mA:s 10:S 1.0A, PD:s 15W V

V,=7V to 20V 4.75 5.0 5.25
V,=8V to 20V 4.75 5.0 5.25
V,=7V to 25V 3.0 100 3.0 100
Line Regulation /::,Vo TJ=25°C mV
V,=8V to 12V 1.0 50 1.0 50
10 = 5.0mA to 1.5A 15 100 15 100

II
Load Regulation /::,Vo TJ=25°C mV
10 = 250mA to 750mA 5 50 5 50
Quiescent Current Id Tj =25°C 4.2 8 4.2 8 mA
10=5mA to 1.0A 0.5 0.5
Quiescent Current Change /::, Id V,=7V to 25V 1.3 mA
V,=8V to 25V 1.3
Output Voltage Drift /::,Vo//::,T 10=5mA -1.1 -1.1 mV/oC
Output Noise Voltage V. f = 10Hz to 100,KHz T, = 25°C 40 40 /LV
Ripple f = 120Hz
RR 62 78 62 78 dB
Rejection V,=8 to 18V
Dropout Voltage VD 10=1A, TJ=25°C 2 2 V
Output Resistance Ro f=1KHz 17 17 mO
Shon Circuit Current Isc V,=35V, TJ=25°C 750' 750 mA
Peak Current Ipeak TJ=25°C 2.2 2.2 A

,* Tm,n<T,<Tmax
MC78XXI: Tm,,= -40°C, Tmax=125°C
MC78XXC, Tmin = O°C, Tmax = 125°C
* Load and line regulation are specified at constant junction temperature changes in Vo due to heating
effects must be taken into account separately pulse testing with low duty is used.

c8 SAMSUNG SEMIC~NDUcrOR 325

MC78XX1MC78XXA LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7806

(Refer to test circuit, Tm;n<Tj<Tmax, 10 = 5OOmA, V; = 11V, Ci = 0.33jLF, Co= 0.1jLF, unless otherwise specified)

MC78061 MC7806C
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max

T1=25°C. 5.75 6.0 6.25 5.75 6.0 6.25

Output Voltage Vo 5.0mA:sI~:s1.0A, Po:s15W V

V; = 8.0V to 21V 5.7 6.0 6.3
Vi = 9.0V to 21V 5.7 6.0 6.3
V;=8V to 25V 5 120 5 120
Line Regulation 6Vo Tj =25°C mV
Vi =9V to 13V 1.5 60 1.5 60
10=5mA to 1.5A 14 120 14 120
Load Regulation 6Vo T1=25°C mV
10 = 250m A to 750mA 4 60 4 60
Quiescent Current . Id TI=25~C 4.3. 8 4.3 8 mA
10=5mA to 1A 0.5 0.5
Quip-scent Current Change 61d Vi =8V to 25V 1.3 mA
V; =9V to 25V 1.3
Output Voltage Drift 6VoI6T 10=5mA -0.8 -0.8 mV/OC
Output Noise Voltage VN f = 10Hz to 100KHz Tj = 25°C 45 45 JLV
Ripple f= 120Hz
RR 59 75 59 75 dB
Rejection Vi =9 to 19V
Dropout Voltage Vo lo=1A, Tj =25°C 2 2 V
Output Resistance Ro f=1KHz 19 19 mO
Short Circuit Current Ise Vi = 35V, Tj =25°C 550 550 mA
Peak Current lpeak TI=25°C 2.2 2.2 A

• Tmin<TI<Tmax
MC78XXI: Tmin= -40°C, Tmax =125°C
MC78XXC, Tmin=O°C, Tmax=125°C
• Load and line regulation are specified at constant junction temperature changes in Vo due to heating
effects must be taken into account separately pulse testing with Jow duty is used .

.c8 SAMSUNG SEMICONDUCTOR 326

MC78XX1MC78XXA LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7808

(Refer to test circuit, Tmln<T,<Tmax, 10=500mA, V,=14V, CI=0.33"F, Co=0.1"F, unless otherwise specified)

MC78081 MC7808C
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max

Tj=25 DC 7.7 8.0 8.3 7.7 8.0 8.3

Output Voltage Vo 5.0mAslos1.0A, PoS15W V

VI = 10.5V to 23V 7.6 8.0 8.4
V, = 11.5V to 23V 7.6 8.0 8.4
V, = 10.5V to 25V 6.0 160 6.0 160
Line Regulation 6Vo Tj=25 DC mV
V, = 11.5V to 17V 2.0 80 2.0 80
10 = 5.0mA to 1.5A 12 160 12 160

I
Load Regulation 6Vo T,=25 DC mV
10 = 250mA to 750mA 4.0 80 4.0 80
Quiescent Current Id Tj =25 DC 4.3 8 4.3 8 mA
10=5mA to 1.0A 0.5 0.5
Quiescent Current Chaoge 6 1d . VI = 10.5V to 25V 1.0 mA
VI = 11.5V to 25V 1.0
Output Voltage Drift 6VoI6T 10=5mA -0.8 -0.8 mVJ"i:,
Output Noise Voltage VN {= 10Hz to 100KHz T, = 25 DC 52 52 "V
.Ripple
RR f=120Hz, V,=11.5V to 21.5 56 72 56 72 dB
Rejection
Dropout Voltage Vo 10=1A, Tj =25 DC 2 2 V
Output Resistance Ro f=1KHz 16 16 mil
Short Circuit Current Ise VI = 35V, Tj =25 DC 450 450 inA
Peak Current Ipeak Tj =25 DC 2.2 2.2 A

* Tmin<Tj<Tmax
MC78XXI: Tmln = -40 DC, T~ax=125DC
MC78XXC, Tmln=ODC, Tmax =125 DC
* Load and line regulation are .specified at constant junction temperature changes in Vo due to heating
effects must be taken into account separately !lulse testing with low duty is used.

c8 SAMSUNG SE~ICONDUCTOR 327

MC78XX1MC78XXA LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7885

(Refer to test circuit T mln<T,<Tmax, 10 == 500mA, V, == 14.5V, C, == 0.33,..F, Co == 0.1,..F, unless otherwise specified)

MC78851 MC7885C
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max

T, == 25°C 8.15 8.5 8.85 8.15 8.5 8.85

Output Voltage Vo 10==5mA to 1.0A, PD S15W V

V, == 11V to 23.5V 8.1 8.5 8.9
V, == 12V to 23.5V 8.1 8.5 8.9
V, '" 11V to 25V 12 170 12 170
line Regulation 6Vo T j == 25°C mV
V, == 11.5V to 18V 5.0 85 5.0 85
10 == 5mA to 1.5A 45 170 45 . 170
Load Regulation 6Vo TJ == 25°C mV
10 == 250mA to 750mA 16 85 16 85
Quiescent Cumint Id Tj == 25°C 4.3 8.p 4.3 8.0 mA
16 == 5mA to 1.0A 0.5 0.5
Quiescent Current Change 610 V, == 11V to 25V 1.0 mA

V, == 12V to 25V 1.0

Output Voltage Drift 6VJ6T 10 == 5mA -1.0 -1.0 mV/oC
Output Noise Voltage VN f;" 10Hz to 100KHz, Ta == 25°C 55 55 ,..V
Ripple Rejection RR f == 120Hz, V, == 12V· to 22V 56 72 56 72 dB
Dropout Voltage VD 10 == 1.0A, T j == 25°C 2.0 2.0 V
Output Resistance Ro f== 1KHz 17 17 mil
Short Circuit Current Ise V, == 35V, TJ == 25°C 450 450 mA
Peak Current lpeak T, == 25°C 2.2 2.2 A

'* Tmin<Ti<Tmax
MC78XXI: Tm'n== -40°C, Tmax ==125°C
MC78XXC: Tmln==O°C, Tmax ==125°C
• Load and line regulation are specified at constant junction temperature changes in Vo due to heating effects
must be taken into account separately pulse testing with low duty is used. •

c8 SAMSUNG SEMICONDUCTOR 328

 MC78XX1MC78XXA LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7809

(Refer to test circuit, Tm;,<T,<Tmax, 10 = 500mA, V; = 15V, C, = 0.33"F, Co = 0.1"F, unless otherwise specified)

MC78091 MC7809C
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max

Tj =25°C 8.65 9 9.35 8.65 9 9.35

Output Voltage Vo 5.0mA::;:;lo::;:;1.0A, PD ::;:;15W V

V;=11.5V to 24V 8.6 9 9.4
V, = 12.5V to 24V 8.6 9 9.4
V; = 11.5V to 25V 6 180 6 180
Line Regulation 6Vo Tj =25°C mY·
V; = 12V to 25V 2 90 2 90
10=5mA to 1.5A 12 180 12 180
Load Regulation

Quiescent Current'

Quiescent Current Change

6Vo

Id

61d
Tj =25°C
10 = 250mA to 750mA
Tj =25°C
10=5mA to 1.0A
V,=11.5V to 26V
4
4.3
80
8
0.5
.4
4.3
90
8.0
0.5
1.3
mV

mA

mA
II
V, = 12.5V to 26V 1.3
Output Voltage Drift 6V o/6T lo=5mA -1 -1 mV/oC
Output Noise Voltage VN f = 10Hz to 100KHz Tj := 25°C 58 58 "V
Ripple f = 120Hz
RR 56 71· 56 71 dB
Rejection V, = 13V to 23V
Dropout Voltage VD 10 = 1A, T, = 25°C 2 2 V
Output Resistance Ro f=1KHz 17 17 mO
Short Circuit Current Isc V,=35V, Tj =25°C 450 450 mA
Peak Current Ipeak Tj =25°C 2.2 2.2 A

• Tmm<Tj<T max
MC7!lXXI: Tm;, = -40°C, Tmax= 125°C
MC78XXC, Tmm=O°C, Tmax =125°C
• Load and line regulation are specified at constant junction temperature changes in Vo due to heating
effects must be taken into account separately· pulse testing with low duty is used.

c8 SAMSUNG SEMICONDUCTOR 329

. '.
 MC78XX1MC78XXA LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7810

. (Refer to test circuit, Tmln<Tj<Tmax, 10 = 500mA, V, = 16V, C, =0.33JlF, Co = 0.1JlF, unless otherwise specified)

MC78101 MC7810C
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max

Tj =25°C 9.6 10 10.4 9.6 10 10.4

Output Voltage Vo 5.0mA~lo~1.0A, Po~15W V
V, = 12.5V to 25V 9.5 10 10.5
V, = 13.5V to 25V 9.5 10 10.5
V, = 12.5V to 25V 10 200 10 200
Line Regulation 6Vo Tj =25°C mV
V, = 13V to 20V 3 100 3 100
10=5mA to 1.5A 12 200 12 200 I
Load Regulation 6Vo T,=25°C mV
10 = 250mA to 750mA 4 100 4 100
Quiescent Current Id Tj =25°C 4.3 8 4.3 8 rnA
10 = 5mA to 1.0A 0.5 0.5
Quiescent Current Change 61d V, = 12.5V to 29V 1.0 rnA
V, = 13.5V to 29V 1.0
Output Voltage Drift 6Vo/6T 10=5mA ~1 -1 mV/oC
Output Noise Voltage VN f = 10Hz to 100KHz Tj = 25°C 58 58 JlV
Ripple f = 120Hz
Rejection
RR V, = 14V to 23V
56 71 56 71. dB

Dropout Voltage Vo 10 = 1A, Tj = 25°C 2 2 V

Output Resistance . 'Ae f=1KHz 17 17 mO
Short Circuit Current Isc V,=35V, Tj =25°C 420 420 rnA
Peak Current Ipeak Tj =25°C 2.2 2.2 A

• Tmln<'Tj<Tmax
· MC78XXI: Tm'n = - 40°C, Tmax = 125°C
MC78XXC, Tmln=O°C, Tmax =125°C
• Load and line regulation are specified at constant junction temperature changes in Vo due to heating
effects must be taken into account separately pulse testing with low duty is used.

c8 SAMSUNG SEMICONDUCTOR. 330.

MC78XX1MC78XXA LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7811

(Refer to test circuit, Tm;n<T,<Tmax, 10= 500mA, V, = 18V, C, =O.33/LF, Co = 0.1/LF, unless otherwise specified)

MC78111 MC7811C
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max

Tj =25°C 10.6 11 11.4 10.6 11 11.4

Output Voltage Vo 5.0mA:slo:s1.0A, Po:s15W V

V; = 13.5V to 26V 10.5 11 11.5
V, = 14.5V to 26V 10.5 11 11.5
V, = 13.5 to 25V 10 220 10 220
Line Regulation 6Vo Tj =25°C mV
V,=14 to 21V 3.0 110 3.0 110
10 = 5.0mA to 1.5A 12 220 12 220

II
Load Regulation 6Vo Tj =25°C mV
10 = 250mA to 750mA 4 110 4 110
Quiescent Current Id T,=25°C 4.3 8 4.3 8 mA
10=5mA to 1A 0.5 0.5
Quiescent Current Change 61d V; = 13.5V to 29V 1.0 mA
V; = 14.5V to 29V 1.0
Output Voltage Drift 6Vo/6T 10 = 5mA -1 -1 mV/oC
Output Noise Voltage VN f = 10Hz to 100KHz Tj = 25°C 70 70 /LV
Ripple f = 120Hz
RR 55 71 55 71 dB
Rejection V, = 14V to 24V
Dropout Voltage .Vo 10=1A, Tj =25°C 2 '2 V
Output Resistance Ro . f= 1KHz 18 18 mO
Short Circuit Current Isc V; = 35V, Tj =25°C 390 390 mA
Peak Current lpeak Tj =25°C 2.2 2.2 A

* Tm,n<Tj<Tmax
MC78XXI: Tm;n= -40°C, Tmax = 125°C
MC78XXC, Tm'n=O°C, Tmax=125°C
* Load and line regulation are specified at constant junction temperature changes in Vo due to heating
effects must be taken into account separately pulse testing with low duty is used.

c8 SAMSUNG SEMICONDUCTOR 331

MC78XX1MC78XXA LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7812

(Refer to test circuit, Tmm<Tj<Tmax, 10= 500mA, VI = 19V, CI =0.33"F, Co=0.1"F, unless otherwise specified)

MC78121 MC7812C
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ fJlax

Tj =25°C 11.5 12 12.5 11.5 12 12.5

Output Voltage Vo 5.0mAslos1.0A, PoS15W V

Vln = 14.5V to 27V 11.4 12 12.6
VI = 15.5V to 27V 11.4 12 12.6
VI;" 14.5 to 30V 10 240 10 240
Line Regulation t::,Vo TI=25°C mV
VI = 16 to 22V 3.0 120 3.0 120
10 = 5mA to 1.5A 12 240 12 240
Load Regulation t::,Vo Tj =25°C mV
10 = 250mA to 750mA 4.0 120 4.0 120
Quiescent Current Id TJ=25°C 4.3 8 4.3 8 mA
10 = 5mA to 1.0A 0.5 0.5
Quiescent Current Change t::, Id . Vi = 14.5V to 30V 1.0 mA
VI = 15V to 30V 1.0
Output Voltage Drift t::, Volt::, T 10=5h1A -1 -1 mV/oC
Output Noise Voltage VN f = 10Hz to 100KHz TI = 25.oC 75 75 "V
Ripple f = 120Hz
RR 55 71 55 71 dB
Rejection Vi = 15V to 25V
Dropout Voltage Vo 10= 1A, Tj = 25°C 2 2 V
Output Resistance Ro f= 1KHz 18 18 mO
Short Circuit Current Ise Vi = 35V, Tj =25°C 350 350 mA
Peak Current Ipeak Tj =25°C 2.2 2.2 A

* Tmin<TJ<Tmax
MC78XXI: Tmin= -40°C, Tmax= 125°C'
MC78XXC, Tmin = O°C, Tmax = 125°C
* Load and line regulation are specified at constant junction temperature changes in Vo due to heating
. effects must be taken into account separately pulse testing with low duty is used.

c8 SAMSUNG SEMICONDUCTOR 332

MC78XX1MC78XXA LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7815

(Refer to test circuit, Tmln<Tj<Tma><, 10 = 500mA, V, = 23V, C, = 0.33/LF, Co = 0.1/LF, unless otherwise specified)

MC78151 MC7815C
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max

T, =25°C 14.4 15 15.6 14.4 15 15.6

Output Voltage Vo 5.0mA:s 10:S 1.0A, PD:s 15W V
V, = 17.5V to 30V 14.25 15 15.75
V, = 18.5V to 30V 14.25 15 15.75
V, = 17.5 to 30V 11 300 11 300
Line Regulation /,;V o Tj =25°C mV
V, =20 to 26V 3 150 3 150
10 = 5.0mA to 1.5A 12 300 12 300

I
Load Regulation /,;V o T,=25°C mV
10 = 250mA to 750rriA 4 150 4 150
Quiescent Current Id TJ=25°C 4.4 8 4.4 8 mA
10=5mA to 1.0A 0.5 0.5
Quiescent Current Change /';Id V, = 17.5V to 30V 1.0 mA
V, = 18.5V to 30V 1.0
Output Voltage Drift /,;VJ/,;T 10=5mA -1 -1 mV'oC
Output Noise Voltage . VN f = 10Hz to 100KHz Tj = 25°C 90 90 /LV
Ripple f = 120Hz
RR 54 70 54 70 dB
Rejection V, = 18.5V to 28.5V
Dropout Voltage VD 10 = 1A, Tj = 25°C 2 2 V
Output Resistance Ro f=1KHz 19 19 m{J
Short Circuit Currel)t Isc V, = 35V, Tj = 25°C 230 230 mA
Peak Current Ipeak Tj =25°C 2.2 2.2 A

• Tmln<Tj<Tma,
MC78XXI: Tmin = - 40°C,. Tma>< = 125°C
MC78XXC, Tmln=O°C, Tma><=125°C
• Load and line regulation are specified at constant junction temperature changes in Vo due to heating
effects must be taken into account separately pulse testing with low duty is used.

c8 SAMSUNG SEMICONDUCTOR 333

MC78XX1MC78XXA LINEAR INTEGRATED CIRCUIT

'ELECTRICAL CHARACTERISTICS MC7818

(Refer to' test circuit, Tmin<TJ<Tmo>c, 10 = 5OOmA, Vi = 27V, Ci = O.33I'F, Co = 0.1I'F, unless otherwise specified)

MC78181 MC7818C
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max

Tj =25°C 17.3 18 18.7 17.3 18 18.7

Output Voltage Vo 5.0mAslos1.0A, Pos15W V,
Vi = 21V to 33V 17.1 18 18.9
Vi = 22V to 33V 17.1 18 18.9
Vi ';'21 to 33V 15 360 15 360
Line Regulation D.Vo TJ=25°C 'mV'
Vi =24 to 30V 5 180 5 180
10 = 5mA to 1.5A 12 360 12 360
Load Regulation 'D.Vo TJ=25°C mV
10 = 250mA to 750mA 4.0 180 4.0 180
Quiescent Current Id TJ;"25~C 4.3 '8 4.3 8 rnA
10 = 5mA to 1A 0.5 0.5
Quiescent Current Change D.ld Vi = 21V to 33V 1 rnA
Vi = 22V to 33V 1
, Output Voltage Drift D.VJD.T 10=5mA -1 -1 mV/oC
Output Noise Volt~ge VN f = 10Hz to 100KHz TJ= 25°C 110 110 I'V
Ripple f = 120Hz
RR 53 69 53 69 dB
Rejection Vi = 22V to 32V
Dr9poilt Voltage Vo 10=1A, TJ=25°C 2 2 V
Output Resistance Ro f=1KHz 22 22 mO
~-~------~-

Short Circuit Current Isc Vi = 35V, TJ=25°C 200 200 rnA

--
Peak Current ' lpeak TJ=25°C 2.2 2.2 A

• Tmin<TJ<Tmax
MC78XXI: Tmln= .,..40°C, Tma.=125°C
MC78XXC, Tmin=O°C, Tma, = 125°C
• Load and line regulation are specified at constant junction temperature qhanges in Vo due to heating
effects must be taken into account separately pulse testing with low duty is used.

c8 SAMSUNG SEMICONDUCTOR 334

MC78XX1MC78XXA LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7824

(Refer to test circuit, Tmm<T,<Tmax, 10=500mA, V, = 33V, C, =0.33"F, Co=0.1"F, unless otherwise specified)

MC78241 MC7824C
Characteristic. Symbol Test Conditions Unit
Min Typ Max Min Typ Max

TJ=25°C 23 24 25 23 24 25

Output Voltage Vo 5.0mAslos1.0A, PoS15W V

Vi = 27V to 38V 22.8 24· 25.2
V, = 28V to 38V 22.8 24 25.2
V, = 27V to 38V 18 480 18 480
Line Regulation 6Vo Tj =25°C mV
V, = 30V to 36V 6 240 6 240
10 = 5mA to 1.5A 12 480 12 480
Load Regulation •

Quiescent Current

Quiescent Current Change

6Vo

Id

61d
Tj =25°C
10 = 250mA to 750mA
Tj =25°C
10=5mA to 1A
V, = 27V to 38V
4
4.3
240
8
0.5
4
4.3
240
8
0.5
1
mV

mA

mA
II
Vi = 28V to 38V 1
Output Voltage Drift 6Vo/6T 10=5mA -1.5 -1.5 mV/oC
Output Noise Voltage VN f = 10Hz to 100KHz TJ= 25°C 170 170 "V
Ripple f = 120Hz
RR 50 66 50 66 dB
Rejection V, = 28V to 38V
Dropout Voltage Vo 10=1A, Tj =25°C 2 2 V.
Output Resistance Ro f= 1KHz ·28 28 mO
Short Circuit Current Isc V, = 35V, T,=25°C 150 150 mA
Peak Current lpeak TJ=25°C 2.2 2.2 A

• Tmln<Tj<Tmax
MC78XXI: Tmin= -40°C, Tmax= 125°C
MC78XXC, Tmin=O°C, Tmax=125°C
• Load and line regulation are specified at constant junction temperature changes in Vo due to heating
effects must be taken into account separately pulse testing with low duty is used.

c8 SAMSUNG SEMICONDUCTOR 335

.MC78XXIMC78XXA LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC780SAC

,
(Refer to tlie test circuits, TJ =0 to 125°C, 10 = 1A, Vi =10V, Ci =0.33"F, Co =0.1,..F unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

Tj =25°C 4.9 5 5.1

Output VOltage Vo V
lo=5mAto 1A, PDI~15W
4.8 '5 5.2
V, = 7.5 to 20V

V,=7.5t025V,
7 50
10=500mA

'Line Regulation AVo Vi =8to 12V 10 50

mV

T =25°C
J
I Vi =7.3t025V 7 50

I Vi =8to 12V 2 25

Tj =25°C
25 100
10=5mAto 1.5A
'Load Regulation AVo mV
10=5mAto 1A 25 100

10 = 250 to 750mA 8 50

Quiescent Current Id TJ =25°C 4.3 6 mA

10=5mAto 1A 0.5

Quiescent Current Change Aid Vi =8to 25V, 10=500mA 0.8 mA

Vi =7.5 to 20V, Tj =25°C 0.8

AVo
Output Voltage Drift 10=5mA -1.1 mVI"C
AT

f=10Hz to 100KHz: "V

Output Noise Voltage VN 10
T.=25°C V;
f=120Hz,lo=500mA
Ripple Rejection RR 68 dB
Vi =8to 18V

Dropout Voltage VD 10=1A, Tj =25°C 2 V

Output Resistance Ro f=1KHz 17 mil

Short Circuit Current I.e V,=35V, Ta=25°C 750 mA

Peak Current Ipeak TJ =25°C 2.2 A

, Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken
into account separately. Pulse testing with low duty cycle is used.

c8 SAMSUNG SEMICONDUCTOR 336

MC78XX1MC78XXA LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7806AC

(Refer to the test circuits, Tj =0 to 150OC, 10 =lA, V, =11V, C, =O.33J.1F, Co =0.1J.&F unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

T,=25°C 5.88 6 6.12

Output Voltage Vo V
10 = 5mA to lA, PD~15W
5.76 6 6.24
=
V, 8.6 to 21V

V, =8.6 to 25V,
9 60
10 = 500mA

'Line Regulation aVo V, =9to 13V 11 60

mV

T j =25°C
I V, =8.3 to 21V 9 60

I V, =9to 13V
I
3 30

T,=25°C
43 100
10 =5mA to 1.5A
'Load Regulation aVo mV
10=5mAto lA 43 100

10 = 250 to 750mA 16 50

Quiescent Current Id T,=25°C 4.3 6 mA

.I o=5mAto lA 0.5

Quiescent Current Change aid V, =9 to 25V, 10 =500mA 0.8 mA

V, =8.6 to 21V, T, = 25°C 0.8

aVo iii
Output Voltage Drift 10=5mA -0.8 rril/fOC
aT
-
f=10Hz to 100KHz J.lV
Output Noise Voltage VN 10 ---v;;
Ta=25°C

f=120Hz. 10 =500mA
Ripple Rejection RR 65 dB
V,=9to 19V

Dropout Voltage Vd 10=IA, T,=25°C 2 V

Output Resistance Ro f=IKHz 17 'mil

Short Circuit Current lac V, '!"35V, T a =25°C 550 mA

Peak Current Ipeak 'T,;'25°C 2.2 A

, Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken
into account separately. Pulse testing with lOw duty cycle is used.

c8 SAMSUNG SEMICONDUCTOR 337

MC78xx/MC78XXA. LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC780SAC

(Refer to the test circuits, T j =0 to 150°C, 10 =1 A, V, = 14V, C, =0.33,..F, Co =0.1,..F unless otherwise specified)

CharacterIstic Symbol Test Conditions Min Typ . Mlix Unit

TJ =25°C 7.84 8 8.16

Output Voltage Vo V
10=5mA to 1A, PoS15W
7.7 8 8.3
Vi= 10.6 to 23V

Vi= 10.6 to 25V,

12 80
10 = 500mA

'Line Regulation !:.vo Vi =11 to 17V 15 80

mV

T =25°C
J
I Vi =10.4 to 23V 12 80

I Vi =11 to 17V 5 40

T j =25°C
45 100
10=5mAt01.5A
'Load Regulation !No mV
10=5mAto 1A 45 100

10 = 250 to 750mA 16 50

Quiescent Current Id TJ =25°C 4.3 6 mA

10=5mAto 1A 0.5

Quiescent Current Change .lId V,=11 to 25V, 10=500mA 0.8 mA

V, =10.6 to 23V, T j =25°C 0.8

.lVo
Output Voltage Driff 10=5mA -0.8 mVI"C
AT
f=10Hz to 100KHz ,..V
Output Noise Voltage VN 10
T.=25°C Ii;
f=120Hz, 10 =500mA
Ripple Rejection RR 62 dB
Vi =11.5 to 21.5V

Dropout Voltage Vo 10.=1A, T j = 25°C 2 V

Output Resistance Ro f=1KHz 18 mil

Short Circuit Current 180 Vi = 35V, T.=25°C 450 mA

Peak Current lpeak TJ =25°C 2.2 A

, Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken
into account separately. Pulse testing with low duty cycle is used.

c8 SAMSUNG SEMICONDUCTOR 338

MC78XX1MC78XXA LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7885AC

(Refer to the test circuits, Tj = 0 to 125°C, 10 = 1A, V, = 14V, C, = 0.33/LF, Co = 0.1/LF unless otherwise specified)

Characteristic . Symbol Test Conditions Min Typ Max Unit

Tj =25°C 8.33 8.5 8.67

Output Voltage Vo 10=5mA to 1.0A, Pos15W V
V, = 11.2V to 23.5V 8.15 8.5 8.85
V, = 11.2V to 25V
10=500mA 12 85
V, = 11.5V to 18Y 15 43
Line Regulation /,;Vo mV
T,=25°C
I V, = 11V to 23.5V 12 85
I V, = 11.5V to 18V 5.0 43
Tj =25°C
10=5mA to 1.5A 45 100
Load Regulation /,;Vo mV
10=5mA to 1.0A 45 100
10 = 250mA to 750mA 16 50
Quiescent Current Id Tj =25°C 4.3 6.0 mA
10=5mA to 1.0A 0.5
Quiescent" Current Change /'; Id . V,=11.5V to 25V, Tj =25°C 0.8 mA
V, = 11.2V to 23.5V, 10 = 500mA 0.8
Output Voltage Drift 6Vo/LT 10=5mA -1.0 mV/oC
Output Noise Voltage VN f=10Hzto 100KHz, Ta=25°C 10 /LVNo
f = 120Hz, V, = 12V to 22V
Ripple Rejection RR 62 dB
10=500mA
Dropout Voltage Vo 10=1.0A, T,=25°C 2.0 V
Output Resistance Ro f= 1KHz 17 m
Short Circuit Current Ishort V,=35V, Ta=25°C 450 mA
Peak Current Ipeak Tj =25°C 2.2 A

* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects
must b.e taken into account separately. Pulse testing with low duty cycle is used.

c8 SAMSUNG SEMICONDUCTOR 339

 MC78XX1MC78XXA LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7809AC

. (Refer to the test circuits, Tj = 0 to 125°C, 10 = 1A, V, =.15V, C, = 0.33/LF, Co = 0.1/LF unless otherwise specified)

Characteristic Symbol Test Conditions • Min Typ Max Unit

Tj =25°C 8.82 9.0 9.18

Output Voltage Vo 10=5mA to 1.0A, Pos15W V

V, = 11.2V to 24V 8.65 9.0 9.35
V,=11.7V to 25V
1~=500mA 12 90
V, = 12.5V to 19V 15 45
Line Regulation 6Vo mV
T =25°C
I V,=11.5V to 24V 12 90
j
I V, = 12.5V to 19V 5.0 45
T)=25°C
10=5mA to 1.0A 46 100
Load Regulation 6Vo mV
10=5mA to 1.0A 46 100
10 = 250mA to 750mA 17 50
Quiescent Current Id Tj =25°C 4.3 6.0 mA
V,=11.7V to 24V, Tj =25°C 0.8
Quiescent Ourrent Change 6 1d V, = 12V to· 25V, 10 = 500mA 0.8 mA
10 = 5mA to 1.0A 0.5
Output Voltage Drift 6VoIfH 10=5mA -1.0 mV'oC
Output Noise Voltage VN f = 10Hz to 100KHz, Ta = 25°C 10 /LVlVo
f= 120Hz, V, = 12V to 22V
Ripple Rejection RR 62 dB
10 = 500mA
Dropout Voltage Vo 10 = 1.0A, Tj = 25·C 2.0 V
Output Resistance Ro f=1KHz 17 m
Short Circuit Current Ishort V,=35V, Tj =25°C 420 .mA
Peak Current I peak Tj =25°C 2.2 A

• Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects
must tie taken into account separately. Pulse testing with low duty cycle is used.

c8 SAMSUNG SEMiCONDUCTOR 340

MC78XX1MC78XXA LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7811AC

(Refer to the test circuits, Tj = 0 to 125°C, 10 = 1A, V, = 18V, C, = 0.33"F, Co = 0.1"F unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

Tj =25°C 10.8 11.0 11.2

Output Voltage Vo 10=5mA to 1.0A, PD:s15W V
V, = 13.8V to 26V 10.6 11.0 11.4
Vi = 13.8V to 27V
10 = 500mA 13 110
V, = 15V to 21V 16 55
Line Regulation 6Vo mV
TJ=25°C
l Vi = 13.5V to 26V 13 110 .
I Vi.= 15V to 21V 6.0 5.5

I
T,=25°C
10=5mA to 1.5A 46 100
Load Regulation 6Vo mV
. 10 = 5mA to 1.0A 46 '100
10 = 250mA to 750mA 17 50
T,=25°C 4.4 6.0
Quiescent Current Id mA
6.0
Vi=13.8V to 26V, Tj =25°C 0.8
Quiescent Current Change 6 1d V, =14V to 27V, 10=500mA 0.8 mA
10=5mA to 1.0A . 0.5
Output Voltage Drift t:,Volt" T 10=5mA -1.0 mV/oC
Output Noise Voltage VN f = 10Hz to 100KHz, Ta = 25°C 10 "VIVo
f = 120Hz, Vi = 14V to 24V
Ripple Rejection RR 61 dB
10=500mA
Dropout Voltage VD 10=1.0A, TJ=25°C 2.0 V
Output Resistance Ro f=1KHz 18 m
Short Circuit Current Ishort Vi = 35V, TJ=25°C 390 mA
Peak Current Ipeak T,=25°C 2.2 A

• Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects
must be taken into account separately. Pulse testing with l.ow duty cycle is used.

c8 SAMSUNG SEMICONDUCTOR 341

MC78XX/MC78XXA LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7812AC

(Referto the test circuits, T j =0 to 1500C, 10 =1,A,V1= 19V, C1=O.33,..F, Co =0.1,..F unless otherwise specified)

Characteristic Symbol Test Conditions Min 1\'p Max Unit

T j =25°C 11.75 12 12.25

Output Voltage Vo V
10=5mA to 1A, Pos15W
11.5 12 12.5
Vi = 14.8 to 27V

Vi = 14.8 to 30V,
13 120
10 = 500mA

*Line Regulation aVo Vi =16t022V 16 120

mV

T =25°C
j
I V, =14.5 to 27V 13 120

I Vi =16 to 22V 6 60

Tj =25°C
46 100
10=5mA to 1.5A
*Load Regulation aVo mV
10=5mA to 1A 46 100

10 = 250 to 750mA 17 50

Quiescent Current Id Tj =25°C 4.4 6 mA

10=5mAto 1A 0.5

C.uiescent Current Change aid Vi =15 to 30V, 10 =500mA 0.8 mA

Vi =14.8 to 27V, Tj =25°C 0.8

aVo
Output Voltage Drift 10=5mA -1 mVI"C
aT

f=10Hz to 100KHz ,..V

Output Noise Voltage VN 10
Ta=25°C. '-i;
f=120Hz,lo=500mA
Ripple Rejection RR 60 dB
Vi =15to 25V

Dropout Voltage Vo 10=1A, Tj =25°C 2 V

Output Resistance Ro f=1KHz 18 mO

Short Circuit Current Iso Vi = 35V, Ta=25°C 350 mA

Peak Current Ipeak Tj =25°C 2.2 A

* Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken
into account separately. Pulse testing with low duty cycle is used.

c8 SAMSUNG SEMICONDUCTOR· 342

MC78XXC/MC78XXAC SERIES LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7815AC

(Refer to the test circuits, T j =0 to 150°C, 10 =1A, Vi = 23V, Ci =0.33/LF, Co ;;0.1 ~ unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

T j =25°C 14.7 15 15.3

Output Voltage Vo V
10=5mA to 1A, PD S15W
14.4 15 15.6
Vi= 17.7 to 30V

Vi= 17.9 to 39V,

13 150
10 = 500mA

. "Line Regulation t.Vo V,=20to 26V 16 150

mV
I V, =17.5 to 30V 13 150
T =25°C
j
I V, =20 to 26V. 75

I
6

TJ =25°C
,52 100
10=5mAt01.5A
"Load Regulation t.Vo mV
10=5mA to 1A 52 109

10 = 250 to 750mA 20 50

Quiescent Current Id TJ =25°C 4.4 6 mA

10=5mA to 1A 0:5

Quiescent Current Change .6.ld V,=17.5 to 30V, 10=500mA 0.8 mA

Vi = 17.5 to 30V, TJ =25°C 0.8

.6.Vo
Output Voltage Drift 10=5mA -1 mVloC
~
f =10Hz to 100KHz /LV
Output Noise Voltage VN 10
T.=25°C VO
f=120Hz, 10 =500mA
Ripple Rejection RR 58 dB
Vi =18.5 to 28.5V

Dropout Voltage VD 10=1A, Tj =25°C 2 V

Output Resistance ,. Ro f=1KHz 19 m{l

Short Circuit Current I';' V,=35V, T.=25°C 230 mA

Peak Current Ipeak Tj =25°C 2.2 A

" Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken
into account separately. Pulse testing with low duty cycle is used.

c8 SAMSUNGSEMICONDUCTOR 343
MC78XXIMC78XXA LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7818AC

(Refer to the test circuits, Tj;=O to 150"C, 10 =1!A, Vi =27V, Ci =0.33I'F, Co =0.1,.F unless otherwise specified)

Characteristic ~ymbol Test Conditions Min lYP Max . Unit

Tj =25OC 17.64 18 18.36

Output Voltage Vo V
10"'5mA to lA, Pos15W
17.3 18 18.7
V,=211033V

Vi =21 to 33V,
25 180
10 = 500mA

"Line Regulation !:No V,=24t030V 28 180

mV
I V, =20.6 to 33V. ~5 . 180
T =25°C
j
I Vi =24 to 30V 10 90
T j =25°C
55 100
10=5mA to 1.5A
"Load Regulation I!.Vo mV
10=5mA to lA 55 100

10 = 250 to 750mA 22 50

Quiescent Current I. Tj =25°C 4.5 6 mA

10=5mAto lA 0.5

Quiescent Current Change I!.I. Vi =2110 33V, 10 =500mA 0.8 mA

Vi =21 to 33V, T j = 25°C 0.8

I!.Vo
Output Voltage Drift 10=5mA -1 mVfOC
I!.T

Output Noise Voltage VN

f =10Hz to 100KHz
10 ~
Ta=25°C Vo

1=120Hz,lo=500mA
Ripple Rejection RR 57 dB
V,=22t032V

Dropout Voltage Vo 10=lA, Tj =25°C 2 . V

Output Resistance Ro f=lKHz 19 mO

Short Circuit Current Iso Vi = 35V, Ta=25°C f 200 rnA

Peak Current Ipeak Tj =25°C 2.2 A

" Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken
into account separately. Pulse testing with low duty cycle is used.

c8 SAMSUNG SEMICONDUCTOR 344

MC78XXJMC78XXA LINEAR INTEG~TED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7824AC

(Refer to the test circuits, T j =0 to 150"C, 10 =11A, Vi =33V, C, =0.33I'F, Co =0.1,.F unless otherwise specified)

Characteristic Symbol Test Conditions Min l'yp Max Unit

Tj =25°C ·23.5 24 24.5

Output Voltage Vo V
10=5mA to 1A, Po:s15W
23 24 25
Vi = 27.3 to 38V

Vi =27 to 38V,
31 240
10=500mA

'Line Regulation l!.Vo Vi =30 to 36V 35 240

mV

T,=25°C
I V,=26.7t038V 31 240

I V, =30 to 36V 14 120

'Load Regulation l!.Vo

TJ=25°C
10=5mA to 1.5A

10=5mA to 1A

10 = 250 to 750mA
60

60

25
100

100

50
mV
II
Quiescent Current I. Tj =25°C 4.6 6 mA

10=5mAto 1A 0.5

Quiescent Current Change l!.1. V, =27.3 to 38V, 10 =500mA 0.8 mA

Vi =27.3 to 38V, TJ= 25°C 0.8

t.Vo
Output Voltage Drift 10= 1mA -1.5 mVJOC
l!.T

f =10Hz to 100KHz I'V

Output Noise Voltage VN 10
T.=25°C Va
f=120Hz, 10 =500mA
Ripple Rejection RR 54 dB
V, =28 .to 38V

Dropout Voltage Vo 10=1A, T j =25°C 2 V

Outp!.!t Resistance Ro f=1KHz 20 mil

Short Circuit Current Iso V,=35V, T.=25°C 150 rnA

Peak ·Current Ipeak Tj =25°C 2.2 A

, Load and ·line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken
into account separately. Pulse testing with low duty cycle is used. .

.c8 SAMSUNG SEMICONDUCTOR . 345

MC78XXIMC78XXA LINEAR INTEGRATED CIRCUIT

TEST CIRCUIT
DC parameters

1 3
MC78XXX VOUT

:~Ci Co :~
O.33~F O,1~

I~ Fig, 3

Load regulation

3
MC78XXX 1 - - - - + - - - - - - - - - - 0 VOUT

RL 270pF
2

\----4--It,J"h----4---o Vo
Jl VO

OV
SOpS

Fig, 4

Ripple rejection'

5.111 1 3
~
MC78XXX VOUT

1 ;;;r-0.33~F 2
~ ~RL

-
470~F
rh
120Hz
f----ll-
Fi g ,5

c8 SAMSUNG SEMICONDUCTOR 346

MC78XX/MC78XXA LINEAR INTEGRATED CIRCUIT

APPLICATION CIRCUIT

Fixed output regulator Constant current regulator

(j) 3 3
V,N o----r---I MC78XXX I---r----Q MC78XXX
Vour V,N

® ®
I
Id 2
AT vxx

li lO

Notes:
Fig. 6

(1) To specify an output voltage, substitute voltage value for "XX."

(2) Although no output capacitor is needed for stability, it does
lo=VXX+ 1d
A1
Fig. 7
II
improve transient respOnse.
(3) Required if regulator is located an appreciable distance from
power. supply filter.

Circuit for increasing output voltage Adjustable output regulator (7 to 30V)

3
V,N MC78XXX
Vour V,N Vour

2 o.T AT
j Id
"F

0.33~F
O.TII'

TOkO

A2

Fig. 9

IA1 ;;,51 d
VO=VXX (1+R2/R,)+ld R2

c8 SAMSUNG SEMICONDUCTOR 347

MC78XX/MC78XXA LINEAR INTEGRATED CIRCUIT

APPLICATION CIRCUIT (continued)

0.5 to 10V regulator High current voltage regulator

, 101

'3
MC78XXX
10 VOUT

2
0.1""

R,= . VBEO'
IREO-I o, Bo,

,Fig. 10 Fig. 11

High output current wi,th short circuit protection Tracking voltage regulator

RSC ;3
MC78XXX
VOUT

Q2 2
4.7I<D

R1 3 VOUT
COMMON COMMON
,3D

Q1=8D534
Q2=2N6124

Rsc= VBE02
1 ~r
~
-VOUT

Fig. 12 Fig. 13

c8 SAMSUNG SEMICONDU~OR 348

MC78XX1MC78XXA LINEAR INTEGRATED CIRCUIT

Split power supply (± 15V - 1A) Negative output voltage circuit

VOUT
3
MC7815

)1 2

MC78XXX
·O.lpF

-2CN 2
MC7915
3

Fig. 14
lN4OO1

-15V

Fig. 15
II
Switching regulator High input voltage circuit

2N3789 lmH VIN 3

MC78XXX
V,N VOUT V,N

2
R
O.33,.F o.lpF
3
2OOO~F Z2
+
10~F
2

+
2000~F

O.5U VIN ~ VI - (VZ + Vee)

Fig. 16 Fig. 17

c8 SA~SUNG SEMICONDUCTOR 349

MC78XX/MC78XXA LINEAR INTEGRATED CIRCUIT

APPLICATION CIRCUIT (continued)

High inputl70ltage circuit High output vo.ltage regulator

1 3
MC7BXXX MC7BXXX

1 1
VIN You

Ro O.33~F
~ O.1~·

Fig. 18 1 Fig. 19
I

High input and output voltage Reducing power dissipation with !dropping resitor

R
3
MC7BXXX
Your VIN Your

2
'0
O.1~ RL

VZ1
R= VI (mlnrVXx-VDROP (max)
10 (max) + 10 (max)
VO=VXX+VZ1
Fig. 20 Fig. 21

c8 SAMSUNG SEMICONDUCTOR 350

MC78XX/MC78XXA LlNEAR·INTEGRATED CIRCUIT

APPLICATION CIRCUIT (continued)

Remote shuntdown Power AM modulator

(unity voltage gain, 10 ~ 1M

R1
01
MC78XXX

2
MC78XXX·

2
3 VOUT

vxx
vob A A
\TV

II
O.1pF

560 -L/'\.;--r- MOdulation

V Signal

R3

LOGIC
INPUT
Fig. 22 Fig. 23
Note: The circuit performs well up to 1QO KHz.

Adjustable output voltage with temperature compensation

MC78XXX f-----.~--___(l VOUT

2 Rl

Q2

01

+
C

Fig. 24

Note: 02 is connected as a diode in order to compensate the

variation of the 01 Vee with the temperature. C allows a
slow rise-time of the Vo
. R
Vo =Vxx(1+1f,l + VBE

c8 SAMSUNG SEMICONDUCroR 351

· MC78XX/MC78XXA LINEAR INTEGRATED CIRCUIT

Light controllers ryo min=Vxx +Vee) .

(b)

3
MC78XXX
VOUT V,N VOUT

Fig. 25

v. lalla when the light goes up Vo rises when the light goes up

Protection against input short-circuit witb high

capacitane loads

.........

1
MC78XXX
3 ...
vIN VoUT

2
+
Z!Z
~

"
!.? Fig. 26

Applications with high capacitance loads and an output voltage

greater than 6 volts need an external diode (see fig. 26) to protect
the device against input short circuit. In this case the input voltage
falls rapidly while the output voltage decreases showly. The
capacitance discharges by means of the Base-Emitter junction of
the series pass trensistor in the regulator. If the energy is sufficiently
high. the transistor may be destroyed. The external diode by-passes
the current from the Ie to ground.

c8 SAMSUNG SEMICONDUctOR 352

MC78LXXAC SERIES LINEAR INTEGRATED CIRCUIT

3-TERMINAL POSITIVE VOLTAGE T0-92

REGULATORS
These regulators employ internal current-limiting and thermal-shutdown,
making them essentially indestructible. If adequate heat sinking is
provided, they can deliver up to 100mA output current. They are intended
as fixed voltage regulators in a wide range of applications including local
(on-card) regulation for elimination of n!lise and distribution problems
associated with single-point regulation. In addition, they can be used with
power pass. elements to make high-current voltage regulators. The
MC78LXXAC used as a Zener diode/resistor combination .replacement,
offers an effective output impedance improvement of typically two orders
of magnitude, along with lower quiescent current and lower noise.

FEATURES
•
•
•
•
•
•
Output current up to 100mA.
No external components.
Internal thermal overload protection.
Internal short circuit current limiting.
Available in JEDEC TO-92.
Output voltage of 2.6V, 5V, 6.2V, SV, S.2V,
ORDERING INFORMATION
Device
1: Output 2: GNO 3: Input

Package Operating Temperature

II
9V, 12V, 15V, 1SV, and 24V. MC78LXXACZ TO-92 O°C - + 125°.c
• Output voltage tolerances of ±5% over
the temperature range. **MC78LXXAIZ TO-92 -40°C - + 125°C
** Under Development
SCHEMATIC DIAGRAM
INPUT

OUTPUT
R4

R9

01

R5. Rl0

~----~--~---4---~----+-----+---------~--------~--------4---~GNO

c8 SAMSUNG SEMICONDUCTOR .353

MC78LXXAC SERIES LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Ta =25°C)

Characteristic Sym!Jol value Unit

Input Voltage (2.6V-9V) 30 V

(12V-18V) Vi 35 V
(24V) 40 V
Operating Temperature Range Top. 0- +125 °C
Storage. Temperature Range ~T~;~_ -65 - +150 °C

MC78L26AC ELECTRICAL CHARACTERISTICS

V'N =9V, lOUT =40mA, O°C :sTj:s 125°C, C'N =0.33/tF, COUT =0.1 #, unless otherwise specified. (Note 1)

Characteristic Symbol Test Conditions Min lYP Max Unit

Output Voltage Vo Tj =25OC 2.5 2.6 2.7 V

4.75V:sV'N:s20V 40 100 mV
Line Regulation fNo Tj =25OC
5V :S V'N:S 20V 30 75 inV
lmA:slouT :sl00mA 10 50 mV
Load Regulation tN o Tj =25OC
lmA:slouT :s40mA 4.0 25 mV
4.75V:s V'N:S 2fN lmAslouTs40mA 2.45 2.75 V
Output Voltage Vo 4.75VsV'NSVmax
lmA:slouT :s70mA 2.45 2.75 V
(Note 2)
Quiescent Current Id Tj =25°C 2.0 5.5 mA
QUiescent Current I with line .1ld 5V:sViN :s20V· 2.5 mA
Change with load .1ld . 1mAsiouT s40mA 0;1· mA
I
Output Noise Voltage YN. Ta =25°C,10Hzsf:s100KHz 30 /tV
.1Vo -0.4 mV/oC
Temperature Coefficient of VOUT 'ouT=5mA
.1T
Ripple Rejection RR f=120Hz,6V:sV,Ns16V, Tj=25°C 43 51 dB
Dropout Voltage Vo \ Tj =25OC 1.7 V
Peak Output/Short-Circuit Current Isc Tj =25°C 140 mA

c8 SAMSUNG SEMICONDUCTOR 354

MC78LXXAC SERIES LINEAR INTEGRATED CIRCUIT

MC78LOSAC ELECTRICAL CHARACTERISTICS

-
V'N =10\1 louT =4OmA OOC sTit> 125°C C'N -0.331'F CO~T -
-0 1/lF unless otherwise specified (Note 1)

Characteristic Symbol Test Conditions Min Typ Max Unit

Output Voltage Vo Tj =25°C 4.S 5.0 5.2 V

7VSV'NS20V 55 150 mV
line Regulation c.Vo T j =25°C
SVsV,Ns20V 45 100 mV
lmAslouT sl00mA 11 60 mV
Load Regulation c.Vo T j =25°C
lmAsiouT s40mA 5.0 30 mV
"NsV,Ns2W lmAslouTs40mA 4.75 5.25 V
Output Voltage Vo 7VSV'NSVmax
lmAslouTs70mA 4.75 5.25 V
(Note 2)
Quiescent Current Id T j =25°C 2.0 5.5 mA

Quiescent Current
Change

Output Noise Voltage

I
I
with line
with load
c.ld
c.ld
VN
c.Vo
SVsV,Ns20V
lmA s louT s40mA
T.=25°C,10Hzsfsl00KHz 40
1.5
0.1
mA
mA
I'V
II
Temperature Coefficient of V OUT louT=5mA -0.65 mV/oC
c.T

Ripple Rejection RR f=l20Hz.8VsV,Nsl8V, Tj=25°C 41 49 dB

Dropout Voltage Vo TJ=25°C 1.7 V
Peak Output/Short-Circuit Current Isc TJ=25°C 140 mA

MC78L62AC ELECTRICAL CHARACTERISTICS

ooc sTj s 125°C. C'N =0.33I'F, COUT =0.1~, unless otherwise specified. (Note 1)
V'N =12V, IQuT =4OmA,
I
Characteristic Symbol Test Conditions Min "lYP Max Unit

Output Voltage Vo T j =25°C 5.95 6.2 6.45 V

S.5VSV'NS2OV 65 175 mV
line Regulation c.Vo Tj =25°C
9VSV'NS20V 55 125 mV
lmAs loUTs l00mA 13 SO mV
Load Regulation c.Vo TJ =25OC
lmAs lOUT s40mA 6.0 40 mV
8.5VsV,Ns2rN lmAslouTs40mA 5.90 6.5 V
Output Voltage Vo 8.5VSV'NSVmax
lmAslouT s70mA 5.90 6.5 V
(Note 2)
Quiescent Current Id' T j =25°C 2.0 5.5 mA

Quiescent Current I with line c.ld SVsV,Ns20V 1.5 mA

Change
I with load c.ld lmA s loUT s40mA 0.1 mA
Output Noise Voltage VN T.=25OC,10Hzsfsl00KHz 50 I'V
c.Vo mV/oC
Temperature Coefficient of VOUT IOUT=5mA -0.75
c.T

Ripple Rejection RR f=120Hz.lrNsV,Ns20V, Tj=25OC 40 46 dB

Dropout Voltage Vo TJ =25°C 1.7 V
Peak Output/Short-Circuit Current Isc TJ =25OC 140 mA

c8 SAMSUNG SEMICONDUCTOR 355

MC78LXXAC SERIES LINEAR INTEGRATED CIRCUIT
MC78LOSAC ELECTRICAL CHARACTERISTICS
VIN =14V, lOUT =40mA, O°C sTj s 125°C, CIN =0.33/LF. COUT =O.lpF, ..unless otherwise specified. (Note 1)
.I,t

Characteristic Symbol Test Conditions Min lYP Max Unit

Output Voltage Vo T1=25°C 7.7 8.0 8.3 V

10.5 s VIN s 23V 80 17.5 mV
Line Regulation !:No T j =25°C
llVsVIN s23V 70 125 mV
lmAs louTsl00mA 15 80 mV
Load Regulation AVo T1=25°C
1mAs lOUT s 40mA 8.0 40 mV
10.5V S VIN s 23V lmA s louT s40mA 7.6 8.4 V
Output Voltage Vo 10.5V S VIN s V maX
lmA s lOUTS 70mA 7.6 8.4 V
(Note 2)
Quiescent Current Id T j =25°C 2.0 5.5 mA

Quiescent Current I with line Aid l1V s VIN s 23V 1.5 mA

Change I with load Aid 1mA s lOUT s40mA 0.1 mA
Output Noise Voltage VN T. = 25°C, 10Hzsfs 100KHz 60 /LV
AVo
Temperature Coefficient of VOUT louT=5mA -0.8 mVI"C
AT
Ripple Rejection RR f=120Hz, l1V:sVIN:s21V, TJ=25°C 39 45 dB
Dropout Voltage Vo Tj=25°C 1.7 V
Peak Output/Short-Circuit
Iso Tj = 25°C 140 mA
Current

MC78L82AC ELECTRICAL CHARACTERISTICS

VIN =14V, lOUT =40mA, OOC sTj s 125°C, CIN =0.33/LF, COUT =O.lpF, unless otherwise specified. (Note 1)

Characteristic Symbol Test Conditions Min lYP Max Unit

Output Voltage Vo T1=25°C 7.87 8.2 8.53 V

l1V s VIN s 23V 80 175 mV
Line Regulation AVo T1=25°C
.12V sVIN s23V 70 125 mV
lmAsiouT sl00mA 15 80 mV
Load Regulation AVo T j =25°C
lmAs lOUT s40mA 8.0 40 mV
l1VsVIN s23V lmAslouTs40mA 7.8 8.6 V
Output Voltage Vo l1V"VIN "Vm..
lmAslouT s70mA 7.8 8.6 V
(Note 2)
Quiescent Current I. T1=25°C 2.0 5.5 mA

Quiescent Current I with line Aid 12V :S VIN:s 23V 1.5 mA

Change I with load Ald' lmAs louTs40mA 0.1 mA
Output Noise Voltage VN T.=25°C,10Hzsfsl00KHz 60 /LV
AVo mV/oC
Temperature Coefficient of VOUT louT=5mA -0.8
AT

Ripple Rejection RR f=I20Hz, 12VsVIN S22V, Tj=25°C 39 45 dB

Dropout Voltage Vo T1=25°C 1.7 V
Peak Output/Short-Circuit Current Isc T j =25°C .140 mA

c8 SAMSUNG SEMICONDUCTOR 356

· MC78LXXAC SERIES LINEAR INTEGRATED CIRCUIT

MC78L09AC ELECTRICAL CHARACTERISTICS

-
Y,N =15V, lOUT =40mA, O·C:5Tj < 125OC, C,N =0.33/LF, COUT =0.1pF, unless otherwise specified. (Note 1)

Characteristic Symbol Test Conditions Min l\'p Max Unit

Output Voltage Vo Tj =25·C 8.64 9.0 9.36 V

11.5V:5 V,N :5 24V 90 200 mV
Line Regulation !!.VO Tj =25·C
13V:5 V,N :5 24V 1100 1150 lmv
1mAsipuTs100mA 20 90 mV
Load Regulation !!.Vo Tj =25·C
1mAslouT :540mA 10 45 mV
11.5VsV,N s24V 1mA s lOUT s40mA 8.55 9.45 V
Output Voltage Vo 11.5V s Y,N S Vm.,
1mAslouT :570mA 8.55 9.45 V
(Note 2)

I
Quiescent Current Id Tj =25°C 2.1 6.0 mA

Quiescent Current I with line !!.Id 13V sV,NS24V 1.5 mA

Change with load !!.Id 1mA:5louT :540mA 0.1 mA
I
Output Noise Voltage VN T.=25°C,10Hz:5f:5100KHz 70 /LV
!!.Vo -0.9 mV/oC
Temperature Coefficient of VOUT louT=5mA
!!.T

Ripple Rejection RR f =120Hz, 12V SV,N S22V, TI = 25°C 38 44 dB

Dropout Voltage Vo Tj =25°C· 1.7 V
Peak OutpuUShort-Circuit Current Isc Tj =25OC 140 mA

MC78L12AC ELECTRICAL CHARACTERISTICS

Y,N = 19V, lOUT = 40mA, 0·C:5Tj:5125°C, C,N =0.33/LF, CouT =0.1/LF, unless otherwise specified. (Note 1)

Characteristic· Symbol Test Conditions 'Min Tv.p Max Unit

Output Voltage Vo Tj =25°C 11.5 12 12.5 V

14.5V :5 V,N :5 27V 120 250 mV
Line Regulation !!.Vo Tj =25°C
16V:5 V,N :5 27V 100 200 mV
1mAslouT s100mA 20 100 mV
Load Regulation !!.Vo T1=25°C I
1mAs·louT :540mA 10 50 mV
14.5VSV,N S27V 1mAslouTs40mA 11.4 12.6 V
Output Voltage Vo 14.5V S Y,N S Vmax
1mAsloul:570mA 11.4 12.6 V
(Note 2)
Quiescent Current Id Tj =25°C 2.1 6.0 mA
Quiescent Current I with line !!.Id 16V:5 V,N :5 27V 1.5 mA
Change with load !!.Id 1mA:5louT :540mA 0.1 mA
I
Output Noise Voltage VN T.=25°C,10Hz:5f:5100KHz 80 /LV

Temperature Coefficient of VOUT !!.Vo -1.0 mV/oC

louT=5mA
!!.T

Ripple Rejection RR f=120Hz, 15VsV,N :525V, Tj=25°C 37 42 dB

Dropout Voltage Yo· Tj =25OC 1.7 V
Peak OutpuUShort-Circuit Current Isc Tj =25°C 140 mA

c8 SAMSUNG ~EMICONDticroR 357

MC78LXXAC SERIES LINEAR INJEGRATED CIRCUIT

MC78L15AC ELECTRICAL CHARACTERISTICS

V'N =2311, lOUT =40mA, OOC sTj s 125°C, C'N =0.33"F, CouT =0.1jLF, unless otherwise specified. (Note 1)

Characteristic Symbol Test Conditions Min Typ Max Unit

. Output Voltage Vo T1",25OC 14.4 15 15.6 V

17.5V s V'N s 30V 130 300 mV
Line Regulation tNo T1=25°C
20VsV,Ns3OV 110 250 nV
lmAslouTsl00mA 25 150 mV
Load Regulation t:.vo T1=25°C
lmAs louT s40mA 12 75 mV
17.5VsV,Ns3OV lmAslouTs40mA 14.25 15.75 V
Output Voltage Vo 17.5VsV,NsVm• x
lmAsloUTs70mA 14.25 15.75 V
(Note 2)
Quiescent Current Id T1=25°C 2.2 6.0 mA
Quiescent Current I with line .o.ld 20VsV,Ns3OV 1.5 mA
Change with load. .o.ld 1mA s lOUT s40mA 0.1 mA
I
Output Noise Voltage VN T.=25°C,10Hzsfsl00KHz 90 "V
.o.Vo mVloC
Temperature Coefficient of VOUT louT=5mA -1.3
.o.T
Ripple Rejection RR f=l20Hz, 18.5VsV,Ns28.5V, Tj=25OC 34 39 dB
Dropout VoJtage Vo T1=25°C 1.7 V
Peak OutpuUShort-Circuit Current Isc T1=25°C 140 mA

MC78L18AC ELECTRICAL CHARACTERISTICS

V'N =27V, lOUT =40mA, OOC sTj s 125°C, C'N =0.33"F, COUT =0.1 JLF, unless otherwise specified. (Note 1)

Characteristic Symbol Test Conditions Min lYP Max Unit

Output Voltage Vo T1=25°C 17.3 18 18.7 V

21V s V'N s 3311 145 300 mV
Line Regulation .o.Vo T1=25°C
22VsV'NS33V 135 250 mV
lmAslouT:5;I00mA 30 170 mV
Load Regulation .o.Vo T1=25OC
lmAs lOUT s40mA 15 85 mV
21VSV'NS33V lmAslouTs40mA 17.1 18.9 V
Output Voltage Vo 21VsV,NsVmax
lmAs louTs 70mA 17.1 18.9 V
(Note 2)
Quiescent Current Id Tj =25OC 2.2 6.0 mA
Quiescent Current I with line .o.ld 21VsV'NS33V 1.5 mA
Change I with load .1.ld 1mA s l~uTs4OmA 0.1 mA
Output Noise Voltage VN T.=25°C,10Hzsfs100KHz 150 "V
.1.Vo mV/oC
Temperature Coefficient of VOUT louT=5mA -1.8
.1.T

Ripple Rejection RR f=l20Hz, 23VSV'N s 3311, Tj=25OC 34 48 dB

Dropout Voltage Vo T1=25OC 1.7 V
Peak OutpuUShort-Circuit Current Isc T1=25OC 140 mA

c8 SAMSUNG SEMICONDUCTOR 358

MC78LXXAC SERIES LINEAR INTEGRATED CIRCUIT

MC78L24AC ELECTRICAL CHARACTERISTICS

V'N= 33V, louT=40mA, O°CsTjs 125°C, C'N=0.33/LF, CouT =0.1/LF, unless otherwise specified. (Note 1)

Characteristic Symbol Test Conditions Min Typ Max Unit

Output Voltage Vo Tj =25OC 23 24 25 V

27VsV'NS38V 160 300 mV
Line Regulation liNo T j =25°C
28VsV'NS38V 150 250 mV
1mAsiouT s100mA 40 200 mV
Load Regulation t.Vo T j =25°C
1mAsiouT s40mA 20 100 mV
'ZNSV'NS'JW 1mAslouTs40mA 22.8 25.2 V
Output Voltage Vo 'lNSV'NSVmax
1mAslouT s70mA 22.8 25.2 V
(Note 2)
Quiescent Current Id 'TJ =25°C 2.2 6.0 mA

Quiescent Current I with line t.ld 28VsV'NS38V 1.5 mA

Change
I with load t.ld 1mAs louTs40mA 0.1 mA
Output Noise Voltage VN T.=25°C,10Hzsfs100KHz 200 /LV
t.Vo
Temperature Coefficient of VOUT louT=5mA -2.0 mV/oC
t.T

Ripple Rejection RR f=120Hz, 28VsV'NS38V, Tj=25°C 34 45 dB

Dropout Voltage Vo Tj =25°C 1.7 V
Peak Output/Short-Circuit Current lse TJ =25°C 140 mA

Notes
1. The maximum steady state usable output current and input voltage are very dependent on the heat sinking and/or
lead length of the package. The date above represent pulse test conditions with junction temperatures as indicated at
the initiation of tests.
2. Power dissipation sO.75W.

c8 SAMSUNG SEMICONDUCTOR 359

MC78LXXAC SERIES LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS

Fig. 1 QUIESCENT CURRENT va A Fig. 2 DROPOUT VOLTAGE ¥sA
FUNCTION OF INPUT VOLTAGE FUNCTION 0 FJUNCTION TEMPERATURE
71J ,2.5

MC7ILOYC MC7ILOYC
so I
r-- ;;;;;::: ~r"1JmA
i'--
-- ~
-
- --
I - --.; 1our01lJmA t--
I- l"""-
i--
. . . . 1-

21J - h VOOT.5IN DROPOUT CONDmON

IL_4QmA AVo,JT_&MIOFVOUT

IIJ -11 11
1)0 0- - -_. -- r- r-- r- -

o so 10 15 20 25 30 ~ ~ ~ 100 125
1..-uT WlLT_- V JUNCrlON TEMPERATURE - 'C

Fig. 3 QUIESCENT CURRENT va A

FUNCTION OF TEMPERATURE Fig. 4 'DROPOUT CHARACTERISTICS
4.2 so

41J J.J
f': I'.....
VooT_5V
T,025'C
.J~
6.
las .........
~~
I~ ........ 10UT 0 1IJmA2101If.,l,,,,,

I:
"- ..........
,
/.~

2.8
V1Ho1OV
f-- r-VCUToSV
Iii
"1\ 21J

J
•

25 10 75 100 1211 2.0 41J SO SO 10

_~RE_'C INPUTWIL_- V

Fig. 5 RIPPLE REJECTION va A Fig. 6 UNE TRANSIENT RESPONSE

FUNCTION OF FREQUENCY
100 400 20
IIIIII II
VIN-Wto1BV
I! INPUT YOI.1l\GE
·v"",_5V MC7BL
80 - 10UT-4OmA
T,025'C
MC7ILOYC
15

I
i
III

80

40
- I
I\,
OUTPUTVOIJl\GE
DEVlImON

iI!

20
r--,L"00mA<AESIS11lE
Vour_5V
J,..,)
-200
10 100 1K 10K lOOK 6 10 12
FREQUENCY - Hz nME-,.s

c8 SAMSUNG SEMICONDUCTOR 360

MC78LXXAC SERIES LINEAR INTEGRATED CIRCUIT

Fig. 7 LOAD TRANSIENT RESPONSE

Fig. 8 TO-92 WORST CASE POWER DISSIPATION
va AMBIENT TEMPERATURE .

--kJ 200
-
f-
LOADCU~REN 5.0

MC78L05AC 100 i ~ 2D
~
o I;; ~ 1D
~~~~~~:H~ ===
Ic if
I~
WITH ~ HEAr siNK F
r--, 0.126" LEAD LEN~
..~ IU
E H
I f-----1 FROM PC BOARD, ~
Olfll'UTVOLWlE

"L~J~
DEVIImON FREE AIR

a:
"
1·0.1 FROM PC BOARD,
~

,
u FREE AIR ~

-1
rVIN_1OV
§ ;0D5 ,
VouT=5V
D.02

-2
o

APPLICATION INFORMATION
10 20 30
TIME- ..
40 50 50
OD1
26 50 7S 100
AMBIENT TElFEf!AT\lRE - OC
126 150

I
The MC78L series regulators have thermal overload protection from excessive power, internal short-circuit protection which
limits each circuit's maximum current, and output transistor safe-area protection for redUCing the output current as the. voltage
across each pass transistor is increased.
Although the internal power dissipation is limited, the junction temperature must be kept below the maximum specified
temperature (12S°C) in order to meet data sheet specifications. To calculate the maximum junction temperature or heat
sink required, the following thermal resistance values should be used:

Thermal Considerations
The TO·92 molded package manufactured by SST is capable of unusually high power dissipation due to the lead frame
design. However, its thermal capabilities are generally overlooked because of a lack of understanding of the thermal paths
from the semiconductor junction to ambient temperature. While thermal resistance is normally specified for the device
mounted 1cm above an infinite heat sink, very little has been mentioned of the options available to improve on the con·
servatively rated thermal capability. .
An explanation of the thermal paths of the TO·92 will allow the designer to determfne the thermal stress he is applying
in any given application.

The TO-92 Package

The TO-92 package thermal paths are complex. In addition to the path through the molding compound to ambient
temperature, there is another path through the pins, in parallel with the case path, to ambient temperature, as shown in
Figure 1.
The total thermal resistance in this model is then:

(hA = (IIJC + IlCA)(IIJL + IILN

IIJC + IlCA + IIJL + liLA

Where: IIJC = thermal resistance of the case between the regulator die and a point on the case directly above the die
locat!on.
ileA = thermal resistance between the case and air at ambient temperature.
OJL - thermal resistance from transistor die through the collector lead to a point 1116 inch below the regulator case.
OLA = total thermal resistance of the collector-base-emitter pins to ambient temperature.
IlJA = junction to ambient thermal resistance.

c8·SAMSUNG SEMICONDUCTOR 361

MC78LXXAC SERIES LINEAR INTEGRATED CIRCUIT

10-92 Thermal Equivalent Circuit 10-92 Thermal Equivalent Circuit .

(PIN at Other Than Ambient Temperature)

OJL
OJC OJL OJC

OLS ! P(WATTS)

OCA OLA P(WATTS) OCA

OJA

~i~
Ta
II
Fig. 9 Fig. 10

Methods of Heat Sinking

With two external thermal resistances in each leg of a parallel network available to the circuit designer as variables, he
can choose the method of heat sinking most applicable to his particular situation. To demonstrate, consider the effect of
placinfj a small 72.OC1W flag type heat sink, such as the Staver F1-7D-2, on the 78LXX molded case. The heat sink effectively
replaces the OCA (Figure 2) and the new thermal resistanc.e; OJA = 145°CIW (assuming, 0.125 inch led length).
The net change of 15°CIW increases the allowable power dissipation to 0.S6W with an inserted cost of 1-2 cents. A still
further decrease in OJA could be achieved by using a heat sink rated at 46°CIW, such as the Staver FS-7A. Also, if the case
sinking does not provide an adequate reduction in total OJA, the other external thermal resistance, OLA, may be reduced by
shortening the lead length from package base to mounting medium. However, one pOint must be kept in mind. The lead
thermal path includes a thermal resistance, OSA, from the pins at the mounting ·points to ambient, that is, the mounting
medium, OLA is then equal to OLS + OSA. The new model is shown in Figure 2.
In the case of a socket, OSA could be as high as 27Q0CIW, thus causing a net increase in OJA and a consequent decrease
in the maximum dissipation capability. Shortening the lead length may return the net OJA to the original value, but pin
sinking would not be accomplished.
In those cases where the regulator is inserted into a copper clad printed circuit board, it is advantageous to have a max-
imum area of copper at the entry points of the pins. While it would be desirable to rigorously define the effect of PC board
copper, the real world variables are too great to allow anything more than a few general observations.
The best analogy fgr PC board copper is to compare it with parallel resistors. Beyond some pOint, additional resistors
are not significanlly effective; beyond some point, additional copper area is not effective.

High Dissipation Applications

vour
VIN 0---'\111,."..---...-----;
Rl IL
C2 RL

Rl
24011 Vour
VIN ~--r----I
-'L-
10-30mA RL

.c8 SAMSUNG SEMICONDUCTOR 362

MC78LXXAC SERIES LINEAR INTEGRATED CIRCUIT

When it is necessary to operate a MC78LXXAC regulator with a large input-output differential voltage, the addition of
series resistor R1 will extend the output current range of the device by sharing the total power dissipation between R1 and
the regulator.

R1= VINIMIN)-VOUT -,2.0V

ILIMAX)+ 10
Where 10 is the regulator quiescent current.
R,egulator power dissipation at maximum'input voltage and maximum load current is now
Po (MAX) = (V3 - VO~T) ILIMAX) + V31a
where V3= V'NIMAx)-(lc(MAx) + 10) R,

The presence of R1 will affect load regulation according to the equation:

load regulation (at constant V ,N)
=Ioad regulation (at constant V3)
+(Iine regulation, mV per V)
x(R1)x(IlIL).
As an example, consider a 15V regulator with a supply voltage of 30±5V, required to supply a maximum load current
of 30mA. 10 is 4.3mA, and minimum load current is to be 10mA.

R, = 25 - 15 - 2 = 34.3 = 2400
30+4,3 8
I
V3 = 35 - (30 + 4.3) x 0.24 = 35.82 = 26,8V
Po IMAX) = (26.8 -15) 30 + 26.8 (4.3)
=354+ 115
=470mW, which permit operation up to 70°C
in most applications.,

Line regulation of this circuit is typically 110mV for an input range of 25 - 35V at a constant load current; ,Le. 11 mVN
Load regulation=constant V, load regulation (typically 10mV, 10-30mA IL)
+(11mVNxO.24x20mA (typically 53mV)
=63mV for a load current change of 20mA at a constant V ,N of 30V.

Typical Application

INPUT o------~---_i I-----~-----O OUTPllT

C1
O,33pF O,1pF
"IOTE2 NOTE 2

Notes
1. To specify an output voltage, substitute voltage value for "xx".
2, Bypass Capacitors are recommended for optimum stability and transient response and should be locate as close as
possible to the regulator.

c8 SAMSUNG SEMICONDUCTOR 363

MC18MXXC SERIES LINEAR INTEGRATED CIRCUIT

3-TERMINAL O.5A POSITIVE TO·220

VOLTAGE REGULATOR
The Mc78MXXC series of three-terminal positive regulators Is available
1'0-220 package with seversl fixed output voltages, making it useful in
a wide rsnge of applications. These reglators can provide local on-card
regulation, eliminating the distribution problems associated with single
point regulation. Each type employs intemal current limiting, thermal
shut-down and safe area protection, making it essentially indestructible.
If adequate heat sinking is provided, they can deliver over O.5A output
cyrrent. Although designed primarily as fixed voltage regulators, these
devices can be used with external components to obtain adlustable
voltages and currents.

FEATURES
• Output Current up to 0.sA
• Output YoItagM of 5; 8; 8; 10; 12; 15; 18; 20; 24V 1: Input 2: GND 3: OUtput
• Thennal OwrIoed Protection
• Short Circuit ProtectIon ORDERING INFORMATION
• Output 'ftIIn-.aor SOA ProIecIIon
Device Package Operating Temperature
MC78MXXIT TO·220 -40- + 125·C
BLOCK DIAGRAM MC78MXXCT TO·220 O·C -+125·C

IN PUT SERIES OUTPUT

PASS
1 ELEMENT 3

CURRENT SOA
GENERAIOR PROI'ECTION ~~R20

SIMTlNG REFERENCE ERROR

CIRCUIT \IOL1I\GE AMPUFIER
t-:-

,
~ R19
THERMAL
PROrECTION - ~

GNo

Fig: 1

c8~SUNG SEMICONDUCTOR. 364

MC78MXXC SERIES LINEAR INTEGRATED CIRCUIT

SCHEMATIC DIAGRAM

r----~----~---~-~-___t"--...,.--oIN

All
~~--r-+--~---+-~OUT

A20

A19
II
Fig. 2

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Input'Voltage (for Vo = 5V to 18V) Vi 35 V

(for Vo=24V) Vi 40 V
Thermal Resistance Junction-Cases 9 JC 5 ·crw
Thermal Resistance Junction-Air 9 JA 65 ·crw
Operating Temperature Range MC78XXI Top, -40-+125 ·C
MC78XXC/AC 0-+ 125 ·C
Storage Temperature Range T.tg -65- +150 ·C

c8 SAMSUNG S~MICONDUcroR 365

MC78MXXC SERIES LINEAR INTEGRATED CIRCUIT

·ELECfRICAL CHARACfERISTICS MC78M05C

(Refer to the test circuits, Tmln:sTj:s125°C, 10 = 350mA, VI = 10V, unless otherwise specified, Ci =0.33J.1F, Co = 0.1J.1F)

Characteristic Symbol Test Conditions. Min Typ Max Unit

Tj =25°C 4.8 5 5.2
Output Voltage Vo 10 = 5 to 350mA 4.75 5 5.25 V
Vi =7to 20V
VI=7to 100
25V
Line Regulation {:;.V~ 10 = 200mA mV
Vi=8to 50
25V
10 = 5mA to 0.5A 100
Load Regulation /:,Vo mV
10 =5mA to 200mA 50
Quiescent Current Id 6 mA
10 =5mA to 350mA 0.5
Quiesce.nt Current Change /:'Id 10=200mA 0.8 mA
Vi=8t025V
/:,Vo 10=5mA
Output Voltage Drift -0.5 mVfOC
/:,T Tj =0 to 1250C
Output Noise Voltage VN f = 10Hz to 100KHz 40 J.lV
f=120Hz 10=300mA 62
Ripple Rejection RR dB
Vi=8to 18V
Dropout Voltage Vo Tj = 25°C, 10 = 500mA 2 V
Short Circuit Current lac Tj = 25°C, Vi = 35V 300 mA
Peak Current lpeak Tj =25OC 700 mA
* Tmin
MC78MXXI: Tmin = - 40°C
MC78MXXC: Tmin = O°C

c8SAMSUNGSEMICONDU~R . 366
MC78MXXC SERIES LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC78M06C

(Refer to the test circuits, Tmin !!OTj !!0125·C, 10 = 350mA, Vi = l1V, unless otherwise specified, Ci =O.33,..F, Co = 0.1,..F)

Characteristic Symbol Test Conditions Min lYP . Max Unit

Tj =25°C 5.75 6 6.25

Output Voltage Vo 10 = 5 to 350mA V
5.7 6 6.3
Vi =8t021V
Vi=8to 100
25V
Line Regulation b.Vo 10=200mA mV
Vi=9to 50
25V
10 = 5mA to 0.5A 120
Load Regulation

I
b.Vo mV
10 =5mA to 200mA 60
Quiescent Current Id 6 mA

10 =5mA to 350mA 0.5

Quiescent Current Change b.ld 10=200mA 0.8 mA
Vi =9t025V
b.Vo ·l o=5mA
Output Voltage Drift -0.5 mVI"C
b.T Tj =0 to 125°C
Output Noise Voltage VN f = 10Hz to 100KHz 45 /LV
f = 120Hz 10 =300mA 59
Ripple Rejection RR dB
Vi=9to 19V

Dropout Voltage Vo Tj =25·C, 10 = 500mA 2 V

Short Circuit Current lee Tj =25·C, Vi = 35V 270 mA

Peak Current Ip••k Tj =25·C ·700 mA
* Tm1n
MC78MXXI: Tmin= -40·C
MC78MXXC: Tmin=O·C

c8 SAMSUNG SEMICONDUCTOR 367

MC78MXXC SERIES LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC78M08C

(Refer to the test circuits, TminST/S125·C, 10 = 350mA,Vi = 14V, unless otherwise specified, Ci =0.33/LF, Co = O.l/LF)

Characteristic Symbol Test Conditions Min . Typ Max Unit

T/=25°C 7.7 8 8.3

Output Voltage Vo 10 = 5 to 350mA V
7.6 8 8.4
Vi = 10.5 to 23V
Vi= 10.5 to 100
25V
Line Regulation ,6,Vo 10=200mA mV
Vi =11 to. 50
25V
. 10 = 5mA to 0.5A 160
Load Regulation . ,6,Vo mV
10=5mA to 200mA 80

Quiescent Current Id 6 mA

10=5mA to 350mA 0.5

Quiescent Current Change ,6,1. 10=200mA 0.8 mA
V, = 10.5 to 25V
,6,Vo 10=5mA
Output Voltage Drift -0.5 mVI"C
,6,T Tj =0 to 125°C

Output Noise Voltage VN f = 10Hz to 100KHz 52 /LV

f= 120Hz 10=300mA 56
Rippl'e Rejection RR dB
Vi =11.5 to 21.5V I
Dropout VolJage VO I, = 25·C, 10 =·500mA 2 V
Short Circuit Current I.e Tj=25°C, Vi = 35V 250 mA

. Peak Current Ipeak T,=250C 700 mA

*·Tm1n
MC78MXXI: Tmin= -40·C
MC78MXXC: Tmin=O·C

c8 SAMSUNG SEM~CONDUcroR 368

MC78MXXC SERIES LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC78M10C

(Refer to the test circuits, Tm;n:sTJ:S 125°C, 10 = 350mA, V, = 17V, unless otherwise specified, C, = 0.33/tF, Co = 0.1/tF)

Characteristic Symbol Test Condition Min Typ Max Unit

TJ=25°C 9.6 10 10.4

Output Voltage Vo 10 = 5 to 350mA V
9.5 10 10.5
V; = 12.5 to 25V
V, = 12.5 to
100
25V
Line Regulation 11 Vo 10 = 200mA mV
V;=13 to
50
25V
10 = 5mA to 0.5A 200
Load Regulation 11 Vo mV
10 = 5mA to 200mA 100
Quiescent Current Id TJ=25°C 6 mA
10 = 5mA to 350mA 0.5
Quiescent Current Change I1ld 10 = 200mA mA
0.8
V; = 12.5 to 25V
I1Vo . 10=5mA
Output Voltage Drift -0.5 mV/oC
I1T Tj=O to 125°C
Output Noise Voltage VN f = 10Hz to 100KHz 65 /tV
f = 120Hz, 10 = 300mA
Ripple Rejection RR 55 dB
V;=13 to 23V
Dropout Voltage VD Tj =25°C,l o=500mA 2 V
Short Circuit Current Isc Tj = 25°C, V; = 35V 250 mA
Peak Current Ipeak Tj =25°C 700 mA
.,. Tmin
MC78MXXI: Tm;n = - 40°C
MC78MXXC: Tmin = O°C

c8 SAMSUNG SEMICONDUCTOR 369

MC78MXXC SERIES LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC78M12C

(Refer to the test circuits, Tm'n~Tj~125°C, 10 = 350inA, Vi = 19V, unless otherwise specified, C, =O.33,..F, Co=0.1,..F)

Characteristic Symbol Test Condition Min Typ Max . Unit

Tj=2!'1°C 1l.5 12 12.5

Output Voltage . Vo 10 = 5 to 350mA V
11.4 12 12.6
V, = 14.5 to 27V
V,= 14.5 to
100
30V
Line Regulation 6V o 10 = 200mA mV
V,=16 to
50
30V
10 = 5mA to 0.5A 240
Load Regulation 6V o mV
10 = 5mA to 200mA 120
Quiescent Current . Id Tj =25·C 6 mA
io = 5mA to 350mA 0.5
Quiescent Current Change 61d 10=200mA mA
0.8
V, = 14.5 to 30V
6Vo 10=5mA
Output Voltage Drift . 6T -0.5 mV/·C
Tj = 0 to 125°C
Output Noise Voltage liN f = 10Hz to 100KHz 75 ,..V
f = 120Hz, 10 = 300mA
Ripple Rejection RR 55 dB
V,= 15 to 25V
Dropout Voltage Vo Tj =25·C,l o =500mA 2 V
Short Circuit Current Ise Tj =25·C, V,=35V . 240 mA
Peak Current I peak Tj =25·C 700 mA

* Tmm
MC78MXXI: Tm'n= -40·C
MC78MXXC: Tmin=O·C

c8 SA'MSUNG SEMICONDUCTOR 370

MC78MXXC SERIES LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC78M15C

(Refer to the test circuits, Tm'nSTJS125·C, 10= 350mA, V, = 23V, unless otherwise specifi~d, C,·=O.33/LF, Co=0.1/LF)

Characteristic Symbol Test Conditions Min Typ Max Unit

TJ =25°C 14.4 15 15.6

Output Voltage Vo 10 = 5 to 350mA V
14.25 15 15.75
'\t,= 17.5 to 30V
VI= 17;5 to 100
30V
Line Regulation 6Vo 10 = 200mA -
mV
V,=20to 50
30V
._. ---------
10 = 5mA to 0.5A 300

II
Load Regulation 6Vo mV
10 =5mA to 200mA . 150

Quiescent Current Id 6 mA

10 =5mA to 350mA 0.5

1-'--"
Quiescent Current Change 61. 10=200mA 0.8 mA
VI = 17.5 to 30V
6Vo 10=5mA
Output Voltage Drift -1 mVI"C
6T TJ =0 to 125~C
Output Noise Voltage VN f = 10Hz to 100KHz 90 /LV
f = 120Hz 10 =300mA 54
Ripple Rejection RR dB
VI =18.5 to 28.5V
f--.
Dropout Voltage Vo Tj = 25·C, 10 = 500mA 2 V

Short Circuit Current Isc TJ = 25·C, VI = 35V 240 mA

f--.
Peak Current Ipeak TJ =25°C 700 mA
.. Tm1n
MC78MXXI: Tm,n= -40·C
MC78MXXC: Tm,n=O·C

c8 SAMSUNG SEMICONDUCTOR ·371

MC78MXXC SERIES LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC78M18C

(Refer to the test circuits, Tmtn STjS125·C, 10 = 350mA, V, = 26V, unless otherwise specified, C i = O.33/LF, Co = 0.1/LF)

Characteristic Symbol Test Conditions Min Typ Max Unit

Tj =2SoC 17.3 18 18.7

Output Voltage Vo 10 = S to 3S0mA V
17.1 18 18.9
Vi = 20.S to 33V
Vi =21 to 100
33V
Line Regulation !:,Vo 10=200mA mV
V,=24to SO
33V
10 = SmA to O.SA 360
Load Regulation !:,Vo mV
10 =SmA to 200mA 180

Quiescent Current Id 6 mA

10 =SmA to 3S0mA O.S

Quiescent Current Change !:'Id 10=200mA 0.8 mA
V,=21 t033V
!:,Vo 10=SmA
Output Voltage Drift !:,T· -1.1 mVI"C
Tj=Oto 12SoC

Output Noise Voltage VN f = 10Hz to 100KHz 100 ,.V

f=120Hz 10=300mA S3
Ripple Rejection RR dB
V,=22t032V

Dropout Voltage VD Tj =2S·C,l o =5OOmA 2 V

Short Circuit Current Iso Tj = 25·C, Vi = 35V 240 mA

Peak Current lpeak Tj =2SoC 700 mA

. . Tm1n
MC78MXXI: Tmin = - 40·C
MC78MXXC: Tmin = O·C

c8 SAMSUNG SEMICONDUCTOR 372

MC78MXXC SERIES LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC78M20C

(Refer to the test circuits, T m,n!5:Tj !5:125·C, 10 = 350mA, Vi = 29V, unless otherwise specified, C, =0.33/LF, Co=0.1/LF)

Characteristic Symbol Test Conditions Min Typ Max Unit

Tj =25°C 19.2 20 20.8

, Output Voltage Vo 10 = 5 to 350mA 19 20 21
.v
Vi =23to 35V
V,=23to 100
35V
Line Regulation 6Vo 10 = 200mA mV
V,=24to 50
35V
10 = 5mA to 0.5A 400
Load Regulation 6Vo oW

Quiescent Current

Quiescent Current Change

Id

61d
10 =5mA to 200mA

10 =5mA to 350mA
10=200mA
200

6
0.5
0.8
mA

mA
II
V,=23 to 35V
6Vo 10=5mA
Output Voltage Drift -1.1 mVJOC
6T T, =0 to 125°C
Output Noise Voltage VN f = 10Hz to 100KHz 110 /LV
f=120Hz lo=300mA 53
Ripple Rejection RR dB
Vi =24t034V I
Dropout Voltage Vo T,=25·C,lo=500mA 2 V
Short Circuit Current Iso T, = 25·C, V, = 35V 240 mA

Peak Current Ipeak T,=25°C 700 mA

* Tmm
MC78MXXI: Tm,"= -40·C
MC78MXXC: Tmin=O·C

ciS SAMSUNG SEMICONDUCTOR 373

MC78MXXC SERIES LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC78M24C

(Refer to the test circuits, Tmin:sTj:S 125°C, 10 = 350mA, Vi == 33V, unless otherwise specified, C, = O.33/LF, Co = 0.1/LF)

Characteristic Symbol Test Conditions Min Typ Max

T,=25OC 23 24 25
Output Vohage. Vo 10 = 5 to 350mA V
22.8 24 25.2
V,=27t038V

V,=27to 100
38V
line-Regulation' /':,.Vo io=,200mA mV
V,=28to 50
38V I
10 = 5mA to O.SA 480
Load Regulation /':,.Vo mV
10 =5mA to 200m.l\ 240

Quiescent Current Id 6 mA

10 =5mA to 350mA 0.5

Quiescent Current Change /':,.Id 10=2oomA 0.8 mA
V,=27to38V
/':,.Vo 10=5mA
Output Voltage Drift -1.2 mVfOC
/':,.T TJ =0 to ,125°C

Output Noise Voltage VN f = 10Hz to 100KHz 170 /LV

f= 120Hz 10=3OOmA 50
Ripple Rejection RR dB
V,=28to38V I
Dropout Voltage Vo T j =25·C,lo=500mA 2 V

Short Circuit Current I", 'V,=35V 240 mA

Peak Current lpeal< T,=25°C 700 mA

* Tmin
MC78MxXl: Tm'n=-40·C
MC78MXXC: Tmin = O·G '

c8 SAMSUNG SEMICONDUCTOR' 374

MC78MXXC SERIES LINEAR INTEGRATED CIRCUIT

APPLICATION CIRCUIT

Fixed output regulator Constant current regulator

F-~--oVOUT VINo--_-I

vxx

Fig. 3

Notes:
(1) To specify an output voltage, substitute voRage value for "XX".

I
(2) Although no output capacitor is needed for stability, it does
improve transient response.
(3) Required if regulator is located 'an appreciable distance from
power supply filter. . Adjustable output regulator (7 to 3OV)

Circuit for increasing output voltage

VOUT
VOUT
Rl

IR,;;':5I d
R2
Vo =Vxx (1+R2/R,)+ld R2

0.5 to 10V regulator

13V<V,N<25V 3
F - - - r - r - - - - f - - -......-_1----<D VoUT
R4
Cl 9100
vxx

1
·7V<-V,N<·I7V
R5
9.1kO

6
10kO
C2
0.1""

Fig. 7
High current voltage regulator

V,No--~-...=.:.c.::.:;::..=---------,
R _ VBEO'
'-"----
IREo-~
Bo,
!-=--+--oVOUT

cR" SAMSUNG SEMICONDUCTOR 375

MC78MXXC SERIES LINEAR INTEGRATED CIRCUIT

APPLICATION CIRCUIT (continued)

High output current with short circuit protection Tracking voltage regulator

Rsc VOUT

Q2
Rl 4.7kll

31l VOUT
COMMON
J('
Rse VBEOQ2 4.7kll
=~

Fig. 9
VOUT
Fig. 10
High input voltage circuit Reducing POYler dissipation with dropping resistor

t-"?--QVOUT

RL

R= V, (min) - Vxx - VORO• (max)

Fig. 11 10 (max)+ld (max)
Fig. 12

Power AM modultor (unity voltage gain, 10 .;; 0.5) Adjustable output voltage with temperature
compensation .

Vo

Y,N o-~--f vxx~ Y,N F---~--O VOUT

~--o
Rl ! Vxx

~ Modulation
Signal

Note: The circuit performs well up to 100 KHz.

Fig. 13 Fig. 14
. Note: Q2 is connected as a .diode in order to compensate the
variation of the Ql VBE with the temperature. C allows a
slow rise-time of the Vn
Vo =Vxx (1+~)+VBE
R,

c8 SAMSUNG SEMICONDUcrO'~ 376

 MC79XX SERIES LINEAR INTEGRATED CIRCUIT

3-TERMINAL NEGATIVE
TO·22O
VOLTAGE REGULATOR
The MC79XXC series ofthree-terminal negative regulators is available in
10-;120 package and with several output voltages. They/canprovideslocal
on-card regulation, eliminating the distribution problems associated with
single point regulation; furthermore, having the same voltage options as
th~MC78XXCpositive standard series, they are particularly suited for split
power supplies. " - .
If adequate heat sinking is provided, the MC79XXC series can deliver an
output current in excess of 1.5A. Although designed primarily as fixed
voltage regulators, these devices can be used with external components
to obtain adjustable voltages and currents.

II
FEATURES
• Output Current up to 1.SA
• Ouput Voltages of - 2V, - SV, - 6V, - 8V, -12V, -1SV, 'I: GND 2: Input 3: Output
-18V, -24V
,. Thermal Overload Protection ORDERING INFORMATION
• Short Circuit Protection
• Output Transistor SOA ProtectIon Operating Temperature
0-125°C
SCHEMATIC DIAGRAM

R15

R16

.--1--'------4-0 OUT

R23

~~~-~-~---~------~~~---------~~--------~~IN

c8 SAMSUNG SEMICONDUCTOR 377

MC79XX SI;RIES LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Input Voltage (for V,;: - 2 to -18V) Vi -35 V

(for Vo = - 24V) V, -40 V
Thermal Resistance Junction-Case 6 Jc 5 °CIW
Junction-Air. 6 JA 65 OCIW
Operating Temperature Range Topr 0- +125 °C
Storage Temperature Range Tstg . -65-+125 .oC

ELECTRICAL CHARACTERISTICS MC7902C

(C,=2.2/LF, Co=1/LF, Tj=O to 125°C, 10=5OOrnA, V,=10V, unless otherwise specified)

Characteristic Symbol Test Conditions. Min Typ Max Unit

Tj =25°C -1.92 -2 -2.08

Output Voltege Vo 10=5mA to 1A PoS15W -1.9 -2 -2.1 V
V, = -7to -20V

V,= -7to 40
-25V
Line Regulation /:;Vo Tj =25°C mV
V, = -8to 20
-12V

Tj =25.oC
70 120
10=5mA to 1.5A
Load Regulation . /:;Vo mV
Tj =25°C
20 60
10 =250 to 750mA

Quiescent Current Id Tj.=25°C 3 6 rnA

10=5rnAto lA 0.5
Quiescent Current Change /:;Id
1.3 rnA
Vi= -7to -25V

/:;Vo
Output Voltage Drift 10=5rnA -0.4 rnVJOC
""ZT
f = 10Hz to 100KHz
Output Noise Voltege VN 40 /LV
Tj =25°C
f=120Hz
Ripple Rejection RR 54 60 dB
/:;V,=10V

Tj =25°C
Dropout Voltege Vo 3.5 V
10=1A

Short Circuit Current lac T,=25°C. 2.2 A

Peak Current 1- Tj=25°C 2.5 A

c8 SAMSUNG SEMICONDUCTOR 378

MC79XX SERIES LINEAR INTEGRATED CIRCUIT.

ELECTRICAL CHARACTERISTICS MC7905C

(C, = 2.2/LF, Co = 1/LF, T, = 0 to 125°C, 10 = 500mA, V, = 10V, unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

Tj =25OC -4.8 -5 -5.2

Output Voltage Vo 10=5mA to 1A, Po!!>15W V
-4.75 -5 . -5.25
V, = -8to -20V
V,= -7to 100
-25V
Line Regulation 6Vo T,=25°C mV
V, = -8to 50
-12V
Tj =25°C
1Q()

II
lo=5mA to 1.5A
Load Regulation 6Vo rrW
TJ=25°C
50
10 =250 to 750mA
Quiescent Current I. T,=25°C 3 6 mA

lo=5mAto 1A 0.5
Quiescent Current Change 61d mA
1.3
V,= -8to -25V

6Vo
Output Voltage Drift lo=5mA -0.4 rrWfOC
6T

f = 10Hz to 100KHz
Output Noise Voltage VN 100 /LV
TJ=25°C
f=120Hz
Ripple Rejection RR 54 60 dB
6V,=10V

TJ=25°C
Dropout Voltage Va 2 V
lo=1A

Short Circuit Current loe TJ=25°C 2.1 A

Peak Current I peak TJ=25OC 2.5 A

c8 SAMSUNG SEMICONDUCTOR 379

MC79XX SERIES LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7906C

(C,=2.2/LF, Co=1/LF, TJ=O to 125·C, 10=500mA, Vi =11V, unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

, TJ=25°C -5.75 -6 -6.25
Output Voltage Vo V
10=5mA to 1A, Po:s15W -5.7 -6 -6.3
V,= -9to -21V

Vi= -8 to . 120
-25V
Line Regulation /',Vo Tj =25°C mV
V,= -9to 60
-13V

Tj =25°C
120
10=5mA to 1.5A
Load Regulation /',Vo mV
T,=25°C
60
10 =250 to 750mA

Quiescent Current Id T,=25°C 3 6 mA

lo=5mAto 1A 0.5
Quiescent Current Change /',Id 1.3
mA
V,= -9to -25V

/',Vo
Output Voltage Drift
--z:r 1.=5mA -0.5 mVI"C

f = 10Hz to 100KHz
Output Noise Voltage VN . 130 /LV
TJ =25°C
f=120Hz
Ripple Rejection RR /',V,=10V
54 60 dB

TJ =25°C
Dropout Voltage VD 2 V
lo=1A

Short Circuit Current Iso T j =25·C 1.8 A

Peak Current lpeak TJ =25°C 2.5 A

·cR SAMSUNG SEMICONDUCTOR 380

MC79XX SERIES LINEAR INTEGRATED CIRCUIT

. ELECTRICAL CHARACTERISTICS MC7908C

(C, = 2.2/LF, Co = l/LF, TJ= 0 to 125°C, 10 = 500mA, V, = 14V, unless otherWise specified)

Characteristic Symbol Test Conditions Min lYP Max Unit

TJ=25°C -7.7 -8 -8.3

Output Voltage Vo V
10=5mAto lA, Pos15W -7.6 -8 -8.4
V,= -11.5to -23V I
V,= -10.5to 160
-25V
Line Regulation /;,Vo Ti=25°C mV
V,=-llto 80
-17V

TJ",25°C
160
Load Regulation

Quiescent Current
/;,Vo

I.
10 =5mA to 1.5A

TJ=25°C
10 =250 to 750mA

TJ=25°C 3
80

6
mV

mA
II
10=5mAto lA 0.5
Quiescent Current Change /;,1. mA
1
V, = - 11.5 to - 25V

/;,Vo
Output Voltage Drift 10=5mA -0.6 mVfOc
6T
f = 10Hz to 100KHz
Output Noise Voltage VN 175 /LV
TJ=25°C

f=120Hz
Ripple Rejection RR 54 60 dB
/;,V,=10V

TJ=25°C
Dropout Voltage VD 2 V
10=lA

Short Circuit Current Ise TJ=25°C 1.5 A

Peak Current Ipeak TJ=25°C 2.5 A

ciS SAMSUNG SEMICONDUCTOR 381

MC79XX SERIES LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7912C

(CI =2.2,.F, Co = l,.F" Tj =0 to 125°C, 1.=500mA, Vi ';'18V, unless otherwlse'specified)

Characteristic Symbol Test Conditions Min 'iYP Max Unit

Tj=25°C -11.5 -12 -12.5

Outpu1 Voltage V. 1.=5mA to lA, P.s15W -11.4 -12 -12.6 V
VI= -15.5to -27V

Vi= -14.5to 240

-30V
Line Regulation /::,.V. Tj = 25°C mV
Vi= -16to 120
-22V I
Tj =25°C
240
1.=5mA to 1.5A
Load Regulation /::,.V. rrW
TJ =25°C
120
I. =250 to 750mA
Quiescent Current Id Tj =25°C 3 6 mA

I. ,.5mA to lA 0.5
, Quiescent Current Change /::"Id 1 mA
VIZ -15to -30V

/::,.V.
Output Voltage Drift 1... 5mA -0.8 rrWf'C
/::,.T

f = 10Hz to 100KHz
Output Noise Vohage VN 200 ,.V
Tj ",,25°C
f=120Hz
Ripple Rejection RR 54 60 dB
/::,.VI=10V

Tj =25°C 2
Dropout. Voltage Vo V
1.-1A

Short Circuit Current I"" Tj ';'25°C 1.5 A

Peak Current lpeak Tj =25°C 2.5 A

c8 SAMSUNG SEMICONDUCTOR 382

MC79XX SERIES LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7915C

(C, = 2.2/.1F, Co = 1/.1F, T, = 0 to 125°C, 10 = 5OOmA, v, = 23V, unless otherwise specified)
Characteristic Symbol Test Conditions Min ~p Max Unit

TJ =25"C -'14.4 -15 -15.6

Output Voltage Vo 10=5mA to 1A, PoS15W -15 V
-14.25 -15.75.
V,=-18to -30V
V,= -17.5to 300
-30V
Line Regulation 6.Vo Tj =25°C mV
V,: -20to 150
-26V
TJ =25°C
300

I
lo=5mA to 1.5A
Load Regulation 6.Vo rrt./
Tj =25"C
150
10 =250 to 750mA
Quiescent Current I. TJ =25°C 3 6 mA

lo=5mAto 1A 0.5
Quiescent Current Change 6.1. mA
1
V, = -18.5to -30V

6.Vo
Output Voltage Drift 6.T . lo=5mA -0.9 rrt.//"C

f = 10Hz to 100KHz
Output Noise-Voltage VN 250 /.IV
Tj =25°C
f=120Hz
Ripple Rejection , RR 54 60 dB
6.V, =10V

Tj =25°C
Dropout Voltage Vo 2 V
lo=1A

Short Circuit Current I.. Tj =25°C 1.3 A

Peak Current lpeak TJ =25"C 2.2 A

c8 SAMSUNG SE~IC9NDUCTOR 383

MC79XX SERIES LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7918C

(C,=2.2,..F, Co ·=1,..F, TJ=O to 12S0C, 10=500mA, V,=27V, unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

TJ=25°C -17.3 -18 -18.7

Output Voltage Vo V
10=5mA to 1A, PoS 15W -17.1 -18 -18.9
V,= -22.5 to -33V I
.1
V;= -21 to . 360
. -33V I
Line Regulation /',Vo TJ=25°Cr- mV
I
V;= -24to 180
-30V
._-
TJ =2SoC
360
lo=SmAt01.5A
Load Regulation /',Vo mV
TJ=25°C
180
10 =250 to 750mA
Quiescent Current Id T,=25°C 3 6 mA

10=5mAto 1A O.S
Quiescent Current Change /',Id mA
1
V,= -22to -33V

/',Vo
Output Voltage Drift lo=5mA -1 mVI"C
/',T
----

V N' f = 10Hz to 100KHz

Output Noise Voltage 300 ,..V
TJ =2SoC

f=120Hz
Ripple Rejection RR 54 60 dB
/',V,=10V
-----

TJ =25°C
Dropout Voltage VD 2 V
lo=1A

Short Circuit Current loe T,=2SoC 1.1 A

- - f--
Peak Current Ipeak TJ7 25°C 2.2 A

c8 SAMSUNG SEMICONDUCTOR 384

MC79XX SERIES LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7924C

(C,=2.2/LF, Co=1/LF, TJ=O to 125°C, 10=500rnA, V,=33V, unl.ess otherwise specified)

CharaCteristic Symbol Test Conditions Min Typ Max Unit

TJ=25°C -23 -24 -25

Output Voltage
r--- V
Vo 10= 5rnA to 1AJPo:!>15W -22.8 -24 -25.2
V,= -27to -38V
-- -
V,= -27to 480
-38V
Line Regulation 6Vo TJ=25°C rnV
V,= -30to 240
-36V
_. - - f---.
TJ=25°C
480

I
10 =5mA to 1.5A
load Regulation 6Vo mV
TJ=25°C
240
10 =250 to 750mA
Quiescent Current 10 TJ=25°C 3 6 rnA

10=5mAto 1A 0.5
1---
Quiescent Current Chang,e 610 mA
1
V,= -27to -38V I

6Vo ,
Output Voltage Drift 10=5mA -1 mV/oC
LS:T
f = 10Hz to 100KHz
Output Noise Voltage VN 400 /LV
TJ=25°C
f=120Hz
Ripple Rejection RR 6V,=10V
54 60 dB

TJ=25°C
Dropout Voltage VD 2 V
10=lA

Short Circuit Current Iso TJ=25'C 1.1 A

Peak Current Jpeak TJ=25°C 2.2 A

c8 SAMSUNG SEMICONDUCTOR 385

MC79XX SERIES LINEAR INTEGRATED CIRCUIT

APPLICATION INFORMATION

Fig. 1 -:- Fixed output regulator

Note.: .
(1) To specify an output voltage, substitute voltage value for
"XXC".
(2) Required for stability. For value given, capacitor must be solid
tantalum. If aluminium electrolitics are used, at least ten times
value shown should be selected. CI is required if regulator is
~~-O-Vo
located an appreciable distance from power supply filter.
(3) To improve'transient response. If large capacitors are used, a
high current diode from input to output (1N4001 or similar)
should be introduced to protect the device from momentary in-
put short ~ircuit.

Fig. 2 - Split power supply (±1SVl1A) Fig. 3 - Circuit for increasing output voltage

+2fN 0--.,.--1

-2fN -15V

R1+R2
Vo-VXX' ."!i2"
• Against potential latch-up problems. VXXIR2 > 31d

• C3 optional for impi'Oved transient response and

ripple rejection.

Fig. 4:"" High current negative regulator (-SVI4A with Fig. S - Typical ECl system power supply (-S.2VI4A)
SA current limiting)

-lOll -12\1

• Optional dropping resistor to reduce the power

dissipated in the boost transistor. .

c8 SAMSUNG SEMICONDUCTOR 386

 MC79XX SERIES LINEAR INTEGRATED CIRCUIT

3-TERMINAL O.SA NEGATIVE

TO-220
VOLTAGE REGULATOR
The MC79MXXlseries of 3-Terminal medium current negative voltage
regulators are monolithic integrated circuits designed as fixed voltage
regulators. These regulators employ internal current limiting, thermal
shutdown and safe-area compensation making them essentially inde-
structible. If adequate heat sinking is prOVided, they can deliver up to
500mA output current. They are intended as fixed voltage regulators in
a wide range of applications including local (on-card) regulation for elimi-
nation of noise and distribution problems associated with single point
regulation. In addition to use as fixed voltage regulators, these devices
can be used with external components to obtain adjustable output
voltages and currents.

FEATURES
•
•
•
•
Output current In excess of O.SA
Internal thermal-overload protection
Internal short circuit current limiting
Output trenslstor safe-area compensation ORDERING INFORMATION
1: GND 2: Inpul 3: Oulpul
I
• Available In JEDEC TO·220
.• Output voltages of - 5V, - 6V, - 8V, -12V, Operating Temperature
-15V, -18V, - 24V o -125°C
SCHEMATHIC DIAGRAM

Rll

R14 R15,
R12

R16

r---~------+-OOUT

R23
L---~--~--~~----~~------------~~~------ ________ __ ____________
~ ~ ~~IN

c8 SAMSUNG SEMICONDUCTOR 387

MC79MXX. SERIES LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol value Unit

Input Voltage (for Vo = - 5V to - 1.8V) VI -35 V

(for Vo=24V) VI -40 V
Thermal Resistance
Junction-Case 9 Jc · 5 °CIW
Junction-Air 9JA 65 OCIW
Operating Temperature Range Top. 0-+125 OC
Storage Temperature Range Tsig -65-+150 °C

TYPICAL APPLICATION
Bypass capacitors are recommended for stable operation of the
MC79MXXC series of regulators over the input voltage and output
current ranges. Output bypass capacitors will improve the transient
response of the regulator. .
The bypass capacitors, (2,..F on the input, 1,..F on the output) should be
ceramic or solid tantalum which have good high frequency characteris-
tics. If aluminum electrolytiqs are used, their values should be 1O,..F or
larger. The bypass capacitors should be mounted with the shortest leads,
and if possible, directly across the regulator terminals.

Fixed Output Regulator

VIN --...----1 I - -......--VOUT

2.0~F l.o~F

ciS SA~SUNG SEMICONDUCTOR 388

MC79XX SERIES LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC79M05C

(Refer to test circuit, O°C<Tj < 125°C, 10 = 350mA, V; = -10V, unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

Tj =25°C -4.8 -5.0 -5.2

Output Voltage Vo 5.0mAslos350mA V
V, = - 7V to - 25V -4.75 -5.0 -5.25
V; = - 7V to - 25V 7.0 50
Line Regulation f',Vo TJ=25°C mV
V;= -8V to -18V 2.0 30
Load Regulation f',V o Tj =25°C 10 = 5.0mA to 500mA 30 100 mV
Quiescent Current Id Tj =25°C 3 6 mA
10 = 5.0mA to 350mA 0.4

II
Quiescent Current Change f',ld mA
V;= -8V to -25V 0.4
Output Voltage Drift f',VoIf',T 'o=5mA 0.2 mV/oC
Output Noise Voltage VN f = 10Hz to 100KHz Tj = 25°C 40 ,.V
Ripple Rejection RR f=120Hz,V,=-8to -18V 54 60 dB
Dropout Voltage Vo 10 = 500mA, Tj =25°C 1.1 V
Short Ci rcuit Cu rrent Isc V;= -35V, Tj = 25°C 140 mA
Peak Current Ipeak Tj =25°C 650 mA

ELECTRICAL CHARACTERISTICS MC79M06C

(Refer to test circuit, O°C<TJ< 125°C, 10 = 350mA, V, = -11V, unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

Tj =25°C -5.75 -6.0 -6.25

Output Voltage Vo 5.0mAslos350mA V
V,= -8.0V to -25V -5.7 -6.0 -6.3
V;= -8V to -25V 7.0 60
Line Regulation f',V o Tj =25"C mV
V,= -9V to -19V 2.0 40
Load Regulation f',Vo Tj =25°C 10 = 5.0mA to 500mA 30 120 mV
Quiescent Current Id TJ=25°C' 3 6 mA
10 = 5.0mA to 350mA 0.4
Quiescent Current Change f',ld mA
V;= -8.0V to -25V 0.4
Output Voltage Drift 6 Vo/f',T 'o=5mA' 0.4 mV/oC
Output Noise Voltage VN f = 10Hz to 100KHz Tj = 25°C 50 ,.V
Ripple Rejection RR f = 120Hz, Vi = - 9 to -19V 54 60 dB
Dropout Voltage Vo 10 = 500mA, Tj = 25°C 1.1 V
Short Circuit Current Isc V;= -35V, Tj =25°C 140 mA
Peak Current Ipeak Tj =25°C 650 mA

• Load and line regulation are specified at constant junction temperature changes in Vo due to heating
effects must be taken into account separately pulse testing with low duty is used.

cIS SAMSUNG SEMICONDUCTOR 389

'MC79XX SERIES LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC79M08C

(Refer to test circuit, O°C<Tj< 125°C, 10 = 350mA, Vi = -14V, unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ- Max Unit

Tj =25°C -7.7 -8.0 -8.3

Output Voltage Vo 5.0mA:s 10:S 350mA . V
Vi = -10.5V to - 25V -7.6 -8.0 -8.4
'Vi = -10.5V to - 25V 7.0 80
Line Regulation 6Vo Tj =25°C mV
Vi = - 11V to - 21V 2.0 50
Load Regulation 6Vo Tj =25°C 10 = 5.0mA to 500mA 30 160 mV
Quiescent Current Id Tj =25°C 3 6 rnA
10 = 5.0mA to 350mA 0.4
Quiescent Current Change 61d rnA
Vi = -10.5V to - 25V 0.4
Output Voltage Drift 6V o/6T 10=5mA -0.6 mV/oC
Output Noise Voltage VN f = 10Hz to 100KHz"'rj = 25°C 60 /LV
Ripple Rejection RR f=120Hz, Vi= -11.5V to -21.5V 54 59 dB
Dropout Voltage VD 10 = 500mA, Tj = 25°C 1.1 V
Short Circuit Current Ise Vi= -35V, Tj =25°C 140 rnA
Peak Cu rrent Ipeak Tj =25°C 650 rnA

ELECTRICAL CHARACTERISTICS MC79M12C

(Refer to test circuit, O°C<TJ< 125°C, 10 = 350mA, Vi = -19V, unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max. Unit

Tj =25°C -11.5 -12 -12.5

Output Voltage Vo 5.0mA:Slo:s350mA V
Vi= -14.5V to -30V -11.4 -1.2 -12.6
Vi = -14.5V to - 30V 8.0 80
Line Regulation 6Vo TJ=25°C mV
Vi= -15V to -25V 3.0 50
Load Regulation 6Vo Tj =25°C 10 = 5.0mA to 500mA 30 240 mV
Quiescent Current Id Tj =25°C 3 6 rnA
10 = 5.0mA to 350mA 0.4
Quiescent Current Change 61d rnA
Vi = - 14.5V to - 30V 0.4
Output Voltage Drift 6Vof6T 10=5mA -0.8 mV/oC
Output Noise Voltage ·V N f = 10Hz to 100KHz Tj = 25°C 75 /LV
Ripple Rejection RR f=·120Hz, Vi= -15V to -25V 54 60 dB
Dropout Voltage VD 10=500mA, TJ=25°C 1.1 V
Short Circuit Current Ise Vi= -35V, TJ=25°C 140 rnA
Peak Current Ipeak Tj =25°C 650 rnA
• I,.oad and line regulation are specified at constant junction temperature changes in Vo due to heating
effects must be taken into account separately pulse testing with low duty is used.

c8 SAMSUNG S,EMICONDUCTOR 390

MC79XX SERIES LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC79M15C

(Refer to test circuit, O°C<TJ< 125°C, 10 = 350mA, V, = - 23V, unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

TJ=25°C -14.4 -15 -15.6

Output Voltage Vo 5.0mAslos350mA V
Vi = -17.5V to - 30V -14.25 -15 -15.75
Vi = -17.5V to - 30V 9.0 80
Line Regulation 6Vo TJ=25°C mV
V,= -18V to -28V 5.0 50
Load Regulation 6Vo TJ=25°C 10 = 5.0mA to 500mA 30 240 mV
Quiescent ,Current Id TJ=25°C 3 6 mA
10 = 5.0mA to 350mA 0.4

I
Quiescent Current Change 6 1d mA
V, = -17.5V to - 28V 0.4
Output Voltage Drift 6Vo/6T 10=5mA -1.0 mV/oC
Output Noise Voltage VN f = 10Hz to 100KHz TJ= 25°C 90 p.V
Ripple Rejection R'R f = 120Hz, V, = - 18.5V to - 28.5V 54 59 dB
Dropout Voltage Vo 10 = 500mA, Tj %25°C 1.1 V
Short Circuit Current Isc Vi= -35V, TJ=25°C 140 mA
Peak Current Ipeak TJ=25°C 650 mA

ELECTRICAL CHARACTERISTICS MC79M18C

(Refer to test circuit, O°C<TJ< 125°C, 10 = 350mA, Vi = - 27V, unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

Tj =25°C -17.3 -18 -18.7

Output Voltage Vo 5.0mAS los350mA V
Vi= -21V to -33V -17.1 -18 -18.9
Vi= -21V to -33V 9.0 80
Line Regulation 6Vo TJ=25°C mV
Vi= -24V to -30V 5.0 60
Load Regulation 6Vo TJ=25°C 10 = 5.0mA to 500mA 30 360 mV
Quiescent .current Id Tj =25°C 3 6 mA
10 = 5.0mA to 350mA 0.4
Quiescent Current Change 61d mA
V,= -21V to -33V 0.4
Output Voltage Drift 6 Vo/6T 10=5mA -1.0 mV/oC
Output Noise Voltage VN f = 10Hz to 100KHz Tj = 25°C 110 p.V
Ripple ,Rejection, RR f = 120Hz, Vi = - 22V to - 32V 54 59 dB
Dropout Voltage Vo 10 = 5OOmA, TJ= 25°C 1.1 V
Short Circuit Current Isc V, = -35V, Tj =25°C 140 mA
Peak Current lpeak TJ=25°C 650 mA

• Load and line regulation are specified at constant junction temperature changes in Vo due to heating
effects must be taken into account separately pulse testing with low duty is used. '

c8 SAMSUNG, SEMiCONDUCTOR 391

MC79XX SERIES LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC79M24C

(Refer to test circuit, 0°C<Tj <125°C, 10 ", 350mA, V,,,, -33V, unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

TJ ",25°C -23 -24 -25

Output Voltage Vo 5.0mA :510:5 350mA V
V,,,, -27V to -38V -22.8 -24 -25.2
V,,,, -27V to -38V 9.0 80
Line Regulation f::,V o Tj ",25°C mV
V,,,, -30V to -36V 5.0 70
Load Regulation f::,Vo TJ ",25°C 10 ", 5.0mA to 500mA 30 300 mV'
Quiescent Current Id TJ ",25°C 3 6 mA
10 ", 5.0mA to 350mA 0.4
Quiescent Current Change f::, Id mA
V,,,, -27V to -38V 0.4
Output Voltage Drift f::, VoIf::, T 10",5mA -1.0 mV/oC
Output Noise Voltage VN f", 10Hz to 100KHz Tj ", 25°C 180 p.V
Ripple Rejection RR f",120Hz, V,,,, -28V to -38V 54 58 dB
Dropout Voltage VD .l o ",500mA, T, '" 25.oC 1,1 V
Short Circuit Current Isc V,,,, -35V, TJ ",25°C 140 mA'
Peak Current Ipeak. TJ ",25°C 650 mA

c8 SAMSUNG SEMICONDUCTOR 392

KA336·5.0 LINEAR INTEGRATED CIRCUIT

VOLTAGE REFERENCE DIODE

TO-92
The KA336-5.0 integrated circuit is precision 5.0V shunt regulator
diodes. The monolithic IC voltage reference operates as a low
temperature coefficient 5.0V zener with 0.6 ohm dynamic impedance.
A third terminal on the KA336-5.0 allows the reference voltage and
temperature coefficient to be trimmed easily.
KA336-5.0 is useful as a precision 5.0V low voltage references for digital
voltmeters, power supplies or OP amp circuitry. The 5.0V make it
convenient to obtain a stable reference from low voltage supplies.
Further, since the KA336-5.0 operates as a shunt regulators, it can be
used as either a positive or negative voltage reference.

FEATURES
• Low temperature coefficient
•
•
•
•
•
Adjustable 4V to 6V
Wide operating range current 01 400~ to 10mA
Three lead transistor package (T0-92)
0.6 ohm dynamic impedance
± 1.0% initial tolerance available
1: Adj 2: Cathode 3: Anode

ORDERING INFORMATION
II
• Guaranteed temperature stability
• Easily trimmed lor minimum temperature drift Operating Temperature
• Fast tum on 0-70·C

SCHEMATIC DIAGRAM
,-------------------~----~--------------~r---~----~2 CATHODE

L - _ 4_ _- -_ _~--------_4_ _- - _ 4_ _ _ _ _ __ + - - - - - -_ _~--+_----~3 ANODE

Rx1, Rx2: External

Resistors

ciS SAMSUNG SEMICONDUCTOR 393·

 ~336·5.0 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic ~ymbol Value Unit

Reverse Current IR 15 mA
Forward Current IF 10 mA
Storage Temperature Range T"g -60 - 150 ·C
Op,ratlng Temperature Range Topr 0-70 ·C

ELECTRICAL CHARACTERISTICS
(Ta = 25·C, unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

Reverse Breakdown Voltage VR IR=1mA 4.8 5.0 5.2 V·

Reverse Breakdown
t:,VR 6OO,.A:sIRs10mA 6 20 mV
Change with Current
Reverse Dynamic Impedance Zo IR= 1mA 0.6 2 0
VR=5V,IR=1mA
Temperature Stability t:,VRT, · 4 12 mV
0·C:sTa:s70·C
\
Reverse Breakdown 6OO,.A:sIR:s10mA
t:,VRT2 6 24 mV
Change with Current 0·C:sTa:s70·C
Adjustment Range VA ±1 V
Reverse Dynamic Impedance ZOT IR=1mA,0·C:sTa:s70·C 0.8 2.5 0
Long Term Stability S IR= 1mA 20 ppm

TYPICAL .PERFORMANCE CHARACTERISTICS

400

/ 350 1\ IR =1mA
Tj =2S"C

T,= 12S"C
W ~300
\
'/
, ~ IV
4:, 25°C_ s:s.
I 250

200
\
~
o
o
./ 10
150
100 1K 10K
10 100K
REVERSE CURRENT (mA) FREQUENCY (Hz)
FIg. 1 FIg. 2

c8 SAMSUNG SEMICONDUCTOR 394.

KA336·5.0 LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

[
,.. OUT~UT TI=25°C

IV
r-' r-nt--

INPUT

-I *"'1
1
r-- c--.
t--. c- ----c OUTPUT

I-l~
r----- - 10
INPiT
! - f---
--- .. -.- .-.----.- ..- - - - t - - - - - - j I-- - ---

0." -'::-O----::,OO::---,:'::K,-----~,O:-::K---=,00K
i 1 4
FREQUENCY (Hz) TIME (ps)
Fig. 3 Fig. 4

5.120
~

5.080 b-::::::: t""""

,
a5.04O
w
" 5.000
:!
, g

. VT(=25~
I--- - ~ 4.950
- I-

- ---
ac: 4.920
10'
0
C

,1/ 1
4.880

10' 4.840
0.5 1.5 2.5 3.5 4.5 5.5 -15 25 -45 65 85 105 125
REVERSE VOLTAGE (V) TEMPERATURE (DC)
Fig. 5 Fig. 8

1.2

!
1.0

,/
/
../
Tj = 25°C

-.;.. ~
0.2

0
0.001 0.01 0.1 10
FORWARD CURRENT (mA)
FIg. 7

c8 SAMSUNG SEMICONDUCTOR . 395

KA336·S.0 LINEAR INTEGRATED CIRCUIT

TYPICAL APPLICATIONS
5.0V REFERENCE 5.0V REFERENCE WITH MINIMUM
TEMPERATURE COEFFICIENT
10V

5.0V
1N457·
KA336·5.0
KA336·5.0 A--~

1N457·

FIGURE 8
t Adjust to 2.490V
~ Any silicon signal diode

TRIMMED 4V TO 6V REFERENCE WITH TEMPERATURE FIGURE 9

COEFFICIENT OF BREAKDOWN VOLTAGE INDEPENDENT

10V PRECISION POWER REGULATOR WITH

LOW TEMPERATURE COEFFICIENT

KA336·5.0 A:--S~~~BRATE

* Does not affect temperature coefficient

FIGURE 10

5V CROWBAR

KA336·5.0

FIGURE 11

100 SENSITIVE
GATE SCR

200

FIGURE 12

c8 SAMSUNG SEMICONDUCTOR 396

KA38S·1.2 LINEAR INTEGRATED CIRCUIT

MICROPOWER VOLTAGE REFERENCE DIODE

TO-92
The KA385 is micropower 2-terminal band-gap voltage regulator
diodes. Operating over a 10~ to 20tnA current range, it. features
exceptionally low dynamic impedance and good temperature stability.
On-chip trimming is used to provide tight voltage tolerance. Since the
KA385-1.2 band-gap reference uses only transistors and resistors, low
noise and good long tenn stability result. Careful design of the KA385-1.2
has made the device exceptionally tolerant of capacitive loading, making
it easy to use in almost any reference application. The wide dynamic
operating range allows its use with widely varying supplies with excellent
regulation.

FEATURES
• Operating current of 10,..A to 20mA
•
•
•
•
1% and 2% initial tolerance
10 dynamic impedance
Low temperature coefficient
Low voltage reference -1_235V
1: N.C. 2: Cathode 3: Anode

ORDERING INFORMATION
I
Operating Temperature
0-70·C
SCHEMATIC DIAGRAM

c8 SAMSUNG SEMICONDUCTOR 397

KA38S·1.2 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Reverse Current IR 30 mA
Forward Current IF 10 mA
Operating Temperature Range Topr 0-70 > ·C
Storage Temperature Tstg -55 - +150 ·C

ELECTRICAL CHARACTERISTICS
(Ta = 25·C, unless otherwise noted)

Characteristic Symbol Test Conditions Min Typ Max Unit

Reverse Breakdown Voltage VR Im'nSIRs20mA 1.205 1.235 1.260 V

Minimum Operating Current Imin O·C sTas 70·C 8 15 ".A
0·CsTas70·C,lm;ns IRs1mA 1.5 mV
Reverse Breakdown Voltage 0·CsTas70·C, 1mAsIRs20mA 25 mV
l::,vR
Change with Current Im;nSIRS 1mA 1
mV
>

.1mAslRs20mA 20
0·CsTas70·C, IR = 100".A 0.4 1.5 0
Reverse Dynamic Impedance ZD
IR = 100".A 0.4 1 0
Average Temperature
0·CsTas70·C, 10p.AsiRs20mA 20 ppm/·C
Coefficient
IR=100".A,10HzSfS10KHz
Wide Band Noise (RMS) EN 0·CsTas70·C
60 ".V

long Term Stability S IR = 100".A 20 ppm/KHR

c8 SAMSUNG SEMICONDUCTOR 398

 KA38S·1.2 LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS

TEMPERATURE DRIFT REVERSE DYNAMIC IMPEDANCE
10K
T,,=25-C

1K
IA=100~

/
~
-
/
l/
o. 1
25 45 B5 B5 . 10 100 1K 10K 100K 1M
TEMPERATURE ('c) FREQUENCY(IIzj
Fig. 1 Fig. 2

NOISE VOLTAGE FILTERED OUTPUT. NOISE

~
1.~1(!o~~
eoo 60
111111 111111
SINGLE POLE LOW PASS

r--...
/'
r--""
ioo"

200
V
1\ KHARP CUTOFF FILTER

~ioo" 11111111
0
10 100 1K 10K 100K 100 1K 10K 100K
FREQUENCY (Hz) CUTOFF FREQUENCY (Hz)
Fig. 3 Fig. 4

ReSPONSE TIME

/
OUTPUT

10
~ INPUT

200 400 eoo

TIME",")
Fla.5

ciS SAMSUNG SEMICONDUCTOR 399

KA38S·1.2 LINEAR INTEGRATED CIRCUIT

STANDARD APPLICATIONS
MICROPOWER REFERENCE FROM 9V REFERENCE FROM.1.SV BATTERY
BATTERY
1.5V
9V

500K
1.2V
1.2V
KA385-1.2
KA385-1.2

c8 SAMSUNG SEMICONDUCTOR 400

KA431 LINEAR INTEGRATED CIRCUIT

PROGRAMMABLE PRECISION REFERENCES

. The KA431 is a three-terminal adjustable regulator series with
guaranteed thermal stability over applicable temperature ranges. The
output voltage may be set to any value between Vre, (approximately 2.5
volts) and 36 volts with two exterrial resistors. These devices have a
typical dynamic output impedance of 0.20. Active output circuitry 1: Ref. 2: Anode 3: Cathode
8 DIP
provid~ a very sharp turn-on characteristic, making these devices
excellent replancement for zener diodes in many applications .

. FEATURES
• Programmable output voltage to 36 volts
• Low dynamic output impedance 0.20 typical 1: Cathode 6: Anode 8: Ref.
2, 3, 4, 7: N.C.
• Sink current capability of 1.0 to 100mA 8 SOP

I
• Equivalent full-range temperature coefficient of 50ppm/o C typical
• Temperature compensated for operation over full rated operating
temperature range
• Low output noise voltage
1: Cathode 2, 3, 6, 7: Anode 8: Ref.
4,5: N.C.

BLOCK DIAGRAM ORDERING INFORMATION

i --- -------,
REFERENCE CATHODE
I Device Operating Temperature Package
I
I
KA431CZ 0-+ 70·C TO-92
KA431CN 0-+ 70·C 8 DIP

f
KA431 CD 0-+70·C 8 SOP
ATHODE(K) KA4311Z -40-+85·C TO-92
KA431 IN -40-+85·C 8 DIP
REFERENCE (R) 0 -

. ANODE (A)

SCHEMATIC DIAGRAM
CATHODE

02

ANODE

cIS SAMSUNG SEMICONDUCTOR 401

KA431 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

(Operating temperature range applies unless otherwise specified.)

Characteristic Symbol Value Unit

Cathode Voltage VKA 37 V

Cathode Current Range (Continuous) IK -100-+150 rnA
Reference Input Current Range 're, 0.05 - + 10 mA
Power Dissipation Po
D, Z Suffix Package 770 ,mW
N Suffix Package 1000 mW
Operating Temperature Topr
KA431CZ, KA431CN, KA431CD 0-+70 ·C
, KA4311Z, KA4311N -40-+85 ·C
Operating Junction Temperature Tj 150 ·C
Storage Temperature Range T.tg -65-+150 ·C

RECOMMENDED OPERATING CONDITIONS

Characteristic Symbol Min Typ Max Unit

Cathode Voltage VKA Vre, 36 V

Cathode Current IK 1.0 100 mA

ELECTRICAL CHARACTERISTICS (Ta=25·C, unless'otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit ·T/C

Ta=25·C 2.440 2.495 2.550

VKA = Vref
Reference Input Voltage Vref Ta=O·C V 1
IK=10mA 2.423 2.567
to 70·C
Deviation of Reference Input VKA=V re" ' K=10mA
Vref(dev) 8 17 mV 1
Voltage Over Temperature 1 Ta=O·C to 70·C
VKA=Vre,
Ratio of Change in Reference -1.4 -2.7
Vref to 10V
Input Voltage to the Change - 1i<=10mA mVN 2
in Cathode Voltage VKA VKA = 10V
-1.0 -2.0
to 36V

IK= 10mA Ta=25·C 1.8 4.0

Reference Input Current Iref R1 = 10KO Ta=O·C p.A 2
R2=oo 5.2
to 70·C
Reference Input Current IK = 10mA, .R1 = 10KO
Deviation Over Temperature lref R2=oo 0.4 1.2 p.A 2
Range Ta = O·C to 70·C
Minimum Cathode Current
IKmin VKA=V re, 0.5 1.0 mA 1
for Regulation
Off-State Cathode 'Current IKoff VKA =36V, Vref=OV 2.6 1000 nA 3
VKA=Vref
Dynamic Impedance 2, ZKA IK= 1.0 to 100mA 0.22 0.5 0 1
fS1.0KHz

• Test Circuit

c8 SAMSUNG SEMICONDUCTOR 402

KA431 LINEAR INTEGRATED CIRCUIT

Note: 1. The deviation parameters VrelldOv) and Ire~dOY) are defined as the differences between the maximum and
minimum values obtained over the rated temperature range. The equivalent full-range temperature coefficient
of the reference input voltage, aVrel, is defined as:

Max VTOI Min V,"I 6 TA Vre~dev)

'~-I
aVrel
~
( °e) =
( Vref!d~1
Vrel @25°e
6TA
) x 10"
L=±
I I
where 6 TA is the rated operating free-air temperature range of the device.
aVrel can be positive or negative depending on whether minimum Vrel or maximum Vre" respectively, occurs
at the lower temperature
Example: Max V..,=2500mV@30oe, Min V..,=2492mV@Ooe, V..,=2495mV@25°e, 6 TA=70oe forKA431e
8mV
(2495rTiV) x 10" °
aV re, 700C = 46ppml e

Because minimum Vre, occurs at the lower temperature, the coefficient is positive.
2. The dynamiC impedance is defined as:
II
ZKA

When the device is operated with two external resistors (see Figure 2), the total dynamic impedance of
the circuit is given by:

Z' _ 6V _
. - 61 -

TEST CIRCUIT
Fig. 1 Test Circuit for VKA=Vre, Fig. 2 Test Circuit for VKA~Vre'
INPUT o---'\j"""'~p----o VKA INPUT o-~Wo~-.-----O VKA

Rl

KA431

Vref
R2

VKA =Vre t<l + RlIR2) + lrel. Rl

Fig. 3 Test Circuit for 10"

INPUT o----'WO--..-,---o VKA

KA431

c8 SAMSUNG SEMICONDUCTOR 403

KA431 LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS

CATHODE CURRENT VS CATHODE VOLTAGE CATHODE CURRENT VS CATHODE VOLTAGE
150 800
VKA = VrrA
T -25'C VKA=Vfflf
125
T" =25°0
100 600

c
'-

0
V-
/
-50 I ,/
I
-75
-100
-2
I -1 0
V..-Col_ V"'--V
1
-200
-1
r 1
V..-~VoI""-V
2

FIGURE 4 FIGURE 6

CHANGE IN REFERENCE INPUT VOLTAGE

NOISE VOLTAGE VS FREQUENCY
VS CATHODE VOLTAGE

:; -5
\ IK =10rnA
TA =25°C

I
1-10
I\,
::
1- "- ~ ~
§
\!-2O
15

130~++~*-~~~-+1+~~++~
S
.&-25 "- ~ >
i
2O~t+~m-~~~-+~#m~t+~

1-30

'"
.~
~.-35

-40
o 10 15 20 25 30 35 40
V..-Cothodo VoItago-V f-frequency-Hz
FIGURE. FIGURE 7

SMALL SIGNAL VOLTAGE AMPLIFICATION

DYNAMIC IMPEDANCE VS FREQUENCY
VS FREQUENCY
100 70
70 T,,=25°0 T,,=25°0
IK=1mA to 100mA 11(=10mA
60

20 .......
10 II' IJ""~
7

1\1'1
0.7

0.4

0.2

0.1
lK 10k lOOK
f-Fraquency-Hz
1M 10M
-10
lK 10K lOOK
f-Fraquenc:y-Hz
,"
1M 10M

FIGURE 8 FIGURE.

ciS SAMSUNG SEMICONDUCTOR 404

KA431 LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

PULSE RESPONSE

T.=i2S0C
LT

UTPUT

1 2
V

II
1

t-Time-us
FIGURE 10

TYPICAL APPLICATIONS
FIGURE ll-SHUNT REGULATOR FIGURE l2-SINGLE-SUPPLY COMPARATOR WITH
TEMPERATURE-COMPENSATED THRESHOLD
v+ Q-Jw.-~--~---,.-OVOUT
V+

~--oOUTPUT

INPUT o--w..H~ Von=2V

Voff=V+
V(lh}= 2.5V
KA431
o---~-+------o GND

FIGURE.13-SERIES REGULATOR FIGURE l4-0UTPUT CONTROL FIGURE l5-HIGHER-CURRENT

V+O-~---------~
OF A THREE-TERMINAL SHUNT REGULATOR
FIXED REGULATOR
V+D-------.,

...-~_oVoul

KA431

c8 SAMSUNG SEMICONDUCTOR 405

KA431 LINEAR INTEGRATED CIRCUIT

TYPICAL APPLICATIONS (Continued)

FIGURE 16-CROW BAR FIGURE 17-0VER·VOLTAGE/UNDER·VOLTAGE

PROTECTION CIRCUIT
V+
KA431
v +o-~--~:-1'-----, OUTPUT ON
WHEN
LOW, HIGH
LlMIT<V + < LIMIT

R2A

R1
Vlimlt=(1 +R2>V re f
Low limit = Vref (1 + ~~~) + V,BE
High limit = V,.d1 + ~~~)

FIGURE 18-VOLTAGE MONITOR FIGURE 19-DELAY TIMER

R2A KA431 KA431

..
Lo w l,m,t=Vref (1 R1B)
+R2B
V+
Delay=R·C·ln (V+)-V,ef
High limit = V,.d1 + ~~~)

FIGURE 20-CURRENT LIMITER OR FIGURE 21-CONSl'ANT·CURRENT SINK

CURRENT SOURCE
Vi-

lout
V+

KA431

Vref Vref
lout= RCL, lout=rs

c8 SAMSUNG SEMICONDUCTOR 406.

KA201A1KA301A LINEAR INTEGRATED CIRCUIT

SINGLE OPERATIONAL AMPLIFIER 8 DIP

The KA201A and KA301A are general-purpose operational amplifiers

which are externally phase compensated, permit a choice of operation
for optimum high-frequency performance at a selected gai,n: unity-gain
compensation can be obtained with a single 30pF capacitor,

FEATURES
• Unlty-gain phase compensation with a single 30pF 8 SOP

• Short-circuit protection and latch-free operation

• Slew rate of 10Vlp.s as a summing amplifier
• Class AB output provides excellent linearity

BLOCK DIAGRAM ORDERING INFORMATION

I
NULUCOMPENSATION I 8 COMPENSATION Device Package Operating Temperature
KA201AN -25·C - +S5·C
S DIP
KA301AN O·C - 70·C
KA201AD -25·C - +S5·C
ssop
KA301AD O·C - + 70·C
5 OFFSET NULL

COMP,
NULL COMP,
SCHEMATIC DIAGRAM
----~--~VCC
INVERTING
INPUT - O - - - , - - - i - - - - - t - - - {
NON·INVERTING
INPUT + O-~--+-----I

Rll
25!l
'---j----<> OUTPUT

L--+-~~-L-~-+--------~------+--+-~---oVEE

OFFSET NULL

c8 SAMSUNG ,SEMICONDUCTOR 407

KA201A1KA301A LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol KA201A KA301A Unit

Supply Voltage Vs ±22 ±18 V

Differential Input Voltage Vto ±30 ±30 V
Input Voltage V, ±15 ±15 V
Output Short Circuit Duration Continuous Continuous
Power Dissipation Po 500 500 mW
Operating Temperature Range Top, -25-+85 0-+70 ·C
Storage Temperature Range T stg -65 - +150 -65 - +150 ·C

ELECTRICAL CHARACTERISTICS
(- 25·CsTas + 85·C for the KA201A, O·CsTas + 70·C for the KA301A, unless otherwise specified)

KA201A KA301A
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max

Rss50KO 0.7 2.0 2.0 7.5 mV

Input Offset Voltage V,O
T aminSTaSTama>< 3 10 mV
1.5 10 3 50 nA
Input Offset Current 1,0
TaminSTaSTamax 20 70 nA
30 75 70 250 nA
Input Bias Current 1'8
TamlnSTaS Tama>< 100 300 nA
Vs= ±20V 1.8 3.0 mA
Supply Current Is Vs=±15V 1.8 3.0 mA
Vs= ±20V, Ta=Tam.. 1.2 2.5 mA
Vee = ± 15V, RL~2KO, Vo = ± 10V 50 160 25 160 V/mV
Large Signal Voltage Gain Av
Tamin,STa::sTamax 25 15 V/mV
Average Temperature
Coefficient of Input 1':,v,olf:,T TaminSTaSTama>< 3.0 15 6.0 30 ,.V/·C
Offset Voltage
Average Temperature 25·CS TaS Tamax 0.01 0.1 0.01 0.3 nArC
Coefficient of Input f:,1,oIf:, T
Offset Current T aminSTaS25·C 0.02 0.2 0.02 0.6 nAl·C

Vs= ±20V TaminSTaSTamax ±15 V

Input Voltage Range VieR
Vs=±15V TamlnSTaSTama>< ±12 V
Common-Mode Rejection
CMRR RsS50KO TaminSTaSTamax 80 96 70 90 dB
Ratio
Power Supp,ly Rejection
PSRR Rss50KO TamlnSTaS Tamax 80 96 70 96 dB
Ratio
RL=10KO ±12 ±14 ±12 ±14 V
Output Voltage Swing Your Vs=±15V
RL=2.0KO ±10 ±13 ±10 ±13 V
Input Resistance R, 1.5 4.0 0.5 2.0 MO
Slew Rate SR 0.5 0.5 V/,.s

c8 SAMSUNG SEMICONDUCTOR'" ' 408

KA201A1KA301 A LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS

SUPPLY CURRENT VOLTAGE GAIN
2.5 120

2.0

,.... - '110

.-. ~ Ta=25-C

I-- ~
5

--
Ta=2S"C

90
o.5

10
SUPPLY VOLTAGE (%V)
FIg. 1
15 20 10
SUPPLY VOLTAGE (%V)
Fig. 2
15 20

II
--
CURRENT, LIMITING COMMON MODE REJECTION
15

- - VS~ ±15V
120
I
-....
'\
Ta=25"C
100

80
-~ R,= 11<0
Ta=25°C

60
~ l! VCM'5. ± lOV

10 15

OUTPUT CURRENT
Fig. 3
20

«::t mAl
25 30
40

20
10 100 1K
FREQUENCY (Hz)
Fig. 4
"
10K 100K
>-.
VCM::S;::tW

I
1M

POWER SUPPLY REJECTION

100
, l'. C1=30pF
Ta=25"C_
"'\
"' ~
"\
I"'\.'\:~
,"'~
~'\ ~J-
~~<. ~
~J- ~
~
"" ~
0

10 100 1K 10K
FREQUENCY (Hz)
100K
"' I000o

1M 10M

Fig. 5

c8 SAMSUNG SEMICONDUCTOR 409

KA201 AlKA301 A LINEAR INTEGRATED CIRCUIT

SINGLE POLE COMPENSATION . OPEN LOOP FREQUENCY RESPONSE,

120
T8=~·C
100

~
v'Tsv- 225

INPUT
II,
> - - - 4 - - 0 v""
iii:
II
z eo
".
C

!II
eo

.0
~ "
~C1~ ~=3PF
~r'\. ~
PHjE

~
r'\.
""-
~
20

SINGLE POLE ~AIN

FIg. •

GAlj\
-20
10 100 1K 10K 100K 1M 10M
FREQUENCY (HII
FIg. 7
LARGE SIGNAL FREoUENCY RESPONSE VOLTAGE FOLLOWER PULSE RESPONSE
16 10
T~=~·b
Vs= ±15V
r=~Tc
V.=::t15V

12
C1=3pF
- -- -
~
~
1\ INPUT '
7
I." \ IJOUTPUT
1\ I
C1=3OpF e -2

1\ 1\ SINGLE POLE
0
>
-. - -- --
-6
\
~ SI~~LE iLE
-8

o ~~ ..... -10
10 20 30 .0 50 eo 70 eo
1K 10K 100K 1M 10M
FREQUENCY (HII TIMEfpa)
Flg.8
FIg. '.

TWO POLE COMPENSATION OPEN LOOP FREQUENCY RESPONSE

120

~POLE
R,
-V~o-_-L--l
100
" 225

INPUT II, >--+-OV"" \

'\ ",ASEI'- J
+V~o-<_---I eo
iii:
S
z eo
;
"' 1\
~ .0

GA~
~
c,iit/,ft 20

"
Cs=3OpF Ta=25-C
Cs=1QC, Vs = ±15V
C1=30pF

""" 10
-20
1
C2=jF

10 100 lK 10K 100K

f'\
1M 10M
FREQUENCY (HII
FIg. 11

c8 SAMSUNG SEMICONDUCTOR 410

KA201A1KA301A LINEAR INTEGRATED CIRCUIT

LARGE SIGNAL FREQUENCY RESPONSE VOLTAGE FOLLOWER PULSE RESPONSE

18 10
J,J±I,~
Ta=25-C
JoJLE_ I-----
Cl=3O!>F J .1 .
12 1\ C2=3OOpF
~ -~.
INPUT

1\ 1 IE
\
OUTPUT

\ TWO'~L~
i"
w
\
"~ -2 \
!i!
1\ -4
-- Ta=25-C
~ -6 Vs = ±15V
Cl=3O!>F

~
-6

-10
rjpF
lK lOOK 1M 10203040 80807080
FREQUENCY (HI! TIllE"",)
FIg. 12 FIg. 11

FEEDFORWARD COMPENSATION OPEN LOOP FREQUENCY RESPONSE

-
120

C,
r-.... Va= ~15V
T.=25·C _
100 225

80 "" 180

INPUT
R,

V"",
Iii
:g,
~
'"
80 " "\
~ PHASE/-- 135
w ~ 'V
R,
~
0
40
'\
90

>
20 45
~IN
C,
FEED FORWARD
<4= 2'1'f:R2
fo=3MHz

FIg. 14
'"
-20
10 100 lK 10K lOOK 1M 10M 100M
FREQUENCY (HI!
FIg. 15

LARGE SIGNAL FREQUENCY RESPONSE INVERTER PULSE RESPOSE

18 10
~.~~!d

12
\ nrn
FEED FORWARD
~ - --- -- -- -- I
1\ JPUT -

~
INPUT

\
1\
-8
- -- -- - -- .

'""
FEE~F0'rARDI
T8=25-C
-6

o
r--.. -10
1'= ±1'5V

lOOK 1M 10M 1020304080807080

FREQUENCY (HI! TIllE .....
FIg. 11 FIg. 17

c8 SAMSUNG SEMICONDUCTOR 411

KA733C LINEAR INTEGRATED CIRCUIT

.DIFFERENTIAL VIDEO AMPLIFIER

14 QIP
The KA733C is a monolithic differential input, differential output,
wideband video amplifier.
The use of internal series-shunt feedback gives wide bandwidth with
low phase distortion and high gain stability. The KA733C offers fixed
gains 10,100,400 without external components, and adjustable gains from
10 to 400 by use of an external resistor.
The KA733C is intended for use as a high performance video and pluse
amplifier in communications, magnetic memories, displays and video
recorder systems. . 14 SOP

FEATURES
• 120MHz bandwidth
• 250KO input resistance
• Selectable gains of 10,100,400
• No frequency compensation required

BLOCK DIAGRAM
ORDERING INFORMATION
Device Package Operating Temperature
G28 GAIN G2A GAIN
12 SELECT
SELECT KA733CN 14 DIP
0-+70·C
G'8 GAINT
SELECT 11 ~~~~;~N KA733CD 14 SOP

SCHEMATIC DIAGRAM

INPUT2 o--~-t===E~~=tt1:=+::::::!J
INPUT1
L--+----"."..-~----+---o OUTPUT1

GAIN SELECT

7K
G2B L---r--"M~+-----1~--o OUTPUT2

. GAIN SELECT {
G1B

400

VEe

c8 SAMSUNG SEMICONDUCTOR 412

KA733C LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Differential Input Voltage V ,O ±5 V

Common mode input Voltage V, ±6 V
Power Supply Voltage Vs ±B V
Output Current 10 10 mA
Power Dissipation Po 500 mW
Operating Temperature Range Top, 0-+70 ·C
Storage Temperature Range T stg -65- + 150 ·C

ELECTRICAL CHARACTERISTICS
(Vcc= +6V, VEE = -6V, Ta=25·C, unless otherwise specified)

Characteristic

Differential Voltage Gain

Gain 1 (Note 1)
Gain 2 ( " 2)
Test
Figure

1
Symbol

Av
Test Conditions

RL = 2KIl, YOU! = 3V p.p

Min

250
80
Typ

400
100
Max

600
120
Unit

VIV
I
Gain 3 ( " 3) 8 10 12
Bandwidth
Gain 1 ( " 1) 40
Gain 2 ( " 2) 2 BW Rs = 501l 90 MHz
Gain 3 ( " 3) 120
Rise Time
Gain 1 (
Gain 2 (
·· 1)
2) 2· t,
Rs = 501l
10.5
4.5 12 ns
Gain 3 (
·
Propagation Delay
3)
Your = 1Vp.p
2.5

Gain 1 (
Gain 2 (
··
1)
2) 2 tpd
Rs = 501l
7.5
6.0 10 ns
Gain 3 (
·
3)
. Input Resistance
Vour = 1Vp.p
3.6

Gain 1 (
Gain 2 (
·· 1)
2) 3 Ri VooS1V 10
4.0
30 KIl
Gain 3 (
· 3)
Input Offset Current 1'0
250
0.4 5 Jl.A
Input Bias Current liB 9 30 Jl.A
Input Voltage Range 1 V'CR ±1 V
Common Mode Rejection Ratio
Gain 2 VOM= ±1V, fS100KHz 60 86 dB
4 CMRR
Gain 2 VCM = ±1V, f=5MHz 60 dB
Power Supply Rejection Ratio
Gain 2 1 PSRR 6Vs= ±0.5V 50 70 dB
Output Offset Voltage
Gain 1 1 Voo RL=oo 0.6 1.5 V
Gain 2 and 3 0.35 l.5 V
Input CapaCitance Gain 2 2.0 pF

c8 SAMSUNG SEMICONDUCTOR 413

KA733C LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTIC (COntinued)

Test
Characteristic Symbol Test Conditions Min Typ Max Unit
Figure

Output Common Mode Voltage 1 VOCM RL=OO 2.4 2.9' 3.4 V

Output Voltage Swing 1 VOUT RL=2KO 3.0 4.0 V
Output Sink Current ISink 2.5 3.6 mA
Power Supply Current 1 Is RL=OO 18 24 mA
Output Resistance . Ro' 20 ()

ELECTRICAL CHARACTERISTICS
The following specifications apply over the range of 0·CsTas70·C Vee = +6V, Vee = -6V

Test
Characteristic Symbol Test Conditions Min :ryp Max Unit
Figure

Differential Voltage Gain

Gain 1 (Note 1) 250 600
RL=2KO
Gain 2 (Note 2) 1 Av 80 120 VN
Vout =3Vp-p
Gain 3 (Note 3) 80 12
Input Bias Current liB 40 p.A
Input Offset Current 110 6.0 p.A·
Input Voltage Range 1 ViCR ±1.0 V
Input Impedance (Gain 2) 3 Ri 8.0 ,KO
Common Mode Rejection Ratio
4 CMRR VCM = ±1V, fS100KHz 50 dB
Gain 2 (Note 2)
Power Supply Rejection Ratio ~,.vee= ±0.5V
1 PSRR 50 dB
Gain 2 (Note 2) /';Vee= ±0.5V
Output Offset Voltage
Gain 1 (Note 1) 1.5
1 Voo V
Gain 2 and Gain 3 (Note 2, 3) 1.5
Output Voltage Swing 1 VoP 2.8 V
Output Sink Current Islnk 2.5 mA
Power Supply Current Is 27 mA

Notes 1. Gain select pins G'A and G'B connected together.

2. Gain select pins G2A and G2B connected together.
3. All gain select pins open.

c8 SAMSUNG SEMICONDUCTOR 414

KA733C LINEAR INTEGRATED CIRCUIT

PARAMETER MEASUREMENT INFORMATION

TEST CIRCUITS

VOD 2KO

1KO

Fig. 1 Fig. 2

o V vool ~2~
500

500
II
[ VIC
1KO

Fig. 3 Fig. 4

VO D 2KO

2A
VOLTAGE AMPLIFICATION ADJUSMENT
Fig. 5 Fig. 6

c8 SAMSUNG SEMICO~DUCTOR 415

KA733C LINEAR INTEGRATED CIRCUIT

. TYPICAL PERFORMANCE CHARACTERISTICS

PHASE SHIFT va FREQUENCY PHASE SHIFT va FREQUENCY

-5
" .......
:

'~
,
-50
0

- ~t'-
N
1\
IfB 1'.. GAIN 2
~\
~:~:S~6-

,
-10
i:~~~~-
e. ~
~
ill1&1 -15 I" 1\\
i
-20
" '1'.
~\:l'jj
-300
~\ GAIN
,
GAIN 1
.,
2

-25 -350
o 10 10 50 100 1000
FREQUENCY (MHz) FREQUENCY (MHz)
Fig. 7 Fig. 8
VOLTAGE GAIN va FREQUENCY PULSE RESPONSE
60 1.6

1.4
50
GAIN 1

,
iii" 1.2
ll-
z 40 ..... "....
r/
1.0
~
lN3
GAIN 2
Vs= ±6V
~ Gi
w w
Ta=25°C 0.8
"~ 30 ::'"
"c!:; I
~.
GAIN2
~:::S~~-
..
~ ~ 0.6
/GAIN1
I- RL =1KO
w 20 ::> 0.4

I\~
i..- ~
Z
w
GAIN 3
::>
0
/
...
III
10
0.2
j
"illz
~ . -0.2

-0.4
6 10 50 100 500 1000 -15 -10 -5 0 10 15 20 25 30 35
FREQUENCY (MHz) TlME(na)
FIg. 9 Fig. 10

PULSE REsPONSE va SUPPLY VOLTAGE PULSE RESPONSE v. TEMPERATURE

1.6 1.6

1.4 I 1.4 ~AIN J -

1.2 1
Vs= ±BV
1.2
~I¥
I.
-1
Vs= ±6V
25 "Ct-i,=1j -

~ 1.0 ~ 1.0 Ta=O·C

w
0.6 V r·="'t w
~
"...
~ II Vs = ±3V
~ 0.8 Ta=7O".)Ta=85"C-
Ta=25°C
~ 0.6 ~ 0.6

~
0
0.4

0.2

-0.2
Ilf
JI
1 1
GAIN 2
Ta=25"C-
RL =1KO

I
~ 0.4

O.2

2
,
-0.4
-15 -10 -5 5 10 15 20
1
25 30 35
-0.4
-15 -10 -5 10 15 25 30 35
TIME(na) TIME·(na)
Fig. 11 FIg. 12

c8 SAMSUNG SEMICONDUCTOR 416

KA733C LINEAR INTEGRATED CIRCUIT

COMMON MODE REJECTION RATIO

va FREQUENCY OUTPUT VOLTAGE SWING va FREQUENCY
100 1.0

90 III
iii
lit
2
80
GAIN 2
III 6.0

"~ ~ 8~ Va= :t6V

70 ~:~:5~~- 5.0 Ta=2S·C-
z ......... 1'- RL =1KO
§z 80
r-.. r-..... I"
w
4.0
'\
"iii 50
~
II:

III
r-... 3.0
~
~

i
i 30
....."
!;
2.0
1\
:I
8
20
0

1.0
\
10

II
10K lOOK 1M 10M 100M 1 10 50 100 500 1000
FREQUENCY (Hili FREQUENCY IMHIII
fig. 13 FIg..14
DIFFERENTIAL OVERDRIVE RECOVERY TIME VOLTAGE GAIN va SUPPLY VOLTAGE
10 I.'
T~=251c
1.3
80
./
/ 1.2
iw 50 / V
..-r-
~

-
1.1
~
1;:
w ~
Va = ±6V
Ta=2SoC
-GAIN 2
V "
w 1.0
"~
"GAIN3
..- V
/

~ '/ ~
0.9
~ ,//
II: 30 w
0.8
i / ~

S
/ /
"
II: 20 w 0.1
II:
GAI~
~
10
./
V 0.6

0.5 /
o 0.4
o 20 40 60 80 100 120 140 160 180 200
DIFFERENTIAL INPUT VOLTAGE (my) SUPPLY VOLTAGE (±Y)
fig. I. fig. 18
OUTPUT VOLTAGE SWING
V8 LOAD RESISTANCE GAIN va FREQUENCY V8 SUPPLY VOLTAGE
7.0 80

6.0 50
iii
lit
8 ~:::5~~- GAIN2 -
~
5.0 ~
~
Ta=25°C

I.
w
4.0
I'
w
~
!:i
30
~

,~
~
~
~
3.0
"w 20

....."
!;

0
2.0
V
"w
Z

!
10
, Vytr
1\\ V•.=.±.8V-
\
1.0

0
i--"'" '" -10
Vr(i
10 50 100 200 500 lK SK 10K 1 10 100 500 1000
LOAD RESISTANCE (0) FREQUENCY (II"",
fig. 17 fig. 11

c8 SAMSUNG SEMICONDUCTOR 417

KA733C LINEAR INTEGRATED CIRCUIT

SUPPLY CURReNT va TEMPERATURE SUPPLY CURRENT va SUPPLY VOLTAGE

21 28

20 I
Losie-
2.

19
~V
~ /
!iw 18
a:
a:
i!
r--.. ........ ....... V,: .6V
/
..."
17 lL'
~

OJ
16
'r- V
V
12
15 V
,. 8
L~
-60 -20 20 60 100 140 3
TEMPERATURE (0C) SUPPLY VOLTAGE (±Yl
Fig. 1. Fig. 20

VOLTAGE GAIN va R.o.

1000

" ~:~:5~6-
I

".... ~
["'...
1"'-1'
10
10 100 ""'" 10K
R...J (Il) '"
Fig. 21

c8 SAMSU~G SEMICONDUCTO~ 418

KA9256 . LINEAR INTERGRATED CIRCUIT

DUAL POWER OPERATIONAL AMPLIFIER

10 SIP
The KA9256 is a dual power operational amplifier and it is output
maximum current is 1.0A CVs= ± 15V). It can·be used in arm driver for
player, driver for brush motors forward and reverse rotation control and CD
output drive·r for hole motor.

FEATURES
• lriteral current limiting: Isc = 350mA (Rsc = 2.20)
• High output current: I. = SOOmA max
• 10 SIP HIS package
• Internal phase compensated

BLOCK DIAGRAM

~---- II
ORDERING INFORMATION
Operating Temperature
'W
~0 'Z 'Z_ tll '";;z ;;'" '"0 '"
Z 0-
0

,
;; W 0
-20 - + 70·C
III
15
III >
;;
+
>
+ , >
::J III
15
III
>
> >

SCHEMATIC DIAGRAM
SENSE

r---------~--~~--~------_r----------~------lr~VCC

INVERTING
INPUT

NON·INVERTING 0---+------+---
INPUT t----+--t-i ,r--------t-------+--oOUTPUT

c8 SAMSUNG SEMICONDUCTOR 419

KA925() LINEAR INTERGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristics Symbol Value Unit

Supply Voltage Vs ±18 V

Output Current 10 1.0 A
Power Dissipation Po 12.5 W
Operating Temperature Range Top, -20-+70 ,oC
Storage Temperature Range T.tg -65 -+ 150 °C

ELECTRICAL CHARACTERISTICS'
(Vee = + 15V, Vee = -15V, Ta= 25°C, unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

Input Offset Voltage VtO 2 6 mV

Input Offset Current Ito 10 200 nA
Input. Bias Current ItB 100 700 nA
Supply Current Is 10 20 mA
Output Voltage Swing VOUT RL =330 ±12 ±13 V
Large Signal Voltage Gain Av 100 dB
Input Voltage Range VieR ±12 ±14 V
Common Mode Rejection Ratio CMRR 70 90 dB
Power Supply Rejection Ratio PSRR' 50 150 p.v1V
Bandwidth BW 1.0, MHz
Slew Rate SR ' Av=1, RL=330, R=100, C=0.1,..F 0.1!;i , V/,..s
Limiting Current los Rsc= 2.20 0.35 A
Cross Talk CT RL = 330, Vo = 1Vp-p 60 dB

c8 SAMSUNG SEMICONDUCTOR 420

KF351 LINEAR INTERGRATED CIRCUIT

8 DIP
SINGLE OPERATIONAL AMPLIFIER
The KF351 is JFET input operational amplifier with an internally
trimmed input offset voltage. The JFET input device provides wide
bandWidth, low input bias currents and offset currents.

FEATURES
• Internally trimmed offset voltage: 10mV 8 SOP
• Low input bias current: SOpA
• Wide gain bandwidth: 4MHz
• High slew rate: 13V/I's
• Low supply current: 1.8mA
• High input Impedance: 1012{}

BLOCK DIAGRAM. ORDERING INFORMATION

II
Device Package Operating Temperature
OFFSET
NULL KF351N a DIP 0-+ 70·e
KF351D a SOP

5 OFFSET
NULL

SCHEMATIC DIAGRAM
vcco---------~--------------~--~----~~-------------------

R5

INPUT(-) OUTPUT

R6

-VEEo---+----+--~--------~---+--~----~--~~~--------~--~

c8 SAMSUNG SEMICONDUCTOR 421

KF351 LINEAR INTERGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristics Symbol Value Unit

'Power Supply Voltage Vs ±18 'V

Differential Input Voltage vlO ±30 V
Input Voltage Range VI ±15 V
Output Short Circuit Duration Continuous
Power Dissipation Po 500 mV
Operating Temperature Range Top' 0-+70 ·C
Storage Temperature Range Tsig -65 -+ 150 ·C

'ELECTRICAL CHARACTERISTICS
(Vee = + 15V, VeE = -15V, Ta= 25·C, unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

5.0 10
Input Offset Voltage VIO Rs=10K mV
, I O·C:sTa:s + 70·C 13
Input Offset Voltage Drift t:"vlol£:;. T Rs=10K I O·C:sTa:s + 70·C 10 ,.V/·C
25 100 pA
Input Offset Current ho
I O·C:sTa:s + 70·C 4 nA
50 200 pA
Input Bias Current liS
J O·C:sTa:s + 70·C 8 nA
Input Resistance Ri 1012 II

Vo= ±10V 25 100

Large Signal Voltage Gain Av VlmV
RL=2Kll ,I O:sTa:s + 70·C 15
Output Voltage Swing VOUT RL=10Kll ±12 ± 13.5 V
Input Voltage Range VieR ± 11 +15 V
C?mmon Mode Rejection Ratio CMRR Rs:s10Kll '70 100 dB
Power Supply Rejection Ratio PSRR Rs:s10Kll 70 ' 100 dB
Power Supply Current Is 1.8 3.4 mA
Slew Rate SR Av =1 13 V/,.s
Gain-Bandwidth Product GBW 4 MHz

c8 SAMSUNG SEMICONDUCTOR 422

LM2241A, LM3241A, LM2902 LINEAR INTEGRATED CIRCUIT

QUAD OPERATIONAL AMPLIFIERS I~-----'-- --------- -

The LM224 series consists of four independent, high gain, internally I 14 DIP

frequency compensated operational amplifiers which were deSigned

specifically to operate from -a single power supply over a wide range
of voltage.
Operation from split power supplies is also possible and the low power
supply current drain is independent of the magnitude of the power supply
voltage.
Application areas include transducer amplifier, DC gain blocks and all
the conventional OP amp circuits which now can be easily implemented
in single power supply systems. 14 SOP

FEATURES
• Internally frequency compensated for unity gain
• Large DC voltage gain: 100dB

II
•
• Wide power supply range: LM224/A, LM324/A: 3V - 32V (or :t 1.SV -16V)
LM2902: 3V - 26V (or ± 1.SV - 13V)
• Input common-mode voltage range includes ground
• Large output voltage swing: OV DC to Vcc-1.SV DC
• Power drain suitable for battery operation.
__J
BLOCK DIAGRAM ORDERING INFORMATION
OUT1 OUT4
Device Package Operating Temperature
IN4 (-)
LM324N
IN4 (+) 14 DIP
LM324AN
0-+70°C
LM324D
14 SOP
IN3 (+) LM324AD
LM224N
14 DIP
LM,224AN
-25-+85°C
LM224D
14 SOP
LM224AD
SCHEMATIC DIAGRAM (One Section Only) 14 DIP
;LM2902N
-40- +85°C
LM2902D 14 SOP

R2
INPUT

"-"""'-------i-oOUT

c8SAMSUNG SEMICONDUCTOR 423

-tM2241A, LM3241A, LM2902 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol LM224/LM224A LM324/LM324A LM2902 Unit

Power Supply Voltage Vs ± 18 or 32 ± 18 or 32 ± 13 or 26 V

Differential I nput Voltage v,o 32 32 26 V
Input Voltage V, -0.3 to +32 -0.3 to +32 -0.3 to +26 V
Output Short Circuit to GND
Continuous Continuous Continuous
Vcc:s15V Ta=25·C (One Amp)
Power Dissipation Po 570 570 570 mW
Operating Temperature Range Topr -25- +85 0-+70 -40- +85 ·C
- Storage Temperature Range T stg -65-+150 -65:- + 150 -65 - +150 ·C

ELECTRICAL CHARACTERISTICS .
(Vcc=5.0V, Vee=GND, Ta=25·C, unless otherwise specified)

LM224 LM324 LM2902

Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max Min Typ Max

VeM=OV to Vcc-l.5V
Input Offset Voltage V,o 2.0 5.0 2.0 7.0 2.0 7.0 mV
Vo=l.4V, Rs=OO
Input -Offset Current 1'0 3 30 5 50 5 50 nA
Input Bias Current I'B 45 150 45 250 45 250 nA
Input -Common-Mode Vee=3OV Vcc Vcr. Vcc
V,eR 0 0 0 V
Voltage Range (Vee = 26V for LM2902) -1.5 -1.5 -1.5
RL=OO Vee =3OV(ali Amps)
1.5 3 1.5 3 1.5 3 mA
Supply Current lee (Voc=26V for LM2OO2)
RL =00 Vee =5V(all Amps) 0.7 -1.2 0.7 1.2 0.7 1.2 mA
Large Signal
Ay Vee = 15V, RL~2KO 50 100 25 100 100 V/mV
Voltage Gain
Vee Vee Vee
Output Voltage Swing VOUT RL = 2KO(LM2~2, RL~ 10KO) 0 0 0 V
-1.5 -1_5 -1.5
Common-Mode
CMRR 70 85 65 70 50 70 dB
Rejection Ratio
Power Supply
PSRR 65 100 65 100 50 100 dB
Rejection Ratio
Channel Separation CS f = 1KHz to 20KHz 120 120 120 dB
Short Circuit to GND los 40 60 40 60 40 60 mA
V'n+ =lV, Vin - =OV 40 mA
Isource 20 20 40 20 40
Vee=15V
V'n+ =OV, Vin _ = lV
Output Current ISlnk 10 20 10 20 10 20 mA
Vee =15V
Vin + =OV, Vin _ = lV
12 50 12 50 ,.A
Vo=200mV
f--------------
Differential Input
V,o Vee Vee Vee V
Voltage

c8 SAMSUNG SEMICONDUCTOR 424

LM2241A, LM3241A, LM2902 LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS
(Vee = 5.0V. VEE = GND. unless otherwise specified)
The following specification apply over the range of -25·CsTas + 85·C for the LM224; and the O·CsTas + 70·C
for the LM324; and the -40·CsTas +85·C for the LM2902·

LM224 LM324 LM2902

Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max Min Typ Max

VeM=OV to Vee·1.5V
Input Offset Voltage V,O 7.0 9.0 10.0 mV
Vo=1.4V. Rs=OO
Input Offset Voltage
6 Viol 6 T 7.0 7.0 7.0 /lV/·C
Drift
Input Offset Current 1'0 100 150 200 nA
Input Offset Current

II
61 ,01!\T 10 10 10 pA/·C
Drift
Input Bias Current liB 300 500 500 nA
Input Common·Mode vee=30V Vee Vee Vee
VieR 0 0 0 V
Voltage Range (Vee =26V for LM2902) ·2.0 ·2.0 ·2.0
Large Signal Voltage Vee = 15V. RL~2.0KO
Av 25 15 15 V/mV
Gain (for large Vo swing) '.
Vee = 30V IRL -2KO 26 26 22 V
VOH
Output Voltage Swing Vcc = 26V for 2902IRL= 10KO 27 28 27 28 23 24 V
VOL
Vcc=5V RLS10KO 5 20 5 20 5 100 mV
--
V.n+ = 1V. Vm =OV
lsource 10 20 10 20 10 20 mA
Vee =15V
Output Current
V.n+ =OV V.n_ = 1V
ISink 10 15 5 8 5 8 mA
Vee = 15V
Differential Input
V'c 'V ee Vee Vee V
Voltage

c8 SAMSUNG SEMICONDUCTOR 425

LM224/A, LM3241A, LM2902 LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS
(Vcc=5.0V, VEE=GND, Ta=25°C, unless otherwise specified) -

LM224A LM324A
Characteristic Symbol Test Conditions Unit
- - Min Typ Max Min Typ Max

VCM=OV to Vcc·1.5V
Input Offset Voltage V'O 1.0 3.0 2.0 3.0 mV
Vo=1.4V Rs=O
Input Offset Current 1'0 2 15 5 30 nA
Input Bias Current - I,e 40 80 45 100 nA
Inp!Jt Comm·Mode Vec Vec
V'CR Vcc = 30V 0 0 V
Voltage Range ·1.5 ·1.5
RL =00 Vce = 30V 1.5 3 1.5 3 mA
Supply Current (All Amps) Icc ~----~~--- --- f - - - - - - -

Large Signal Voltage Gain

-----~--

Av
RL=oo Vcc=5V
--~--~-

Vec= 15V RL<!:2KO 50

0.7
100
1.2
25
0.7
100
,.-
1.2 mA
--
V/mV
- -~
--
Vee Vec
Output Voltage Swing VOUT - RL=2KO 0 0 V
·1.5 ·1.5
----~--- ---- --
Common·Mode Rejection Ratio CMRR 70 85 65 85 dB
Power Supply Rejection Ratio PSRR 65 100 65 100 dB
-- ------ -------~- - . - - - ---
Channel Separation CS f = 1KHz to 20KHz 120 120 dB
------------------- ------ ---~----- -~- - - ---- - --
Short Circuit to GND los 40 60 40 60 mA
-------------~ --.--~ -- -- ----
Vm+ =1V Vm- =OV
Isource 20 40 20 40 mA
Vee =15V_
-------- ---~------ - 1---- --
Vm+ =OV V,n_ = 1V
Ou!put Current 10 20 10 20 mA
Vee = 15V
j ISlnk --
Vm+ = OV V,n_ = 1V
12 -50 12 50 p.A
Vo=200mV
----------------- - - - - -- - - - - - - - -
Differential Input Voltage VID Vee Vce V

c8 SAMSUNQ SEMICONDUCTOR 426

LM2241A, LM3241A, LM2902 LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS
(Vcc=5.0V, Vee=GND, unless otherwise specified)
The following specification apply over the range of - 25·C::::;Ta::::; + 85·C for the LM224A; and the O·C::::;Ta::::; + 70·C
for the LM324A

LM224A LM324A
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max

VeM =OV to Vee-1.5V

Input Offset Voltage V,O 4.0 5.0 mV
Vo=1.4V Rs=OO
-------------------- ~--
---------~--
- - 1------1---- ---- - --_.- --.- 1-----
Input Offset Voltage Drift fl.V,o/fl.T 7.0 20 7.0 30 /lV/·C
- - -- - - - --_.------- ~-
1---- ---- --~- - - - -- -_. ---- ----
Input Offset Current 1,0 30 75 nA
- - - ' - - - - - - - - - - - - - - --------- ~-------~--
1--- 1----- - - - - ----- --- --
Input Offset Current Drift fl.!,c,tfl.T 10 200 10 300 pA/·C
-- ------~----- ---- I---- ---- - - - - - - 1------

I
Input Bias Current liB 40 100 40 200 nA
-- - - -I - - - - - - ---- - - - - - - -
Input Common-Mode Vee Vee
VieR Vee = 30V 0 0 V
Voltage Range -2.0 -2.0
Large Signal Voltage Gain Av Vee = 15V RL~2.0KO 25 15 V/mV
Vee = 30V IRL = 2KO 26 26
VOH V
Output Voltage Swing IRL= 10KO 27' 28 27 28
VOL
Vee=5V RL::::;10KO 5 20 5 20 -rr;v-
- - --'- - - - - 1-----
V,n+ = 1V V,n_ = OV
Isource 10 20 10 20 mA
Vee = 15V
O.utput Current 1---- .. ---- ---- ----- ----- ------ 1-----
V,n + =OV V,n - = 1V
ISlnk 5 8 5 8 mA
Vee = 15V
-- -----
Differential Input Voltage V'D Vee Vee V

c8 SAMSUNGSEMICONDUcrOR 427
LM2241A, LM3241A, LM2902 . LINEAR INTEGRATED CIRCUIT

APPLICATION NOTE
The LM224 ~ries are opamps which operate with only a single power supply voltage, have true-differential inputs, and
remain in the linear mode with an input common-mode voltage of 0 Voc. These amplifiers operate over a wide range of power
supply voltage with little change in· performance charactaristics. At 25"C amplifier operation is possible down to a minimum
supply voltage of 2.3 Voc. .
The pinouts of the package have been designed to simplify PC board layouts. Inverting inputs are adjacent to outputs for
all of the amplifiers and the outputs have also been placed at the corners of the package (pins 1, 7, 8, and 14).
Precautions should be taken to insure that the power supply for the integrated circuit never becomes reversed in polarity
or that the unit is not inadvertently installed backwards ina test socket as an unlimited current surge through the resulting
forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit.
Large differential input voltages can be easily accommodated and, as input differential voltage protection diodes are not
needed, no large input currents result from large differential input voltages. The differential input voltage may be larger the
Vex; without damaging the device. Protection should be provided to prevent the input voltages from going negative more than
-030/00 (at 25"C). An input clamp diode with a resistor to the IC input terminal can be used.
To reduce the power supply current drain, the amplifiers have a class A output stage for small signal levels which converts
to class B in a large signal mode. This allows the amplifiers to both source and sink large output currents. Therefore both
NPN and PNP external current boost transistors can be used to extend the power capability of the basic amplifiers. The output
voltage needs to raise approximately 1 diode drop above ground to bias the on-chip vertical PNP transistor for output cur-
.rent sinking .applications.
For ac applications, where the load is capacitively coupled to the output of the amplifier, a resistor should be used, from
the output of the amplifier to ground to increase the class A bias current and prevent crossover distortion. Where the load
is directly coupled, as in dc applications, there is no crossover distortion.
Capacitive loads which are applied directly to the output of the amplifier reduce the loop stability margin. Values of 50 pF
can be accommodated using the worst-case noninverting unity gain connection. Large closed loop gains or resililive isola-
tion should be used if larger load capacitance must be driven by the amplifier.
The bias network of the LM224 establishes a drain current which is independent of the magnitude of the power supply
voltage over the range of from 3 Voc to 30 Voc.
Output short circuits either to ground or to the positive power supply should be of short time duration. Units can be destroyed,
not as a result of the short circuit current causing metal fusing, but rather due-to the large increase in IC chip dissipation
which will cause eventual failure due to excessive junction temperatures. Putting direct short-circuits on more than one amplifier
at a time will increase the totailC power dissipation to destructive levels, if not properly protected with external dissipation
limiting resistors in series with the output source current which is available at 25"C provides a larger output current capa-
bility at elevated temperatures (see typical performance characteristics) than a standard Ie op amp.
The circuits presented in the section on typical applications emphasize operation on only a single power supply voltage.
If complementary power supplies are available, all of the standard op amp circuits can be used. in general, introducing a
pseud~round (a bias voltage reference of VccI2) will allow operation above and below this valUe in single power supply sys-
tems. Many application circuits are shown which take advantage of the wide input common-mode voltage range which includes
ground. In most cases, input biasing is not required and input voltages which range to ground can easily be accommodated.

c8 SAMSUNG SEMICONDUCTOR 428

LM22~A, LM3241A, LM2902 LINEAR INTEGRATED CIRCUIT
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT VOLTAGE RANGE INPUT CURRENT
,. ,-----,..-----,..----"""7'1

10 ~--+--+-+--+--+-+--+--+----;

II
5 10 15 65 -35 -15 5 25 45 85 85 105 125
Fig. 1 POWER SUPPLY WLTAIlE (±Y) Fig. 2 TEIIPEIIATUIIE rei

SUPPLY CURRENT IIOLTAGE GAIN

160

1
r---
r---
-
p 1
/
...... r---.. ...........
L_20<II_

I
~21<D_

I!,-OOC'Y +
,
85"C V 40

I
10 20 30 10 20 30 40
Fig. 3 SUPPLY lIOLTAGE (V) Fig. 4 SUPPLY WLTMIE (V)
OPEN LOOP FREQUENCY COMMON MODE REJECTION
RESPONSE RATIO
120 I

I
I-"

o
100 lK
4
10K
. +
10""
1000

'00k
~

-•.soc

I rrr~111 III
lOOK
Yo

1M
Fig. 5 FREQUENCY (Hz) Fig. 6 F1IEOUENCY (Hz)

c8 SAMSUNG SEMICONDUCroR 429

LM2241A, LM3241A,. LM2902 LINEAR INTEGRATED CIRCUIT

VOLTAGEFO~ERPULSE VOLTAGE FOLLOWER PULSE

RESPONSE RESPONSE (SMALL SIGNAL)
500 I I

LJ
~
/
J I\.
\,
V+_15Vocl 450

-
J5t'
:'Vw
50pF

r\ 'If
INPU

·3

OUTPUT

300
1\.

V
T.-+25"C

r.-- VCr30r
250
10 20 30 «I o • 5
nME(001 nME(oo)
FIg. 7 FIg. 8
LARGE SIGNAL FREQUENCY OUTPUT CHARACTERISTICS
RESPONSE CURRENT SOURCING
20
I I IIIIII "'~ I I II
1IIIIIIlllllill
~;
15

-- +7VDC + 2K

1\
\

I
~
1K 10K 100K 1M
FREQUENCY (Hz) OUTPUT SOURCE CURRENT (mADe)
Fig. 8 Fig. 10
OUTPUT CHARACTERISTICS
CURRENT LIMITING
CURRENT SINKING
90

fi
10
I I I
-

V
80

70 -

:E 1
w

I Vcc ... +5Voc

Vcc=+15Voc
Vcc=+30Voc
............
.........
~o --..
0.1

1/.
v~~
vcc

20

10
~
~

- .........

V 111111111 111II1
0.001 om 0.1 1 10 100 -55 -35 -15 25 ' 45 6S 86 105 125
OUTPUT SlN~ CURRENT (rnA) T_EMrURErC)
fig. 11 fig. 12

c8·SAMSUNG SEMICONDUCTOR 430

LM2241A, LM3241A, LM2902 LINEAR INTEGRATED CIRCUIT

TYPICAL APPLICATIONS (Vee='5.0V)

Voltage Reference Non·lnverting DC Gain

Vee
+5V _ _ _ _ _ _

+Vo

~~-VVOUT Vo

Rl 1.0MO GAIN=l..;{
10K

V,N

Fig. 13 Fig. 14

AC Coupled Non·lnverting Amplifier

Rl R2
Pulse Generator
Rl
II
looKO Vee
1
Co
VOUT

RL
>-+--oVOUT

100KO

00 o...f1.I1....
AV=l+~
V
Rl
Av=ll ,
Fig. 15 Fig. 16
Bi·Quad Filter R

C looK!I

looKIl O _BW
- to
where
TBP=Center frequency gain
TN == Bandpass notch gain
1 Rl
to=2rRC R2=Tsp
R3
Rl =OR R3=TNR2
Cl =10C
Example: to = 1000Hz
R2 BW=100Hz
Cl Tsp=l
>--+--I/---<> ~~i~~T TN=l
R=lS0KIl
Rl=l.SMIl
R2=1,SMIl
R3= 1,6MIl
C=O.Ol"F
Fig. 17

c8 SAMSUNG SEMICONDUCTOR 431

 LM2481LM348 LINEAR INTEGRATED CIRCUIT

QUAD OPERATIONAL AMPLIFIERS

14 DIP
The LM2481LM348 is-' a true quad LM741. It consists of four
independent, high-gain, internally compensated, low-power operational
amplifiers which have been designed to provide' functional
characteristics identical to those of the familiar LM741 operational
amplifier. In addition the total supply current for all four amplifiers is
. comparable to the supply current of a single LM741 type OP Amp.
Other featur.es include input offset currents and input bias current which
are much less than those of a !ltandard LM741. Also, excellent isolation
between amplifiers has been achieved by independently biasing each
14 SOP
amplifier and using layout techniques which minimize thermal coupling.

FEATURES
• LM741 OP Amp operating characteristics
• Low supply current drain
• Class AB output stage-no crossover distortion
• PJn compatible with the LM324 & MC3403'
• Low Input offset voltage-1mV Typ.
• Low input offset current-4nA Typ.
• Low Input bias current·30nA Typ.
• Gain bandwidth product for LM348 (unity galn)-1.0MHz Typ.
• Channel seperatlon 120dB
• Overload protection for outputs

BLOCK DIAGRAM ORDERING INFORMATION

OUT4 Device Package Operating Temperature
IN4 (-} LM348N 14 DIP
0- +70'C
IN4 (+) LM348D 14 SOP
LM248N 14 DIP
-25-+85'C
LM248D' 14 SOP
IN3 (+)

IN3 (-)

OUT3

SCHEMATIC DIAGRAM (One Section Only)

r-~----------~--~~--------~~----------~-ovcc

NON INVERTING
INPUT

R9

INVE~J~~~ o---+--+-+--:-+-----' '----''WY-+--te-_te_------t----<J OUTPUT

Rl0

Q17

c8 SAMSUNG SEMICONDUCTOR 432

 LM2481LM348 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Ta =25°C)

Characteristic Symbol Value Unit

Supply Voltage Vs ±18 V

Differential Input Voltage V ID ±36 V
Input Voltage V, ±18 V
Output Short Circuit Duration Continuous
Operating Temperature LM248
Topr
-25-+85 'c
LM348 0-+70 'c
Storage Temperature Tstg -65-+150 'c

ELECTRICAL CHARACTERISTICS
(Vee = 15V, VEE = - 15V, Ta = 25'C, unless otherwise specified)

Characteristic Symbol Test Conditions

Min
LM248
Typ Max Min

1.0 6.0 I
LM348
Typ Max

! 1.0 -
6.0
Unit
II
Input Offset Voltage V,o RsS10KO ' - mV
Tamtn~Ta:::s;:T amax 7.5 7.5
~.

4 50 4 50
Input Offset Current 1'0 -j - - nA
Tamin:S Ta:S Tamax 125 100
30 200 30 200
Input Bias Current I'B nA
.Tam,nSTaSTamax 500 400
Input Resistance R, 0.8 2.5 0.8 2.5 MO
Supply Current (all Amplifiers) Is 2.4 4.5 2.4 4.5 rnA
25 160 25 160
Large Signal Voltage Gain Av RL~2KO Vim V
Ta.mnSTaSTamax 15 15
Channel Separation CS f = 1KHz to 20KHz 120 120 dB
Common Mode Input
V,eR TamtnSTa:sTamax ±12 ± 12 V
Voltage Range
Small Signal Bandwidth BW Av =1 1.0 1.0 MHz
Phase Margin ¢m Av=1 60 60 Degrees
Slew Rate SR Av=1 0.5 0.5 V/p.s
Output Short Circuit Current los 25 25 rnA
--
RL~ 10KO ±12 ±13 ± 12 ±13
Output Voltage Swing VOUT Tam,"STaSTamax V
RL~2KO ±10 ±12 ±10 ±12
Common Mode Rejection Ratio CMRR RsS10K Tam,n:sTa:sTamax 70 90 70 90 dB
Supply Voltage Rejection Ratio PSRR RsS10K Tamin:sTaSTamax 77 96 77 96 dB

'II TamtnSTaSTamax
LM248: Tam," = - 25'C, Tamax = + 85'C
LM348: Tam," = O'C, Tamax = + 70'C

c8 SAMSUNG SEMICONDUcrO~ 433

LM2481LM348 LINEAR INTEGRATED CIRCUIT
TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT VOLTAGE SWING.
50

~4O

I 4
I .~
i! ..
!; 30
L·
u
3 8
~ /
i
II>
g
20

~
.."ill 10
V ..
V
0~ __ ~ __- 4__ ~ ____ ~ __ ~ __ ~
o
o. 10 15 20 o 5 10 15 20 25
Fig. 1 SUPPLY VOLTAGE (± V) Fig. 2 SUPPLY VOLTAGE (± V)

SOURCE CURRENT LIMIT SINK CURRENT LIMIT

5 -1
r 51. r
Vs= ±15V
Vs '" ±15
T._25"C T.=25"C

1\, --- ~ i'-...

0

1,\
1\ 5

\
0
o 5 10 15 20
\ 25 30
0
5 10 15 20 25 30
Fig. 3' OUTPUT SOURCE CURRENT (mAl Fig. 4 OUTPUT SINK CURRENT (mAl

OUTPUT IMPEDANCE COMMON-MODE REJECTION RATIO

lk 120
FV,=±15 VS =I±15V
!==T.=25·C
T.-25·C
100

~
k/'"
A,=
eo

~
A
~
,;..t! I
~~
= ~~ I 60

, o. 1
=7-
-7

100
./

lk
Fig. 5
.,7
/
;";'-1

10k
FREQUENCY (Hzl
lOOk 1M
40

20

100
Fig. 8
lk
" ~
10k
FREQU~ (Hz)
~
lOOk

c8 SAMSUNG SEMICONDUCTOR 434

LM2481LM348 LINEAR INTEGRATED CIRCUIT
OPEN LOOP FREQUENCY RESPONSE BODE PLOT
110 20 100

VsJ±15~- 15 ~ II
........... -..... JHls~
LLk) 90

"
T.-25°C. T•• 25·C
90 10 80
I'-
70
r\. "r-.. .... 70

Ii
I'-
i
l!.
!! 50
3
"" !!
3 -10
-5
'"~

-rn
\ ,GAiN

""
-15 . 1k
30
-20 \ ~ 20
\ '\
10

-10
r\.

"
-25 - I

-30

-35
-
+
2k \ , -10
10

I
10 100 lk 10k lOOk 1M 0.1 10
Fig. 7 FREQUENCY (Hz) Fig. 8 FREQUENCY (MHz)

LARGE SIGNAL PULSE RESPONSE SMALL SIGNAL PULSE RESPONSE

10
Jo 100
Jo A~-1 .I.
v,- ±15V-

/
/ Av=1
Vs - t15V
\ , 0
I
I 1\
T.=25°C

RL 0!!2k

i
/ T.-25°C
\ II I \
II \ II \
~ -10 'f 0
i

10
"IN
100 v"

-10 -100

40 80 120 160 200 2 3

Fig. 9 TIME (PS) Fig. 10 TIME(",,)

UNDISTORTED OUTPUT VOLTAGE SWING INVERTING LARGE SIGNAL PULSE RESPONSE

32
vs~ ~1~J Jo

R'=f~
10V V,I.±1Jv-
R,=2k I
.... T.=25°C
Av ·1 I I\. A'=-1~_
T.-25·C
<1%DIST
II \
J \
i
II \
\.
\
a- 10

\.
10

"IN
"-10

o
100 1k 10k 100k o 20 40 60 80 100 120 140 180 180 200
Fig. 11 FREQUENCY (Hz) Fig. 12 TIME ws)

c8 SAMSUNG SEMICONDUCTOR 435

LM248/LM348 LINEAR INTEGRATED CIRCUIT

POSITIVE COMMON·MODE INPUT

INPUT NOISE VOLTAGE AND NOISE CURRENT
VOLTAGE LIMIT
160 (6 20
v!_L~t J
1/
I I
~ -2SoC::s;Ta::s; +85°C
140 T.",,25°C 1.4 !::
!
I
1.2 i
~ ~
.!i! 15
/
/
1.0 ;

1\ 0.8
I§.
:>
Q,
iI
I!I
~ MEAN NOISE VOLTAGE
0.6
u
§ ~
w

0
:E 10
/
/
MEAN NOISE CURRENT
0.4 ~
:E
:E
8
!l!
i=

/
20 0.2
~
Q,

o 0 5
10 100 lk 10k 5 10 15 20
Fig. 13 FREQUENCY (Hz). . Fig. 14 POSITIVE SUPPLY VOLTAGE (V)

NEGATIVE COMMON - MODE INPUT

VOLTAGE LIMIT .

Fig. 15 NEGATIVE SUPPLY VOLTS (V)

c8 SAMSUNG SEMICQNDUcroR 436

LM2481LM348 LINEAR INTEGRATED CIRCUIT

TYPICAL APPLICATIONS
Function Generator
TRIANGLE WAVE
OUTPUT R2

VREF

>-+----<0 SQUARE WAVE OUTPUT

1= Rl +R3
4CRIRI
II R3= R2Rl
R2+Rl

Bi·Quad Filter
Fig. 16

R
I
R

C 100Ka

Cl R2
Y,N o--U-.--'li"ltr--+---I l00Ka

VREF' Rl VREF R3

R2
Cl
>--+---11---0 NOTCH OUTPUT
Q=BW Example: 10 = 1000Hz
10 BW=I00Hz
where Tsp=1
VREF TSp = Center frequency gain TN=1
TN = Bandpass notch gain R = 160Ka
Rl=I.6MIl
1 Rl R2=1.6MIl
10 = 27RC R2 = TBP R3= 1.6Ma
Rl =QR R3=TNR2 C=O.Q1~F
Cl=10C
Fig. 17

c8 SAMSUNG SEMICONDUCTOR 437

LM2581A, LM358/A, LM2904 LINEAR INTEGRATED'CIRCUIT .

QUAD OPERATIONAL AMPLIFIERS

The LM258 series consists of four independent, high gain, internally 8 DIP
frequency compensated op~rational amplifiers which ·were deSigned
speCifically to operate from a single power supply over a wide range
of voltage. \
Operation from split power supplies is also possible and the low power
supply 9urrent drain is independent of the magnitude of the power supply
voltage,
Application areas include transducer ampliti.er, DC gain blocks and all a SOP
the conventional OP amp circuits which now can be easily Implemerl'ted
In single power supply systems.

FEATURES.
• Internally frequency compensated
• Large DC voltage gain: 100dB 9 SIP
• Wide power supply renge: LM258JA, LM358IA: 3V - 32V
(or ±1.5V-16V)
LM2904: 3V - 26V (or ± 1.5V - 13V)
• Input common·mode voltage range Includes ground
• Large output· voltage swing: OV DC to Vee - 1.5V DC
• Power drain suitable for battery operation.

BLOCK DIAGRAM

;:: I +
::>
0
~ ~

SCHEMATIC DIAGRAM (One section only) ORDERIN'G INFORMATION

VCC~--~~--------~--~~r-----~, Device Package Operating Temperatur
LM358N
8 DIP
LM358AN
LM358S 9 SIP O-+70·C
LM358D
8 SOP
LM358AD
LM258N'
8 DIP
LM258AN
LM258S 9SIP -25-+85·C
LM258D
8 SOP
LM258AD
LM2904N 8 DIP
-40-+85·C
LM2904D 8 SOP

c8 SA~SUNG SEMICONDUCTOR 438

LM258/A, LM358IA, LM2904 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol LM2581LM258A LM3581LM358A LM2904 Unit

Power Supply Voltage Vs ± 16 or 32 ± 16 or 32 ±13 or 26 V

Differential Input Voltage VIO ±32 ±32 ±26 V
Input Voltage VI -0.3 to +32 -0.3 to +32 -0.3 to +26 V
Output Short Circuit to GND
Continuous Continuous Conti'nuous
VeeS15V Ta=25·C (One Amp)
Operating Temperature Range Topr -25-+85 0-+70 -40-+85 ·C
Storage Temperature Range Tstg -65-+150 -65 - +150 -65-+150 ·C

ELECTRICAL CHARACTERISTICS
(Vee = 5.0V, Vee=GND, Ta=25·C, unless otherwise specified)

Characteristic Symbol Test Conditions

LM258 LM358 LM2904
Unit
I
Min Typ Max Min Typ Max Min Typ Max

VeM=OV to Vee-1.5V
Input Offset Voltage VIO ±2.0 ±5.0 ±2.0 :t7.0 ±2.0 ±7.0 mV
Vo= 1.4V, Rs=OO
Input Offset Current 110 ±3 ±30 ±5 ±50 ±5 ±5O nA
Input Bias Current liB 45 150 45 250 45 250 nA
Input Common-Mode Vee = 30V Vee Vee Vee .
VieR 0 0 0 V
Voltage Range (LM2904, Vee = 26V) -1.5 ·1.5 -1.5
Rl=oo Vcc= 3OV(LM2902, Vcc =26V) 1.0 2.0 1.0 2.0 1.0 2.0 rnA
Supply Current lee
Rl =00 over full temperature range 0.7 1.2. 0.7 1.2 0.7 1.2 rnA
Large Signal
Av Vee = 15V, RL~2KO 50 100 25 100 100 V/mV.
Voltage Gain
Vee Vee Vee
Output Voltage Swing VOUT RL = 2KO(LM2904, RL~ 10KO) 0 0 0 V
-1.5 -1.5 -1.5
Common-Mode - CMRR 70 85 65 70 50 70 dB
~ejection Ratio

Power Supply
PSRR 65 100 65 100 50 100 dB
Rejection Ratio
Channel Separation CS f = 1KHz to 20KHz 120 120 120 dB
Short Circuit to GND los 40 60 40 60 40 60 rnA
Vln +=1V, Vln_=OV
lsource 20 40 20 40 20 40 rnA
Vee =15V
Vln + =OV, Vln _ = 1V
Output Current ISlnk 10 20 10 20 10 20 rnA
Vee =15V
Vln+ = OV, Vln _ = 1V
12 50 12 50 p.A
Vo=2oomV
Differential Input
VIC .Vee Vee Vee V
Voltage

c8 SAMSUNG SEMICONDUCTOR. 439

LM2581A, LM358/A, LM2904 LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS
(Vee = 5.0V, VEE = GND, unless otherwise specified)
The following specification apply over the range of - 25·CsTas + 85·C for the LM258; and the O·CsTas + 70·C
for the LM358; and the -40·CsTas +85·C for the LM2904

LM258 LM358 LM2904

Characteristic ~ymbol Test Conditions
Min Typ Max Min Typ Max Min Typ Max

VCM=OV to Vcc-1.5V :!:7.0 :!:9.0 :!:10.0 mV

Input Offset Voltage VIO
Vo=1.4V, Rs=O
Input Offset Voltage
6V loI6T· Rs=OD 7.0 7.0 7.0 /LV/·C
Drift
Input Offset Current 110 :!:100 :!:150 ±45 ±200 nA
Input Offset Current
61 10/6T 10 10 10 pA/·C
Drift
Input Bias Current liB 40 300 40 500 40 500 nA
Input Common-Mode VCC= 30V Vcc Vcc Vcc
VICR 0 0 0 V
Voltage Range (LM2904, Vee = 26V) -2.0 -2.0 -2.0
Large Signal Voltage
Av Vee = 15V, RL~2.0KD 25 15 15 V/mV
Gain
VCC= 30V IR =2KD 26 25 22
VOH V
Output Voltage Swing Vee=26V for 2904IRL= 10KD 27 28 27 28 23 24
VOL Vce=5V RLS10KD 5 20 5 20 5 100 mV
V;n+ = 1V, V,n=OV
lsource 10 20 10 20 10 20 rnA
Vee = 15V
Output Current
V;n+ = OV V;n_ = 1V
ISink 5 8 5 8 5 8 rnA
Vee = 15V

c8 SAMSUNG SEMICONDUCTOR 440

LM258/A, LM358/A, LM2904 LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS
(Vcc=5.0V, VEE=GND, Ta=25°C, unless otherwise specified)

LM258A LM358A
Characteristic Symbol Test Conditions
Min Typ Max Min Typ Max

VCM=OV to Vcc·1.5V
Input Offset Voltage V,o 1.0 3.0 2.0 3.0 mV
Vo=1.4V Rs=O
Input Offset Current 1'0 2 15 5 30 nA
Input Bias Current I'B 40 80 45 100 nA •
Input Comm-Mode Vcc Vee
V,CR Vcc = 30V 0 0 V
Voltage Range ·1.5 ·1.5
RL =00 Vee = 30V 1.0 2.0 1.0 2.0 rnA
Supply Current

Large Signal Voltage Gain

Output Voltage Swing

lee

Av
VOUT
Rl :ooover full temperature range
Vee = 15V RL<!:2KO

Rl=2KO
50

0
0.7
100
1.2

Vce
·1.5
25

0
0.7
100
1.2

Vee
-1.5
rnA
V/mV

V
II
Common-Mode Rejection Ratio CMRR 70 85 65 85 dB
Power Supply Rejection Ratio PSRR 65 100 65 100 dB
Channel Separation CS f = 1KHz to 20KHz 120 120 dB
Short Circuit to GND los 40 60 40 60 rnA
V'n+ =1V Vin - =OV
Isource 20 40 20 40 rnA
Vcc= 15V

Output Current
V'n+ =OV Vin - = 1V
Vce= 15V
10 20 10 20 rnA ..
ISink
Vm+ = OV V,n_ = 1V
12 50 12 50 rnA
Vo=2oomV
Differential Input Voltage V,~ Vec Vcc V

ciS SAMSUNG SEMICONDUCTOR 441

lM258/A, -LM358IA, LM2904 LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS (Vcc=5.0V, VEE=GND, unless otherwise specified)

The following specification apply over the range of - 25·C;sTa;s + 85·C forthe LM258A; and the O·C;sTa;s + 70·C
for the LM358A

LM258A LM358A
Characteristic Symbol Test Conditions Unit
Min Typ 'Max Min Typ Max

VCM=OV 0 Vcc·1.5V
Input Offset Voltage V'O 4.0 5.0 mV
Vo=1.4V Rs=OO
~--- -
Input Offset Voltage Drift 6V,o/6T Rs=OO 7.0 15 .7.0 20 p,V/·C
Input Offset Current 1'0 30 75 nA
Input Offset Current Drift 61,oI6T 10 200 10 300 PArC
Input Bias Current I,s 40 100 40 200 nA
Input Common·Mode Vee Vce
V'CR Vcc=30V 0 0 V
Voltage Range ·2.0 ·2.0
Large Signal Voltage Gain Av Vee = 15V RL~2.0K!l 25 15 'V/mV
v ee =30vIR =20KO 26 26 V
VOH
Output Voltage Swing IRL=10KO 27 28 27 28 V
VOL Vee=5V RL;S10KO 5 20 5 20 mV
V,n + = 1V V,n_ =OV·
Isource 10 20 10 20 rnA
Vee = 15V
Output Current
V,n + =OV V,n_ = 1V
Isink 5 8 5 8 rnA
VCC= 15V
Differential Input Voltage VID Vec Vee V

c8 SAMSUNG SEMICONDUCTOR 442

LM258/A, LM358/A, LM2904 LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS

SUPPLY CURRENT VOLTAGE GAIN

! I I
I
1-- . - ~.
---- ~--"
I
1--- -~~ 120 f - -
RL=L
iii /
V ""';too
t---- S
z
C
CO 80
w
CO
I ~ I--
0
>
1 40
Ta=O°C to +85°:""-
V !

II
I
10 20 30 10 20 30
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)

OPEN LOOP FREQUENCY RESPONSE LARGE SIGNAL FREQUENCY RESPONSE

f~"
Vee 100KD

,20
lOMo
lKO [r--
~o
~ V"
112 Vee V''! !J{;
112Vcc

40 I-
'" ~
~
V.. -10to 15V AND'
I -25'C.:Ta.:+85'C
I 11
~~5~:h~~85,d

~
\.
r....

"~ o
lK 10K
r--..
100K
10 , 100 1K 10K lOOK 1M I (Hz)
FREQUENCY (n FREQUENCY (n

OUTPUT CURRENT SOURCE OUTPUT SINK CURRENT

Vee

'~' '~:/,- Vo
J

3
1

t- I--V+-+5VOC
I--V+-+3OVDC
V+-+15\1tJc

ITa= +25°C
- ,......1/

1 1

'/ I
. II
1
/ '/J
J

1 0D1 / r// !
0JlD1 0D1 0.1 10 100 0JlD1 0D1 0.1 10
QUTPUT SOURCE CURRENT (mAl OUTPUT SINK CURRENT (mAl

c8 SAMSUNG SEMICONDUCTOR .443

LM258/A, LM358/A, LM2904 LINEAR INTEGRATED CIRCUIT
INPUT COMMON·MODE VOLTAGE RANGE COMMON·MODE REJECTION RATIO

v ,r ii 120
Ne~~E V
,r ~ 100 r-
V
,r
,r V POSm~ ~ SO
V
1/ ,r
,r
I SO r--r-
- Y
+ 7.5V 100KD

V
1/ V
1/ V
,r
i~ r--r- -
f-r- -
I-r- - +
20 I-r- ...':!w
looo1 ... ~\
1000 I, .
1
Yo- -1-1-

V f-r- -
l00KiJi
-- - I -
II'" o
10 100 lK 10K lOOK
SUPPLY VOLTAGE (y) FREQUENCYCI)

c8 SAMSUNG SEMICONDUCTOR 444

LM258IA, LM358IA, LM2904 LINEAR INTEGRATED CIRCUIT

TYPICAL APPLICATIONS (Vee =5.0V)

Voltage Reference Non-Inverting DC Gain
Vee
+5V _____ _

+Vo

AC Coupled Non-Inverting Amplifier

RI R2
Pulse Generator
Rl
II
>--f--,-Q 1I0UT

f\f\ 2 V p•p
V
AV=II

Bi-Quad Filter
R

R
C lOOK!!

C Q _BW
Cl F.l2 100KO - 10
VIN o---f I---<~~Ir--+--I 100KIl where
TBP=Cenler Irequency gain·
TN = Bandpass notch gain
I Rl
10= 2 ..RC R2=TBP
Rl =QR R3=TNR2
R3 • Cl=10C
VREF Example: 10 = 1000Hz
BW=100Hz
TBP=1
R2
TN=1
R=160KIl
Rl=I.6M!I
R2=1.6MIl
R3=1.6MIl
C=O.OlpF

c8 SAMSUNG SEMICONDUCTOR 445

LM741 C/LM741'E1LM7411 LINEAR INTEGRATED CIRCUIT

8 DIP
SI~GLE OPERATIONAL AMPLI~IERS .. '
The LM741 series are general purpose operational amplifiers which
feature improved performance over industry standards like the LM709. '
It Is intended for a wide range of analog applications.
The high gain and wide range of operating voltage provide superior
performance in Intergrator, summing amplifier, and general feedback
applications.
8 SOP
FEATURES
• Short circuit protection
• Excellent temperature stability
• Internal frequency compensation
• High Input voltage range
• Null of offset

BLOCK DIAGRAM ORDERING INFORMATION

OFFSET Device Package Operating Temperature
NULL
LM741EN
8 DIP
LM741CN
0- +70·C
LM741ED
8 SOP
LM741CD
OFFSET LM7411N 8 DIP
NULL -40- +85·C
LM7411D 8S0P

SCHEMATIC DIAGRAM
'INVERTING INPUT

5 OFFSET NULL

c8 SAMSUNG SEMICONDUCTOR 446

LM741C/LM741 ElLM741I· LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)

Characteristic Symbol LM741C LM741E LM741 I Unit

Power Supply Voltage Vs ±18 ±22 ±18 V

Differential Input Voltage VIO ±30 ±30 ±30 V
Input Voltage VI ±15 ±15 ±15 V
Output Short Circuit Duration Indefinite Indefinite Indefinite
Power Dissipation Po 500 500 500 mW
Operating Temperature Range Topr 0-+701 0-+701 -40- +85 .0C
Storage Temperature Range Tstg -65 -+.150 -65-+150 -65-+150 °C

ELECTRICAL CHARACTERISTICS

II
(Vcc =15V, VEE= -15V, Ta=25°C, unless otherwise specified)

LM741E LM741C/LM741I
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max

RsS10KD 2.0 6.0

Input Offset Voltage VIO mV
RsS500 0.8 3.0
Input Offset Voltage
VIOR Vs= ±20V ±10 ±15 mV
Adjustment Range
Input Offset Current 110 3.0 30 20 200 nA
Input Bias Current liB 30 80 80 500 nA
Input Resistance· RI Vs= ±20V 1.0 6.0 0.3 2.0 MO
Input Voltage Range VICR ±12 ±13 ±12 ±13 V
Vs= ±20V,
Vo=±15V 50
Large Signal Voltage Gain Av RL~2KO V/mV
Vs=±15V,
20 200
Vo= ±10V
Output Short Circuit Current los 10 25 35 25 mA
HL~10KO ±16
Vs= ±20V
RL>2KO ±15
Output Voltage Swing VOUT V
RL~10KO ±12 ±14
Vs=±15V
RL~2KO . ±10 ±13
Rss10KO, VCM = ±12V 70 90
Common MOQe Rejection Ratio CMRR dB
Rss50KO, VCM = ± 12V 80 95
Vs = ±20V to Vs = ±5V
80 96
RsS500
Power Supply Rejection Ratio PSRR dB
Vs= ±15V to Vs = ±5V
77 96
RsS10KD

c8 SAMSUNG SEMICONDUCTOR 447

 LM741 C/LM741 ElLM7411 LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS (Continued)

LM741E LM741C/LM741I
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max

Transient I Rise Time t,

Unity Gain
0.25 0.8 0.3 p's
Response
I Overshoot OS 6.0 20 5 %
Bandwidth BW 0.43 1.5 1.0 MHz
Slew Rate SR Unity Gain 0.3 0:7. 0.5 V/p.s
Supply Current Is RL=co !l 1.7 2.8 mA
Vs= ±20V 80 150
Power Consump.tion Pc - mW
Vs= ±15V 50 85

ELECTRICAL CHARACTERISTICS
(- 25·C:sTa:s85·C for the LM7411, 0·C:sTa:s70·C for the LM741C, LM741 E, Vee = + 15V, VeE = -15V, unless
otherwise specified)

LM141E LM741C/LM741I
Characteristic Symbol Test Conditions Unit
Min I Typ Max Min Typ Max

Rs:s500 4.0
Input Offset Voltage VIO mV
Rs:s10KO 7.5
Input Offset Voltage Drift t,Vldt, T 15 p.V/·C
Input Offset Current . 110 70 300 nA
Input Offset Current Drift t,lldt, T 0.5 nA/oC
Input Bias Current liS 0.21 0.8 nA
Input Resistance Ri Vs = ±20V 0.5 MO
Input Voltage Range VICR ±12 ±13 ±12 ±13 V
RL~ 10Kfr ±16
Vs= ±20V
RL~2KO . ±15
Output Voltage Swing VOUT V
RL~10KO ±12 ±14
Vs=±15V
RL~2KO ±10 ±13'
Output Short Circuit Current . los 10 40 mA
Rs:s10KO, VCM = ± 12V 70 90
Common Mode Rejection Ratio CMRR dB
Rs:s50KO, VCM = ± 12V 80 95
Vs= ±20V Rs:s500 86 96
Power Supply Rejection Ratio PSRR dB
to±5V Rs:s10KO 77 96
Vs= ±20V,
32
Vo= ±15V
Vs=±15V,
Large Signal Voltage Gain Av RL~2KO 15 V/mV
Vo = ±10V
Vs= ± 15,
Vo=2V 10

.c8 SAMSUNG SEMICONDUCTOR 448

LM741C/LM741 ElLM741I LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS

INPUT OFFSET CURRENT .. SUPPLY VOLTAGE POWER CONSUMPTION va SUPPLY VOLTAGE
5.0 100

i 4.0
TaJ25 c- 0

80
Ta=L.c
/
L
i
Iii 3.0
~
~ r--
V
/

i L
~
35 2.0
20 ./
V
V
V
I
1.0
5 10 15 20 10 15 20
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
Fig. 1 FIg. 2

OPEN LOOP VOLTAGE GAIN VI FREQUENCY OPEN LOOP PHASE RESPONSE .. FREQUENCY
10' 0

10'
h
1\
'"
-45
10' ~:~':S!~V-

1\
Va= :!::15V
Ta=25-C
z
.."3 10' I" i

'"I"I"
"9.- 90
~
0
>
10'

~ f'
10'
--135

'0'

10-
10 100 1K 10K lOOK 1M
1\ 10M
-180
10 100 1K 10K lOOK 1M 10M
FREQUENCY (HI) FREQUENCY (Hz)
FIg. 3 Fig. 4

OUTPUT VOLTAGE SWING .. LOAD RESISTANCI' OUTPUT VOLTAGE SWING .. FREQUENCY

28 j.--"'"
28
I--r- 36I--H++-+--+-t-t+++H++-:i-tit-l
...... j..-"'"
IE 24 !E32I--H++-+--+-t-t++-+-H+-+--:i-tit-l
I V i:::S!~V- "! 28 I-++++-+--H++-+-+-t++-+--+tit-l
22
II ~
~ 20
~ 24 f---+-+tt---t--t-t-tt---tt----t-ttt-~:·:~!~V I
S 18 § 20 f--t-+t+-+-+-+++--+--\-t
\-+tHr-t--HH---t
~
;S
... 18 ~ 161--t+H-t-+-+++-~\~~-t--t-~-i
I'! 14 I I'!~ 12r-t-+t+-+-+-+++--+-~~---t----t-~-1
~

~ 12 1 ;S
... 8 1--t+H-t-+-+++-~+f\j--+-t-~-i
II
10

0.1
I 0.2 o.s 1.0 2.0 5.0 10
Ol=OO~~-l=K~~L,=~~-ll~l=OOK="~--~lM.
LOAD RESISTANCE \KClI FREQUENCY (HI)
FIg. 5 FIg. I

c8 SAMSUNG SEMICONDUCTOR 449

LM741C/LM741 ElLM741I LINEAR INTEGRATED CIRCUIT

INPUT RESISTANCE AND INPUT CAPACITANCE

OUTPUT RESISTANCE va FRE.QUENCY va FREQUENCY
600 10M 100 .

R,.
500 r-
~:~:5~~V -. s: lto<
'"1\ 1

- h

II
I
a:
!;
~100K C" 1
f--~

100
~

1 10K 0.1
100 1K 10K lOOK 1M 100 lK 10K lOOK 1M
FREQUENCY (Hz) FREQUENCY (Hz)
Flg.7 Fig••
INPUT BIAS CURRENT vs AMBIENT INPUT RESISTANCE vs AMBIEIIIT TEMPERATURE
'TEMPERATURE
100 10

--- .....- --
----
7.0
80

Vs=±15V~
1
..
!Z
a:
80
.!i~l 5.0

i
a:
"
U 3.0

..;II
- --
Vs= ::I::15V a:

.
!;
40
r-- r- .
!;
! 2.0
!
20 r--

o 1.0
o 10 20 30 40 50 so 70 o 10 20 30 40 50 60 70
TEMPERATURE (.C) TEMPERATURE (.C)
FIg. 8 Flg.l0
INPUT OFFSET CURRENT va AMBIEIljT POWER CONSUMPTION vs AMBIENT
TEMPERATURE TEMPERATURE
100

~
I. .

--
. Vs= ±20V - 90
r---..... Ii
.sz Va= ::t:15V
.......
r--.... .......

-- ........
0
~ so
lI!
"
II)
--- r-- r- io-.
...8~
a: 70

.
60

o 50
o 10 20 30 40 50 80 70 o 10 20 30 40 50 60 70
TEMPERATURE (.C) TEMPERATURE (.C)
Fig. 11 Flg.12

c8 SAMSUNG SEMICONDUCTOR 450

LM741C/LM741 ElLM741I LINEAR INTEGRATED CIRCUIT

OUTPUT SHORT CIRCUIT CURRENT TRANSIENT RESPONSE

va AMBIENT TEMPERATURE
30 28

24
28

~.
28
r-.... 1'000..
20
90%/
I-\.

ii . . r----..
II:
II:

"ut: 24
....... J
~ f'... i'..... I
Ii:
0
:z:
In
22

""""
II Va= ±15V_
Ta=2SoC
10% Rl=2Kn
20
I----' RISETIr C'=JlOPF-

II
18
01020 30 40 50 6070 0.5 1.0 1.5 2.0 2.5
TEMPERATURE (0C) TIME fl. ••
Fig. 13 Fig. 14
VOLTAGE FOLLOWER LARGE SIGNAL COMMON MODE REJECTION RATIO
PULSE RESPONSE .s FREQUENCY
10 100

90
!
" "-
..1 iiJ I
Vs= ±15V_ 3!.
i:~:5!~V -
-- - Ta=2S"C Q

iz
80

70
1\
VOUTPUT I' ~ 60
j I j\ u
w
Ul 50
['I..
II \
"- 1\
INPUT I. II:
W

I "
0 40

~
::IE
I z
f- 1- -- \ 0
::IE
::IE
0
u
30

20 "-
-8 10

-10
• 20 30 ~ 50 60 70 60 90 10 ,00 1K 10K lOOK 1M 10M
OUTPUT VOLTAGE (V) TIME fl..) FREQUENCY (Hz)
FIg.1S fig. 16

c8 SAMSUNG SEMICONDUCTOR 451

MC14581MC1458C/MC14581 LINEAR INTERGRATED CIRCUIT

DUAL OPERATIONAL AMPLIFIERS

a DIP
The MC1458 series is a dual general purpose operational amplifier.
The MC1458 series is a short circuit protected and require no external
components for frequency compensation.
High common mode voltage range and absence of "latch up" make the
MC1458 ideal for use as voltage followers.
The high gain and wide range of operating voltage provides superior
performance in intergrator, summing amplifier and general feedback
a SOP
applications.

FEATURES
• Interal frequency compensation
• Short circuit protection 9 SIP
• Large common mode and differential voltage range
• No latch up
• Low power consumption

BLOCK DIAGRAM

;: I + w
w +
:> >
0
~ ~ '":i!::
ORDERING INFORMATION
Device Package Operating Temperature
MC1458CN
8 DIP
MC1458N o -+70·C
MC1458S 9 SIP
MC1458D
8 SOP O-+70·C
MC1458CD
MC1458IN 8 DIP
-25-+85·C
MC1458ID 8 SOP

ciS SAMSUNG SEMICONDUCTOR 452

MC14581MC1458C/MC14581 LINEAR INTERGRATED CIRCUIT

SCHEMATIC DIAGRAM
r-t------?---~----<t--~--------~-<>VCC

R6

OU,PUT

R7

II
VEE

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Power Supply Voltage Vs ±18 V

Inp'lt Differential Voltage VID ±30 V
Input Voltage V, ±15 V
Operating Temperature Range MC14581 Topr -25- +85 ·C
MC14581C 0-+70 ·C
Storage Temperature Range Tstg -65-+150 ·C

c8 SAMSUNG SEMICONDUCTOR 453

MC14581MC1458C/MC14581 LINEAR INTERGRATED .cIRCUIT

ELECTRICAL CHARACTERISTICS
(Vs = ± 15V, Ta = 25°C, unless otherwise specified)

MC14581MC14581 MC1458C
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max

Input Offset Voltage V,o RsSl0KO 2.0 6.0 2.0 10 mV

--
Input Offset Current 1'0 20 200 20 300 nA
Input Bias Current I,s 80 500 80 700 nA
--
Large Signal Voltage Gain Av Vo = ± 10V, RL~2"OKO 20 100 20 100. V/mV
--
Input Voltage Range V'CR ±12 ±13 ± 11 ±13 V
Input Resistance R, 0.3 1.0 1.0 MO
--~--~.

Common Mode Rejection Ratio CMRR Rssl0KO 70 90 60 90 dB

---
Power Supply Rejection Ratio PSRR Rssl0Kil 77 90 77 90 dB
Supply Current (Both Amplifier) Is 2.3 5.6 2.3 8:0 mA
-----_.-
RL=10KO ±12 ±14 ± 11 ±14
Outp'ut Voltage Swing VOUT V
RL=2KO ±10 ±13 ±9 ±13
Output Short Circuit Current los 20 20 mA
-'-
Power Consumption Pc Vo=OV 70 170 70 240 mA
---~---

Transient Response (Unity Gain)

Rise Time t, V,=20mV, RL~2KO, CLS100pF 0.3 0.3 p,s
Overshoot OS V,=20mV, RL~2KO, CLS100pF 15 15 -%
Slew Rate SR V,=10V, RL~2KO, CLsl00pF 0.8 0.8 V/p,s

ELECTRICAL CHARACTERISTiCS
(TamonSTaSTamax, Vs = ± 15V, unless otherwise specified)

MC1458/MC14581 MC1458C
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max

Input Offset Voltage V,o RsSl0KO 7.5 12 mV

--------
Input Offset Current 1'0 300 400 nA
---------
In"put Bias Current I,s 800 1000 nA
Large Signal Voltage Gain Av Vo ~ ± 10V, RL~2.0K 15, 15 V/mV
Common Mode Rejection Ratio CMRR Rssl0K 70. 90 70 90 dB
Power Supply Rejection Ratio PSRR Rssl0K 77 90 77 90 dB
--
RL= 10K. ±12 ±14 ± 11 ±14
Output Voltage Swing VOUT V
RL=2K ±10 ±13 ±9 ±13
---------
Input Voltage Range V'CR ±12 ±12 V

* Tamm:sTa:s:Tamax
MC14581: Tam'n = - 25·C, Tamax = + 85°C
MC45581C: Tamon = O·C, Tamax = 70·C

c8 SAMSUNG SEMICONDUCTOR 454

MC1458/MC1458C/MC14581 LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS

OPEN·LOOP VOLTAGE GAIN.8 POWER
OPEN·LooP FREQUENCY RESPONSE
SUPPLY VOLTAGES
120 120

115
100

I: 110
!. - eo "-
'"I'" I'"
105

5l
!:i 100
,......V""
Ii!
/
....g
z
95

~
20
Ie
a
90

85

eo
30 6.0 9.0 12 15
POWER SUPPLY 'VOLTAGE (V)

POWER BANDWIDTH
Fig. 1
18 21
-20
10 100 1K 10K
FREQUENCY (Hz)
Fig. 2
OUTPUT VOLTAGE SWING '8 LOAD
lOOK
1\
1M 10M I
(LARGE SIGNAL SWING va FREQUENCy) RESISTANCE
32 32

28 28 IILI
Vs = ±15V
I I I I
24
'" 24

"1
~ 20 r- --- -- ~ ~ 20 V U±112l

/~
w

~ 16
\ g~ 16
Ii! l-

II.
I-
~ i! 12
12
8 10KI +
Vo

8.0
AL=2K
VOl:rAGE FOLLOWER
\ ./ 11rr 9.1K R,
4.0
r-j1iITiSurl'iiTr5i i' THOr°'l' IIIII i III
°10 100 1K 10K lOOK ° 100 200 500 1K 2K 5K 10K
FREQUENCY ,Hz) LOAD RESISTANCE (0)
Fig. 3 Fig. 4

c8 SAMS~NG SEMICONDUCTOR 455

MC3303IMC3403 LINEAR INTEGRATED CIRCUIT

QUAD OPERATIONAL AMPLIFIER

14 DIP
The MC3303 series is a monolithic Quad operational amplifier
consisting of four independent amplifiers. The device has high
gain, intemally frequency, compensated operational amplifiers
designed to operate from a single power supply or dual power
supplies over a wide range of voltages. The common made input
range includes the negative supply, thereby eliminating the
necessity for external biasing components in many applications.

FEATURES 1450P

• Output voltage can swing to GND or negative supply

• Wide power supply range;
Single supply of 3.0V to 36V
Dual supply of % 1.SV to % 18V
• Electrical characteristics similar to the popular LM741
• CLASS AS output stage for minimal crossover distortion
• Short circuit protected output.

BLOCK DIAGRAM· ORDERING INFORMATION

Device' Package Operating Temperature
MC3303N 14 DIP -40-+85·C
MC3403N 14 DIP
O-+70·C
MC3403D 14 SOP

SCHEMATHIC DIAGRAM
OUTPUT

r---------~--------~--~~----~--~~----~--ov~

NON·
INVERTING 0--+----------+-+----,
INPUT "

INVERTING
INPUT

VEE or
~~~~--~~+-~~_+~--_+--_ _~~_ _~~~----~~_ _~~GND

c8 SAMSUNG SEMICONDUCTOR 456

MC3303IMC3403 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Supply Voltage Vs :1:18 or 36 V

Differential Input Voltage VIO :1:36 V
Input Voltage Vi :1:18 V
Output Short Circuit Duration Continuous
Power DisSipation Po 670 mW
Operating Temperature MC3303 . Top. -40-+85 ·C
MC3403 0-+70 ·C
Storage Temperature T.lg -65-+150 ·C

ELECTRICAL CHARACTERISTICS

II
(Vee = + 15\1, VEE = -15V for MC3403, Vee = + 14V, VEE = GND for MC3303, Ta=25·C, unless otherwise specified)

MC3303 MC3403
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max

2.0 8.0 2.0 10

Input Offset Voltage VIO mV
ITamin:sT.:sT.max 10 12
30 75 30 50
Input Offset Current 110 nA
ITamin:S T.:s Tamax 250 200
0.2 0.5 0.2 0.5
Input Bias Current liB ,.A
ITam.. :sT.:sTamax 1.0 0.8

Large Signal Voltage Vo= :I: 10V 20 200 20 200

Av VlmV
Gain RL =2KO ITamin:sT.:sTamax 15 15
Input Impedance Ri 0.3 1 0.3 1.0 MO
RL =10KO 12 12.5 :1:12 :1:13.5
Output Voltage Swing VOUT RL =2KO 10 12 :1:10 :1:13 V
RL =2KO Tamin:sT.:sT.max :1:10 :1:10
Input Common Mode 12V- 12.5V- 13V- 13.5V-
VieR V
Voltage Range VEE VEE VEE VEE
Common Mode Rejection
Ratio .
CMRR Rs:sl0KO 70 90 70 90 dB

Power Supply Gurrent Is Vo=O, RL=OO 2.8 7.0 2.8 7.0 mA

Output Short Circuit
los Each amplifier :1:10 :1:30 :1:45 :1:10 :1:20 :1:45 mA
Current
Positive ·Supply
PSRR+ 30 150 30 150 ,..VIV
Rejection Ratio
Negative Supply
PSRR- 30 150 ,..VIV
Rejection Ratio
Average Temperature
Coefficient of Input t-liJt-T 50 50 pAl"C
Offset Current

c8 SAMSUNG SEMICONDUCTOR 457

MC3303IMC3403 LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS (Continued) .

IYcc= + 15V, Vee = -15V for MC3403, Vee = +14V, Vee=GND for MC3303, unless otherwise specified)

MC3303 MC3403
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max

Input Offset Voltage Drift /:; Vi.}/:; T 10 10 /LV/'C

Power Bandwidth GBW Av=1, RL=2KO, Vo=20V!>p, THD=5% 9.0 9.0 KHz
Small SIgnal Bandwidth BW Av = 1, RL = 10KIl, Vo = 50mV 1.0 1.0 MHz
Slew Rate SR Av=1, VIN= -10V to +10V 0.6 0.6 VI/Ls
Rise Time . tr Av;::1, RL=10KIl, Vo=50mV 0.35 0.35 /Ls
Fall Time tf Av =1, RL=10KIl, Vo=50mV 0.35 0.35 /L s
Over Shoot OS Av = 1, RL = 10KIl, Vo = 50mV 20 20 %
Phase Margin !lim Av = 1, RL = 2KIl, CL = 200pF 60 60 Degrees
Crossover Distortion CD VIN =30mVp-p, Vo=2.0Vp-p, f=10KHz 1.0 1.0 %

• Tamin<Ta<T.....,.
MC3303: Tamln= -40'C, Tamax = +85'C
MC3403: Tamin=O'C, T.max = +70'C

ELECTRICAL CHARACTERISTICS
(Vee=5.0V, Vee=GND, Ta=;!5°C unless otherwise specified)

MC3303 MC3403
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max

Input Offset Voltage VIO 10 2.0 10 mV

Input Offset Current 110 75 30 50 nA
Input Bias Current 118 500 200 500 nA
Large Signal Open
Av' RL=2.0KIl 10 200 10 200 V/mV
Loop Voltage Gain
Power Supply
PSRR 150 150. /LVN
Rejection Ratio
RL = 10K, Vee = 5.0V 3.3 3.5 3.3 3.5
Output Voltage Range Voor V
RL = 10K, 5.0V SVeeS30V Vcc·2.O Vee·f.7 Vce·2.O Vcc'1.7
Supply Current Icc 2.5 7.0 2.5 7.0 mA
Channel Separation CSI f = 1KHz to 20KHz 120 120 dB

c8 S~MSUNG SEMICONDUCToR 458

MC3303IMC3403 LINEAR INTEGRATED ·CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS

FIg. 1. Large Signal Open Loop Voltage Gain
V. Fraquencv Fig. 2. Wave Response
120

~~~~~~v I!
~.
1:1 A,,=100

.... IiI I
I

!j i .~
_.
I"-
- - -"
I

I I I ,l.
N-;J~. ii
I

f
~
II ,Ii'

-20
1.0
-\1
10 100
FREQUENCY-Hz
11J
Fig. 3. Output Voltage V. Frequency
10k 10k
IIII lQOk 1.0M

Fig. 4. Output Voltage V. Supply Voltage

I
30
I IIIII TUJ.b! i
25
itt-' - --+ +-U~
vs = ± 15V

III]
RL =10 kll I
:
ii
>
t 20

J.
.\ ,Vttl
.'iil- if
! , II
j f[
j
~
III: -" rT .
" 15
~
~
\
10

~ ~!
o 5.0
-~! ~-- •.
-t't '+- ~!I
'

I-

-5.0
I Ilr-
1.0k 10k lOOk 1.0M U M M ro U M ffi ffi 20
V+ AND v-
FREQUENCY":'Hz POWER SUPPLY VOLTAOES-V

FIg_ ~. Input Bias Voltage V. Temperature Fig. 6. Input Blae Current V. Supply Voltage

.. _--
- - - - "1-.--\--+--
.. 300 - - -
1 -- -- - - I - -
._--
.- - - - - - . - . - - - ':lI 170 ....
-t
- - j -_-.l-_...,....~I
I --- c-- ~ ---- i
B ~~~~~~~~~--~-.~--~ B
1--1-- -,I__~--+r-..
--,1~~~~.4-~
o~
..~S
iz f----t--t--+-- ~- 1--1-- -- . -- -- 160
- 100f-+---+-~--1----· --+-- -- --- -- ~
f---4---+~f--+-+-+---l--.-- --

OL-~-L~L-~-L~ __L-~-L~ 160L-~-L~ __~-L~__L-~-L~

-75 -55 -35 -15 5.0 25 45 65 85 105 125 o u U M M ro U M ffi ffi 20
. TEMPERATURE-oC' V+ ANDV-
POWER BUPPLY VOLTAGES-V

.c8 SAMSUNG S~MICONDUcrOR 459

MC3303IMC3403. LINEAR INTEGRATED CIRCUIT

TYPICAL APPLICATIONS
Fig. 7. Multiple feedback bandpass filter Fig. 8. Weln bridge oscillator
5OkO
r---""'''''''--~r---o Your

R3

Yin 0 ... I
10
ft'f
RI
C
;'
R2
C2

10 = center frequency R I
10= 2 RC 10rlo=1 kHz
BW = Bandwidth .. R=16 kll
R In kO C=O.OI pF
C In pF
Fig. 9. Comparator with hysterasis
a = BW<IO
10
R2 HYSTERESIS
CI=C2=~
RI VOHt:Qt
RI=R2=11.
R8=9Q2_tJ Use scaling factors in these expressions. VREF O-~Mr--"""'-I
If source Impedance is high or varies, Iilter may I1e preceded with voltage V Your I
VIN 0------1 our I
follower buffer to stabilize filter parameters.
VOL
Design example: VINL I VINH
I
a
given: = 5, 10 = I kHz RI
VINL = RI + R2 (VOL - VREF) + VREF VREF
let RI=R2=IOkO
then R3 = 9(5)2 -10 RI
VINH = RI + R2 (VOH - VREF) + V~EF
R3=215 kO
5 RI
C="3=1.6 nF H =RI +R2(VOH- VOU

Fig. 10. High Impedance dlfferantial amplifier Fig. 11. AC Coupled Inverting amplifier
R RI
lOOkO

VI

VOUT

RI
bRI
~w )~w
/\
\T/\
1
2Vp-p

T
Vour=C (I +a+b) (V2-VI)
V2
R Av = 10 (as shown)

c8 SAMSUNG SEMICONDUCTOR 460

MC3303/MC3403 LINEAR INTEGRATED CIRCUIT

Fig. 12. Ground referencing a differential input signal Fig. 13. Voltage reference
V+

>-.--oVOUT R2
10kO

>-~-OVOUT

+VCM~-~~~--~~r---l Rl
I R3 10kO R, v+
I lMO VOUT= R,+R2 (=Tasshown)
I
I
VOUT= ivcc
Fig. 14. AC Coupled non·invertlng amplifier Fig. 15. Pulse generator
l00kO lMO

R2

Re
6.2kll
I
R3
l00kll R5
R5 100kO
l00kO
o f\ f\ 2 VPi>
V 'Wlde control voltage range:
R2
Av=I+ T1

AV = 11 (as shown)
T OVoc~Vc~2 (V + -1.5Voc)

Fig. 16. BI·Quad filter R

R
C l00kll

C
Cl R2
VIN o-,...Jl--1r--~~-4--f l00kll
BANDPASS
OUTPUT

VREF
R3

R2
Cl
>--~-II----o NOTCH OUTPUT
=
Example: fo lOO1l Hz
BW=I00Hz
where,
Tep=1
TN=1
Tep= Cenler frequency gain
R=I60 kIl
TN = Bandpass notch gain
Rl=I.6MIl
1
fo= 2rllC R2=~
. Tep
R2=1.6 Mil
R3=1.6 Mil
Rl=QR R3=TNR2 C= 0.001 ~F
Cl=IOC

c8 SAMSUNG SEMICONDUCTOR 461

MC3303IMC3403 LINEAR INTEGRATED CIRCUIT

Fig. 17. Voltage controlled oscillator

OUTPUT 1

/'vA..
OUTPUT 2

Fig. 18. Function generator

TRIANGLE 'WAVE
OUTPUT
~----'''N\r---..-o SQUARE WAVE
OUTPUT

RI
1- R1+R2 'I R3-~
- 4CRIR1 I - R2+R1

c8 SAMSUNG SEMICONDUCTOR 462

 MC4558C/AC/I LINEAR INTEGRATED CIRCUIT

DUAL OPERATIONAL AMPLIFIER a DIP

The MC455S series is a monolithic integrated circuit designed
for dual operational amplifier.

FEATURES
a SOP
• No frequency compensation required.
• No latch-up.
• Large common mode and differential voltage range.
• Parameter tracking over temperature range.
• Gain and phase match between amplifiers.
• Internally frequency compensated. 9 SIP
• Low noise Input transistors.

BLOCK DIAGRAM
II

<.)
<.) ;::. I + ttl + I '"
I-
<.)
<.)
> ::> > ::> >
0 0
~ ~ '"~ '"
~

ORDERING INFORMATION
Device Package Operating Temperature
MC455SIN S DIP
-40- +S5·C
MC4558ID S SOP
MC4558ACN S DIP
MC455SACD SSOP
MC455SCN S DIP 0- + 70·C
MC455SCD SSOP
MC4558S 9 SIP

c8 SAMSUNG SEMICONDUCTOR 463

MC4558C/AC/I LINEAR INTEGRATED CIRCUIT

SCHEMATIC DIAGRAM (One Section Only)

v~o-----~----~~--------~----~----~-,

INPUT
+ 0--+------+----'

'---+---1--+-0 OUT

ABSOLUTE MAXIMUM RATINGS.

Characteristic Symbol Value Unit

±22 V
Power Supply Voltage MC4558ACI MC4558C Vs
MC45581 ±18 V
Differential Input Voltage vlO %30 V
Input Voltage VI ±15 V
Power Dissipation Po ·400 mW
Operating Temperature Range MC45581 -40-+85 ·C
Topr ·C
MC4558AC/MC4558C 0-70
Storage Temperature Range Tstg -65-+150 ·C

c8 SAMSUNG SEMICONDUcroR 464

MC4558C/AC/I LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS
(Vee = 15V, VEE = - 15V, Ta= 25·C, unless otherwise speCified)

MC4558I/MC4558AC MC4558C
Characteristic Symbol Test conditions Unit
Min Typ Max Min Typ Max

1 5 2 6
Input Offset Voltage V,O Rss10KO mV
TaminST.STam .. 1 6 7.5
20 200 20 200
Input Offset Current 1,0 T.=Tam.. 70 200 300 nA
T.=Tamln 85 500 300
80 500 80 500
Input Bias Current liB Ta=Tamax 30 500 800 nA

Large Signal
Voltage Gain
Av Vo = ± 10V RL~2.0KO
T.=Tamln

TamlnSTaSTam...
50
25
±12
300
200

±13
1500
20
15
±12 ±13
200
800

V/mV I
Common Mode Input
V,CR , V
Voltage Range TaminST.STamax ±12 ±13
Common Mode 70 90 70 90
CMRR Rss10KO dB
Rejection Ratio TaminST.STamax 70 90
Supply Voltage 76 90 76 90
PSRR' RsS10KO dB
Rejection Ratio TaminSTaSTam.. 76 90 76 90
RL~10KO ±12 ±14 ±12 ±14
Output Voltage Swing Vour TaminST..STamax V
RL~2KO ±10 ±13 ±10 ±13
2.3 5.0 2.3 5.6
Supply Current
Is Ta=Tam ... 4.5 5.0 mA
(Both Amplifiers)
T.=Tamln 6.0 6.7
70 150 70 170
Power Consumption
Pc T.=Tamax 135 150 mV
(Both Amplifiers)
T.=Tamln 180 200
V, = 10V, RL~2KO
Slew Rate SR 1.0 .1.0 V/p.s
CLS100pF
V, = 20m V, RL~2KO,
Rise Time tr 0.3 0.3 p's
CLS100pF
Vi =2OmV, RL~2KO,
Overshoot OS 15 15 %
CLs100pF
• MC45581: T amin = - 40·C, Tamax = + 85·C
MC4558AC/MC4558C: Tamin = O·C, Tamax = + 70·C

c8 SAMSUNG SEMICONDUCTOR 465

MC4558C/AC/I LINEAR INTEGRATED CIRCUIT

TYPICAL PERFO.RMANCE CHARACTERISTICS

BURST NOISE Vs SOURCE RESISTANCE RMS NOISE Vs SOURCE RESISTANCE
1000

1,OHz

~
o
10 100 l.oK 10K 1001< _
Fig. 1 SOURCE REBI8TAHCI! (II) Fig.2 SOURCE_ (II)

OUTPUT NOISE V. SOURCE RESISTANCE SPECI"RAL NOISE DENSITY

10 F 140
1=
1=
f=f- 120 ......... .l~l..
.i lD
.
y. ... \
I \
I
Ioi
u
1
V
40

,
G.01 o
10 100 . l.oK 10K 100K l.oM 10 100 l.oK 10K
FIg.3 SOUIICE-.va (II) FIg.4FMGUINCYIHII

OPEN LOOP FREQUENCY RESPONSE PHASE MARGIN V. FREQUENCY

180 ._-
+1«)

,
180
'" \
fOO
1.
1+
100

80
.-"""'-
l\.
,
\
~+80 I\.. ~
. l+4C) I\.. ~
+20
'1\. --
1\ u ItTyliAIN
o
"\
40

20
i .\
I I I ,
-20
I"' o lD
lD 10 100 l.OK 10K 100K 1.I1M _ 10 100 1.OK 10K 100K 1.oM _
1'lg.5FMGUINCYIHII Flg.S - I I 1 I I

c8 SAMSUNG SEMICONDUCTOR 466

MC4558C/AC/I LINEAR INTEGRATED CIRCUIT

POSITIVE OUTPUT VOLTAGE SWING NEGATIVE OUTPUT VOLTAGE SWING

Vs LOAD RESISTANCE Vs LOAD RESISTANCE
15 15

III~
±15V SUPPLIES I' ± 15V SUPPLIES
13
/' 13

'±12V ±12V
11
V ! V
W 9.0 Ii
±'iN ~ ±9V
~ g 7.0
V
II ±6V "o~ 5.0
±6V
--

J.~
~
I

-
3.0 3_0

" /I
±:w ±:w

~ I II

I
1.0 1.0
100 500 1.oK 2.oK 10K 20K • 5OK100K 100 500 1DK 2.oK 10K 20K SOK100K

Fig. 7 LOAD RESISTANCE (II) Fig. 8 LOAD RESISTANCE (II)

POWER BANDWIDTH
(LARGE SIGNAL SWING VERSUS FREQUENCY)
28

24
TRANSIENT RESPONSE TEST CIRCUIT

1
;e
20

i 18
>-o-+---~ __ ThSoo~
~ (Output)

i 12
RL CL

§
f. e.o
\

10 100 loOK 10K lOOK 100M

Fig. 9 FREQUENCY(Hz} Fig. 10

c8 SA.MSUNG SEMICONDUCTOR 467

KA319 LINEAR INTERGRATED CIRCUIT

14 DIP
DUAL HIGH SPEED VOLTAGE COMPABATOR
The KA319 is a dual high speed voltage comparator desigfled to
operate from a single + SV supply up to ± 1SV dual supplies.
Open collector of the output stage makes the KA319 compatible with
RTl, DTl and TTL as well as capable of driving lamps and relays at
currents up to 2SmA. Typical response time of 80ns with ± 1SV power
supplies makes the KA319 ideal for application in fast AID converts, level
shifters, oscillaters, and multivibrators.
14 SOP
FEATURES
• Operates form a single 5V supply
• Typically 80ns response time at ± 15V
• Open collector outputs: up to + 35V
• High output drive current: 25mA
• Inputs and outputs can be isolated from system ground
• Minimum fan·out of 2 (each side)
• Two' independent compators

BLOCK DIAGRAM ORDERING INFORMATION

Device Package Operating Temperature
KA319N 14 DIP
0- + 70·e
KA319D 14 SOP

SCHEMATIC DIAGRAM
'-~~~--~----~--~-----4~--~-4~----------~----ovcc

1-+---+--~-oOUTPUT

c8 SAMSUNG SEMICONDUCTOR 468

KA319 LINEAR INTERGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Supply Voltage Vs 36 V
Output to Negative Supply Voltage Vo-VEE 36 V
Ground to Negative Supply Voltage GND-VEE 25 V
Ground to Positive Supply Voltage GND-Vcc 18 V
Differential Input Voltage V,D ±5 V
Input Voltage V, ±15 V
Output Short Circuit Duration 10 sec
Power Dissipation PD 500 mW
Operating Temperature Range Topr 0-+70 ·C
Storage Temperature Range Tstg -65-+150 ·C

ELECTRICAL CHARACTERISTICS
(Vcc= +15V, VEE = -15V, Ta=25·C, unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

II
2.0 8.0
Input Offset Voltage (Note 1) V,O Rss5K mV
TammSTaSTamax 10
80 200
Input Offset Current (Note 1) 1'0 nA
TamlnSTaS Tamax 300
250 1000
Input Bias Current liB nA
TamlnSTaS Tamax 1200
Voltage G'ain Av 8 40 V/mV
Response Time (Note 2) t, Vs= ±15V 80 ns
V,nS - 10mV, lout = 25mA 0.75 1.5 V
Saturation Voltage VOL Vcc~4.5V, VEE = 0, V,NS -10mV,
0.3 0.4 V
ISINKs3.2mA Tamin.:STa:sTamax
Output Leakage Current 10L V,"~10mV, Vout = 35V 0.2 2 p.A
Vs= ± 15V ±13
Input Voltage Range V'CR TaminSTa:s Tamax V
Vcc =5V, VEE=OV 1 3
Differential Input Voltage VID ±5 V
Positive Supply Current Iccl Vcc =5V, VEE=OV 4.3 mA
Positive Supply Current Icc2 Vs=±15V 8 12.5 mA
Negative Supply Current lEE Vs= ± 15V 3 5 mA

Note: 1. The offset voltage and offset currents given are the maximum values required to drive the output within
a volt of either supply with a 1mA load. Thus, these parameters define an error band arid take into account
the worst case effects of voltage gain and input impeance.
2. The response time specified is for a 100mV input step with 5mV overdrive.
3. TamlnSTaSTamax
KA319: Tamm=O·C, Tamax =70·C

c8 SAMSUNG SEMICONDUCTOR 469

KA319 LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS

INPUT CURRENTS va TEMPERATURE SUPPLY CURRENTS va TEMPERATURE
300 12

vsJ :15V

250
r- I-- '. 10

BIAS
C· 1000- POSITIVE SUPPLY, Vs = ± 15V
.s.... 8.0

zw
a:
a: 6.0
is
...
~ POSITIVE SUPPLY, Voc=5.QV, V£E=O

..." 4.0

100

50
-
o 10 20 30
OFFSET

40
TEMPERATURE (0C)
50 60 10
2.0

10
NEGATIVE SUPPLY Y. Vs= ± 15V

20 30
TEMPEAATUIIE (0C)
40 50 60 10

Fig. 1 Flg.Z

TRANSFER FUNCTION RESPONSE TIME FOR VARIOUS

INPUT OVERDRIVES
40 8.0 :E 6.0
Va:::. ±15V LJ6V w
~:~::, -
r-~1,.=1.4KD 1.0 "~ 5.0
35
Ta=25 D C
/ 0
> 4.0
1\ " r-... V+ =5.OV
Ta=25°C

IE
30
. I I
6.0 :E .5
.... 3.0 \ \ \ I
%
!2 25
/ V+ =5.0V
5.0 ~ "0 2.0
\ \ \.
/ /'
%
w
~ 20mV \5.OmV \ 2.OmV
~ 20 4.0 ~ 1.0
\ \.
'/
'0
0 >
>. ....
."
....
....
15

'/
3.0 ~

i!
"
0 10 2.0

5.0
I 1.0

o
-1.0
-- -- -- --lJ.
-0.6 -0.2 0.2 0.8 1.0
o
50 100 150 200 250 300 350
DIFFERENTIAL INPUT VOLTAGE (mVI TIME (na)
Fig. 3 Fig. 4

RESPONSE TIME FOR VARIOUS INPUT CHARACTERISTICS va DIFFERENTIAL

r,
INPUT OVERDRIVES INPUT VOLTAGE

---
:E 6.0 400
w Va= ±15V

~"
5.0 I-To=ZS·C
V I. .
!i! 4.0 V'S= ±15V 300

.5
.... 3.0
20mV I / j2.0mV
RI.=5000
V++=5.0V
i
i!
2.0
/ f·o~v T.=25·C
!Zw ZOO
1/ a:

-
a:
1.0
"u
It-JI ~ 100
!>
1.'00
w
.5
i!!

g"j! 50

MAXIMUM DIFF~rNT'iL
~ iNPUT VOLTAGE
i!! -100
50 100 150 200 250 300 350 :',0 -8.0 -2.0 2.0 6.0 10
TIME(na) DIFFERENTIAL INPUT VOLTAGE (V)
Fig. 5 Fig. 8

c8 SAMSUNG SEMICONDUCTOR 470

KA319 LINEAR INTEGRATED CIRCUIT

RESPONSE TIME FOR VARIOUS RESPONSE TIME FOR VARIOUS

INPUT OVERDRIVES INPUT OVERDRIVES

.."£ 6.0

~:~~v_
..
£ 6.0

~
5.0 5.0
~ \' \ V+=5.OV fl Z .I.
!i! 4.0
\\ \
Ta=25"C -
..g 4.0
20mV
/ 12.0mV
Vs =5.OV
RL,='5000

~ ~
3.0 3.0 V+ =5.OV

0
2.0
\ \ 0
2.0
1/1 Ta=25"C

1.0
20mV \ 5.0mV\ 2.0mV
1.0 I '/S.Omv
I\, \.. II

.."~
~-50
!i!
i- 1OO
!!

I
50 100 150 200 250 300 350 50 100 150 200 250 300 350
TIME(..) TIME(ns)
Fig. 7 fig. I
OUTPUT SATURATION VOLTAGE SUPPLY CURRENT va SUPPLY VOLTAGE
va OUTPUT VOLTAGE
25 12

T~=25"C Ta=~5"C
20
/ 10
,/
:c ./
i.. / S B.O

Ii
,/' ~ITIVE SUPPlY
15

/
iii ::!a:
a:
a: ,.u 6.0
::>
u
~
V
~ ./
10

V ,.II:

- --
'.0
0

5.0
J
til

2.0
V ~ NEGATIVE SUPPLY

/V.=±15V i""'"
'~IUT OVERDriVE = 5.0mr
./
0.2 0.4 0.6 0.6 1.0 5.0 10 15
OUTPUT VOLTAGE (V) SUPPLY VOLTAGE (+ V)
fig. 9 Fig. 10

OUTPUT LIMITING CHARACTERISTICS

va OUTPUT VOLTAGE
120 r----,---. .---,.---,--r----".2

100 1--H\---1--+--t---t---j 1.0

i 80 1--+-t-~~--t--+-~I---iOBz
!:
Ii
::!a:
::>
u
so h/-t---t--~t--~FOo.:=--t-----l
i
~
,.I: 0.6

Ii! '"
2~
;;
40 H--j----:;..-r--t---t---t---j 0.4
~
0
i
20 I+-F-t----t---t---t---f----j 0.2

L-_~ __ ~_~ __ ~ __ ~_-JO

5.0 10 15
OUTPUT. VOLTAGE (V)
fig. 11

c8 SAMSUNG SEMICONDUCTOR 471

KA361 LINEAR INTEGRATED CIRCUIT

14 DIP
HIGH SPEED VOLTAGE COMPARATOR
The KA361 is a very high speed differential input; complementary TIL
output voltage comparator. Applications involve high speed AJD converts
and zero·crossing detectors in disc file systems. .

FEATURES
• Complementary TIL outputs 1480P
• Independent strobes
• High speed: 20ns (max)
• Operates from OP amp supplies: :!: 15V
• Low input offset voltage
• Versatile supply voltage range

BLOCK DIAGRAM SCHEMATIC DIAGRAM

. STROBE1
,---~+;::=:;=;==+=:8vcc

OUTPun

~----1f-OGND

ORDERING INFORMATION
Device Package Operating Temperature
OUTPUT2
KA361N 14 DIP
O-+70·C
KA361D 14 SOP

OPERATING CONDITIONS
Supply Voltage Min Typ Max Unit
V+ 5 15 V v-O-~--+~-~-----~~

V- -6 -15 V
Vee 4.75 5.25 V

c8 SAMSUNG SEMICONDUCTOR 472

KA361 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Positive Supply Voltage V+ +16 V

Negative Supply Voltage V- -16 V
Gate Supply Voltage Vee +7 V
Output Voltage Your +7 V
Differential Input VoltagEl V'D ±5 V
Input Voltage Range V, ±6 V
Power Dissipation PD 600 mW
Operating Temperature Range Topr 0-+70 ·C
Storage Temperature Range Tstg -65-+150 ·C

ELECTRICAL CHARACTERISTICS
(V+ = +10V, Vee = +5V,V- = -10V, Ta=25·C, unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

II
Input Offset Voltage V'O 0·C::s;Ta::S;70·C 1 5 mV
Input Bias Current I,s 10 30 p.A
Input Offset Current 1'0 2 5 p.A
Voltage Gain Av 3 Vim V
Input Resistance R, f=1KHz 20 KO
Logical "1" Output Voltage VOH Vee = 4. 75V, I.ourco = - 5mA 2.4 3.3 V
Logical "0" Output Voltage VOL Vcc = 4. 75V, I.'nk = 6.4mA 0.4 V
Strobe Input "1" Current "- l.tH Vcc=5.25V, V.trobo =2.4V 200 p.A
Strobe Input "0" Current Istl Vee = 5.25V, V.trobe = 0.4V -1.6 mA
Strobe Input "0" Voltage . V.tl Vee = 4.75V 0.8 V
Strobe Input "1" Voltage V.tH Vee = 4.75V 2 V
Output Short Circuit Current los Vee=5.25V, Vour=OV, V+ =10V, V- = -10V 18 -55 mA
Supply Current 1+ Vee = 5.25V, Tam,n::s;T.::s;Tamax 5 mA
Supply Current 1- Vee = 5.25V, Tamm::s;Ta::s;Tamax 10 mA
Supply Current Icc Vee = 5.25V, Tamm::s;T.::s;Tamax 20 mA
Propagation Delay Time tpd (0) V'N = 50mV overdrive 14 20 ns
Propagation Delay Time tpd (1) V'N = 50mV overdrive 14 20 ns
Delay Between Output A and B td V'N = 50mV overdrive 2 5 ns
Strobe Delay Time (tpd (0)) td V'N = 50mV overdrive 8 ns
Strobe Delay Time (tpd (1)) td V'N = 50mV overdrive 8 ns

c8 SAMSUNG SEMICONDUCTOR 473

KA710C LINEAR INTERGRATED CIRCUIT

HIGH SPEED VOLTAGE COMPARATOR

14 DIP
The KA710C is a h'igh speed voltage comparator intended for· use as
an accurate, low-level digital level sensor or as a replacement for
operational amplifiers in comparator applications where speed is of
prime importance.
The output of the comparator is compatible with all intergrated logic
forms.
The K,l\710C is useful as pulse height disciminators, a variable threshold
schmitt trigger, voltage comparators in high-speed AID converters, a
memory sense amplifier or a high noise immunity line receiver.
14 SOP

FEATURES
• Low offset voltage: SmV
• High gain: 1000 (Min)
• High speed: 40ns Typ 41# 1

BLOCK DIAGRAM ORDERING INFORMATION

Device Package Operating Temperature
KA710CN 14 DIP
0- + 70·C·
KA710CD 14 SOP

SCHEMATIC DIAGRAM
r-------------------------------~------OVcc

UK 2.BK

500

3.9K

INVERTING INPUT C>-----k__--....__~..l

NON·INVERTING INPUT C>----------+--------l ~------r--+------oOUTPUT

1.7K

GND

c8 SAM'SUNG SEMICONDU~OR 474

KA710C LINEAR INTERGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Positive Supply Voltage Vee +14 V

Negative Supply Voltage VEE -7 V
Peak Output Current Ipeak 10 mA
Output Short Circuit Duration 10 Sec.
Differential Input Voltage VIO ±5 V
Input Voltage VI ±7 V
Power Dissipation Po 200 mW
Operating Temperature Range Topr 0-+70 ·C
Storage Temperature Range Tslg -65-+150 ·C

I
ELECTRICAL CHARACTERISTICS
(Vee= +12V, VEE = -6V, Ta=25·C, unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

Rs;:s2000 1.6 5.0

Input Offset Voltage VIO mV
I 0;:sTa;:s70·C 6.5
Vour=1.4V 1.8 5.0
Input Offset Current 110 p.A
I 0;:sTa;:s70·C 7.5
16 25
Input Bais Current he p.A
I Ta= O·C 25 40
Large Signal Voltage Gain Av 1000 1500 VN
Input Voltage Range VieR Vee= -7.0V ±5.0 V
Common Mode· Rejection Ratio CMRR Rs;:s2000 70 98 dB
Differential Input Voltage Range VIOR ±5.0 V
Output Voltage (High) VOH VIN 0!::5mV,0<lour <5mA 2.5 3.2 4.0 V
Output Voltage (Low) VOL VIN 0!::5mV -1.0 -0.5 0 V
Output Sink Current ISlnk VIN 0!::10mV, Vo=OV 0.5 mA
Positive Supply Current lee Vo=OV, VIN0!::10mV 5.2 9.0 mA
Negative Supply Current lee Vo=OV, VIN ;:s10mV 4.6 7.0 mA
Power Consumption Po Vo=OV, VIN 0!::10mV 150 mW
Response Time t, (NOTE1) 40 ns

Note: 1. The response time specified is for a 100mV input step with 10mV overdrive.

c8 SAMSUNG SEMICONDUCToR 475

LM211/LM311 LINEAR INTEGRATED CIRCUIT

a'DIP

VOLTAGE COMPARATOR
The LM211 series is a monolithic, low input current voltage
comparator.

FEATURE
• Low Input bias current: MAX 2S0nA. a SOP
• Low input offset current:' MAX SOnA.
• Differential Input Voltage: ±30V.
• Power supply voltage: single S.OV supply to ± 1SV.
• Offset voltage null capability.
• Strobe capability.

BLOCK DIAGRAM ORDERING INFORMATION

Device Package Operating Temperature

GND 1 LM211N a DIP

-25-+a5·C
LM211D a SOP
7 OUTPUT
LM311N a DIP
O-+70·C
6 BALANCE/STROBE LM311D a SOP

5 BALANCE

SCHEMATIC DIAGRAM,
BALANCE
BALANCEI 6
5
STORBE O--+---+-----~ 8
r--+-r---r----f--+---,.--r----r-~------_r--oVcc

R3

+2

INPUTS 7
l---t--'-....-o OUTPUT

-3o---+---{

1
'---t-------.4--oGND

VEE

c8 SAMSUNG SEMICONDUCTOR· 476

LM211/LM311 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Total Supply Voltage Vs 36 V

Output to Negative Supply Voltage LM211 YO-VEE 50 V
LM311 40 V
Ground to Negative Supply Voltage Vee 30 V
Differential Input Voltage VIO ±30 V
Input Voltage Y'N ±15 V
Output Short Circuit Duration 10 sec
Voltage at Strobe Pin Vee to Vee-5.0 V
Power Dissipation Po 500 mW
Operating Temperature LM211 Top, -25-+85 ·C
LM311 0-+70 ·C
Storage Temperature T" 9 -65-+150 ·C

ELECTRICAL CHARACTERISTICS

Characteristic Sym'bol
(Vee = 15V, Vee = -15V, Ta= 25·C, unless otherwise specified)

Test Conditions
Min
LM211
Typ Max Min
LM311
Typ Max
Unit
II
Input Offset Voltage 0.7 3.0 2.0 7.5
V,O Rs<50KD mV
(NOTE1) - ITamlnSTaS Tamax 4.0 10
Input Offset Current 4.0 10 6 50
1'0 nA
(NOTE1) ITam"ln<Ta<Tamax 20 70
60 100 100 250
Input Bias Current lIB nA
ITaminSTaSTamax 150 300
Voltage' Gain Av 40 200 40 200 V/mV
Response Time (NOTE2) t, 200 200 nS
VidS -5.0mV, lo=50mA 0.75 1.5
Vid= -10.0mV, lo=50mA 0.75 1.5
Vee~4.5V, Vee=OV,
Saturation Voltage Vsat V
l.ink s8.0mA
V~s -6.0mV TammSTaST..", 0.23 0.4
V,.s -10.0mV. 0.23 0.4
Strove "ON" Current Is' 3 3 rnA
V'd~5.0mV Vo=35V 0.2 10
nA
Output Leakage Current I'eak V'd~10mV Vo=35V 0.2 50
Vid~5.0mV, Vo=35V,
0.1 0.5 p.A
Tamln<Ta<Tamax
-14.710 -14.710
Input Voltage Range VieR Tamin STaSTamax -14.5 13.0 -14.5 13.0 V
13.8 13.8
Positive Supply Current lee 2.4 6.0 2.4 7.5 rnA
Negative Supply Current lee -1.3 -5.0 -1.3 -5.0 rnA
Strobe Current Istrobe 3 3. rnA
NOTE 1 TaminSTaSTamax
LM211: Tamln= -25·C, Tamax= +85·C LM311: Tamin=O·C, Tamax = +70·C
NOTE 2 The response time specified is for a 100mV input step with 5mV over drive

C8 SAMSUNG SEMICONDUCTOR 477

LM211/LM311 -LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS

INPUT alAS CURRENT V. TEMPERATURE INPUT OFFSET CURRENT V. TEMPERATURE

-
30
1
V._ :t15V
Vs-±l&V

RAISED· r - t--....

-""
~
I"' ........
-
RAISED
0

NOR.....L
100
--1""-0,. N~AL """"
0 0
-156 -35 -15 5 25 45 65 65 105,125
0102030 "" 506010 ·Pins S. 8 and 8 are shorted.
-Pine s..,
and 8 ... 1horIed.
TEMPERATUIE I"e)
~1II!('e)
fig. 2
fig. 1
INPUT BIAS CURRENT V. DIFFERENTIAL
OFFSET VOLTAGE V. INPUT RESISTANCE INPUT VOLTAGE
100 225

T•• 25OC 200

Va-±15V
T•• SOC
I I 175
MAXIMUM

I
/ / 1"--
"'"
lYPICAL

50
I'.
I' .UJ.IIL

1
10K 1001<
'-nililii~
,1M 10M
25

0
-16 -12 -8 -4 0 4 8 12 18
INPUT _ANCE (Ill DIFI'ERENTIAL INPUT _TAGE IV)
fig. 3 fig. •
COMMON MODE LIMITS V. TEMPERATURE OUTPUT VOLTAGE V. DIFFERENTIAL
INPUT VOLTAGE .
v+ 60

REFERR£OTO Va_$IN
-0.&t--SUPPLY VOLTAGES '50
r--- T._""" NORMAL OUTPUT
RL_1K11 -

-
V++_4fN

10-
.5
_~MITTER .
FOL1DINER
~
-~

-
A
'\
~ 1\
0
Q.2
'\.
V --156 0 J "-
-35 -15 5 25 45 55 86 105 125 -1.0 _
-116 _ _
. 0 _ I"e)
OS 1.0
_(mY)

""I fig. I

c8 SAMSUNG SEMICONDUCTOR 478

 LM211/LM311 LINEAR INTEGRATED CIRCUIT

SATURATION VOLTAGE V. CURRENT SUPPLY CURRENT V. TEMPERATURE

10

0.7 r-- T•• J..c V' Vs= :l::15V

~
lL:
V ...
... .......
V p(i.imv'ESUPPLY
lL: " " OUTPUT LOW
1/ . I" t'-....~
./
POSITI~
/ NEGATIVE SUPPLY·
OUTPUT HIGH
2 /
2
0.1

0 0

II
10 20 30 40 60 -55 -35 -15 5 25 45 65 65 106 121
OUTPUT CUAIIEIIT (mAl TEMPERATURE ('C)
fig. 7 fig .•
LEAKAGE CURREIiITS V. TEMPERATURE

!==.VS.>16V

,. ~

OUTPUT Voor.4OV
........
,
",..

I - - - - iNPUTVti .tN

10-" I--"""
26 ""
--- 45 55
TEllPEMrURE (.C)
fig. •
65 7S

c8 SAMSUNG SEMICONDUCTOR 479

LM211/LM311 LINEAR INTEGRATED CIRCUIT

TYPICAL APPLICATIONS
Switching Power Amplifier
,-----------~--------------~----------~-------------O~e

R1 R12
01
02
2N6125
620 2N6125
620
OUTPUT----'----4

R13

R4 300K
RS Rs R9 R14
510 39K 15K
39K 510
Rs
INPUT

REFERENCE

R7
Fig.1· 15K

Relay Driver with Strobe Digital Transmission Isolator

V+

Vee

TTL STROBE

Fig. 2 Fig. 3

c8 SAMSUNG SEMICONDUCroR 480

 LM239/A, LM339/A, LM2901, LM3302 LINEAR INTEGRATED CIRCUIT

QUAD DIFFERENTIAL COMPARATOR

14 DIP
The LM239 series consists of four independent voltage comparators
that one designed to operate from single power supply over a wide range
'of voltage.

'FEATURES
• Single or dual supply operation
• Wide range of supply voltages LM239/A, LM339/A: 2 - 36V
(or::t:1-::t:18V)
14 SOP
LM2901 , LM3302: 2 - 28V
(or ::t:1- ::t:14V)
• Low supply current drain SOOpA lYJI.
• Open collector outputs for wired and connectors
• Low input bias current 25nA l\'p.'
• Low input offset currant ::t: SnA Typ.
• Low Input offset voltage ::t: 2mV Typ.
• ,Common mode input Yoltage range includes ground.
• Low output saturation IIOItage
• Output compatible with TTL, DTL and MOS logic
system
I
BLOCK DIAGRAM ORDERING INFORMATION
Device Package Operating Temperature
LM239N
14 DIP
LM239AN
-25-+85°e
LM239D
14 SOP
LM239AD
LM339N
14 DIP
LM339AN
0-70 o e
LM339D
14 SOP
LM339AD
LM2901N 14 DIP
LM2901D 14 SOP -45-+85°e
LM3302N 14 DIP

c8 SAMSUNG SEMICONDUCTOR 481

. LM239/A, LM~/A, LM2901, LM3302 LINEAR INTEGRATED CIRCUIT

SCHEMATIC DIAGRAM
r-_-----'-_ _ _~-----<>vcc
(OR
Vcc+)

NON INVERTING o---~--r r---~OUTPUT

INPUT

INVERTING 0-------+---+------'
INPUT

L-_~_ _ _ _ _ _~~~_--oGNO
(OR
VCC-)

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol· Value Unit

Power Supply Voltage Vs ± 18 or 36 V

Power Supply Voltage Only LM3302 Vs ± 14 or 28 V
Differential Input Voltage VID 36 it
Differential Input Voltage Only LM3302 VID 28 V
Input Voltage V, -0.3 to +36 V
Input Voltage Only LM3302 V, -0.3 to +28 V
Output Short Circuit to GND Continuous
. Power Dissipation
Operating Temperature LM239/LM239A
PD
Topr
570
-25- +85
mW
·C
LM339/LM339A 0-+70 ·C
LM2901/LM3302 -40- +85 ·C
Storage Temperature. Ts1g -65-+150 ·C

c8 SAMSUNG SEMICONDUCTOR 482

LM239/A, LM339/A, LM2901, LM3302 LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS (Vee = 5V, Ta = 25·C, unless otherwise specified)

LM239A1LM339A LM239/LM339
Characteristics Symbol Test Condition Unit
Min T.yp Max. Min Typ Max

VeM=OV to Vcc-1.5V z1 z2 z1 z5
Input Offset Voltage V,O mV
Vo;::1.4V, Rs=O TamlnSTaSTamax ±4.0 ±9.0
±5 z50 z5 z50
Input Offset Current 1'0 nA
Tamln::;Ta::;Tainax Z 150 z 150
25 250 25 250
Input Bias Current Ie nA
Tamln::;TaSTamax 400 400

Input Common Mode 0 Vcc·lo5 0 Vcc·lo5

VieR V

I
Voltage Range TamtgSTaSTamax 0 Vee-2 0 Vee-2
RL=OO , 0.8 2.0 0.8 2.0
Supply Current Icc mA
RL=oo Vee =36V 1.0 2.5
, 1.0 2.5
Voltage Gain AVOL Vee = 15V, RL~15KO (for large SWiAg) 50 200 200 V/mV
Large Signal Response Y'N = TTL Logic Swing
tRES 300 300 ns
Time V",,=1.4V, VRL =5V, RL=5.1KO
Response Time tREs VRL =5V, RL=5.1KO 1.3 1.3 /LS

Output Sink Current V'N-~1V, V,N + =OV, Vos1.5V 6 16 6 16 mA

Sink
'
V'N-~1V, V,N + =OV 250 400 250 400
Output Saturation Voltage Vsa; mV
l"nk=4mA TamlnSTaSTamax 700 700

V,n - =0 V.O = 5V 0.1 0.1 nA

Output Leakage Current Ileak
Y'n = 1V Vo=30V 1.0 1.0 /LA

• TamlnSTaST amax
LM239/LM239A: Tamln= -25·C, Tamax= +85·C
LM339/LM339A: Tamln = O·C, Tamax = + 70·C
LM2901/LM3302: Tamln= -40·C, Tamax= +85·C

c8 SAMSUNG SEMICONDUCTOR 483

LM239/A,LM339/A,LM2901,LM3302 LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS IYcc= 5V, Ta=25°C, unless otherwise specified)

LM2901 LM3302
Characteristics Symbol . Test Condition Unit
Min Typ Max Min Typ Max

V CM = OV to Vcc -1.5V ±2 ±7 ±3 ±20

Input Offset Voltage VIO mV
Vo=1.4V, Rs=O I Tamin:s:Ta.sTamax 9 ±15 ±40
±5 ±50 ±3 ±100
Input Offset Current 110 nA
I Tamin<T.STamax ±50 ±200 ±300
25 250 25 250
Input Bias Current 18 nA
I TamlnST.ST"",ax 200 500 1000

Input Common Mode 0 Vee-1.5 0 Vcc·1.5

VICR V
Voltage Range I TamlnST.STamax 0 Vcc·2 0 Vcc·2
RL=OO 0.8 2.0 0.8 2.0
Supply Current Icc rnA
RL=oo, Vcc =36V, LM3302, Vcc=28V 1.0 2.5
Voltage Gain AVOL Vcc =15V, RL~15KO (for large swing) 25 100 2 30 V/mV
Large Signal Response VIN = TIL Logic Swing
tRES1 300 300 ns
Time V ref =1.4V, VRL =5V, RL=5.1KO
Response Time tRES2 VRL =5V, RL=5.1KO 1.3 1.3 /Ls

Output Sink Current Islnk VIN-~1V, VIN + =OV, VoS1.5V 6 16 6 16 rnA

VIN-~1V, VIN + =OV 250 400 250 400

Output Saturation Voltage V sat mV
ISlnk=4mA I Tamin<T.<Tamax 700 700

Output Leakage Current Ileak

Vln- =0 I Vo=5V 0.1 0.1 nA
Vin= 1V1 Vo=30V LM3302, Vo=28V 1.0 1.0 /LA

* Tamin<Ta<Tamax
LM239/LM239A: Tamin= -25°C, Tamax= +85°C
LM339/LM339A: T amin = O°C, Tamax = + 70°C
LM2901/LM3302: Tamln= -40°C, Tamax= +85°C

c8 SAMSUNG SEMICONDUCTOR 484

LM239/A, LM339A, LM2901, LM3302 LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS

SUPPLY CURRENT V. SUPPLY VOLTAGE INPUT CURRENT Vs SUPPLY VOLTAGE

Ta=olc
0.8

1.,...00-" ~
.--- I
60

~
....- po- Ta= +25·C-
....z

,"" 1.,...00-" ~

-
w
I rr:
rr: 40
Ts=O'C
:>
u Ta-+~
+170- c
~
Ta=

R,=~I
.
!;
;!!
Ta-+70"C-

0.' , "". 20

0.2
o 10 20
SUPPl.Y VOLTAGE (V)

OUTPUT SATURATION VOLTAGE

30 10 20
SUPPLY VOLTAGE

RESPONSE TIME
30

II
IN~T O~ERD~IVE
I I
1+5VI ,~
I • >

5~±-
E < >
OUT OF V 3 !! ~- ~-VIN -
SATURATION
~ +
V 2 r--
/ Ta= + 25°C
1 r--
r.
/" 0

~ 0
/ w
~ -50
l/ ~-.100
0.001
0.01
l/ 0.1 10
~
;!!
0.5 1.5
OUTPUT SINK CURRENT (mA) TIME (,.a)

RESPONSE TIME

! INPlkov~RDR~VE
~
• 100mV /iomv 5mV
3

~
2
I
1 I I
0
IJ ~ ~ ~
V.
+ V""

o 0.5 1 1.5
I
TIME (,<a)

=8 SAMSUNG SEMICONDUCTOR 485

LM239/A, LM339/A, LM2901, LM3302 LINEAR INTEGRATED CIRCUIT

APPLICATION INFORMATION
The LM239 series includes four high gain, wide bandwidth devices which, like most comparators, can easily oscillate
if the output lead is inadvertently allowed to capacitivelycouple to the inputs via stray capacitance. That occurs
during the output voltage transitions, when the compar.ator changes state.
To minimize this problem, PC board layout should be designed to reduce stray input output coupling; reducing the input resis-
tors to less than 10KO reduces the feedback signal levels and finally, adding even a small amount (1 to 10rnV) of positive feed-
back.(hysteresis) causes such a rapid transition that oscillations due to stray feedback are not possible.
It is good design practice to ground all unused pins.
The differential input voltage may be larger than positive supply without damaging the device. Note that voltages more negative
than -O.3V should not be used: an input clamping diode can be used as protection. '
The output,LM3.39 is the uncommitted collector of a NPN transistor with grounded emitter. This allows the device to be used
like any open-collector gate providing the OR-wide facility.
The output sink current capability is approximately 16 mA; if this limit is exceeded, the output transistor will come out of
saturation and the output voltage will rise very rapidly.
Under this limit, the output saturation voltageis limited by the approximatively 600 rsat of the output transistor.

TYPICAL APPLICATIONS (Vee= +'15V)

Basic comparator Non-inverting comparator with Hysteresis

5V 5V '

3K!!
+VREFO----p..
Vo >--t--OVo
+VIN o-~~~IY
10K!!,

Fig. 6 Fig. 7

Inverting comparator with,Hysteresis

3KII
+VIN 0----1'"
>--+--0 Vo
1M!!

c8 SA~SUNG SEMICONDUcroR 486

LM239/A, LM339/A, LM2901, LM3302 LINEAR INTEGRATED CIRCUIT

Driving C/MDS Driving TTL

5V 5V

Fig. 9 Fig. 10

AND gate
15V
DR gate

1!'>V
I
3K!l 3K!l
3x100K!l -=#No~-P......
Ao-_~:":"",, A 0---1;-'--,
B o-_II"Ir--;'-....-l1:V" B o--"""'_+-'--v A+B+C

+1~C
~~c
o "0" "1" "0" "1"

Fig. 11 Fig. 12

Large fan-in AND gate Squarewave oscillator

15V
15V

4.3K!l
100KO

3K!l
Vo ..fLJ±Vcc
~-+---c;;I
O~
f=100KHz
A·B·C·D
"0" "1"
15V 0--,.,..,-+--'---'

Fig. 13 Fig. 14

c8 SAMSUNG SEMICONDUCTOR 487

LM239/A, LM339/A, LM2901, LM3302 LINEAR INTEGRATED CIRCUIT

ORlng the outputs Peak auqio level display

15V

02
3Kn
5.fN

>--+--oVo Rl0
6BOll
IN lKIl

01 Rll BBOIl
112
LM239

>------'6BOU
R12

13
-10 dB (0.6V)
R2

Fig. 15 Fig. 16

Zero crossing detector (single supply) Zero crossing detector (split supplies)
VINmln ",,04V peak for 1% 'phase distortion (.10 fJ)

15V

+vcc
R4
220 10KIl
B.2KII 6BKU KIl

Rl R2 >,,-1-0Vo
01

Fig. 1,8
D1 prevents input from going negative by more than O.6V:
R1+R2=R3 ..
R3 .;; R5/10 for smaller error in zero crossing

c8 SAMSUNG SEMICONDUCTOR 488

LM2931A, .LM3931A, LM2903 LINEAR INTEGRATED CIRCUIT

DUAL DIFFERENTIAL COMPARATOR

8 DIP
The LM293 series consists of two independent voltage comparators
that one designed to operate from a single power supply over a wide
range of voltage.

FEATURES
8 SOP
• Single Supply Operation: 2V to 36V
• Dual Supply Operation: :t 1V to :t 18V
• Allow Comparison of Voltages Near Ground Potential
• Low Current Drain 800J.<A, Typ
• Compatible with all Forms of Logic
• Low Input Bias Current 25nA lYP
9 SIP
• Low Input Offset Current ± 5nA lYP .
• Low Offset Voltage :t 2mV Typ

II
BLOCK DIAGRAM

oz
5 I +
Cl
N
I-
::::J
o
o ~ ~

ORDERING INFORMATION
Device Package Operating Temperatur .
LM293N
8 DIP
LM293AN
LM293S 9 SIP -25 _+85°C
LM293D
8 SOP
LM293AD
LM393N
8 DIP
LM393AN
LM393S 9 SIP 0,- + 75°C
LM393D
8 SOP
LM393AD
LM2903N 8 DIP
-40-+85°C
LM2903D 8 SOP

c8 $AMSUNG SEMICONDUCTOR 489

LM293/A, LM393/A; LM2903 LINEAR INTEGRATED CIRCUIT

SCHEMATIC DIAGRAM
vee
. - - - - - - - , - - - - . , . . - - - - : - - 0 (OR
vee+)
CURRENT
REGULAlOR

OUTPUT

INVERTING
INPUT

GND
L--~~----~-4--_o(OR
Vee-)

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Power Supply Voltage

Differential Input Voltage
Vs
V,o
±18 or 36
36
. V
V
Input Voltage V, -0.3 to +36 V
Output Short Circuit t6 GND Continuous
Power Dissipation ·po 570 mW
Operating Temperature
LM293/LM293A -25- +85 ·C
Topr ·C
LM393/LM393A 0-+70
LM2903 -40- +85 ·C
Storage Temperature Tstg -65-+150 ·C

c8 SAMSUNG SEMICONDUCTOR 490

 LM2931A, LM3931A, LM2903 LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS (Vee =5V, Ta=25·C, unless otherwise specified)

LM293A1LM393A LM293JLM393
Characteristic Symbol Test Conditions Unit
Min Typ Max Min Typ Max

VCM=OV to Vcc-1.5V ±1 ±2 ±1 ±5
Input Offset Voltage VIO mV
Vo = 1.4V,.R. =0 T am,n:S T a:S T amax ±4.0 ±9.0
±5 ±50 ±5 ±50
Input Offset Current 110 nA
Tam;n:sTa:sTamax ±150 ± 150
25 250 25 250
Input Bias Current Ie nA
T amln:sTa:sTamax 400 400

Input Common Mode 0 Vcc-1.5 0 Vcc-1.5

VICR V

II
Voltage Range T amln:sTa:sTamax 0 Vcc-2 0 Vcc-2
RL=OO 0.4 1 0.4 1
Supply Current Icc mA
RL =00 Vee = 36V 1 2.5 1 2.5
Voltage Gain Av Vee = 15V, RL~15Kn(for large Vo swing) 50 200 50 200 V/mV
Large Signal Response V1N = TTL Logic Swing
tRES' 300 300 nS
Time V ref =1.4V, VRL =5V, RL=5.1Kn
Response Time tRES2 . VRL =5V, RL=5.1Kn 1.3 1.3 J.'S
Output Sink Current Islnk VIN-~1V, V1N + =OV, Vo:s1.5V 6 16 6 16 mA

VIN-~1V, VIN + =OV 250 400 250 400

Output Saturation Voltage V.a• mV
1.;nk=4mA Tamln:sTa:sTamax 700 700

VIN - =0, Vo=5V 0.1 0.1 nA

Output Leakage Current Ileak
V;n+ '" 1V Vo=30V 1.0 1.0 J.'A

'* TaminSTaSTamax
LM293/LM293A: Tamln = - 25· C, Tamax = + 85· C
LM393/LM393A: Tam;n=O·C, Tamax= +70·C
LM2903: Tam;n= -45·C, Tamax= +85°C

.. ciS SAMSUNG SEMICONDUCTOR 491

LM293/A, LM393/A, LM2903 LlN.EAR INTEGRATED CIRCUIT

·ELECTRICAL CHARACTERISTICS (Vcc =5V, Ta=25·C, unless otherwi!le specified)

LM2903
Characteristic Symbol Test Conditions Unit
Min Typ Max

VCM = OV to Vcc-1.5V· ±2 ±7
Input Offset Voltage VIO mV
Vo= 1.4V, Rs=O Tamtn:sTaS Tamax ±9 ±15
±5 ±SO
Input Offset Current 110 nA
Tamln~Ta~Tamax ±50 ±2oo
25 250
Input Bias Current Is nA
Tamln ~ Ta~ Tamax SOO
Input Common Mode 0 Vcc·1.5
VICR Vee=30V V
Voltage Range Tamin~Ta~Tamax 0 Vcc-2
RL=OO 0.4 1
Supply Current Icc mA
RL=OO Vcc =36V 1 2.5
Voltage Gain Av Vee = 15V, RL~15KO (for large Vo swing) 25 100 V/mV
Large Signal Response VIN = TIL Logic Swing
tRES1 300 nS
Time Vref=1.4V, VRL =5V, RL=5.1KO
Response Time tRES2 VRL =5V, RL=5.1KO 1.5 ItS
Output Sink Current ISlnk VIN-~1V, VIN + =OV, Vo~1.5V 6 16 mA

VIN-~1V, VIN + =OV 250 400

Output Saturation Voltage V... mV
. Isink =4mA T amin~T.~Tamax 700

V IN - =0, Vo=5V 0.1 nA

Output Leakage Current Ileak
Vln+.= 1V Vo=30V 1.0 "A
* Tamin~Ta:::;;Tamax '
LM293/LM293A: T amin = - 25·C, Tamax = + 85·C
LM393/LM393A: T amin = O·C, Tamax = + 70·C
LM2903: Tamln= -45·C, Tamax= +85·C

c8 SAMSUNG SEMICONDUCTOR 492

LM293/A, LM393/A, LM2903 LINEAR INTEGRATED CIRCUIT

•
TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT V. SUPPLY VOLTAGE INPUT CURRENT V. SUPPLY VOLTAGE

Ta=oJc _
0.8
~
C
.!
Ii
....- ~ ...- Ta= +1250C
I
....- ~ ~
".
w
a:

-
a: 0.8
"
u ~
Ta= J70 0 C
~
...... "....
"co
0.4
V Rl=OO

0.2
o 10 20
SUPPLY VOLTAGE

OUTPUT SATURATION VOLTAGE

M
30 10 20
SUPPLY VOLTAGE M

RESPONSE TIME
30

II
I IN~T OJERD~IVE I +5vl
t
~~
~ j
~. 1 100mV 20mA 5mV

~~
OUT OF
:! SATURATION VIN - ~OUT-
~
+
I---

i~ 0.1
Ta= +85-6
~~=+25OC- 1 I---

a /~ ~Ta=ood s
~
5 0.01
/ 'A~a=_Joc .!
w
~
0

o
L ~~ g
-5)

0.001 ~
0.01
r 0.1 1 10
t--100
~
i!!
0.5 1 1.5
OUTPUT SINK CURRENT (mAl TIMEt.sl

RESPONSE TIME

INPUT OVERDRIVE

4
I fI I
3
100mV I /20mv l5mv
2 I I /1 +5V

1 il II II
5.11<0
0
Vw
-
+ V"",

o 0.5 1 1.5
TillE",",

c8 SAMSUNG SEMICONDUCTOR 493

LM2931A, LM3931A, LM2903 LINEAR INTEGRATED CIRCUIT

APPLICATION INFORMATION .
The LM293 series are high gain, wide bandwidth devices which, like most comparators, can easily oscillate if the
output is inadvertently allowed to capacitively couple to the inputs via stray capacitance. That occurs during the
output voltage transitions, when the comparator changes state.
To minimize this problem, PC board layout should be deslg~ed to reduce stray input-output coupling, reducing the input resis-
tors to less than 10KO reduces the feedback signal levels and finally, adding even a small am!>unt (1 to 10mV) of positive feed-
back (hysteresis) cauSes such a rapid transition that oscillations due to stray feedback are not possible.
If is good design practice to ground all unused pins.
The differential input voltage may be larger than positive supply withoUt damaging the device. Note that voltages more negative
than -0.3V should not used: an input clamping diode can be used as protection.
The output of the LM239 series is the uncommitted collector of a NPN transistor with grounded emitter. The allows
the device to be used like any open·collector gate providing the OR-wide facility.
The output sink current capability is approximately 16mA; if this limit is exceeded, the output transistor will come out of satu-
ration and the output voltate will rise very rapidly.
Under this limit, the output saturation voltage is limited by the approximatively 600 r... of the output transistor.

TYPICAL APPLICATIONS (Vee = + 15V)

Basic comparator Non-inverting comparator with Hysteresis Inverting comparator with

Hysteresis

+vcc +vcc

+VAEF 3K!I +VIN 3KII

3KII

>-4-0 vo +VIN 10KII +v 1M1l

1MII

Fig. 3 Fig. 4 1MII Fig. 5

Driving C-MOS Driving TTL

+5V +5V

Fig. 6 Fig. 7

c8 SAMSUNG S~MICONDUcroR 494

LM293/A, LM393/A, LM2903 LINEAR INTEGRATED CIRCUIT

APPLICATION INFORMATION (continued)

AND gate OR gate

+vcc +V..

3KIl 3K{!

3x100KIl
A 0--410__--,
A 0---4\,,.,,,,..., >--4--oA·B·C
Bo---4\,"""'~----~~~
B n-_ _ -+----~-I,...,

C 0-_ _-'
+V.. C 0---4\,"""'~
+~
oS "0" "1" o "0" "1"

Large fan·in AND gate

Fig. 8

Squarewave oscillator +Vre

Fig. 9
II
+Vcc-r- A-BOO
o --J A,o--N-~-=':::.:..::.t·!.o"
''0'' "l"IB o---M~
Co---M~
oo--M..::..:..J

Fig. 11

Pulse generator One-shot multivibrator

+Vre

15K!!
R1 D1

1M1l 1N914 10KII -.::;...:: V+

R2 D2 1ms :J C
">4--ovo 10 11
1N914

Vo

Fig. 12 Fig. 13

c8 SAMSUNG SEMICONDUCTOR 495

 KS555 CMOS INTEGRATED CIRCUIT

CMOS TIMER
8 DIP
The KS555 is CMOS RC ·timer providing significantly improved per-
formance over the standard NE555,While at the same time being direct
replacements for those devices in most applications. Improved
parameters include low supply current, wide operating supply voltage
range, low THRESHOLD, TRIGGER and RESET currents, no crowbar-
ring of the supply current during output transitions, higher frequency
performance and no requirement to decouple CONTROL VOLTAGE for
stable operation.
Specifically, the KS555 is stable controller capable of producing accurate 8 SOP
time delays or frequencies. In the one shot mode, the pulse width of each
circuit is precisely controlled by one external resistor and capacitor. For
astable operation as an oscillator, the free running frequency and the duty
cycle are both accurately controlled by two external resistors and one
capacitor. Unlike the regular bipolar 555 device, the CONTROL
VOLTAGE terminal need not be decoupled with a capacitor. The circuit
is triggered and reset on falling (negative) waveforms, and the output
inverter can source or sink currents large enough to drive TTL loads, or
provide minimal offsets to drive CMOS loads.

FEATURES APPLICATIONS
• Exact equivalent in most cases for NE555.
• P.recision Timing
• Low Supply Current: 80pA Typ.
• Pulse Generation
• Extremely low trigger, threshold and. reset current: 20pA Typ.
• Sequential Timing
• High speed operation: 500KHz
• Time Delay Generation
• Wide operation supply voltage range: 2 to 18 Volts
• Pulse Width Modulation
• Normal reset function: No crowbarring of supply during output
• Pulse Position Modulation
transition.
• Missing Pulse Detector
• Timing from microseconds through hours
.• Operates In both astable and monostable modes
ORDERING INFORMATION
• Adjustable duty cycle
• High output source/sink driver can drive TTL/CMOS Device Package Operating Temperature
• Highly immunized to static charge KS555N 8 DIP
-20 _ +85°C
SCHEMATIC DI.rA::G-:R:A~M~-.,..._--.,-
,
_ _ _..,'=K=S5~55=D==8:;S=O=P======::;:===o;~
vee
8

THRESHOLD
0-----1
6

CONTROL VOLTAGE OUTPUT

GN[

.c8 SAMSUNG SEMICONDUCTOR 496

KS555 CMOS INTEGRATED CIRCUIT

BLOCK DIAGRAM
vee

THRESHOLD
6
10-----...-------1 ~-___._--I ">0.------1') OUTPUT
3

CONTROL R JI;lISCHARGE
VOLTAGE

I
2o-------~------~ GNJ1
TRIGGER
COMPARATOR
R
B

GND 1

This block diagram reduces the circuitry down to its simplest equivalent components. Tie down unused inputs.
R= 100K{J±20% Typ. .

TRUTH TABLE
Threshold Trigger Discharge
Reset Output
Voltage Voltage Switch
Don't Care Don't Care Low Low On
-- ---------- -------
>2/3 (Vee) > 113 (Vee) High Low On
--- ---------- ----~---- - f------- - - - -
< 1/3(Vee) - 2/3(Vee) >_________
1/3(Vee) - 2/3(Vee)
c---'. High Stable Stable
--.-----~------ - - - - - - ' - f--- '-
Don't Care < 1/3 (Vee) High High Off

Note: RESET will dominate all other input.TRIGGER will dominate over THRESHOLD.

ABSOLUTE MAXIMUM RATINGS (Note 1)

Characteristic Symbol Value Unit

Supply Voltage Vee 18 V

Input Voltage VIN -0.3 - Vee +0.3 V
(Trigger, Control Voltage,
Threshold and Reset)
Output Current lOUT 100 mA
Power Dissipation Po 200 mW
Operating Temperature Range Topr -20 - +85 °C
Storage Temperature Range T.tg -65 - +150 DC

Note 1: Stresses above those listed under absolute maximum rating may cause permanent damage to the device.

c8 SAMSUNG SEMICONDUcroR 497

KS555. CMOS INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS
(T. = 25°C. Vee =2 to 15 Volts unless otherwise specified)

Characteristic Symbol Test Conditions Min 1\'p Max Unit

Supply Voltage Range Vee -20°C <T.< +7O"C 2 18 V

Vec=2V 60 200 pA
Supply Current Icc
Vc;e=18V 120 300 pA
Timing Error MT R.= Rb = 1KO to 100KO
C=0.1/LF.
I~itial Accuracy 5Y :sVee:S 15V 2.0 5.0 %
Vcc=5V 50 ppm/oC
Drift With Temperature Vee = 10V 75 ppm/oC
Vee = 15V 100 ppml°C
Drift With Supply Voltage Vee=5V 1.0 3.0 %N
Threshold Voltage VTH Vee=5V O.~ 0.66 0.67 Vee
Trigger Voltage V TA Vee=5V 0.29 0.33 0.34 Vee
Vee = 18V 50 pA
Trigger Current IrR Vee=5V 10 pA
Vcc=2V 1 pA
Vcc=18V 50 pA
Thresl10ld Current ITH Vee=5V 10 pA
Vee=2V 1 pA

I VRfff =GND Vee =18V 100 pA

Reset Current IRE VRfff=GND Vee=5V 20 pA
VRfff=GND Vee=2V 2 pA
Vee=18V 0.4 0.7 1.0 V
Reset Voltage VRE
Vee=2V . 0.4 0.7 1.0 V
Control Voltage Ve Vee=5V 0.62 0.66 0.67 Vee
Vee=18V.lsINK=3.2mA 0.1 0.4 V
VOL
Vee=5V.lsINK=3.2mA 0.15 0.4 V
Output Voltage Drop
Vee = 18V.lsource= 1.0mA 17.25 17.8 V
VOH
Vee =5V. Isource =1.0mA 4.0 4.5 V
Rise Time of Output Tr RL= 10MO. CL= 10pF. 35 40 '5 ns
Fall Time of Output Tf Vee=5V 35 40 75 ns
Guaranteed Max Osc. Freq. Fmax Astable Operation 500 KHz

c8 SAMSUNG SEMICONDUCTOR 498

KS555 CMOS INTEGRATED CIRCUIT

APPLICATION NOTES
General
The KS555 device is, in most instances, a direct 'replacement for the NE555 device. However, it is possible to effect
economies in the external component count using the KS555. Because the bipolar 555 device produce large crowbar currents
in the output driver, it is necessary to. decouple the power supply lines with a good capacitor close to the device. The KS555
device produce no such transients. See Figure 1.
The KS555 produces supply current spikes of only 2-3mA instead of 300-400mA and supply decoupling is normally not
necessary, in most instances, the CONTROL VOLTAGE decoupling capacitors are not required since the input impedance
of the CMOS comparators on Chip are very high. Thus, for many applications 2 capacitors can be saved using an KS555.
400

T... 25°C n
300

I
NE555

\
.\
KSS55

200 400 eoo 000

nME_nl

Fig 1. Supply current transient compared with a standard bipolar 555 during an output transition

Power Supply Considerations

Although the supply current consumed by the KS555 device is very low, the total system can be high unless the timing
components are high impedance. Therefore, use high values for R and low values for C in Figures 2. and 3.

Output Drive Capability

The output driver consists of a CMOS inverter capable of driving most logic families including CMOS and TTL. As such,
if driving CMOS, the output swing at all supply voltages will equal the supply voltage. At a supply voltage of 4.5 vol!s or
more the KS555 will drive at least 2 standard TTL loads.

Astable Operating
The circuit can be connected to trigger itself and free run as a multivibrator, see Figure 2. The output swings from rail
to rail, and is a true 50% duty cycle square wave. (Trip points and output swings are symmetrical). Less than a 1% frequency
variation is observed, over a voltage range of +5 to +15V.
vee
1
f= 1.4RC 10KIl
Vee

ALTERNATE
KS555 OUTPUT
OUTPUT

R
Fig. 2. Astable Operatiol

=8 SAMSUNG SEMICONDUCTOR 499

 KS555 CMOS INTEGRATED CIRCUIT

Monostable Operation
In this mode of operation, the timer functions as a one-shot. Initially the external capacitor (C) is held discharaged by
a transistor inside the timer. Upon application of a negative TRIGGER pulse to pin 2, the internal flip flop is set which releases
the short circuit across the external capacitor and drives the OUTPUT high. The voltage across the capl\citor now increases
exponentially with a time constant t=RaC.
When the voltage across the capacitor equals 2/3 Vee, the comparator resets the flip flop, which in turn discharge the
capacitor rapidly and also drives the OUTPUT to its low state. TRIGGER must return to a high state before the OUTPUT
can return to a low state.

vee

Ra

KS555

5 -,
I
II
I

Vcc:s18V -'--
~~~~TOR;

Fig. 3. Monostable Operation

Control Voltage
ThE! CONTROL VOLTAGE terminal permits the two trip voltages fo'r the THRESHOLD and TRIGGER internal compara-
tors to be controlled, This provides the possibility of oscillation frequency modulation in the applied voltage. In the monostable
mode, delay times can be changed by varying the applied voltage to the CONTROL VOLTAGE pin.

Reset .
The RESET terminal is designed to have essentially the same trip voltage as the standard bipolar 555, i.e. 0.6 to 0.7 volts.
At all supply voltages it represents an extremely high input impedance. The mode of operation of the RESET function is,
, however, much improved over the sta'ndard bipolar 555 in that it controls only the internal flip flop, which in turn controls
simultaneously the state of the multiple 'threshold problems sometimes encountered with slow falling edges in the bipolar
devices. '

c8 SAMSUNG SEMICONDUCTOR 500

 KS555H CMOS INTEGRATED CIRCUIT

CMOS TIMER
8 DIP
The KS555H is monolithic integrated circuit fabricated using CMOS process.
Due to its high impedance inputs (threshold. trigger. reset). it is capable of
producing accurate time delay and oscillation using less expensive,
smaller timing capacitors than NE555.
Another features are very low power consumption and high speed astable
operation and very low voltage operation.

FEATURES
8 SOP
• Very low power consumption: 1.2mW
'. Very high speed operation: 2MHz
• Complementary CMOS output capable of switching rail·to·rail
• Output fully CMOS·, TTL·, and MOS· compatible
• Exactly equivalent in most cases for'NE555 or .556 (dual timer)

I
or the 355
• Well behaved reset function
• Timing from microseconds through hours
• Operates in both astable and monos table modes
• Adjustable duty cycle
• Highly immuned to static charge

APPLICATIONS
• Precision Timing
• Pulse Generation
• Sequential Timing
• Time Delay Ger1'eration
• Pulse Width Modulation
• Pulse Position Modulation
• Missing Pulse Detector

BLOCK DIAGRAM' ORDERING INFORMATION

Package Operating Temperature
a DIP
a SOP

.GND GND1GND
Fig. 1

c8 SAMSUNG SEMICONDUCTOR 501

KS555H CMOS INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Supply Voltage Vee 18 V

Input Voltage
V ,N -0.3 - Vee V
(Trigger, Reset,: Threshold)
Lead Temperature T ,ead ' 300 ·C
(Soldering 10 sec)
Power Dissipation PD 600 mW
Operating Temperature, Range Topr 0-70 ·C
Storage Temperature Range Tstg -65-150 ·C

ELECTRICAL CHARACTERISTICS
(Ta=25·C, Vee =5V, refer to application circuit unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

Supply Voltage . Vee 3 18 V

Supply Current Icc 240 itA
Vee = 15V 480 itA
Control Voltage Ve 3.33 V
Vee =15V 10 V
Threshold Voltage VTH '3.33 V
Vee =15V 10 V
Threshold Current ITH Vee=5V 50 PA
Trigger Voltage VTR 1.67 V
Vee =15V 5 V
Trigger Current IrR 50 PA
Reset Voltage VRf 0.7 1 V
Reset Current IRE 50 PA
IOL=5mA 0.1 V
IOL=8mA 0.15 V

Low Level Output Voltage VOL Vee = 15V

IOL=10mA 0.1 V
IOL=50mA 0.5 V
10L= 100mA 1 V
10H= -1mA 4.5 V
10H'= -2mA 4 V
High Level Output Voltage VOH Vee=15V
10H= -1mA 14.8 V
10H= -5mA 14 V
10H = -10mA 12.7 V

c8 SAMSUNG SEMICONDUCTOR 502

KS555H CMOS INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS (Continued)

Characteristic Symbol . Test Conditions Min Typ Max Unit

Initial Error of
TEl 1 %
Timing Interval Vee = 5 to 15V, RA = Rs = 1 to 100K
Timing Error Due to CT =0.1J.'F
TES 0.1 %N
Supply Drift
Rise Time of Output T, 20 nS
RI = 10MO, CI = 10pF
Fall Time of Output T, 20 nS
Maximum Astable
FMAX RA = 4700, Rs = 2000, CT = 200pF 2.1 MHz
Oscillation

APPLICATION CIRCUIT
·1) ASTABLE
I
The circuit can be connected to trigger itself and free run as multivibrator. The external capacitor charges through
RA and Rs and discharges through Rs only. Thus the duty cycle may be precisely set by the ratio of these two
resistors. In this mode of operation, the capacitor charges and discharges between 1/3. Vee and 213 Vee.
As in the trigger mode, the charging and discharging times, and therefore the frequency are essentially independently
of the supply voltage.
The frequency of oscillation is given by

f == 11T = 1.44/(RA + 2 x Rs)/C

Vee

O'1~FJ

J
CONT
(8)
VDD RL

~ RESET

(7)
DISCH
KS555H (3)
OUT OUTPUT

Rs (6)
, . - - THREE

(2)
TRIG
f"
." GND
rf;1)

c8SAMSUNG SEMICONDUCTOR 503

KS555H CMOS INTEGRATED CIRCUIT

2) MONOSTABLE
, In this mode of operation, the timer functions as one shot. Initially; the external capacitor C is held discharged
by a transistor inside timer. Upon application of negative trigger pulse to pin 2, the flip flop is set which releases
the short circuit across the external capacitor and drives the output high.
=
The voltage across the external capacitor now increases exponentially with a time constant T RA "C. When the
voltage across the external capacitor equals 213"Vee , the comparator resets the flip flop, 'which in turn discharges
the capacitor repidly and alsq drives the output to its state.

Vee
(

O'1"F
J
R

J
CONT VDD
(8)

~ RESET

(7)
DISCH
(3)
KS555H OUT OUTPUT

~ THRES

INPU T (2) TRIG

GND

. ,g1)
Fig. 3

c8 SAMSUNG SEMICONDUCTOR 504

KS556 CMOS INTEGRATED CIRCUIT

14 DIP
CMOS TIMER
The KS556 is monolithic integrated circuit fabricated using C-MOS
process. Due to high impedance inputs (Trigger, Threshold, Reset), it
is capable cif producing accurate time delay using less expensive,
smaller timing capacitor than NE556.
Another features one very low power consumption and high speed
astable operation and very low voltage operation. .
14 SOP

FEATURES
• Very low power consumption: 2.4mW .
• Very high speed operation: 2MHz
• Output fully CMOS, TTL, and MOS compatible

II
• Timing from mlcrosecpnds through hours
• ~djustable duty cycle

APPLICATIONS ORDERI.NG INFORMATION

• Precision Timing Device Package Operating Temperature
• Pulse Generation
• Sequential Timing KS556N 14 DIP
0- + 70·C
• Time Delay Generation KS556D 14 SOP
• Pulse Width Modulation

BLOCK DIAGRAM
vee (14)

VA BIAS
C.K.T.
CONTROL (3.11) cr---+----j
THRESHOLD (2.12) cr--+---j
GND (7)

\ ""-_.....r. OUTPUT (5, 9)

GND

c8 SAMSUNG SEMICONDUCTOR 505

KS556 CMOS INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (fa =25°C)

Characteristic Symbol Value Unit

Supply Voltage Vee 18 V

Input Voltage
V1N -0.3-Vee V
(Trigger, Reset, Threshold)
Lead Temperature
T1ead 300 ·C
(Soldering 10 sec)
Power Dissipation Po 600 mW
Operating Temperature Range Top, 0-+70 ·C
Storage Temperature Range Tstg -6S-+150 ·C

ELECTRICAL CHARACTERISTICS
(Ta= 2S·C, Vee = SV, refer to application circuit unless otherwise specified)

Characteristic Symbol Test Cond!tions Min Typ Max Unit

Supply Voltage Vee 3 18 V

240
Supply Current Icc p.A
Vee=1SV 480
3.33
Control Voltage Ve V
Vee=1SV 10
3.33
Threshold Voltage VTH V
Vee = 1SV 10
Threshold Current IrH 50 pA
1.67
Trigger Voltage VTR V
Vee=1SV S
Trigger Current IrR SO pA
Reset Voltage VRe 0.7 V
Reset Current IRE 50 pA
IOL=SmA 0.1
IOL=8mA 0.1S
Low Level Output Voltage VOL Vee=1SV IOL= 10mA 0.1 V
Vee=1SV IOL=50mA O.S
Vee=1SV IOL=100mA 1
IOH= -1mA 4.S
IOH= -2mA 4
High Level Output Voltage VOH V
Vee = 1SV IOH= -1mA 14.8
IOH= -SmA 14
IOH= -10mA 12.7

c8 SAMSUNG SEMICO.NDUCTOR . 506

KS556 CMOS INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS (Continued)

Characteristic Syinbol Test Condition Min Typ Max Unit

Initial Error of Timing Interval TEl Vee=5 to 15V 1 %

RA=Rs=1 to 100K
Supply Voltage Sensitivity of TES CT =0.1/LF
0.1 %N
Timing Interval
,
Rise Time T, RL= 10MO, CL= 10pF 20 nS
Fall Time T, RL = 10MO, CL= 10pF 20 nS
RA = 4700, Rs = 2000
Maximum Astable Oscillation Fmax 2 MHz
CT =200pF

APPLICATION CIRCUIT
1) Astable
II
The circuit can be connected to trigger itself and free runs as multivibrator. The external capacitor chrages through
RA and Rs and discharges ·through Rs only. Thus the duty cycle may be precisely set by the ratio of these two
resistors. In this mode of operation, the capacitor charges and discharges between 1/3 Vee and 2/3 Vee.
As in the trigger mode, the charging and discharging times, and therefore the frequency, are essentially independently
of the supply voltage. These frequency of oscillation is given by

F =11T =1.44/(R" + 2* Ra)/C

vee

O'1~F±
OPEN

(3J (14)
CONT Vee
RL (1K)
~ RESET

(1.13)
DISCH
KS556 (5.9)
OUT OUTPUT

RS ~

(6.8)
THRES

TRIG
I"'· pF)

t
CT GND

rh(7)

c8 SAMSUNG SEMICONDUcroR 507

KS556 CMOS INTEGRATED CIRCUIT

2) Moriostable
In this mode of operation, the timer functions as one shot. Initially, the external capacitor (C) Is held discharged
by a transistor inside timer. Uponapplicatioi:l of negative trigger pulse to trigger pin the flip flop is set which releases
the short circuit across the external capacitor and drives the output high. .
The voltage across the external capacitor nQw increases exponentially with time constant T = RA X C. When the'
voltage across the extemal capacitor equals 213 x Vee, the comparator resets the flip flop, which in tum discharges
the capacitor !rapidly and also drives the output to its state.

Voo

O'l~F± .
OPEN

(3.11,1 (14)
CONT Voo RL(lK)
(4.10)
---<: RESET

(1.13)
DISCH

KS556 (5.9)
OUT OUTPLUT

f"""
:: ~ THRES OpF)

(6.8)
INP UT TRIG

GND
);7)

c8 SAMSUNG SEMICONDUCTOR 508

 NE555 LINEAR INTEGRATED CIRCUIT

8 DIP
TIMER
The NE555 series are a monolithic integrated circuit and high
stable device for generating accurate time delay or oscillation.

FEATURES
• Turn off tim!lless than 2/Ls
• Maximum operating frequency greater than 500KHz
• Timing. from microseconds to hours 8 SOP
• Operates in both astable and monostable modes
• High output current
• Adjustable duty cycle
• Temperature stability of 0.005% per °C

APPLICATIONS
•
•
•
•
•
Precision timing
Time delay generation
Pulse generation
Pulse position modulation
Sequential timing
ORDERING INFORMATION
II
• Missing pulse detector Device Package Operating Temperature
NE5551N 8 DIP
-40- +85·C
NE5551D 8 SOP
. BLOCK DIAGRAM NE555CN 8 DIP
0-+70·C
NE555CD 8 SOP

Vee
Control Voltage

Rl
R2

' - - - - - - - - - - . . . . . . ( 3 ) - -.......-( } _ _ _ _ _ _....I

Output' GND

=8 SAMSUNG 'SEMICONDUcToR 509

NE555 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)

Characteristic Symbol Value Unit

Supply Voltage Vcc· 16 V

Lead Temperature (soldering 10 sec) T 'oad 300 ·C
Power Dissipation Po 600 mW
Operating Temperature Range NE5551 Topr -40- +85 ·C
NE555C 0-+70 ·C
Storage Temperature Range T" g -65- + 150 ·C

ELECTRICAL CHARACTERISTICS
(T.=25"C, Vcc=S-1S\I, unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

Supply Voltage Vcc 4.5 16 V

Supply Current" Vce=5V, RL=oo 3 6 mA

Icc
"1(low stable) Vcc=15V, RL=oo 10 15 mA
"Timing Error
(Monsotable)
21nitial Accurary MT1 RA = 1 KO to 1.0 3.0 %
Drift with Temperature 100KO 50 ppm/·C
Drift with Supply.Voltage C=0.1/LF 0.1 0.5 %N
"Timing Error
(astable) RA=1K t.o
21nitial Accurary MT2 100KO 2.25 %
Drift with Temperature C=0.1/LF 150 ppm/·C
Drift with Supply Voltage 0.3 %N
Vee=15V 9.0 10.0 11.0 V
Control Voltage Vc
. Vcc=5V 2.6 3.33 4.0 V.
Vce= 15V 10.0 V
Threshold Voltage· VTH
Vcc=5V 3.33 V
"3Threshold Current IrH 0.1 0.25 /LA
Trigger Voltage VTR Vcc=5. 1.1 1.67 2.2 V
Trigger Voltage VTR Vce= 15V 4.5· 5 5.6 V
Trigger Current IrR VT=OV 0.5 2.0 /LA
Reset Voltage VRE 0.4 ·0.7 1.0 V
Reset Current IRE 0.1 0.4 mA

c8 SAMSUNG SEMICON·DUcrOR 510

NE555 LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS
(Ta =25OC, Vee =5 -15V, unless otherwise specified)

Test
Characteristic Symbol Min Typ Max . Unit
Conditions

V ee .. 15V
Is ;nk=10mA 0.1 0.25 V
l"nk=50mA 0.4 0.75 V
Output Voltage (low) VOL
Vee= 5V
1.,nk=5mA 0.25 0.35 V
Vee = 15V
lsou,eo = 200mA 12.5 V
locu,eo = 100mA 12.75 13.3 V
Output Volta!1e (high) VOH

II
Vee=5V
locu",. ':" 1OOmA 2.75 3.3 V
Rise Time of Output T, 100 nsec
Fall Time of Output T, 100 nsec
Discharge Leakage Current 10 20 100 nA

APPLICATION CIRCUIT
Cl Rs

THRESHOLD
r-------~2~----------~

Low

vee

Flip-Flop

~----------------------~3}-------------~
Output

Notes:
1. Supply current when output is high is typically 1mA less at Vee =5V.
2. Tested at Vee =5.0V and Vee =15V
3. This will determine the maximum value of RA +Ra. for 15Voperation, the max total R=20MO, and for 5Voperation the
max total R=6.7MO.

=8 SAMSUNG SeJ.liICONDUcrOR 511

NE555 LINEAR INTEGRATED CIRCUIT

APPLICATION NOTE
The application circuit shows astable mode.
The pin 6 (threshold) tied to the pin 2 (trigger) and pin 4 (reset) tied to Vee (pin 8).
The external capacitor C, of pin 6 and pin 2 charges through RA• RB and discharges through RB only.
In the internal circuit of the NE555 one input of upper comparator is the 213 Vcc (OR, =R2 =R3). another input of it connect-
ed pin 6. .
As soon as charging C, is higher than 213 Vcc. discharge transistor 0, turn on and C, discharges to collector of transistor 0,.
Therefore flip-flop circuit is reset and output is low. .
One input of. lower comparator is the 1/3 Vcc. discharge transistor 0, turn off and C, ~harges through RII and RB.
Therefore flip-flop circuit is s8t and output is high.
So to say. when C, charges through R" and RB output Is high and when C, discharges through Rb output is low
The charge time (output is high) T, is 0.693 (RA +RB) C, and the discharge time (output is low) T. is 0.693 (RB C,).

(In VCC"lm~e -0.693)

Vcc-2mcc

Thus the total period time·T is given by

T=T, +T.=0.693 (RA+2RB)'C"
Then. the frequency of astable mode is given by

f=.-!.= 1.44
T (RA +2RB)C,

The duty cycle is given by

D.C= T.=~
T RA+2RB

If you make use of the NE556 you can make two astable mode.
If you want another application note. request information on our timer IC application circuit designer.

c8 SAMSUNG SEMICONDUCTOR .512

NESS6 LINEAR INTEGRATED CIRCUIT

DUAL TIMER
14 DIP
The NE556 series dual monolithic timing circuits are a highly stable
controller capable of producing accurate time delays or oscillation.
The NE556 is a dual NE555. Timing is provided an external resistor
and capacitor for each timing function.
The two timers operate independently of each other, sharing only Vee
and ground.
The circuits may be triggered and reset on falling waveforms. The output
structures may sink or source 200mA. .
14 SOP

FEATURES
• Direct replacement for NE556
• Replace two NE555 timers
• Operates in both astable and monostable modes
• High output current
• TTL compatible
• Timing from microsecond to hours
• Adjustable duty cycle
• Temperature stability of 0.005% per °c

APPLICATIONS- ORDERING INFORMATION

• Precision timing _ • .Sequential timing Device Package Operating Temperature
• Pulse shaping • Pulse generator
• Pulse width modulation • Time delay generator NE5561N 14 DIP
-40-:' +85·C
• Frequency division • Touch tone encoder NE5561D 14 SOP
• Traffic light control • Tone burst generator
NE556CN 14 DIP
0-+70·C
NE556CD 14 SOP
BLOCK DIAGRAM
Control Voltage 3 r--------{11 Control Voltage 8 Trigger

A A
A A
Comparator

THAESHOLD
A

~------~Ou~~-u~t 5r----~~ ~~----~9'}O~u~tP-ut~----{1101~Ae-s-~--~

cR. SAMSUNG SEMICONDUCTOR 513

NESS6 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Ta=25°C)

Characteristic Symbol Value Unit·

Supply Voltage Vee 18 V

Lead Temperature (soldering 10 sec) T 'ead 300 ·C
Power Dissipation Po 600 mW
Operating Temperature Range NE5561 Topr -40-+85 ·C
NE556C 0-+70 . ·C
Storage Temperature Range T stg -65 - +150 ·C

ELECTRICAL CHARACTERISTICS
(Vee = +5V to + 15V, unless otherwise specified)

Characteristic Symbol Test Conditions Min ~p Max Unit

Supply Voltage Vee 4.5 16 V

*1 Supply Current (Two timers) Vee =5V, RL= 00 6 12 mA
Icc
(low state) Vcc =15V, RL=oo 20 30 mA
*2 Timing Error (monostable) MT1 RA=2KOto100KO
Initial Accuracy C=0.1!'f 0.75 %
Drift with Temperature T=1.1Rc 50 %
Drift with Supply Voltage 0.1 %N
Vcc=15V 9.0 10.0 11.0 V
Control Voltage Vc
Vee=5V 2.6 3.33 4.0 V
Vcc=15V 10.0 V
Threshold Voltage VTH
Vcc=5V 3.33 V
*3 Threshold Current IrH 30 250 nA
Vcc=15V 4.5 5.0 5.6 V
Trigger Voltage VTR
Vee=5V 1.1 1.67 2.2 V
Trigd~( Cur.dnt IrR VT=OV 0.5 2.0 p.A
*5 Reset \"uilage VRE 0.4 0.7 1.0 V
Reset Current IRE 0.1 0.6 mA
Vcc=15V
1.'nk=10mA 0.1 0.25 V
1.'nk=50mA 0.4 0.75 V
1.'~k=100mA 2.0 2.75 V
Output Voltage Low VOL
ISink =200mA 2.5 V
Vcc=5V
Isink= 8mA 0.25 0.35 V
l~nk=5mA 0.15 0.25 V

c8 SAMSUNG SEMICONDUCTOR 514

NESS6 LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS
(Vcc=+5V to +15V, unless otherwise specified)

Characteristic Symbol Test Conditions Min l\'p Max Unit·

Vcc=15V
lsou",. =200mA 12.5 V
Output Voltage (high) VOH lsou"," =100mA 12.75 13.3 V
Vcc=5V
lsourc. = 100mA 2.75 3.3 V
Rise Time of Output Tr 100 nsec
Fall Time of Output Tf 100 nsec
Discharge Leakage Current 10 20 100 nA

I
*4 Matching Characteristics
Initial Accuracy MCH 1.0 2.0 %
Drift with Temperature 10 ppm/oC
Drift with Supply Voltage 0.2 0.5 %N'
*2 Timing Error (astable) RA, Rs =1kO to 100kO
Initial Accuracy C=0.1,..F 2.25 %
MT.
Drift with Temperature Vcc=15V 150 ppm/oC
Drift with Supply Voltage 0.3 %N

Notes:
1. Supply current when output is high is typically 1.0mA less at Vee =5V.
2. TestedatVee =5VandVec=15V
3. This will determine the maximum value of RA +Rs for 15V operation:
The maximum total R=20MO, and for 5Voperation the maximum total R=6.6MO.
4. Matching characteristic refer to tne difference between performance characteristics of each timer section in the monostable
mode.
5. As reset voltage lowers, timing is inhibited and then the output goes low.

c8 SAMSUNG SEMICONDUCTOR 515

 NE558 LINEAR INTEGRATED CIRCUIT

QUAD -TIMER 16 DIP

The NE558 series are a monolithic Quad Timers which
can be used to produce four entirely independent timing
functions. These highly stable, general purpose
controllers can be used in a monostable mode to
produce accurate time delays, from microseconds to
. hours. The time is precisely controlled by one external
resistor and one capacitor in the time delay mode. A
stable mOde can be operated by using two of four timer
sections. .
16 SOl!

FEATURES
• Wide supply voltage range: 4.SV to 16V
• 100mA output current per section
• Edge triggered without coupling capacitor
• Time period equals RC .
• Output independent of trigger conditions.

.APPLICATIONS ORDERING INFORMATION

• Quad one·shot Device Package Operating Temperature
.. Sequential timing
NE5581N 14 DIP -45-+85·C
• Precision timing
• Time delay generation NE558CN 14 DIP
O-+70·C
NE558CD 14 SOP.

BLOCK DIAGRAM

OUTPUT D TIMING D TRIGGER D RESET GROUND TRIGGER C TIMING C OUTPUT C

OUTPUT A TIMING A TRIGGER A CONTROL Vee TRIGGER B TIMING B OUTPUT B

VOLTAGE

c8 SAMSUNG SEMICONDUCTOR 516

NESS8 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Ta =25°C)

Characteristic Symbol Value Unit

Supply Voltage Vee 18 V

Lead Temperature (soldering 10 sec) Ttead 300 °C
Power Dissipation Po 600 mW
Operating Temperature Range NE5561 Top, -40-+85 °C
NE556C 0 -70 °C'
Storage Temperature Range Totg -65-+150 °C

ELECTRICAL CHARACTERISTICS
(Vee=5V-15V, Ta=25°C unless otherwise specified)

Characteristic

Supply Voltage
Supply Current
Symbol

Vee
Icc
\
Test Conditions

Vee = 15V, reset voltage=15V

Min

4.5
Typ

16
Max

16
36
Unit

mA
V I
Timing Error (T = RC),
±2 5 %
Initial Accuracy
MT R = 2KO to 100KO, C = 11'F PPM/OC
Drift with Temperature 30 150
Drift with Supply Voltage 0.1 0.9 %N
'Trigger Voltage VTR Vee=15V 0.8 1.5 2.4 V
'Trigger Current IrR Trigger voltage = OV 50 100 I'A
2Reset Voltage VRE .Reset 0.8 2.4 'V
2Reset Current IRE Reset 50 500 ,.,A
Threshold Voltage VTH 0.63 X Vee V
Threshold Current IrL 15 nA
k=10mA 0.1 0.4
30utput Voltage VOUT V
IL= 100mA 1.0 2.0
Output Leakage Current IOL 10 500 nA
Propagation Delay Time Tp 1.0 ,.,S
Rise Time Tr k=100mA 100 nS
Fall Time Tf IL= 100mA 100 nS

NOTES: 1. The trigger functions only on the falling edge of the trigger pulse onlY after previously being high. After
reset the trigger must be brought high and then low to implement triggering.
2. For reset below 0.8V, outputs set low and trigger inhibited..
'3. Output structure is open collector which requires a pull up resistor to Vee to sink current.
The output is nom ally low sinking current. .

ciS SAMSUNG SEMICONDUCTOR 517

NES58 LINEAR INTEGRATED CIRCUIT

APPLICATIONS
• Long·Time Delay

TRIGGERlJ

T
OUTPUT ~'l . ._______
Nt
558C J7 C2 OUTPUT~
OUTPUT~~
I--r"--ITR Ol-------<l
OUTPUT 4

OUTPUT 4 ~
TOELAY: 3(R,C)
Tour: R2C2
Fig. 1. Circuit Fig. 2. Timing Chart

• Ring Counter

cS
_".
SAMSUNG SEMICONDtJ~R
: I.
518
 Data Converter Application
Devlc,e Fu!,!ctlon Package Page

KSV3100A High-Speed AID-DA Converter 40 DIP 521

KSV3110 High-Speed AID-DA Converter 40 DIP 531
KSV3208' High-Speed AID Converter 28 DIP 541
, KAD0808 8 Bit ~p-Compatible AID Converter with 8-Channel 28 DIP 549
, Multiplexer
KAD0809 8 Bit I'P-Compatible AID Converter wit~ 8-Channel 28 DIP 549
Multiplexer
KAD0820AIB 8 Bit High Speed I'P Compatible AID Converter with 20 DIP 560
Track/Hold Function
KDA0800 8 Bit DIA Converter 16 DIP 580
KDA0801 8 Bit DIA Converter 16 DIP 580
KDA0802 8 Bit DIA Converter 16 DIP 580
KS25C02 8 Bit CMOS SuCcessive Approximation Register 16 DIP 586
KS25C03 8 Bit CMOS Successive Approximation Register 16 DIP 586
KS25C04 12 Bit CMOS Successive Approximation Register 24 SDIP 586
KS7126 3 112 Digit AID Converter 40 DIP 568
KSV3100A LINEAR INTEGRATED CIRCUIT

HIGH·SPEED AlD-D/A CONVERTER

40 DIP
Samsung KSV3100A, VLSI circuit in CI (Collector Implanted) technology,
consists of a high-speed flash-type a-bit AID converter and a high-speed
low-glitch 10-bit D/A converter designed as an R-2R network with
switched current sources. Also, the various auxiliary circuits, as reference
vol~ge sources; pre-amplifier, input clamping circuit and feed-in output
amplifier are integrated on the single Chip.
KSV3100A has been developed for use in all applications which call for
a high-speed AlD-D/A converter.
For instance, this VLSI circuit can be used to advantage to decode
television signals in Pay-TV converters or for MAC converters used in
direct satellite broadcast.
Other promising applications can be seen in industrial electronics, e.g.
in conjunction with Signal processing.
Although KSV3100A was initially designed as high-speed codecs for the
video range, it can be used with equal benefits for lower frequencies,
even down to zero.

BLOCK DIAGRAM

KSV3100A
I
Keyed
Clamping
______ 1

Fig, 1

The auxiliary circuits contained on-chip provide versatile potential applications needing a minimum of external components.
For example, an impedance converter is connected upstream of the AID converter to provide a high-impedance signal input,
in spite of the high input capacitance of the AID converter. The reference voltage for the AID converter is generated on-chip,
but both the ground ofthe circuit and the reference voltage are fed to pins, so that an external filter capacitor may be connected.
Further, the input is equippedwith switches which optionally provide operation with keyed clamping or peak clamping or
withoutclamping. Also the. D/A converter's reference voltage is generated on-Chip, and a gated amplifier is arranged at the
output of the DIA converter so that im external analog signal can be fed-in instead of the signal delivered by the D/A converter.
Separate clock inputs are provided for the AID converter and the D/A converter thus enabling the application of time
compression procedures.
All inputs and outputs are TTL compatible.

c8 SAMSUNG SEMICONDUCTOR 521

KSV3100A LINEAR INTEGRATED CIRCUIT

PIN DESCRIPTION
Pin No. Description Pin No. Description

1 No Connection 21 Analog Input AID Converter

2 Analog Output D/A Converter 22 Clamping Level Input
3 -5V Supply D/A Converter-Analog 23 Clamping Pulse Input
4 Digital Input Bit 9 (MSB) 24 Analog Ground AID Converter
5 Digital Input Bit 8 25 Reference Voltage AID Converter
6 Digital Input Bit 7 26 +5V Supply AID Converter-Digital
7 Digital Input Bit 6 27 Digital Output Bit 7 (MSB)
8 Digital Input Bit 5 28 Digital Output Bit 6 •
9 Digital Input Bit 4 29 Digital Output Bit 5
10 Digital Input Bit 3 30 Digi.talOutput Bit 4
11 Digital Input Bit 2 31 Digital Output Bit 3
.12 Digital Input Bit 1 32 Digital Output Bit 2
13 Digital Input Bit 0 (LSB) 33 Digital Output Bit 1
14 + 5V Supply D/A Converter-Analog-Digital 34 Digital Output Bit 0 (LSB)
15 Clock Input D/A Converter 35 Digital Ground AID Converter
16 GND D/A Conv. & Clock AID Converter 36 +5V Supply AID Converter-Analog
17 -5V Supply AID Converter-Analog 37 GND of Ref. Voltage AID Converter
18 Clock Input AID Converter 38 Extetnal Analog Input
19 +5V Supply AID Converter 39 Output Signal Switchover Input
20 Peak Clamping Enable Input 40 No Connection

RECOMMENDED OPERATING CIRCUIT

DlAOUT
EXT. SIGNAL

:V AGND

,t, DGND
+5V >-----{]I
DlACLOCK

+5V ~--t!~---=----qL___lP"-~+:!t;-----II--~..JA/D IN
",. o.47~F
KSV3100A KEY PULSE

-5V »-·4J"'~/yr---'4J/~Ifr---'\I""'¥-A...- ...<C +5V

910 lK 560
Fig. 2

c8 SAMSUNG SEMICONDUCTOR 522

KSV3100A LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristics Symbol Value Unit

Positive Supply Voltage Vee 6 V

Negative Supply Voltage Vee -6 V
Input Voltages (Digital) V, -0.5 - Vee +0.5 V
Input Voltages (Analog) V, -0.5 - Vee +0.5 V
Output Current Pin 2 10 ±10 mA
Ambient Operating Temperature Range
Storage Temperature Range
T.
Tstg
0-+70
-40 - +125
°C
°C .

RECOMMENDED OPERATING CONDITIONS

.
Characteristics Symbol Min Typ Max Unit

Positive Supply Voltage Vee 4.75 5 5.25 V

Negative Supply Voltage VeE -4.75 -5 -5.25 V
AID Converter
Analog Input Voltage V, 0 - 2 V
Input Frequency, Analog Input f, - - f c,/2 -
Clock Amplitude V18H 2.0 - Vee V
V18l 0 - 0.8 V
Conversion Rate f18 () - 20 MSPS'
Clock High Time (See Fig. 3) tH 15 - - ns
Clock Low Time (See Fig. 3) tl 35 - - ns
AID Output Voltage VOH 2.4 - Vee V
VOL 0 - 0.4 V
Clamping Level V22 -1 - +2 V
Clamping Pulse V23H . 2.0 - Vee V
V23L 0 - 0.8 V
Resistor of 20 to 6OKO
Activation of Peak Clamping - from Pin 20 to + 5V -
D/A Converter
Clock Amplitude V15H 2.0 - Vee V
V15L 0 - 0.8 V
Conversion Rate f15 0 - 20 MSPS'
Digital Input Voltage V'H 2.0 - Vee V
V'l 0 - 0.8 V
Analog Input Voltage at Pin 38 V3JJ -1 - +3 V
Output Signal Switch Over Input
for the D/A Converter Out V39 0 - 0.8 V
for the Ext. Signal (from Pin 38) Out V39 2 - Vee V

• MSPS (Mega Sample Per Second)

c8 SAMSUNG SEMICONDUCTOR 523

KSV3100A LINEAR INTEGRATED CIRCUIT·
ELECTRICAL CHARACTERISTIC.S Nee=5V, VEE= -5V, fI5 =20MHz, fIB = 2OMHz, Ta=25°C)

Characteristic Symbol Min Typ Max Unit

Current Consumption
lee - 90 120 mA
lEE - -SO -110 mA
Power Dissipation PTOT - - 1.2 W
Total Transfer Time A/D-D/A trOT See Fig. 3 -
AlQ Converter
Input Current Pin 21 II - 2 - pA
Input Capacitance Pin 21 CI - 10 - pF
Input Impedance ~In 21
at f= 1KHz ZI - 20 - MO
atf=10MHz ZI - 100 - KO
3dB Bandwidth of the Input Amp. - ~
50 - MHz
Keyed Clamping Active Level V23 2.0 - Vee V
On Resistance of the Clamping Switch
Between Pin 21 and 22
RON - 300 - Ohm

Input Current of the Clamping Level

Input Pin 22 N20=3V, V22 =2V)
122 - 150 - pA

Aperture Delay ( ® In Fig. 3) tAD - - 10 ns

Digital Output Delay ( ® In Fig. 3) toy - 25 - ns
Transfer Time ( ® in Fig. 3) tw One clock period -
Differential Non·Linearity - See "Ordering Information" -
Absolute Non-Linearity - - 1 - %
Number of Bits - - 8 - -
Code of the Digital Output Signal. - Binary -
Output CODE at the Input
with V21 =OV - 00000000 -
with V21 = V"" - 11111111 -
Internal Reference Voltage V25 1.8 2.0 2.2 V
D/A Converter
Output Impedance Pin 2 Zo - 15 - 0
Input Current Pin 38 (V3Jj'=2V) 110 - 0.6 - mA
Internal Reference Voltage Vre! 1.8 2.0 2.2 V
Input Resister Hold Time ((f)'in Fig. 3) tlH 6.0 - - ns
Input Resister Setup Time (®,in Fig. 3) tlH 20 - - ns
Differential Non-Linearity - See "Ordering Information" -
Absolute Non-linearity - - 1' - o/~
Number of Bits - - 10 - -
Code of the Digital Input Signal - Binary -
Output Signal at the Input
with 0 0 0 0 0 00000
with 1 1 1 1 1 1 1 11 1
V2
. V2
-
-
0
2
-- V
V
Settling Time ts - 50 - ns

c8 SAMSUNG SEMICONDUCTOR .524

 KSV3100A LINEAR INTEGRATED CIRCUIT

ORDERING INFORMATION
KSV3100A has four kind of version according to the accuracy bit (so called 'Precision') of D/A Converter, and their marking
• specifications are as follow; .

D/A Converter AID Converter

Device Package Temperature Range
Accurary Bit Dltt. Nonlinearity Dlff. Nonlinearity
KSV3100ACN·10 10 bit ± 1/2 LSB
KSV3100ACN·9 9 bit ±1 LSB
40 DIP 0- + 70°C ±1/2 LSB
KSV3100ACN-8 8 bit ±2 LSB
KSV3100ACN·7 7 but ±4 LSB

• The accuracy of AID Converter can be guaranteed as '8 bit' (differential nonlinearity = ± 1/2 LSB) regardless of th~
D/A Converter's accuracy.

TIMING DIAGRAM

AID
II
Converter
Analog
Input

Data Out

Clock DAC
(1) Sample
® Aperture Delay
®.Digital Output Delay
DIA
o Data Valid (after Sample (1)
Data In Converter ® Transfer Time AID
® Total Transfer Time AlD-
D/A with Common Clock
(j) Input Register Hold Time
Analog Output
® Input Register Setup Time

Fig. 3

c8 SAMSUNG SEMICONDUCTOR 525

KSV3100A LINEAR INTEGRATED CIRCUIT

INNER .CONFIGURATION OF THE CONNECTION PINS

The following figures schematically show the circuitry at the various pins.

+5V +5V

x
x
_*-~_-5V

.Fig. 4: Pin 2, Output ---4--t---+---o

_~ _ _ _ _ _--+-_ _-5V
Fig. 5: Pins 4 to 13, 15, 18, 23 and 39, Inputs

Fig. 6: Pins 20 and 22, Inputs Fig. 7: Pin 21, Input

+5V
+5V

x
x

---+-~--~~-u
---~--~~~-o
_ _ _ _ _ _ _ _ _ _ _~__-5V _ _ _ _ _ _ _ _-4-_- 5V

Fig. 8: Pin 25, Reference Voltage Pin Fig. 9: Pins 27 to 34, Outputs

c8SAMSUNG :SEMICONDUCTOR 526

KSV3100A LINEAR INTEGRATED CIRCUIT

+5V

Fig. 10: Pin 38, Input

x=protection diode

DESCRIPTION OF THE CONNECTIONS AND _THE SIGNALS

,
.,

Pin No. Description

Pin 1 No Connection
Pin 2 Analog Output D/A Converter
This pin whose diagram is shown in Fig. 4. is the output for the processed analog signal
either originating from the D/A converter or from the external analog input pi~ 38.
Pin 3 -5 Volt Supply D/A Converter. Analog
This pin gets the riegative supply for the analog part of the D/A converter.
Pin4to 13 Digital Inputs Bit 9 to Bit 0
This diagram of these pins is shown in Fig. 5. They are the inputs of the D/A converter and
not-used inputs should be connected to the ground.
Pin 14 +5 Volt Supply D/A Converter. Digital
This pin gets the positive supply for the digital part of the 'D/A converter..
Pin 15 Clock Input D/A Converter
This pin whose !liagram is shown in Fig. 5 must be supplied with the clock signal for the
D/A converter.
Pin 16 Ground CIA Converter and Clock AID Converter
This pin serves as ground pin for the D/A converter and for the clock of the AID converter.
Pin 17 -5 Volt Supply AID Converter. Analog
This pin is the negative supply pin for the analog part of the AID converter.
Pin 18 Clock Input AID Converter
The diagram of this pin is shown in Fig. 5. Pin 18 is supplied with the clock of the AID
converter.
Pin 19 +5 Volt Supply AID Converter
Via this pin the AID converter gets its positive supply.
Pin 20 Peak Clamping Enable Input
Via pin 20 whose diagram is shown in Fig. 6, the peak clamping facility can be enabled.

c8 SAMSUNG SEMICONDU~R 527

KSVJ100A LINEAR INTEGRATED CIRCUIT

DESCRIPTION OF THE CONNECTIONS AND THE SIGNALS (Continued)

Pin No. Description

Pin 21 Analog Input AID Converter

Fig. 7 is the diagram of this input. To pin 21 is applied the analog signal to be converted
into digital.
Pin 22 Clamping Level Input
Via this pin whose diagram is shown in Fig. 6, the input of the AID converter is supplied
with the desired clamping level.
Pin 23 ' Clamping Pulse Input
Fig. 5 is the diagram of this input. Pin 23 must be supplied with the key pulse if keyed
clamping is required.
Pin 24 , Analog Ground AID Converter
This pin serves as ground pin for the analog part of the AID converter.
Pin 25 Reference Voltage AID Converter
This pin whose diagram is shown in, Fig. S. is intended for connecting a decoupling
capacitor to the AID converter's reference voltage, the other 'end of this capacitor to pin 37.
Pin 26 +5 Volt Supply AID Converter, Digital
This pin is the positive supply pin for the digital part of the AID converter.
Pin 27 to 34 Digital Outputs Bit 7 to Bit 0
Fig. 9 shows the diagram of these outputs which supply the digitized analog signal in
parallel 8-bit code.
Pin 35 Digital Ground AID Converter
This pin is the ground connection for the digital part of the AID converter.
Pin 36 +5 Volt Supply AID Converter, Analog .
This pin is the pj>sitive supply pin for the analog part of the AID converter.
Pin 37 Ground of Reference Voltage AID Converter
.To this pin must be connected the ground end of the decoupling which is at pin 25.
Pin 36 External Analog Input
The diagram of this Input is shown in Fig. 10. Pin 38 serves for feeding an external analog
signal Into the output amplifier of the KSV3100A instead of the D/A-converted signal
orlginatirig from pin 4, to 13.
Pin 39 Output Signal Switchover Input
This pin whose diagram is shown in Fig. 5, is intended for enabling the external analog
signal fed to pin 38.
Pin 40 No Connection

c8 SAMSUNG SEMICO~DUCTOR 528

 KSV3100A LINEAR INTEGRATED CIRCUIT

APPENDIX: APPLICATION CIRCUITS

KSV3100~

DC Coupled
Video Signal

Fig. 11: Operation without clamping of the input signal'

Pin 20 (peak clamping enable input) should be opened, while pin 23 (clamping pulse input) remains at OV. The input
signal is applied to the analog input, pin 21, without coupling capacitor such that it lies between 0 and + 2V.
II
KSV3100A
Keyed
Clamping
___ ___ J

O.47W
+
Video Signal

]on -5V
Fig. 12: Operation with peak clamping
The input signal is clamped automatically to the negative peak value. Pin 20 is connected to + 5V via a 391<0 resistor,
and pin 22 (clamping level input) is connected, as desired, to zero or a voltage between -1 and + 2V. The input
signal is fed to pin 21 by way of a coupling capacitor, and no key pulse (clamping pulse) is needed.

c8SAMSUNG SEMICONDUCTOR 529

 KSV3100A LINEAR INTEGRATED CIRCUIT

KSV3100A
Keyed
Clamping

!ideo Signal

~
+5V

...--- 1K

910

. -5V

Fig. 13: Operation with keyed clamping

The input signal is applied to pin 21 through a coupling capacitor. Pin 20 must not be connected. While the input
signal is at the desired clamping level, an high-level is applied at the clamping pulse input, pin 23. By this means
the clamping switch in the KSV3100A connects the input with the clamping level at pin 22 and recharges the coupling
capacitor accordingly. The clamping level can be set to zero or, by means of an external voltage devider, to any
desired value between - 1 and + 2V~

c8 SAMSUNG SEMICONDUCTOR .530

 PRELIMINARY
KSV3110 LINEAR INTEGRATED CIRCUIT

HIGH·SPEED AJD·D/A CONVERTER

40 DIP
Samsung KSV3110, VLSI circuit in CI (Collector Implanted) technology
consists of a high-speed flash-type 8-bit AID converter and a high-speed
low-glitch 10-bit D/A converter designed as an weighted current
sources. Also, the various auxiliary circuits, as reference voltage
voltqge sources, pre-amplifier, input clamping circuit and feed-in output
amplifier are integrated on the single chip.
KSV3110 has been developed for use in all applications which call for
a high-speed A/D-D/A converter.
For instance, this VLSI circuit can be used to advantage to decode
television signals in Pay.:nt converters or for MAC converters used in
direct satellite broadcast.
Other promising applications can be seen in industrial electroniCS, e.g.
in conjunction with sign!!1 processing.
Although KSV311 0 was initially designed as high-speed codecs for the
video range, it can be used with equal benefits for lower frequencies,
even down to zero.

BLOCK DIAGRAM

KSV3110

Fig. 1

The auxiliary circuits contained on-chip provide versatile potential applications needing a minimum of external components.
For example, an impedance converter is connected upstream of the AID converter to provide a high-impedance signal input,
in spite of the high input capacitance of the AID converter. The reference voHage for the AID converter is generated on-chip,
but both the ground of the Circuit and the reference voHage are led to pins, so that an external filter capacitor may be connected.
Further, the input is equipped with switches which optionally provide operation with keyed clamping or peak clamping or
wijhout clamping. Also the D/A converter's reference voltage is generated on-chip, and a gated amplifier is arranged at the
output of the D/A converter so that an external analog signal can be fed-in instead of the signal delivered by the D/A converter.
. Separate clock inputs are provided for the AID converter and the D/A converter thus enabling the application of time
compression procedures.
All inputs and outputs are TIL compatible.

c8 SAMSUNG SEMICONDUCTOR 531

 PRELIMINARY
KSV3110 LINEAR INTEGRATED CIRCUIT

PIN DESCRIPTION
Pin No. Description Pin No. Description

1 Analog Output D/A Converter 21 Analog Input AID Converter

2 - 5V Supply D/A-Analog 22 Clamping Level Input
3 - 5V Supply D/A Converter-Digital 23 Clamping Pulse Input
4 Digital Input Bit 9 (MSB) 24 Analog Ground AID Converter
5. Digital Input Bit 8 25 Reference Voltage AID Converter
6 Digital Input Bit 7 26 +5V Supply AID Converter-Digital
7 Digital Input Bit 6 27 Digital Output Bit 7 (MSB)
8 Digital Input Bit 5 28 Digital Output Bit 6
9 Digital Input Bit 4 29 Digital Output Bit 5
10 Digital Input Bit 3 30 Digital Output Bit 4 .
11 Digital Input Bit 2 31 Digital Output Bit 3
12 Digital Input Bit 1 32 Digital Output Bit 2
13 Digital Input Bit 0 (LSB) 33 Digital Output Bit 1
14 + 5V Supply D/A Converter-Analog-Digital 34 Digital Output Bit 0 (LSB)
15 Clock Input D/A Converter 35 Digital Ground AID Converter
16 GND DIA Conv. & Clock AID Converter 36 +5V Supply AID Converter-Analog
17 -5V Supply AID Converter-Analog 37 GND of Ref. Voltage AID Converter
18 Clock Input AID Converter 38 External Analog Input
19 +5V Supply AID Converter 39 Output Signal Switchover Input
20 Peak Clamping Enable·lnput 40 + 5V Supply D/A-Analog

RECOMMENDED OPERATING CIRCUIT

o~OUT~--------------dml1~~~~~--------~+5V
-5v~--------~11
EXT. SIGNAL

D----_~+5V

D/AIN
~AGNo
,t, LlGNo

o~CWCKr-~>--------------a1

AID CLOCK

+5V :::~~~----~------~
39K
______~~--~+l·~---------t~----~~-'AlOIN
0.47.F
KSV3110 KEY PULSE

-5V~+5V
910 1K 560
Fig. 2

c8 SAMSUNG SEMICONDUCTOR 532

 PRELIMINARY
KSV3110 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristics Symbol Value Unit

Positive Supply Voltage Vee 6 V

Negative Supply Voltage VEE -6 V
Input Voltages (Digital) V, -0.51-1 Vee +0.5 V
Input Voltages (Analog) V, -0.51- 1Vee +0.5 V
Output Current Pin 2 10 ±10 mA
Ambient Operating Temperature Range T. 0-+70 DC
Storage Temperature Range Tstg -40 - +125 DC

RECOMMENDED OPERATING CONDITIONS

Characteristics Symbol Min Typ Max Unit

Positive Supply Voltage

Negative Supply Voltage
AID Converter
Analog Input Voltage
Vee
VEE

V,
4.75
-4.75

0 -
5
-5
5.25
-5.25

2
V
V

V
I
Input Frequency, Analog Input f, - - f o,l2 -
Clock Amplitude V18H 2.0 - Vee V
V'8L 0 - 0.8 V
Conversion Rate f'8 0 - 20 MSPS·
Clock High Time (See Fig. 3) tH 15 - - ns
Clock Low Time (See Fig. 3) tL 35 - - ns
AID Output Voltage VOH 2.4 - Vee V
VOL 0 - 0.4 V
Clamping Level V22 -1 - +2 V
Clamping Pulse V23H 2.0 - Vee V
V23L 0 - 0.8 V
Resistor of 20 to 6OKO
Activation of Peak Clamping -
from Pin 20 to + 5V
-
D/A Converter
Clock Amplitude V'5H 2.0 - Vee V
V'5L 0 - 0.8 V
Conversion Rate f'5 0 - 20 MSPS·
Digital Input Voltage V,H 2.0 - Vee V
V,L 0 - 0.8 V
Analog Input Voltage at Pin 38 Vas -1 - +3 V
Output Signal Switch Over Input
for the D/A Conver:ter Out V39 0 - 0.8 V
for the Ext. Signal (from Pin 38) Out V39 2 - Vee V

• MSPS (Mega Sample Per Second)

c8 SAMSUNG SEMICONDUCI*OR 533

)
PRELIMINARY
KSV3110 LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS (Vee =5V, V EE = -5V, f,5=20MHz, f,s=20MHz, Ta=25°Cj

Characteristic Symbol Min Typ Max . Unit

Current Consumption
Icc - 90 120 mA
lEE - -80 -110 mA
Power. Dissipation PTOT - - 1.2 W
Total Transter Time A/D·D/A trOT See Fig. 3 -
AID Converter
. Input Current Pin 21 I, - 2 - p.A
Input Capacitance Pin 21 C, - 10 - pF
Input Impedance Pin 21
at f=1KHz. 2, - 20 - MO
at f=10MHz 2, - 100 - KO
3dB Bandwidth of the Input Amp. - - 50 - MHz
Keyed Clamping Active Level V23 2.0 - Vee V
. On Resistance of the Clamping Switch
Between Pin' 21 and 22
RON - 300 - Ohm

Input Current of the Clamping Level

Input Pin 22
122 . - 200 - p.A

Aperture Delay ( ® in Fig. 3) tAD - - 10 ns

Digital Output Delay ( ® in Fig. 3) tov - 18 - ns
Transfer Time ( ® in Fig. 3) tw One clock period -
Differential Non·Linearity - See "Ordering Information" -
Absolute Non-Linearity - - 1 - %
Number of Bits - .- 8 - -
Code of the Digital Output Signal - Binary -
Output CODE at the Input
with V2; =OV - 00000000 -
with V2, = Vre, - 11111111 -
Internal Reference Voltage V25 1.8 2.0 2.2 V
D/A Converter
Output Impedance Pin 2 20 - 15 - 0
Input Current Pin 38 110 - 2 - p.A·
Internal Reference Voltage Vre, 1.8 2.0 2.2 V
Input Resister Hold Time ( (fJ in Fig. 3) t'H 6.0 - - ns
Input Resister Setup Time (ill in Fig. 3) t'H 20 - - ns
Differential Non-Linearity - See "Ordering Information" -
Absolute Non-Linearity - - 1 - %
Number of Bits - - 10 -'- -
Code of the Digital Input Signal - Binary -
Output Signal at the Input
with 00000 00000 V2 - 0 - V
with 1 1 1 1 1 1 1 1 1 1 V2 - 2 - V

c8 SAMSUNG SEMICONDUCTOR. 534

 PRELIMINARY
KSV3110 LINEAR INTEGRATED CIRCUIT

ORDERING INFORMATION
KSV3110 has four kind of version according to the accuracy bit (so called 'Precision') of D/A Converter, and their marking
specifications are as follow;

DIA Converter AID Converter

Device Package Temperature Range
Accurary Bit Dltt, Nonlinearity Dltt. Nonlinearity

KSV,3110CN-10 10 bit ± 1/2 LSB

KSV3110CN·9 9 bit' ±1 LSB
40 DIP 0- +70·C ±1/2 LSB
KSV3110CN-8 8 bit ±2 LSB
KSV3110CN·7 7 but ±4 LSB
• The accuracy of A/D Converter can be guaranteed as '8 bit' (differential nonlinearity = ± 1/2 LSB) regardless of the
D/A Converter's accuracy.

TIMING. DIAGRAM

Clock ADC

AID
Converter
II
Analog
Input

Data Qut

Clock DAC
CD Sample
CD Aperture Delay
® Digital Output Delay
DIA
® Data Valid (after Sample CD)
Data In Converter ® Transfer Time AID
® Total Transfer Time AID·
D/A with Common Clock
CD Input Register Hold Time
Analog Qutpu.t
® Input Register Setup Time

Fig. 3

c8 SAMSUNG SEMICQNDUcroR 535·

 PRELIMINARY
KSV3110 LINEAR INTEGRATED CIRCUIT

INNER CONFIGURATION OF THE CONNECTION PINS

The following figures schematically show the circuitry at the various pins.

+sv +5V

x
x
_*"----+-_ -sv
Fig. 4: Pin 1, Output -----+--f--.+-..,...O

-5V
200--_"'\1\1\.--.--;
Fig. ·5: Pins 4 to 13, 15, 18, 23 and 39, Inputs
22G--+--.r--4----j-- -t-------'

Fig. 6: Pins 20 and 22, Inputs Fig. 7: Pin 21, Input

+SV
+sv

--+-~--+-4--0
---~-~~+-~-o
_ _ _ _ _ _ _ _-+-_-sv _ _ _-\-_ _ _~~-5V

Fig. 8: Pin 25, Reference Voltage Pin Fig. 9: Pins 27 to 34, Outputs

ciS SAMSUNG SEMICONDUCTOR 536

 PRELIMINARY
KSV3110 LINEAR INTEGRATED CIRCUIT

Fig. 10: Pin 38, Input

x =protection diode

DESCRIPTION OF THE CONNECTIONS AND THE SIGNALS

Pin No.
Pin 1 Analog Output D/A Converter
Description

This pin whose diagram is shown in Fig. 4, is the output for the processed analog signal
II
either originating fro,!, the D/A converter or from the external.analog input pin 38.
Pin 2 - 5 Volt Supply D/A Converter, Analog
This pin gets the negative supply for the analog part of the D/A converter
Pin 3 - 5 Volt Supply D/A Convetter, Digital
This pin gets the negative supply for the digital part of the D/A converter.
Pin 4to 13 Digital Inputs Bit 9 to Bit 0
This diagram of these pins i~ shown in Fig. 5. They are the inputs of the D/A converter and
not·used inputs should be connected to the ground.
Pin 14 +5 Volt Supply D/A Converter, Digital
This pin gets the poSitive supply for the digital part of the D/A converter.
Pin 15 Clock Input D/A Converter
This pin whose diagram is shown in Fig. 5 must be supplied with the clock signal for the
D/A converter.
Pin 16 Ground D/A Converter and Clock AID Converter
This pin serves as ground pin for the D/A converter and for the clock of the AID converter.
Pin 17 -5 Volt Supply AID Converter, Analog
This pin is the negative supply pin for the analog part of the AID converter.
Pin 18 Clock Input AID Converter
The diagram of this pin is shown in Fig. 5. Pin 18 is supplied with the ciock of the AID
converter.
Pin 19 +5 Volt Supply AID Converter
Via this pin the AID converter gets its positive supply.
Pin 20 Peak Clamping Enable Input
Via pin 20 whose diagram is shown in Fig. 6, the peak clamping facility can be enabled.

c8SAMSUNG SEMICONDUCTOR 537

 PRELIMINARY
KSV3110 LINEAR INTEGRATED CIRCUIT

DESCRIPTION OF THE CONNECTIONS AND THE SIGNALS (Continued)

Pin No. Description

Pin 21 Analog Input AID Converter

Fig. 7 is the diagram of this input. To pin 21 is applied the analog signal to be converted
into digital.
Pin 22 Clamping Level Input
Via this pin whose diagram is shown in Fig. 6, the input of the AID converter is supplied
with the desired clamping level.
. Pin 23 Clamping Pulse Input
Fig. 5 is the diagram of this input. Pin 23 must be supplied with the key pulse if keyed
clamping is required. .
Pin 24 Analog Ground AID Converter
This pin serves as ground pin for the analog part of the AID converter.
Pin 25 Reference Voltage AID Converter
This pin whose diagram is shown in Fig. 8, is intended for connecting a decoupling
capacitor to the AID converter's refe(ence voltage, the otlier end of this capacitor to pin ~.
Pin 26 +5 Volt Supply AID Converter, Digital
This pin is the positive supply pin for the digital part of the AID converter.
Pin 27 to 34 Digital Outputs Bit 7 to Bit 0
Fig. 9 shows the diagram of these outputs which supply the digitized analog signal in
parallel 8-bit code.
Pin 35 Digital Ground AID Converter
This pin is the ground connection for the digital part of the AID converter.
Pin 36 +5 Volt Supply AID Converter, Analog
This pin is the positive supply pin for the analog part of the AID converter.
Pin 37 Ground of Reference Voltage AID Converter
To this pin must be connected the ground end of the decoupling which is at pin 25.
Pin 38 External Analog Input
The diagram of this input is shown in Fig. 10. Pin 38 serves for feeding an external analog
signal into the output amplifier of the KSV3110 instead of the D/A-converted signal
originating from pin 4 to 13.
Pin 39 ·Output Signal Switchover Input
This pin whose diagram is shown in Fig. 5, is intended for enabling the external analog
signal fed to pin 38.
Pin 40 + 5 Volt Supply D/A Converter, Analog
This pin is the negative supply pin for the analog parts of the D/A converter

c8 SAMSUNG SEMICONDUCTOR 538

 PRELIMINARY
KSV3110 LINEAR INTEGRATED CIRCUIT

APPENDIX: APPLICATION CIRCUITS

KSV3110

Keyed
Clamping
______ J

OCCoupled
Video Signal

Fig. 11: Operation without clamping of the input signal

Pin 20 (peak clamping enable input) should be opened, while pin 23 (clamping pulse input) remains at OV. The input
signal is applied to the analog input, pin 21, without coupling capacitor such that it lies between 0 and + 2V.
II
KSV3110

+5V

}on -5V
Fig. 12: Operation with peak clamping
The input signal is clamped automatically to the negative peak value. Pin 20 is connected to + 5V via a 391<0 resistor,
and pin 22 (clamping level input) is connected, as deSired, to zero or a voltage between -1 and + 2V. The input
signal is fed to pin 21 by way of a coupling capacitor, and no key pulse (clamping pulse) is needed.

c8 SAMSUNG SEMICONDUCTOR 539

 PRELIMINARY
KSV3110 LINEAR INTEGRATED CIRCUIT

KSV3110

Keyed
Clamping

(ideo Signal

60 +SV

[
f---- 1K

910

-SV

Fig. 13:.0peralion wilh keyed clamping

The input signal is applied 10 pin 21 through a coupling capacitor. Pin 20 must not be connected. While the input
signal is at the desired clamping level, an high-level is applied at the clamping pulse input, pin 23. By this means
the clamping switch in the KSV311 0 connects the input with the clamping level at pin 22 and recharges the-coupling
capacitor accordingly. The clamping level can be sel to zero or, by means of an external voltage devider, to any
desired value between ~ 1 and + 2V.

c8 SAMSUNG SEMICONDUCTOR 540

 PRELIMINARY
KSV3208 LINEAR INTEGRATED CIRCUIT

HIGH·SPEED AID CONVERTER 28 DIP

Samsung KSV3208, VLSI circuit in CI (Collector Implanted) technology,

consists of a high-speed flash-type 8-bit AID converter. Also, the various
auxiliary circuits, as reference voltage sources, pre-amplifier, input
clamping circuits are integrated on the single chip. .
KSV3208 has been developed for use'in all applications which call for
a high-speed AID converter.
For instance, this VLSI circuit can be used to advantage to decode
television signals in Pay-TV converters or for MAC converters used in
direct satellite broadcast.' ,
Other promising applications can be seen in industrial electronics, e.g.
in conjunction with signal processing.
Although KSV3208 was initially designed as high-speed converter for
video frequency 'range, it can be used with equal benefits for lower
frequencies, even down to zero.

ORDERING INFORMATION

BLOCK DIAGRAM II
Voltage
Reference
KSV;i208

VIDEO Flash
SIGNAL AID
Converter
8 Bits

Clock

~----~--------------~17~------------~------------~
Fig. 1

The auxiliary circuits contained on-chip provide versatile potential applications needing a minimum of external
components. For example, an impedance converter is connected upstream of the AID converter to provide a high-
impedance signal input in spite of the high input capacitance of the AID converter. The reference voltage for the
AID converter is generated on-chip, but both the ground of the circuit and the reference voltage are fed to pins,
so that an external filter capaCitor may be connected.
Further, the input is equipped with switches which optionally provide operation with keyed clamping of peak
clamping or without clamping.
All inputs and outputs are TTL compatible.

c8 SAMSUNG SEMICONDUCTOR 541

 PRELIMINARY
KSV3208 LINEAR INTEGRATED CIRCUIT

PIN DESCRIPTION
Pin No. Description

1 GND of Reference Resistor String

2 + 5V Supply of ECl Logic Part, Digital
3 GND of ECl to TIL Translator Part, Digital
4 Digital Output Bit 0 (lSB)
5 Digital Output Bit 1
6 Digital Output Bit 2
7 Digital Output Bit 3
8 Digital OutPlJt Bit 4
9 Digital Output Bit 5
10 Digital Output Bit 6
11 Digital Output Bit 7 (MSB)
12 + 5V Supply of TIL Output Part, Digital
13 No Connection
14 GND of ECl logic Part, Digital
15 GND of Input Stage, Analog
16 + VREF , Reference Voltage Point of Resistor String
17 Clock Input
18 No Connection
19 + 5V Supply of Input Stage, Analog
20 - 5V Input Stage, Analog
21 Clamping Pulse Input
22 Clamping level Input
23 Analog Signal Input
24 Peak Clamp Enable Input
25 No Connection
26 No Connection
27
28
GND of ECl Clock Part, Digital
- 5V Supply of ECl logic Part, Digital .
R.ECOMMENDED OPERATING CIRCtJlT

28[J-------<c::: - 5V
+5V
+5V
DO PEAK CLAMP
01 f - - ' W I r - - - < + 5V 560
02 f---<=:--JAlO INPUT
~AGNO OUT
03 u-----------~1K CLAMPING PULSE
04 LJ-----..:::::::=::1GATE PULSE

rh OGNO
05
06
[J----<+5V
[J----<-5V
910

07
-5V
+5V LJ-----..C:::JCLOCK
NC

Fig. 2

c8 SAMSUNG SEMICONDUCTOR 542

 PRELIMINARY
KSV3208 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristics Symbol Value Unit

Positive Supply Voltage Vee 6 V

Negative Supply Voltage VEE -6 V
Input Voltages (Digital) V, -0.5 - Vee +0.5 V
Input Voltages (Analog) V, -0.5 - Vee +0.5 V
Ambient" Operating Temperature Range T. 0- +70 DC
Storage Temperature Range T" g -40 - + 125 DC

RECOMMENDED OPERATING CONDITIONS

Characteristics Symbol Min Typ Max Unit

Positive Supply Voltage Vee 4.75 5 5.25 V

Negative Supply Voltage VEE -4.75 -5 -5.25 V
Analog Input Voltage . V, 0 - 2 V
Input Frequency. Analog Input
Clock Amplitude

Conversion Rate
Clock High Time (See Fig. 3)
I,
V"H
V"L
I"
tH
-
2.0
0
0
15
-
-
-
-
- -
1,,/2
Vee
0.8
20
-
V
V
MSPS'
I1s
I
Clock Low Time (See Fig. 3) tL 35 - - ns
Clamping Level V22 -1 - +2 V
Clamping Pulse (High) V21H 2.0 - Vee V
Clamping Pulse (Low) V21L 0 - 0.8 V
Resistor 01 20 to 60Kohm
Activation 01 P~ak Clamping - lrom Pin 24 to + 5V
-
• MSPS (Mega Sample Per Second)

ciS SAMSUNG SEMICONDUCTOR 543

 PRELIMINARY
KSV3208 LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS·
(Vcc=5V, VEE =5V, f17= 20MHz, Ta=25 a C)

Characteristics Symbol Min Typ Max Unit

Current Consumption
Icc - - 100 mA
lEE - - -SO mA
Power Dissipation P'o' - - 0.9 W
Total Transter Time AID T,o' See Fig. 3 -
Input Current Pin 23 I, - 1 - p.A
Input Capacitance Pin 23. C, - 10 - pF
3dB Bandwidth of the Input Amp. - - 50 - MHz
Keyed Clamping Active Level V21 2.0 - Vee V
On Resistance of the Clamping Switch
Between Pin 23 and 23
RON - 300 - Ohm

Input Current of the Clamping Level

Input Pin 22
122 - 200 - p.A

Aperture Delay (® in Fig. 3) tSd - - 10 ns

Digital Output Delay (0 in Fig. 3) td, - - 14 ns
Transfer Time (® in Fig. 3) T'T On Clock Period -
Differential Non-Linearity - - - ± 1/2 LSB
Absolute Non-Linearity - 1 - %
Number of Bits - - 8 - -
Code of the Digital Output Signal - Binary -
Output CODE at the Inpuf ,
with V23 =OV - 00000000 -
with V23 = Vref - 11111111 -
Internal Reference Voltage Vref 1.8 2.0 2.2 V

TIMING DIAGRAM

Clock ADC

G) Sample
Analog ® Aperture Delay
Input
o Digital Output Delay
Data Out o Data Valid (after Sample G))
® Transfer Time AID

Fig. 3

c8 SAMSUNG SEMICONDUCTOR 544

 PRELIMINARY
KSV3208 LINEAR INTEGRATED CIRCUIT

INNER CONFIGURATION OF THE CONNECTION PINS

The following figures schematically show the circuitry at the various pins.

_ _ _~___,.---+5V
- - - - - r - - - - , . . - - - , . . - + 5V

x x

--~~-~-r-O
_ _ _ _ _ _ _>---5V
- - - - - -........--5V

Fig. 4: Pin 4 to 11, Outputs Fig. 5: Pin 16, Reference Voltage

---~-r---r---.---+5V
--------,..---.------.-+5V II
22 o---+---r--+---+-+-~--'
'--+-_ _ _+-_~~nA~:ING

x --~__+-4---0

x
--+-------'----5V

Fig. 6: Pin 17, 21 Input

--+----+------~_'____''__ _ _ 5V

- - - - - - r - - - r - - - + 5V Fig. 7 Pins 22 and 24, Inputs

CLAMPING x: Protection Diode

PIN 23 0--.--+--1

4--+--~-+---O

-~--~--'--------5V

Fig. 8: Pin 23, Input

c8 SAMSUNG SEMICONDUCTOR 545

 PRELIMINARY
KSV3208 LINEAR INTEGRATED CIRCUIT

DESCRIPTION OF THE CONNECTIONS AND THE SIGNALS

Pin No. Description
Pin 1 GND of Reference Resistor String
This pin must be connected to the ground of the decoupling capacitor
whitch is at pin 16.
Pin 2 + 5 Volt Supply of ECl logic Part, Digital
This pin is the positive supply pin for the ECl logic part.
Pin 3 Digital Ground of ECl to TTL Translator Pat1.
This pin is the digital ground connection for the TTL output stage
where ECl level is translated to TTL level.
Pin 4 to Pin 11 Digital Outputs Bit 0 to Bit 7.
Fig. 4 shows the diagram of there outputs which supply the digitized
analog signal in parallel 8·bit code.
Pin 12 + 5 Volt Supply off TTL Output Part, Digital
This pin is the digital positive supply pin for the TTL output stage
, where ECl level Is translated to TTL level.
Pin 14 Digital GND of ECl logic Part
This pin serves as the digital ground for the ECl logic part.
Pin 15 Analog GND of Input Stage
This pin serves as the analog ground for the input stage;
buffer amp, bandgap reference, clamp block.
Pin 16 + VAEF, Reference Voltage Point of Resistor String
Tl)is pin whose diagram is shown Is Fig. 5, is intended for connecting a
decoupling capacitor to the AID converter's reference voltage. The other end
of this capacitor is connected to pin 1. (GND 9f Ref.erence Resistor String).
Pin 17 Clock Input
The diagram of this pin is shown in Fig. 6.
Pin 17 is supplied with the clock of AID converter.
Pin 1·9 + 5 Volt Supply of Input Stage, Analog
This pin ,is the analog positive supply pin for the input stage;
bandgap reference.
Pin 20 -5 Volt Supply of Input Stage, Analog
This pin 'is the analog negative supply pin for the input stage;
buffer amp, bandgap reference, clamp block.
Pin 21 Clamping Pulse Input
Fig. 6 is diagram of this pin. Pin 21 must be supplied with the key pulse
if keyed clamping ,is required.
Pin 22 Clamping level Input
Via this pi!) whose diagram is shown is Fig. 7, the input of the AID
converter is· supplied with the desired clamping level.
Piri'23 Analog Signal Input
Fig. 8 is the diagram of this input. To pin 23 is applied the analog signal
to be converted into digital.
Pin 24 Peak Clamp Enable Input
Via pin 24 whose diagram is shown in Fig. 7, 'the peak clamping facilities
can be enable. "
Pin 27 Digital GND of ECl Clock Part
This pin serves as the digital ground for the ECl clock block.
Pin 28 - 5 Volt Supply of ECl logic Part, Digital
This pin is the digital negative supply for the ECl logic part.

c8 SAMSU~G SEMICONDUCTOR 546

 PRELIMINARY
KSV3208 LINEAR INTEGRATED CIRCUIT

APPENDIX: APPLICATION CIRCUITS

Keyed Voltage
Clamping I Reference
I
_.J

Flash
DC COUPLED AID
Video Signal· Converter
8 Bits

Fig. 9: Operation without clamping of the input signal

Pin 24 (peak clamping enable input) should be opened, while pin 21 (clamping pulse input) remains at OV.
The input signal is applied to the analog input, pin 23, without coupling capacitor such that it lies between
o and +2V
I
Keyed Voltage
r-+-_c_la_mping Reference
_...1

O.47~
+ Flash
AID
Converter
8 Bits

+5V

r 10n
-5V
Fig. 10: Operation with peak clamping
The input signal is clamped automatically to the negative peak value. Pin 24 is connected to + 5V via a
39Kohm resistor and pin 22 (clamping level input) is connected, as desired, to zero or a voltage betgween
-1 and + 2V. The input signal is fed to pin 23 by way of a coupling capacitor, and no key pulse (clamping
pulse) is needed.

c8 SAMSUNG SEMICONDUCTOR 547

 PRELIMINARY
KSV3208 LINEAR INTEGRATED CIRCUIT

Keyed I Vollage
Clamping I . Reference
I
__ JI

Flash
AID
Converter
8 Bils

-5V

Fig. 11: Operation with keyed clamping

The input signal is applied to pin 23 through a coupling capacitor. Pin 24 must not be connected. While
the input signal is at the desired clamping level, an high-level is applied at the clamping pulse input, pin
21. By this means the clamping switch in the KSV3208 connects the input with the clamping level at pin
22 and recharges the coupling capaCitor accordingly. The clamping level can be set to zero or, by means
of an external voltage devider, to any desired value between -1 and + 2V.

c8 SAMSUNG SEMICONDUCTOR 548

KAD0808/KAD0809 CMOS INTEGRATED CIRCUIT

. 8·BIT I'P·COMPATIBLE AID CONVERTERS

28 DlP
WITH 8·CHANNEL MULTIPLEXER
The KAD0808/KAD0809 Analog to Digital converter is a monolithic
CMOS device with an 8-bit resolution, 8-channel input multiplexer and
microprocessor compatible control logic. It uses successive
approximation as the conversion technique.
The design of the KAD0808/KAD0809 has been optimized by
incorporating the most desirable aspects of several AID conversion
techniques. The KAD0808/KAD0809 offers high speed, high accuracy,
minimal temperature dependence, excellent long-term accuracy and
repeatability, and consumes minimal power.

FEATURES
• Total unadjusted error- :!: 1/2 LSB or :!: 1 LSB
• Resolution-8-bits
• Conversion time-1001'S

I
• No missing codes
• Latched TRI-STATE output·
• Easy interface to all microprocessors, or operates "stand alone"
• Single supply-S VDe .
• 8-channel multiplexer with latched control logic'
• Outputs meet TTL voltage level specifications
• OV to SV analog input voltage range with ORDERING INFORMATION
single SV supply
• No zero or full-scale adjust required
Device Package Temperature Range Dlff. Nonlinearity
• Standard 28·pin DIP package
KAD0808IN :!:1/2 LSB
28 DI~ - 40·C - + 85·C
KAD0809IN :!:3/4 LSB
BLOCK DIAGRAM

r:-------
I 8·BIT AID ,----'---
I
I
'i==:;---O
I-
END OF CONVERSION
(EOC)
I
I
8 CHANNELS I
8· ANALOG MULTIPLEXING
INPUTS ANALOG /----f-l
SWITCHES

30BIT {
ADDRESS 0- ADDRESS
LATCH AND
ADDRESS DECODER
LATCH ENABLE
(ALE)

11
Vee GND REF(+)
I
IL. _ _ _ _ _ _ _ _ _ _ ...JI
REF(-)
OUTPUT (OE)
ENABLE

=8 SAMSUNG SEMICONDUCTOR 549

KAD0808IKAD0809 CMOS INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS(Note·1 & 2)

Characteristic Symbol Value Unit

Supply Voltage (Note 3) Vee 6.5 V

Voltage at Any Pin Except Control Inputs V, -0.3V - (Vcc+0.3V) V
Voltage at Control Inputs V, -0.3V - +15V V
Package Dissipation at Ta= 25·C Po 875 mW
Operating Temperature Top, - 40·C - + 85·C ·C .
Storage Temperature Range T.tg -65·C - + 125·C ·C

ELECTRICAL CHARACTERISTICS
Converter Specifications: Vee=5 VOC=V ..fl +), V..fl_)=GND, Tf =T,=20ns and IClK = 640KHz unless otherwise
stated.

Characteristic Symbol 'rest Conditions· Min :ryp Max Unit

KAD0808
Total Unadjusted Error 25·C - - ±1/2 LSB
(Note 5) -40·C - 85·C - - ±3/4 LSB
KAD0809 O·C - 70·C - - ±1 LSB
. Total Unadjusted Error
+12. LSB
(Note 5) -40·C. - 85·C - - - 4
Input Resistance Rref From. Rel( + ) to Ref( -) 1.0 2.5 - KG
Analog Input Voltage Range Y'n (Note 4) V( +) or V(-) GND-0.10 - Vee +0.10 V
Comparator Input Current Ion Ic = 640KHz, (Note 6) -2 ±0.5 2 p.A
Analog Multiplexer
Vcc =5V, V,N =5V,.
OFF Channel Leakage Current 10FFI+) Ta=25·C - 10 200 nA

Vee = 5V, Y,N = 0,

OFF Channel Leakage Current 10FF(_)
Ta=25·C
-200 -10 - nA

Control Inputs
Logical "1" Input Voltage V,H Vee- 1.5 - Vcc V
Logical "0" Input Voltage V,l 0 - 0.4 V
Supply Current Icc fClK = 640KHz - 0.3 3.0 mA
Logical "1" Output Voltage VOH 10= -360p.A Vee-0.4 - Vee V
Logical "0" Output Voltage VOL lo=1.6mA 0 - 0.45 V
Logical "0" Output Voltage EOC VOUT(O) lo=1.2mA 0 - 0.45 V

TRI-STATE Output Current lOUT

.Vo=5V - - 3 p.A
Vo=O -3 - - p.A

c8 SAMSUNG SEMICONDUcrOR 550

KAD0808/KAD0809 CMOS INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS
Timing Specifications VCC=V re'I+I=5V, Vre'I_I=GND, t,=t,=20ns and Ta=25"C unless otherwise noted.

Characteristic Symbol Test Conditions Min Typ Ma~ Unit

Minimum Start Pulse Width tws (Figure 5) - 100 200 ns

Minimum ALE Pulse Width tWAlE (Figure 5) - 100 200 ns
Minimum Address Set-Up Time t. (Figure 5) - 25 50 ns
Minimum Address Hold Time t. (Figure 5) - 25 50 ns
Analog MUX Delay Time
From ALE
td Rs = on (Figure 5) - 1 2.5 ",S

OE Control to a Logic State tH10 tHO Cl = 50pF, Rl= 10K (Figure 8) - 125 250, ns
OE Control to Hi-Z t'H, tOH Cl = 10pF, Rl = 10K (Figure 8) - 125 250 ns
Conversion Time tCON f c = 640KHz, (Figure 5) 90 100 116 ",S
Clock Frequency felK 10 640 1280 KHz
Input Capacitance C'N At Control Inputs - 10 15 pF
TRI-STATE Output Capacitance

Note 1:
Note 2:
Note 3:
COUT At TRI-STATE Outputs - 10

Absolute maximum ratings are those values beyond which the life of the device may be impaired.
All voltages are measured with respect to GND, unless otherwise specified.
A zener diode exists, Internally, from Vee to GND and has a typical breakdown voltage of 7 Voe.
15 pF

I
Note 4: Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages
one diode drop below ground or one diode drop greater than the Vee supply. The spec allows 100mV
forward bias of either diode. This means that as long as the analog V,N does not exceed the supply voltage
by more than 100mV, the output code Will, be correct. To achieve an absolute OVoe to 5V oc input voltage
range will therefore require a minimum supply voltage 4.900 Voe over temperature variations, initial
tolerance and loading.
Note 5: Total unadjusted error includes offset, full-scale, linearity,:and multiplexer errors. See Figure 3. None 'of those
AIDs requires a zero or full-scale adjust. However, if an all zero code is desired for an analog input other
than O.OV, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference voltages
can be adjusted to achieve this. See Figure 13. '
Nole 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current
varies directly with clock frequency and lias little temperature dependence (Figure 6).

c8 SAMSUNG SEMICONDUCTOR 551

KAD0808lKAD0809 CMOS INTEGRATED CIRCUIT

FUNCTIONAL DESCRIPTION
Multiplexer. The device contains an a·channel single·
ended analog signal multiplexer. A particular input Selected Address Line
channel is selected by using the address decoder. Analog Channel C B A
Table 1 shows the input states for the address lines INO L L L
to select any channel. The address is latched into IN1 L L H
the decoder on the low·to·high transition of the address IN2 L H L
latch enable signal. IN3 L H H
IN4 H L L
INS H L H
IN6 H H L
CONVERTER CHARACTERISTICS IN7 H H H
The Converter
The heart of this single chip data acquisition system is its a·bit analog-to-digitlll converter. The converter is designed
to give fast, accurate, and repeatable conversions over a wide range of temperatures. The converter is partitioned
into 3 major sections: the 256R ladder network, the successive approximation register, and the comparator. The
converter's digital outputs are positive true. '
The 256R ladder network approach (Figure 1) was chosen over the conventional R/2R ladder because of its
inherent monotonicity, which guarantees no missing digital codes. Monotonicity is particularly important in closed
loop feedback control systems. A non-monotonic relationship can cause oscillations that will be cata!!trophic for
the system. Additionally, the 256R network does not cause load variations on the reference voltage.
The bottom resistor and the top resistor of the ladder network in Figure 1 are not the same value as the remainder
of the network. The difference in these resistors causes the output characteristic to be symmetrical with the zero
and full·scale pOints of the transfer curve. The first output transition occurs wh'en the analQg signal has reached
+ 1/2 LSB and succeeding output transitions occur every 1 LSB later up to full-scale.
The successive approximation register (SAR) performs a iterations to approximate the input voltage. For any SAR
type converter, n-iterations are required for an n-bit converter. Figure 2 shows a typical example of a 3-bit
converter. In the KADOaOa, KADOa09 the approximation technique is extended to a bits using the 256R network.

CONTROLS FROM S.A,A.

~ ______~A~______~\
REF(+)

.
: 256R

R
TO
COMPARATOR
INPUT

112~~
REF(-)
Fig_ 1 Resistor Ladder and Switch Tree

c8 SA~SUNG SEMICONDUCTOR 552

KAD0808/KAD0809 CMOS INTEGRATED CIRCUIT

FUNCTIONAL DESCRIPTION (Continued)-

The AID converter's successive approximation register (SAR) is reset on the positive edge of the start conversion
(SC) pulse. The conversion is begun on the falling edge of the start conversion pulse. A conversion in process
will be interrupted by receipt of a new start conversion pulse. Continuous conversion may be accomplished by
tying the end-of-conversion (EOC) output to the SC input. If used in this mode, an external start conversion pulse
should be applied after power up. End-of-conversion will go low between 0 and 8 clock pulses after the rising edge
of start conversion.
The most important section of the AID converter is the comparator. It is this section which Is responsible for the
ultimate accuracy of the entire converter. It is also the comparator drift which has the greatest influence on the
repeatability of the device. A chopper-stabilized comparator provides the most effective method of satisfying all
the converter requirements.
The chopper-stabilized comparator converts the DC input signal into an AC signal. This signal is then fed throught
a high gain AC amplifier and has the DC level restored. This technique limits the drift component of the amplifier
since the drift is a DC component which is not passed by the AC amplifier. This makes the entire AID converter
extremely insensitive to temperature, long term drift and input offset errors.
Figure 4 shows a typical error curve for the KAD0808.

w
o
111

110
101
I-- FULL-SCALE
-. J ERROR =112 LSB
w
8
111
110

101
+ 112 LSB
TOTAL ~
UNADJUSTED ~.
INFINITE RESOLUTION
PERFECT CONVERTER I
S Q ERROR i
'3 100 ~ 100
~ 011 '3011
o o
~ 010 ~ 010 -1/2 LSB
-QUANTIZATION
001 001 ERROR
000 V,N 000 " - ' - - - - - - - - - - - - V , N
0/8 1/8 2/8 3/8 4/8 5/8 6/8 7/8 0/8 1/8 218 3/8 4/8 5/8 618 7/8
V,N AS FRACTION OF FULL·SCALE V,N AS FRACTION OF FULL-SCALE

Fig. 2 3-Blt AID Transfer Curve Flg_ 3 3-Blt AID Absolute Accuracy Curve

REFERENCE LINE

_ QUAN;~~~~ {IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII111111111111111111111111111111111111111111111111111111111111111111111111
INPUT OV FULL
VOLTAGE - SCALE

Flg_ 4 Typical Error Curve

c8 SAMSUNG SEMICONDUCTOR 553

KAD0808IKAD0809 CMOS INTEGRATED CIRCUIT

PIN CONFIGURATION
Dual-In-Line Package

IN2
INl
INO
ADD A
ADD B
ADDC
KAD0808 ALE
2-' KAD0809 2-' MSB
OUTPUT
ENABLE 2-'
2- 3
2-'
2- 8 LSB
REF(-)
2-'

TOP VIEW

TIMING DIAGRAM

CLOCK

START 50%
,--, 50%
~ \

ALE 5O'lor~
----' twALE
-~ ~LE ADDRESS "
ADDRESS 5O'~ 50%
•
\
ts - f-- th

ANALOG V V
INPUT
- Sl/:..,
LSB
STABLE

COMPARATOR'
INPUT
(INTERNAL MODE) I I
f-- td---j

OUTPUT
ENABLE \ / L
EOC

- tEoe j
tCON
/50%

OUTPUT -------:...------.!~!:~!!.:.-----------------_{..._____.JL
r
Fig_ 5

c8 SAMSUNG SEMICONDUCTOR . 554

KAD0808/KAD0809 CMOS INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS

1.5...---,..-----,-,..---,..------..

•.S f---f---f--nf--;.t7q£'__j
~
~ .f-----f---~~----r---'__j

I-O'51-~';£Hf.L--r-----r------l

3.75 °OL---,.~~-~2~~--~3.=75--~
V.dVl

Fig. 6 Comparator liN VS VIN (Vee = VAEF = SV) Fig. 7 Multiplexer RON vs VIN (Vee = VAEF = SV)

TRI·STATE TEST CIRCUITS AND TIMING DIAGRAMS

Vee
Vee
1'1....._ __
II
90%
OUTPUT
ENABLE 50%
10%
GND--~~'-----
1--...-----<>

VOH~% IH'!,

OUTPUT ~ ___....J/5O%
GND------------~

IOH,IHO

Vee Vee

10K

OUTPUT GND----~-----
ENABLE
vee=5CoH IHO\!
OUTPUT
VOL 10% \1.. :50_'%1_ _

Fig. 8

c8 SAMSUNG SEMICONDUCTOR 555

KAD0808/KAOoa09 CMOS INTEGRATED CIRCUIT

APPLICATIONS INFORMATION
OPERATION
1.0 Ratiometric Conversion
The KAD0808, KAD0809 is designed as a complete Data Acquisition System (DAS) for ratiometric conversion
systems. In ratiometric systems, the physical variable being measured is expressed as a percentage of full-scale
which is not necessarily related to an absolute standard. The voltage input to the KAD0808 is expressed by the
equation.

V,N ' Ox Vz = Zero voltage

=
V's - Vz Dmax-Dmin Ox = Data pOint being measured
=
Y'N Input voltage into the KAD0808 Dmax = Maximum data limit
=
V's Full-scale voltage Dmin = Minimum da~a limit

A good example of a ratiometric transducer is a potentiometer used as a position sensor. The position of the wiper
is directly proportional to the output voltage which is a ratio of the full-scale voltage across it. Since the data is
represented as a proportion of full-scale, reference requirements are greatly reduced, eliminating a large source
of error and cost for many applications. A major advantage of the KAD0808. KAD0809 is that the input voltage
range is equal to the supply range so the transducers can be connect!!d directly across the supply and thier
outputs connected directly into the multiplexer inputs, (Figure 9).
Ratiometric transducers such as potentiometers, strain gauges, thermistor bridges, pressure transducers, etc., are
suitable for measuring proportional relationships; however, many types of measurements must be referr!!d to an
absolute standard such as voltage or current. This means a system reference must be used which relates the full-
= =
scale voltage to the standard volt. For example, if Vee VAEF 5.12V, then the full-scale range is divided into 256
standard steps. The smallest standard step is a LSB which is then 20mV.

2.0 Resistor Ladder Limitations

The voltages from the resistor ladder are compared to the selected into 8 times in a conversion. These voltages
are coupled to the comparator via an analog·switch tree which is referenced to the supply. The voltages at the
top, cente'r and bottom of the ladder must be controlled to maintain proper operation.
The top of the ladder, Ref( +), should not be .more positive than th~ supply, and the bottom of the ladder, Ref( -),
should not be more negative than ground. The center of the ladder voltage must also be near the center of the
supply because the analog switch tree changes from N-channel switches to P-channel switches. These limitations
are automatically satisfied in ratiometric systems and can be easily met in ground referenced systems.
Figure 10 shows a ground referenced system with a separate supply and reference. In this system, the supply must
be trimmed to match the reference voltage. For instance, if a 5.12V is used, the supply should be adjusted to the
same voltage within O.1V.

r-----~------~----~~vee
REF(+) MSS

~ -----I------+-------I'n7 . DIGITAL OUTPUT

QOUT PROPORTIONAL
TO ANALOG INPUT

= =
QOUT ...YttL .Ylli..
V AEF Vee
=
4.5V s,Vcc V AEF s,5.5V
• Ratiometric transducers
Fig_ 9 Ratiometric Conversion System

c8 SAMSUNG SEMICONDUCTOR 556

KADOS08/KAD0809 CMOS INTEGRATED CIRCUIT

APPLICATIONS INFORMATION (Continued)

The KAD0808 needs less than a milliamp of supply current so developing the supply from the reference is readily
accomplished. In Figure 11 a ground referenced system is shown which generates the supply from the reference.
The buffer shown can be an op amp of sufficient drive to supply the milliamp of supply current and the desired
bus drive, or if a capacitive bus is driven by the outputs a large capacitor will supply the transient supply current
as seen in Figure 12. The KA301A is overcompensated to insure stability when loaded by the 10",F output capacitor.
The top and bottom ladder voltages cannot exceed Vee and ground, respectively, but they can be symmetrically
less than Vee and greater than ground. The center of the ladder voltage should always be near the center of the
supply. Sensitivity of the converter can be increased, (I.e., size of the LSB steps decreased) by using a symmetrical
reference system. In Figure 13, a 2.5V reference is symmetrically centered about Vcd2 since the same current flows
in identical resistors. This system with a 2.5V reference allows the LSB bit to be half the size of a 5V reference system.

I - - - - - - - - - l Vee

II
MSB

~---'-I REF( +)
DIGITAL OUTPUT
QOUT REFERENCED
TO GROUND

InO
REF(-) LSB
~
L-----<o-------<>--I GND QOUT= VAEF

KADOB08
4.5V SVee = VAEFS5.5V

Fig. 10 Ground Referenced Conversion System USing Trimmed Supply

Vee
MSB

DIGITAL OUTPUT
1-~>--------,.--1REF( +) OOUT REFERENCE'D
In7 TO GROUND

InO
REF(-) LSB
VIN
L-----------~__1GND
QOUT = VAEF
KAD0808 4.5V SVCC =VAEFS5.5V
Fig. 11 Ground Referenced Conversion System with Reference Generating Vee Supply

c8 SAMSUNG SEMICONDUCTOR 557

 KAD0808JKAD0809 . CMOS INTEGRATED CIRCUIT

10-15 Voe
1K

, \.

Vee
>----,~~--REF( +)

Fig. 12 Typical Reference ,and Supply Circuit

5V

DIGITAL OUTPUT
,PROPORTIONAL
TO ANALOG INPUT
1.25V:sVIN:s3.75V

2.5V REFERENCE RA=Rs

• Aatiometrlc transducers

Fig. 13 Symmetrically Centered Reference

3.0 Converter Equations

The transition between adjacent codes Nand N + 1 is givn l:1y:
N 1
VIN = ((VREF(+)- VREF(_) [256 + 512' ± VTUEI + VREFH

The center of an output code N is given by:

N" .
VIN{(VREF(+) - VREF(-~[256' ± VTUEI + VREFI-)

The output code N for an arbitrary input are the Integers within the range:.

N = V VIN ,- V~FH x 256 ± Absolute Accuracy

REF(+)- REF(-)
Where: VIN = Voltage at comparator input
VREF(+) = Voltage at Ref(+)
VREFI-) = Voltage at Ref( -)
VTuE=Total unadjusted error voltage (typically VREF(+)+512)

.c8 SAMSUNG SEMICONDUCTOR 558

KAD0808IKAD0809 CMOS INTEGRATED CIRCUIT

4.0 Analog Comparator Inputs

The dynamic comparator input current is caused by the pariodic switching of on·chip stray capacitances. These
are connected alternately to the output of the resistor ladder/switch tree network and to the comparator input as
part of the operation of the chopper stabilized comparatdr.
The average value oJ the comparator input current varies directly with clock frequency and with VIN as shown in
Figure 6.
If no filter capacitors are used at the analog inputs and the signal source impedances are low, the comparator
input current should not introduced converter errors, as the transient created by the capacitance discharge will
die out before the comparator output is strobed.
If input filter capacitors are desired for noise reduction and signal conditioning they will tend to average o4,t the
dynamic comparator input current. I will then take on the characteristics of a DC bias current whose effect can
be predicted conventionally.

TYPICAL APPLICATION

ADDRESS
DEcoDe
(AD4 - AD15)'
eLK
VREF(+)
VREF(-)

START
OE
EOC I---~~---INTERRUPT

2- 1
2-'
DB7
DBS
INTERRUPT

MSB
II
ALE 2- 3 DB5
2-' DB4
A KADOBOB 2-' DB3
B KADOB09 2-' DB2
C 2- 7 DBl
2- 8 DBO
5V SUPPLY LSB

Vee
VINB}
J
GND
0-5V
GROUND ANALOG INPUT
RANGE

V'Nl
• Addre~s latches needed for 8085 and SC/MP interfacing the KAD080B to a microprocessor

MICROPROCESSOR INTERFACE TABLE

Processor Read Write Interrupt "(Comment)

8080' MEMR MEMW INTR (Thru RST Circuit)

8085 RD WR INTR (Thru RST Circuit)
Z..8Q RD WR INT (Thru RST Circuit, Mode 0)
SC/MP NRDS" NWDS SA (Thru Sense A)
6800 VMA- !Il2-RlW VMA-91-RIW IRQA or'i"RQB (Thru PIA)

c8 SAMSUNG SE,..ICONDUCTOR 559

 PRELIMINARY
KAD0820AlB CMOS INTEGRATED CIRCUIT

8·BIT HIGH SPEED j.tP·COMPATIBLE AID

20 DIP
CONVERTER WITH TRACK/HOLD FUNCTION
By using a half-flash conversion technique, the 8-bit
KAD0820A/B CMOS AID offers a 1.51's conversion time
and dissipates only 75mW of power. The half-flash
technique consists of 32 comparators, a most
,significant 4-bit ADC and a least significant 4-bit ADC.
The input to the KAD0820A/B is tracked and held by the
input sampling circuitry eliminating the need for an
extemal sample-and-hold for signals moving at less than
100mV/l's.
For ease of interface to microprocessors, the
KAD0820A/B has been designed to appear as a memory
location or 1/0 port with'out the need for external
interfacing logic.

FEATURES
• Built-In track-and-hold function
• No missing codes
• No external clocking
• Single supply + 5Voc
• Easy interface to all microprocessors, or operates
sta~d-alone
• Latched TRI-STATE output
• Logic inputs and outputs meet both CMOS and TTL
voltage level specifications
• Operates ratiometrically or with any reference ORDERING INFORMATION
value equal to or less than Vcc
• OV to 5V analog input voltage range with single Device Package Temperature Range Diff. Nonlinearity
5V supply
• No zero or full·scale adju~t required KAD0820AIN :!: 1/2 LSB
20 DIP - 40·C - + 85·C
• Overflow output available for cascading KAD0820BIN :!:1 LSB
• 0.3 n standard width 20·pin DIP

BLOCK DIAGRAMS
VREF(+) OFL
4.BIT OFL
FLASH DB?
ADC DB6
(4 MSBs) DB5,
VREF(-) DB4

OUTPUT
LATCH
4'BIT DAC AND
TRI-5TATE
BUFFERS

VREF(+ DB3
4-BIT
16 FLASt4 DB2
ADC DB1
(4 LSBs)
VREF(-) DBO

INT

MODE WR/RDY CS Rp
Fig. 1

c8 SAMSUNG SEMICONDUCTOR 560

 PRELIMINARY
KAD0820AlB CMOS INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Note 1 & 2)

Characteristic Symbol Value Unit

Supply Voltage Vee 10 V

Package Dissipation at Ta= 25·C Po 875 mW
Logic Control Inputs VI -0.2 - Vee+0.2 V
Voltage at Other Inputs and Output VI -0.2 - Vee+0.2 V
Operating Temperature Range Topr -40 - +85 ·C
Storage Temperature Ral)ge T.tg -65-+150 ·C

ELECTRICAL CHARACTERISTICS
The following specifications apply for RD mode (pin 7= 0), Vee = + 5V, VREF(+l= +5V, and VREF(-l= GND, Ta=2S·C
unless otherwise specified. .

Characteristic Symbol Test Conditions Min Typ Max Unit

I
Resolution - 8 8 Bits
Total Unadjusted Error KAD0820A ± 1/2 ±1I2 LSB
'. (Note 3)
INL
KAD0820B
- ±1 ±1 LSB
Reference
RRE~ 1.4 2.3 5.3 KI'l
Resistance
Maximum VREF(+l
Input Voltage
VREF(+lmax - Vee Vee V

Minimum VREF(-l
Input Voltage
VREF(-lmln - GND GND V

Minimum VREF(+l
Input Voltage
VREF(+)mln - VREF(-l VREF(-l V

Maximum V REFH
Input Voltage
VREF(-lmax - VREF(+l VREF(+l V

VIN Input
Voltage VIN GND'().1 - Vee+0.1 V

e5=Vee
Maximum Analog
Input Leakage Current
IL VIN = Vee - 0.3 3 p.A
VIN=GND -0.3 -3 p.A
Power Supply
Sensitivity
Is Vee=5V±5% - ± 1116 ±1/4 LSB

ciS SAMSUNG SEMICONDUCTOR 561

 PRELIMINARY
KAD0820AlB CMOS INTEGRATED CIRCUIT

DC ELECTRICAL CHARACTERISTICS
The following specifications aPply for Vee = 5V, Ta = 25°C unless otherwise specified.

Characteristic Symbol Test Conditions Min Typ Max Units

Logical "1" Input Voltage VINI,) Vee = 5.25V

CS, WR, RO 2.0 - Vce V
Mode 3.5 - Vce V

Logical "0" Input Voltage Vce=4.75V

CS, WR, RO 0 - 0.8 V
VINIO)
Mode 0 - 1.5 V
VINI,) = 5V; CS, RO - 0.1 1 /lA
Logical "1" Input Current IIN(1) VIN(1)=5V; WR - 0.1 1 /lA
VINI,) = 5V; Mode - 50 170 /lA
VINlo) = OV; es, RO, WR,
- 0.1 1
Logical "0" Input Current VINIO)
Mode !lA
Vce=4.75V, lOUT = -360/lA; - 2.4 2.8 V
OBO-OB7, OFL, INT
Logical "1" Output Voltage VOUTI')
Vee = 4.75V, louT =' -10/lA; - 4.5 4.6 V
OBO - OB7, OFL, INT
Vee = 4. 75V, louT = 1.8mA;
Logical "0" Output Voltage VOUTIO)
OBO - OB7, OFL, INT, ROY
- 0.34 0.4 V

TRI-STATE Output Current

VouT =5V; OBO- OB7, ROY - 0.1 1 /lA
louT
VOUT=OV; OBO- OB7, ROY - -0.1 -1 /lA

Output Source Current ISOURCE

VOUT=OV; OBO-DB7, OFL -7.2 -12 - mA
INT -5.3 -9 - mA
VOUT = 5V; OBO - DB7, 'OFL,
Output Sink Current ISINK
INT, RDY
8.4 14 - mA

Supply Current Icc CS=WR=RD=O

_. 7.5 13 mA

AC ELECTRICAL CHARACTERISTICS The following specifications apply for Vee =5V,

t r =t,=20ns, VREFI +)=5V, VREFI-I=GND and Ta=25°C unless otherwise specified.

Characteristic Symbol Test Conditions Min Typ Max Unit

Conversion Time for RD Mode tCAD Pin 7 = 0, (Figure 2) - 1.6 2.5 /ls

Access Time (Delay from Falling

Edge of RD to Output Valid)
tAeeo Pin 7 = 0, (Figure 2) - tCRD +20 t~AD + 50 ns

Conversion Time for Pin 7 = Vec; tWA = 600ns,

WR-RD Mode
tewR.AD
tRD = 600ns; (Figures 3a and 3b)
- 1.52 - /lS

Write Time
Min Pin 7 = Vee; (Figures 3a and 3b) - - 600 ns
tWR
Max (Note 4) See Graph - 50 - /lS

Pin 7 = Vce; (Figures 3a and 3b)

Read Time Min tRD
(Note 4) See Graph
- - 600 ns

c8 SAMSUNG SEMICONDUCTOR 562

 PRELIMINARY
KAD0820AlB CMOS INTEGRATED CIRCUIT

AC ELECTRICAL CHARACTERISTICS (Continued) The following specifications apply for

Vcc =5V, t,=t,=20ns, VREF(+)=5V, VREF(_)=OV and·Ta=25°C unless otherwise specified.

Characteristic Symbol Test Conditions Min Typ Max Unit

Pin 7=Vcc, tRo<t,;

Access Time (Delay from Falling (Figure 3a)
Edge of FID to Output Valid) tACC' CL=15pF - 190 280 ns
CL= 100pF - 210 320 ns
Pin 7=Vcc, tRo>t,; (Figure 3b)
Access Time (Delay from Falling CL= 15pF - 70 120 ns
Edge of RD to Output Valid) tACC2
CL= 100pF - 90 150 ns
Pin 7 = Vcc; (Figure 3b and 4)
Internal Comparison Time t, - 800 1300 ns
CL=50pF
TRI-STATE Control (Delay from.
Rising Edge of RD to Hi-Z State) t'H, tOH RL=1K, CL=10pF - 100 200 ns

Pin 7 = Vcc, CL= 50pF

II
Delay from Rising Edge of
t'NTL tRO > t,; (Figure 3b) t, hs
WR to Falling Edge of INT
tRo<t,; (Figure 3a) - tRo + 200 tRo + 290 ns
Delay from Rising Edge of (Figure 2, 3a and 3b)
t'NTH - 125 225 ns
RD to Rising Edge of INT CL=50pF
Delay from Rising Edge of
WR to Rising Edge of INT t'NTHWR (Figure 4), CL = 50pF - 175 270 ns

Delay from CS to RDY tROY . (Figure 2), CL=50pF, Pin 7=0 - 50 100· ns
Delay from INT to Output Valid t,o (Figure 4) - 20 50 ns
Pin 7=Vcc, tRo<t,
Delay from RD to INT t R, - 200 290 ns
(Figure 3a)
Delay from End of Conversion (Figure 2, 3a, 3b and 4)
to Next Conversion
tp
(Note 4) See Graph - - 500 ns

Slew Rate, Tracking - 0.1 - V/p.s

Analog Input Capacitance CV'N - 45 - pF
Logic Output Capacitance COUT - 5 - pF
Logic Input Capacitance C'N - 5 - pF

Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: Total unadjusted error includes offset, full-scale, and linearity errors.
Note 4: Accuracy may degrade if tWR or tRo is shorter than the minimum value specified. See Accuracy vs tWR and
Accuracy vs tRP graphs.

c8 SAMSUNG SEMICONDUCTOR 563

 PRELIMINARY
KAD0820AlB CMOS INTEGRATED CIRCUIT

TRI·STATE TEST CIRCUITS AND

TIMING DIAGRAMS Vee
Vee tlH

GNO
1--~-.-oOATA OUTPUT

lK
OATAVOH~
OUTPUT ~ ,
,GNO - - - - - - - - - - ' =
f r =20ns CL= 10pF
tOH
Vee Vee tOH
Vee

J
GNO

OH
vee
OATA
OUTPUT
VOL 10%
t r =20ns
TIMING DIAGRAMS
CSI
\ "--,---
Ri'il--+---"

,ROy--t-""""\1

INT ----I--~..J
INT ----+---~"

------
OBO- OB7 OBO-OB7

Fig. 2 RD Mode (Pin 7 is Low) Fig. 3a WR·RD Mode (Pin. 7 is High and tRD<t~

~WW--------------­
ROLOW------~--------

WR
AD ----+-----+....1
tRO

Im----+----~I INT _ _ _ -+,.

tlll1'L !til
t=tlO
OBO-OB7 _ _ _ _ ...J»---~\DATA VALlO)--
OBO-OB7
- ------------
tAce2 Fig. 4 WR·RD Mode (Pin 7 is High)
t1H. tOH Stand·Alone Operation
Fig. 3b WR·RD Mode (Pin 7 is High and tRD>tl)

ciS SAMSUNG SEMICONDUCTOR, 564

 PRELIMINARY
KAD0820AlB CMOS INTEGRATED CIRCUIT

TYPICAL APPLICATIONS

13
CS 0 - - . - - - - r - - - O 5V
VGep2...
8
RD
6
ROY
9
INT
DBO

en DBl
:J
DB2
'" DB3 VREF( + 11-'1;;.2- - - - - . - - o 5 V
DB4
DB5
.VREF(_1 11
. DB6
DB7
OFL GND 10

8·Bit Resolution Configuration

CS
WR
13
6 WR
Cs Vee 1To5V
VIN
I
Ft>
BO
S-y
-
r,;m
2 DBO 7
Bl 3 DB1
MODE
VREF(+) ~
~ B2

::
4DB2

~ 5 DB3
14DB4
Jo.l

B5 15 DB5 VREF(-) 11
B6 16 DB6
B7 JO.l
17 DB7
B8 lK

GND~
OFL 18 OFL

.1.-- ~:
5K

~ lK

13 Cs Vee 1fo5V
6 WR VIN
..-
J
-~ RD

2 DBO
3 DB1
MODE r!;o5V
12
VREF(+)

l~
4 DB2
5 DB3
14 DB4
15 DB5 11
VREF(-)
16 DB6
fi7,
17 DB7.
18 OFL
GND~

90Bit Resolution Configuration

c8 SAMSUNG SEMICONDUCTOR 565

 PRELIMINARY
KAD0820AlB CMOS INTEGRATED CIRCUIT

TYPICAL APPLICATIONS (Continued)

25K AM
CH1

-15V
40K

DBO TO DB?

Telecom AID Converter Multiple Input Channels

1.2~s
VIN .., r-
(OVTO 5V)U

10 GND WR 2 LSB 12 1-'1-=-3_ _---1~-15V

13 CS 11 JO.1~F

10
F---~---1~- -15V
11 VREF(-)
KAD0820A KDA0800
15 8
+5V
16
Vee /----MIr--5V .
17 6
? MODE
18 MSB 5
12 VREF(+)

+15V

OV-5V

-15V

1.82K 1%

Fast Infinite Sample-and-Hold

c8 SAMSUNG SEMICOND~croA 566

db Digital Waveform Recorder
~
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C
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~
I
CONVERTERS MEMORY COUNTERS CONTROL LOGIC

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HCT393
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CS
EWR1

EWR2
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3"
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CD
-9:
RD1
RD, WR
ERD1
RD2
CS ----t1l'~7AU,...T'l'7A L- J!......... :'.!~. .::_I T ERD2

WR
~~
oPl
cn~
TRIGGER LEVEL
-;e
Z;ti
5V o-M"'''H.~~~~~-----' -I~
m""(
CLOCK INPUT (te) -1.3M samples/sec G')
(SAMPLING FREQUENCY = tcl3) e4K memory

~
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•
KS7126 CMOS INTEGRATED CIRCUIT

3 112 DIGIT AID CONVERTER

40 DIP ,
The single chip CMOS KS7126 incorporates all the active devices for a
3 112 digit analog-to-digital converter tadirectly drive an LCD display. The
internal oscillator, voltage reference and display segmentlbackplane
drivers simplify system integration, reduce board space requirements
and lower total cost. A low cost, high resolution-O.05%-indicating meter
requires only II display, four resistors, four capacitors and 9V battery.
The KS7126 dual slope conversion technique rejects interference signal
when the integration time is set to a multiple of the interference sighal
period. This is especially useful in industrial measurement environments
where SO, 60 and 40Hz line frequency signals are present. With an auto-
zero error less than 10I'v, zero driflless than 1I'VJOC, input bias current
of 10pA max and rollOver error of less than one count, the KS7126 brings
exceptional value to the portable battery powered field.
In addition, the differential input and reference allows the measurement
on load cells, strain gauges and other bridge type transducers. The low '
power KS7126 can be used as a plug-in replacement for existing 7106
based systems by changing only the values of seven passive com-
ponel1t s.

FEATURES ORDERING INFORMATION

• Long Battery Life: 800 Hours TYpical
Temperature Range
• Auto-Zero Cycle
• Guaranteed Zero Reading With Zero Input' 0- + 70·C
• Low Noise: 151'Vp-p
• High Resolution (0.05%) and Wide Dynamic Range (72dB)
• LoW Input Leakage Current: 1pA TYpical, 10pA Maximum
• Direct LCD Display Drive-No External Components
• Precision Null Detection With True Polarity at Zero
• High Impedance Differential Input
• Convenient 9V Battery Operation With Low
Power Dlsslpatiom 500/lW TYpical, 900l'W Maximum
• Internal Clock Circuit
• Drop-In Replacement for TSC7126, ICL7126

TYPICAL APPLICATIONS
• Thermometry • Digital Scales
• Bridge Readouts (Strain Gauges, Load Cells, Null Detectors) • LVDT Indicators
• Digital Meters • Portable Instrumentation
- Voltage/CurrentlOhmslPower • Power Supply Readouts
-pH • Process Monitors
- Capacitancellnductance' • Photometers
- Fluidlflow RatelViscosity/Level

c8 SAMSUNG SEMICONDUCTOR 568

KS7126 C.MOS INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Char.acterlstlc Symbol value Unit

Supply Voltage Vee 15 V

Analog Input Voltage (Either Input) (1) V,N Vee-VEE V
Reference Input Voltage (Either Input) VREF Vee-VEE V
Clock Input . VCl Test-Vee V
Power Dissipation Pd 800 mW
Lead Temperature (Soldering, 60 Sec) T, 300 °C
Operating Temperature Topr 0~+70 °C
Storage Temperature Tstg -65-+160 .oC
I
ELECTRICAL CHARACTERISTICS
Characteristic Symbol Test Conditons Min Typ Max Unit

II
V,N=O.OV Digital
Zero Input Reading - Full scale = 200.0mV
-000.0 +000.0 +000.0
Reading
Zero Rading Drift - V,N = 0, 0·C<TI:I<70·C 0.2 1 . p.VI·C
V,N =VREF 999 999 1000 Digital
Ratiometric Reading - VREF =100mV 1000 Reading
Linearity (Max. deviation from Full scale = 200mV
NL -1 +0.2 +1 Counts
straight line fit) or full scale = 2,000V
Rollover Error
(Difference in reading for equal
positive and negative reading
- - V,N = + V,N = 200.0mV -1 +0.2 +1 Counts
hear full scale)
Noise (Pk·Pk value not exceed
95% of time)
EN V,N=OV - - 15 p.V

Leakage Current @ Input IL V,N=OV 1 10 pA

VeM= +1V; V,N=OV
Common Mode Rejection Ratio CMRR
Full scale = 200.0mV - 50 - p.VIV

Scale Factor Temperature V,N = 199.0mV

Coefficient
- 0<Ta<70·C (Ext. Ref. 0 ppml·C)
-;- 1 5 ppml·C

Temp. Coeff. of Analog Common 250KO between common and

(with respect to positive supply)
.VeTL
positive supply
- 80 - ppml~C

Analog Common Voltage 250K!1 between common and

Ve 2.4 2.8 3.2 V
(with respect to positive supply) positive supply
Pk·Pk Segment Drive Voltage
Vso Vee to VEE =9V 4 5 6 V
(Note 5)
Pk·pk Backplane Drive Voltage
. Veo Vee to VEE =9V,. 4 5 6 V
(Note 5)
Power Supply Current Is V,N = OV, Vee to VEE = 9V - 55 100 . p.A

c8 SAMSU~G SEMICONDUCTOR 569

KS7126 CMOS INTEGRATED CIRCUIT

Notes
11 Input voltage may exceed the supply voltage provided the input current is limited to ± 100pA
2) Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
3) Unless otherwise noted, specifications apply T.=25°C, fClOCK=16KHz and are tested in the circuit of Figure 1.
4) Refer to "Differential Input" discussion on page 7. .
5) Backplane drive is ill phase with segment drive for 'off' segment, 180 out of phase for 'on' segment. Frequency is 20 times
conversion lJ!te. Average DC component is less than 50mV.
6) During auto-zero phase, current is 10 - 20pA higher, 48KHz oscillator, Figure 2, increases current by 8pA (Typ.)

TYPICAL OPERATING CIRCUITS

IN IN
+

30
KS7126

Figure 1: KS7126Clock Frequency 16 KHz (1 reading/sec.) Figure 2: KS7126 Clock Frequency 48 KHz (3 readings/sec.)

PIN CONFIGURATION
" ." w
I-~I
C)Z 0
g~ z
u N

~ '8 ~
...
+
t:;
I
u.
W
+u.
W
I
t:; <:0 +
z
I .it f-
z W 1 :30.
'"0 0 ~ W a:
>
a:
> 0
a: a:
0
ZO
<0 :>
z
:> 3 >'"" :> w
> & 8 :l '"
C)
0.
III
'"~
21

KS7126

a
~ f1. aJ ~

_-----'-___ ., __------'--_.,,~ i
8' ~
- ~

c8 SAMSUNG SEMICONDUCTOR 570

KS7126 CMOS INTEGRATED CIRCUIT

PIN DESCRIPTION

Pin Number Name Description

1 Vee Positive supply voltage.

2 D, Activates the D section of the units display.
3 C, Activates the C section of the units display.
4 B, Activates the B section of the units display.
5 A, Activates the A section of the units display.
6 F, Activates the F section of the units display. '
7 G, Activates the G section of the units display.
8 E, Activates the E section of the units display.
9 D2 Activates the D section olthe tens display.
10 C2 Actatives the C section of the tens display.
11 B2 Activates the B section of the tens display.

II
12 A2 Activates the A section of the tens display.
13 F2 Activates the F section of the tens display.
14 E2 Activates the E section of the tens display.
15 D3 Activates the D section of the hundreds display.
16 B3 Activates the B section of the hundreds display.
17 F3 Activates the F section of the hundreds display.
18 E3 Activates the E section of the hundreds display.
19 AB. Activates both halves of the 1 in the thousands display.
20 POL Activates the negative polarity display.
21 BP Backplane drive output
22 Go Activates the G section of the hundreds display.
23 Aa Activates the A section of the hundreds display.
24 C3 Activates the C section olthe hundreds display.
25 G2 Activates the G section of the tens display.
26 VEE Negative power supply voltage.
The integrating capacitor should be selected to give maximum voltage swing
that ensures component tolerance build up will not allow the integrator output
to saturate. When analog common is used as a reference and the conver-
27 V'NT sion rate is 3 reading per second, a 0.047/LF capacitor may be used.
The capacitor must have a low dielectric constant to prevent roll-over errors.
See INTEGRATING CAPACITOR section for additional details.
Integration resistor connection. Use a 180KO fr a 200mV full-scale
28 V euFF
range and a 1.8MO for"2V full-scale range.
The size of the auto-zero capacitor influences the system noise. Use a O.33/LF
capacitor for a 200mV full-scale, and 0.033/LF capacitor for a 2V full-scale.
29 CAZ See paragraph on AUTO-ZERO CAPACITOR for more details.

c8 SAMSUNG SEMICONDUCTOR 571

KS7126 CMOS INTEGRATED CIRCUIT

PIN DESCRIPTION (Conti~ued)

Pin Number Name Description

30 V 1N - The low input is connected to this pin.

31 V1N + The high input signal is connected to this pin.
This pin is primarily used to set the analog common-mode voltage for bat-
ANALOG . tery operation or in sytem where the input signal is referenced to the poWer
32 COMMON
supply. See paragraph for ANALOG COMMON for more details.
It also acts as a reference voltage source.
33 CAEF - See pin 34
A 0.1pF-capacitor is used in most applications. If a large common mode vol-
tage exists (for example the V 1N pin is not at analog common), and
34 C AEF +
a 200mV scale is used, a 1.0"F is recommended and will hold the rollover
error to 0.5 COunt. .
35 V AEF - See pin 36.
The analOg input required to 'generate a full-scale output (1.999 counts).,
Place 100mV between pins 35 and 36 for 199.9mV full-scale. Place 1.000 volt
36 V AEF +
between pins 35 and 36 for 2V full-scale. See paragraph on REFERENCE
VOLTAGE.
lamp test. When pulled high (to Vee) all segments will be turned ON and the
display should read -18~8. It may also be used as a negative supply for ex-
37 TEST
ternally generated decimal points. See paragraph under TEST for additional
informatiOn.
38 OSCa See pin 40.
39 OSC. See pin 40.
Pins 40, 39, 38 make up the oscillator section. For a 48KHz clock (3 read-
ings per second) connect pin 40 the junction of a 180KO resistor an
40 OSC,
a 50pF capaCitor. The 180K resistor is tied to pin 39 an the 50pF capaCitor

i is tied to pin 38.

c8 SAMSUNG SEMICONDU~OR 572

KS7126 CMOS INTEGRATED CIRCUIT

DETAILED DESCRIPTION
ANALOG SECTION
Fig. 3 shows the Block Diagram of the Analog Section for the KS7126. Each measurement cycle is divided into three phases.
They are (1) Auto-zero (A-Z), (2) Signal integrate (I NT) and (3) De-Integrate (DE).

TO DIGITAL SECTION

Fig. 3 Analog Section of KS7126

I
1_ Auto-zero phase
During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to
analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed
around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier, integra-
tor, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the noise of the sys-
tem. In any case, the offset referred to the input is less than 101'V.

2. Signal integrate phase

During signal integrate, the auto-zero loop is opened. the internal short is removed, and the internal input high and low
are connected to the external pins. The converter then integrates the differential voltage between IN + and IN - for a fixed
time. This differential voltage can be within a wide common mode range; within one Volt of either supply. If, on the other hand,
the input signal has no return with respect to the converter power supply, IN- can be tied to analog COMMON to estab-
lish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined.

3. De-integrate phase
. The final phase is de-integrate, or reference integrate: Input low is internally connected to analog COMMON and input high
is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be
connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return
to zero is proportional to the input signal. Specifically the digital reading displayed is 1000( ~ )
. V REF
Differential Input
The input can accept differential voltages anywhere within the common mode range of the input amplifier; or specifically
from 0.5 Volts below the positive supply to 1.0 Volt above the negative supply. In this range the system has a CMRR of 86dB
typical. However, since the integrator also swings with the common ijlode voltage, care must be exercised to assure the in-
a
tegrator output does not saturate. A worst case condition would be large positive common-mode voltage with a near full-
scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has
been used up by the positive common mode voltage. For these critical applications the integrator swing can be reduced to
less than the recommended 2V full scale swing with little loss of accuracy. The integrator output can swing within 0.3 Volts
of either supply without loss of linearity. ' .

c8 SAMSUNG SEMICONDUCTOR 573

KS7126 CMOS INTEGRATED CIRCUIT

Differential R.rence
The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of
common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on
its modes. If there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called
up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal.
This difference in reference for (+) or (-) input voltage will give a,roll-over error How.ever, by selecting the reference capaci-
tor large enpugh in comparision to the stray capacitance, this error can be held to less than 0.5 count for the worst case condition
(See component Value Section)

Vee
REF + vee 27KIl

,
6.8 VOLT 200KO
ZENER KS7126
REF -

RS7126 REF+ 1'.2 REFERENCE

REF-

COMMON

Fig. 4: Using. an External Reference

vee vee
vee
1 - --l TEST
Vee
I I 37
I I
I I TO LLD
I DECIMAL
I KS7126 DECIMAL
I I POINT
POINT
KS7126 I IDLeO
SELECT
BP 21 DECIMAL
POINT
GND
L__ __J
TEST 57 32 GND

L - - - - - - - - o ~~~lANE
Figure 5: Simple Inverter for Fixed Decimal Point Figure 6: ExclusiveOR Gate for Decimal Point

Analog Common
. This pin is included primarily to set the common mode voltage for battery operation or for any system where Ine input sig-
nals are floating with respect to the power supply. The COMMON pin sets a voltage that is approximately 2.8 Volts more negative
than the positive supply. This is selected to give a minimum end-of-life battery voltage of about 6V. However, the analog
COMMON has some of the attributes of a reference voltage. When the total supply voltage is large enough to cause the zener
to regulate ( < 7V), the COMMON voltage will have a low voltage coefficient (0.001%1%), low output impedance (=150),and
a temperature coefficient typically less than 80 ppml"C.
The limitations of the on-Chip reference should be also recognized, however. The reference temperature coefficient (TC)
can cause some degradation in performance. Temperature changes of 2 to SOC, typical for instruments, can give a scale factor
error of a count or more. Also the common voltage will have a poor voltage coefficient when the total supply voltage is less
than that which will cause the zener to regulate « 7V), These problems are eliminated if an external reference is used, as
shown in Fig. 4.
Analog COMMON Is also used as the Input low return during auto·zero and de·integrate. If IN- is different from analog
COMMON, a common mode voltage exists in the System and is taken care of by the excellent CMRR of the converter. However,
in some appncations IN - will be set at a fixed known voltage (power supply common for instance). In this application, analog
COMMON should be tied to the same point, thus remOVing the common mode voltage from the converter. The same holds
true for the reference voltage. If reference can be conveniently referenced to analog COMMON, it should be since this removes
tlie common mode voltage from the reference system.

c8SAMSUNG SEMICONDUCTOR 574

KS7126 CMOS INTEGRATED CIRCUIT

Within the IC, analog COMMON is tied to an N channel FET that can sink 100pA or more of current to hold the voltage
2.8 'volts below the positive supply (when a load is trying to pull the common line positive). However, there is only 1pA of source
current .. so COMMON may easily be tied to a more negative vQltage thus overriding the internal reference.

Test
The TEST pin serves two functions. It is coupled to the internally generated digital supply through a 500n resistor. Thus
it can be used as the negative supply for externally generated segment drivers such as decimal paints or any other presen-
tation the user may want to include on the LCD display Fig. 5 and Fig. 6 show such an application. No more than a 1mA load
should be applied.
The second function is a "lamp test". When TEST is pulled high (to Vecl all segments will be turned on and the display
should read - 1888. The TEST pin will sink about 10mA under these conditions.
CAUTION: In the lamp test mode, the segments have a constant D-C voltage (no square-wave) and may burn the LCD
display if left in this mode for extended periods.

DIGITAL SECTION
Fig. 7 shows the digital section for the KS7126. An internal digital ground is generated from a 6 volt zener diode and a large

II
P channel source follower. This supply is made stiff to absorb the relative large capacitive current when the back plane (BP)
voltage is switched. The BP !requency is the clock frequency divided by 800. For three readings/second this is a 60Hz square
wave with a nominal amplitude of 5 volts. The segments are driven at the same frequency and amplitude and are in phase
with BP when OFF, but out of phase when ON. In all cases negligible DC voltage exists across the segments. The polarity
indication is "ON" for negative analog inputs. If IN - and IN + are reversed, this indication can be reversed also, if desired.

--+---~---+--~~--~------------4-----~--~~rOTEST
*Three Inverters.
One Inverter shown for clanty.

------......-.1----0 VEE

OSCl

Fig. 7: Digital Section

c8 SAMSUNG SEMICONDUCTOR 575

 KS7126. CMOS INTEGRATED CIRCUIT

System Timing
Fig. 8 shows the clocking arrangement used in the KS7126. Three basic clocking arrangements can be used.
1: An external oscillator connected to pin 40
2. A crystal between pins 39 and 40.
3. An R-C oscillator using all three pins

EXTERNAL
OSCILLATOR

Fig. 8: Clock Circuits

The oscillator frequency is divided by four before it clocks the decade counts. It is then futher divided to form the three
convert - cycle phases. These are signal iritegrate (1000 counts), reference de-integrate (0 to 2000 counts) and auto - zero
(1000 to 3000 counts): For signals less than full scale, auto - zero gets the unused portion of reference de-integrate. This
makes a complete measure cycle of 4,000 (1 ,600 clock pulses) independent of input voltage. For three readings/second, an .
oscillator frequency of 48 KHz would be used.
To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator frequency .
of 60KHz, 48KHz, 33l bKHz, ·etc. should be selected. For 50Hz rejection, oscillator frequencies of 66lJ:,KHz, 50KHz, 40KHz,
etc. would be suitable. Note that 40KHz (2.5 readings/second) will reject both 50 and 60Hz (also 400 and 440Hz)

COMPONENT VALUE SELECTION

1. Integrating Resistor
Both the buffer amplifier and the integrator have a class A output Stage with 6 pA of quiescent c~rrent. They can supply -1 pA
of drive current with negligible non-linearity. The integrating resistor should be large enough to remain in this very linear region
over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2 Volt
full scale, 1.8MO is near optimum and similarly 180KO for.a 200.0mV scale.

2. Integrating Capacitor
The integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance build-up will not
saturate the integral swing (approx. 0.3 Volt from either supply). When the analog COMMON is used as a reference, a nomi-
nal ±2 Volt full scale integrator swing is fine.For three readings/second (48KHz clock) nominal values for C'NT are 0.047!,F,
.' for 1/sec (16KHz) 0.15!,F of course, it different oscillator frequencies are used, these values should be changed in inverse
proportion to maintain the same output swing.
The integrating capacitor should have low dielectric absorption to prevent roll-over-errors. While other types may be ade-
qU!'te for this application, polypropylene capaCitors give undetectable errors at reasonable cost. At three readings/sec., a
7500 resistor should be placed in series with the integrating capaCitor, to compensate for comparator delay.

3. Auto·Zero Capacitor
The size of the auto-zero capaCitor has some influence on the noise of the system. For 200mV full scale where noise is
very important, a 0.32!,F capaCitor is recommended. On the 2 Volt scale, a 0.033!,F capacitor increases the speed of recov-
ery from overload and is adequate for nOise on this scale.

4. Reference Capacitor
. A 0.1 ~ capacitor gives good results in most applications. However, where a large common mode voltage exists (i .e. the
a
REF - pin is not analog COMMON) and a 200mV scale is used, large value is required to prevent roll-over error. Gener-
ally 1.0!,F will hold the roll-over error to 0.5 count in this instance.

5. Oscillator Components
For all ranges of frequency a 50pF capacitor is recommended and the resistor is selected from the approximate equa-
tion f '" ~5 For 48KHz clock (3 readings/second) R=18KO
RC

c8 SAMSUNG SEMICONDUCTOR 576

KS7126 CMOS INTEGRATED CIRCUIT

TYPICAL APPLICATIONS
Ve_c______________~~--~----~----------------------------,
Scaie factor adjust
(Vref =100mV for fIC to RMS)
OSC,
OSC2

flClIN

KS7126

2.2MO
CREF-
ANALOG COMMON
(OR COMMON)
VIN+
VIN-

CAZ
VeUFF

I
VINT

G,
Co

Go

Figure 9: AC to DC Converter with KS7126. Test is Used as a Common

Mode Reference' Level to Ensure Compatibility with Most Op·Amps.

To pin 1

Topinll
40 40
1801<0

..
'.r' Set Vref= 1.000V

/
,i
50~F
Set Vref=100.0mV

50pF
~
Vee
F= \.1 +5V
250Kll 240KO lOKO liMO ~~ 6.8V
Do·lp1' :p.o.,p1'!

...
KS7126 .01p1' lMO KS7126 O.lp1' lMO
,
. 22.FII
... J.·...1...8MO
• IN
..O~3,F
IN

180KO
'i,'
~ 750!l. :; 0.047~F ."
VEE -5V

~
F=
}TODISPLAY ~ } TO DISPLAY
f=
21 F= - TO BACKlpLANE 21 f----- TO BACKPLANE

Figure 11: KS7126 with Zener Diode Reference:

Figure 10: Recommended Values for2.000V Full-Scale,
Three Readings Per Second .

.c8 SAMSUNG SEMICONDUCTOR 577

KS7126 .. CMOS INTEGRATED CIRCUIT

Vee To pi" 1
Vee

40 Fl
Sell!ref-l00.0mV
:~

50pF
IooKII
24aKIl 20K!l~r 'T 27K(J
po.l"F --.o'I l2V

KS7126
LJ_='""""""---<>--_-=+=c.:.O"'l"F=--_ _ _+-Q IN
+
KS7126
O.33.F..
.01"F
-III
lMO
- IN

-=-9V ... d'

F }TODISPLA:
1=
21 F - TO BACK PLANE

Figure 12: KS7126 Using the Internal Reference. 200.0mV Figure 13: KS7126 Operated From Single +5V
Full-Scale, Three Readings Per Second, Floating Supply Supply. An External Reference Must Be Used.
Voltage (9V Battery).

To pin 1 TO pi" 1
Vce--------------~ V
560KIl ee
40
l--_ _ ~_ SetV""-100.0mV
40

50pF
~---~~~~~~~~~Vec
TSC9491CJ

KSl726
KS7126

D-----'-=='---'-------~VEE

"Values depend on clock frqeucny. See figure 10,'12, 15.

Figure 14:. KS7126 Measuring Ratiometric Values of Quad Figure 15: KS7126 with an External Band-Gap
Load Cell. The Resistor Values Within the Bridge are Reference (1.2V Typ) IN - is tied to Common.
Determined by the Desired Sensitivity. Values Shown are for One Reading Per Second .

.c8 SAMSUNG SEMICONDUCTOR 578

KS7126 CMOS INTEGRATED CIRCUIT

To pin 1
Vee--------------------____,

40

D----~I------' Scale factor adjust

SOpF 100KO/
1MU

LJ------+-~--t-+\-I.----~ To logic
GND
KS7126

Silicon NPN
MPS37040r
similar
o Rang<

U Range
1+~---Cl(1t:t-g20

I
KS74HCTL10
KS74HCTLS266

Figure 16: KS7126 Used as a Digital Centigrade Figure 17: Circuit for Developing Underrange and Overrange
Thermometer. A Silicon Diode-Connected Transistor Has Signals from KS7126 Outputs.
a Temperature Coefficient of About 2mV/"C.

To pin 1
Vee

40 S60KO
II Set V,.f 1,OOOV
""SOpF

=0.1,,1' '"
2S0KO
.01,,1'
240KIl
1MO
Vee

KS71 26 :;p IN.

O.022'F-t~
1.SMU
0.1S.F

.} 10 DISPLAY

21""- 10 BACK PLANE

Figure 18: Recommended Component Values for 2.00V Full-Scale, One Reading Per Second.
·Values depend on clock frequency. See Figure 10, 12,15

c8 SAMSUNG SEMICONDUCTOR 579

KDAOSOO/KDAOS01/KDA0802 LINEAR INTEGRATED CIRCUIT

a·BIT DIA CONVERTER 16 DIP

The KDA0800 series are monolithic 8-bit high-speed current-output

digital-to-analog converters (DAC) featuring typical settling times of
100ns. When used as a multiplying DAC, monotonic performance over
a 40 to 1 reference current range is possible. The KDA0800 series also
features high compliance complementary current outputs to allow
differential output voltages of 20 Vp•p with simple resistor loads. the
reference-to-full-scale current matching of better than ± 1 LSB eliminates
the need for full-scale trims in most applications while the nonlinearities
of better than ± 0.1 % over temperature minimizes system error
accumulations.
The' noise immune inputs of the KDA,0800 series will accept TTL levels
with the logic threshold pin, VLC , potential allow direct interface to all
logic families. The performance and characteristics of the device are
essentially unchanged over the full ± 4.5V to ± 18V power supply range;
power dissipation is only 33mW with ± 5V supplies and is independent
of the logic input states.

FEATURES ORDERING INFORMATION

• Fast settling output time: 100ns
• Full 'scale error: ± 1 LSB Device Package Temperature Range NonUnearity
• Nonlinearity over'temperature: ± 0.1 % KDA0800CN ±0.19%FS
• Full scale current drift: ± 10 ppm/oC
• High output compliance: -10V to + 18V KDA0801CN 16'DIP 0- +,70·C ±0.39%FS
• Complementary current outputs KDA0802CN ±0.1%FS
• Interface directly with TTL, CMOS, PMOS
and others
• 2 quadrant wide range multiplying capability
• Wide power supply range: ± 4_5V to ± 18V
• Low power consumption: 33mW at ± 5V
• Low cost
• Standard 16 DIP package

BLOCK DIAGRAM
v+ VLC B1 MSB B2 B3 B4 85 B6 87 88 LS8

COMP v-

,c8 SAMSUNG SEMICONDUCTOR 580

KDA0800/KDA0801fKDA0802 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Supply Voltage Vcc ± 18V or 36V V

Power Dissipation Po 500mW. mW
Reference Input Differential Voltage (V·14 to V15) Y,N V_ - V+ V
Reference Input Common-Mode Range (V14, V15) Y'N V_ - V+ V
Reference Input Current Ire' 5mA rnA
Logic Inputs Y'N V_ - V_+36V V
Operating Temperature Topr DoC _ + 70°C °C
Storage Temperature Tstg - 65°C - + 150°C °C

ELECTRICAL CHARACTERISTICS
(Vs = ± 15V, Ire' = 2mA, Tm,nsTasTma>< unless otherwise specified. Output characteristics' refer to both lOUT and lOUT')

KDA0800
Characteristic Symbol Test Conditions Unit
Min Typ Max

Resolution
Monotonicity .

Nonlinearity
KDA0802
KDA0800
KDA0801
-
8
8
8
8

-
8
8
±0.1
±0.19
±0.39
Bits
Bits

%FS
I
To ± 1/2 LSB, all bits switched
Settling Time ts
"ON" or "OFF", Ta=25°C
- 100 150 ns

Propagation Delay
Each Bit tPLH, tpHL Ta=25°C - 35 60 ns
All Bits Switched - 35 60 ns
Full Scale Tempco TCI Fs ±10 ±50 ppm/DC
Full scale current change
Output Voltage Compliance Voc
<1/2 LSB, ROUT >20MO Typ
-10 - 18 V

Vre,=10V, R14=5KO
Full Scale Current IFS4 1.94 1.99 2.04 rnA
R15=5KO, Ta=25°C
Full Scale Symmetry IFss IFs4 -IFs2 - ±1 ±8.0 p.A
Zero Scale Current Izs - 0.2 2.0 p.A
V- = -5V 0 2.0 2.1 rnA
Output Current Range IFsR
V- = -8V to -18V 0 2.0 4.2 rnA
Logic Input Levels
Logic "0" V,L VLC=OV 0 - 0.8 V
l,ogic "1" V,H 2.0 - Vcc V
Logic Input Current VLC=OV
Logic "0" I'L -10VSV,N S +0.8V - -2.0 -10 p.A
Logic "1" I'H 2VSV,NS+18V - 0.002 10 p.A
Logic Input Swing V's V- = -15V -10 - 18 V
Logic Threshold Range VTHR Vs=±15V -10 - 13.5 V
Reference Bias Current 1,5 - -1.0 p.A p.A
Reference Input Slew Rate dl/dt 4.0 8.0 - mA/p.s
Power Supply Sensitivity PSSI Fs + 4.5VSV+ S18V - 0.0001 0.01 %/%

ciS SAMSUNG SEMICONDUCTOR 581

KDA0800/KDA0801/KDA0802 CMOS INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS (Continued)

KDA0800
Characteristic Symbol Test Conditions Unit
Min Typ. Max

-4.5VsV-s18V
PSSIFs -
Ire. = 1rnA
- 0.0001 0.01 %/%

.Vs= ±5V, Ire.=1rnA

1+ - 2.3 3.8 rnA
1- - -4.3 -5.8 rnA
Vs =5V, -15V, l,e.=2rnA
Power Supply Current . 1+ - 2.4 3.8 rnA
1- - -6.4 -7.8 rnA
Vs= ±15V, l,e.=2rnA
1+ - 2.5 3.8 rnA
1- - -6.5 -7.8 rnA
±5V,lre.=1rnA - 33 48 rnW
Power Dissipation Po 5V, -15V, Ire .=2rnA - 108 136 rnW
± 15V, I,e' = 2rnA - 135 '174 rnW

TYPICAL APPLICATIONS
MSS LSS
B1 B2B3B4B5B6B7B8 + Vre, 255
IFs=~X256
Iref
+Vref --+Vref 10 10 + 1';;= IFs for all
logic states
For fixed reference, TTL operation,
LT----:r--T--i-:r==:y 10 typical values are:
Vre.= 10V
Rre.=5KO
R15= R,e'
Cc=O.Q1I'F
+V
VLC=OV (Ground)

Fig. 1 Basic Positive Reference Operation

+ l,e.=2mA,--_ _ _"""""

KDA0800

_ - V,e' 255 Note: Rre; sets IFs: R15 is

IFs = ~ x 256 for bias current cancellation

Fig. 2 Recommended Full Scale Adjustm~nt Circuit Fig. 3 Basic Negative Reference Operation

c8 SAMSUNG SEMICONDUCTOR 582

KDA0800/KDA0801/KDA0802 LINEAR INTEGRATED CIRCUIT

TYPICAL APPLICATIONS (Continued).

MSB LSB
B1B2B3B4B5B6B7B8 Eo

+ Ire f=2mA

B1 B2 B3 B4 B5 B6 B7 B8 10 mA rc; mA Eo Eo
Full Scale 1 1 1 1 1 1 1 1 1.992 0.000 -9.960 0.000
Full Scale - LSB 1 1 1 1 1 1 1 0 1.984 0.008 -9.920 -0.040
Half Scale + LSB 1 0 0 0 0 0 0 1 1.008 0.984 -5.040 -4.920
Half Scale 1 0 0 0 0 0 0 0 1.000 0.992 -5.000 -4.960
Half Scale - LSB 0 1 1 1 1 1 1 1 0.992 1.000 -4.960 -5.000
Zero Scale + LSB 0 0 0 0 0 0 0 1 0.008 1.984 -0.040 -9.920
Zero Scale O· 0 0 0 0 0 0 0 0.000 1.992 0.000 -9.960

I
Fig. 4 Basic Unipolar Negative Operation
10K

Iref =2mAO------ 14
--.-
KDA0800
·I~r
-
10 2 Eo
10K

B1 B2 B3 B4 B5 B6 B7 B8 Eo Eo
Pos. Full Scale 1 1 1 1 1 1 1 1 -9.920 + 10.000
Pos. Full Scale - LSB 1 1 1 1 1 1 1 0 -9.840 +9.920
Zero Scale + LSB 1 0 0 0 0 0 0 1 -0.080 +0.160
Zero Scale 1 0 0 0 0 0 0 0 0.000 +0.080
Zerc. Scale - LSB 0 1 1 1 1 1 1 1 +0.080 0.000
Neg. Full Scale + LSB 0 0 0 0 0 0 0 1 +9.920 -9.840
Neg. Full Scale 0 0 0 0 0 0 0 0 + 10.000 -9.920
Fig. 5 Basic Diploar Output Operation
RL'5K

104
KDA0800

102
If RL = At: within ± 0.05%, output is symmetrical
about ground

B1 B2 B3 B4 B5 B6 B7 B8 Eo
Pos. Full Scale 1 1 1 1 1 1 1 1 +9.920
Pos. Full Scale - LSB 1 1 1 1 1 1 1 0 +9.840
( + ) Zero Scale 1 0 0 0 0 0 0 0 +0.04Q
( - ) Zero Scale 0 1 1 1 1 1 1 1 -0.040
Neg. Full Scale + LSB 0 0 0 0 0 0 0 1 -9.840
Neg. Full Scale 0 ,0 0 0 0 0 0 0 -9.920
Fig. 6 Symmetrical Offset Binary Operation

c8 SAMSUNG SEMICONDUCTOR 583

KDAOSOO/KDA0801/KDA0802 LINEAR INTEGRATED CIRCUIT

TYPICAL APPLICATIONS (Continued)

RL

KDA0800
KDA0800

For complementary output For complementary output

(operation as negative logic DAC), connect (operation as a negative logic DAC) connect
inverting input of op amp to r;; (pin 2), non-inverting input of op am to 10 (pin 2);
connect 10 (pin 4) to ground. connect 10 (pin 2); connect 10 (pin 4) to ground.
Fig. 7 Positive Low Impedance Output Operation Fig •. 8 Negative Low Impedance Output Operation

VTH = VLe + 1.4V

15V CMOS, HTL, HNIL
VTH=7.6V I
TTL, OTL

VTH":l.4V
I
I
I

I
12V TO 15V

}
,ffiK
VLe
11: 15V

9.1K
vLel
~
II

I 02V
,IZEN'ER O.2K J l .
o.,UF
I

--- --+-- -- ___ ~-----.L-_-_

5VeMOs I 10VeMos I 1.0KEL,L
V1H =2.5V I VTH =5V 'I VTH = -1.29V

KDA0800 i ~'0V i
VLe: 6.2KO I Typical values: RIN = 5K, + VIN = 10V
I VLe I,
. I c: I 1N4148
I~
10;
JO.'~F II
1KIJ
I I
I I
Do not exceed negative logic input range of DAC.
Fig. 9 Interfacing with Various Logic Families , Fig. 10 Pulsed Reference Operation

(a) lret~peak negative swing of liN (b) + Vral must be above peak positive swing of VIN
Vref

jIrel Rrel
o--#W~--i 14
KDA0800

o--.,.,.,~-t'5
'=:-_ _ _ _ _..J Rrel=R,5
KDA0800 - - HIGH INPUT
IMPEDANC~

Fig. 11. Accommodating Bipdlar References

c8 SAMSUNG SEMICONDUCTOR 584

KDAOBOO/KDA0801/KDA0802 CMOS INTEGRATED CIRCUIT

TYPICAL APPLICATIONS (Continued)

FO'R TURN "ON", VL = 2.7V VL
FOR TURN "OFF", VL=0.7V
SV

VOUT
-C OV
0 .4V

1 x PROBE rOY
.....L....,-0.4V

KDAoaoo
R1S -1SV

;;w. 15
13
TO D.U.T.

-1SV
Fig. 12 Settling Time Measurement
II
rSV STOP
OV .....J CONVERSION
FREE RUN

SV o-__~--,-16=-t
KS2SC02 D ~------~-------------,

.----+--'-1 GNDQ1 ° Q2Q3Q4QSQ6Q7

3 4 S 6 11 12 1314
LSBo---~
1SV 1SV SV
a·BIT DIGITAL ; - - _ - - 0 ANALOG
WORD INPUT

MSBo----r~+-+-r-~~
12 11 10 9 a 7 6 S
.--_...-_ _ _
VROE_F ~R,,11'f__1'-l4 LSB B7 B6 BS B4 B3 B2 MSB _,,2=------<>---+-+-----'
VR+
2.SK
KDAOSOO
R2 1S

100K

-1SV
Note. For 1 P.s conve'rsion time with a·bit resolution and 7·bit accuracy,
an KA361 comparator replaces the KA319 and the reference
current is doubled by reducing R1, R2 and R3 to 2.5KO and R4 to 2MO .
. Fig. 13 A Complete 2 p.S Conversion Time, 8·Bit AID Converter

c8 SAMSUNG SEMICOND.UCTOR 585

KS25C02lKS25C03/KS25C04 CMOS INTEGRATED CIRCUIT

8-81T AND 12·81T CMOS SUCCESSIVE

18 DIP
APPROXIMATION REGISTERS
These are a-bit and 12-bit CMOS registers designed for
use in successive approximati9n AID converters. They
contain all the logic and control circuits necessary in
combination with the AID converter to perform
successive approximation analog-to-digital conversions.
The KS25C02 has a bits with serial capability and is not
expandable. The KS25C03 has a bits and is expandable
without serial capability. The KS25C04 has 12 bits with
serial capability and expandibility.
Fabricated using a 2,..m, dual-layer metal CMOS process,
these parts deliver speeds and drive capability
equivalent to their TTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS
devices without any external components.
All inputs and outputs are protected from damage due
to static discharge by internal diode clamps to Vee and ORDERING INFORMATION
ground.
Device Package Temperature Range Registers
KS25C021N 16 DIP 4 bit
KS25C031N 16 DIP - 40·C - + 85·C a bit
KS25C041N 24SDIP 12 bit
FEATURES
• Complete logic for successive approximation AID • Active low or active high logic outputs
converters • Use as general purpose serlal-to-parallel converter
• 8-bit and 12-blt registers or ring counter
• Capable of short cycle or expanded operation • Low power consumption characteristics of CMOS
• Continuous or start-stop operation • Inputs and outputs interface directly with TTL,
• Compatible with DIA converters using any logic NMOS and TTL devices_
code

PIN CONFIGURATIONS
(25C02)
DO
(25~03) 1 0

KS25C02
AND
KS25C03
KS25C04

c8 SAMSUNG SEMICONDUCTOR 586

KS25C02lKS25C03/KS25C04 CMOS INTEGRATED CIRCUIT·

LOGIC DIAGRAM
DO
(25C02.
25C04 07(11) 06(10) 00 ace
CP~·2
~.,

NOTE 1: Cell logic is repeated for register stages 05 to 01 KS25C02, KS25C03

2: Numbers in parenthesis are for KS25C04

TRUTH TABLE
Time Inputs Outputs'
II
tn 0 S E2 003 07 Q6 QS Q4 Q3 Q2 Q1 ao ace ~
0 X L L X X X X X X X X X X
1 07 H L .X L H H H H H H H H
2 06 H L 07 07 L H H H H H H H
3 05 H L 06 07 06 L H H H H H H
4 04 H L 05 07 06 05 L H H H H H
5 03 H L 04 07 06 05 04 L H H H H
6 02 H L 03 07 06 05 04 03 L H H H
7 01 H L 02 07 06 05 04 03 02 L H H
8 00' H L 01 07 06 05 04 03 02 01 L .H
9 X H L 00 07 06 05 04 03 02 01 00 L
10 X X L X 07 06 05 04 03 02 01 00 L
X X H X H NC NC NC NC NC NC NC NC

NOTES:
1: Truth table for KS25C04 is extended to include 12 outputs.
2: Truth table for KS25C02 does not include E column or last line in truth table shown.
3: Truth table for KS25C03 does not include 00 column.
H = High Voltage Level
L = Low Voltage Level
X = Oon't Care
=
NC No Change

cIS SAMSUNG SEMICONDUCTOR 587

KS25C02lKS25C03lKS25C04 CMOS INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Supply Voltage Vee -0.5 - +7 V

DC Input Diode Current ItK ±20 mA
DC Output Diode Current 10K ±20 mA
Continuous Output Current Per Pin 10' ±35 mA
Continuous Current Through Vee or GND Pins ICON ±125 mA
Power Dissipa,ion Per Package Po 500 mW
Operating Temperature Top, 0-+70 ·C
Storage Temperature TS'g -55 -+125 ·C

DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Conditions)

Characteristic " Symbol Test Conditions Min Typ Max Unit

Operation Voltage Vcc 4.5 5.0 5.5 V

High-Level Input Voltage VIH Vee = Min 2.0 - Vee V
Low-Level Input Voltage VIL Vee = Min 0 - 0.8 V
Vcc = Min, VIN = VIH or VIL
High-Level Output Voltage VOH 10= -20p,A Vcc-0.1 - Vee V
10= -4mA 2.4 - Vee V
Vee = Min, V'N = VIH or VIL
Low-Level Output Voltage VOL 10 = 20p,A 0 - 0.1 V
10 = 9.6mA 0 - 0.4 V
Low-Level Input Current IlL Vcc = Max, VIL = 0.4V - 0.5 " 1.0 p,A
High-Level Input Current IIH V~e = Max, VIH = 2.4V - 0.5 1.0 p,A
Supply Current Icc Vee = Max, VIN = Vee or GND - 1.0 10.0 p,A

AC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Conditions), CL=15pF "

Characteristic Symbol Test Conditions Min Typ Max Unit

Propagation Delay to a Logical "0"

tpDO 10 18 28 ns
from CP to any Output
Propagation Delay to a Logical "0" CP high, Slow,
from E" to 07(011) Output "
tpDO
kS25C03, KS25C04 only
- 15 24 ns"

Propagation Delay.to a Logical "1"

tpO"' 10 20 38 ns
from CP to Any Output
Propagation Delay to a Logical "1" CP high, Slow,
from E" to 07(011) Output
tpo,
KS25C03, KS25C04 only
- 12 19 ns

Data Input Setup Time ts(O) -10 4 8 ns

Start Input Setup Time ts(s) 0 5 10 ns
Minimum Low CP Width tPWL - 5 20 ns
Minimum High CP Width tPWH - 1.5 20 ns
Maximum Clock Frequency fMAX - - 25 MHz

c8 SAMSUNG SEMICONDUCTOR 58a

KS25C02lKS25C03/KS25C04 CMOS INTEGRATED CIRCUIT

TIMING DIAGRAMS
KS25C02, KS25C03, KS25C04

CP

{
INPUTS : ~

07-L____ ~ ____________________________ ~ _____________________

06
-'-----'
05

04

03
OUTPUTS

02

01

00

Occ
II
l DO

APPLICATION iNFORMATION
Operation clock low-to-high transition in order to guarantee cor-
rect resetting. After the clock has gone high resetting
The registers consist of a set of master latches that act
the register, the S signal must be removed. On the next I
as the control elements in the device and change state clock low-to-high transition tl:le data on the D input is
on the input clock high-to-Iow transition and a set of set into the 07(11) register bit and the 06(10) register
slave latches that hold the register data and change on bit and 05(9) is set to a low. This operation is repeated
the input clock low-to-high transition. Externally the
for each register bit in turn until the register has been
device acts as a special purpose serial-lo-parallel con-
filled. When the data goes into 00, the Occ signal goes
verter that accepts data at the 0 input of the register
low, and the register is inhibited from further change
and sends the data to the appropriate slave latch to until reset by a Start signal.
appear at the register ,output and the DO output on the
KS25C02 and KS25C04 w!1en the clock goes from low- The KS25C02, KS25C03 and KS25C04 have a specially
to-high. There are no restrictions on the data input; it tailored two-phase clock generator to provide non-
can change state at any time except during a short in- overlapping two-phase clock pulses (i.e., the clock
terval centered about the clock low-to-high transition. waveforms intersect below the thresholds of the gates
At the same time that data enters the register bit the they drive). Thus, even at very slow dV/dt rates at the
next less significant bit register is set to a low ready clock input (such as from relatively weak comparator
for the next iteration. outputs), improper logic operation will noi result.
The register is reset by holding the.S (Start) signal low Logic Codes
during the clock low-to-high transition. The register syn-
chronously resets to the state 07(11) low, and all the All three registers can be operated with various logic
remaining register outputs high. The Occ (Conversion codes. Two's complement code is used by offsetting
Complete) signal is also set high at this time. The S the comparator 1/2 full range + 1/2 LSB and using the
signal should not be brought back high until after the complement of the MSB (07 or 011) with a binary DIA

.ciS SAMSUNG SEMICONDUCTOR 589

KS25C02lKS25C03lKS25C04 CMOS INTEGRATED CIRCUIT

APPLICATION INFORMATION (Continued)

converter. Offset binary is used in the same manner but tion of ace and the appropriate register output.
with the MSB (07 or (11). BCD D/A converters can be
used with the addition of illegal code suppression logic.
Comparator Bias
To minimize the digital error below ± 1/2 LSB, the
Active High or Active Low Logic . comparator must be biased. If a D/A converter is used
The register can be used with either D/A converters that which requires a low voltage level to turn on, the com-
require a low voltage level to turn on, or D/A converters parator should be biased + 1/2 LSB: I! the D/A converter
that require a high voltage level to turn the switch 'on. requires a high logic level to turn on, the .comparator
I! D/A converters are used which turn on with a low logic must be biased -1/2, LSB.
level, the resulting digital output from the register is
Definition of Terms
active low. That is, a logic "1" is represented as a low
voltage level. I! D/A converters are used that turn on with CP: The clock input of the register.
a high logic level then the digital output is active high; 0: The serial data input of the register.
a logic "1" is represented as a high voltage level.
DO: The serial data out. (The D input delayed one bit).
Expand,d Operation
An active low enable 'input, E, on the KS25C03 and
E: The register enable. This input is used to expand the
length of the register and when high forces the 07 (11)
KS25C04 allows registers to be connected together to
register output high and inhibits conversion. When not
form a longer register by connecting the clock, D, and used for expansion the enable is, held at a low logic level
S inputs in parallel and connecting the ace output of
(ground).
one register to the E input of the next less significant
register. When the start resets the register, the E signal Q 1 1= 7(11) to 0: The outputs of the register.
goes high, forcing the a7 (11) bit high and inhibiting the Q cc : The conversion complete output. This output re-
register from accepting data until the previous register
mains high during a conversion and goes low when a
is full and its ace goes low. I! only one register is
conversion is complete.
used. the E input should be held at a low 10gic'Ievei.
,07(11): The true output of the MSB of the register.
Short Cycle
07(11): The complement output of the MSB of the
I! all bits are not required, the register may be truncated
register.
and, conversion time saved by using a register output
going low rather than the ace signal to indicate the S: The start input. If the start input is held low for at
end of conversion. I! the register is truncated and least a clock period the register will be reset to 07(11)
operated in the continuous conversion mode, a lock-up low and all the remaining outputs high. A start pulse
condition may occur on power turn-on. This condition that is low for a shorter period of time can be used if
can be avoided by making the start input the OR func- it meets the set-up time requirements of the S input.

TYPICAL APPLICATIONS
BCD ILLEGAL CODE SUPPRESSION

s o S
DO DO
CLOCK CP KS25C02
CLOCK CP KS25C02 Qcc
Qcc
Q7Q6Q5Q4Q3Q2Q1QO Q7Q6Q5Q4Q3Q2Q1QO

OIA CONVERTER OIA CONVERTER

ACTIVE HIGH ACTIVE LOW

c8 SAMSUNG SEMICONDUCTOR 590

·KS25C02lKS25C03/KS25C04 CMOS INTEGRATED CIRCUIT

FAST PRECISION AID CONVERTER

100
BIPOLAR
.y. 100K
100
f;~~UNIPOLAR)
-15V
0

BIPOLAR OFF
~+- ____ ~ ____________________ ~8__- - .

11
: } ANALOG INPUTS
R2
100 9.95K
15V 5V

1K

-15V
I
1 9
11 DATA IN
CONY COMP o---::---fCC
SERIAL OUT o----:'---i 14 START
CLOCK

INPUT RANGES

UNIPOLAR BIPOLAR CONNECT EQUIV. DAC louT

o to 10 ±5 Input to A 2.36KO
o to 5 ±2.5 Input to A 1.90KO
o to 20 ±10 Input to B 3.08KO
B to DAC OUT

c8 SAMSUNG SEMICONDUCTOR 591

KS25C02lKS25C03/KS25C04 CMOS INTEGRATED CIRCUIT

SWITCHING TIME WAVEFORMS'

AT LEAST AT LEAST

CP
- - - - - r - - - - 1,5V

tSID) MIN

tpoo MAX
tpoo MIN
tpDI MIN

07(11) 1,5V
tpDO MAX

tp01 MAX. tpDO MIN

06(10) -1,5V

tpD1 MIN tpD1 MAX

DO
. KS25C02, -1.5V
KS25C04

tpDO MIN

E
KS25C03,
KS25C04

07(11)
1J , , ,", . ~i 1.5V

ENABLE TO 07(11)'
CP=H
S=L
1.5V

WAVEFORMS INPUTS OUTPUTS

-- Must be steady Will be steady

--
~
May change from Will be changing
H to L from H to L

iZlT May change from

LtoH
Will be changing
from L to H

Don't care: any

5 change permitted
Changing: state
unknown

c8 SAMSUNG SEMICONDUCTOR 592

KA33V LINEAR INTEGRATED CIRCUIT

SILICON MONOLITHIC BIPOLAR INTEGRATED

TQ.92
CIRCUIT VOLTAGE STABILIZAER FOR
ELECTRONIC TUNER
The KA33V is a monolithic integrated voltage stabilizer especially
designed as voltage supplier for electronic tuners.

FEATURES
• Low Temperature Coefficient
• Low Dynamic Resistance
• l\tplcal Reference Voltage of 33V

ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)

Characteristic Symbol Value Unit

1: Anode 2: Cathode
Zener Current Iz 10 mA
Power Dissipation (T. = 75°C) PD 200 mW
Operating Ambient Temperature-
Topr -20-75 °C
Range
Storage Temperature Range Ts.g -40-125 °C

ELECTRICAL CHARACTERISTICS (Ta =25°C)

Characteristic Symbol Test Conditions Min Typ Max Unit

II
Stabilized Voltage Vz Iz=5mA 31 35 V
Stabili;:ed Voltage·Temperature Drift 6Vz/6T Iz=5mA -1 0 1 mV/oC
T.=-20t075°C
Dynamic Resistance rz Iz=5mA, f=1KHz 10 25

SCHEMATIC DIAGRAM
2 Cathode

R4

~r 01

~ 02
~,.. 03

~,.. 04

*05
r-. 03
R3
VOl!
/" .
I. 01
R2 ~Rl " .

1 Anode

c8 SAMSUNG SEMICONDUCTOR 595

KA33V LINEAR INTEGRATED CIRCUIT

MEASURING CIRCUITS
Measuring Circuit for Stabilized Voltage Vz
---lz=5mA
.----~ A ~----~ ______~________~

. V IIoR Meter
KA33V

Measuring Circuit for Dynamic Resistance

Iz-- IZ
----lAC-To

. 5O~F 100

c
0.1,.1'
WI

EB

vz

o.smA
WI
rz= a.5mA 1--+-+--'" SmA

Iz
VV1

c8 SAMSUNG SEMICONDUCTOR 596

KA33V LINEAR INTEGRATED CIRCUIT
TYPICAL APPLICATION
Ych Zch

RI

C
Channel
setting
variable
resistor
15KI!

• to luning dlod88 (varaclor) In cue or Ych on

(1) UHF TUNER

II
TRI TR2

-( -(
TRI: RF AMP: KSC1393
KSC1070 (Under development)
TR2: osc: KSC1730 ~ OAFC
terminal
01·04: 18220 05: MIXER: 18818

(2) VHF TUNER

-(
TR3

TR2

TR1: RM AMP: KSC1393

TR2: MIXER : KSC1394
TR3: osc : KSC1730 ~ 0
.01,04: 182209 AFC terminal
02, 03: 182207

cB SAMSUNG SEMICONDUCTOR 597

KA33V LINEAR INTEGRATED CIRCUIT
POWER·TEMPERATURE DERATING CURVE TYPICAL CHARACTERISTIC CURVES (Ta=25"C)

ALLow\BLE DISSIPATION YS. DYNAMIC RESISTANCE va.

AMBIENT TE.MPERATURE ZENER CURRENT
60

,
60
FR1AIR
\ T.=+25'C
40 I",.-\--

I~
"I '.1KHz -
I'l ~
0 ~ 20

I~ ~
II

I
10
6
"" r-...

~
I
6

4
==
2
-20 25 50 75 2 4 6 10
T. - AMBIENT TEMPERATURE - ·C . Iz -;- ZENER CURRENT -mA

STABILIZED VOLTAGE TEMPERATURE STABILIZED VOLTAGE VARIATION

DRIFT va. ZENER CURRENT va. TIME

FREE AIR
~Z~~~1V -

1
, 1-0

IT'}
0
Iz==5mA XY-RECODER
1

1 , . ·r"
2 1--. t - -

3 r--- r---
4

4 6 10 10 15 20304050 1 10 20 30
Iz - ZENER CURRENT - mA min.
STABILIZED VOLTAGE VARIATION It TTlme
SUPPLY VOLTAGE VARIATION YS.
ZENER CURRENT

-1DL-____ ~ ____ ~ _____ L_ _ _ __ L_ _ _ _ ~

10
lz - ZENER CURRENT - rnA

c8 SAMSUNG SEMICONDUCTOR 598

KA2580A1KA2588A LINEAR INTEGRATED CIRCUIT

18 DIP
8-CHANNEL SOURCE DRIVERS
These integrated circuits, rated for operation with output voltages of up
to 5fN and designed to link NMOS logic with high-current inductive loads,
will work with many combinations of logic-and load-voltage levels, meet-
ing interfacll requirements beyond the capabilities of standard logic
buffers.
KA2580A is a high current source driver used to switch the ground ends
of loads that are directly connected to a negative supply. Typical loads
are telephone relays, PIN diodes, ·and LEOs.
20 DIP
KA2588A is a high-current source driver similar to KA258OA, has separ-
ated logic and driver supply lines. Its eight drivers can serve as an inter-
face between positive logic (TTL, CMOS, MOS) or negative logic
(NMOS) and either negative or split-load supplies.
KA2580A is furnished in 18-pin dual in-line plastic package; KA2588A
is supplied in a 2O--pin dual in-line plastic package. All input connections
are on one side of the packages, output pins on the other, to simplify
printed wiring board layout.

FEATURES
• TTL, CMOS, PMOS, NMOS Compatible

I
• High Output Current Ratings
• Intemallnlnslent Suppression
• Efficient Input/Output Pin Structure

SCHEMATIC DIAGRAM

NC
SUB/VEE SUBIVEE

KA21i8OA KA2588A

c8 SAMSUNG SEMICONDUCTOR 599

KA258oA1KA2588A LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

(T.=25°C, for Any One Driver unless otherwise noted)

Characteristic Symbol value Unit

Output Voltage Vee 50 V

Supply Voltage (ref, sub) Vs 50 V
Supply Voltage (ref, sub, KA2588A) Vee 50 V
Input Voltage (ref, Vs) VIN -30 V
Total Current lee+ls -500 mA
Substrate Current ISUB 3.0 A
Power Dissipation (single output) Pel 1.0 W
(total Package)' 2.2 W
Operating Temperature T. -20-+85 °C
Storage Temperature lStg -65- +150 °C

, Derate at the rate of 18mWI"C above 25°C

TYPICAL OPERATING VOLTAGE

Vs VIN(on) VIN (off) Vee Vee (max) DVCType

OV -15V- -3.6V -0.5V- OV NA -50V KA2580A

--
NA -45V KA2580A
+5V OV- +l.4V +4.5V;" +5V
s5V -45V KA2588A
NA -38V KA2580A
+12V OV- +8.4V + 11.5V- + 12V
s12V -38V KA2588A
NA -35V KA2580A
+15V OV- +11.4V + 14.5V - + l'5V
s15V -3SV KA2588A

Notes
1) For simplicatlon, these devices are characterized to the above with specific voltages for inputs, 'logic supply (V.), load
, supply (VeEJ, and coliector supply (Vee). '
2) Typical use of the KA2580A is with negative referenced logic. The more common application of the KA2588A is with positive
referenced logic supplies.' '
3) In application, the devices are capable of operation over a wide range of logic and supply voltage levels. ,
4) The substrate must be tied to the most negative point In the external circuit to maintain Isolation drivers and ~o provide
for normal circuit operation.

,c8 SAMSUNG SEMICONDUCTOR 600

KA2580A1KA2588A LINEAR INTEGRATED CIRCUIT

PARTIAL SCHEMATIC (KA2580A)

IN o---llN_4-f
10K

'-----+-_OUT
+Vs SUBJVee

SUB

ELECTRICAL CHARACTERISTICS (KA2580A)

(T. =2S0C, Vs -rN, Vee" -45V unless otherwise noted)

Characteristic Symbol Test Conditions Min Max Unit

vln=-o.sv,
SO pA
VOUT -Vee - -SrN
Output Leakage Current Icex VIN;" -0.4V,
100 pA

I
VouT-Vee - -SOY
T.=70oC
Output Sustaining Voltage
Vce (sus) VIN=-0.4V,loUT=-2SmA 3S V
(Note 1, 2)
VIN=-2.4V,loUT=-100mA 1.8 V
Output Saturation Voltage Vce (sat) VIN --3.rN,louT --22SmA 1.9 V
VIN --3.av, louT=-3S0mA 2.0 V
VIN--3.av,loUT=-3S0mA -SOO pA
IIN'(on)
Input Current VIN=-1SV,louT=-3S0mA -2.1 mA
lOUT- -SOOpA, T.=70oC
liN (off) -SO pA
(Note 3)
louT=-100mA, Vce:S1.av -2.4 V
Input Voltage VIN(on) louT--22SmA, Vce:s1.9V -3.0 V
(Note 4) louT=-3S0mA, Vce:s2.OV -3.6 V
VIN(off) loUT=-500pA, T.=7QOC -0.2 V
Clamp Diode Leakage Current IR VR-SrN, T.-70oC SO pA
Clamp Diode Forward Voltage Vf If-3S0mA 2.0 V
Input Capacitance CIN 2S pF
Turn-On Delay tPHL O.S VIN to O.S VOUT S.O ,.S
Turn-Off Delay tPLH O.S VIN to O.S VOUT 5.0 ,.8
Notes
1) Pulsed test, tp:s300uS, duty cycle:s2%.
2) Negative current Is defined as coming out of specified device pin.
3) The lin (off) current limit guarantees against partial turn-on of the output.
4) The Yin (on) voltage limit guarantees a minimum output source per the specified conditions.
5) The substrate must always be tied to the most negative point and must be at least 4.rN below Ve.

c8 SAMSUNG SEMICONDUct'OR 601

 KA2580AlKA2588A LINEAR INTEGRATED CIRCUIT

PARTIAL SCHEMATIC (KA2588A)

+vs vee

.7.2K
IN ........,.,.-+-t
10K

'------:t- OUT

SUB
.' ELECTRICAL CHARACTERISTICS (KA2588A)
(T.=25·C, Vs=Vee=5.0V, VEE =-40V unless otherwise noted)

Characteristic Symbol Test Conditions Min Max Unit

V,N 2: 4.5V, VOUT=VEE=-45V 50 pA

Output Leakage Current leEX Y'N 2: 4.fN, VOUT =VEE = -45V
100 pA
T.=70°C
Output Sustaining Voltage
VCE (sus) V'N2::4.6V,loUT=-25mA 35 V
(Note 1, 2)
Y'N =2.6V, louT = -100mA
1.8 V
Ref. Vee
V'N=2.0V,loUT= -225mA
Output Saturation Voltage VeE (sat) 1.9 V
Ref. Vce
Y'N "'1.4V, louT'" -350mA
2.0 V
Ref. Vce
V'N=1.4V,loUT=-350mA -500 pA
liN (on) Vs=15V, VEE =-30V,
Input Current -2.1 mA
Y'N =OV, lOUT'" -350mA
louT=-500pA, T.=70oC
liN (off) -50 pA
(Note 3)
IOUT= -100mA, VcE s1.8V 2.6 V
Input Voltage (Note 4) V'Nton) IOUT=-225mA, Vces1.9V . 2.0 V
louT=-350mA, VeEs2.0V 1.4 V
V,N(of!) IOUT=-500pA, T,.,=7O"C 4.8 V
Clamp Diode Leakage Current IR VR=5QV, T.=7QOC 50 pA
Cla!11P Diode Forward Voltage Vf ;' If=350mA 2.0 V
Input Capacitance C,N 25 pF
Tur'n-On Delay tpHL 0.5 Y,N to 0.5 Vout 5.0 ,.8
Turn-Off Delay tPLH 0.5 Y'N to 0.5 Vout 5.0 ,.S
Notes
1) Pulsedtest,"tps300uS, dutycycles2%.
2) Negative current is defined as coming out of specified device pin.
3) The lin (off) current limit guarantees against partial turn-on of the output.
4) The Yin (on) yoltage limit guarantees a minimum output source per the specified conditions.
5) The substrate must always be tied to the most negative point and must be at least 4.0V below·V•.
6) Vee must never be more positive than Vs.

c8 SAM8UNG ~EMICONDUcroR 602

KA2580Al2588A LINEAR INTEGRATED CIRCUIT

ALLOWABLE PEAK COLLECTOR CURRENT ALLOWABLE PEAK COLLECTOR CURRENT AT 7O·C AS

AT 50·C AS A FUNCTION OF DUTY CYCLE A FUNCTION OF DUTY CYCLE
500
I'

=d
5l 450 I'
51450
!( !(
1
z
400 ~ 400
1!:

I:
RECOMMENDED MAXIMUM OUTPUT CURRENT
!z35O
\ ~\ ~
u

~250
I!!
B300
~ 250
I"\'0 ~ ~ r---...
~
" 3.......

~ 200
I
CONDUCTING
. SIMULTANEOUSLY
j
. NUMBER OF OUTPUTS
w
~ 200 - NUMBER OF
CONDUCTING
OUTP~ ~."'s
.
~ ""'-
~~ t:--. ........... r..:::
.
~ 150 ~ 150 -SiMU~NEOUSLY r--- - 8

f:
I I
__ Vs=15V 0- r---- ;;;- ts
r::
~ys=15V
KA2580A KA2580A ~
KA25B8f , KA2588A

0L-.~'0~~20~~~~~~~~5~0~OO~~~~~OO~~9~0-'~00% :;I 0
o 10 20 30 40 50 60 70 80 90 100%
PER CENT DUTY CYCLE
PERCENT DUTY CYCLE

TYPICAL APPLICATIONS
+12V KA258BA KA258BA

111
I

Vacuum Fluorescent Display Driver (Split Supply) Telecommunicaiton Relay Driver (Positive Logic)

Telecommunication Relay Driver (Negative Logic)

c8 SAMSUNG SEMICONDUCTOR
•
603
KA2651 LINEAR INTEGRATED CIRCUIT.

FLUORESCENT DISPLAY DRIVERS

18 DIP
Consisting of eight NPN Darlington output stages and the associat-
ed common-emitter Input stages, these drivers are designed to Inter-
face between low-level digital logic and vacuum fluorescent displays.
KA2651 is capable of driving the digits and/or segments of these dis-
plays and Is designed to permit all outputs to be activated simultane-
ously. Pull-down resistors are Incorporated into each output and no ex-
ternal components are required for most fluorescent display applications.

FEATURES
• Digit or Segment Drivers
• Low Input Current
• Intemal Output Pull-Down Resistors
• High Output Breakdown Voltage
• Single or Split Supply Operation

BLOCK DIAGRAM

c8 SAMSUNG SEMICONDUCTOR 604

KA2651 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS

(Ta = 25·C, Voltage are with reference to ground unless otherwise noted)

Characteristic Symbol Value Unit

Supply Voltage Vee 65 V

Input Voltage VIN 20 V
Output Current lout -40 rnA
Operating Temperature Ta -20 +85 ·C
Storage Temperature T.tg -65 + 150 ·C

RECOMMENDED OPERATING CONDITIONS

Characteristic Symbol Value Unit

Supply Voltage Vee 5.0-50 V

Input ON Voltage VIN 2.4-15 V
Output ON Current" loutON -25 rnA
" Positive (negative) current Is defined as going into (coming out of) the specified device pin.

ELECTRICAL CHARACTERISTICS
(Ta = 25°C, Vee = 60V, VEE = OV unless otherwise noted.)

Characteristic Symbol Test Conditions Min Typ Max Unit

I
Output Leakage Current louTLK VIN =0.4V 15 p.A
Output OFF Voltage VOUTOFF VIN=0.4V 1.0 V
Output Pull·Down Current louTPo Input Open, VOUT = Vee 350 500 775 p.
Output ON Voltage VOUTON VIN = 2.4V lOUT = - 25mA 57 58 V
VIN=2.4V 120 225 poA
Input ON .Current liN
VIN=5.0V 375 650 p.A
lee All Inputs Open 10 100 p.A
Supply Current
All Inputs = 2.4V 5.5 8.0 mA

c8 SAMSUNG SEMICONDUCTOR 605

 ·KA2651 LINEAR INTEGRATED CIRCUIT

PARTIAL SCHEMATIC
,-------,.------.---0 Vee

10K
I NPUT o----'w..-----t-~--I
'----+--'-Q OUTPUT

125K

GNDo-------~~--~----------~

(One Driver)

TYPICAL MULTIPLEXED FLUORESCENT DISPLAY

Vee
SEGMENT SELECT (
KA2651

b-1 " t;a

I~ I~
~ Ff7
a-~
f-~
":::: ~ I
~
Fit ~
9-4
~~I-
e-~ Ftt
d-~ ~
~

L!J r
c-~
d p-~ ttt
~
r,)
. 9 FTIlr-

DIGIT SELECT
-----------
-----------
T
KA2651 --------
...,
" ---------- 0
o1 - 1 -" 18 ----- ,------0
o2-~ .'7 F;7 --
o3 -- ~
...fLoo
4-~
5 -~
Ff6 r-f-------
~ r-r------
~ r-r-----
{"
o6 --~
F,3 r- f-------- VBIAS
·07 '12 6
. ~ VFI
·08 --~ ~
9 Vm Ff& r--

. ciS SAMSUNG SEMICONDUCTOR 606

KA2803 LINEAR INTEGRATED CIRCUIT

LOW POWER CONSUMPTION EARTH

LEAKAGE DETECTOR 8 DIp·

The KA2803 is designed for use in earth leakage circuit interrupters, for
operation directly off the AC line in breakers. The input of the differen-
tial amplifier is connected to the secondary coil of ZCT (Zero Current
Transformer). The amplified output of differential amplifier is integrated
at external capacitor to gain adequate time delay that is specified in
KSC4613.
The level comparator generates high level when earth leakage current
is greater than some level.

FUNCTIONS
• Differential amplifier
• Level camparator
• Latch circuit

FEATURES
• Low power consumption (P. =5mW, 100Vl200V)
• Built-in voltage regulator
• High gain differential amplifier (VT =13.5mV)
•
•
•
•
•
1mA output current pulse to trigger SCR'S
Low external part count, economic
Mini-dip package (8 Dip), high packing density
High noise immunity, large surge margin
Super temperature characteristic of input sensitivity
I
• Wide operating temperature range (1. = -25°C - +80 0 C)

APPLICATION CIRCUIT

1. Full wave Application Circuit 2. Half wave Application Circuit

LOACo LOAD

( ____ '[ _. _______.____________________ J

Fig. 1 Fig. 2 .

.c8 SAMSUNG SEMICONDUCTOR 607

KA2803' LINEAR INTEGRATED CIRCUIT

. ABSOLUTE MAXIMUl\II RATINGS (Ta = 25°C)

Characteristic Symbol value Unit'

Supply Voltage VccfVee 20 V

Supply Current Is 8 mA
Power Dissipation . Po 300 mW
Lead Temperature (soldering 10 sec) T'e'" 260. °C
Operating Temperature Topr -25- +80 °C
Storage Temperature T.tg -65-+150 °C

ELECTRICAL CHARACTERISTICS (Ta =25°C)

Characteristic Symbol Test Conditions Min ~p Max Unit

Vee =12V (-25°C) 580 pA

Supply Current 1 Is, VA.lJ, =3oomV (25°C) 400 530. pA
(80°C) 480 pA
Vee -16V (-25°C - 800C)
Trip Voltage 10 13.5 17 mVrms
VA.lJ,=X
------
Vee ... 16V (25°C)
Differential Amplifier Output
Iro, VA.lJ,=30mV 12 30 pA
Current 1
- ,-_ ... _.._-
Voo-1.2V
Vee-16V (25°C)
Differential Amplifier Output
ITo2 Voo-O.6V 17 37 pA
Current 2
VA~ V, short
_. - --- -----_.
Vse-1.4V
Vos=O.6V
Output Current 10 Vee .. 12V (-25°C) -200 pA
(+25°C) -100 pA
...
(+800C) -75 pA
Latch on Voltage Vocon Vee .. 16V (25°C) 0.7 1.4 V
Latch Input Current I",on Vee =12V (25°C) 5 pA
Vec.12V (-25-8OOC)
Output Low Current 10SL 200 pA
~
VosL=O.2V
Dllf. Input Clamp Voltage "DC -1oomA (-25 - 800C) 0.4 2 V
- .. V'De
Maximum Current Voltage VSM ISM" 7mA (-25°C) 20 28 V
VA.lJ,-X(25-800C)
Supply Current 2 IS2 900 pA
.-
vos-a.s
Latch Off Supply Voltage VooI' VOl'" high (25°C) 7.0 V
Vee =16V (25°C)
Response Time Ton 2 4 msse .
VA.lJ,-O.3V

c8 SAMSU~~ SEMICONDUCTOR 608

KA2803 LINEAR INTEGRATED CIRCUIT

APPLICATION NOTE·
(refer to full wave application circuit Fig. 1)
The Fig 1 shows the KA2803 connected in a typical leakage current detector system.
The power is applied to the Vee terminal (Pin 8) of the KA2803 directly from the power line.
The resistor Rs and capacitor Cs are chosen so that pin 8 voltage is at least 12V.
The value of Cs is recommended above 1pF at this time.
If the leakage current is at the load, it is detected by the zero current transformer (ZCT).
The output voltage signal of ZCT is amplified by the differential amplifier of the KA2803 internal circuit and appears as half-
cycle sine wave signal referred to input signal at the output of the amplifier.
The amplifier closed loop gain is fixed about 1000 times with internal feedback resistor to compensate for zero current trans-
former (ZCT) Variations.
The resistor RL should be selected so that the breaker satisfies the required sensing current.
The protection resistor Rp is not usually used put when the high current is injected at the breaker, this resistor should be used
to protect the earth leakage detector IC the KA2803.
The range of Rp is from several hundred Il to several kll.
The capacitor C, is for the noise canceller and standard value of C, is 0.0471'F. Also the capacitor C 2 is noise canceller
capacitance but it is not usually used.
When high noise is only appeared at this system 0.0471'F capacitor may be connected between pin 6 and pin 7.
The amplified signal is finally appeared to the Pin 7 with pulse signal through the internal latch circuit of the KA2803.
This signal drivies the gate of the external SCR which energizes the trip coil which opens the circuit breaker.
The trip time of breaker is decided by the capacitor C3 and the mechanism breaker.
This capacitor should be selected under 1pF for the required the trip time.
The full wave bridge supplies power to the KA2803 during both the positive and negative half-cycles of the line voltage.
This allows the hot and neutral lines to be interchanged.
If your application want the detail information, request it on our application circuit designer of KA2803.
I

c8 SAMSUNG SEMICONDUCTOR 609

 KA2804 LINEAR INTEGRATED CIRCUIT

ZERO VOLTAGE SWITCH

8 DIP
The KA2804 is a TRIAC controller providing a complete solution for tem-
perature controlled electric panel heaters, cookers, film processing baths
etc.
Switching occurs at the zero voltage point in order to minimize radio fre-
quency interference. The device is suitable for mains-on-line operation
- and requires minimal components.

FEATURES
• Easy operation either through the AC line or a DC supply.
• Supply voltage controL
• Very few-external components.
• Symmetrical burst control - No DC current compon,nts in the
load circuit.
• Negative output current pulse up to 250mA-short circuit pro-
/ tection.
• Reference voltage output.

BLOCK DIAGRAM

Vs IS 1--~---~4' ~9.tt'::NV-

1 - - - - - - 1 3 I~XUT

GND

AC VSYN ISYN~
INP.UTo--"'4~----(1
RSVN

REFERENCE 1---,( 1 06EwE

VOLTAGE OUTPUT

Vo Lo

c8 SAMSUNG SEMICONDUCTOR 610

KA2804 LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Ta=25°C)

Characteristic Symbol Value Unit

Supply Voltage -Vs 8.2 V

Supply Current -Is 40 (average) mA
Synchronous Current IsvN 5.0 (rms) mA
Input Voltage VI ~IVsl V
Power Dissipation Po 350 mW
Junction Temperature TJ 125 °C
Operating Ambient Temperature Top, -20-+70 °C
Storage Temperature TSIg -65-+150 °C

ELECTRICAL CHARACTERISTICS
(Vs=8.0V, VSVN =100 to 115V,ms, Ta =25°C, f=50/60Hz, unless otherwise specified)

Characteristic Symbol Test Conditions Min Typ Max Unit

Circuit Current -I~ Pin 5, RSVN =56K - 2.0 2.5 mA

I
Pin 5, Is=2.5mA
Supply Voltage 1 -Vs 1
RSVN =56K
7.2 - 8.4 V
~-

Pin 5, Is=20mA
Supply Voltage 2 -Vs2
RSVN=56K
7.2 - 8.6 V

Synchronous Current IsvN Pin8 0.3 - - mA

Output Pulse Width Tp Pin 6, RSVN =56K - 200 - ,.s
Output Voltage Vo Pin 6, 10~200mA 4.2 5.2 - V
Output Current 10 Pin 6, Ro~25 200 250 - mA
Output Leakage Current ILO Pin6 - - 2.0 pA
Input Offset Voltage VIO Pin3,4 - 2.0 5.0 mV
Input Bias Current II Pin 3, 4 - 0.5 1.0 pA
Common Mode Input
Voltage Range
-VICM Pin 3, 4 0 - 5.7 V

Output Leakage Current kc Pin2 - - 0.2 pA

Reference Voltage -VR Pin 1, IR~1uA - 3.6 - V

c8 SAMSUNG SEMICONDUCTOR 611

KA2804 LINEAR INTEGRATED CIRCUIT

APPLICATIONS
ON-OFF TEMPERATURE CONTROL fJC
.------4~-------------------------------- __~------------_.----_o10Wrms
SO/60Hz

NTC
7 Ro
56
KA2804

RH

VR

Rsyn
RH! HYSTERESIS VOLTAGE SET S6K
Rs
6.8K
ZW

. TIME PROPORTIONAL TEMPERATURE CONTROL AC

.-------------.....,----~--___.---------------------~--------------.,....--_o 100Vrms
SO/60Hz
RT 39K

RD
56
NTC 7

KA2804

Cl
Ci
..J

Rsyn
Rs S6K.
RT Cr TIMING PERIOD SET
6.8K
ZW

c8 SAMSUNG SEMICONDUCTOR 612

LM386/S/D LINEAR INTEGRATED CIRCUIT

LOW VOLTAGE AUDIO POWER AMPLIFIER

8 DIP
The LM386/SID is a power amplifier designed for use in low
voltage consumer applications. The gain is internally set to 20
to keep external part count low, but the addition of an external
r~sistor and capacitor between pins 1 and 8 will increase the
gain to any value up to 200.
The inputs are ground referenced while the output is automatically
biased to one half the supply voltage. The quiescent power drain is only 8 SOP
30 milliwatts when operating from a 6 volt supply, maldng the LM386 ideal
for battery operation.

FEATURES
• Battery operation. 9 SIP
• Minimum external parts.
• Wide supply voltage range: 4V -12V (LM386)
4V-9V (LM386S/D)
• Low quiescent current drain (4mA.)
• Voltage gains: 20 - 200.
• Ground referenced Input.
• Self-centering output quiescent voltage.
• Low distortion.
• 3 kinds of package types
LM386 (8 Dip), LM386S (9 Sip), LM386D (8 Sop)

ORDERING INFORMATION
Device
LM386N
Package
8 DIP
Operating Temperature
I
LM386S 9 SIP - 20·C - + 70·C
SCHEMATIC DIAGRAMS LM386D 8 SOP

GAIN GAIN

+INPUT
o: LEFT (LM386/D)
RIGHT (LM386S)

c8 SAMSUNG SEMICONDUCTOR 613

LM386IS/D LINEAR INTEGRATED CIRCUIT

CONNECTION DIAGRAM

(LM386ID) (LM386S)

lOP VIEW GAIN -IN +IN GND Vo Vee BY PASS GAIN

Fig. 2 Fig. 3

ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)

Characteristic Symbol Value Unit

Supply Voltage Vee 15 V

LM386 660
Power Dissipation LM386S Pd 500 mW
LM386D 300
Input Voltage V, ±0.4 V
Operating Temperature Topr -20-+70 ·C
Storage Temperature T"g -40-+125 ~C

ELECTRICAL CHARACTERISTICS
(T.=25·C, Vcc =6V, RL = 80, f=1KHi, unless otherwise sp.eclfied)

Characteristic Symbol Test Conditions Min Typ Max Unit

Quiescient Circuit Current Icc V,=O 4 8 mA

Vcc = 6V, THD=10% 250 325 mW
Output Power Po
Vcc=f!V, THD=10% 500 700 mW
Pins 1 and 8 Open 26
Voltage Gain (D·Type) Av dB
10",F from Pin 1 to 8 46
Pins 1 and 8 Open 300
Bandwidth (D·Type) BW KHz
10",F from Pin 1 to 8 60
Total Harmonic Distortion
THD Po = 125mW, Pins 1 and 8 Open 0.2 %
(O·Type).
Input Resistance R, 50 KO
Input Bias Current Ib Pins 1 and 8 Open 250 nA
. )

c8 SAMSUNG SEMICONDUCTOR 614

LM3861S/D LINEAR INTEGRATED CIRCUIT

TYPICAL APPLICATIONS (LM386ID)

Amplifier with Gain;:50 1(34' dB) Low Distortion Power Wienbridge Oscillator
390
vee
,lice 1,2K

ELDEMA
CF·S·2158
311-15mA
,
I Rl
I
I

RL =r=0'os"

Cl
tm I
10

1= 1
2"C1 VR1R2
Fig. 4 I:: 1KHzIAS SHOWN
Fig. 5

Square Wave Oscillator Amplifier with Bass Boost

vee
Vee

250#
I
1--"1
Vee ~----~--~,+~~r-~VO

1
I
>.:,.:.tIHf-_-GVO I
RL

RL
..l. 0.o5#

10

Fig. 6 Fig. 7
AM Radio Power AmpllTIer

81l
SPEAKER

Fig. 8

c8 SAM.SUNGSEM.ICONDUCTOR 615
LM386/S/D LINEAR INTEGRATED CIRCUIT

TOTAL HARMONIC DISTORTION-OUTPUT POWER TOTAL HARMONIC DISTORTION-FREQUENCV

10. 2.0
III 1.8
Vcc-6V Vcc_fN I
r- RL-BO
1
I::
RL_80
1. ,K Z - Po-126n'tN
A,.28dB cc.••0)

r:
~:
f-

1
/
II
I

l V
1

0.
I-
~ 0.4
0.. 2
"'-
-- 1"'- t--. V
0.
0.001 0.1 1.0
20 50 100 200 500 1K 2K 51< 10K 20K
~ (W): OUTPUT POWER I (Hz), FREQUENCY

VOLTAGE GAIN-FREQUENCY QUIESCENT CIRCUIT CURRENT-stIPPLY VOLTAGE

60

60 l,Hl~ 'i I'!;:!I

i 5 _r-
V1*O

! <40 it:
"
~
g 30 01.1.0
1\ ~
Il
4

~
~
:c 20
--~
I1
10. .l!

1
100 lK 10K lOOK 1M 10 11 12
I (Hz), FREQUENCY Vee (VI, SUPPLY VOLTAGE

OUTPUT VOLTAGE SWING-SUPPLY VOLTAGE :FREQUENCY RESPONSE WITH BASS BOOST

''0

26

4
1/ 1\
J r\
\
+f
1

1'- ............ .........

9

7
10 11 12
20 50 100 200 500 1K 2K 5K 10K 20K
Vee (V), SUPPLY VOLTAGE
t(Hz), FREQUENCY

c8 SAMSUNG SEMICONDUcroR 616

I
PACKAGE DIMENSIONS

TO·92 Unit mm TQ.92L Unit: mm

5.59
I 4.33 I
/
4.83
- I "
6.10
"
I
I '.
4.33 ------
I 4.83
8.25
8.75

~:::[ --, ~
2.16
13.97
14.97 ~3.22
II
13.00
14.02

~Il
0.56 I,

1.27TYP---jr---t--_-,:=2.5:;,:-4 g:: I!~I 3.00

I TYP 1.50TYP--!
TYP
3'46~n1'02 TYP
4'~1
/
3.96
5.15 '\ I /
. 1.80 2.39
3.35
3.85
TYP m
3.56 4.12
TYP
5.01

TO·3P

15.55 4.55
Unit: mm TO·220
1/J3.61
TYP...J
Unit: mm

~
.
II
1/J3.20 16.05 5.05 1.95 II 1.40
TYP 2.20 6.12
6.62

19.75
8.94
20.2~
9.44
o
37.66
o
1!.n""""F"'i""""'T"'F~-+3.27
38.68
0 3.97
4.23
3.53 2.08 12.72
2.79
3.04 2.33 13.48
1.75
2.25
0.45
I
0.88 0.55
1.14 It-..j
I 10.87
1----;;.~45;:.p -i I 0.55
0.71
TYP

c8 SAMSUNG SEMICONDUCTOR 619

, '

'"'PACKAGE DIMENSIONS

7 SIP Unit: mm 8 SIP Unit: mm

21.59 21.59
22.10 22.10

0 6.68
7.18 ~.~ 6.09
0 6.68
7.18 ~.~ 6.09

~ --t~~
3.30 3,30

~
TYP 0.71
1.27
1.78
3.81
--11 0.20
0.30 ~
TYP r- --II 0.45
0.71
I
~3.81
1.27
1.78
--11 0,20
0.30

c {~~~~3)]12,75
c: _ 3,25

9 SIP Unit: mm 10 SIP HIS Unit: mm

21.59
22.10 0,51
TYP

~.~
I~oo
a 6.09

7~,!
3.81
0.51
TYP
2.54 I ~-11 0.45 1.27 _11 0.20
TYP 0.71 1.78 0.30
~
TYP ~ 0.41
0.61

1]2.75 25.15
3.25 25.65

c8 SAMSUNG SEMICONDUCTOR 620

 PACKAGE DIMENSIONS

12 SIP HIS Unit: mm 8 DIP Unit: mm

R1.78
TYP ~t±r------:br1 0-10·
I I

.y~37
0.58 8.95
9.45
TYP

o 0 7.87

0.20 .
0.30

~
'~4.05
~ 4.55
- 2.92
254 _ 3.42
~~::::~:3CI3.25
L....~~~~:---~-111:-.l3.75
,- 29.35
29.85
.
TIP 6.361
0.56
IL 0.51
L----~1.0=2

12 DIP HIS Unit: mm 14 DIP Unit: mm

I
19.35 0-10·
19.85
I ~

4.83
5.33
0

I I~I
]09
6.60

1.02
1.52
dOI~
~
75

0.45

~1381
--L 4.31
3.30
3.81 2.92
/
~ ~ 0.36 I~ 0.5.1 3.43 0.51
TYP 0.56 1.02 1.02

c8 SAMSUNG SEMICONDUCTOR 621

PACKAGE DIMENSIONS

14 DIP HIS Unit mm 16 DIP Unit mm

0'-10·
0-10·
~2.10 :J- I I
~
19.15
19.65

II: : : : : : : ][~:~~
TYP [[E.37
7.87
5.74
1--t-6::':.2~4 0.35
;;;L,
r l!Lt~71
-~
0.45 ~f-
1.52
0.30
4.01 ~
1r--_-==-..,_-+---+-4.51 , r-------,-=-'-+'4.31

F+==Fr---f-3.83
4.33
0.51
}~
~ ~u ~U~Ui
2.92
3.43
0.51
1.02
R'0.79 1.02
TYP

16 DIP HIS Unit: mm 1,8 DIP Unit: mm

~-1
7'07' 4.85
27.57 5.35

~'3"
.::-:::-=t~~.51
4.31 -L

2.54 I I II 0.36
~ r- --; '0.56
TYP 0.56 1.02

c8 SAMSUNG SEMICONDUCTOR 622

 , .'

PACKAGE DIMENSIONS

20 DIP .unit: mm 22 DIP Unit: mm

, 26.36
26.87
" 0-1'0·
J I 26.36
26.87
I 0-10·
L- .
II: :0: :::: : ~ ]I]::~ O~ G~::::::~][: m]:;
~ I• 1.02
1.52
0.20 r
~0.~30-~ --11 1.02 7
0.20
1.52 *"0.30~~
3.81
4.31
~3.81
4.31
""'''''=='--'-2.92
3.43
0.51 254
TYP
II II
-----j~
n.,.. ~
3.43_0.51
1.02 0.56 _. _ _
1.02

24 DIP Unit: mm 24 SKINNY DIP Unit mm

I. 31.37 I 0-10·

[::~~::::~:n~~n:
. 7
.
1.02
1.52
~::: ~~~:::
I~
~ :~:~:
¥ ,
~0.2~0_--.J-,
0.30
,
~~
1.52
0.20
0.30

6iJOijQ~~ 4.57
VVVVVVVVVVVt
0.3~ ~
5.07
2.54
TYP
II- --11 o.J.1 3.43 0.51
1.02

c8 SAMSUNG SEMICONDUCTOR 623

PACKAGI: DIMENSIONS

28 DIP Unit: mm 28SDIP Unit: mm

I;~:~ I· 1-
~~::::::::~]f~
II
1.02
~
7 0.20
1.52 0.30

5.15
5.65

2.92
0.51 3.43 1.27
1.02
1.77

30 SDIP Unit:·mm 40 DIP Unit: mm

27.22 0-10·
27.72
~
.-L I
52.19
52.70
I 0-10·
l--

~~~~~~~~];a:~:
nnn

~::~::::::::::~::] !~~:~~ ~~~:~~

~~ ~ 1.52 0.30
.
. II 1.02
111:52 0.20
0.30

hooooonooooonoU 5.15 r--------,-+

~.

rrn VV11
5.07
rrmn~
~~ .~~ 1~ 1.27
5.65
~T2.92
I
r-- ----r---0:56 '---343
2.54
TYP
~u.JL·. 0.36
. 0.51
TYP 0.56 L-----:-;1.7=7
1.02

c8 SAMSUNG SEMICONDUCTOR 624

PACKAGE DIMENSIONS

40 SDIP Unit: mm 42 DIP Unit: mm

36.04
36.54
rno:fD
I ;;;gl· oJ:
mn

o
Ur
h3.34· 14.99
D0
[~:::::::::::~::U:~;
~3.84 15.49
1I;:;crn"jj"'i'ffi"jiEi!:jffi~11n:;;:;rn1-n:;!1.02·
1.52
o.~o
0.20
7 ~~ ¥ 0.20
1. 52 0.30

4.57
~~~~~~~~IIt~
~TU ~
254 II
~ I--
I 036
--j~ 3.43 0.51
1.02

8 SOP Unit: mm 14 SOP Unit: mm

I
0.41
~h-

0]
0.79 0.20 I 'j

~Tg:;~
==----.-
,37 6.10
. 4.62 ~ 6.60
o I O~

--JI 0.36
0.51

W!ih ,
II

,
1.47
1.73
0.36

051
--l~
1/ 0.20

~1.47
"
1.27
1.73

TYP
1.27
TYP i i

c8 SAMSUNG SEMICONDUCTOR 625

.PACKAGE DIMENSIONS

16 SOP Unit: mm 20 SOP Unit: mm

0.41
0.10 1H- 0.79
~ 0.2mi~lM!

~J1:~~ ~ it; ~:~ ~_ _ _f'i'i"'lill-L

6.86
7.11
mT ~
I 0.20
8.89
9.40

. 0.35 I~
0.51
-II 0.10
0.20

~I-- .
10:11

1.27
TYP
,
I
lil.47
1.73
W!Llr
--l
.. I
1.90
1.27
TYP

24 SOP Unit: mm 28 SOP Unit: mm

0.41
0.79 0.41

T I~0'79
(.::~:: ::::;]
7.54 9.73 7.54 10.18
7.80 0.10 10.24 7.79 0.10 10.69
0.20 0.20

. I '-II 0.35
0.51
I 0.10
0.20 I
.I~'
0.51 ~~0.30

ciS SAMSUNG SEMICONDUCTOR 626

PACKAGE DIMENSIONS

16 ZIP Unit: mm 19 ZIP Unit: mm

24.15
~I 24.65 I 6.86
7.36

2i1J[ 01
1.14 1~~~~~~~~n~~~~~~~~ g~ IT
I
1--_~22~.65::-_--I 2.92 -II
0.31
0.46
23.15 368 I
. ~
?<;A

TYP
2.85
2.85
~~
~f3.35
~OA1
TYP 0.61
~~ _II
TYP
0.41
0.61

T()'92
(KA33V On Iy) 458
Unit: mm
I
,, "
-------- 14.58
1 2

ill
14.5

It~-
1.27

!\ 11.02
3.56 \ 1 2 IJ
'/
3.60

1. Anode 2. Cathode

c8 SAMSUNG SEMICONDUCTOR 627

NOTE

•
SALES OFFICES/MANUFACTURER'S REPRESENTATIVES

1. U.S.A

SALES OFFICES ILLINOIS

. CALIFORNIA 901 Warrenville Rd.
Suite 120 UsIe, 60532-1359
201 East Sandpoint
Suite 220 Santa Ana 92707 312-852-2011
714-662-3406
TEXAS
2700 Augustine Drive
Suite 198 Santa Clara 95054 1 5851 Dallas Parkway
408-727-7433 Suite 745
Dallas 75248-3307
214-239-0754
MASSACHUSETTS NORTH CAROLINA
20 Burlington Mall Road 3200 Nothline Ave
Suite 205 Burlington 01803
617 -273-4888 Suite 501G
Forum VI Greensbor.o, 27408
919-294-5141

MANUFACTURER'S REPRESENTATIVES
ALABAMA COLORADO
EMA ELECTRODYNE
1200 Jordan Lane, Suite 4
2620 S. Parker Road
Jordan Center Suite 11 0 Aurora 80014
Huntsville 35805
303-695-8903
205-536-3044

ARIZONA CONNECTICUT
HAAS & ASSOC., INC. PHOENIX SALES
257 Main Street

II
7505 East Main
Suite 300 Torrington, 06790
Scottsdale 85252 203-476-7709
602-994-3813
GEORGIA
CALIFORNIA
EMA
SYN PAC 6695 Peachtree Industrial Boulevard
3945 Freedom Circle Suite 650 Suite 101 Atlanta 30360
Santa Clara 95054 404-448-1215
408-988-6988
WESTAR REP COMPANY FLORIDA
1 801 Parkcourt Place MICRO ELECTRONIC COMPONENTS
Suite 1030 Santa Ana 92701
714-835-4711 989 Woodgade Dr
QUEST-REP, INC. Palm Harbor, 33563
San Diego, CA. 813-784-8561
61 9-546-1 933
ILLINOIS
CANADA
IRI
TERRIER ELECTRONICS 8430 Gross POinte Road
145 The West Mall Skokie 60076
Etobicoke, Ontario M9C tC2 312-967-8430
416-622-7558

ciS SAMSUNG SEMICONDUCTOR 631 .

SALES OFFICES/MANUFACTURER'S REPRESENTATIVES

INDIANA OHIO
STB & AssociATES J.N. BAILEY & ASSOCIATES
3003 E. 96th $treet 1 3071 Old Dayton Road
Suite 102 Indianapolis 46240 New Lebanon 45345
311-844-9227 51>3-687-1325
1667 Devonshire Drive
MICHIGAN Brunswick'44212
C.B. JENSEN & ASSOC. 216-273-3798
2145 Crooks Road 2679 Indianola Avenue
Troy 48084 Columbus 43202
313-643-0506 614-262-7274

MARYLAND
PENNSYL VANIA
. ADVANCED TECHNOLOGY SALES
809 Hammonds Ferry
RIVCO JANUARY, INC.
Lithicum 21 090 78 South Trooper Road
301-789-9360 Norristown 1 9403
215-631-1414
MASSACHUSETTS
Contact local sales, office SOUTH CAROLINA
EMA
MINNESOTA 210 W. Stone Avenue
COMSTRAND INC Greenville, 29609
803-233-4637
2852 Anthong Lane South
Minneapolis, 55418
612-788-9234 TEXAS
VIELOCK ASSOCIATES
NEW JERSEY 720 E. Park Boulevard
NECCO Suite 102 Plano 75074
2460 Lemoine Avenue 2.14-881-1940
Ft. Lee 07024
201-4611-2789
UTAH
NEW MEXICO ELECTRODYNE
Contact local sales oIfie8 2480 South Main Street
Suite 1 09 Salt Lake City 8411 5
801-486-3801
NORTH CAROLINA
Contact local sales office
WISCONSIN
OREGON IRI
631 Mayfair
EARL & BROWN Milwaukee 53226
7719 S. W. Capitol Highway 414-259-0965
Portland 97219
603-245-2283
WASHINGTON
NEW YORK EARL & BROWN
NECCO 2447-A 15200 Avenue, N.E.
Redmond 98052
2460 Lemoine Avenue 206-885-5064
Ft. Lee 07024
201-4611-2789

.·cR SAMSUNG SEMICONDUCTOR 632

SALES OFFICES/MANUFACTURER'S REPRESENTATIVES

2. EUROPE

W/GERMANY ·BYTECH LTD

SILCOM ELEKTRONICS 2 The Westem centre,
Neusser Str. 336-338 Western Road.
D-4050 MOchengladbach Bracknell Berkshire RG121RW.
Tel: (02161) 60752 Tel: Sales 0344 482211,
TIx:852189 Accounts/Admin, 0344 424222
Tlx: 848215

MICRONETICS VERTRIEB5- RAPID SILICON

GESELLSCHAFT ELEKTRONISCHER Rapid House Denmrak Street
High Wycombe Buckinghamshire HP 11 2 ER
BAUELEMENTE and SYSTEME GmbH
Tel: 0494 26271;
Weil der Stadter StraBe 45 Sales hot line; 0494 442266
7253 Renningen 1 Tlx: 837931
Tel: (07159) 6019 Fax: 0494 21860
Tlx: 724708
STEATITE ELECTRONICS LTD.
ZEPHYR HOUSE WARING STREET.
ING. THEO HENSKES GmbH
WEST NORWOOD LONDON SE279 LH
Laatzener Str. 1 9 Tel: (01) 670-8663
Postfach 721226
Tlx: 892425
30000 Hannover 72 HAGLEY HOUSE HAGLEY ROAD
Tel: (0511) 865075
EDGBASTON BIRMINGHAM B168CW
Tlx: 923509 Tel: (021) 454-2655
Fax: 876004 TIx: 337046

ASTRONIC GmbH SWEDEN

Winzerer Str. 47d NORDISK ELEKTRONIK AB
8000 MOnchen 40 Huvudstagatan 1 Box 1409

I
Tel: (089) 309031 5-17127 Solna
Tlx: 521687 Tel: (08) 7349770
Fax: (089) 3006001 Tlx: 10547
Fax: (08) 272204

FRANCE . SWITZERLAND
ASiAMOS
PANATEL AG
Batiment EVOLIC 1
155, Boulevard de Valmy Hardstra8e 72
92705 Colombes, France . CH-5430 Wettingen Zurich
Tel: (1) 47601255 Tel: (056) 275275
Tlx: 61 3890F Tlx: 58068
Fax: (1) 47601582 Fax: (056) 271924

FINLAND
UNITED KINGDOM INSTRUMENTARIUM ELEKTRONIIKKA
KORD DISTRI.BUTION LTD. P.O. Box 64, Vitikka
Watchmoor Road, Cambertey SF-02631 Espoo, Helsinki
Surrey GU 153AC Finland
Tel: 0276 685741 Tel: (358) 05284~0
Tlx: 859919 KORDIS G. Tlx: 124426
Fax: (358) 0524986

c8 SAMSUNG SEMICONDUCTOR 633

SALES OFFICEs/MANUFACTURER'S REPRESENTATIVES

AUSTRI~ ITALY
ABRAHAMCZIK + DEMEL MOXEL S.P.A.
G••mbH • CO. KG 20092 Cinisello Balsamo (MI)
Eichenstra8e 58-64/1 Via C. Frova. 34
A-1"120 Viema Tel: (02) 612,,0521
Tel: (0222).857661 Tlx: 352045
T1x: 134273 Fax: (02: 617.2582
Fax: 833583 DIS. EL S.R.L.
10148 Torino
BELGIUM Via Ala eli Stura 71/18
NEWTEC INTERNATIONAL Tel: (220) 1522345
Chaussee de Louvain 186 Tlx: 215118
1940 WoIuwe-'St-Etlenne
Leuvensesteenweg 186 SPAIN
~ 940-Sint-Stevens-WoIuwe SEMICONDUCTORES S.A.
Tel: (02) 7250900 'Ronda General Mitre, 240
Tlx: 25820 Barcelona-6
Fax: (02) 7250813 . Tel: (93) 2172340
T1x: 97787 SMCD E
NETHERlANDS , Fax: 2175698
BV HANDELMIJ. MALCHUS
SANTOS DEl VALLE, S.A.
Fokkerstraat 511-513
. Postbus 48 GaIiIeo, 54, 56
28015 Madrid
NL-3100 AA Schiedam
Tel: (,,1) 446814H44
Tel: (010) 373777
Tlx: 42615 LUSA E.
Tlx: 21598

=8 SAMSUNG SEMICONDUCTOR 634

SALES OFFICES/MANUFACTURER'S REPRESENTATIVES

3. ASIA
HONG KONG JAPAN
AV. CONCEPT . ADO ELECTRONIC INDUSTRIAL CO., LTD.
Hunghom Commercial Centre, 7th FL., SASAGE BLDG. 4-6 SOTOKANDA
Room 708, Tower A.·7/F 2-CHOME CHIYODA-KU, TOKYO 101, JAPAN
37-39, Ma Tau Wai Road Tel: 03-257-1618
Hunghom, Kowloon, Hong Kong Fax: 03-257-1579
Tel: 3-629325"'6, 3-347722"'3 INTERCOM PO INC.
T1x: 52362 ADVCC HX
IHI 8LDG, 1:6-7, SHIBUYA, SHIBUYA-KU:
Fax: 852-3-7234718
TOKYO 150 JAPAN
PROTECH Tel: 03-406-5612
FLAT 3 10lF WING SHING IND, BLDG Fax: 03-409-4834
26 NGFONG ST, SANPOKONG CHEMI·CON INTERNATIONAL CORP.
KOWLOON, Hong Kong
MITSUYA TORANOMON BLDG.
Tel: 3-255106
22-14, TORANOMON 1 CHOME
T1x: 38396 PTLD HX
MINATO-KU TOKYO 105, JAPAN
Fax: 852-3-7988459
Tel: 03-508-2841
TRIATOMIC Fax: 03-504-0566
1004 President Commercial Centre, TOMEN ELECTRONICS CORP.
602-608, Nathan Road, K9wloon. Hong Kong
1-1, USCHISAIWAI-CHO 2 CHOME
Tel· 3-880151"'2, 3-886184"'5
CHIYODA-KU TOKYO, 100
Tlx: 36631 TRIAT HX
. Tel: 03-506-3473
Fax: 852-3-884026
Fax: 03-506-3497
MATSUDA DIA SEMICON SYSTEMS INC.
6/F CHUNG PAK Commercial BLDG
WACORE 64 1-37-8 SANGENJAYA
2 Cho Yuen SI. Yau Tong Bay
SETAGAYA-KU TOKYO 154 JAPAN
Kowloon, Hong Kong
Tel: 03-487-0386
Tel: 3-7276383
Fax: 03-487-8088
Tlx: 42349 MAZDA HX
Fax: 852-3-7989661
SINGAPORE
JERS GEMINI ELECTRONICS PTE LTD.
Flat C-l, 13th Floor, Hoi Bun Industrial Bldg. 100, UPPER CROSS STREET

II
6 Wing Yip Street, Kwun Tong, Kowloon, #09-08 OG BLDG. SINGAPORE 0105
Hong Kong ·Tel: 65-5351777
Tel: 3-418311-8 Tlx: RS 42819
Tlx: 55450 JERSE HX Fax: 65-5350348
Fax: 852-3-7598599
INDIA
TAIWAN MURUGAPPA ELECTRONICS LTD.
YOSUN INDUSTRIAL CORP. PARRRY HOUSE' 3rd floor 43 Moore Street
MIN SHENG COMMERCIAL BUILDING MADRAS 600 001 India
10F., No. 481, MIN-SHENG EAST RD., Tel: 21019/31003
TAIPEI, TAIWAN, R.O.C. T1x: 041-8797 HIL IN.
Tel: 501-0700 (10 LINES)
Tlx: 26777 YOSUNIND
Fax: (02) 503-1278
KENTOP ELECTRONICS CO., LTD.
5F-3, 21st CENTURY BLDG.,
NO. 207, TUN-HWA N. RD., TAIPEI
Tel: (02) 716-1754, 716-1757
Fax: (02) 717-3014

c8 SAMSUNG SEMICONDUCTOR 635

SALES OFFICES/MANUFACTURER'S REPRESENTATIVES

4. KOREA
. NAEWAE ELECTRIC CO., LTO. NEW CASTLE
Room 403, 2200ng Sumln .Bldg, SEMICONDUCTOR CO., LTD.
. #16·1, Hangangro·2ka, Yongsanku, 12.3·1, Joo Kyo Dong
Seoul Korea. Joongku, Seoal Korea
Tel: 701·7341"'5 Tel: 274·3220, 3458
Fax: 717·7246
HANKOOK SEMICONDUCTOR
SAMSUNG
1131·9 Kurodong, Kuroku,
LIGHT-ELECTRONICS CO., LTD. Seoul Korea
149·Jang Sa Dong Tel: 868·0277"'9
Jongroku, Seoul Korea Fax: 868·4604
Tel: 744·2110,269·618718
Fax: 744·4803

SEGYUNG ELECTRONICS
182·2 Jang Sa Dong
Jongroku, Seoul Korea.
Tel: 272·6811 "'6
Fax: 273·6597

c8 SAMSUNG SEMICONDUCTOR 636

 •• SAMSUNG
•••
•••
••
Semiconductor & Telecommunications

HEAD OFFICE :
9/10FL . SAMSUNG MAIN BLDG . TELEX : KORSST K27970
250, 2-KA , TAEPYUNG-RO, TEL (SEOUL) 751-2114
CHUNG-KU , SEOUL , KOREA FAX : 753-0967
CP .O BOX 8233

BUCHEON PLANT:
82-3, DODANG-DONG , TELEX : KORSEM K28390
BUCHEON , KYUNGKI-DO , KOREA TEL (SEOUL) 741-0066 , 662-0066
CPO . BOX 5779 SEOUL 100 FAX : 741-4273

KIHEUNG PLANT :
SAN #24 NONGSUH-RI , KIHEUNG-MYUN TELEX : KORSST K23813
YONGIN-GUN , KYUNGKI-DO, KOREA TEL (SEOUL) 7410620/7
C.P.O. BOX 37 SUWON FAX 741-0628

GUMI BRANCH :
259, GONDAN-DONG, GUMI , TELEX : SSTGUMI K54371
KYUNGSANGBU~DO, KOREA TEL : (GUM I) 2-2570
FAX (GUMI) 52-7942

SAMSUNG SEMICONDUCTOR INC .:

3725 NORTH FIRST STREET TEL : (408) 434-5400
SANJOSE, CA 95134-1708, USA TELEX : 339544
FAX : (408) 434-5650

HONG KONG BRANCH :

13FL. BANK OF AMERICA TOWER TEL : (5) 21-0307/9, 21-0300 , 23-7764
12 HARCOURT ROAD , HONG KONG TELEX : 80303 SSTC HX
FAX: (5) 84-50787

TAWAN OFFICE :
RM 1102, I.T. BLDG , NO. 385 TEL : (2) 777-1044/5
TUN-HWA S, RD , TAIPEI , TAIWAN FAX : (2) 777-3629

SAMSUNG JAPAN CO :
RM 3108, KASUMIGASEKI BLDG. TEL (03) 581 -1 816/7585
2-5, 3-C HOME KASUMIGASEKI TELE X: J24244
CHI YODA-KU , TOKYO , 100 JAPAN FAX : (03) 581-7088

SAMSUNG SEMICONDUCTOR EUROPE GMBH:

WESTEND SAVIGNY ST RA SSE 5 TEL : 001-496-975-6006-0
6000 FRAN KFURT, MAIN1 , WIG 001-496-974-7898
TELEX : 4170878 SSTF D
FAX : 001-496-975-) 558

SAMSUNG (U .K.) LTD .:

6 FL. VIC TORIA HOUSE SOUTHAMPTON TELEX : 297987 STARS LG PRINTED IN KOREA
ROW W.C. 1 LONDON . ENGLAND TEL: 831-6951/5
APRIL , 1988
FAX : (01) 430-0096