1:XIUNX

The Programmable Gate Array

Data Book
,

1989
 SECTION TITLES

1 Programmable Gate Arrays

2 Produc·t Specifications

3 Quality, Testing, Packaging

4 Technical Support

5 Development Systems

6 Applications

7 Article Reprints

8 Index
 The Programmable Gate Array Company

GATE ARRAYS PROGRAMMABLE LOGIC

DEVICES

EXTENSIVE
SIMULATION PRIMITIVE

USER
PROGRAMMABLE

DEVELOPMENT
TOOLS

116201

THE PROGRAMMABLE GATE ARRAY

(LOGIC CELLTM ARRAY)
l:XllIXX TABLE OF CONTENTS

1 Programmable Gate Arrays

About the Company 1-1
Introduction to Programmable Gate Arrays
A Cost of Ownership Comparison
1-3
1-9 III
2 Product Specifications

•
XC3000 Logic Cell Array Family 2-1
XC2064, XC2018 2-55
Military Logic Cell Arrays 2-97
XC1736 Serial Configuration PROM 2-139
XC1764 Serial Configuration PROM 2-150
Ordering Information 2-152

3 Quality, Testing, and Packaging

Quality Assurance and Reliability
Methodology
Packaging
3-1
3-11
3-17 •
•
4 Technical Support
Technical Seminars and Users' Group Meetings 4-1
Video Tapes 4-2
Newsletter 4-3
Technical Bulletin Board 4-4
Field Applications Engineers 4-6

•
Training Course 4-7
XACT Manuals 4-8
User's Guides 4-9

5 Development Systems
Overview 5-3
Design Manager 5-4
System Architecture 5-18
PC Hardware Requirements 5-22
Macro Library 5-25
Product Briefs 5-32
Ordering Information 5-49

6 Applications
Introduction 6-1
Estimating Size and Performance 6-3
Incorporating PLD Equations Into LCAs 6-7
The XC2000 User's Guide to the XC3000 Family 6-11
Designing with the XC3QOO Family 6-12
Designing with the XC2000 Family 6-13

1962
 TABLE OF CONTENTS

6 Applications (Con'f)
Additional Electrical Parameters 6-14
LCA Performance 6-16
Start-up and Reset 6-19
Metastable Recovery 6-20
Battery Backup for Logic Cell Arrays 6-22
Compact Multiplexer and Barrel Shifter 6-23
Majority Logic, Parity 6-24
Multiple Address Decoding 6-25
Binary Adders, Subtractors, and Accumulators 6-26
Adders and Comparators 6-27
Conditional Sum Adder 6-30
Building Latches Out of Logic 6-31
Synchronous Counters, Fast and Compact 6-32
30 MHz Binary Counter 6-33
Up/Down Counter 6-34
Loadable Up/Down Counter 6-35
30 MHz Counter with Synchronous Reset 6-36
Fast Bidirectional Counters for Robotics 6-37
40 MHz Presettable Counter 6-38
Asynchronous Preset in XC3000 CLBs 6-40
Frequency/Phase Comparator for Phase-Locked-Loops 6-41
Gigahertz Presettable Counter 6-42
100 MHz Frequency Counter 6-44
Serial Pattern Detectors 6-45
Serial Code Conversion 6-46
8-Bit Format Converter 6-48
Megabit FIFO in Two Chips 6-50
State Machines 6-52
Complex State Machine in One LCA 6-53
Self-Diagnosing Hardware 6-54
PS/2 Micro Channel Interface 6-57
High-Speed Bar Code Reader 6-59
DRAM Controller with Error Correction 6-61
Logic Analyzer/In-Circuit Emulator 6-67

7 Article Reprints
Building Tomorrow's Disk Controller Today 7-1
The Acid Test 7-5
Programmable Logic Betters the Odds 7-8
Using LCAs in a Satellite Earth Station 7-12
Faster Turnaround for a T1 Interface 7-17
Two, Two, Two Chips in One 7-19
LCA Stars in Video 7-22
Taking Advantage of Reconfigurable Logic 7-24

8 Index
Index 8-1
Sales Office Listing 8-3 1962
 SECTION 1

Programmable Gate Arrays

1 Programmable Gate Arrays

2 Product Specifications

3 'Quality, Testing, Packaging

4 Technical Support

5 Development Systems

6 Applications

7 Article Reprints

8 Index
 Programmable Gate Arrays

About the Company ............................................................................ 1-1

Introduction to Programmable Gate Arrays ......................................... 1-3
A Cost of Ownership Comparison ....................................................... 1-9

Contributors

Peter AlIke Dave Galli Richard Ravel

Keath Armstrong Jim Hsieh Ed Resler
Jim Chumbley Steve Knapp Steve Schreifels
Rick Dudley Dave Lautzenheiser Don Soderman
Chuck Erickson Mark Markham Robert Stransky
Lee Farrell Bob McGrath Thomas Waugh
Brad Fawcett Bill O'Neill Perry Wu
Chuck Fox Wes Patterson Pardner Wynn

© Copyright 1989 by Xilinx, Inc. All Rights Reserved.

Patents Pending

Xilinx, Logic Cell, LCA, XACT, XACTOR, Programmable Gate Array, Inc.. Apollo and AEGIS are registered trademarks of APOLLO
and Logic Processor are trademarks 01 Xilinx, Inc. The Program- Computer. Mentor and IDEA are registered trademarks and
mable Gate Array Company is a Service Mark of Xilinx, Inc. QuickSim, NETED, EXPAND are trademarks of Mentor Graphics,
Inc. ValidGED and ValidSim are trademarks of Valid Logic Systems,
IBM is a registered trademark and PCIAT, PC/XT, PS/2, and Micro Inc. Sun is a registered trademark of Sun Microsystems, Inc.
Channel are trademarks of International Business Machines SCHEMA II is a trademark of Omation Corporation. OrCAD is a
Corporation. ABEL is a trademark and Data 110 is a registered registered trademark of OrCAD Systems Corporation. Viewlogic is a
trademark of Data 1/0 Corporation. FutureNet is a registered registered trademark of Viewlogic Systems, Inc. CASE Technology
trademark and DASH is a trademark of FutureNet Corporation, a is a trademark of CASE Technology, a division of Teradyne's
Data I/O Company. SimuCad and Silos are registered trademarks Electronic Design Automation Group. Xilinx, Inc. does not assume
and P-Silos and PIC-Silos are trademarks of SimuCad Corporation. any liability arising out of the appiication or use of any produci
Microsoft is a registered trademark and MS-DOS is a trademark of described herein; nor does it convey any license under its patent,
Microsoft Corporation. Logitech is a registered trademark of copyright or maskwork rights or any rights of others. Xilinx, Inc.
LOGITECH Inc. Lotus is a registered trademark of Lotus reserves the right to make changes, at any time, in order to improve
Development Corporation. AboveBoard and AboveBoard/PS are reliability, function or design and to supply the best product possible.
trademarks of Intel Corporation. RAMpage!, SixPakPlus and Xilinx, Inc. cannot assume responsibility for the use of any circuitry
SixPakPremium are registered trademarks of AST Research, Inc. described other than circuitry entirely embodied in their product. No
Mouse Systems is a trademark of Mouse Systems Corporation. other circuit patent licenses are implied. Xilinx, Inc. cannot assume
Centronics is a registered trademark of Centronics Data Computer responsibility for any circuits shown or represent that they are free
Corporation. PAL and PALASM are registered trademarks of from patent infringement or of any other third party right. Xilinx, Inc.
Advanced Micro Devices, Inc., DAISY, Logician, and DNIX are assumes no obligation to correct any errors contained herein or to
registered tradmarks of Daisy Systems. UNIX is a trademark of advise any user of this text of any correction if such be made.
AT&T Technologies, Inc. CUPL is a trademark of Logical Devices,

Printed in U.S.A. 1962

 About the Company ...

Xilinx is the first company to develop a user-programmable Due to their density and the convenience of user program-
gate array. The invention of a high-density, general- mability, Xilinx's Programmable Gate Arrays represent an
purpose user-programmable logic device was the result of important new alternative in the market for Application •
a number of breakthroughs, and several aspects of the Specific Integrated Circuits (ASICs). The company contin-
device's array architecture have been patented. Since the ues to concentrate its resources exclusively on expanding
introduction of its first product in 1985, Xilinx has continued its growing family of Programmable Gate Arrays and asso-
to lead in the development of new programmable gate ar- ciated development systems, and on providing technical
rays with higher speeds, higher densities, and lower costs. support to a rapidly growing customer base.

1-1
1-2
 INTRODUCTION TO
PROGRAMMABLE GATE ARRA YS
Steady advances in the level of integration in elec- to consider factory-programmed custom and semicus-
tronic circuits have improved many equipment features, tom Application Specific Integrated Circuits (ASICs).
reducing costs, power consumption, and system size, Recent breakthroughs in logic architectures have re-
while increasing performance and reliability. Increas- sulted in the first high density ASICs that can be config-
ing levels of integration are most evident in micropro- ured by the user. These user programmable gate arrays
cessor and memory ICs. With each process generation, combine the logic integration benefits of custom VLSI
the technology gap between these VLSI circuits and
other standard logic ICs has widened. To achieve
comparable densities for their proprietary logic func-
with the design, production, and time to market advan-
tages of standard products. The flexibility of user pro-
gramming significantly reduces the risks of design
II
tions, designers of digital equipment have been forced changes and production rate changes.

ASIC ALTERNATIVES
Application Specific ICs are the best solution for most logic functions. The best ASIC solution depends on density requirements and production volumes.

20,000 STANDARD
CELL AND
CUSTOM
10,000
z
Q
I-
0 5,000
Z USER PROGRAMMABLE
::J
GATE ARRAYS
w
~ 1,000
~
0
100

0
100 1,000 10,000 100,000
1101 01
VOLUME/DESIGN

O GATE
USER PROGRAMMABLE
ARRAYS
STANDARD CELL
AND CUSTOM ICS
Unlike conventional gate arrays,programmable gate arrays Standard cell and custom ICs require unique masks for all
require no fixed costs, and no custom factory fabrication. Since layers used. in manufacturing. This imposes extra costs and
each device is identical, manufacturing costs follow the same delays for development, but results in the lowest production
learning curve as other high-volume standard product ICs. costs for high volume applications. Standard cell ICs offer the
advantages of high level building blocks and analog functions.

GATE
ARRAYS
PLDs are often used in place of fiveto ten SSIjMSI devices, Gate arrays implement user logic by interconnecting transistors
and are the most efficient ASIC solution for densities up to a or sim pIe gates into more complex functio~sduring the last
few hundred gates. Programmable Logic Devices (PLDs) stages of the manufacturing process. Gate arrays offer densitieE
include a number of competing alternatives, all based on vari- up to 100,000 gates or more, with utilization of 80-90% for
ations of AND-OR plane architectures. The primary limita- smaller devices, and 40-60% for the largest.
tions of the PLD architecture are the number of flip-flops, the Unlike standard IC products, gate array costs include fixed
nUl;nqer of input/out~utsignals, and the rigidity of the AND- costs as well as the production cost per unit. Gate arrays
OR plane logic and its interconnections. The use of one func- become cost effective when production volumes are high
tion often precludes the use of many other similar functions. enough to provide a broad base for amortization of fixed costs.

1-3
Introduction to Programmable Gate Arrays

PROGRAMMABLE GATE ARRA Y ARCHITECTURE

l:. Xilinx's proprietary Logic Cell Array architecture
is similar to that of other gate arrays, with an in- DO
0
00
0 00
0
00
0
00 00
0
00
0
0
terior matrix of logic blocks and a surrounding ring of
I/O interface blocks. Interconnect resources occupy the 0 0 0 0 0 0 0 0 0 0

channels between the rows and columns of logic blocks, 0 0 0 0 0 0 0 0 0

and between the logic blocks and the I/O blocks. 0 0 0 0 0 0 0 0 0 0
Like a microprocessor, the Logic Cell Array (LCA) is 00 0 0 0 0 0 0 0 00
a program-driven logic device. The functions of the 0 0 0 0 0 0 0 0 0 0
LCA's configurable logic blocks and I/O blocks, and 00 0 0 0 0 0 0 0 00
their interconnection, are controlled by a configuration 0 0 0 0 0 0 0 0
program stored in an on-chip memory. The configura- °00 0 0 0 0 0 0 0
°
00
tion program is loaded automatically from an external
0 0 0 0 0 0 0 0 0 0
memory on power-up or on command, or is pro- DO
grammed by a microprocessor as a part of system 0 0 0 0 0 0 00
initialization.
°DO 0 0 0 0 0 0 0 0 0
Logic Cell Array performance is determined by the
speed of logic, storage elements, and programmable 0 0 0 0
interconnect. LCA performance is specified by the °0
0
0 0 0 0
maximum toggle rate for a logic block storage element 0 0
configured as a toggle flip-flop. For typical applica-
0
tions, system clock rates are one-third to one-half the 00
0 DOD
maximum flip-flop toggle rate.

1101 02

0
-- :~

----:..

~···jf······················ ~:""".
:D-= o. _ _ _ _ _ _
0 0
~

'"

1101 03 1101 04 1101 05

CONFIGURABLE INPUT/OUTPUT INTERCONNECT

LOGIC BLOCK BLOCK
The flexibility of the LCA is due to re-
The core of the Logic Cell Array is a The periphery of the Logic Cell Array is sources that permit program control of
matrix of identical Configurable Logic made up of user programmable Input/ the interconnection of any two points on
Blocks (CLBs). Each CLB contains pro- Output Blocks (lOBs). Each block can be the chip. Like other gate arrays, the
grammable combinatorial logic and programmed independently to be an in- LCA's interconnection resources include
storage registers. The combinatorial put, an output, or a bi-directional pin a two-layer metal network of lines that
logic section of the block is capable of with three-state control. Inputs can be run horizontally and vertically in the
implementing any Boolean function of programmed to recognize either TTL or rcws and columns between the CLBs.
its input variables. The registers can be CMOS thresholds. Each lOB also Programmable switches connect the
loaded from the combinatorial logic or includes flip-flops that can be used to inputs and outputs of lOBs and CLBs to
directly from a CLB input. The register buffer inputs and outputs. nearby metal lines. Crosspoint switches
outputs can be inputs to the combinato- and interchanges at the intersections of
rial logic via an internal feedback path. rows and columns allow signals to be
switched from one path to another.
Long lines run the entire length or
breadth of the chip, bypassing inter-
changes to provide distribution of critical
signals with minimum delay or skew.

1-4
XC2000
PROGRAMMABLE GATE ARRAY FAMILY

The XC2000 series of programmable gate arrays was

introduced in 1985. Price reductions since that time have
reflected steadily increasing production volumes. The
family includes two compatible arrays: the XC2064 with
1200 gates, and the XC2018 with 1800 gates.

II
FEATURES o Fully user-programmable:
• I/O Functions
• Logic and storage functions
• Interconnections
o Three performance options: 33,50, and 70 MHz toggle rates
o Three package types: Dual In-line Package
Plastic Leaded Chip Carrier
Pin Grid Array

o TTL or CMOS input thresholds

THE XC2000 FAMILY OF PROGRAMMABLE GATE ARRAYS

XC2064 XC2018
Number of gates 1200 1800
Configurable Logic Blocks 64 100
Combinatorial Logic Functions 128 200
Latches and flip-flops 122 174
Input/Outputs 58 74

XC1736
CMOS SERIAL CONFIGURATION PROM

The 1736 Serial Configuration PROM is a companion device that

provides permanent storage of LCA configuration programs. It can
be used whenever a dedicated device is preferable to sharing of a
larger EPROM, or to loading from a microprocessor.

FEATURES o One-Time Programmable (OTP) 36,288 bit serial memory designed to

store configuration programs for Programmable Gate Arrays
o Simple interface to a Logic Cell Array (LCA) requires only two I/O pins
o Daisy chain support for multiple devices
o Cascadable for large arrays or manyLCAs
o Storage of multiple configurations for a single LCA
o Low power CMOS EPROM process
o Space-efficient, low-cost 8-pin DIP packages

1-5
Introduction to Programmable Gate Arrays.

XC3000
PROGRAMMABI.E GATE ARRAY FAMII.Y

The XC3000 series is a second genera-

tion family of CMOS programmable gate
arrays that includes five compatible
members with logic densities from 2000
to 9000 gates.

FEATURES o Fully user-programmable: o Second generation afthitecture

• I/O Functions • 5-input logic functions
• Logic and storage functions .2 flip-flops per CLB/IOB
• Interconnections • Enhanced routing resources
o Five member product family • Three-state drivers for wide ANDs
.2000-9000 gates o Programmable voltage slew rates on outputs
• Compatibility for ease of design migration o Three package types:
o Two performance options: • Plastic Leaded Chip Carrier
.50 and 70 MHz toggle rates • Pin Grid Array
• Quad Hat Package

The XC3000 Family of Programmable Gafe Arrays

XC3020 XC3030 XC3042 XC3064 XC3090
Number of gates 2000 3000 4200 6400 9000
Combinatorial Logic Functions 128 200 288 ,448 740
Latches and flip-flops 256 360 480 688 928
Input/Outputs 64 80 96 120 144

1-6
DEVELOPMENT SYSTEMS
Designing with Xilinx Programmable Gate Arrays is similar to design-
ing with other gate arrays. Designers can use familiar CAE tools for
design entry and simulation. The open Xilinx development system
includes a standard netlist format, the Xilinx Netlist File (XNF), that
provides a bridge between schematic editors or simulators, and the Xilinx
XACT software for design implementation and real time design verifica-
tion. The Xilinx software is supported on the PCI AT and compatibles as
well as on popular engineering workstations.

II

Design Entry Software

consists of libraries and netlist interfaces for
DESIGN
ENTRY
j PALASMTM.
TO·XNF
TRANSLATOR
standard CAE software such as FutureNet,
Schema II, OrCAD, Viewlogic, Daisy,
Mentor, Valid, CASE, and PALASM.
Programmable gate array libraries permit
design entry with standard TTL functions,
with Boolean equations, and with user-
defined macros.

Simulation Software
includes models and netlist interfaces to
standard simulator software, such as SILOS
and CADAT, that is used for logic and timing
simulations.

Design Implementation
DESIGN
IMPLEMENTATION Software
is used to convert schematic netlists and
Boolean equations into efficient designs for
programmable gate arrays. The software
includes programs that perform partitioning,
optimization, placement and routing, and
DESIGN EDITOR interactive design editing.
TIMING CALCULATOR XACTORTM
DOWNLOAD CABLE DESIGN VERIFIER
BITSTREAM GENERATOR
DS21 DS26127/28

In-circuit Design
IN·CIRCUIT Verification Tools
DESIGN
VERIFICATION permit real-time verification and debugging
l:XILlNX of a programmable gate array design as soon
XC3020·70
PC6SC
as it is placed and routed. Designers benefit
X9201MB730 from faster and more comprehensive design
verification, and from reduced requirements
1101 06 to generate simulation vectors to exercise a
design.

1-7
Introduction to Programmable Gate Arrays

TECHNICAl. SUPPORT
SOFTWARE UPDATES TECHNICAl. I.ITERATURE
Xilinx is continuing to improve the XACT development In addition to this databook, technical literature for the XiJinx
system software, and new versions are released two-three programmable gate array includes four volumes that are
times per year. Updates are provided free of charge during delivered with every XACT development system.
the first year after purchase, provided the user returns the
registration card. After the first year, users are encouraged to
purchase a Software Maintenance Agreement so that they will o User's Guide
continue to recieve software updates. The User's Guide is a collection of "how to" applications
notes on such subjects as getting started with an LCA
design, Boolean equation design entry, use of the simula-
tor, placement and routing optimization, and LCA con-
figuration.
XII.INX USER GROUP
Xilinx users are invited to attend training and information
exchange sessions that are held two-three times per year in o Reference Manuals (2 vols)
various locations worldwide. These User Group meetings are The XACT Reference Manuals include a detailed descrip-
intended for experienced users of Xilinx Programmable Gate tion of each Xilinx software program.
Arrays, and they emphasize the efficient use of the XACT
development system.
o Macro library
The Xilinx development system includes over 100 macros,
including counters, registers, and multiplexers. The macro
library manual includes schematics and documentation for
FIEI.D APPI.ICATIONS each macro.
ENGINEERS
Xilinx provides local technical support to customers through a
network of Field Applications Engineers (FAEs). For the
name and phone number of the nearest FAE, customers may
caJl one of the Xilinx sales offices listed in the back of this
book.

APPI.ICATIONS HOT I.INE

Xilinx maintains an applications hot line to provide technical
support to LCA users. This service is available from 8:00 am
to 6:00 pm Pacific Time. CaJl (408) 879-5199 or (800) 255-7778
and ask for Applications Engineering.

BUI.I.ETIN BOARD
To provide customers with up-to-date information and an im-
mediate response to questions, Xilinx provides 24-hour access
to an electronic bulletin board. The Xilinx Technical bulletin
board provides the following services to all registered XACT
customers.

o Read files from the bulletin board

o Check current software version numbers
o Download files
o Upload files
o Leave messages for other Bulletin Board Users.

1-8
 A Cost of Ownership
&XlliNX Comparison

CONTENTS Programmable
Gate Arrays Gate Arrays
Executive Summary
ROM vs. EPROM Analogy
Who Recognizes the Costs?
Standard product
Off-the-Shelf delivery
Custom product
Months to manufacture
II
=
Total Cost Fixed Cost + (Variable Cost) (Units) Fast time to market
Programmed by the user
Manufacturing delays
Programmed in the factory
Fixed Development Costs for Gate Arrays
Simulation NoNRE NRECosts
No inventory risk Design specific
Time to Design For Testability Fully factory tested User develops test
NRECharges Simulation useful Simulation critical
Design Iterations In-circuit design verification Not possible
Test Program Development Design changes anytime NRE charge repeated
Second Source Second source exists Additional cost and time
Summary of Fixed Development Costs
Variable Costs Methodology
Unit Cost (Cents/Gate)
Inventory This analysis compares the total costs of custom gate
Yield to Production arrays with those of user programmable gate arrays. It
Cost of Ownership Analysis looks at the various categories of costs, both fixed and
Breakeven Analysis variable, for devices from 2000 to 9000 gates, 90% of the
Time to Market gate array market according to most studies.
Product Life Cycles
References Because the gate array has fixed or up-front development
costs (NRE, extra simulation time, generating lest vectors,
etc.) that the programmable gate array doesnot, its total
EXECUTIVE SUMMARY cost of ownership is higher until a sufficienf quantity is
purchased. This analysis allows the user to calculate
Introduction total cost of ownership at different quantities and
derive breakeven quantities-the volume below which
Custom or mask-programmed gate arrays have many it is more cost effective to use the programmable gate
hidden costs beyond the obvious unit cost and NRE (non- array (Breakeven Analysis). The overall objective is to
recurring engineering) charges. Most of these additional determine the production volumes at which each product
costs are due to the fact that a gate array is a custom is most cost effective.
integrated circuit, one manufactured exclusively for a
particular customer. Compared to a standard product, Executive Summary Conclusion
there are many hidden expenses, both du';ng the design
phase and after purchase, beyond the direct device cost. The choice between user and mask programmed gate
arrays must take into account more than the NRE and
User programmable gate arrays, on the other hand, are cents/gate unit cost. The use of a custom product entails
high volume standard products-manufactured and fully many other costs and risks. Because of these fixed costs,
tested devices that are used by all customers. There is no 4t is less .expensiVe at lower volumes to use a standard
customization of the silicon. ·product: a programmable gate array. Since many of the

1-9
A Cost of Ownership Comparison

hidden costs of using a custom gate array do not accrue multiplied by the number of units. At lower volumes, the
to anyone department, only the project manager can custom gate array is more expensive because of fixed
recognize the total cost. costs that are incurred even if no units are purchased. The
programmable gate array project cost starts at zero, but
Similar considerations have led to the widespread accep- rises faster because of a higher cost per-unit. In this case
tance of EPROM memories as compared to ROMs, the breakeven volume is between 10k and 20k units. This
despite a higher EPROM cost per unit. The same factors paper will discuss the various components of this analysis
can be applied in the choice of a gate array. and show the user how to make a similar calculation for a
specific situation.
Figure 1 shows a representative breakeven graph for a
2000 gate device. The data are for 1990. The vertical axis Several significant factors are omitted from this graph.
shows the total project cost-fixed costs plus unit costs First, the additional fixed costs (NRE, simulation) of bring-
ing on a custom gate array second source are not included.
Second, and much more important, the cost of the longer
TOTAL
PROJECT time to market when designing with the mask gate array is
COST ($)
not included. This factor is reviewed in Time to Market.
Both of these factors would raise the custom gate array
curve and increase the breakeven quantity. In other
words, the programmable gate array would be more cost
effective at an even higher production volume.

~~Th~~~}NRE ROM VS. EPROM ANALOGY

SIMULATION TIME
DESIGNING TESTABILITY
TEST PROGRAM
DESIGN ITERATIONS ~ _ _ _ _ _ _ _ _ _ __ There is a relevant historical precedent for the use of a
10K 20K flexible standard product instead of a custom product with
PROJECT UNITS a lowerdirectcost perunit. While EPROMs have a cost per
110201 bit that is 2 to 3 times that of ROMs, they have consistently
- CUSTOM GATE ARRAY captured almost half the programmable memory market,
- PROGRAMMABLE GATE ARRAY measured in bits shipped. See Figure 2. Many of the rea-
sons forthe use of EPROMs are the same as those forthe
Figure 1. Typical Breakeven Analysis 2000 Gates-1990 use of programmable gate arrays: faster time to market,

ROM/EPROM ANALOGY
140

120

100

80 • ROM
TERABITS
SHIPPED
60
IlllI EPROM

40

20

0
1983 1984 1985 1986 1987 1988 1989
EPROM MIL¢lBIT 10.9 9.2 4.0 2.5 1.8 1.3 0.9
ROM MIL¢lBIT 4.5 3.2 1.7 1.0 0.7 0.5 0.4
110205
RATIO 2.4 2.9 2.4 2.5 2.6 2.6 2.3
SOURCE:DATAQUEST

Figure 2. ROM/EPROM Analogy

1-10
lower inventory risk, easy design changes, faster delivery, design is all-or-nothing. Simulation is a useful tool with
and second sources. The higher price per bit is offset by programmable gate arrays, but it is a critical one with gate
the elimination of inventory and production risks. arrays, and the designer can expect to spend more time
simulating a custom gate array design. The program-
Gate arrays have even more disadvantages versus pro- mable gate array designer can count on in-circuit
grammable gate arrays than do ROMs versus EPROMs. verification and on-line changes if necessary.
The upfront design time, risk, and expense of ROMs is
minimal, while that of gate arrays is substantial. ROM test Gate array simulation cost includes both computer time
tape generation is automatic, while that for gate arrays re- charges and the time of the engineer doing the simulation.
quires extensive engineering effort. Therefore, program- While the gate array vendor mayor may not charge explic-

•
mable gate arrays may be even more widely used versus itlyforcomputertime, an estimate wou Id be $5,000 and 2.5
gate arrays than are EPROMs versus ROMs. manweeks of simulation effort for a 2000 gate array, and
$10,000 and 7 manweeks for a 9000 gate array. This
compares to 0.5 and 1 week for the programmable gate
WHO RECOGNIZES THE COSTS?
array, with no Simulation charge.
Many of the elements of the total cost of ownership for a
gate array do not accrue to a single department, and often Typically one fully burdened manweek, including com-
are not fully recognized. For example, the additional engi- puter support, costs about $2000.
neering time needed to design for testability may not be 2000 Gates 9000 Gates
seen by purchasing. The inventory costs of a custom prod-
uct may not be recognized by the design department. Gate Array
However, these are real costs, and they influence the
profitability of the product and company. The person Simulation Charge $SK $10K
making the choice between custom gate arrays and Man Weeks 2.SMW 7MW
programmable gate arrays should consider the total
costs of ownership for each alternative. . Programmable Gate Array

Simulation Charge None None

TOTAL COST = FIXED COST + Man Weeks O.SMW 1MW
(VARIABLE COST)(ONITS)

The total costs of using a product can be separated into Time to Design for Testability
two components. The first is the fixed costs: upfront devel-
opment costs that are independent of volume. Some One key to getting a successful gate array the firsttime is to
examples of these for gate arrays are the masking charge, focus on testing issues. The user must guarantee that the
simulation charge, and test program development. Due to device can be fully tested in a reasonable amount of time.
amortization of these costs, the user's cost per unit can be Since the gate array vendor's only guarantee is that the
very high until a sufficient volume of units is purchased. device will pass the test program, the user must be certain
The second component of total cost is the variable cost, that if the IC meets the user-generated test specifications,
the incremental cost per unit. Besides the obvious unit it will work in the circuit.
cost, another element of variable cost is inventory cost.
Spending extra time in the design phase provides insur-
This analysis will examine costs by these two categories. ance that the device can be tested. A 1987 Dataquest
Fixed costs are summarized first, then variable costs. ASIC Market Report observes that "an engineer can sit
They are added to produce total cost. down at a $20,000 CAE/CAD station and design a
$1,000,000 test problem." Designing in testability may
also be the only way to provide for testing of complex
FIXED DEVELOPMENT COSTS sequential circuitry, or elements like long counters.
Therefore the gate array designer must spend additional
Simulation time in the design phase. An estimate is 1 additional week
for a 2000 gate arraY,and 2 additional weeks for a 9000
With a custom product, it is critical that the device work the gate array.
first time. Otherwise, the user must pay to have the device
prototyped a second time and will incur the manufacturing The programmable gate array is a standard product with
delay a second time. Custom gate arrays do not support a no incremental test costs. It is fully tested by Xilinx before
conventional, iterative, modular design process-the shipment. No application specific testing is needed.

1-11
A Cost of Ownership Comparison

Gate Array Incremental Cost Gate Array Incremental Cost

2000 Gates 9000 Gates 50% of (original NRE time and cost + one half of
Probability original simulation time and cost)
1 Man Week 2 Man Weeks

Test Program Development

NRE Charges
As noted in Time to Design forTestability, testability is criti-
NRE (Non-Recurring Engineering) charges cover the on- cal to production success for gate arrays. Gate array ven-
line vendor interface, design verification, mask charges, dors rarely make production errors, but faulty devices may
prototype samples and a nominal simulation (pre- and not be detected because the test vectors are not
post-layout) time. The charges may vary with estimated comprehensive.
production volumes. At volumes below 50,000 units,
$15,000 to $20,000 is a competitive quote for lower density The estimate for test vector development is 2 weeks for a
gate arrays. At the 9000 gate level, NRE charges may be 2000 gate array, and 4 weeks for a9000 gate array. Since
in excess of $30,000. the programmable gate array is a standard product, it is
fully tested at the factory. No application-specific testing is
There are no NRE charges for programmable gate arrays. needed.
The entire design process is done by the customer. Pro-
grammable gate array software tools run on common A risk that the program manager should consider involves
workstations and personal computers, and are much less the level of experience or knowledge that the design team
expensive than comparable tools for custom gate arrays. has with test development. lithe first pass design is unsuc-
cessful, how much time and effort will be required to debug
Typical Gate Array NRE for 10,000to 50,000 units the problem? Both additional cost and time to market are
at risk.
2000 Gates 9000 Gates
Gate Array Incremental Cost

$15K-$20K $30K-$40K 2000 Gates 9000 Gates

Design Iterations 2 Man Weeks 4 Man Weeks

The phrase 'We need to add this feature" is all too common Second Source
to the designer of electronic equipment. Designers often
find themselves faced with the need to modify a design
If a second source is required, the gate array designer
during prototyping or initial customer evaluation. Changes must identify a compatible vendor and resubmit the
may be required to add features or reduce costs. As design. This involves another NRE charge and time for
systems become more complex, "bugs" can be more translating logic and resimulation. The model used here is
prevalent. the NRE charge plus one half the simulation cost.
Design iterations are almost never due to the failure of the Programmable gate arrays are standard products that al-
gate array vendor. Rather, it is a risk associated with the
ready have a second source.
choice of an inflexible technology in a very dynamic indus-
try. Gate Array Incremental Cost

Industry data suggest that about half of all gate array de- 2000 Gates 9000 Gates
signs are modified before they are released to production.
When a modification is required, NRE costs are incurred NRE $15K-$20K $30K-$40K
forthe second pass. Since resimulation is likely to involve Simulation
less effort than the initial simulation, 25% (50% probability Charge $2.5K $5K
times one half the effort) of the simulation cost is added. Man Weeks 1MW 3MW

1-12
 --------- - - - -

Summary of Gate Array Fixed Development Costs volume will be purchased. Since programmable gate
arrays are newer products, their cost is declining at a
The summary in Table 1 shows typical fixed costs for both steeper rate than gate arrays. They are in the introduction
a 2000 gate and a 9000 gate array. Since assumptions phase of their life cycle, while gate arrays are in a more
may vary, a blank column is provided as a worksheet. mature phase of the cycle. Price comparisions should be
based on projections overthe production life ofthe product.
VARIABLE COSTS A standard product has more silicon content and less fac-
tory overhead than a custom product. Since all customers
Production Unit Cost (Cents/Gate)
buy the same product, there is more of the semiconductor
Gate array prices are often quoted in terms of cents per leaming curve with cumulative volume. Given the
gate. For 1.5 micron, 2000 gate arrays, at the volumes profitability levels of array manufacturers, gate array •
considered in this analysis (10,000 to 30,000 units), a prices may decline only slightly over time and could even
figure of 0.15-0.20 cents/gate (without package) is typical. rise.
At similar volumes, the cost per gate (without package) for
a programmable gate array is 2-3 times the cost of a cus- 1990 Programmable Gate Array Unit Costs-
tom gate array. For reasons explained below, this gap is Without Package
expected to narrow over the next few years. All of the
cents/gate numbers are for die only. Since CMOS gate 2000 4000 9000
arrays and programmable gate arrays use the same pack- Gates Gates Gates
ages, the package adders are equivalent.
20KUOty 10KUOty 10KUOty
An important consideration in calculating the total cost of Programmable 0.30-0.40 0.35-0.45 0.50-0.60
ownership is the year during which most of the production (Cents/Gate)

Typical Typical Customer

2000 Gates 9000 Gates Application

1. Simulation
NRE $5,000 $10,000
Man Weeks 2MW 6MW
2. Design for Testability 1MW 2MW
3. NRE Charges $15K-$20K $30K-$40K
4. Design Iterations @ 50% probability
NRE $11,250 $22,500
Man Weeks 0.5MW 1.5MW
5. Test Program Development 2MW 4MW
6. Second Source (NRE + 50% SIM)
NRE $20,000 $40,000
Man Weeks 1MW 3MW

Total Without Second Source

NRE $33,750 $67,500
Man Weeks 5.5MW 13.5 MW
Total With Second Source
• NRE $53,750 $107,500
Man Weeks 6.5MW 16.5 MW

Total Fixed Costs@ $2K!MW @$-,MW

Without Second Source $44,750 $94,500
With Second Source $66,750 $140,500

Table 1. Typical Fixed Costs

1-13
A Cost of Ownership Comparison

Process Technology volume applications, few gate arrays are retooled to take
advantage of process advances. The time from design
There are also technology reasons forthe steeper decline
start to end of production lifetime is usually several years.
in cost of the programmable gate array. Figure 3 shows
Overthis period, the programmable gate array will move to
that the processes used for logic IC's, including gate
successively more advanced processes, resulting in
arrays, typically lag behind those used for memory IC's.
steadily decreasing costs. By the end of the production
Since the programmable gate array is a standard IC built
on a memory process, it can take advantage of each new lifetime, the programmable gate array will be several proc-
process to shrink the die and reduce costs. esses ahead and the cost difference will be reduced
significantly.
With a conventional gate array, the process that is avail-
able at the time of design is usually used throughout the Pad-Limited Die Sizes
production lifetime of the product. Except for very high As gate arrays and programmable gate arrays grow in I/O
pin count, a phenomenon known as "pad-limiting" is more
likely to occur. The spacing between I/O pads is deter-
mined by mechanical limitations of the equipment used for
lead bonding. In I/O intensive applications the number of
(2.0~) pads around the outer edge of the die determines the die
size, instead of the number of gates. See Figure 4. In I/O
intensive applications, a "cost per 1/0" may be a more
useful measure than "cost per gate."
MEMORIES
For a given 1/0 count, in the pad-limited case the program-
mable gate array and the gate array would be the same die
0.1 L-..l...-...L-L-L---1---l_L-..l...-...L-L---L--1_L-L-l size. As a result, the highervolume, standard product, pro-
ro ~ ~ ~ M ~ M ~ M ~ 00 ~ ~ ~ ~ ~ grammable gate array could actually be less expensive on
YEAR a per-unit basis than the custom product gate array. There
110202
would be no breakeven quantity-the programmable gate
Figure 3. Process Evolution array would have a lower cost of ownership at all volumes.

PAD LIMITED DIE

350 , - - - - - - - - - - - - - .

300 1---------/--7fI'.;~--l 000000000000000

o 0
o 0
2501--------:.J;£-----l o 0

/~/""--------I
o 0
DIE 200 1 - - - - -
WIDTH /'
MILS 1 5 0 I - - / - - : . J t f L - - - - - - - - - l § 1'111 §
o
o
0
0
100 1-~~---------_1 o 0
o 0
501------------_1
o 0
000000000000000
ol-~--._--r__,--,__,--~
40 60 80 100 120 140 160 180
NUMBER OF PADS 110203

Figure 4. Minimum Die Size vs. 1/0

1-14
Effect of Die Cost on Total Cost mum economical wafer lot quantity. Inventory is created
and costs are incurred. Moreover, there is the problem of
Figure 5 illustrates a third point about the capability of pro-
inventory ownership if the parts are never ordered by the
grammable gate arrays to narrow the cost difference with
customer.
custom gate arrays. The chart shows the contribution to
total device cost of wafer, die, assembly and test. Wafer Although the safety stock reserve is a function ofthe cost of
cost represents about 20% to 40% of the total device cost, the product itself, a figure of 10% is reasonable for gate
and die cost about 30% to 50%. A 50% difference in die arrays that have unit costs under $25.00. In comparison,
cost-between a gate array and a programmable gate since changes to programmable gate arrays can be made
array-shown in the chart translates to only a 20% differ- in software in minutes, and since only one part type is
ence (80 vs. 100) in total cost by the time the device has widely stocked, the comparative safety stock reserve
been tested. This comparison is based on production of is 0%.
the programmable gate array in a more advanced process
than the custom gate array, as discussed in Unit Cost
(Cents/Gate).
Gate Array Incremental Inventory Cost
II
10% Additional Unit Cost
Inventory ReserveS

Inventories include extra devices ordered and stocked to

cover contingencies. For a custom product this is the only YIELD TO PRODUCTION
way parts can be delivered in less than the normal produc-
tiontime (2-4 months). Contingencies are often thought of Due to rapidly changing markets, many designs never go
in terms of negative events like a defective lot or manufac- into production. Sometimes acompanywill develop com-
turing shortfalls. peting projects, with only one moving to production. Many
times the market will change, or competition will emerge,
However, contingencies also include positive events like and projects will be cancelled or redirected. Of course
stocking for large, upside orders or where demand is each design team expects that its project will succeed, but
difficult to estimate. This can be especially true during a in the aggregate this is not true. If a company chooses gate
product's introduction, when design changes and demand arrays as the primary logic technology, and starts many
spikes occur simultaneously. designs, this factor will occur.

With a custom product it is also necessary to build inven- The March, 1986 Technology Research Letter states that
tory as the product nears the end of its life cycle. Demand only 1/3 of gate array designs go into production. The 1987
is low and difficu It to forecast, and it may not be possible to Dataquest ASIC and Standard Logic Semiconductor Vol-
reorder a small quantity. Spares and replacements must ume 1 reports 50% go into production. With 50%, the true
be stocked. A JIT inventory system is less practical. cost of the gate array should recognize additional costs for
simulation, designing for testability, and NRE. For 2000
Since minimum manufacturing quantities for semiconduc- gates, using the numbe.rs in Summary of Fixed Develop-
tors· are determined by wafer lots, a custom product will ment Costs, this would mean an additional ($5,000 + 3 MW
have excess WIP (work in process) or finished goods + $17,500). For 9000 gates the number is ($10,000 +
inventory.if the desired order quantity is less than the mini- 8 MW +$35,000).

100
• GATE ARRAY (211)

"#- 80
o PROGRAMMABLE GATE ARRAY (ql1)

§
w
60

~
w
40
a:
20

110204
WAFER DIE ASSEMBLY TEST

Figure 5. Relative Manufacturing Cost by Stage of Completion

1-15
A Cost of Ownership Comparison

Gate Array Incremental Cost mary of Fixed Development Costs}. Therefore, at lower
unit volumes the programmable gate array is less expen-
Simulation Cost + Time to Design for Testability + NRE Cost
sive, until the gate array can amortize the upfront fixed
costs.

COST OF OWNERSHIP ANALYSIS

Table 2 is a form that can be used for calculating the total
While gate arrays have a lower unit cost, they have incre- cost of ownership at various volumes. Table 2 pOints tothe
mental fixed costs that must be incurred before the first unit "breakeven quantity"-the quantity where the unit cost of
is received. Example costs are shown in Table 1 (Sum- the two devices is the same-of the next section.

Project Quantity 1,000 5,000 10,000 20,000

Gate Array-No second source

1. Fixed costs from Table 1

2. Unit cost

3. Inventory reserves: (Line 2)(1.1)

4. Total variable cost = (Line 3)(Qty)

5. Total cost = Line 1 + Line 4

6. Unit cost = Line S/aty

Gate Array-second source

7. Fixed costs from Table 1

8. Second source costs

9. Total fixed costs

10. Total variable cost-Line 4 above

11. Total cost = Line 9 + Line 10

12. Unit cost = Line II/Qty

Programmable Gate Array

13. Unit cost

Table 2. Total Cost VS. Volume Purchased

1-16
 E:XILINX
BREAKEVEN ANALYSIS $2,000 product that has 15% profit margins. For 10,000
units sold:
Figure 6 is a graphical representation ofthe breakeven cal-
culation for the case of 2000 gates, 1990 pricing, and no Lost Profit = $2,000 x 10,000x 15%x 113= $1.0 million or
second source. Upto the breakeven unit volume, the pro- $100 per device
grammable gate array solution has a lower total project
cost. At the 9000 gate level, assume the gate array is used in a
$10,000 product that has 20% profit margins. For 2000
Similar graphs can be built for different assumptions by units sold:
filling in Table 1. Forthe gate array, the breakeven graph is

•
merely line 5 or line 11 plotted versus quantity. For the Lost Profit = $10,000 x 2, 000 x 20% x 113 = $1.33 million or
programmable gate array, it is line 13 times the quantity $667 per device
plotted versus the quantity.
Note that these catastrophic costs are not included in any
of the previous sections. They are a quantitative estimate
of the risk of using a custom product.
TOTAL
PROJECT
COST ($)
PRODUCT LIFE CYCLES

In the electronics industry the lifet.imes of products are

shrinking. In the personal computer industry it is not un-
common to find product upgrades within.6-12 months.
This means that the volumes associated with anyone gate
r.m~=} NRE
SIMULATION TIME
array design can be much smaller than anticipated, even if
the end product still exists. It alsomeans that it is critical to
DESIGNING TESTABILITY
TESTPROORAM achieve a rapid design time.
DESIGN ITERATIONS
~--------~--------~
10K 20K The numbers used for Figure 1 show that 2000 gate pro-
PROJECT UNITS grammable gate arrays are more economical at volumes
110201 up to 10,000 to 20,000 units. These volumes will represent
- CUSTOM GATE ARRAY
- PROGRAMMABLE GATE ARRAY
an increasing number of products.

Figure 6. Typical Breakeven Analysis 2000 Gates-1990 REFERENCES· .

1. Technology Research Group Letter, March 1986,

page 7.
TIME TO MARKET
2. Dataquest Inc., Gate Arrays-Product Analysis,
There are numerous examples of products.that failed due page 3. ASIC and Standard Logic Semiconductors.
to late market entry. A study by McKinsey & Co. stated that 1987.
a product that is six months late to market Will miss out on
1/3 ofthe potential profit overthe product's lifetime. Ifthere 3. Reinertsen. Donald G ....Whodunit? The Search forthe
is any problem in simulation, or any iteration of the gate New-Product Killers." Electronic Business, July 1983.
array deSign, then a gate array would easily add six pages 62-66.
additional months to a product schedule.
4. Integrated Circuit Engineering Corp .• ASIC Outlook,
At the 2,000 gate level, assume the gate array is used in a 1987.

1-17
 I:XILINX

The Programmable Gate Array Company

1-18
 SECTION 2

Product Specifications

1 Programmable Gate Arrays

•
2 Product' Specifications

3 Quality, Testing, Packaging

•
4 Technical Support
•
5 Development Systems
•
6 Applications
•
7 Article Reprints
•
8 Index
•
 Product Specifications

XC3000 Logic Cell Array Family

Features, Description, Architecture ............................................... 2-1
Interconnect ................................................................................... 2-7
Internal Buses ................................................................................ 2-11
Programming ................................................................................. 2-14
Special Configuration Functions .................................................... 2-21
Performance .................................................................................. 2-24
Power ............................................................................................. 2-26
Component Selection, Ordering Information ................................. 2-29
Pin Descriptions ............................................................................. 2-30
Parametrics .................................................................................... 2-38
Package Dimensions ..................................................................... 2-48
XC2064, XC2018 Logic Cell Arrays
Features, Description, Architecture ............................................... 2-55
Interconnect ................................................................................... 2-59
Power ............................................................................................. 2-64
Programming ................................................................................. 2-66
Performance .................................................................................. 2-72
Pin Descriptions ............................................................................. 2-78
Parametrics .................................................................................... 2-82
Component Selection, Ordering Information ................................. 2-29
Package Dimensions ..................................................................... 2-92
Military Logic Cell Arrays
XC2018B ....................................................................................... 2-95
XC3020B ....................................................................................... 2-99
XC3090B ....................................................................................... 2-125
Serial Configuration PROM
XC1736 Features, Descriptions ..................................................... 2-139
Parametrics .................................................................................... 2-144
Ordering Information, Package Dimensions .................................. 2-149
XC1764 Advance Information ........................................................ 2-150
Sockets ............................................................................................... 2-151
LCA Component Selection, Ordering Information ............................... 2-152

1962
 XC3000
Logic Celi™Array Family

Product Specification

FEATURES The Logic Cell Array's user logic functions and intercon-
nections are determined by the configuration program
• High Performance-50, 70 and 100 MHz Toggle data stored in internal static memory cells. The program
Rates can be loaded in any of several modes to accommodate
• Second Generation User-Programmable Gate Array various system requirements. The program data resides
• 1/0 functions externally in an EEPROM, EPROM or ROM on the appli-
• Digital logic functions cation circuit board, or on a floppy disk or hard disk.

•
• Interconnections On-chip initialization logic provides for optional automatic
• Flexible array architecture loading of program data at power-up. Xilinx's companion
• Compatible arrays, 2000 to 9000 gate XC1736 Serial Configuration PROM provides a very
logic complexity simple serial configuration program storage in a one-time-
• Extensive register and 1/0 capabilities programmable eight-pin DIP.
• High fan-out signal distribution
• Internal three-state bus capabilities
• TTL or CMOS input thresholds Basic Logic Config- User Program
• On-chip oscillator amplifier Array Capacity urable IIOs Data
(usable Logic (bits)
• Standard product availability
• Low power, CMOS, static memory technology gates) Blocks
• Performance equivalent to TTL SSIIMSI
• 100% factory pre-tested XC3020 2000 64 64 14779
• Selectable configuration modes XC3030 3000 100 80 22176
XC3042 4200 144 96 30784
• Complete XACTTM development system
XC3064 6400 224 120 46064
• Schematic Capture
• Automatic PlacelRoute XC3090 9000 320 144 64160
• Logic and Timing Simulation
• Design Editor
• Library and User Macros The XC3000 Logic Cell Arrays are an enhanced family of
• Timing Calculator Programmable Gate Arrays, which provide a variety of
• XACTOR In-Circuit Verifier logic capacities, package styles, temperature ranges and
• Standard PROM File Interface speed grades.

DESCRIPTION
ARCHITECTURE
The CMOS XC3000 Logic Cell™ Array (LCA) family
provides a group of high-performance, high-density, digi- The perimeter of configurable I/O Blocks (lOBs) provides
tal, integrated circuits. Their regular, extendable, flexible, a programmable interface between the internal logic array
user-programmable array architecture is composed of a and the device package pins. The array of Configurable
configuration program store plus three types of configur- Logic Blocks (CLBs) performs user-specified logic func-
able elements: a perimeter of 1/0 Blocks, a core array of tions. The interconnect resources are programmed to
Logic Blocks and resources for interconnection. The form networks, carrying logic signals among· blocks,
general structure of a Logic Cell Array is shown in analogous to printed circuit board traces connecting
Figure 1 on the next page. The XACT development MSIISSI packages.
system provides schematic capture and auto place-and-
route for design entry. Logic and timing simulation, and in- The blocks' logic functions are implemented by pro-
circuit emulation are available as design verification alter- grammed look-up tables. Functional options are imple-
natives. The deSign editor is used for interactive design mented by program-controlled multiplexers. Intercon-
optimizaton, and to compile the data pattern which repre- necting networks between blocks are implemented with
sents the configuration program. metal segments joined by program-controlled pass tran-

2-1
XC3000 Logic Cell Array Family

sistors. These functions of the Logic Cell Array are ing cell data. The cell is only written during configuration
established by a configuration program which is loaded and only read during readback. During normal operation
into an internal, distributed array of configuration memory the cell provides continuous control and the pass transis-
cells. The configuration program is loaded into the Logic tor is "off" and does not affect cell stability. This is quite
Cell Array at power-up and may be reloaded on command. different from the operation of conventional memory de-
The Logic Cell Array includes logic and control signals to vices, in which the cells are frequently read and re-written.
implement automatic or passive configuration. Program
data may be either bit serial or byte parallel. The XACT The memory cell output!) Q and Q use full Ground and Vcc
development system generates the configuration program levels and provide continuous, direct control. The addi-
bit-stream used to configure the Logic Cell Array. The tional capacitive load together with the absence of address
memory loading process is independent of the user logic decoding and sense amplifiers provide high stability to the
functions.

RW09~~
CONFIGURATION MEMORY .------i·L.
'"
a
CONFIGURATION
The static memory cell used for the configuration memory ., _ CONTROL
}--a
in the LogiC Cell Array has been designed specifically for
high reliability and noise immunity. Integrity of the LCA
configuration memory based on this design is assured
even under adverse conditions. Compared with other
programming alternatives, static memory provides the
DATA -I . ". . ". . . . . ,.,.,.,. ".1 1105 12
best combination of high density, high performance, high
reliability and comprehensive testability. As shown in Figure 2. A static configuration memory cell is loaded
Figure 2, the basic memory cell consists of two CMOS with one bit of configuration program and controls one
inverters plus a pass transistor used for writing and read- program selection in the Logic Cell Array.

THREE-STATE BUFFERS WITH ACCESS CONFIGURABLE LOGIC

TO HORIZONTAL LONG LINES BLOCKS

y------- --------y- y-

p y-
O y-
0 y-
1 y-
o y-

•
.---------INTERCONNECTAREA-------~·
p

u
n
p y-
~-

0
~-

yC
o I y-
,;,..-,-.-.L---fL---I a: f--t'--..::::po""

~~L--¥_~~ f--~~L-~~
w
f-
Z

w
~~~---fL-~~ f--t'--~-~-~
~
L.L.
p ~~~--~~~ f-~-~-~~~

~-

Figure 1. The structure of the Logic Cell Array consists of a perimeter of programmable
110 blocks, a core of configurable logic blocks and their interconnect resources.
These are all controlled by the distributed array of configuration program memory cells.

2-2
cell. Due to the structure of the configuration memory I/O BLOCK
cells, they are not affected by extreme power supply
excursions or very high levels of alpha particle radiation. In Each user-configurable I/O Block (lOB), shown in Figure 3,
reliability testing no soft errors have been observed, even provides an interface between the external package pin of
in the presence of very high doses of alpha radiation. the device and the internal user logic. Each I/O Block
includes both registered and direct input paths. Each lOB
The method of loading the configuration data is selectable. provides a programmable three-state output buffer which
Two methods use serial data, while three use byte wide may be driven by a registered or direct output signal.
data. The internal configuration logic utilizes framing Configuration options allow each lOB an inversion, a con-
information, embedded in the program data by the XACT trolled slew rate and a high impedance pull-up. Each input
development system, to direct memory cell loading. The circuit also provides input clamping diodes to provide
serial data framing and length count preamble. provide electro-static protection, and circuits to inhibit latch-up
programming compatibility for mixes of various Xilinx produced by input currents.
programmable gate arrays in a synchronous, serial, daisy-
chain fashion. The input buffer portion of each I/O Block provides thresh-

OUT
INVERT
PROGRAM·CONTROLLED MEMORY CELLS

THREE·
STATE
INVERT
OUTPUT
SELECT
SLEW
RATE
........................................................................................,.

PASSIVE
PULL UP
Vee
.~~

•
,"'" ",no
(OUTPUT ENABLE)
J.i~ -+------.)1......)--1-,
.:...1

OUT~~:·~o--.IL-;r~~l

o,,~," ~, ~LIPp_~, VOPAD

REGISTERED IN ~;....:----+-----1 Q D I---+--+--~-<

FLIP
FLOP
or
LATCH
R
L--'-_-+-_ _ _ _ _ _ _ _ (GLOBAL RESET)
.ok .ik

110501
=tJ-- ~~~ · ~f-=. . .,. . P-RO-G-R-'-"-"-:-,-:-.-:-, -,-O-"-"-~-·,-· ~'" " ":~,~.-. ---~
Figure 3. The IhpuVOutput Block includes input and output storage elements and I/O options selected by
configuration memory cells.
A choice of two clocks is available on each die edge.
The polarity of each clock line (not each flip·flop or latch) is programmable. A clock line that triggers the flip·flop
on the rising edge is an active Low Latch Enable (Latch transparent) signal and vice versa.
Passive Pull·up can only be enabled on inputs, not on outputs.
All user inputs are programmed for TTL or CMOS thresholds.

2·3
XC3000 Logic Cell Array Family

old detection to translate external signals applied to the Configuration program bits for each I/O Block control
package pin to internal logic levels. The global input-buffer features such as optional output register, logical signal
threshold of the I/O Blocks can be programmed to be inversion, and three-state and slew rate control of the
compatible with either TTL or CMOS levels. The buffered output.
input signal drives the data input of a storage element
which may be configured as a positive edge-triggered "0" The program-controlled memory cells of Figure 3 control
flip-flop or a low level-transparent latch. The sense of the the following options:
clock can be inverted (negative edge/high transparent) as
long as all lOBs on the same clock net use the same clock • Logical Inversion of the output is controlled by one
sense. Clock/load signals (I/O Block pins .ik and .ok) can configuration program bit per I/O Block.
be selected from either of two die edge metal lines. I/O
storage elements are reset during configuration or by the • Logical three-state control of each I/O Block output
active low chip RESET input. Both direct input [from I/O buffer is determined by the states of configuration pro-
Block pin .1] and registered input [from I/O Block pin .q] gram bits which turn the buffer on, or off, or select the
signals are available for interconnect. output buffer three-state control interconnection
[I/O Block pin .q. When this I/O Block output control
For reliable operation inputs should have transition times signal is HIGH, a logic "1", the buffer is disabled and the
of less than 100 ns and should not be left floating. Floating package pin is high impedance. When this 110 block
CMOS input-pin circuits might be at threshold and produce output control signal is LOW, a logic "0", the buffer is
oscillations. This can produce additional power dissipa- enabled and the package pin is active. Inversion of the
tion and system noise. A typical hysteresis of about 300 buffer three-state control logic sense (output enable) is
mV reduces sensitivity to input noise. Each user I/O Block controlled by an additional configuration program bit.
includes a programmable high impedance pull-up resistor
which may be selected by the program to provide a
• Direct or registered output is selectable for each 110
constant HIGH for otherwise undriven package pins. Al- block. The register uses a positive-edge, clocked flip-
though the Logic Cell Array provides circuitry to provide flop. The clock source may be supplied [110 Block pin
input protection for electrostatic discharge, normal CMOS .ok) by either of two metal lines available along each die
handling precautions should be observed. edge. Each ofthese lines is driven by an invertible buffer.
Flip-flop loop delays for the I/O Block and logic block flip-
flops are about 3 nanoseconds. This short delay provides • Increased output transition speed can be selected to
improve critical timing. Slower transitions reduce ca-
good performance under asynchronous clock and data pacitive load peak currents of non-critical outputs and
conditions. Short loop delays minimize the probability of a minimize system noise.
metastable condition which can result from assertion of the
clock during data transitions. Because of the short loop
delay characteristic in the Logic Cell Array, the I/O Block • A high impedance pull-up resistor may be used to
prevent unused inputs from floating.
flip-flops can be used to synchronize external signals
applied to the device. Once synchronized in the I/O Block,
the signals can be used internally without further consid- Summary of I/O Options
eration of their clock relative timing, except as it applies to
the internal logic and routing path delays. • Inputs
• Direct
• Flip-flopllatch
Output buffers of the 110 Blocks provide CMOS-compat- • CMOSITTL threshold (chip inputs)
ible 4 mA source-or-sink drive for high fan-out CMOS or • Pull-up resistor/open circuit
TTL compatible signal levels. The network driving I/O
Block pin .0 becomes the registered or direct data source • Outputs
for the output buffer. The three-state control signal • Direct/registered
[I/O Block pin.q can control output activity. An open-drain • Inverted/not
type output may be obtained by using the same signal for • Three-state/onloff
driving the output and three-state signal nets so that the • Full speed/slew limited
buffer output is enabled only for a LOW. • Three-state/output enable (inverse)

2-4
CONFIGURABLE LOGIC BLOCK Each configurable logic block has a combinatorial logic
section, two flip-flops, and an internal control section. See
The array of Configurable Logic Blocks (CLBs) provides Figure 4. There are: five logic inputs [.a, .b, .C, .d and .e];
the functional elements from which the user's logic is a common clock input [.k]; an asynchronous direct reset
constructed. The logic blocks are arranged in a matrix input [.rdj; and an enable clock [.ec]. Allmaybedrivenfrom
within the perimeter of I/O Blocks. The XC3020 has 64 the interconnect resources adjacent to the blocks. Each
such blocks arranged in 8 rows and 8 columns. The XACT CLB also has two outputs [.x and .y] which may, drive
development system is used to compile the configuration interconnect networks.
data which are to be loaded into 1he internal configuration
memory to define the operation and interconnection of Data input for either flip-flop within a CLB is supplied from
each block. User definition of configurable logic blocks the function For G outputs ofthe combinatorial logic, orthe
and their interconnecting networks may be done by auto- block input, data-in [.dl]. Both flip-flops in each CLB share
matic translation from a schematic capture logic diagram the asynchronous reset [.rd] whic~, when enabled and
or optionally by installing library or user macros. HIGH, is dominant over clogked inputs. All flip-flops are

•
......,.............................,..,.......................................................................................................................................................................................................................................·...·.......·........n.·•.•·.-..•..-...·.·.::;
:::"'~"""''''''''''''''''~'''''''''''N'o.~.,

f: ®

I
DATA IN -{ .di ?,

OQ I
I~ .a ox F t--+-h-t-------l-+-'--t-----l
t,I...

'"
~
LOGIC
'b
-i C COMBINATORIAL
I"

v...a£Si ~ .y,.",m. G I]."

•.:. :wouw""
!~ ~.:~

I
~ .ec
Dol
~
ENABLE CLOCK., RD ,t.:

I
;~

"I" (ENABLE) ~

CLOCK -!
~
.k I
RESET -i~.rd"---------------i
~
~ "0" (INHIBIT) - - - - - - j

I. '~wm ~m.w'".w'.w.w.v.~~~~~~~.'"~~~~:.w.w.w.w
.... . .....w.·.·..·.·.·.·.·.·.·.·.·.·.·.·.··.,·.·.·.w.·.·.,w.·.·.vm.wu.w.•..w.•......•.•..w...w.w.wmm...wMwM..... ..... ~' .J
1105 02
Figure 4., Each Configurable Logic Block includes a combinatorial logic section,
two flip-flops and a program memory controlled muHiplexer selection of function.

It has: five logic variable inputs .a, .b, .c, .d and .e.
a direct data in .di
an enable clock .ec
a clOCk (invertible) .k
an asynchronous reset .rd
two outputs .x arid .y

2-5
XC3000 Logic Cell Array Family

ANY FUNCTION
OFUPT04
VARIABLES
F
PARALLEL E~t&~ =-
CLOCK ENABLE=::::;-TFr:g~~~~~t)-_ _ _ _ +_ TERMINAL
COUNT

DUAL FUNCTION OF 4 VARIABLES

ANY FUNCTION
OF UP TO 4
VARIABLES
G
DO~i=t::==~~'Qt~~
t-+++-+-h.c-,- - - ,
!l ~l
Sa t. .,. . . . . . . . . . . . . . . . . . . . . . . . ..·.·.·.·.·.·.·.·u.....·•••·•·.·.•...•••.·.·... ..........................::

F -01
ANY FUNCTION 01
OF 5 VARIABLES
G
'---
FUNCTION OF 5 VARIABLES
5b
,...... . .......•

ANY FUNCTION
OF UPTO 4
VARIABLES

02

-
FUNCTION OF 6 VARIABLES
ANY FUNCTION
OF UPT04
VARIABLES

5c
1105 03

Figure 5 Figure 6. The C8BCP macro (modulo 8 binary counter

w~h parallel enable and clock enable) uses one combina-
5a. Combinatorial Logic Option 1 generates two functions of toriallogic block of each option.
four variables each. One variable, A, must be common to
both functions. The second and third variable can be any
choice of of B, C, Ox and Oy. The fourth variable can be
any choice of 0 or E.

5b. Combinatorial Logic Option 2 generates any function of five

variables: A, 0, E and and two choices out of.B, C, Ox, Oy.

5c. Combinatorial Logic Option 3 allows variable E to select

between two functions of four variables: Both have common
inputs A and 0 and any choice out of B, C, Ox and Oy for the
remaining two variables. Option 3 can then implement some
functions of six or seven variables.

2-6
reset by the active low chip input, RESET, or during the (as are block outputs) they are usable only for block
configuration process. The flip-flops share the enable Input connection and not routing. Figure 8 illustrates
clock [.ee] which, when LOW, recirculates the t'lip-fiops' routing access to logic block input variables,.control inputs
present states and inhibits response to the data-in orcom- and block outputs. Three types of metal resources are
binatorial function inputs on a CLB. The user may enable provided to accommodate various network interconnect
these control inputs and select their sources. The user requirements:
may also select the clock net input [.k], as well as its active
sense within each logic block. This programmable inver- • General Purpose Interconnect
sion eliminates the need to route both phases of a clock • Direct Connection
signal throughout the device. Flexible routing allows use • Long Lines (multiplexed busses and wide AND gates)
of common or individual CLB clocking.
General Purpose Interconnect
The combinatorial logic portion of the logic block uses a 32
by 1 look-up table to implement Boolean functions. Vari- General purpose interconnect, as shown in Figure 9,
ables selected from the five logic inputs and two internal consists of a grid of five horizontal and five vertical metal
block flip-flops are used as table address inputs. The segments located between the rows and columns of logic

•
combinatorial propagation delay through the network is and I/O Blocks. Each segment is the "height" or ''width'' of
independent of the logic function generated and is spike a logic block. Switching matrices join the ends of these
free for single input variable changes. This technique can segments and allow programmed interconnections be-
generate two independent logic functions of up to four tween the metal grid segments of adjoining rows and
variables each as shown in Figure 5a, or a single function columns. The switches of an unprogrammed device are all
of five variables as shown in Figure 5b, or some functions non-conducting. The connections through the switch
of seven variables as shown in Figure 5c. Rgure 6 shows matrix may be established by the automatic routing or by
a modu 108 binary counter with parallel enable. It uses one using "Edit net" to select the desired pairs of matrix pins to
CLB of each type. The partial functions of six or seven be connected or disconnected. The legitimate switching
variables are implemented using the input variable [.e] to matrix combinations for each pin are indicated in
dynamically select between two functions of four different Figure 10 and may be highlighted by the use of the show
variables. For the two functions offour variables each, the matrix command in XACT.
independent results (F and G) may be used as data inputs
to either flip-flop or either logic block output. Forthe single
INTERCONNECT SWITCHING
function of five variables and merged functions of six or "PIPs" MATRIX
seven variables, the F and G outputs are identical. Sym-
metry of the F and G functions and the flip-flops allows the
. r·.:/, . t-·.:
interchange of CLB outputs to optimize routing efficiencies
of the networks interconnecting the logic blocks and 1/0
0·::···:·::0
Blocks. .. . : ~- ...
PROGRAMMABLE INTERCONNECT

Programmable Interconnection resources in the Logic Cell

Array provide routing paths to connect inputs and outputs . t-·.;
of the I/O and logic blocks into logical networks, Intercon-
nections between blocks are composed from a tWO-layer
grid of metal segments. Specially designed pass transis-
··::0
....
: . ... ~-
tors, each controlled by a configuration bit, form program-
mable interconnect points (PIPs) and switching matrices
used to implement the necessary connections between
selected metal segments and block pins. Figure 7 is an
example of a routed net. The XACT development system
provides automatic routing of these interconnections. t L.:·: 4.: .:
Interactive routing (Editnet) is also available for design CONFIGURABLE INTERCONNECT
optimization. The inputs of the logic or I/O Blocks are LOGIC BLOCK BUFFER
multiplexers which can be programmed to select an input
network from the adjacent interconnect segments. As the Figure 7. An XACT view of routing resources used to form a
switch connections to block inputs are unidirectional typical interconnection network from CLB GA.

2-7
XC3000 Logic Cell Array Family

t· ..
..
'::'".E1
.'"t. .
':."~
. t-· :
,
.::t5 t· ..
..
':.".{5
: .'"t

~
0'" . .... +-0·:
.
..
:0'
.
~-
.
... ~
0'" . . .. .. . .
..
+-'
"E} .. ,
. .
.
.-
. ...;.:.--~-d
. ... :'.' ·':'"·5
t·.~ .: .'"t. '--~-+-i t-· .~. t·.~.:.· t"

1- 0 -:-- : 0 --/ :0 "·::0':,·

1- -I- __, - -- \" I- __ , --- .. +-'
ClB CONTROL INPUTS CLB lOGiC INPUTS

0:··· • :CloB
X OU~P:~~\::.::
.. ..
y
ColB ~U;~~~~
.. ..
••: : O.. :..
l- ... .j... . ••. • : • +- .... ' : . ~- .. '
..
.. .j...'

t-· :
'::f}
.' t

0 -_. .. +-0 . .·. : 0:.'

t-· : t·.~ . "t '.~ .

0:·
~-...
.. -- 1-
~- ... .. .j...'

: :

:
'::{3 :

: '::·0 : :

:
'::0 : :

Figure 8. The Xilinx XACT Development System view of the

locations of interconnect access, ClB control inputs, logic inputs and outputs.
The dot pattern represents the available programmable interconnection points (PIPs).

Some of the interconnect "PIPs" are directional. This is indicated on the XACT design editor status line:
ND is a nondirectional interconnection.
D:H->V is a PIP which drives from a horizontal to a vertical line.
D:V->H is a PIP which drives from a vertical to a horizontal line.
D:C->T is a "T" PIP which drives from a cross of a T to the tail.
D:CW isa corner PiP which drives in the clockwise direction.
PO indicates the PIP is non-conducting, P1 is "on."

2-8
Special buffers within the general interconnect areas to its right and to the .C input of the CLB to its left. The.y
provide periodic signal isolation and restoration for im- output can use direct interconnect to drive the .d input of
proved performance of lengthy nets. The interconnect
buffers are available to propagate signals in either direc-
tion on a given general interconnect segment. These bi-
directional (bidi) buffers are found adjacent to the switch-
ing matricies, above and to the right and may be high-
lighted by the use of the "Show BIDI" command in XACT.
The other PIPs adjacent to the matrices are access to or
rV 2
~ 4

~= ~~
from long lines. The development system automatically
defines the buffer direction based on the location of the
interconnection network source. The delay calculator of
the XACT development system automatically calculates 6 8

e
and displays the block, interconnect and buffer delays for

~~~
any paths selected. Generation of the simulation nellist
with a worst-case delay model is provided by an XACT

e =e~ •
option.
11 12 13 15

Direct Interconnect

Direct interconnect, shown in Figure 11, provides the most

efficient implementation of networks between adjacent
=~ =~
logic or I/O Blocks. Signals routed from block to block 16 17 19 20
using the direct interconnect exhibit minimum interconnect 1105 13
propagation and use no general interconnect resources. Figure 10. Switch matrix interconnection options for each "pin."
For each Configurable Logic Block, the .X output may be Switch matrices on the edges are different.
connected directly to the .b input of the CLB immediately Use "Show Matrix" menu option in XACT

'::Ci :.
: .' t· ..
: :

t- .. ; .:
'::[5
.' t
..
~-
. ~q . 0·:·::···· ~

. fj
t· t·.; . t- .. ; t
..
'" SWITCHING
.
. ~O· ..· ..
0·····..
+- ... ..
~
MATRIX

GRID OF GENERAL INTERCONNECT

':"5 : :
:.-:
El
METAL SEGMENTS l:
Figure 9. Logic Cell Array general-purpose interconnect is . Figure 11. The.x and .y outputs of each CLB have single
composed of a grid of metal segments which may be contact, direct access to inputs of adjacent CLBs.
interconnected through switch matrices to form networks for
CLB and 110 block inputs and outputs.

2-9
XC3000 Logic Cell Array Family

GLOBAL BUFFER DIRECT INPUT GLOBAL BUFFER INTERCONNECT

*UNBONDED lOBs (6 PLACES) ALTERNATE BUFFER DIRECT INPUT

Figure 12. X3020 die edge I/O blocks are provided with direct access to adjacent CLBs.

2-10
the block immediately above and the .8 input of the block A buffer in the upper left corner of the Logic Cell Array chip
below. Direct interconnect should be used to maxi mize the drives a global net which is available to all.kinputs of logic
speed of high performance portions of logic. Where logic blocks. Using the global buffer for a clock signal provides
blocks are adjacent to I/O Blocks, direct connect is pro- a skew-free, high fan-out, synchronized clock for use at
vided alternately to the I/O Block inputs [./] and outputs [.0] any or all of the I/O and logic blocks. Configuration bits for
on all four edges of the die. The right edge provides the .k input to each logic block can select this global line or
additional direct connects from CLB outputs to adjacent another routing resource as the clock source for its flip-
lOBs. Direct interconnections of I/O Blocks with CLBs are flops. This net may also be programmed to drive the die
shown in Figure 12. edge clock lines for I/O Block use. An enhanced speed,
CMOS threshold, direct access tothis buffer is available at
Long Lines the second pad from the top of the left die edge.

The long lines bypass the switch matrices and are in- A buffer in the lower right comer of the array drives a
tended primarily for signals which must travel a long horizontal long line that can drive programmed connec-
distance, or must have minimum skew among multiple tions to a vertical long line in each interconnection column.
destinations. Long Lines, shown in Figure 13, run vertically This alternate buffer also has low skew and high fan-out.
and horizontally the height or width of the interconnect The network formed by this alternate buffer's long lines
area. Each interconnection column has three vertical long can be selected to drive the .k inputs of the logiC blocks.
lines, and each interconnection row has two horizontal CMOS threshold, high speed access to this buffer is •
long lines. An additional two long lines are located adja- available from the third pad from the bottom of the right die
cent to the outer sets of switching matrices. In devices edge.
larger than the XC3020, two vertical long lines in each Internal Busses
column are connectible half-length lines. On the XC3020
only the outer long lines are. A pair of three-state buffers is located adjacent to each
configurable logic block. These buffers allow logic to drive
Long Ii nes can be driven by a logic block or 110 block output the horizontal long lines. Logical operation of the three-
on a column by column basis. This capability provides a state buffer controls allows them to implement wide multi-
common low skew control or clock line within each column plexing functions. Any three-state buffer input can be
of logic blocks. Interconnections of these long lines are selected as drive for the horizontal long line bus by
shown in Figure 14. Isolation buffers are provided at each applying a low logic level on its three-state control line.
input to a long line and are enabled automatically by the See Figure 15a. The user is required to avoid contention
development system when a connection is made. which can result from multiple drivers with opposing logic

3 VERTICAL LONG LINES

GLOBAL ~ bb 66 ~bb
~... .::::;:.;:::
~:::O···:::--::::: ~::O··:0-:: :~::O
':g ....... . ::: : 0··:::--:::::
BUFFER

~
. . ... ... . . ., . .
.... .. .. .. ....
..
ON-CHIP .. ~ ~;:: ~:: :" .
:

r..
:
.. :
.. :
..
t-..
THREE STATE . . .. . . . r. 't..
BUFFERS .. .. ..
PULL-UP
RESISTORS (
FOR ON-CHIP
OPEN DRAIN
SIGNALS ~~~------~~~Da~------~~~-------r~~-4H---~~~

"0
..
..i:J : : :
2 HORIZONTAL LONG LINES
::f9f
Et ...
.':' rsEt ... .jB[t .... :
':,"W .. W.··.·
p t< . t-.; . t" .. ; .' t· ..
Figure 13. Horizontal and vertical long lines provide high fan-out, low-skew signal distribution in each row and column. The global
buffer in the upper left die corner drives a common line throughout the LCA.

2-11
XC3000 Logic Cell Array Family

levels. Control of the three-state input by the same signal of the long line to provide a HIGH output when all con-
that drives the buffer input, creates an 'open drain' wired- nected buffers are non-conducting. This forms fast, wide
AND function. A logical HIGH on both buffer inputs creates gating functions. When data drives the inputs, and sepa-
a high impedance which represents no contention. A· rate signals drive the three-state control lines, these buff-
logical LOW enables the buffer to drive the long line low. ers form multiplexers (three-state buses). Inthis case care
See Figure 15b. Pull-up resistors are available at each end must be used to prevent contention through multiple active

* FOUR OUTER LONG LINES ARE

CONNECTIBLE HALF-LENGTH LINES
1/0 BLOCK CLOCK NETS
D o c:- (2 PER DIE EDGE)

g.:.:."~F~~t#=~~~~~~~~===~*==
::p;-<,"-':7'••-;r-Ht-"'=:----Ht-=~-_tlII-:::=-''----lH-_:_:_.L...-_IlI__:_:_--L.-_flj_,_:_.-
o HORIZONTAL
LONG LINES

THREE STATE
BUFFERS

Figure 14. Programmable interconnection of long lines is provided at the edges of the routing area. Three-state buffers allow the
use of horizontal long lines to form on-chip wired-AND and multiplexed buses. The left two vertical long lines per column
(except 3020) and the outer perimeter long lines may be programmed as connectible half-length.

(LOW1§=J
DN.

Figure 15a. Three-state buffers implement a Wired-AND function. When all the buffer three I
state lines are HIGH, (high impedance), the pull-up resistor(s) provide the HIGH
output. The buffer inputs are driven by the control signals or a LOW.

1105 04

Figure 15b. Three-state buffers implement a Multiplexer where the selection is

accomplished by the buffer three-state signal.

2-12
buffers of conflicting levels on a common line. Figure 16 complete in orderto allowthe oscillator to stabilize. Actual
shows three state buffers, long lines and pull-up resistors. internal connection is delayed until completion of configu-
ration. In Figure 17 the feedback resistor, R1, between
Crystal Oscillator output and input biases the amplifier at threshold. The
value should be as large as practical to minimize loading
Figure 16 also shows the location of an internal high speed of the crystal. The inversion of the amplifier, togetherwith
inverting amplifier which may be used to implement an on- the R-C networks and an AT cut series resonant crystal,
chip crystal oscillator. It is associated with the auxiliary produce the 360 degree phase shiftofthe Pierce oscillator.
buffer in the lower right corner of the die. When the A series resistor, R2, may be included to add to the
oscillator is configured by "MAKEBITS" and connected as amplifier output impedance when needed for phase shift
a signal source, two special user 1/0 Blocks are also con- control, crystal resistance matching, orto Iimitthe amplifier
figured to connect the oscillator amplifier with external input swing to control clipping at large amplitudes. Excess
crystal oscillator components as shoWn in Figure 17. A feedback voltage may be corrected by the ratio of C2/C 1.
divide by two option is available to assure symmetry. The The amplifier is designed to be used from 1 MHz to one-
. oscillator circuit becomes active before configuration is half the specified CLB toggle frequency. Use at frequen-

•
BI-DIRECTIONAL
INTERCONNECT GLOBALNET\ 3 VERTICAL LONG
BUFFERS

II I I GG
11 II I- /

I
LINES PER COLUMN

GH
II I
---l
.1
W
.1
UV HORIZONTAL LONG LINE

~
PULL-UP RESISTOR
1
- I--
\\
dY 1 p~ HORIZONTAL LONG LINE

~O 10
I--

} if
OSCILLATOR
AMPLIFIER OUTPUT

- --i
I~
IA V DIRECT INPUT OF P47
TO AUXILIARY BUFFER
J
r
1
1r;:lG'- r- 1 'ilH'-- I
'P4'i

fecc ~
V CRYSTAL OSCILLATOR
+ ~ BUFFER

--
1 1
~ '--
J THREE-STATE INPUT
""-rT- .,-,-- ~¥;l>
.0 y.. - p THREE-STATE CONTROL
- k
L..::-"
L
~J
J- ---
~
:--- THREE-STATE BUFFER

-- .0 .q.ok
~ ~
r- ALTERNATE BUFFER
000 []
r ~ I' 00 tI:
e;Je;J 1
JI 00
eJeJ ~
\ OSCILLATOR
AMPLIFIER INPUT

Figure 16. An XACT Development System extra large view of possible

interconnections in the lower right corner of the XC3020.

2-13
XC3000 Logic Cell Array Family

cies below 1 MHz may require individual characterization determined by the input levels of three mode pins; MO, M1
with respect to a series resistance. Crystal oscillators and M2.
above 20 MHz generally require a crystal which operates
in a third overtone mode, where the fundamental fre- In Master configuration modes the LCA becomes the
quency must be suppressed by the R-C networks. When source of Configuration Clock (CCLK). The beginning of
the oscillator inverter is not used, these 1/0 Blocks and configuration of devices using Peripheral or Slave modes
their package pins are available for general user 1/0. must be delayed long enough for their initialization to be
completed. An LCA with mode lines selecting a Master
configuration mode extends its initialization state using
PROGRAMMING four times the delay (43 to 130 ms) to assure that all daisy-
chained slave devices which it may be driving will be ready
Initialization Phase even if the master is very fast, and the slave(s) very slow.
Figure 18 shows the state sequences. At the end of Initiali-
An internal power-on-reset circuit is triggered when power
is applied. When Vee reaches the voltage at which Table 1
portions of the LCA begin to operate (2.5 to 3 Volts), the
programmable 1/0 output buffers are disabled and a high MO M1 M2 Clock Mode Data
impedance pull-up resistor ·is provided for the user 1/0
pins. A time-out delay is initiated to allow the power supply 0 0 0 active Master Bit Serial
voltage to stabilize. During this time the power-down 0 0 1 active Master Byte Wide Addr. = 0000 up
mode is inhibited. The Initialization state time-out (about 0 1 0 reserved
11 to 33 ms) is determined by a 14-bit counter driven by a 0 1 1 active Master : Byte Wide Addr. = FFFF down
self-generated, internal timer. This nominal 1 MHz timer is 0 0 reserved
subject to variations with process, temperature and power 0 1 passive Peripheral Byte Wide
supply over the range of 0.5 to 1.5 MHz. As shown in 1 0 reserved
Table 1, five configuration mode choices are available as 1 passive Slave Bit Serial

INTERNAL EXTERNAL

XTALl

o
o
SUGGESTED COMPONENT VALUES R2
Rl 1-4MO
R2 0-1 KO
(may be required for low frequency, phase
shift andlor compensation level for crystal Q)
Cl,C210-40pf
~ Cl
~C2
Yl 1 - 20 MHz AT cut series resonant

68 PIN 84 PIN 100 PIN 132 PIN 164 PIN 175 PIN
PLCC PLCC I PGA COFP I PQFP PGA COFP PGA
I XTAL 1 (OUn 47 57 I Jll 67 I 82 P13 105 T14
1105 14
XTAL2 IN 43 53 J Lll 61 J 76 M13 99 P15

Figure 17. When activated in the "MAKEBITS" program and by selecting an output network for its buffer, the
crystal oscillator inverter uses two unconfigured package pins and external components to implement an oscillator.
An optional divide-by-two mode is available to assure symmetry.

2-14
zation the LCA enters the Clear state where it clears the preamble and length count in on positive and out on
configuration memory. The active low, open-drain initiali- negative configuration clock edges. An LCA which has
zation signal INIT indicates when the Initialization and received the preamble and length count then presents a
Clear states are complete. The LCA tests for the absence HIGH Data Out until it has intercepted the appropriate
of an external active low RESET before it makes a final number of data frames. When the configuration program
sample of the mode lines and enters the Configuration memory of an LCA is full and the length count does not
state. An external wired-AND of one or more INIT pins can compare, the LCA shifts any additional data through, as it
be used to control configuration by the assertion of the did for preamble and length count.
active low RESET of a master mode device or to signal a
processor that the LCAs are not yet initialized. When the LCA configuration memory is full and the length
count compares, the LCA will execute a synchronous
If a configuration has begun, a re-assertion of RESET for start-up sequence and become operational. See
a minimum ofthree internal timer cycles will be recognized Figure 20. Three CCLK cycles after the completion of
and the LCA will initiate an abort, returning to the Clear loading configuration data the user 110 pins are enabled as
state to clear the partially loaded configuration memory configured. As selected in MAKEBITS, the internal user-
words. The LCA will then re-sample RESET and the mode logic reset is released either one clock cycle before or after
lines before re-entering the Configuration state. A re- the 1/0 pins become active. A similar timing selection is
program is initiated when a configured LCA senses a programmable for the DONE/PROG output signal.
HIGH to LOW transition on the DONEIPROG package pin. DONE/PROG may also be programmed to be an open
The LCA returns to the Clear state where the configuration drain or include a pull-up resistor to accommodate wired
memory is cleared and mode lines re-sampled, as for an ANDing. The High During Configuration (HDC) and Low
aborted configuration. The complete configuration pro- During Configuration (LDC) are two user 1/0 pins which
gram is cleared and loaded during each configuration pro- are driven active when an LCA is in its Initialization, Clear
gram cycle. or Configure states. They and DONE/PROG provide
signals for control of external logic signals such as reset,
Length count control allows a system of multiple Logic Cell bus enable or PROM enable during configuration. For
Arrays, of assorted sizes, to begin operation in a synchro- parallel Masterconfiguration modes these signals provide
nized fashion. The configuration program generated by PROM enable control and allow the data pins to be shared
the MakePROM program of the XACT development sys- with user logic signals.
tem begins with a preamble of 111111110010 followed by
a 24-bit 'length count' representing the total number of User 1/0 inputs can be programmed to be either TTL or
configuration clocks needed to complete loading of the CMOS compatible thresholds. At power-up, all inputs
configuration program(s). The data framing is shown in have TTL thresholds and can change to CMOS thresholds
Figure 19. All LCAs connected in series read and shift

POWER-ON DELAY IS
214 CYCLES FOR NON-MASTER MODE-11 TO 33 mS
2'· CYCLES FOR MASTER MODE--43 TO 130 mS

USER UO PINS WITH HIGH IMPEDANCE PULL-UP

~_ _I_NI_T_SI_GN_A_L~LO_W_(:...XC_3_00_0:...)_~ .• t~:~6~H

LOW ON DONE/PROGRAM AND RESET

CLEAR IS
-200 CYCLES FOR THE XC3020--130 TO 400 I'S
-250 CYCLES FOR THE XC303D-165 TO 500!'8
110515 -290 CYCLES FOR THE XC3042-195 TO 580 I'S
-330 CYCLES FOR THE XC3064-220 TO 660 !'8
-375 CYCLES FOR THE XC3090-250 TO 750 !'8
Figure 18. A state diagram of the configuration process for power-up and reprogram.

2-15
XC3000 Logic Cell Array Family

at the completion of configuration if the user has selected Configuration Data

CMOS thresholds. The threshold of PWRDWN and the
direct clock inputs are fixed at a CMOS level. Configuration data to define the function and interconnec-
tion within a Logic Cell Array are loaded from an external
If the crystal oscillator is used it will begin operation before storage at power-up and on a re-program signal. Several
configuration is complete to allow time for stabilization methods of automatic and controlled loading of the re-
before it is connected to the internal circuitry. quired data are available. Logic levels applied to mode se-

11111111 - DUMMY BITS' ]

0010 - PREAMBLE CODE
< 24-BIT LENGTH COUNT> - CONFIGURATION PROGRAM LENGTH HEADER
1111 - DUMMY BITS (4 BITS MINIMUM)

o < DATA FRAME #001> 111 FORXC3020

o < DATA FRAME #002 > 111
o <DATAFRAME#OO3> 111 197 CONFIGURATION DATA FRAMES PROGRAM DATA

(EACH FRAME CONSISTS OF:

A START BIT (0) REPEATED FOR EACH LOGIC
A 71-BIT DATA FIELD CELL ARRAY IN A DAISY CHAIN
o <DATAFRAME#196> 111 THREE STOP BITS
o < DATA FRAME # 197> 111

1111 POSTAMBLE CODE (4 BITS MINIMUM)

'THE LCA DEVICES REQUIRE 4 DUMMY BITS MIN., XACT 2.10 GENERATES 8 DUMMY BITS 1105 05

Device XC3020 XC3030 XC3042 XC3064 XC3090

Gates 2000 3000 4200 6400 9000

CLBs 64 100 144 224 320

Row X Col (8 X8) (lOX 10) (12 X 12) (16X 14) (20 X 16)

lOBs 64 80 96 120 144

Flip-flops 256 360 480 688 928

Bits per frame 75 92 108 140 172

(w/l start 3 stop)

Frames 197 241 285 329 373

Program Data = 14779 22176 30784 46064 64160

Bits· Frames + 4
(excludes header)

PROM size (bits) = 14819 22216 30824 46104 64200

Program Data
+ 40 bit Headers

Figure 19. The internal Configuration Data Structure for an LCA shows the preamble, length count
and data frames which are generated by the XACT Development System.

The Length Count produced by the "MAKEBIT" program = [(40-bit preamble + sum of program data + 1 per daisy chain device)
rounded up to multiple of 8]- (2::; K::; 4) where K is a function of DONE and RESET timing selected. An additional 8 is added if
roundup increment is less than K. K additional clocks are needed to complete start-up after length count is reached.

2-16
lection pins at the start of configuration time determine the supply currents. If unused blocks are not sufficient to
method to be used. See Table 1. The data may be either complete the 'tie,' the FLAGNET command of EDITLCA
bit-serial or byte-parallel, depending on the configuration can be used to indicate nets which must not be used to
mode. Various Xilinx Programmable Gate Arrays have drive the remaining unused routing, as that might affect
different sizes and numbers of data frames. To maintain timing of user nets. NORESTORE will retain the results of
compatibility between various device types, the Xilinx TIE for timing analysis with QUERYNET before
2000 and 3000 product families use compatible configura- RESTORE returns the design to the untied condition. TIE
tion formats. For the XC3020, configuration requires can be omitted for quick breadboard iterations where a few
14779 bits for each device, arranged in 197 data frames. additional mA of Icc are acceptable.
An additional 40 bits are used in the header. See
Figure 20. The specific data format for each device is pro- The configuration bit-stream begins with HIGH preamble
duced by the MAKEBITS command of the development bits, a four-bit preamble code and a 24-bit length count.
system and one or more of these files can then be When configuration is initiated, a counter in the LCA is set
combined and appended to a length count preamble and to 0 and begins to count the total number of configuration
be transformed into a PROM format file by the 'MAKE clock cycles applied to the device. As each configuration
PROM' command of the XACT development system. A data frame is supplied to the LCA, it is internally assembled
compatibility exception precludes the use of a 2000 series into a data word. As each data word is completely
device as the masterfor3000 series devices iftheir DONE assembled, it is loaded in parallel into one word of the •
or RESET are programmed to occur after their outputs internal configuration memory array. The configuration
become active. The ''tie'' option of the MAKEBITS program loading process is complete when the current length count
defines output levels of unused blocks of a design and equals the loaded length count and the required configu-
connects these to unused routing resources. This pre- ration program data frames have been written. Internal
vents indeterminant levels which might produce parasitic user flip-flops are held reset during configuration.

POSTAMBLE

r"J :l' rJ}Gt--LAST--+-r~'-i-r~ 'f , ,

Irr-'I-

, PREAMBLE 'LENGTH COUNT'

START
DATA , 'r'
J3
START LENG TH COUNT*

1Ul.l--1 _----l
DOUT LEAD DEVICE
HIGH
WEAK PULL·UP
I/O ACTIVE

1/2 CLOCK CYCLE

DELAY FROM DATA INPUT PROGRAM / . ; DONE

INTERNAL RESET \
'\
• THE CONFIGURATION DATA CONSISTS OF A COMPOSITE TIMING OF THE ASSERTION OF DONE AND
4O-BIT PREAMBLE/LENGTH-COUNT, FOLLOWED BY ONE OR TERMINATION OF THE INTERNAL RESET
MORE CONCATENATED LCA PROGRAMS, SEPARATED BY MAY EACH BE PROGRAMMED TO OCCUR
4-BIT POSTAMBLES. AN ADDITIONAL FINAL POSTAMBLE BIT ONE CYCLE BEFORE OR AFTER THE I/O
IS ADDED FOR EACH SLAVE DEVICE AND THE RESULT ROUNDED OUTPUTS BECOME ACTIVE.
UP TO A BYTE BOUNDRY. THE LENGTH COUNT IS TWO LESS
THAN THE NUMBER OF RESULTING BITS.

110506 Figure 20. Configuration and start-up of one or more LCAs.

110506

2-17
XC3000 Logic Cell Array Family

Two user programmable pins are defined in the unconfig- other portions of the system. The state diagram of Figure
ured Logic Cell array. High During Configuration (HDC) 18 illustrates the configuration process.
and Low During Configuration (LDC) as well as
DONEIPROG may be used as external control signals Master Mode
during configuration. In Master mode configurations it is
convenient to use LDC as an active-low EPROM Chip In Master mode, the Logic Cell Array automatically loads
Enable. After the last configuration data-bit is loaded and configuration data from an external memory device. There
the length count compares, the user 1/0 pins become are three Master modes which use the internal timing
active. Options in the MAKEBITS program allow timing source to supply the configuration clock (CCLK) to time the
choices of one clock earlier or later for the timing of the end incoming data. Serial Master mode uses serial configura-
of the internal logic reset and the assertion of the DONE tion data supplied to data-in (DIN) from a synchronous
signal. The open-drain DONE/PROG output can be AND- serial source such as the Xilinx Serial Configuration
tied with multiple Logic Cell Arrays and used as an active PROM shown in Figure 21. Parallel Master Low and
high READY, an active low PROM enable or a RESET to Master High modes automatically use parallel data sup-

DURING CONFIGURATION
THE 5KO M2 PULL·DOWN
RESISTOR OVERCOMES THE
INTERNAL PULL·UP.
BUT IT ALLOWS M2 TO
BE USER 110.
DOUT
M2
HOC
LDC
GENERAL·
PURPOSE INIT (XC3000)
USER I/O
PNS

: }OTHER
: 110 PINS

LCA
OPTIONAL
IDENTICAL SLAVE
LeAs CONFIGURED
THE SAME

.5V

RESET RESET ,. .................. .,,

DIN
Vee Vpp
DATA SERIAL
.,, ..
CCLK CLK MEMORY CASCADED
SERIAL
LDC CE CEO MEMORY

.................. .
DONE DIP OE XC1736
,, ,
~ ~

1105 16

Figure 21. Master Serial Mode. The one-time·programmable XC1736 Serial Configuration PROM supports automatic loading of
configuration programs up to 36K bits. Multiple devices can be cascaded to support additional LCAs. An early DONE inhibits the
XC1736 data output a CCLK cycle before the LCA lID become active.

2-18
plied to the 00-07 pins in response to the 16-bit address internally serialized by the configuration clock. As each
generated by the LCA. Figure 22 shows an example of the data byte is read, the least significant bit of the next byte,
parallel Master mode connections required. The LCA HEX ~O, becomes the next bit in the internal serial configuration
starting address is 0000 and increments for Master Low word. One Master mode LCA can be used to interface the
mode and it is FFFF and decrements for Master High configuration program-store and pass additional concate-
mode. These two modes provide address compatibility nated configuration data to additional LCAs in a serial
with microprocessors which begin execution from oppo- daisy-chain fashion. CCLK is provided for the slaved
site ends of memory. For Master high or low, data bytes devices and their serialized data is supplied from OOUT to
are read in parallel by each read clock (RCLK) and DIN - OOUT to DIN etc.

USER CONTROL OF HIGHER

.--r---------,...-+5V ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT FROM
ALTERNATIV E CONFIGU RATIONS

5kn DOUT *
M2 CCLK *

GENERAL-
PURPOSE
HOC

RCLK
A15

A14
II
USER 110
PNS INIT (XC3000) A13 EPROM
(2Kx S
A12 OR LARGER)
} OTHER A11
I/O PINS
A10 A10
LeA
RESET RESET A9 A9
AS AS
A7 A7 07
A6 A6
04 A5 A5

A4 A4
02 A3 A3

01 A2 A2
DO A1 A1 01

AO AO

DONE DIP

-----d=
DATA BUS

(OC~pt~~ _ _ _-'X'-_A_DD_R_E_SS_...:
00-07-------.X ~
PROM: BYTE N

--{,..----.~~:~:::rs:TS====t1~'1THr=~\
RCLK

(~~Tt~~~ l1+_ _ _ _ _\~.'8O~~=====:I.

S CCLKs
'--
(OU{P<C-~~*
DOUT~
(OUTPUT) ~ DO BYTE N *

* FOR OPTIONAL SLAVE MODE LCAs IN A DAISY CHAIN

1105 17

Figure 22. Master Parallel Mode. Configuration data are loaded automatically from an external byte wide PROM.
An early DONE inhibits the PROM outputs a CCLK before the LCA 110 become active.

2-19
XC3000 Logic Cell Array Family

Peripheral Mode modes, Peripheral mode may also be used as a lead

device for a daisy-chain of slave devices.
Peripheral mode provides a simplified interface through
which the device may be loaded byte-wide, as a processor Slave Mode
peripheral. Figure 23 shows the peripheral mode connec-
tions. Processor write cycles are decoded from the com- Slave mode provides a simple interface for loading the
mon assertion ofthe active low Write Strobe (WS) , and two Logic Cell Array configuration as shown in Figure 24.
active low and one active high Chip Selects (CSO, CS1, Serial data are supplied in conjunction with a synchroniz-
CS2). If all these signals are not available, the unused ing input clock. Most Slave mode applications are in daisy-
inputs should be driven to their respective active levels. chain configurations in which the data input are supplied
The Logic Cell Array will accept one byte of configuration by the previous Logic Cell Array's data out, while the clock
data on the 00-07 inputs for each selected processor is supplied by a lead device in Master or Peripheral mode.
Write cycle. Each byte of data is loaded into a buffer Data may also be supplied by a processor or other special
register. The LCA generates a configuration clock from circuits.
the internal timing generator and serializes the parallel
input data for internal framing or for succeeding slaves on Daisy-Chain
Data Out (DOUT). A output HIGH on READY/BUSY pin
indicates the completion of loading for each byte when the The Xilinx XACT development system is used to create a
input register is ready for a new byte. As with Master composite configuration bit stream for selected LCAs

CONTROL ADDRESS DATA

SIGNALS BUS BUS

ADDRESS
DECODE
LOGIC
+5V

REPROGRAM

CS2 7lI/////

CCLK (INTERNAL)\./ \j

-----------------------~
DOUT ~

RDY/BUSY

*FOR OPTIONAL SLAVE MODE LCAs IN A DAISY CHAIN 1105 18

Figure 23. Peripheral Mode. Configuration data are loaded using a byte-wide data bus from a microprocessor.

2-20
including: a preamble, a length count for the total bit- and write-strobe cycle. The internal timing generator
stream, multiple concatenated data programs and a continues to operate for general timing and synchroniza-
postamble plus an additional fill bit per device in the serial tion of inputs in all modes.
chain. After loading and passing-on the preamble and
length count to a possible daisy-chain, a lead device will Special Configuration Functions
load its configuration data frames while providing a HIGH
DOUT to possible down-stream devices as shown in The configuration data include control over several special
Figure 25. Loading continues while the lead device has functions in addition to the normal user logic functions and
received its configuration program and the current length interconnect:
count has not reached the full value. The additional data
are passed through the lead device and appear on the • Input thresholds
Data Out (DOUT) pin in serial form. The lead device also • Readback enable
generates the Configuration Clock (CCLK) to synchronize • DONE pull-up resistor
the serial output data and data in of down-stream LCAs. • DONE timing
Data are read in on DIN of slave devices by the positive • RESET timing
edge of CCLK and shifted out the DOUT on the negative • OSCillator frequency divided by two
edge of CCLK. A parallel Master mode device uses its
internal timing generator to produce an internal CCLK of 8
times its EPROM address rate, while a Peripheral mode
Each of these functions is controlled by configuration data
bits which are selected as part of the normal XACT
II
device produces a burst of 8 CCLKs for each chip select development system bit-stream generation process.

+5V
1
I J
MO Ml PWRDWN
MICRO SkU

--
COMPUTER
,--
STRB CCLK M2 - *
DO DIN DOUT - *
110
Dl I-- HDC -
D2 f-- LDC C > - - GEN ERAL-
PORT +5V PUR POSE
03 t-- LCA USERI/o

D41-- ;--

D5 f--
liP OTHER {
VO PINS

r
D6 !----

r RESET
-
D7 INIT

RESET

==x,.
~
DIN BITN BITN+l

j \-------. I
m
CCLK

DOUT BITN-l BITN

(OUTPUT)

* FOR OPTIONAL SLAVE MODE LeAs IN A DAISY CHAIN

110519

Figure 24. Slave Mode. Bit-serial configuration data are read at rising edge of the CCLK.
Data on DOUr are provided on the falling edge of CCLK.

2-21
XC3000 Logic Cell Array Family

Input Thresholds Readback

Prior to the completion of configuration all LCA input The contents of a Logic Cell Array may be read back if it
thresholds are TTL compatible. Upon completion of con- has been programmed with a bit-stream in which the
figuration the input thresholds become either TTL or Readback option has been enabled. Readback may be
CMOS compatible as programmed. The use of the TTL used for verification of configuration and as a method of
threshold option requires some additional supply current determining the state of intemallogic nodes during debug-
forthreshold shifting. The exception is the threshold ofthe ging with the XACTOR In-Circuit debugger. There are
PWRDWN input and direct clocks which always have a three options in generating the configuration bit-stream:
CMOS input. Prior to the completion of configuration the
user 1/0 pins each have a high impedance pull-up. The • "Never" will inhibit the Readback capability.
configuration program can be used to enable the 1/0 Block • "One-time," will inhibit Readback after one Readback
pull-up resistors in the Operational mode to act either as an has been executed to verify the configuration.
input load or to avoid a floating input on an otherwise • "On-command" will allow unrestricted use of Read-
unused pin. back.

+~v +~v
+5V

T
l~
I I I I ~ I ~
MO M1 PWRDWN MO M1 PWRDWN MO M1 PWRDWN

51<0 CCLK r-- ' - - - CCLK 51<0 '--- CCLK 5

DOUT \I
DIN DOUT DIN DOUT I-
- M2 LCA " ... LCA
SLAVE #1 SLAVE#n
- HOC M2 .... M2 ....
GENERAL·
-< RCLK A15 r- .... - A15 HOC r- HOC I--
PURPOSE
USER 110
A14 A14 LDC p- GENERAL· LOC p- GENERAL-
PURPOSE PURPOSE
PNS A13 A13 r-- USER VO r-- USER VO
- A12 A12
EPROM
OTHER { OTHER {
VO PINS VOPINS
OTHER
I/O PINS A11 A11 r- I--
- LCA A10 A10 INIT f>- INITP-
MASTER
A9 A9 r - - DIP r - - DIP
r-- 07 A8 AS r< RESET r< RESET
r - - 06 A7 A7 07'"
V-- 05 A6 A6 06",
NOTE: XC2QOO DEVICESOONOT
r-- 04 A5 A5
05 """" HAVE INIT TO HOLD OF FAMASTER
r--- 03 A4 A4 04", DEVICE. RESET OF A MASTER DEVICE
r-- 02 />3 />3
03 """"
SHOULD BE ASSERTED BY AN EXTERNAL
TIMING CIRCUIT TO ALLOW FOR LCA CCLK
r - - 01 A2 A2
D2 """" VARIATIONS IN CLEAR STATE TIME.
r - - DO A1 A1
01 """"
AO AO
LOC OE
00""""

rI -< RESET
olP INIT P;;c.L CE

8
OPEN
r-r--"+5V

5 1<0 EACH

REPROGRAM ' " COLLECTOR \I

....
SYSTEM RESET ~ .."
~ "" 1105 20

Figure 25. Master Mode configuration with daisy chained slave mode devices.
All are configured from the common EPROM source. The Slave mode device INIT signals
delay the Master device configuration until they are initialized. A well defined termination
of SYSTEM RESET is needed when controlling multiple LCAs.

Any XC3000 slave driven by an XC2000 master mode device must use "early DONE and early internal reset".
(The XC2000 master will not supply the extra clock required by a "late" programmed XC3000.)

2-22
Readback is accomplished without the use of any of the driver which pulls DONEIPROG LOW. Once it recognizes
user 1/0 pins; only MO, M1 and CCLK are used. The a stable request, the Logic Cell Array will hold a LOW until
initiation of readback is produced by a LOW to HIGH the new configuration has been completed. Even if the re-
transition of the MO/RTRIG (Read Trigger) pin. Once the program request is externally held LOW beyond the con-
readback command has been given, the input CCLK is figuration period, the Logic Cell Array will begin operation
driven by external logic to read back each data bit in a upon completion of configuration.
format similar to loading. After two dummy bits, the first
data frame is shifted out, in inverted sense, on the DONE Pull-up
M 1/RDATA (Read Data) pin. All data frames must be read
back to complete the process and return the mode select DONEIPROG is an open drain 1/0 pin that indicates the
and CCLK pins to their normal functions. LCA is in the operational state. An optional internal pull-up
resistor can be enabled by the user of the XACT develop-
The readback data includes the current state of each ment system when 'Make Bits' is executed. The
internal logic block storage element, and the state of the DONEIPROG pins of multiple LCAs in a daisy-chain may
[.i and .ff] connection pins on each 1/0 Block. These data be connected together to indicate all are DONE or to direct
are imbedded into unused configuration bit positions dur- them all to re-program.
ing readback. This state information is used by the Logic
Cell Array development system In-Circuit Verifier to pro- DONE Timing
vide visibility into the internal operation of the logic while
the system is operating. To readback a uniform time- The timing of the DONE status signal can be controlled by
sample of all storage elements it may be necessary to a selection in the MAKEBITS program to occur a CCLK
inhibit the system clock. cycle before, or after, the timing of outputs being activated.
See Figure 20. This facilitates control of external functions
Re-program such as a PROM enable or holding a system in a wait state.

The Logic Cell Array configuration memory can re-written RESET Timing
while the device is operating in the user's system. To
initiate a re-programming cycle, the dual function package As with DONE timing, the timing of the release of the
pin DON E/PROG must be given a HIGH to LOW transition. internal RESET can be controlled by a selection in the
To reduce sensitivity to noise, the input signal is filtered for MAKEBITS program to occur a CCLK cycle before, or
2 cycles of the LCA's internal timing generator. When re- after, the timing of outputs being enabled. See Figure 20.
program begins, the user programmable 1/0 output buffers This reset maintains all user programmable flip-flops and
are disabled and high impedance pull-ups are provided for latches in a 'zero' state during configuration.
the package pins. The device returns to the Clear state
and clears the configuration memory before it indicates Crystal Oscillator Division
'initialized'. Since this clear operation uses chip-individual
internal timing, the master might complete the clear opera- A selection in the MAKEBITS program allows the user to
tion and then start configuration before the slave has incorporate a dedicated divide-by-two flip-flop in the crys-
completed the clear operation. To avoid this problem, tal oscillator function. This provides higher assurance of a
wire-AND the slave INIT pins and use them to force a symmetrical timing signal. Although the frequency stabil-
RESET on the master (see Figure 25). Reprogram control ity of crystal oscillators is high, the symmetry of the
is often implemented using an external open collector waveform can be affected by bias or feedback drive.

2-23
XC3000 Logic Cell Array Family

PERFORMANCE of the storage element, the critical timing is data set-up

relative to the clock edge provided to the flip-flop element.
Device Performance The delay from the clock source to the output of the logic
block is critical in the ti ming of signals produced by storage
The high performance of the Logic Cell Array is due in part elements. Loading of a Logic Block output is limited only
to the manufacturing process, which is similar to that used by the resulting propagation delay of the larger intercon-
for high speed CMOS static; memories. Performance can nect network. Speed performance of the logic block is a
be measured in terms of minimum propagation times for function of supply voltage and temperature. See Figures
logic elements. The parameter which traditionally de~ 28 and 29.
scribes the overall performance of a gate array:is the
toggle frequency of a flip-flop. The configuration for Interconnect Performance
determining the toggle performance of the Logic Cell Array
is shown in Figure 26. The flip-flop output Q is fed back Interconnect performance depends on the routing re-
a
through the combinatorial logic as to form the toggle flip- source used to implement the signal path. As discussed
flop. earlier, direct interconnect from block to block provides a
fast path for a signal. The single metal segment used for
Actual Logic Cell Array performance is determined by the Long lines exhibits low resistance from end to end, but
timing of critical paths, including both the fixed timing for relatively high capacitance. Signals driven through a
the logic and storage elements in that path, and the timing programmable switch will have the additional impedance
associated with the routing of the network. Examples of of the switch added to their normal drive impedance.
internal worst case timing are incluqed in the performance
data to allow the user to make the best use of the capabili- General purpose interconnect performance depends on
ties of the device. The XACT development system timing the number of switches and segments used, the presence
calculator or XACT generated simulation models should of the bi-directional re-powering buffers and the overall
be used to calculate worst case paths by using actual loading on the signal path at all points along the path. In
impedance and loading information. Figure 27 shows a calculating the worst case timing for a general interconnect
variety of elements which are. involved in determing sys- path the timing calculator portion of the XACT develop-
tem performance. Actual measurement of internal timing ment system accounts for all of these elements. As an
is not practical and often only the sum of component timing approximation, interconnect timing is proportional 10 the
is relevant as in the case of input to output. The relation- summation of totals of local metal segments beyond each
ship between input and output timing is arbitrary and only programmable switCh. In effect, the time is a sum of R-C
the total determines performance. Timing components of time each approximated by an R times the total C it drives.
internal functions may be determined by measurement of The R of the switch and the C of the interconnect isa
differences at the pins of the package. A synchronous function of the particular device performance grade. For a
logic function which involves a clock to block"output, and string of three local interconnects, the approximate time at
a block-input to clock set-up is capable of higher speed the first segment, afterlhe first switch resistance would be
operation than a logic configuration of two synchronous three units; an additional two units after the next switch
blocks with an extra combinatorial block level between plus an additional unit after the last switch in the chain. The
them. System clock rates to 60% of the toggle frequency interconnect R-C chain terminates at each re-powering
are practical for logic in which an extra combinatorial level buffer. The capacitance of the actual block inputs is not
is located between synchronized blocks. This allows im- significant; the capacitance is in the interconnect metal
pie mentation of functions of up to 25 variables. The use of and switches. Figure 30 illustrates this.
the wired-AND is also available for wide, high speed func-
tions.

Logic Block Performance

Logic block performance is expressed as the propagation

time from the interconnect point at the input of the combi- CLOCK -:.,-:- - - I >
nato rial logic to the output of the block in the interconnect
area. Combinatorial performance is independent of the
specific logicfundion because of the table look-up based
t. ....J 1105 07

implementation. Timing is different when the combinato-

rial logic is used in conjunction with the storage element. Figure 26. ''Toggle" Flip-Flop used to
For the combinatorial logic function driving the data input characterize device performance.

2-24
 CLOCK TO

r--TCKO OUTPUT

····································-········-·····CLB............~
.1'
COMBINATORIAL SETUP
T,Lo--....•...I·>-----T,CK ---Of·1
......................................................CLB .....::
r·······
CLS· •. lOS

w
LOGIC 1-+--;'---; .-{>+

CLOCK-~-----+-----------4r~
L_ (K)
••

r
PAD

~ .. .. ......................................... .........
,

I"---TCKO~
lOS ••

PAD ~-----{>-J
110521
~TPID~ I' TOKOP-------t·1

Logic input to Output

K Clock
Description

Combinatorial

To output
Logic-input setup
Speed Grade

TllO

TCKo
TICK
Symbol Min

12
-50

Max

14

12
Min Max

8
-70

8
7
-100

Min Max

7
Units

ns

ns
ns
•
Logic-input hold TCKI 0 0 0 ns

InputlOutput Pad to input (direct) TPID 9 6 4 ns

-
Output to pad (fast) Top 15 9 6 ns

1/0 clock to pad (fast) TOKPo 18 13 10 ns

FF toggle frequency FClK 50 70 100 MHz

Figure 27. Examples of Primary Block Speed Factors.

Actual timing is a function of various block factors combined with routing factors.
Overall performance can be evaluated with the XACT timing calculator or by an optional simulation.

1.2
1.3

1.2
o
w 1.1
1.1 N
C :::;
w ..:
N
:::; 1.0
<:
::;
~
a:
0
0.9 ~ 1.0+-------------"1-
~
>- 0.8
:5
~
w
w Cl
0 0.7
0.9
0.6

0.5 4 4.5 5.0 5.5 6.0

-55 -40 0 30 70 85 Vcc
1105 08 TEMPERATURE iC) 110522

Figure 28. Change in speed performance as a function of Figure 29. The speed performance of a CMOS device
temperature. normalized for 30°C. increases with Vcc within the operating range.

2-25
XC3000 Logic Cell Array Family

POWER Power Dissipation

Power Distribution The Logic Cell Array exhibits the low power consumption
characteristic of CMOS ICs. For any design the user can
Power for the LCA is distributed through a grid to achieve use Figure 32 to calculate the total power requirement
high noise immunity and isolation between logic and I/O. based on the sum of the capacitive and DC loads both
Inside the LCA, a dedicated Vcc and ground ring surround- external and internal. The configuration option of TTL chip
ing the logic array provides power to the I/O drivers. See inputthreshold requires power for the threshold reference.
Figure 31. An independent matrix of Vcc and ground lines The pOwer required by the static memory cells which hold
supplies the interior logic of the device. This power the configuration data is very low and may be maintained
distribution grid provides a stable supply and ground for all in a power-down mode.
internal logic, providing the external package power pins
are all connected and appropriately decoupled. Typically Typically most of power dissipation is produced by exter-
a 0.1 ~F capacitor connected near the Vcc and ground pins nal capacitive loads on the output buffers. This load and
of the package will provide adequate decoupling. frequency dependent power is 25 ~W/pF/MHz per output.
Another component of I/O power is the DC loading on each
Output buffers capable of driving the specified 4 mA loads output pin by devices driven by the Logic Cell Array.
under worst-case conditions may be capable of driving 25
to 30 times that current in a best case. Noise can be Internal power dissipation is a function of the number and
reduced by minimizing external load capacitance and size olthe nodes, and the frequency at which they change.
reducing simultaneous output transitions in the same In an LCA the fraction of nodes changing on a given clock
direction. It may also be beneficial to locate heavily loaded is typically low (10-20%). For example, in a large binary
output buffers near the ground pads .. The I/O Block output counter, the average clock cycle produces changes equal
buffers have a slew limited mode which should be used to one CLB output at the clock frequency. Typical global
where output rise and fall times are not speed critical. clock buffer power is between 1.7 mW/MHz for the
Slew-limited outputs maintain their DC drive capability, but XC3020 and 3.6 mW/MHz for the XC3090. The internal
generate less external reflections and internal noise. More capacitive lo~d is more a function of interconnectthan fan-
than 32 fast outputs should not be switching in the same out. With a ''typical'' load ofthree general interconnect seg-
direction exactly simultaneously. A few ns of deliberate ments, each Configurable Logic Block output requires
skew can alleviate this problem of "ground-bounce". about 0.4 mW per MHz of its output frequency.

~ ___ -: ~WITCH MATRIX --.... ~ ___ -:

'~~------~---r----~~~-----'------~~---; ~--~--
i. / i. ___ ~
R3

1-- ..
CLB ,
t----.~_

TIMING: INCREMENTAL

IF R1=R2=R3=R AND C,=C2=C 3 =C T1 =3RC T2=3RC+2RC T3=3RC+2RC+1RC 6RC+ BUFFER

THEN CUMULATIVE TIMING =3RC =5RC =6RC

110523
Figure 30. Interconection timing example. Use of the XACT timing calculator
or XACT-generated simulation model provide actual worst-case performance information.

2-26
Total Power = Vcc· Iceo + external (DC + capacitive) supply a retention voltage to the Vcc pins of the package.
+ internal (CLB + lOB + Long line + pull-up) When normal power is restored, Vcc is elevated to its
normal operating voltage and PWRDWN is returned to a
Because the control storage of the Logic Cell Array is HIGH. The Logic Cell Array resumes operation with the
CMOS static memory, its cells require a very low standby same internal sequence that occurs at the conclusion of
current for data retention. In some systems, this low data configuration. Internal I/O and logic block storage ele-
retention current characteristic can be used as a method ments will be reset, the outputs will become enabled and
of preserving configurations in the event of a primary the DONE/PROG pin will be released. No configuration
power loss. The Logic Cell Array has built in power-down programming is involved.
logic which, when activated, will disable normal operation
of the device and retain only the configuration data. All When the power supply is removed from a CMOS device
internal operation is suspended and output buffers are it is possible to supply some power from an input signal.
placed in their high impedance state with no pull-ups. The conventional electro-static input protection is imple-
Power-down data retention is possible with a simple bat- mented with diodes to the supply and ground. A positive
tery-backup circuit because the power requirement is voltage applied to an input (or output) will cause the
extremely low. For retention at 2.4 volts the required positive protection diode to conduct and drive the power
current is typically on the order of 50 nanoamps. pin. This condition can produce invalid power conditions
and should be avoided. A large series resistor might be
To force the Logic Cell Array into the Power-Down state, used to limit the current or a bi-polar buffer may be used to
the user must pull the PWRDWN pin low and continue to isolate the input signal.

GND

GROUND AND
VeeRING FOR
+ --+- -+-- +- -+-- + --+- -+ 1/0 DRIVERS

+-- +-- + --+ --+ --+--+, --+,

, ,
+--+- -+ -- +- -+- -+--+- -+
I I I I I I I I
I I I I I I I I

+-- + -- + --+ --+- -+--+ --+

I I I I I
Vee I I I I I

+ --+- -+ -- +- -+- -+-- +-- +

I I I I I I I
, , , --~~~

. .. LOGIC POWER GRID

+-- +- -+ --+ --+- -+--+ --+
I I I I I • I I
I I I I I I , I

+ --+- -+--+-- +--+-- +--+

GND

1105 24

Figure 31. LCA Power Distribution.

2-27
XC3000 Logic Cell Array Family

500 , 100
90
IL 80
70
/ 60
/ / 50
40
/
150 30
/

/ /
100 20
/
V V
V
50
/
/
/
/
L
V 10

40 1/ L 8
7
30
/ / 6
(mW) / / / 5 (mA)
20
/
L 4
/ / 3

L
/

50 CLB OUTPUTS10
/ /
.L
V 2
/
(18 mW/MHz)
,v V V
5
/
/
/
V
L
/ 1
.9
4 1/ V .8
20 CLB OUTPUTS / /
(7.2 mW/MHz) .7
3 /" L .6
/ / .5
2
/ V .4
/ V .3

/ /
V
3020 GLOBAL CLOCK BUFFER 1 .2
OR
ONE OUTPUT WITH 50 pF LOAD
/ V
/
(1.8 mW/MHz)

o. 5 .1
0.5 1/ 2 3 4 5 10 20 30 40 50

FREQUENCY MHz
ONE CLB OR lOB OUTPUT /
DRIVING THREE LOCAL
INTERCONNECTS
(0.36 mW/MHz)
1105 09

Figure 32. LeA Power Consumption by Element. Total chip power is the sum of Vee-leeo plus effective internal and external
values of frequency dependent capacitive charging currents and duty factor dependent resistive loads.

2-28
 Comp.onent Selection,
Ordering Information,
E:XllINX Electrical Parameters &
Physical Dimensions

XC2064

XC2018

XC3020

XC3030

XC3042

XC3090

1972 01

XC1736-PD8C plastic 8 Pin, Mini-DIP -40'C to 85'C COMPATIBLE PACKAGE OPTIONS

XC1736-CD8M Ceramic 8 Pin, Mini-DIP -55'C to 125'C
"
LCA Temperature Options
A range of Xilinx LCA (levices is available in iejentiCal
packages with identical pin-outs. A desi~n can thus be
Symbol Description Temperature started with one device, then migrated to a larger or
C Commercial O'Cto 70'C smaller chip while retaining the original footprint and
I Industrial -40'C to 85'C PC-board layout. .
M Military to
-55'C 125'C Examples: PLCC .68:. 2064-20H3-3020-3030
B Military MIL~STD-883, Class B PLCC 84: 2018.,3020-3030-3042
PGA 84: 2018~3()20-3030-3042
PQFP 100:. 3020-3030-3042
CQFP100: 3020-3030-3042
ORDERING INFORMATION PGA 132: 3042-3064
Note, however, that the XC2000 and XC3\lOO .families
Ex~mple: . .~Q2.]0.
DeVice Type .
iL..
L Temperature
Range
differ in the position ofXTl1 as well as th(~e garallel
address bits (6; 7 ancl11) and most of the da~.pi(ls u$id
in parallel master mode. ' '.
T~ggle Number of Pins XC2018 and XC3020 are not ,available in P~esl since
Rate
the PGA84 is the same size and offers Ill9reIIO•.
'. ':~ '~';<:~\\ :"v" , , '
Package Type Note that a PlCC in a socket with PGMootP"'1IIf fi{lemtEt~
a printed circuit board pin-out dlffertnt from ~~gev:ice.

2-29
XC3000 Logic Cell Array Family

PIN DESCRIPTIONS DONE

The DONE output is configurable as open drain with or
1. Permanently Dedicated Pins. without an internal pull-up resistor. At the completion of
configuration, the circuitry of the LCA becomes active in a
Vee synchronous order, and DONE may be programmed to
Two to eight (depending on package type) connections to occur one cycle before or after that.
the nominal +5 V supply voltage. All must be connected.
PROG
GND Once configuration is done, a HIGH to LOW transition of
Two to eight (depending on package type) connections to this pin will cause an initialization of the LCA and start a
ground. All must be connected. reconfiguration.

PWRDWN MO
A LOW on this CMOS compatible input stops all internal As Mode 0, this input and M1, M2 are sampled before the
activity to minimize Vcc power, and puts all output buffers startot configuration to establish the configuration mode to
in a high impedance state, but configuration is retained. be used.
When the PWRDWN pin returns HIGH, the device returns
to operation with the same sequence of buffer enable and RTRIG
DONE/PROGRAM as at the completion of configuration. As a Read Trigger, a LOW-to-HIGH input transition, after
All internal storage elements are reset. If not used, configuration is complete, will initiate a Readback of con-
PWRDWN must be tied to Vcc. figuration and storage element data by CCLK. This opera-
tion may be limited to a single request, or be inhibited al-
RESET together, by selecting the appropriate readback option
This is an active low input which has three functons. when generating the bit stream.

Priortothe start of configuration, a LOW input will delay the M1

start of the configuration process. An internal circuit As Mode 1, this input and MO, M2 are sampled before the
senses the application of power and begins a minimal start of configuration to establish the configuration mode to
time-out cycle. When the time-out and RESET are com- be used. If Readback is to be used, a 5 KQ resistor should
plete, the levels of the "M" lines are sampled and configu- be used to define mode level inputs.
ration begins.
RDATA
If RESET is asserted during a configuration, the LCA is re- As an active low Read Data, after configuration is com-
initialized and will restart the configuration at the termina- plete, this pin is the output of the readback datil.
tion of RESET.

If RESET is asserted after configuration is complete it will

provide an asynchronous reset of all lOB and CLB storage
elements of the LCA.

CCLK
During configuration, Configuration Clock is an output of
an LCA in Master mode or Peripheral mode. LCAs in Slave
mode use it as a clock input. During a Readback operation
it is a clock input for the configuration data being shifted
out.

2-30
2. User 1/0 Pins that can have special functions. RClK
During Master parallel mode configuration RCLK repre-
M2 sents a "read" of an external dynamic memory device
As Mode 2 this input has a passive pullup during configu- (normally not used).
ration. Together with MO and M1 it is sampled before the
start of configuration to establish the configuration mode to ROYIBUSY
be used. After configuration this pin becomes a user pro- During Peripheral parallel mode configuration this pin
grammable 1/0 pin. indicates when the chip is ready for another byte of data to
be written to it. After configuration is complete, this pin be-
HOC comes a user programmed lID pin.
High During Configuration is held at a HIGH level by the
LCA until after configuration. It is available as a control 00-07
output indicating that configuration is not yet completed. This set of 8 pins represent the parallel configuration byte
After configuration this pin is a user lID pin. for the parallel Master and Peripheral modes. After con-
figuration is complete they are user programmed lID pin.
lOC

•
Low During Configuration is held at a lOW level by the AO-A15
LCA until after configuration. It is available as a control This set of 16 pins present an address output for a
output indicating that configuration is not yet completed. It configuration EPROM during Master parallel mode. After
is particularly useful in Master mode as a LOW enable for configuration is complete they are user programmed lID
an EPROM. After configuration this pin is a user lID pin. pin.
If used as a LOW EPROM enable, it must be programmed
as a HIGH after configuration. DIN
This user lID pin is used as serial Data input during Slave
INIT or Master Serial configuration. This pin is Data 0 input in
This is an active low open drain output which is held LOW Master or Peripheral configuration mode.
during the power stabilization and internal clearing of the
configuration memory. It can be used to indicate status to OOUT
a configu ring microprocessor or, as a wired AN D of several This user lID pin is used during configuration to output
slave mode devices, a hold-off signal for a master mode serial configuration data for daisy-chained slaves' Data In.
device. After configuration this pin becomes a user pro-
grammable lID pin. TClKIN
This is a direct CMOS level input to the global clock buffer.
BClKIN
This is a direct CMOS level input to the alternate clock
buffer (Auxiliary Buffer) in the lower right corner.

XTl1 3. Unrestricted User 1/0 Pins.

This user I/O pin can be used to operate as the output of
an amplifier driving an external crystal and bias circuitry. 1/0
A pin which may be programmed by the user to be Input
XTl2 and/or Output pin following configuration. Some of these
This user lID pin can be used as the input of an amplifier pins present a high impedance pull-up (see next page) or
connected to an external crystal and bias circuitry. The perform other functions before configuration is complete
lID Block is left unconfigured. The oscillator configuration (see above).
is activated by routing a net from the oscillator buffer
symbol output and by the MAKEBITS program.

CSD, CS1, CS2, WS

These four inputs represent a set of Signals, three active
low and one active high, which are used in the Peripheral
mode to control configuration data entry. The assertion of
all 4 generates a write to the internal d(ita buffer. The re-
moval of any assertion, clocks in the DO':';D7 data present.

2-31
XC3()OO Logic Cell Array Family

XC3000 Family Configuration Pin Assignments

USER
100 100 132 164 175 OPERATION
PGA PGA

I::'
I/O
I/O
II

I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O
I/O
I/O

I/O
I/O
I/O
I/O
I/O
I/O

_ REPRESENTS A 50KO TO 100KO PULL-UP

• INIT IS AN OPEN DRAIN OUTPUT DURING CONFIGURATION
(I) REPRESENTS AN INPUT
AVAILABLE PACKAGES

1105 25

Note: Pin assignments of "PGA Footprint" PLCC sockets and PGA packages are not electrically identical.
Generic I/O pins are not shown_

2-32
 XC3000 Family 68-Pln PLCC, 84-Pln PLCC and PGA Pinouts

XC-3020' XC-3020'
68PLCC XC-3030, XC-3042 84 PLCC 84PGA 68 PLCC XC-3030, XC-3042 84 PLCC 84PGA
10 l'WRON 12 B2 44 I'!ESET 54 K10
11 lCLKIN-IiO 13 C2 45 DONE-PG" 55 J10
n.c. 110' 14 B1 46 D7-1/0 56 K11
12 1/0 15 C1 47 XTl1 (OUll-BClKIN-I/O 57 J11
13 va 16 D2 48 D6-1I0 58 H10
- va 17 D1 - 1/0 59 H11
14 1/0 18 E3 49 D5-I/O 60 F10
15 va 19 E2 50 C"SO-I/O 61 G10
16 1/0 20 E1 51 D4-1/0 62 G11
17 va 21 F2 - VO 63 G9
18 Vee 22 F3 52 Vee 64 F9
19 va 23 G3 53 D3-IIO 65 F11
- va 24 G1 54 CST-IIO 66 E11

•
20 1/0 25 G2 55 D2-VO 67 E10
21 va 26 F1 - 1/0 68 E9
22 1/0 27 H1 n.c. 1/0' 69 D11
- 1/0 28 H2 56 D1-VO 70 D10
23 va 29 J1 57 RDY/BUSV-"RcrK-I/O 71 C11
24 va 30 K1 58 DO-DIN-I/O 72 B11
25 M1-lmATA 31 J2 59 DOUl-I/O 73 C10
26 MO-l1TRlG" 32 l1 60 CClK 74 A11
27 M2-1I0 33 K2 61 AO-WS-IIO 75 B10
28 HOC-Va 34 K3 62 A1-CS2-1/0 76 B9
29 110 35 L2 63 A2-1/0 77 A10
30 EOC-VO 36 L3 64 A3-1/0 78 A9
31 1/0 37 K4 n.c. 110' 79 B8
n.c. va· 38 L4 n.c. 1/0' BO AB
32 1/0 39 J5 65 A15-1/0 81 B6
33 110 40 K5 66 M-I/O 82 B7
n.c, 1/0' 41 l5 67 A14-1/0 83 A7
34 TfllT-I/O 42 K6 68 A5-1/0 84 C7
35 GND 43 J6 1 GND 1 C6
36 1/0 44 J7 2 A13-1/0 2 A6
37 1/0 45 l7 3 AS-I/O 3 AS
36 1/0 46 K7 4 A12-1/0 4 B5
39 1/0 47 l6 5 A7-1/0 5 C5
40 1/0 48 l8 n.c. 1/0' 6 M
41 110 49 K8 n.c. 1/0' 7 B4
n.c. 110' 50 19 6 A11-1/0 8 A3
n.c. 1/0' 51 L10 7 AB-IIO 9 A2
42 1/0 52 K9 8 A10-1I0 10 B3
43 XTl2(INl-1/0 53 l11 9 A9-1/0 11 A1

Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-limited .

• Indicates unconnected package pins for the XC3020.

2-33
XC3000 Logic Cell Array Family

XC3000 Family 100·Pin QFP Pinouts

PIN No. XC3020 PIN No. XC3020 PIN No. XC3020

XC3030 PQFP XC3030 CQFP PQFP XC3030
CQFP PQFP CQFP
XC3042 XC3042 XC3042
1 16 GNO 35 50 I/O' 69 84 I/O'
2 17 A13-VO 36 51 I/O' 70 85 I/O'
3 18 A6-VO 37 52 M1-RO 71 86 I/O
4 19 A12-1/0 3B 53 GNO' 72 87 OS-I/O
5 20 A7-1/0 39 54 Ma-RT 73 88 CSO-I/O
6 21 I/O' 40 55 Vee" 74 89 04-VO
7 22 I/O' 41 56 M2-1/0 75 90 I/O
8 23 A11-1/0 42 57 HOC-I/O 76 91 Vee
9 24 A8-1/0 43 58 I/O 77 92 03-1/0
10 25 A10-1/0 44 59 LOC-I/O 78 93 ~-I/O
11 26 A9-1/0 45 60 I/O' 79 94 02-1/0
12 27 Vee· 46 61 I/O 80 95 I/O
13 28 GNO' 47 62 VO 81 96 I/O'
14 29 l'Wlml'l" 48 63 VO 82 97 110'
15 30 I/O 49 64 VO 83 98 01-1/0
16 31 I/O" 50 65 lliIlT-I/O 84 99 "RcrR"-lIDSY/RDY -I/O
17 32 I/O' 51 66 GNO 85 100 DO-DIN-I/O
18 33 I/O' 52 67 I/O 86 1 DOUT-I/O
19 34 I/O 53 68 VO 87 2 CCLK
20 35 I/O 54 69 I/O 88 3 Vee"
21 36 I/O 55 70 I/O 89 4 GNO'
22 37 I/O 56 71 I/O 90 5 AO-WS-I/O
23 38 I/O 57 72 I/O 91 6 A1-CS2-1/0
24 39 I/O 58 73 VO 92 7 I/O'
25 40 I/O 59 74 I/O' 93 8 A2-1/0
26 41 Vee 60 75 I/O' 94 9 A3-1/0
27 42 I/O 61 76 XTAL2-1/0 95 10 I/O'
28 43 I/O 62 77 GNO' 96 11 I/O'
29 44 I/O 63 78 "RESET 97 12 A15-1/0
30 45 VO 64 79 Vee" 98 13 M-I/O
31 46 I/O 65 80 OONE-l'IT 99 14 A14-1/0
32 47 I/O 66 81 07-1/0 100 15 AS-I/O
33 48 I/O 67 82 XTALH/O
34 49 I/O 68 83 06-1/0

Unprogrammed lOBs have a default pull-up.

This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew limited.
, Indicates unconnected package pins for the XC3020 .
• , Indicates unconnected package pins for the XC3020 and the XC3030.

2-34
 ~XIUNX

Table 2d. XC3000 Family 132 Pin PGA Pinouts

PGAPin XC·3042 PGAPln XC-3042 PGAPin XC·3042 PGAPln XC·3042

Number XC·3064 Number XC-3064 Number XC·3064 Number XC·3064

C4 GND 813 Ml·m:; P14 m:sE'f M3 OOUT-I/O

Al J5WI.'IDN Cll GND Mll vee P1 CCLK
C3 1/0 A14 MO-RT N13 OONE-PG M4 vee
82 1/0 012 vee M12 07-1/0 L3 GNO
83 1/0 C13 M2-1/0 P13 XTAL1-1/0 M2 AO-WS-I/O
A2 1/0* 814 HOC-IIO N12 1i0 N1 A1-CS2-1/0
84 1/0 C14 1/0 P12 1i0 M1 110
C5 110 E12 1i0 Nll 06-1i0 K3 1/0
A3 1/0* 013 1/0 Ml0 1i0 L2 A2-1/0
M 1/0 014 IDC"-I/O Pll 1/0* L1 AS-I/O
85 1/0 E13 1/0* Nl0 1/0 K2 1/0
C6 1/0 F12 1/0 Pl0 1/0 J3 1/0
AS 1i0 E14 1/0 M9 05-1/0 Kl A15-1/0

•
86 1i0 F13 1/0 N9 C"Sli-1/0 J2 M-IIO
AS 1/0 F14 1/0 P9 1/0* Jl 1/0*
87 110 G13 1/0 P8 1/0* Hl A14-1/0
C7 GND G14 lNIT-11O N8 04-110 H2 AS-IIO
C8 vee G12 vee P7 1i0 H3 GND
A7 1/0 H12 GNO M8 vee G3 vee
88 1/0 H14 1/0 M7 GNO G2 A13-1I0
AS 1/0 H13 1i0 N7 03-1/0 Gl AS-IiO
A9 1i0 J14 1/0 P6 ~-I/O Fl 1/0*
89 1i0 J13 1/0 N6 1/0* F2 A12-1I0
C9 1i0 K14 1i0 P5 1/0* El A7-1/0
Al0 1/0 J12 1/0 M6 02,1/0 F3 1i0
810 1/0 K13 1i0 N5 1/0 E2 1/0
All 1/0* L14 1/0* P4 1/0 01 All·I/O
Cl0 110 L13 1/0 P3 1i0 02 AS-I/O
811 1/0 K12 1/0 M5 01-1/0 E3 1/0
A12 1/0* M14 110 N4 RCLK-BUSYIROY-I/O Cl 1/0
812 1/0 N14 1i0 P2 1i0 81 Al0-1i0
A13 1/0* M13 XTAL2-1/0 N3 1i0 C2 A9-1/0
C12 ItO L12 GNO N2 OO-OIN-I/O 03 vee

Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-limited .

• Indicates unconnected package pins for the XC3042.

2-35
XC3000 Logic Cell Array Family

XC3000 Family 164-Pin CQFP Pinouts

CQFPPin XC-3064 CQFPPin XC-3064 CQFPPin XC-3064 CQFPPin XC-3064

Number XC-3090 Number XC-3090 Number XC-3090 Number XC-3090
20 l'WROO 61 vo· 103 DONE-PG" 143 DO-DIN-IIO
21 TCLKIN-IIO 62 M1-~ 104 07-110 144 DOUT-I/O
22 1/0' 63 GND 105 XTAl1(OUT)- 145 CClK
64 MO-RTRIG BClKIN-VO
23 1/0' 146 Vee
24 VO 65 Vee 106 1/0' 147 GND
66 M2-1/0 107 I/O 148 AO-WS-I/O
25 1/0'
26 110 67 HDC-VO 108 I/O 149 A1-CS2-110
27 110' 68 110 109 D6-VO 150 110
110 110
28 VO 69 1/0 151 110
29 110 70 I/O 111 I/O 152 A2-1/0
30 I/O 71 JJ::jC"-1/0 112 VO 153 A3-1/0
31 I/O 72 1/0'
113 VO 154 110
32 I/O 73 VO 114 1/0 155 110
33 I/O 115 D5-VO 156 A15-1I0
74 1/0'
34 110 75 I/O 116 C"SO-VO 157 M-IIO
35 110 76 I/O 117 1/0' 158 110
36 VO 77 I/O 118 VO 159 110
37 VO 78 VO 119 1/0' 160 A14-110
38 110 79 110 120 I/O 161 A5-110
39 I/O 80 VO 121 D4-1/0 162 1/0'
40 I/O 81 W-IIO 122 110
163 110'
41 GND Vee 123 Vee 164 GND
82
42 Vee 83 GND 124 GND 1 Vee
43 VO 84 110 125 D3-VO 2 A13-1/0
44 VO 85 1/0 126 CST-IIO 3 A6-1/0
45 110 86 VO 127 I/O 4 1/0
46 110 87 110 128 110' 5 1/0'
47 110 88 I/O 129 110 6 110
48 110 89 VO 130 1/0' 7 1/0'
49 I/O 90 VO 131 D2-110 8 A12-110
50 I/O 91 I/O 132 110 9 A7-1I0
51 110 92 I/O 133 110 10 110
52 VO 93 110 134 110 11 110
53 VO 94 110 135 110 12 A1HO
54 I/O 95 1/0 136 110 13 AS-IIO
137 D1-110 VO
55 VO 96 1/0' 14
56 110 97 VO 138 RDYi£lUSY- 15 110
l'lcrK-110
57 1/0' 98 110' 16 A10-1/0
139 I/O
58 VO 99 XTAl2(IN)-1I0 17 A9-1/0
140 110'
59 1/0' 100 GND 18 Vee
141 I/O
60 I/O 101 "RESET 19 GND
142 110'
102 Vee

Unprogrammed lOBs have a default pull-up_

This Prevents an undefined pad level for unbonded or unused 10Bs_
Programmed outputs are default slew-limited_
• Indicates unconnected package pins for the XC-3064_

2-36
 E:XIUNX

XC3000 Family 175-Pin PGA Pinouts

PGA Pin PGA Pin PGA Pin PGA Pin

Number XC-3090 Number XC-3090 Number XC-3090 Number XC-3090
B2 I'WflOO D13 110 R14 DONE-I'l! R3 DO-DIN-IIO
D4 TClKIN-I/O B14 Ml-1mATl\" N13 07-1/0 N4 DOUT-VO
B3 VO C14 GND T14 XTAll (OUT)-BClKIN-VO R2 CClK
C4 VO B15 MO-RTRIG P13 110 P3 vee
B4 110 D14 vee R13 110 N3 GND
M VO C15 M2-VO T13 110 P2 AO-WS-I/O
D5 110 E14 HDC-I/O N12 VO M3 Al:CS2-1/0
C5 110 B16 110 P12 D6-1/0 Rl 110
B5 VO D15 110 R12 VO N2 110
AS 110 Cll; 110 T12 VO Pl A2-1/0
..
C6 110 D16 IDC"-vO Pll VO Nl A3-110
D6 vq F14 VO Nll 110 l3 110
B6 110 E15 110 Rll VO M2 110
A6 110 E16 110 Ml A15-110

•
Tll D5-1/0
B7 VO F15 VO Rl0 CSO-I/O l2 M-IIO
C7 110 F16 110 Pl0 110 L1 VO
D7 110 G14 110 Nl0 110 K3 VO
A7 VO G15 VO T10 110 K2 A14-VO
AS 110 G16 110 T9 110 Kl AS-VO
88 110 H16 110 R9 D4-110 Jl VO
C8 110 H15 1IiIlT-VO P9 110 J2 VO
D8 GND H14 vee N9 vee J3 GND
D9 vee J14 GND N8 GND H3 vee
C9 VO J15 VO P8 D3-IIO H2 A13-VO
B9 110 J16 110 RB CS"f-IiO Hl A6-110
A9 110 K16 110 T8 110 Gl 110
Al0 110 K15 110 T7 110 G2 110
Dl0 110 K14 110 N7 110 G3 110
Cl0 110 l16 110 P7 110 Fl 110
Bl0 110 l15 110 R7 D2-1/0 F2 A12-1/0
All 110 M16 110 T6 110 El A7-110
Bll 110 M15 110 R6 110 E2 110
Dl1 110 L14 110 N6 110 F3 110
Cll 110 N16 110 P6 110 Dl A11-IIO
A12 110 P16 110 T5 110 Cl AS-liD
B12 110 N15 110 R5 Dl-IIO D2 110
C12 110 R16 110 P5 RDYilmS'i'-~-lIo Bl 110
D12 110 M14 110 N5 110 E3 A10-1I0
A13 110 P15 XTAl2(IN)-110 T4 110 C2 A9-110
B13 110 N14 GND R4 VO D3 vee
C13 110 R15 m:sET P4 110 C3 GND
A14 110 P14 vee
Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-limited.

Pins A2, A3, A15, A16, T1, T2, T3, T15 and T16 are not connected.
Pin A 1 does not exist.

2-37
XC3000 Logic Cell. Array Family

PARAMETRICS

Absolute Maximum Ratings Units

Vee Supply voltage relative to GND -0.5 to 7.0 V

VIN Input voltage with respect to GND -0.5 to Vee + 0.5 V

VTS Voltage applied to three-state output -0.5 to Vee + 0.5 V

TSTG Storage temperature (aml:?ient) -65 to + 150 °C

TSOL Maximum soldering temperature (10 sec @ 1/16 in.) + 260 °C

Junction temperature plastic + 125 °C

TJ
Junction temperature ceramic + 150 °C

"Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings
conditions for extended periods of time may affect device reliability.

Recommended Operating Conditions Min Max Units

Vee Supply voltage relative to GND Commercial O°C to 70°C 4.75 5.25 V

Supply voltage relative to GND Industrial -40°C to 85°C 4.5 5.5 V

Supply voltage relative to GND Military -55°C to 125°C 4.5 5.5 V

VIHT High-level input voltage - TIL configuration 2.0 Vee V

VILT Low-level input voltage - TIL configuration 0 0.8 V

VIHe High-level input voltage - CMOS configuration 70% 100% Vee

ViLe Low-level input voltage - CMOS configuration 0 20% Vee

TIN Input signal transition time 250 ns

2-38
 Electrical Characteristics Over Operating Conditions Min Max Units

VOH High-level output voltage (@ IOH = -4.0 rnA, Vee min) Commercial 3.86 V

VOL Low-level output voltage (@ IOl = 4.0 rnA, Vee min) 0.32 V

VOH High-level output voltage (@ IOH = -4.0 rnA, Vec min) Industrial 3.76 V

VOL Low-level output voHage (@ IOl = 4.0 rnA, Vee min) 0.37 V

•
VOH High-level output voltage (@loH = -4.0 rnA, Vee min) Military 3.7 V

VOL Low-level output voltage (@ IOl = 4.0 rnA, Vee min) 0.4 V

leePD Power-down supply current (Vee = 5.0 V @ 70°C) XC3020 500 ~

XC3030 800 ~

XC3042 1150 ~

XC3064 1650 ~
,
XC3090 2500 ~

leeo Quiescent LCA supply current in addition to leePD 1

Chip thresholds programmed as CMOS levels 500 ~

Chip thresholds programmed as TTL levels 10 rnA

ill Leakage Current Commercial/Industrial Temperature -10 +10 ~

Leakage Current Military -55°C to 125°C -20 +20 ~

CIN Input capacitance, all packages except PGA 175

(sample tested)
All Pins except XTL 1 and XTL2 10 pF
XTL 1 and XTL2 15 pF

Input capacitance, PGA 175

(sample tested)
All Pins except XTL 1 and XTL2 15 pF
,
XTL 1 and XTL2 20 pF

IRIN Pad pull-up (when selected) @ VIN = OV (sample tested) 0.02 0.17 rnA

IRll Horizontal long line pull-up (when selected) @ logic LOW 0.4 3.4 rnA

Note: 1. With no output current loads, no active input or long line pull-up resistors, all
package pins at Vee or GND, and the LCA configured with a MAKEBITS '1ie"
option. See LCA power chart for additional activity dependent operating component.

2-39
XC3000 Logic Cell Array Family

CLB SWITCHING CHARACTERISTIC GUIDELINES

CLB OUTPUT (X,V)

(COMBINATORIAL)

CLB INPUT (A,B,C,D,E)

CLBCLOCK
~---@TCL--~

o TDICK -----+--
CLB INPUT
(DIRECT IN)

CLB INPUT
(ENABLE CLOCK)

CLBOUTPUT
(FLIP-FLOP)

CLB INPUT
(RESET DIRECT)

CLBOUTPUT
(FLIP-FLOP)
1105 26

BUFFER (Internal) SWITCHING CHARACTERISTIC GUIDELINES

Speed Grade -50 -70 -100 Units

Description Symbol Min Max Min Max Min Max

Global and Alternate Clock Distribution""

Either: Normal lOB input pad to clock buffer input TPID 9 6 4 ns
Or: Fast (CMOS only) input pad to clock buffer input TPIDC 5 3 2 ns
Plus: Clock buffer input to any clock k 9 6 5 ns

TBUF driving a Horizontal Longline (L.L.)"

I to L.L. while T is Low (buffer active) TID 8 5 4 ns
T,J,. to L.L. active and valid TON 15 9 7 ns
Ti to L.L. (inactive) with single pull-up resistor Tpus 34 22 14 ns
with pair of pull-up resistors TpUF 17 11 7 ns

BIOI
Bi-directional buffer delay 6 4 3 ns

•• Timing is based on the XC3020, for other devices see XACT timing calculator.

2-40
CLB SWITCHING CHARACTERISTIC GUIDELINES (Continued)
Testing of the switching characteristic guidelines is modeled after testing specified by MIL-M-3851 0/605. Devices are 100%
functionally tested. Benchmark timing patterns are used to provide correlation to the switching characteristic guideline values.
Actual worst-case timing is provided by the XACT Timing calculator or Simulation modeling.

Speed Grade -50 -70 -100 Units

Description Symbol Min Max Min Max Min Max

Combinatorial Delay
Logic Variables a, b, c, d, e, to outputs x, y 1 TllO 14 9 7 ns

Sequential delay
Clock k to outputs x, y 8 TCKO 12 8 7 ns

•
Clock k to outputs x,y when Q is returned
through function generators F or G to drive x, y 23 15 12 ns

Set-up time before clock K

Logic Variables a,b,c,d,e 2 TICK 12 8 7 ns
Data In di 4 TDICK 8 5 4 ns
Enable Clock ec 6 TECCK 10 7 5 ns
Reset Direct inactive rd 2 1 1 ns

Hold Time after clock k

Logic Variables a,b,c,d,e 3 TCKI 0 0 0 ns
Data In di 5 TCKDI 6 4 2 ns
Enable Clock ec 7 TCKEc 0 0 0 ns

Clock
Clock High time' 11 TCH 9 7 5 ns
Clock Low time' 12 TCl 9 7 5 ns
Max. flip-flop toggle rate' FClK 50 70 100 MHz

Reset Direct (rd)

rd width 13 TRpw 12 8 7 ns
delay from rd to outputs x, y 9 TRIO 12 8 7 ns

Master Reset (MR)

MRwidth TMRw 38 25 21 ns
delay from MR to outputs x, y TMRQ 30 20 17 ns

• These timing limits are based on calculations.

Note: The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than
the Data In hold time requirement (TCKDI, #5) of any CLB on the same die.

2-41
XC3000 Logic Cell Array Family

lOB SWITCHING CHARACTERISTIC GUIDELINES

==®~"Dt-·=0_t-=--=--_-]-~~=
110 BLOCK (I)

110 PAD INPUT

.'. 1 TplCK ® TIKPI

~
110 CLOCK
(IKlOK)

@ TIOl @TloHJ-

4-0TIKR~ J@
110 BLOCK (RI)

RESET

~® TOOK @TOKO .... @TRPOI+-

110 BLOCK (0)

@TOp _

110 PAD OUTPUT

(DIRECT) f r,=..0
110 PAD OUTPUT
(REGISTERED)
-- )K
TOKPO

VOPADTS

va PAD OUTPUT
J
1105 27

PROGRAM·CONTROLLED MEMORY CELLS Vo<

THREE STATE ~~f.:~.t'--I-____=;IL)------t-~

(OUTPUT ENABLE)

OUT J.~!--,,_ /
I~
DIRECT IN ~.". '----f--------.
~1~·q'----t---I

_.._. _
. ._
. ._"f:-
REGISTERED IN

- "i~'
j}
CCNTROlLED
MULTIPLEXER 0"' PROGRAMMABLE INTERCONNECTION POINT'or PIP

2-42
lOB SWITCHING CHARACTERISTIC GUIDELINES (Continued)
Testing of the switching characteristic guidelines is modeled after testing specified by MIL-M-3851 0/605. Devices are 100%
functionally tested. Benchmark timing patterns are used to provide correlation to the switching charC1eristic guideline values.
Actual worst-case timing is provided by the XACT Timing calculator or Simulation modeling.

-50 -70 -100 Units

Description Symbol Min Max Min Max Min Max

Propagation Delays (Input)

Pad to Direct In (i) 3 TPID 9 6 4 ns
Pad to Registered In (q) with latch transparent TpTG 34 21 17 ns
Clock (ik) to Registered In (q) 4 TIKRI 11 7 6 ns

Set-up Time (Input)

Pad to Clock (ik) set-up time 1 TPICK 30 20 17 ns

Propagation Delays (Output)

Clock (ok) to Pad (fast) 7 TOKPO 18 13 10 ns
same (slew rate limited) 7 TOKPo 43 33 27 ns
Output (0) to Pad (fast) 10 TOPF 15 9 6 ns
same (slew-rate limited) 10 Tops 40 29 23 ns
Three-state to Pad begin hi-Z (fast) 9 TTsHz 12 8 8 ns
same (slew-rate limited) 9 TTsHz 37 28 25 ns
Three state to Pad active and valid (fast) 8 TTsoN 20 14 12 ns
same (slew -rate limited) 8 TTsoN 45 34 29 ns

Set-up and Hold Times (Output)

Output (0) to clock (ok) set-up time 5 TOOK 15 10 9 ns
Output (0) to clock (ok) hold time 6 TOKO 0 0 0 ns

Clock
Clock High time 11 TCH 9 7 5 ns
Clock Low time 12 TCl 9 7 5 ns
Max. flip-flop toggle rate FCLK 50 70 100 MHz

Master Reset Delays

RESET Pad to Registered In (q) 13 TRRI 35 23 20 ns
RESET Pad to output pad 15 TRPO 50 33 28 ns

Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture).
Typical fast mode output riselfall times are 2 ns and will increase approximately 2%/pF of additional load.
Typical slew rate limited output rise/fall times are approximately 4 times longer.
A maximum total external capacitive load for simUltaneous fast mode switching in the same direction
is 500 pF per power/ground pin pair. For Slew-rate limited outputs this total is 4 times larger.

2. Voltage levels of unused (bonded and Unbonded) pads must be valid logic levels. Each can be configured
with the internal pull-up resistor or alternatively configured .as a driven output or driven from an external source.

3. Input pad set-up time is specified with respect to the internal clock (.ik)
In order to calculate system set-up time, subtract clock delay (pad to ik) from the input pad set-up time value.
Input pad holdtime with respect to the internal clock (ik) is negative. This means that pad level changes immediately
before the internal clock edge (ik) will not be recognized.
For a more detailed description see the discussion on "LeA Performance" in the Applications chapter
(6-14 to 18).

2-43
XC3000 Logic Cell Array Family

GENERAL LCA SWITCHING CHARACTERISTICS

r - - - - - - - i l t....
' __ (0™RW)________

MO/M1/M2
----,f®'~®'~f--------
~®TPGW=-1
DONEtPROG

___J
__-
----,[®TPGI
INIT
(OUTPUT) USER STATE ______C_L_EA~RI_S-T-AT-E--------J/ CONFIGURATION STATE
-- II .

\~~-~/
r-NOTE3-j
------------------------------~\ (~~t-----
Vee (VAUDj
•\. ____ iJ~
VCCPD

1105 28

-50 -70 -100 Units

Description Symbol Min Max Min Max Min Max

RESET (2) MO, M1, M2 setup time required 2 TMR 1 0 1 0 0 0 115

MO, M1, M2 hold time required 3 TRM 1 1 115
RESET Width (Low) req. for Abort 4 TMRW 6 6 115

DONEJPROG Width (Low) required for Re-config. 5 TpGW 6 6 6 115

INIT response after Dip is pulled Low 6 TpGI 7 7 7 115
PWRDWN (3) Power Down Vcc VCCPD 2.0 2.0 2.0 V

Notes: 1. Vee must rise from 2.0 Volts to Vee minimum in less than 10 ms for master modes.
2. RESET timing relative to valid mode lines (MO, M1, M2) is relevant
when ~ is used to delay configuration.
3. PWRDWN transitions must occur during operational Vcc levels.

2-44
 MASTER SERIAL MODE SWITCHING CHARACTERISTICS GUIDELINES

CClK
(OUTPUT)

SERIAL DATA IN

1105 29 SERIAL DOUT

(OUTPUT) _ _ _ _ _---J ' - - _ _ _ _ _---J ' - -_ _ _ _ _- ' '-_ _ _ _ _ _ __

•
Speed Grade -50 -70 Units

Description Symbol Min Max Min Max Min Max

CCLK3 Data In setup 1 TDSCK 60 60 ns

Data In hold 2 TCKDS 0 0 ns

Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min. in less than 10 ms,
otherwise delay configuration using RESET until Vcc is valid.
2. Configuration can be controlled by holding RESET low with or until after
the INIT of all daisy-chain slave mode devices is HIGH.
3. Master serial mode timing is based on slave mode testing.

2-45
XC3000 Logic Cell Array Family

MASTER PARALLEL MODE PROGRAMMING SWITCHING

CHARACTERISTIC GUIDELINES
Testing of the switching characteristic guidelines is modeled after testing specified by MIL-M-3851 0/605. Devices are 100%
functionally tested. Benchmark timing patterns are used to provide correlation to the switching charcteristic guideline values.
Actual worst-case timing is provided by the XACT Timing calculator or Simulation modeling.

AO-A15 ADDRESS for BYTE n ADDRESS for BYTE n + 1

(OUTPUl)

DO-D7

/ ~~====-::"-::"-:'~-7-C-C-L-KS-
RCLK
(OUTPUl)
_-_-_-_-_-_-J""""",,_--

CCLK
(OUTPUl)

DOUT D7
(OUTPUl)
BYTE n-1
110530

-50 -70 Units

Description Symbol Min Max Min Max Min Max

RCLK To address valid 1 TRAC 0 200 0 200 ns

To data setup 2 TDRC 60 60 ns
To data hold 3 TRCD 0 0 ns
RCLK high TRCH 600 600 ns
RCLK low TRCL 4.0 4.0 Ils

Notes: 1. At power-up, Vcc must rise from 2.0 V to Vee min. in less than 10 ms,
otherwise delay configuration using RESET until Vee is valid.
2. Configuration can be contorlled by holding RESET low with or until
after the TNlT of all daisy-chain slave mode devices is HIGH.

This timing diagram shows that the EPROM requirements are extremely relaxed:
EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements.

2-46
PERIPHERAL MODE PROGRAMMING SWITCHING CHARACTERISTICS

(
,,
CSlICSO \ I ,

,J
CS2
7 \ ,,

00-07

CCLI< ,,
\. ___ J
,, ,,
\. ___ J
,, II
ROY/BUSY _______________________ J :

1105 10
OOUT _---Jx'--_-.Jx'--_____ ---J \...----.JX'---__L
-50 -70 -100 Units

Description Symbol Min Max Min Max Min Max

Write WS Low time reqired 1 TCA 0.5 0.5 0.5 JlS

DIN setup time required 2 Toc 60 60 60 ns

DIN hold time required 3 Tco 0 0 0 ns

ROY/BUSY delay after end of WS 4 TWTRB 60 60 60 ns

ROY Earliest next WS after end of BUSY 5 TRBWT 0 0 0 ns

BUSY Low time generated 6 TBUSY 4 9 4 9 4 9 CCLK

Periods

Notes: 1. Configuration must be delayed until the mrr

of all LCAs is HIGH.
2. Time from end of WS to CCLK cycle for the new byte of data
depends on completion of previous byte processing and the phase
of the internal timing generator for CCLK.
3. CCLK and DOUT timing is tested in slave mode.

This timing diagram shows very relaxed requirements:

Data need not be held beyond the rising edge of WS. BUSY will go active within 60 ns after the end of WS. BUSY will stay
active for several microseconds. WS may be asserted immediately after the end of BUSY.

2-47
XC3000 Logic Cell Array Family

SLAVE MODE PROGRAMMING SWITCHING CHARACTERISTICS

:: =to ·=tl4:_@_2_l:_=2= - - -<'1*'~1_'·~ '=j~_TC_C_L r-

__ ___

(OUTPUT) BIT N-1 JK BIT N 110531

-50 -70 Units

Description Symbol Min Max Min Max Min Max

CCLK To DOUT 3 Tcco 100 100 ns

DIN setup 1 TDCC 60 60 ns
DIN hold 2 TCCD 0 0 ns
High time 4 TCCH 0.5 0.5 ns
Low time 5 TCCL 0.5 5.0 0.5 5.0 ~s
Frequency Fcc 1 1 MHz

Note: Configuration must be delayed until the INIT of all LCAs is HIGH.

PROGRAM READBACK SWITCHING CHARACTERISTICS

DONE/PROG
(OUTPUT) ____-L/___________________________________ _
~0 TRTH--1

RTRIG
7 t~ _ __
@ TRTCC~
Ir----~
CCLK(1)

CD TCCRD ~Ir-------------­
RDATA
(OUTPUT) _ _ _ _ _ _---J )K VALID 1105 32

-50 -70 Units

Description Symbol Min Max Min Max Min Max

RTRIG RTRIG high 1 TRTH 250 250 ns

CCLK RTRIG setup 2 TRTCC 10 10 ns

RDATAdelay 3 TCCRD 100 100 ns

Notes: 1. CCLK and DOUT timing are the same as for slave mode.
2. RETRIG (MO positive transition) shall not be done until after one clock following active 110 pins.
3. Readback should not be initiated until configuration is complete.

2-48
 E':XIUNX

L
PIN NO. 1 .045
PIN NO.1 IDENTIFIER
.045 x 45' " "
9
c
1/. 61

PWRDWN

.9 0 '.9 4 Va; Va;

±.OO5 ±.OO4

1 M1
MO

Ir~:2~7~~~~~~~~5'::'i:~;:;4i5':'i::;=;::~
DONE
RESET .028 *=I=:~*,
PIN SPACING
.050 lYPICAL

LEAD C()'PLANARllY ± 0.002 IN

ALL DIMENSIONS ARE

IN INCHES

•
9 JA = 35-40 'CIW
110534

58-Pin PLCC Package

.045 X 45'",,"
11
LL,
I
PIN NO. 1
PIN NO.1 IDENTIFIER

75
.045

PWRDWN CCLK
DOUT/IO

1. 190 1.1~ Va; Va;

±.005 ±.004 ~~ 1.120 ±.010

PIN SPACING
.050 TYPICAL

M1 DONE
Me RESET .028 ~=I==I:=*""7""--lL
- '--
~t-----..,-33-1.154±.004.~5341
uuuuuwu

14~-------1.190 ±.005--------~l.
DIMENSIONS ARE IN INCHES
1105 36
9 JA = 30-35 'C/W
84-Pin PLCC Package

2-49
XC3000 Logic Cell Array Family

1.000±.010
1.100:t.012
~ .100TYP
.100
r. Lh. TYP
"-
L f. Lll f.D. tL.I.f.ll
f/'V
1
1".
'+.1 ,./
H

G
r. 1:'1..
" 1.000
±.O10
" t-'
L ,
f. ll.L llf.D.
I-' t-' "
o , INDEX PIN 'TYP .070 DIAI.oS MAX
1:'1..1".
r.t\ :s. .L~f.D.

f7:'I

J... " " '-'

/'6- TA , ..£., , -'f.

f. f.
~
..c:;;;::,.
~
...Ii.

PINN0.liND X""'-
~ I 05• .018
i"-i.010 ±.002DIA
1 ,. 11
DIMENSIONS ARE IN INCHES
NOTE: INDEX PIN MAY OR MAY NOT BE
ELECTRICALLY CQNNECTED TO PIN C2.

110535

84·Pln PGA Package

0.009 +/- 0.005

PIN SPACING
i-----0.742REF.-----ot O.0258TYP

'~5_7'" '. --y .1.1.1;;

.1.1.1.1

~lIlnlllml1h::±:_~, n ~,
0.57 +/- 0.006
All. DIMENSIONS IN INCHES
0JA • 71l-8O" CtW (OSl)
110539

100·Pin PQFP Package

2·50
 ----------------------

E:XIUNX

LEAOFRAME
O.OO5THK

DEVfTREOUS

r
SOLDER GLASS

~[

0.145 MAX

0.0300 .0.0050
0.0500 10.0050
BOTTOM VIEW 0.120 MAX
(LID SIDE UP}
(DIE FAClfiG UP) SIDE VIEW

TYP

PIN SPACING
0.025 TYPICAL

NOTES:
4 1. LEADS.ARE SHIPPED UNFORMED IN CARRIERS IN TRAYS
2. FORMINce TOOL INFORMATION:
- FANCORT INDUSTRIES - (201) 575-0610 weST CALDWELL NJ.
-IlISIINOUSTllIES(619}425-a970CHULA VISTA, CA
ALL DIMENSIONS IN INCHES

TOP VIEW
8JA - 40'50" CJW (ost'
8JC - 5-41° CIW(oSt)
(DIE FACING OQWN)
110540

100-PiilCQFP Package

2-51
XC3000 Logic Cell Array Family

INDEX
MARK

DIMENSIONS ARE IN INCHES

___-+__ 8 JA =25-30·CIW
--+------ ---------+-------- 8.;c=5°CNV

,.085 i.OO9

PIN KOVAR

----i !+- .018 ±.OO2 DIA. 132 PlCS

.040 X 45°
4PLCS. 10 11 12 13 14

Q0000000,000000 0

00000000000000 TYP ..070DlA

±.cos

M00000000000000
000
000 000
000 000
000 +
000 .645 1.460
±.OtS
G800 000
i.OOS

000 000
000 000
000
000 000000
000 000000
000 000000
~-----:.~------~
.100TYP.

.070 i.Ot SQ.

~-------------I.300TYP. --------1
1----------1~g---------~

1105 38
132·Pin PGA Package

2·52
 LEADFRAME
0.005 THK

DEvrrREOUS
SOLDER GLASS

HYP .~[
PIN SPACING
0.025 TYPICAL L II
BOTTOM VIEW
(LID SIDE UP)
(DIE FACING UP)
0.145 MAxj 1111

0:0300 .0.0050 ~ t
SIDE VIEW
0.0500 .0.0050
0.120 MAX

0.011 TYP

PIN SPACING
0.025 TYPICAL

NOTES:
1. LEADS ARE SHIPPED UNFORMED IN CARRIERS IN TRAYS
2. FORMING TOOL INFORMATION:
_ FANCORT INDUSTRIES - (201) 575-0610 WEST CALDWELL NJ.
TOP VIEW _ RISIINDUSTRIES INC. (619) 425-3970 CHULA VISTA, CA
(DIE FACING DOWN)
ALL DIMENSIONS IN INCHES

9JA - 35-45' CIW (e.l)

9JC -3-5' CIW (e.t)
1105.41

164-Pin CQFP Package

2-53
XC3000 Logic Cell Array Family

o NOEl<

8JA_18 DC/rN
-I--ir------,+------tt--t- 8JC.O.5-1.0"CIW

WE10 METAUC HEATSIIIK .025 REF.

ElECTRICALLY CONNECTED TO VC,
J

PIN KOVAR
.OOSR. TYP.

1·000000000000000 ("#--------.-
~00000000G000000·
N0000000000000000 TYP ..070 OIA
U05

13 0000
n0000 0000
110000 0000
~0000 0000
£ 90 G?,-::::0:--::0~ _ _+,_ _~0~·~0~0~0-+-.845±'''' 1.660SO±.016

,0000 0000 1.500±·015

70000 0000
'0000 0000
-0000 0000
40000
30000 000000 DIELECTRIC COAT

20000 000000 STANO OFF PIN

10000 000000 4PL

T R P N L K
J "
G F
I. .69S±·OO7 .1
110537

175-Pin PGA Package

2-54
 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 o 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 o 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 I 0 0 0 0

-t-
0 0 0 0 O 0 0 0
0 0 0 0 o 0 0 0
0 o 0 0 0 0 0 0
0 0 0 0 0 0 0 0

•
0 0 0 0 0 0 0 0
0.071 ±.006
0 0 0 0 I 0 0 0 0
r-

0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r- 0.070 ±.O 08
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0.046
Rell

1
PIN T
~i~~~m fff1]]ffilT r 0.197

U
KOVAR
T

Di~~
0.018 ± .002 G. b O . 0 5 0 Dia
r
0.00 5 R
Typ 16
@) @) @) @) @) @) @) @) @)@)@)@)@)@)@)0)
@) @) @) @) @) @) @) @) @)@)@)@)@)@)@)@)
15
@) @) @) @) @) @) @) @) @)@)@)@)@)@)@)@)
14
13
@) @) @) @) @)@)@)@)
12
@) @) @) @) @)@)@)@)
11
@)@)@)@) I @)@)@)@) 1.660 ± .016

+-
10
@) @) @) @) @)@)@)@) Squa re

r.
9 @)@)@)@) @)@)@)@)
L

8 @)@)@@ @)@)@)@) 1.500 ±.012

@)@)@@ @) @ @) @)-
~Dielectric
7

6 @)@)@@ I @)@)@)@ Coat

~5 -€> @) @) @) @)@)@)@)
.100 Typ
r- 4 -@@)@@)
3 @)@)@@@)@)@)@)@)@)@)@)@)@)@)@)
@)@)@)@)

2@)@@)@)@)@)@@ @) @) @) @) @) @ ~@)
1ft@)@)@)@)@)@)@) @)@)@)@)@)@)@ ~

~ Stand Off Pin

T R P N M L K J H G F E D C B
A
- - 0.070 ± .005 Dla 4 Places
Typ
199101
175-Pin PPGA Package
 Component Selection &
Ordering Information

XC2064

XC2018

XC3020

XC3030

XC3042

XC3064

XC3090

197201

XC1736-PD8C Plastic 8 Pin, Mini-DIP -40°C to 85°C COMPATIBLE PACKAGE OPTIONS

XC1736-CD8M Ceramic 8 Pin, Mini-DIP -55°C to 125°C
A range of Xilinx LCA devices is available in identical
LCA Temperature Options packages with identical pin-outs. A design can thus be
Symbol Description Temperature started with one device, then migrated to a larger or
C Commercial O°Cto 70°C smaller chip while retaining the original footprint and
I Industrial -40°C to 85°C PC-board layout.
M Military -55°C to 125°C Examples: PLCC 68: 2064-2018-3020-3030
B Military MIL-STD-883, Class B PLCC84: 2018-3020-3030-3042
PGA84: 2018·3020-3030-3042
POFP 100: 3020·3030-3042
COFP100: 3020-3030-3042
ORDERING INFORMATION PGA 132: 3042-3064

-- IJ TTL
Example:

Toggle
XC2064-70PC68C

,_.M.
Range

Number of Pins
Note, however, that the XC2000 and XC3000 families
differ in the position of XTL 1 as well as three parallel
address bits (6, 7 and 11) and most of the data pins used
in parallel master mode.
XC2018 and XC3020 are not available in PGA68, since
Rate the PGA84 is the same size and offers more I/O.

Package Type Note that a PLCC in a socket with PGA footprint generates
a printed circuit board pin-out differentfrom a PGA device.
1972
 XC2064
XC2018
Logic Cell™ Array
Product Specification

FEATURES Part Logic Config- User Config-

Number Capacity urable lias uration
(usable) Logic Program
• Fully user-programmable:
gates Blocks (bits)
• 1/0 functions
• Digital logic functions XC2064 1200 64 58 12038
• Interconnections XC2018 1800 100 74 17878
• General-purpose array architecture
• Complete user control of design cycle
• Compatible arrays with logic cell complexity equivalent
The Logic Cell Array's logic functions and interconnec-
to 1200 and 1800 usable gates
tions are determined by data stored in internal static
• Standard product availability
memory cells. On-chip logic provides for automatic load-
• 100% factory-tested
ing of configuration data at power-up. The program data
• Selectable configuration modes
can reside in an EEPROM, EPROM or ROM on the circuit
• Low-power, CMOS, static memory technology
board or on a floppy disk or hard disk. The program can be
• Performance equivalent to TTL SSIIMSI
loaded in a number of modes to accommodate various
• TTL or CMOS input thresholds
system requirements.
• Complete development system support
• XACT Design Editor
• Schematic Entry
• XACTOR In Circuit Emulator ARCHITECTURE
• Macro Library
The general structure of a Logic Cell Array is shown in
• Timing Calculator
Figure 1. The elements of the array include three catego-
• Logic and Timing Simulator
ries of user programmable elements: 1/0 Blocks,Configur-
• Auto Place I Route
able Logic Blocks and Programmable Interconnections.
The 1/0 Blocks provide an interface between the logic
DESCRIPTION array and the device package pins. The Configurable
Logic Blocks perform user-specified logic functions, and
The Logic Cell™ Array (LCA) is a high density CMOS the interconnect resources are programmed to form net-
integrated circuit. Its user-programmable array architec- works that carry logic signals among blocks.
ture is made up of three types of configurable elements:
InputlOutput Blocks, Logic Blocks and Interconnect. The Configuration of the Logic Cell Array is established
designer can define individual 1/0 blocks for interface to through a distributed array of memory cells. The XACT
external circuitry, define logic blocks to implement logic development system generates the program used to
functions and define interconnection networks to compose configure the Logic Cell Array. The Logic Cell Array
larger scale logic functions. The XACTTM Development includes logic to implement automatic configuration.
System provides interactive graphic design capture and
automatic routing. Both logic simulation and in-circuit Configuration Memory
emulation are available for design verification.
The configuration of the Xilinx Logic Cell Array is estab-
The Logic Cell Array is available in a variety of logic lished by programming memory cells which determine the
capacities, package styles, temperature ranges and logic functions and interconnections. The memory loading
speed grades. process is independent of the user logic functions.

2-55
XC206412018 Logic Cell Array

The static memory cell used for the configuration memory structure of the configuration memory cells, they are not
in the Logic Cell Array has been designed specifically for affected by extreme power supply excursions or very high
high reliability and noise immunity. Based on this design, levels of alpha particle radiation. In reliability testing no
which is covered by a pending patent application, integrity soft errors have been observed, even in the presence of
of the LCA configuration memory is assured even under very high doses of alpha radiation.
adverse conditions. Compared with other programming
alternatives, static memory provides the best combination Input/Output Block
of high density, high performance, high reliability and
comprehensive testability. As shown in Figure 2, the basic Each user-configurable I/O block (lOB) provides an inter-
memory cell consists of two CMOS inverters plus a pass face between the external package pin of the device and
transistor used for writing data to the cell. The cell is only the internal logic. Each I/O block includes a programmable
written during configuration and only read during read- input path and a programmable output buffer. It also
back. During normal operation the pass transistor is "off" provides input clamping diodes to provide protection from
and does not affect the stability of the cell. This is quite electro-static damage, and circuits to protect the LCA from
different from the normal operation of conventional mem- latch-up due to input currents. Figure 3 shows the general
ory devices, in which the cells are continuously read and structure of the I/O block.
rewritten.
The input buffer portion of each I/O block provides thresh-
The outputs Q and Q control pass-transistor gates directly. old detection to translate external signals applied to the
The absence of sense amplifiers and the output capacitive package pin to internal logic levels. The input buffer
load provide additional stability to the cell. Due to the threshold of the I/O blocks can be programmed to be

I/O BLOCK

0 Q OQ
CONFIGURABLE
LOGIC BLOCK~

-[}
-[}
o 0 0 0
-[} 0 01 0 0 • INTERCONNECT AREA •
-[}
-[} 0 0j0 0
-[}
-[} 0 0 0 0
M04 01
Figure 1. Logic Cell Array Structure

2-56
compatible with either TTL (1.4 V) or CMOS (2.2 V) levels. block output buffer. Each I/O block output buffer is con-
The buffered input signal drives both the data input of an trolled by the contents of two configuration memory cells
edge triggered 0 flip-flop and one input of a two-input which turn the buffer ON or OFF or select logical three-
multiplexer. The output of the flip-flop provides the other state buffer control. The user may also select the output
input to the multiplexer. The user can select either the buffer three-state control (I/O block pin TS). When this
direct input path or the registered input, based on the I/O block output control signal is HIGH (a logic "1") the
content of the memory cell controlling the multiplexer. The buffer is disabled and the package pin is high-impedance.
I/O Blocks along each edge of the die share common
clocks. The flip-flops are reset during configuration as well Configurable Logic Block
as by the active-low chip RESET input.
An array of Configurable Logic Blocks (CLBs) provides the
Output buffers inthe I/O blocks provide 4 mAdrive for high functional elements from which the user's logic is con-
fan-out CMOS or TTL compatible signal levels. The output structed. The Logic Blocks are arranged in a matrix in the
data (driving I/O block pin 0) is the data source for the I/O center of the device. The XC2064 has 64 such blocks

READorWRITE _ _ l~ :,- -·'·'·'·_· · · ·- ,-· ~~---,--·····-~t:

· - +~r. =;iiMTI~ __

1104 02
DATA --.W'- ~
:~""-"'-"'-'-'-"" ....-...-.-.-.-.-...-.-...-.....-...-.-...-...........-.-.:.:.-.:.:.:.:.:...:...:.-.:.-.:.:.:.:.....:.:.:.-.~:.:.:.......... ;:

Figure 2. Configuration Memory Cell

I--------------;;_-+-- TS (OUTPUT ENABLE)

OUT

IN

D 0 f-----J

VOCLOCK
~ _ PROGRAM-CONTROLLED
~ - MULTIPLEXER

1104 03
Figure 3. 1/0 Block

2-57
XC206412018 Logic Cell Array

OUTPUTS

A
G
B Y
INPUTS COMB.
C LOGIC
0
F

CLOCK
1104 04

Figure 4. Conflgurable Logic Block

arranged in an 8-row by 8-column matrix. The XC2018 has third form of the combinatorial logic (Option 3) is a special
100 logic blocks arranged in a 10 by 10 matrix. case of the two-function form in which the B input dynami-
cally selects between the two function tables providing a
Each logic block has a combinatorial logic section, a single merged logic function output. This dynamic selec-
storage element, and an internal routing and control sec-
tion. Each CLB has four general-purpose inputs: A, B, C
and D; and a special clock input (K), which may be driven
fromthe interconnect adjacenttothe block. Each CLB also
has two outputs, X and Y, which may drive interconnect
networks. Figure 4 shows the resources of a Configurable
Logic Block.

The logic block combinatorial logic uses a table look-up

memory to implement Boolean functions. This tech-nique
can generate any logic function of up to four variables with F
a high speed sixteen-bit memory. The propagation delay A
through the combinatorial network is independent of the
B ANY
function generated. Each block can perform any function FUNCTION
I----<
of four variables or any two functions of three variables C OF4
VARIABLES
each. The variables may be selected from among the four -
~
D
inputs and the block's storage element output "Q".
Figure 5 shows various options which may be specified for G
the combinatorial logic.

If the single four-variable configuration is selected (Option

1), the F and G outputs are identical. If the two-function
alternative is selected (Option 2), logic functions F and G
OPTION 1
may be independent functions of three variables each.
The three variables can be selected from among the four 1 FUNCTION OF 4
VARIABLES
logic block inputs and its storage element output "Q". A

2-58
tion allows some five-variable functions to be generated High inputs and the asynchronous reset is dominant. The
from the four block inputs and storage element Q. Combi- storage elements are reset by the active-low chip RESET
natorial functions are restricted in that one may not use pin as well as by the initialization phase preceding configu-
both its storage element output Q and the input variable of ration. If the storage element is not used, it is disabled.
the logic block pin "0" in the same function.
The two block outputs, X and Y, can be driven by either the
If used, the storage element in each Configurable Logic combinatorial functions, F or G, or the storage element
Block (Figure 6) can be programmed to be either an edge- output Q (Figure 4). Selection of the outputs is completely
sensitive "0" type flip-flop or a level-sensitive "0" latch. interchangeable and may be made to optimize routing
The clock or enable for each storage element can be efficiencies of the networks interconnecting the logic
selected from: blocks and 1/0 blocks.

• The special-purpose clock input K Programmable Interconnect

• The general-purpose input C
• The combinatorial function G Programmable interconnection resources in the Logic Cell
Array provide routing paths to connect inputs and outputs

•
The user may also select the clock active sense within of the I/O and logic blocks into desired networks. All
each logic block. This programmable inversion elimi- interconnections are composed of metal segments, with
nates the need to route both phases of a clock signal programmable switching points provided to implement the
throughout the device. necessary routing. Three types of resources accommo-
date different types of networks:
The storage element data input is supplied from the
function F output of the combinatorial logic. Asynchro-
nous SET and RESET controls are provided for each • General purpose interconnect
storage element. The user may enable these controls • Long lines
independently and select their source. They are active • Oirect connection

OPTION 2 OPTION 3

2 FUNCTIONS OF 3 DYNAMIC SELECTION OF

1104 05 VARIABLES 2 FUNCTIONS OF 3
VARIABLES

Figure 5. CLB Combinatorial Logic Options

Note: Variables 0 and Q can not be used in the csame function.

2-59
XC206412018 Logic Cell Array

General·Purpose Interconnect and then toggling the states of the interconnect points by
selecting them with the "mouse". In this mode, the connec-
General-purpose interconnect, as shown in Figure 7a, is tions through the switch matrix may be established by
composed of four horizontal metal segments between the selecting pairs of matrix pins. The switching matrix com-
rows and five vertical metal segments between the col- binations are indicated in Figure 7b.
umns of logic and 1/0 blocks. Each segment is only the
"height" or "width" of a logic block. Where these segments Special buffers withi!) the interconnect area provide peri-
would cross at the intersections of rows and columns, odic signal isolation and restoration for higher general
switching matrices are provided to allow interconnections interconnect fan-out and better performance. The repow-
of metal segments from the adjoining rows and columns. ering buffers are bidirectional, since signals must be able
Switches in the switch matrices and on block outputs are to propagate in either direction on a general interconnect
specially designed transistors, each controlled by a con- segment. Direction controls are automatically established
figuration bit. by the Logic Cell Array development system software.
Repowering buffers are provided only for the general-
Logic block output switches provide contacts to adjacent purpose interconnect since the direct and long line re-
general interconnect segments and therefore to the sources do not exhibit the same R-C delay accumulation.
switching matrix at each end of those segments. A switch The Logic Cell Array is divided into nine sections with
matrix can connect an interconnect segment to other buffers automatically provided for general interconnect at
segments to form a network. Figure 7a shows the general the boundaries of these sections. These boundaries can
interconnect used to route a signal from one logic block to be viewed with the development system. For routing
three other logic blocks. As shown, combinations of within a section, no buffers are used. The delay calculator
closed switches in a switch matrix allow multiple branches of the XACT development system automatically calculates
for each network. The inputs of the logic or 1/0 blocks are and displays the block, interconnect and buffer delays for
multiplexers that can be program-med with configuration any selected paths.
bits to select an input network from the adjacent intercon-
nect segments. Since the switch connections to block
inputs are unidirectional (as are block outputs) they are
usable only for input connection. The development sys-
tem software provides automatic routing of these intercon-
nections. Interactive routing is also available for design
optimization. This is accomplished by selecting a network CLB

1104 06

I
I
A-(-----I •• ...l SEE FIG. 7b

o
A

B
x
C CLB J-+--t*i+t--
K y
SET
F-----------lD 0
K-}----I
C-,:-----1

RES

D-'~---I
CLB t+++r----.-J CLB

1104 07

Figure 6. CLB Storage Elememt Figure 7a. General·Purpose Interconnect

2-60
Long Lines the global buffer for a clock provides a very low skew, high
fan-out synchronized clock for use at any or all of the logic
Long-lines, shown in Figure 8a, run both vertically and blocks. At each block, a configuration bit for the K input to
horizontally the height or width of the interconnect area. the block can select this global line as the storage element
Each vertical interconnection column has two long lines; clock signal. Alternatively, other clock sources can be
each horizontal row has one, with an additional long line used.
adjacent to each set of I/O blocks. The long lines bypass
the switch matrices and are intended primarily for signals A second buffer below the bottom row of the array drives
that must travel a long distance or must have minimum a horizontal long line which, in tum, can drive a vertical long
skew among multiple destinations. line in each interconnection column. This aHernate buffer
also has low skew and high fan-out capability. The
A global buffer in the Logic Cell Array is available to drive network formed by this alternate buffer's long lines can be
a single signal to all Band K inputs of logic blocks. Using selected to drive the B, C or K inputs of the logic blocks.

•
2 VERTICAL
LONG LINES GLOBAL
NET AVAILABLE PROGRAMMABLE
~ r-'--.
I I I I I, I I SWITCH MATRIX INTERCONNECTIONS
OF GENERAL INTERCONNECT
SEGMENTS BY PIN

,
,,,
t;r,
, ,
g' tJ'
a
7
3

4
a

7
3

s.. .'
0
• •
00
6 •

U'
QQO

,-I :0 a 3 a 3

a., e.,
0 0 ,, 7 4 7 4
,,
6 •
a a
b
X
a 3 s 3

Y 7 4 7 4

:, 6 5 6 5
,
t;r,

{~ DO
, ,
, ,
QQO
OQ
r-'
:0
0

0
-}
_
_
4 HORIZONTAL
GENERAL PURPOSE
INTERCONNECT
7
~'
a

6 5
3

4 S'
8

6 6
3

I
0 0 I
I
I
I
I
I

I I I I
,
5 VERTICAL
GENERAL PURPOSE \ PROGRAMMABLE
INTERCONNECT INTERCONNECT POINTS
BETWEEN SWITCH (DO NOT USE MORE THAN
MATRICES ONE PER INPUT PIN)

1104 08

Figure 7b. Routing and Switch Matrix Connections

2-61
XC206412018 Logic Cell Array

Alternatively, these long. lines can be driven by a logic or bottom of the die. Direct interconnections of 1/0 blocks
1/0 block on a column by column basis. This capability with CLBs are shown in Figure 8b.
provides a common, low-slsew clock or control line within
each column of logic blocks. Interconnections of these Crystal Oscillator
long lines are shown in Figure 8b.
An internal high speed inverting amplifier is available to
Direct Interconnect implement an on-Chip crystal OSCillator, ·It is associated
with the auxiliary clock buffer in the lower right corner of the
Direct interconnect, shown in Figure 9, provides the most die. When configured to drive the auxiliary clock buffer,
efficient implementation of networks between adjacent two special adjacent user 110 blocks are also configured to
logic or 1/0 blocks. Signals routed from blgck to block by connect the oscillator amplifier with external crystal oscil-
means of direct interconnect exhibit minimum int!lrcon- lator components, as shown in Figure 10. This circuit
nect propagation and use minimum interconnect re- becomes active before configuration is complete in order
sources. For each Configurable Logic Block, the X output to allow the oscillator to stabilize. Actual internal connec-
may be connected directly to the Cor D inputs of the CLB tion is delayed until completion of configuration. The
above and to the A or B inputs of the CLB below it. The Y feedback resistor R1 between output and input, biases the
output can use direct interconnect to drive the B input of the amplifier at threshold. It should be as large a value as
block immediately to its right. Where logic blocks are practical to minimize loading of the crystal. The inversion
adjacent to 1/0 blocks, direct connect is provided to the of the amplifier, together with the R-C networks and
1/0 block input (I) on the left edge ofthe die, the output (0) crystal, produce the 360-degree phase shift of the Pierce
on the right edge, or both on 1/0 blocks at the top and oscillator. A series resistor R2 may be included to add to

a a I
SWITCH
MATRIX
I

L-

-----l
B

~
a a .

0 CLB
X

SWITCH
MATRIX
L- HORIZONTAL
LONG LINE

a a
TWO VERTICAL GLOBAL
LONG LINES LONG LINE

1104 09
Figure 8a. Long Line Interconnect

2-62
GLOBAL VERTICAL LONG LINES HORIZONTAL LONG LINES 1/0 CLOCKS
BUFFER (2 PER COLUMN) (1 PERROW) (1 PER EDGE)

•
~
z
z

1/0 CLOCKS ALTERNATE OSCILLATOR

(1PER EDGE) BUFFER AMPLIFIER

Figure ab. XC2064 Long Lines, (fa Clocks, 1/0 Direct Interconnect

2-63
XC2064/2018 Logic Cell Array

the amplifier output impe-dance when needed for phase- For packages having more than 48 pins, two Vcc pins and
shift control or crystal resistance matching or to limit the two ground pins are provided (see Figure 11). Inside the
amplifier input swing to control clipping at large ampli- LCA, a dedicated Vcc and ground ring surrounding the
tudes. Excess feedback voltage may be adjusted by the logic array provides power to the 110 drivers. An independ-
ratio of C2/C1. The amplifier is designed to be used over ent matrix of Vcc and ground lines supplies the interior
the range from 1 MHz up to one-half the specified CLB logic of the device. This power distribution grid provides a
toggle frequency. Use at frequencies below 1 MHz may stable supply and ground for all internal logic, providing the
require individual characterization with respect to a series external package power pins are appropriately decoupled.
resistance. Operation at frequencies above 20 MHz Typically a 0.1 ~F capacitor connected between the Vcc
generally requires a crystal to operate in a third overtone and ground pins near the package will provide adequate
mode, in which the fundamental frequency must be sup- decoupling.
pressed by the R-C networks. When the amplifier does not
drive the auxiliary buffer, these 1/0 blocks and their pack- Output buffers capable of driving the specified 4 rnA loads
age pins are available for general user 1/0. under worst-case conditions may be capable of driving 25
to 30 times that current in a best case. Noise can be
reduced by minimizing external load capacitance and
POWER reducing simultaneous output transitions in the same
direction. It may also be beneficial to locate heavily loaded
Power Distribution output buffers near the ground pads. Multiple Vcc and
ground pin connections are required for package types
Power for the LCA is distributed through a grid to achieve which provide them.
high noise immunity and isolation between logic and 1/0.
Power Dissipation

The Logic Cell Array exhibits the low power consumption

characteristic of CMOS ICs. Only quiescent power is
required for the LCA configured for CMOS input levels.
The TTL input level configuration option requires addi-
tional power for level shifting. The power required by the
static memory cells which hold the configuration data is
very low and may be maintained in a power-down mode.

Typically most of power dissipation is produced by capaci-

tive loads on the output buffers, since the power per output
is 25 ~W I pF I MHz. Another component of 1/0 power is
the DC loading on each output pin. For any given system,
the user can calculate the 110 power requirement based on
the sum of capacitive and reSistive loading of the devices
driven by the Logic Cell Array.

Internal power supply dissipation is a function of clock

frequency and the number of nodes changing on each
clock. In an LCA the fraction of nodes changing on a given
clock is typically low (10-20%). For example, in a 16-bit
binary counter, the average clock produces a change in
slightly less than 2 of the 16 bits. In a 4-input AND gate
there will be 2 transitions in 16 states. Typical global clock
buffer power is about 3 mW I MHz for the XC2064 and
4mW I MHz for the XC2018. With a ''typical'' load of three
general interconnect segments, each Configurable Logic
Block output requires about 0.4 mW I MHz of its output
1104 10 frequency. Graphs of power versus operating frequency
Figure 9. Direct Interconnect are shown in Table 1.

2-64
 ON-CHIP EXTERNAL

ALTERNATE
CLOCK BUFFER
XTAll

o
o
SUGGESTED COMPONENT VALUES R2
R1 1-4Mn
R20-1Kn
(may be required for low frequency, phase

•
~ Cl
shift andlor oompensation level for crystal OJ
C1,C2 10-40pF ~C2
Y1 1 -20 MHz AT cut

XTAL1 XTAL2
48 DIP 33 30
68PLCC 46 43
68PGA J10 L10
84PLCC 56 53
84PGA K11 L11

1104 11

Figure 10. Crystal Oscillator

GND

GROUND AND
VeeRING FOR
+- -+ -- + --+ --+- -+- -+- -+ UODRIVERS

+- -+ -- + --+- -+- -+- -+--+

I I t I I I I I
I , I , I I I I

+- -+ --+ --+ --+- -+--+--+,

I
I
I
I
I
I
I
I ,
+ --+ -- +- -+ --+- -+-- +-- +,
Vee
I
I
I
I
I
I
I
I
I
I , 1
I Vee
+ --+ -- +- -+ --+-
,, -+ -- +--
, +,
+--+--+--+--+--
,, ,, ,, ,, LOGIC POWERGRID
+ --+- -+- -+- -+ --+ -- +-- +
I I I I 1 I I
r I I I I I I

+ -- +- -+--+ --+ -- + -- +--+

GND

1104 12

Figure 11. LCA Power Distribution

2-65
XC206412018 Logic Cell Array

PROGRAMMING As each data bit is supplied to the LCA, it is internally

assembled into a data word. As each data word is
Configuration data to define the function and intercon- completely assembled, it is loaded in parallel into one word
nection within a Logic Cell Array are loaded automatically of the internal configuration memory array. The last word
at power-up or upon command. Several methods of must be loaded before the current length count compare is
automatically loading the required data are designed into true. If the configuration data are in error, e.g., PROM
the Logic Cell Array and are determined by logic levels address lines swapped, the LCA will not be ready at the
applied to mode selection pins at configuration time. The length count and the counter will cycle through an addi-
form of the data may be either serial or parallel, depending tional complete count prior to configuration being "done".
on the configuration mode. The programming data are
independent of the configuration mode selected. The Figure 14 shows the selection of the configuration mode
state diagram of Figure 12 illustrates the configuration based on the state of the mode pins MO and MI. These
process. package pins are sampled priorto the start of the configu-
ration process to determine the mode to be used. Once
Input thresholds for user 1/0 pins can be selected to be configuration is DONE and subsequent operation has
either TTL-compatible or CMOS-compatible. At power- begun, the mode pins may be used to perform data
up, all inputs are TTL-compatible and remain in that state readback, as discussed later. An additional mode pin, M2,
until the LCA begins operation. If the user has selected must be defined althe start of configuration. This package
CMOS compatibility, the input thresholds are changed to pin is a user-configurable 1/0 after configuration is com-
CMOS levels during configuration. plete.

Figure 13 shows the specific data arrangement for the Initialization Phase
XC2064 device. Future products will use the same data
format to maintain compatibility between different devices When power is applied, an internal power-on-reset circuit
of the Xilinx product line, but they will have different sizes is triggered. When Vcc reaches the voltage at which the
and numbers of data frames. For the XC2064, configura- LCA begins to operate (2.5 to 3 Volts), the chip is initial-
tion requires 12,038 bits for each device. Forthe XC2018, ized, outputs are made high-impedance and a time-out is
the configuration of each device requires 17,878 bits. The initiated to allow time for power to stabilize. This time-out
XC2064 uses 160 configuration data frames and the (15 to 35 ms) is determined by a counter driven by a self-
XC2018 uses 197. generated, internal sampling clock that drives the configu-
ration clock (CCLK) in master configuration mode. This
The configuration bit stream begins with preamble bits, a internal sampling clock will vary with process, temperature
preamble code and a length count. The length count is and power supply over the range of 0.5 to 1.5 MHz. LCAs
loaded into the control logic of the Logic Cell Array and is with mode lines set for master mode will time-out of their
used to determine the completion of the configuration initialization using a longer counter (60 to 140 ms) to
process. When configuration is initiated, a 24-bit length assure that all devices, which it may be driving in a daisy
counter is set to 0 and begins to count the total number of chain, will be ready. Configuration using peripheral or
configuration clock cycles applied to the device. When the
current length count equals the loaded length count, the 1104 13
configuration process is complete. Two clocks before MODE PIN
completion, the internal logic becomes active and is reset. MODE SELECTED
On the next clock, the inputs and outputs become active as MO Ml M2
configured and consideration should be given to avoid
0 0 0 MASTER SERIAL
configuration signal contention. (Attention must be paid to
avoid contention on pins which are used as inputs during 0 0 1 MASTER LOW MODE
configuration and become outputs in operation.) On the
last configuration clock, the completion of configuration is 0 1 1 MASTER HIGH MODE
signalled by the release of the DONE I PROG pin of the 1 0 1 PERIPHERAL MODE
device as the device begins operation. This open-drain
output can be AN D-tied with multiple Logic Cell Arrays and 1 1 1 SLAVE MODE
used as an active-high READY or active-low, RESET, to
MASTER lOW ADDRESSES BEGIN AT 0000 AND INCREMENT
other portions of the system. High during configuration MASTER HIGH ADDRESSES BEGIN AT FFFF AND DECREMENT
(HOC) and low during configuration (LDC), are released
one CCLK cycle before DONE is asserted. In master
mode configurations, it is convenient to use LDC as an Figure 14. Configuration Mode Selection
active-low EPROM chip enable.

2-66
 E:XIUNX

slave modes must be delayed long enough for this initiali- zation will require about 160 additional cycles of the inter-
zation to be completed. nal sampling clock (197 for the XC2018) to clear the
internal memory before another configuration may begin.
The initialization phase may be extended by asserting the Reprogramming is initialized by a HIGH-to-LOW transition
active-low external RESET. If a configuration has begun, on RESET (after RESET has been HIGH for at least 6 ns)
an assertion of RESET will initiate an abort, including an followed by a LOW level (for at least 6 ns) on both the
orderly clearing of partially loaded configuration memory RESET and the open drain DONE/PROG pins. This re-
bits. After about 3 clock cycles for synchronization, initiali- turns the LCA to the CLEAR state, as shown in Fig. 12.

POWER·ON DELAY IS
214 CYCLES FOR NON-MASTER MODE-1 1 TO 33 mS
216 CYCLES FOR MASTER MODE-43 TO 130 mS

USER 110 PINS WITH HI<;iH IMPEDANCE PULL·UP

HDC= HIGH
LDC=LOW

LOW ON DONEIPROGRAM AND RESET

CLEAR IS
-160 CYCLES FOR THE XC2064-100 TO 320 liS
-200 CYCLES FOR THE XC2016-125 TO 390 liS
1104 14

Figure 12. A State Diagram of tile Configuration Process for Power-up and Re-program

11111111 DUMMY BITS (4 BITS MINIMUM), XACT 2.10 GENERATES 8 BJTS

0010 PREAMBLE CODE HEADER
< 24-BIT LENGTH COUNT > CONFIGURATION PROGRAM LENGTH
1111 DUMMY BITS (4 BITS MINIMUM)

o < DATA FRAME # 001 > 111

o < DATA FRAME # 002 > 111
o <DATAFRAME#003> 111 XC2018 XC2064
CONFIGURATION PROGRAM DATA
FRAMES 196 160
DATA BITS
PER FRAME 87 71 REPEATED FOR EACH LOGIC
CELL ARRAY IN A DAISY CHAIN
o < DATA FRAME # 159>
111
o <DATAFRAME#160> 111

1111 POSTAMBLE CODE (4 BITS MINIMUM)

START-UP REQUIRES THREE CONFIGURATION CLOCKS BEYOND LENGTH COUNT

1104 15

Figure 13. XC2064 Internal Configuration Data Arrangement

2-67
XC206412018 Logic Cell Array

Master Mode least significant bit of each byte, normally DO, is the next bit
in the serial stream.
In master mode, the Logic Cell Array automatically loads
the configuration program from an external memory de-
vice. Figure 15a shows an example of the master mode
connections required. The Logic Cell Array provides
Addresses supplied by the Logic Cell Array can be se-
lected by the mode lines to begin at address
incremented to read the memory (master low mode), or
°
and

sixteen address outputs and the control signals RCLK they can begin at address FFFF Hex and be decremented
(read clock), HOC (high during configuration) and LOC (master high mode). This capability is provided to allowthe
(low during configuration) to execute read cycles from the Logic Cell Array to share external memory with another
external memory. Parallel eight-bit data words are read device, such as a microprocessor. For example, if the
and internally serialized. As each data word is read, the processor begins its execution from low memory, the Logic

USER CONTROL OF HIGHER

.--1--------.--- +5V ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT FROM
ALTERNATIVE CONFIGURATIONS

5i<n DOUT
*
M2 CCLK
*
HOC
A15
GENERAL-
PURPOSE RCLK A14
USER 110
PNS A13 EPROM
A12 OR~~ER)
} OTHER A11
110 PINS
A10 A10
LeA
RESET RESET A9 A9
07 AS AS
06 A7 A7
05 AS A6
04 A5 A5
03 A4 A4
02 A3 A3
01 A2 A2
DO A1 A1 01
AD AD DO

DONE Dip

DATA BUS

* FOR OPTIONAL SLAVE MODE LCAs IN A DAISY CHAIN

1104 16

Figure 15a. Master Parallel Mode. Configuration data are loaded automaticaly from an external byte wide PROM.
An XC2000 LDC signal can provide a PROM inhibit as the user lias become active.

2-68
Cell Array can load itself from high memory and enable the Figure 16 shows the peripheral mode connections. Proc-
processor to begin execution once configuration is com- essor write cycles are decoded from the common asser-
pleted. The DONE / PROG output pin can be used to hold tion of the active-low write strobe (WS), and two active-low
the processor in a Reset state until the Logic Cell Array has and one active-high chip selects (CSa CS1 CS2). If all
completed the configuration process. these signals are not available, the unused inputs should
be driven to their respective active levels. The Logic Cell
The master serial mode uses serial configuration data, Array will accept one bit of the configuration program on
synchronized by the rising edge of RCLK, as shown in the data input (DIN) pin for each processor write cycle.
Figure 15b. Data is supplied in the serial sequence described earlier.

Since only a single bit from the processor data bus is

Peripheral Mode loaded per cycle, the loading process involves the proces-
sor reading a byte or word of data, writing a bit of the data
Peripheral mode provides a simplified interface through to the Logic Cell Array, shifting the word and writing a bit
which the device may be loaded as a processor peripheral. until all bits of the word are written, then continuing in the

DURING CONFIGURATION
THE 5 k!l M2 PULL-DOWN
RESISTOR OVERCOMES
THE INTERNAL PULL-UP.
BUT IT ALLOWS M2TO BE
USER 1/0.

5k!l '----

"-----
~

-
-
-
DOUT

M2
HOC
I I
MO Ml PWRDWN
+r

*
'--+
r-*
•
--<: LOC
GENERAL-
P URPOSE
USERVO
PNS -
)m","
1/0 PINS

- LeA

+5V

RESET->---( RESET II Vpp

r---·----------.... --;
Vee
DIN DATA SERIAL
CCLK CLK
MEMORY
~ CASCADED
SERIAL

DONE- - DIP
LDC CE CEO
XC1736
~ MEMORY

rOE :L .. _________________ .J

'"v (HIGH RESETS THE XC1736 ADDRESS POINTER)

(00::
CCLK~

(OUTPUT) _
_=====' -------'- _ *
* FOR OPTIONAL SLAVE MODE LCAs IN A DAISY CHAIN
1104 17 Figure 15b. Master Serial Mode. The one time programmable XC1736 Serial Configuration PROM
supports automatic loading of configuration programs up to 36K bits. Multiple XC1736s can be cascaded to
support additional LCAs. An XC2000 LOC signal can provide an XC1736 inhibit as the user lias become active.

2-69
XC206412018 Logic Cell Array

same fashion with the next word, etc. After the configu ra- supplied by the lead device, which is configured in master
tion program has been loaded, an additional three clocks or peripheral mode. After the configuration program has
(a total of three more than the length count) must be been loaded, an additional three clocks (a total of three
supplied in order to complete the configuration process. more than the length count) must be supplied in order to
When more than one device is being used in the system, complete the configuration process.
each device can be assigned a different bit in the proces-
sor data bus, and multiple devices can be loaded on each Daisy Chain
processor write cycle. This "broadside" loading method
provides a very easy and time-efficient method of loading The daisy-chain programming mode is supported by Logic
several devices. Cell Arrays in all programming modes. In master mode
and peripheral mode, the LCA can act as a source of data
Slave Mode and control for slave devices. For example, Figure 18
shows a single device in master mode, with 2 devices in
Slave mode, Figure 17, provides the simplest interface for slave mode. The master mode device reads the external
loading the Logic Cell Array configuration. Data is sup- memory and begins the configuration loading process for
plied in conjunction with a synchronizing clock. For each all of the devices.
LOW-to-HIGH input transition of configuration clock
(CCLK), the data present on the data input (DIN) pin is The data begin with a preamble and a length count which
loaded into the internal shift register. Data may be sup- are supplied to all devices at the beginning of the configu-
plied by a processor or by other special circuits. Slave ration. The length count represents the total number of
mode is used for downstream devices in a daisy-chain cycles required to load all of the devices in the daisy chain.
configuration. The data for each slave LCA are supplied After loading the length count, the lead device will load its
by the preceding LCA in the chain, and the clock is configuration data while providing a HIGH DOUTto down-

ADDRESS DATA +5V +5V

BUS BUS

5kn
DO
10WRT
DIN CCLK *
WRT
DOUT *
M2
ADDRESS CSO HDC
DECODE
LOGIC LDC
GENERAL·

,~
OTHER
1/0 PINS
1 PURPOSE
USER 1/0

CS1
CS2
DONE DIP
RESET RESET

CS2
-':....t....I..~1...L..J1

CCLK -----t----.
(OUTPUT) -----il===~L----l:===
DIN
_____ ~uw---~~----~---

DOUT-----~~'r--------~-.
(OUTPUT) _ _ _ _ _ _ _ _, ,_ _ _ _ _ _ _ _ _ _- - '

* FOR OPTIONAL SLAVE MODE LCAs IN A DAISY CHAIN 1104 18

Figure 16. XC2000 Peripheral Mode. Configuration data are loaded using serialized data from a microprocessor.

2-70
stream devices. When the lead device has been loaded connected to the internal circuitry.
and the current length count has not reached the full value,
memory access continues. Data bytes are read and SPECIAL CONFIGURATION FUNCTIONS
serialized by the lead device. The data are passed through
the lead device and appear on the data out (DOUT) pin in In addition to the normal user logic functions and inter-
serial form. The lead device also generates the configura- connect, the configuration data include control for several
tion clock (CCLK)to synchronize the serial output data. A special functions:
master mode device generates an internal CCLK of
8 times the EPROM address rate, while a peripheral mode • Input thresholds
device produces CCLK from the chip select and write • Readback enable
strobe timing. • Reprogram
• DONE pull-up resistor
Operation
Each of these functions is controlled by a portion of the
When all of the devices have been loaded and the length configuration program generated by the XACT Develop-
count is complete, a synchronous start-up of operation is ment System.
performed. Onthe clock cycle following the end of loading,
the intemallogic begins functioning in the reset state. On Input Thresholds
the next CCLK, the configured output buffers become
active to allow signals to stabilize. The next CCLK cycle During configuration, all input thresholds are TTL level.
produces the DONE condition. The length count control of During configuration input thresholds are established as
operation allows a system of multiple Logic Cell Arrays to specified, either TTL or CMOS. The PWRDWN input
begin operation in a synchronized fashion. If the crystal threshold is an exception; it is always a CMOS level input.
oscillator is used, it will begin operation before configura- The TTL threshold option requires additional power for
tion is complete to allow time for stabilization before it is threshold shifting.

+5V

MICRO 5kQ
COMPUTER

STRB CCLK M2 *
DO DIN DOUT -*

D1 HDC
1/0 D2 LDC
PORT GENERAL-
PURPOSE
D3 LCA USER 1/0
D4

D5 OTHER {
1/0 PINS
D6 DIP
D7

RESET RESET

==xI;
~
DIN BITN BITN +1

CCLK
~ h I

1104 19
DOUT
(OUTPUT)
BITN-1
~ BITN

*FOR OPTIONAL SLAVE MODE LCAs IN A DAISY CHAIN

Figure 17. Slave Mode. Bit-serial configuration data are read at rising edge of the CCLK. Data on DOUT are
provided on the falling edge of CCLK. Identically configured non-master mode LCAs can be configured in parallel
by connecting DINs and CCLKs.

2-71
XC2064/2018 Logic Cell Array

Readback guarantees that the LCA will return to the Clear state.
Either of these methods may be needed in the event of an
After a Logic Cell Array has been programmed, the con- incomplete voltage interruption. They are not needed for a
figuration program may be read back from the device. normal application of power from an off condition.
Readback may be used for verification of configuration,
and as a method of determining the state of internal logic DONE Pull-up
nodes during debugging. Three readback options are
provided: on command, only once, and never. The DONE I PROG pin is an open drain 1/0 that indicates
programming status. As an input, it initiates a reprogram
An initiation of read back is produced by a LOW-to-HIGH operation. An optional internal pull-up resistor may be
transition of the MO I RTRIG (read trigger) pin. Once the enabled.
readback cornmand has been given, CCLK is cycled to
read back each data bit in aformat similar to loading. After Battery Backup
two dummy bits, the first data frame is shifted out, in
inverted sense, on the M1 I RDATA (read data) pin. All Because the control store of the Logic Cell Array is a
data frames must be read back to complete the process CMOS static memory, its cells require only a very low
and return the mode select and CCLK pins to their normal standby current for data retention. In some systems, this
functions. Read back data includes the state of all internal low data retention current characteristic facilitates pre-
storage elements. This information is used by the Logic serving configurations in the event of a primary power loss.
Cell Array development system In-Circuit Debugger to The LogiC Cell Array has built in power-down logic which,
provide visibility into the internal operation of the logic when activated, will disable normal operation of the device
while the system is operating. To read back a uniform time and retain only the configuration data. All internal opera-
sample of all storage elements, it may be necessary to tion is suspended and all o\Jtput buffers are placed in their
inhibit the system clock. high impedance state.

Re-program Power-down data retention is possible with a simple bat-

tery-backup circuit because the power requirement is
The Logic Cell Array configuration memory may be re- extremely low. For retention at 2.0 volts, the required
written while the device is operating in the user's system. current is typically on the order of 50 nanoamps. Screen-
The LCA returns to the Clear state where the configuration ing to this parameter is available. To force the Logic Cell
memory is cleared, 1/0 pins disabled, and mode lines re- Array into the power-down state, the user must pull the
sampled. Re-program control is often implemented using PWRDWN pin LOW and continue to supply a retention
an external open collector driver which pulls DONE/PROG voltage to the Vcc pins of the package. When normal
LOW. Once it recognizes a stable request, the Logic Cell power is restored, Vcc is elevated to its normal operating
Array will hold DONE/PROG LOW until the new configura- voltage and PWRDWN is returned to a HIGH. The Logic
tion has been completed. Even if the DONE/PROG pin is Cell Array resumes operation with the same internal se-
externally held LOW beyond the configuration period, the quence that occurs at the conclusion of configuration.
Logic Cell Array will begin operation upon completion of Internal 1/0 and logic block storage elements will be reset,
configuration. To reduce sensitivity to noise, these re- the outputs will become enabled and then the
program signals are filtered for 2-3 cycles of the LCA's DONEIPROG pin will be released. No configuration
internal timing generator (2 to 6I1S). Note that the Clear programming is involved.
time out for a Master mode re-program or abort does not
have the 4 times delay of the Initialization state. If a daisy
chain is used, an external RESET is required, long enough
to guarantee clearing all non-master mode devices. For PERFORMANCE
XC2000 series LCAs this is accomplished with an external
time delay. The high performance of the Logic Cell Array results from
its patented architectural features and from the use of an
In some applications the system power supply might have advanced high-speed CMOS manufacturing process.
momentary failures which can leave the LCA's control Performance may be measured in terms of minimum
logic in an invalid state. There are two metods to recover propagation times for logic elements.
from this state. The first is to cycle the Vcc supply to less
than 0.1 Volt and reapply valid Vcc. The second is to Flip-flop loop delays for the 1/0 block and logic block flip-
provide the LCAwith simultaneous LOW levels of at least flops are about 3 nanoseconds. This short delay provides
611S on RESET and DONE/PROG pins after the RESET very good performance under asynchronous clock and
pin has been HIGH following a return to valid Vcc. This data conditions. Short loop delays minimize the probability

2-72
 5k!l
I ~
- M2
II r
Ma Ml PWRDWN

CCLK-
DOUT DIN
+~v

I I 1
MO Ml PWRDWN

' - - CCLK

LCA
DOUT
5k!l

"
...
-
II
CCLK

DIN
+5V
1

MO Ml PWRDWN

LCA
!

DOUT
5k!l

SLAVE'l SLAVEiIn
- HDC M2 I- M2

GENERAL·
-< RCLK A15 _ .... --:- A15 HOC I-- HDC f-
PURPOSE
USERVO
A14 A14 LDC ~ GENERAL· LOC """"
GENERAL·
PURPOSE PURPOSE
PNS A13 A13 I-- USERVO USERVO
- A12 A12
EPROM
OTHER {
VOPINS
OTHER{
VOPINS
c-
OTHER
I/O PINS All All I-- c-
- LCA A10 Ala
MASTER
A9 AS ~ DIP - DIP

,-- 07 AS AS --< RESET -< RESET

I\)
r - - De A7 A7 D7 r--
23 r - - D5 AS AS De r--
,-- 04 AS A5 05 r--
,
NOTE: RESET OF AI ASTER DEVICE
SHOULD BE ASSERT o BY AN EXTERNAL
r- 03 A4 A4 D4
, TIMING CIRCUIT TO , ,LLOW FOR LeA CCLK
,-- 02 AS AS D3 VARIATIONS IN CLEI R STATE TIME.

r- 01 A2 A2 02,
,
v----- 00 Al
AD
Al
AD
01
00,

fr
LOC DE
r< O/P
RESET L CE r-----"+5V

B 5k!l
OPEN
..... COUECTOR
REPROGRAM
... "
SYSTEM RESET ~ . "
--- I

Figure 18. Master Mode with Daisy Chain

1104 20 M
Any XC3000 slave driven by an XC2000 master mode device must use "early DONE and early internal reset".
(The XC2000 master will not supply the extra clock required by a "late" programmed XC3000.)

•
XC2064/2018 Logic Cell Array

of a metastable condition which can result from assertion Logic Block Performance
of the clock during data transitions. Because of the short
loop delay characteristic in the Logic Cell Array, the 1/0 Logic block propagation times are measured from the
block flip-flops can be used very effectively to synchronize interconnect point at the input of the combinatorial logic to
external signals applied to the device. Once synchronized the output of the block in the interconnect area. Com-
in the 1/0 block, the signals can be used internally without binatorial performance is independent of logic function
further consideration of their clock relative timing, except because of the table look-up based implementation.
as it applies to the internal logic and routing path delays. Timing is different when the combinatorial logic is used in
conjunction with the storage element. Forthe combinato-
Device Performance rial logic function driving the data input of the storage
element, the critical timing is data set-up relative to the
The single parameter which most accurately describes the clock edge provided to the storage element. The delay
overall performance of the Logic Cell Array is the maxi- from the clock source to the output of the logic block is
mum toggle rate for a logic block storage element config- critical in the timing of signals produced by storage ele-
ured as a toggle flip-flop. The configuration for determin- ments, The loading on a logic block output is limited only
ing the toggle performance of the Logic Cell Array is shown by the additional propagation delay of the interconnect
in Figure 19. The clock forthe storage element is provided network. Performance of the logic block is a function of
by the global clock buffer and the flip-flop output Q is fed supply voltage and temperature, as shown in Figures 22
back through the combinatorial logic to form the data input and 23.
forthe next clock edge. Using this arrangement, flip-flops
in the Logic Cell Array can be toggled at clock rates from Interconnect Performance
33-70 MHz, depending on the speed grade used.
Interconnect performance depends on the routing re-
Actual Logic Cell Array performance is determined by the source used to implement the signal path. As discussed
critical path speed, including both the speed of the logic earlier, direct interconnect from block to block provides a
and storage elements in that path, and the speed of tM minimum delay path for a signal.
particular network routing. Figure 20 shows a typical
system logic configuration of two flip-flops with an extra The single metal segment used for long lines exhibits low
combinatorial level between them. Depending on speed resistance from end to end, but relatively high capa-
grade, system clock rates to 35 MHz are practical for this citance. Signals driven through a programmable switch
logic. To allow the user to make the best use of the will have the additional impedance of the switch added to
capabilities of the device, the delay calculator in the XACT their normal drive impedance.
Development System determines worst-case path delays
using actual impedance and loading information. General-purpose interconnect performance depends on
the number of switches and segments used, the pre-sence
of the bidirectional repowering buffers and the overall
loading on the signal path at all pOints along the path. In
calculating the worst-case delay for a general interconnect
path, the delay calculator portion of the XACT develop-
ment system accounts for all of these elements. As an
approximation, interconnect delay is proportional to the
summation of totals of local metal segments beyond each
programmable switch. In effect, the delay is a sum of
R-C delays each approximated by an R times the total C
it drives. The R of the switch and the C of the interconnect
are functions of the particular device performance grade.
D Q f--+--i:-- x, Y For a string of three local interconnects, the approximate
K -'::~-------I delay at the first segment, after the first switch resistance,
would be three units; an additional two delay units afterthe
next switch plus an additional delay after the last switch in
the chain. The interconnect R-C chain terminates at each
1104 21 repowering buffer. Nearly all of the capacitance is in the
interconnect metal and switches; the capacitance of the
Figure 19. Logic Block Configuration for block inputs is not significant. Figure 21 shows an esti-
Toggle Rate Measurement mation of this delay.

2-74
 COMBINATORIAL CLB

INPUTS
......................................................
"......... . ...SOURCE ,.,.,.,...,.,....•.CLB

Q
,.,...,...,.,.".,.,',.,.,.".".,,1:NPUTS =E-
~GENERAL/ =
1 DESTINATION CLB

Q
,.
:--

INTERCONNECT!:

GLOBAL GLOBAL J:.-____---'

II
CLOCK CLOCK

1104 22

Figure 20. Typical Logic Path

r-, r-,
rr------~~------~4-----~~------4--+~ ~_+~----~ ~
L_~ L_~

REPOWERING
BUFFER

CLB

r ,
I I
L_~

R1

C1

DELAY:
INCREMENTAL

IF R,=R 2 =R3 =R AND C,=C 2=C 3 =C

THEN CUMULATIVE DELAY 3RC SRC 6RC 6RC + BUFFER

1104 23

Figure 21. Interconnection Delay Factors Example

2-75
XC2064f2018 Logic Cell Array

1.3

1.2

1.1
0
§ 1.0
..J
<
::;
a: 0.9
0
~
0.8
S
w
c 0.7

0.6

0.5
-55-40 o 30 70 85 125
TEMPERATURE r C)
NOTE: NORMALIZED FOR 3O'C
1104 25

Figure 22. Delay vs. Temperature

1.2

5"
llJ 1.1
N
::::;
<
::i!
0:
~ 1.0
>-
S
llJ
0
0.9

4 4.5 5.0 5.5 6.0

Vee
1104 26

Figure 23. Delay vs. Power Supply Voltage

2-76
 I:XILINX

100
90
80
/
70
60
/ 50
/ 40

150
/ 30

V
100
/ / 20

/
/ /
V V
III
0 10
/ / / 9
40
1/ / 8
L / /
0 / / 6
(mW) / / / 5 (rnA)
20
/ / / 4
/ / / V 3
V V
/ / /
0
/ / 2

/
V V /

V
/
/
/
/
/ V
/ /
/ .9
.8
20 CLB OUTPUTS
3 LOCAL SEGMENTS ~ / / / ..
.7
EACH
3
/ / / .6
/ / / .5
/ / V
2 .4

(3mWIMHz) /
V / V .3
V
GLOBAL CLOCK
BUFFER
1
/ V
/ .2

/
(1.25 mWIMHz)

1 110 OUTPUT
(50pF)0.5
/

0.5
~/
1
/ 2 4 5 10 20 30 40 50
.1

FREQUENCY MHz
(0.4 mWIMHz) /
1 CLBOUTPUT
3 LOCAL
INTERCONNECT

1104 'Zl

Table 1. Typical LCA Power Consumptl.on By Element

2-77
XC206412018 Logie Cell Array

DEVELOPMENT SYSTEMS
Design verification may be accomplished by using the
To accomplish hardware development support for the XILINX XACTOR In-Circuit Design Verifier directly in the
Logic Cell Array, Xilinx provides a development system target system and/or the P-SILOS logic simulator.
with several options to support added capabilities. The
XACT system provides the following: PIN DESCRIPTIONS

• Schematic entry 1. Permanently Dedicated Pins.

• Automatic place and route
• Interactive design editing for optimization Vee
• Interactive timing calculations One or two (depending on package type) connections to
the nominal +5 V supply voltage. All must be connected.
• Macro library support, both for standard Xilinx
supplied functions and user defined functions
GND
• Design entry checking for consistency and One or two (depending on package type) connections to
completeness
ground. All must be connected.
• Automatic design documentation generation
• PROM programmer format output capabilities PWRDWN
• Simulation interface support including automatic A LOW on this CMOS compatible input stops all internal
netlist (circuit description) and timing extraction activity to minimize Vcc power and puts all output buffers
• Logic and timing simulation in a high impedance state, but Configuration is retained.
• In-circuit design verification for multiple devices When the PWRDWN pin returns HIGH the device returns
to operation with the same sequence of buffer enable and
The host system on which the XACTsystem operates is an DONE/PROGRAM as at the completion of configuration.
IBM PC/ATorcompatible system with DOS 3.0{)r higher. All internal storage elements are reset. If not used,
The system requires 640K bytes of internal RAM, 1.5 to 5.5 PWRDWN must be tied to Vcc.
Mbyte of Extended Memory, color graphics and a mouse.
A complete system requires one parallel I/O port and two RESET
serial ports for the mouse and in-circuit emulation. This is an active low input which has three functons.

Designing with the XACT Development System Priorto the start of configuration, a LOWinputwili delay the
start of the configuration process. An internal circuit
Designing with the Logic Cell Array is similar to using senses the application of power and begins a minimal
conventional MSI elements or gate array cells. A range of time-out cycle. When the time-out and RESET are com-
supported packages, including FutureNet and Schema, plete, the levels of the "M" lines are sampled and configu-
provide schematic capture with elements from a macro ration begins.
library. The XACT development system then translates
the schematic description into partitioned Logic Blocks If RESET is asserted during a configuration, the LCA is re-
and I/O Blocks, based on shared input variables or efficient initialized and will restart the configuration at the termina-
use of flip-flop and combinatorial logic. Design entry can tion of RESET.
also be implemented directly with the XACT development
system using an interactive graphic design editor. The If RESET is asserted after configuration is complete, it will
design information includes both the functional specifica- provide an asynchronous reset of all lOB and CLB storage
tions for each block and a definition of the interconnection elements of the LCA.
networks. Automatic placement and routing is available
for either method of design entry. After routing the inter- RESET can also be used to recover from partial power
connections, various checking stages and processing of failure. See section on Re-program under "Special Con-
that data are performed to insure that the design is correct. figuration Functions."
Design changes may be implemented in minutes. The
design file is used to generate the programming data CCLK
which can be down loaded directly into an LCA in the user's During configuration, Configuration Clock is an output of
target system and operated. The program information an LCAin Master mode or Peripheral mode. LCAs in Slave
maybe usedto program PROM, EPROM or ROM devices, mode use it as a clock input. During a Readback operation
or stored in some other media as needed by the final it is a clock input for the configuration data being shifted
system. out.

2-78
DONE If used as a LOW EPROM enable, it must be programmed
The DONE output is configurable as open drain with or as a HIGH after configuration.
without an internal pull~up resistor. At the completion of
configuration, the circuitry of the LCA becomes active in a XTL1
synchronous order, and DONE may be programmed to This user I/O pin can be used to operate as the output of
occur one cycle before or after that. an amplifier driving an external crystal and bias circuitry.

PROG XTL2
Once configuration is done, a HIGH to LOW transition of This user I/O pin can be used as the input of an amplifier
this pin will cause an initialization of the LCA and start a connected to an external crystal and bias circuitry. The
reconfiguration. I/O Block is left unconfigured. The oscillator configuration
is activated by routing a net from the oscillator buffer
MO symbol output and by the MAKEBITS program.
As Mode 0, this input and M1, M2 are sampled before the
start of configuration to establish the configuration mode to CSO,CS1,CS2,WRT
be used. These four inputs represent a set of signals, three active

•
low and one active high, which are used in the peripheral
RTRIG mode to control configuration data entry. The assertion of
As a Read Trigger, a LOW-to-HIGH input transition, after all four generates a LOW CCLK. In master mode, these
configuration is complete, will initiate a Readback of con- pins become part of the parallel configuration byte
figuration and storage element data by CCLK. This opera- (D4,D3,D2,D1). After configuration is complete, they are
tion may be limited to a single request, or be inhibited al- user-programmed I/O.
together, by selecting the appropriate read back option
when generating the bit stream. RCLK
During Master parallel mode configuration RCLK repre-
M1 sents a "read" of an external dynamic memory device
As Mode 1, this input and MO, M2 are sampled before the (normally not used).
start of configurationto establish the configuration modeto
be used. If Read back is to be used, a 5 kQ resistor should DO-D7
be used to define mode level inputs. This set of 8 pins represent the parallel configuration byte
for the parallel Master mode. After configuration is com-
RDATA plete they are user programmed I/O pin.
As an active low Read Data, after configuration is com-
plete, this pin is the output of the readback data. AO-A15
This set of 16 pins present an address output for a
2. User I/O Pins that can have special functions. configuration EPROM during Master parallel mode. After
configuration is complete they are user programmed 110
M2 pin.
As Mode 2, this input has a passive pullup during configu-
ration. Together with MO and M1 it is sampled before the DIN
start of configuration to establish the configuration mode to
be used. After configuration this pin becomes a user pro-
grammable I/O pin.
°
This user I/O pin is used as serial Data input during Slave
or Master Serial configuration. This pin is Data input in
Master or Peripheral configuration mode.

HDC DOUT
High During Configuration is held at a HIGH level by the This user I/O pin is used during configuration to output
LCA until after configuration. It is available as a control serial configuration data for daisy-chained slaves' Data In.
output indicating that configuration is not yet completed.
After configuration this pin is a user I/O pin. 3. Unrestricted User I/O Pins.

LDC I/O
Low During Configuration is held at a LOW level by the A pin which may be programmed by the user to be Input
LCA until after configuration. It is available as a control and/or Output pin following configuration. Some of these
output indicating that configuration is not yet completed. It pins present a high impedance pull-up (see next page) or
is particularly useful in Master mode as a LOW enable for perform other functions before configuration is complete
an EPROM. After configuration this pin is a user I/O pin. (see above).

2-79
XC2064/2018 Logic Cell Array

CONFIGURATION MODE: <M2:M1 :MO>

USER

~r,~';. PE~\~~~~l I ,.- <l~;~O~I-, ,·-:to:ih-' ~~p P~C PO;:A

OPERATION

, I
~
AS (0)

...!i .JQL

15

'(HIGHI MO (HIGH)
HIQ> .
MO~
~~~
=
... ~~.
I/O
LDC .OW
K4

it
«HIGH»

D6 ... :.~ * ~
K8 I/O

• OS21~
. .........:..!:e.

.~

37
~
110~

.J:!
E10
I/O

C10
qO) )11
~ Llli't~.
-""-
A 62 \10

I/O

«HIGH» IS HIGH IMPEDANCE WITH A 20-50 KO INTERNAL PULL-UP DURING CONFIGURATION

1104 28

Table 2a. XC2064 Pin Assignments

A PLCC in a "PGA-Footprint" socket has a different signal pinout than a PGA device.

2-80
 I 'MODE, <M2,Ml,MO> USER

M~~~~O~ER I ~y,~; I PE~:~~~~AL I MAS<~~,~~'GH I M~~~~:OW IpLCC Ip~6c I :~A OPERATION

A1: IO} I A6
3 I A5

;;HiG'<~~ •
A1: IO}
10}
4
5
"4
, B4 '"
"!!!!!' 9 I Al
~ II} 10 12 I B2 l'WImWII

,~< i», 14
15
,. 02
01
, E3 '"
20 I El
21 I F2

20 25 I G2
2. I Fl
~~H}GH>~,
I Hl
"~I!
24 3{) I Kl
I J2
=i~)
'Ml .oW ""I 25 31
MO LOW MO HIGH

2. 34 I K3
, «HIGH» 29 35 L2
LOC (LOW) 30 ,36 L3
1,0

~~~'
I»
33 40 I"
34 41 L5

44
36 45

,,«HIGH»,
1,0
39 49 KB
40 150 LO
41 1 51 Ll0

~
4315: Lll
'Ill 44 54 (10
0) 45. ,Jl0

~>

!Hl
1,0
49 '10

I
rllh' '"~I, 51 G9

55 I 6.
~; ~~~" I 69 1,0

DC 59 73 :10
LK CCLJ«O) 60 I

A2 63 \10
AS 64 AO

.~~~I~B~; 1,0

! .2

«HIGH» IS HIGH IMPEDANCE WITH A 20-50 Kn INTERNAL PULl·UP DURING CONFIGURATJON

1104 29

Table 2b, XC2018 Pin Assignments

2-81
XC206412018 Logic Cell Array

PARAMETRICS

Absolute Maximum Ratings Units

Vee Supply voltage relative to GN D -0.5 to 7.0 V

VIN Input voltage with respect to GND -0.5 to Vee + 0.5 V

VTS Voltage applied to three-state output -0.5 to Vee + 0.5 V

TSTG Storage temperature (ambient) -65 to +150 °C

TSOL Maximum soldering temperature (10 sec @ 1/16 in.) +260 °C

'Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only. and functional operation of the device at these or any other
conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure
to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Recommended Operating Conditions Min Max Units

Vee Supply voltage relative to GN D Commercial DoC to 70°C 4.75 5.25 V

Supply voltage relative to GND Industrial -40°C to 85°C 4.5 5.5 V

Supply voltage relative to GN D Military -55°C to 125°C 4.5 5.5 V

VIHT High-level input voltage - TTL configuration 2.0 Vee V

VILT Low-level input voltage - TTL configuration 0 0.8 V

VI He High-level input voltage - CMOS configuration .7 Vee Vee V

VILe Low-level input voltage - CMOS configuration 0 .2 Vee V

2-82
Electrical Characteristics Over Operating Conditions Min Max Units

VOH High-level output voltage (@ IOH = -4.0 ma Vee min) Commercial 3.86 V

VOL Low-level output voltage (@ IOL = 4.0 ma Vee min) 0.32 V

VOH High-level output voltage (@ IOH = -4.0 ma Vee) Industrial 3.76 V

VOL Low-level output voltage (@ IOL = 4.0 ma Vee) 0.37 V

VOH

VOL
High-level output voltage (@IOH

LOW-level output voltage (@ IOH

= -4.0 ma Vee)
= 4.0 ma Vee)
Military 3.7

0.4
V

V
III
leeo Quiescent operating power supply current

CMOS thresholds (@ Vee Max) 5 mA

TTL thresholds (@ Vee Max) 10 mA

leePD Power-down supply current (@ Vee = 5.0 V) 0.5 mA

IlL Leakage Current Commercial/Industrial Temperature -10 +10 ~

Leakage Current Military -55°C to 125°C -100 +100 ~

CIN Input capacitance (sample tested) 10 pF

2-83
XC2064120HI Logic Cell Array

CLB SWITCHING CHARACTERISTICS

INPUT (A,B,C,D)
x x
--0 TllO~
OUTPUT (X,V)
(COMBINATORIAL) XX
CD
OUTPUT (X ,V)
(TRANSPARENT LATCH)
TITO

xXI
--0 TICK o TCKI4

CLOCK(K)

--0 Tlcc CD Tccl -

CLOCK (C)
7
-0 TICI (DTCII -

CLOCK (G) !+-- G) TCKO--to

@ Tcco--to

@TCIO-

OUTPUT (VIA FF)

XX
SET/RESET DIRECT (A,D)
tI @ TRIO

SET/RESET DIRECT (F,G)

-k @
=-1-----
TRlO

CLOCK (ANY SOURCE)

_
fr.=:-@
_ _..J TCH @ TCl

1104 30

2-84
ClB SWITCHING GUIDELINES (Continued)

Speed Grade -33 -50 -70 -100 Units

Description Symbol Min Max Min Max Min Max Min Max

Logic Input Combinatorial 1 TllO 20 15 10 7.5 ns

to Output Transparent latch 2 TITO 25 20 14 10 ns

•
Additional for Q
through F or G to out ToLO 13 8 6 6 ns

K Clock To output 9 TCKO 20 15 10 7 ns

Logic-input setup 3 TICK 12 8 7 6 ns
Logic-input hold 4 TCKI 0 0 0 0 ns

CClock To output 10 Tcco 25 19 13 9 ns

Logic-input setup 5 Tlcc 12 9 6 5 ns
Logic-input hold 6 Tcci 6 0 0 0 ns

Logic Input To output 11 TClo 37 27 20 13 ns

to G Clock Logic-input setup 7 Tici 6 4 3 2 ns
LogiC-input hold 8 TCII 9 5 4 3 ns

Set/Reset direct Input A or D to out 12 TRIO 25 22 16 10 ns

Through F or G to out 13 TRlo 37 28 21 14 ns
Master Reset pin to out TMRO 35 25 20 17 ns
Separation of set/reset TRs 17 9 7 5" ns
Set/Reset pulse-width TRPW 12 9 7 5" ns

Flip-flop Toggle Q through F to flip-flop FClK 33 50 70 100" MHz

rate

Clock Clock High 14 TCH 12 8 7 6 ns

Clock Low 15 TCl 12 8 7 6 ns

Notes: 1. All switching characteristics apply to all valid combinations of process, temperature and supply with a
nominal chip power dissipation of 250 mW.
" These parameters are for clock pulses generated within a CLB. For an externally generated pulse, derate
these paramenters by 20%.

2-85
XC2064/2018 Logic Cell Array

108 SWITCHING CHARACTERISTIC GUIDELINES

PAD
(PACKAGE PIN) (IN) =m (OUT) XX)
0 Top:/
OUTPUT SIGNAL
X
f4- 0TpID~ 0- TTHZ j.-
INPUT
(DIRECT) '!XX -, THREE-S
®TpL G)TLP
r--
(1/0
L
CLOCK) ri } T
-18 LW
t

INPUT
(REGISTERED)
--- XX ®TLlr,:
\ \<-
f4- CD TAl'" (]) TA c

1104 31

Speed Grade -33 -50 -70 -100 Units

----
Description Symbol Min Max Min Max Min Max Min Max

Pad To input (direct) 1 TPID 12 8 6 4 ns

(package pin)

I/O Clock To input (storage) 5 Tu 20 15 11 8 ns

To pad-input setup 2 TpL 12 8 6 4 ns
To pad-input hold 3 TLP 0 0 0 0 ns
Pulse width 4 TLw 12 9 7 5' ns
Frequency 33 50 70 100' MHz

Output To pad (output enabled) 8 Top 15 12 9 7 ns

Three-state To pad begin hi-Z 9 TTHZ 25 20 15 11 ns

To pad end hi-Z 10 TTON 25 20 15 13 ns

RESET To input (storage) 6 TRI 40 30 25 17 ns

To input clock 7 TRC 35 25 20 14 ns

Note: Timing is measured at O.S vee levels with SOpF output load.
• These parameters are for clock pulses generated within an LeA. For an externally applied clock, derate these
paramenters by 20%.

2-86
GENERAL LCA SWITCHING CHARACTERISTICS

__--II
~-r----j-~ @TpH
PWRDWN
@TpS
r------------------------~----~_;\ Ir~t~~~------------
Vee (VALID)
_ _ _ _ _oJ.
/ \_ .IF VpD

__ n t (CV™RWJc-

MO/M1/M2

DONE/PROG
(1/0)

USER 1/0

J=@
~0TPGW=r

------~-------,~ 'r----------------------------
USER STATE ~'-IN_IT_IA_l_IZA_T_IO_N_S_T_A_TE_________________
TCLH t@TCLL=1_ _
•
CLOCK

1104 32

Speed Grade -33 -50 -70 -100 Units

Description Symbol Min Max Min Max Min Max Min Max

RESEF M2, M 1, MO setup 2 TMR 60 60 60 60 ns

M2, M1, MO hold 3 TRM 60 60 60 60 ns
Width-FF Reset 4 TMRW 150 150 150 150 ns
High before RESETS 5 TRH 6 6 6 6 JlS
Device Reset 5 6 TDRRW 6 6 6 6 JlS

DONEIPROG Progam width (low) 7 TpGW 6 6 6 6 JlS

Initialization 8 TpGI 7 7 7 7 Jls
Device Reset 5 9 TDRDW 6 6 6 6 Jls

CLOCK Clock (high) 10 TClH 12 8 7 5 ns

Clock (low) 11 TCll 12 8 7 5 ns

PWR DWN4 Setup to Vcc 12 Tps 0 0 0 0 ns

Hold from Vee 13 TPH 0 0 0 0 ns
Power Down VPD 2.0 2.0 2.0 2.0 V

Notes: 1. Vee must rise from 2.0 Volts to Vee minimum in less than 10 ms for master mode.
2. RESET timing relative to power-on and valid mode lines (MO, Ml, M2) is relevant
only when RESET is used to delay configuration.
3. Minimum CLOCK widths for the auxiliary buffer are 1.25 times the TClH, TClL.
4. PWR OWN must be inactive until alter initialization state is complete.
5. After RESET is high, RESET = DiP = LOW for 61ls will abort to CLEAR.

2-87
XC206412018 Logic Cell Array

MASTER MODE PROGRAMMING SWITCHING CHARACTERISTICS

Ao-A15
(OUTPUT)
XXXXXXX ,,_ _ _ _ _ _ _ _ _ _ _ _- - J .................."-;-"................... ' - -_ _ _-

00-07

RCLI<
(OUTPUT)
14------ ® TRCl--------rI---

CCLI<
(OUTPUT)

DOUT
(OUTPUT)
BYTE n-1

1104 33

Speed Grade -33 -50 -70 -100 Units

Description Symbol Min Max Min Max Min Max Min Max

RCLK From address invalid 1 TARC a a a a ns

, To address valid 2 TRAC 200 200 200 200 ns
To data setlJp 3 TDRC 60 60 60 60 ns
To data hold 4 TRCO a a a a ns
RCLK high 5 TRCH 600 600 600 600 ns
RCLK low 6 TRCL 4.0 4.0 4.0 4.0 I1s

Notes: 1. CCLK and DOUr timing are the same as for slave mode.
2. At power-up, VCC must rise from 2.0 V to Vcc min. in less than 10 ms.

This timing diagram shows that the EPROM requirements are extremely relaxed: EPROM access time can be longer than
4000 ns, EPROM data output has flo hold time requirement

2-88
 E:XIUNX

PERIPHERAL MODE PROGRAMMING SWITCHING CHARACTERISTICS

CSO

CS2

CCLK(2)
(OUTPUT)

DIN

OOUT(2)
(OUTPUT)

1104 34

Speed Grade -33 -50 -70 -100 Units

..
Description Symbol Min Max Min Max Min Max Min Max

Controls 1 Active (last active 1 TCA 0.25 5.0 0.25 5.0 0.25 5.0 0.25 5.0 J.l.S
(CSO, CS1, input to firstinactive)
CS2, WRT)
Inactive (first inactive 2 TCI 0.25 0.25 0.25 0.25 J.l.s
input to last active)
CCLK2 3 Tccc 75 75 75. 75 ns
DIN setup 4 Toc 50 50 50 50 ns
DIN hold 5 Tco 0 0 0 0 ns

Notes: 1. Peripheral mode timing determined from last control signal of the logical ANDel (CSQ, ~, CS2. WRT)
. to transition to active or inactive state.
2: CCLK and DOUT timing are the same as ·for slave mode.
3. Configuration must be. delayed at least 40 ms after Vee mil).

2-89
XC206412018 Logic Cell Array

SLAVE MODE PROGRAMMING SWITCHING CHARACTERISTICS

DIN ZXX BITN BITN+1

~ CD TDCC .... ~@TCCD @TCCL

CCLK
GTCCH ®TCCO~
DOUT
(OUTPUT) BITN-1 xxx '------
BITN
1104 35

Speed Grade -33 -50 -70 -100 Units

Description Symbol Min Max Min Max Min Max Min Max

CCLK To DOUT 3 Tcco 65 65 65 65 ns

DIN setup 1 TDCC 10 10 10 10 ns
DIN hold 2 Tcco 40 40 40 40 ns
High time 4 TCCH 0.25 0.25 0.25 0.25 Ils
Low time 5 TccL 0.25 5.0 0.25 5.0 0.25 5.0 0.25 5.0 Ils
Frequency Fcc 2 2 2 2 MHz

Note: Configuration must be delayed at least 40 ms after Vcc min.

PROGRAM READBACK SWITCHING CHARACTERISTICS

DONE/PROG
(OUTPUT)
~--~------------------------------------
CD TDRT I+-~­
Ir-~~---,br,,------------------
RTRIG

CCLK(1)

RDATA VALID
(OUTPUT)

1104 36
-
Speed Grade -33 -50 -70 -100 Units

Description Symbol Min Max Min Max Min Max Min Max
--
RTRIG PROG setup 1 TORT 300 300 300 300 ns
RTRIG high 2 TRTH 250 250 250 250 ns

CCLK RTRIG setup 3 TRTCC 100 100 100 100 ns

RDATAdelay 4 TCCRO 100 100 100 100 ns

Notes: 1. CCLK and DOUT timing are the same as for slave mode.
2. DONE/PROG outputlinput must be HIGH (device programmed) prior to a positive transition of RTRIG (MO).

2-90
 Component Selection,
Ordering Information
& Physical Dimensions

XC2064

•
XC2018

XC3020

XC3030

XC3042

XC3064

XC3090

1972 01

XC1736-PD8C Plastic 8 Pin, Mini-DIP -40°C to 85°C COMPATIBLE PACKAGE OPTIONS

XC1736-CD8M Ceramic 8 Pin, Mini-DIP -55°C to 125°C
A range of Xilinx LCA devices is available in identical
LCA Temperature Options packages with identical pin-outs. A design can thus be
Symbol Description Temperature started with one device, then migrated to a larger or
C Commercial O°Clo 70°C smaller chip while retaining the original footprint and
I Industrial -40°C to 85°C PC-board layout.
M Military -55°C to 125°C Examples: PLCC 68: 2064-2018-3020-3030
B Military MIL-STD-883, Class B PLCC84: 2018-3020-3030-3042
PGA 84: 2018-3020-3030-3042
POFP 100: 3020-3030-3042
COFP100: 3020-3030-3042
ORDERING INFORMATION PGA 132: 3042-3064
Example:

0..""" =:1... j TTL

XC2064-70PC68C

,~,.
Range
••"
Note, however, that the XC2000 and XC3000 families
differ in the position of XTL 1 as well as three parallel
address bits (6, 7 and 11) and most of the data pins used
in parallel master mode.
Toggle Number of Pins XC2018 and XC3020 are not available in PGA68, since
Rate the PGA84 is the same size and offers more I/O.

Package Type Note that a PLCC in a socket with PGA footprint generates
a printed circuit board pin-out differentfrom a PGA device.
1972

2-91
XC2064/2018 Logic Cell Array

PIN 1

o.~~~~nnnnnn~l,
.L-

1-1-
2.440±.025 _ _ _ _ _ _ _ _ _ --..J

,r:=r
F'
... r
:'i
,,~~ ~
f 1\\
'"'"'''' 1 11'-·" ""
NOT DRAWN TO SCALE

1104 39

48-Pin Plastic DIP Package

PIN1~

-.lI-
.040 ± .020 2.400± .024 •I .100+025

.12....L---.-;M":OO~~ <t. .045 ± .010 .018 ± .002

1104 40
DIMENSIONS IN INCHES
NOT DRAWN TO SCALE

48-Pin Ceramic DIP Package

2-92
 PIN Np~~ ~O. 1 IDENTIFIER
9

PWRDWN

Vee Vee

PIN SPACING
.050 TYPICAL

~~~~TC~'9054~±r.0~".~
.990±.005
DONE
RESET

•
1104 41

68-Pin PLCC Package

~--- 1.100 SQ ±.012

1
DIMENSIONS ARE IN INCHES

NOTE: INDEX PI~~~~E~~ED TO PIN C2.

MAY NOT BE
ELECTRICALLY
1104 42

68-Pin PGA Package

2-93
XC2064/2018 Logic Cell Array

.045
x 45° " ' " 11
LL
1
PIN NO.1 IDENTIFIER

75
.045

PWRDWN CCLK P
DOUT/IO P
~
P

1.190 1.154
±.005 ±.004 Vee Vee

PIN SPACING
.050 TYPICAL

M1 DONE
MO RESET .028 ~:::j:=h==*

~r33_1.154±.0041~53"!1
lr-.~f---------1.190±.005,------~--·
ClUUUClUU

DIMENSIONS ARE IN INCHES

1104 43
E> JA = 30--35 °CIW
84-Pin PLCC Package

1
f<.-------1.10Ot.012 5QI--------->l'1 I-' .100 TYP
1.oo0:t.010

.100
~ I" rhffi ..u. TVP

L ..L
V '-
1:'1 !"
'-
("t\ !" ;t .~
'-V'-V
1
I"

1.1:
'-
G ..L ("
1'- '-
1.000
1'-I-' \ '- '- ±.O10

1. ("
1'- '-
INDEX PIN
I-' I-' '-
:'P \0\:08 MAX 1'l1.

'-f-' '-
..L /1" '- f-' '-
~
'-

BL D...L ..L ~
\..
It--. r:\.. £. ..L ..G::::,.£, D...L
'- \.. '-'
.LA ..L 1. 1. 1. r::-. t\
T ..'- ..'-1::. " "I-' " '- "V '-J

DIMENSIONS ARE IN INCHES ~ !.-'050 :6~2DlA

±.010 .
1

NQTE: INDEX PIN MAY OR MAY NOT BE

10 11

ELECTRICALLY CONNECTED TO PIN C2.

1104 44

84-Pin PGA Package

2-94
 Military Logic CelfMArrays

XC2018B,XC3020B,XC3090B Product Specifications

INTRODUCTION Surface Mount Through Hole

Total Ceramic User Ceramic User
Xilinx introduced the first field programmable gate array Device 1/0 QFP 1/0 PGA 1/0
(FPGA) in 1985. The development of the PGA was the
XC2018 74 CPGA 84 74
result of a number of technical breakthroughs and truly
XC3020 64 COFP 100 64 CPGA 84 64
represents the latest in advanced technology for micro- XC3030 80 COFP 100 80 CPGA 84 74
electronic applications. Due to its density and the conven-

•
XC3042 96 COFP 100 82 CPGA 132 96
ience of user programmability, the Logic Cell™ Array is an XC3064 120 COFP 164 120 CPGA 132 110
important new alternative in the ASIC market. Xilinx XC3090 144 COFP 164 142 CPGA 175 144
continues to concentrate its resources exclusively on
expanding its growing family of programmable gate arrays
and associated development systems. See the Xilinx
STANDARD MILITARY DRAWINGS (SMD)
Programmable Gate Array Data Book for a complete
description of the architecture of both the 2000 and 3000
The Standard Military Drawing program (SMD) is a pro-
series arrays.
gram initiated by the Federal government to simplify the
procurement of Integrated Microcircuits (especially the
MIL·STD-883 CLASS B INTRODUCED
more advanced technologies) by military contractors. The
Defense Electronics Supply Center (DESC) issues the
Xilinx continues its leadership in field programmable gate
SMD that is consistent with the Xilinx military product
arrays (FPGA) by announcing the first military qualified
specification and test conditions. DESC assigns an SMD
FPGA's. The 2018B and the 3020B were introduced in the
specification number and releases the drawing. This
first quarter of 1989. The balance olthe Xilinx 3000 series
drawing is then availble for use by all departments and
family will be available during 1989.
agencies of the Department of Defense. The Xilinx device
can then be easily procured by a military contractor by
Logic Config· User Program specifying the SMD# instead of the Xilinx part number.
Capacity urable II0s Data This eliminates the need for a separate Source Control
(usable Logic (bits)
Drawing (SCD) and greatly reduces paperwork.
Device gates) Blocks

XC2018B 1800 100 74 17878 DESC has assigned the Xilinx XC2018-50PG84B device
XC3020B 2000 64 64 14779 SMD# 5962-88638. SMD numbers are under develop-
XC3030B 3000 100 80 22176 ment by DESC for other Xilinx devices. Contact your Xilinx
XC3042B 4200 144 96 30784 representative for more information.
XC3064B 6400 224 120 46064
XC3090B 9000 320 144 64160 LCA IDEAL FOR MILITARY APPLICATIONS

MILITARY PACKAGING Field programmable gate arrays are taking market share
from mask gate arrays in the commercial market are
Xilinx offers two military packaging alternatives. In addi- expected to be even more successful in the military mar-
tion to the industry standard ceramic pin grid array (CPGA) ket. Approximately 50% of all logic sales in the U.S.
packages we offer a ceramic quad flat package (CQFP) military market are ASIC's today. That number is expected
that meets the JEDEC standard outline drawing #MO-082. to grow to 70% by 1993.. FPGA's offer lower costs and
This CQFP has 25 mil pin-to-pin spacing. It is shipped with more flexibility than mask gate arrays.
the leads unfonned allowing selection of cavity up or cavity
down and lead forming at the point of board assembly for The LCA is especially suited to military ASIC applications.
better contact. With a FPGA one specification can be written to cover

2-95
Military Logic Cell Arrays

multiple applications. Xilinx programmable gate arrays • Standard Product

are "configured" by downloading software to the part - no - No overrun charges
fuses are blown. There is no requirement for post-pro- - Simplified product qualification.
gramming testing for fault verification. The device is never - No test vectors to write
obsolete because it can be reprogrammed many times. - Simplified documentation (SMD)

Because Xilinx FPGA's are standard parts, they can be Reliability

stocked in inventory at Xilinx, at Xilinx distributors or at the
user site. One part can be stocked for multiple applica- • Standard Product
tions, minimizing inventory costs. Another benefit of being - Reliability of hi-volume memory product
a standard product is the inherent high reliability of a high
volume memory product rather than a low volume custom • Fully tested by Xilinx
circuit. Non-recurring engineering costs (NRE) are never - Fault coverage assured by vendor
required for a FPGA thereby providing cost effective
solutions in military volumes and allowing very inexpen- Security
sive design iterations.
• No design information needed by manufacturer
For maximum security the configuration data may be - Secure design process. Design data held to
"down-loaded" from a remote site thereby eliminating the vendor at user site.
potential of tampering with the configuration data locally.
The FPGA can be made non-volatile in this instance with • Remote configuration
the addition of a small battery backup. - Ensures secure design data capability

One of the most effective advantages of the Xilinx FPGA Flexibility

is the ability to reconfigure some or all of the device while
it remains in the circuit. This opens up entirely new • Standard product
possibilities allowing the same gates to be used by differ- - An ASIC where one spec can be used for multiple
ent functions at different times. applications
- An ASIC stocked by distribution'
IMPORTANT BENEFITS FOR MILITARY DESIGNS
• Reprogrammable
Cost Containment - Logic can be changed "on the fly"

• No NRE • No FAB turnaround

- Very cost effective in military volumes - Design changes in minutes
- Low cost design iterations

2-96
MIL-STD-883 CLASS B COMPLIANCE MIL-STD-883 CLASS B-METHOD 5005 QUALITY
CONFORMANCE INSPECTION (QCI) TESTING
Xilinx is now serving military customers in accordance with
MIL-STD-883 Class 8 paragraph 1.2.1 together with the Every lot of devices shipped to the requirements of
attendant requirements of M IL-M-38S1 O. This includes full MIL-STD-883C is required to be qualified by four kinds of
compliance with all processing requirements of Method Quality Conformance Inspection (QCI) Tests. The QCI
S004 and all Quality Conformance Inspection (QCI) requirements specified by the Defense Electronics Supply
requirements of Method SOOS (Groups A,B,C,D). Center (DESC) undergo regular revisions. Xilinx rigor-
ously incorporates these revisions into our QCI testing in
MIL-M-38510 (as invoked by MIL-STD-883) conformance with the requirements of MIL-STD-883C.
Military Specification Microcircuits-General These are:
Specification (describes the design, processing and as-
sembly workmanship guidelines) Group A-Electrical tests done to data sheet limits at all
three temperatures of the military temperature range,
MIL-STD-883 -SsoC to +12SoC. These are performed on a sample from
Military Standards-Test Methods and Procedures for the same lot being shipped.
Microelectronics (delineates the detailed testing and in-
spection methods for military integrated circuits) Group B-Mechanical tests performed on a sample of •
devices of the same device/package type assembled
MIL-STD-883 Class B-Method 5004 Processing Flow within the same 6 week widow of the lot being shipped.
This group consists of upto 8 subgroups including physical
dimensions, mark permanency, solderability, internal vis-
METHOD CONDo ual/mechanical, bond strength, internal water vapor con-
FULL TRACEABILITY tent, fine & gross leak, and ESD sensitivity.

Group c-Packagerelated reliability tests performed on

XILINX SPECIFICATION
a sample of devices made with die from the same 1 year
window. This group consists of up to 2 subgroups includ-
2010/B ing (1) life testing (1000 hr at 125°C) and (2) temperature
cycling, constant acceleration, fine & gross leak, and a
visual examination.
10101C

Group D-Package related reliability tests performed on

2001/E
a sample of devices made in the same package within the
same 1 year window. This group consists of up to 8 sub-
groups: physical dimensions; lead integrity and seal; ther-
1014 mal shockltemperature cycling/moisture resistance/seal/
visual; mechanical shock vibration (variable frequency)/
constant acceleration/seal/visual; salt atmosphere/seal/
250(;
visual; internal water-vapor content; adhesion of lead
finish; lid torque.
1015

250(;

55°C. 25°C. +1250(;

2009

5005

1637 01

2-97
Military Logic Cell Arrays

2-98
 XC20188
Military Logic Celi™Array

Product Specification. See Note 1.

FEATURES Part Logic Config- User Config-

Number Capacity urable I/O's uration
• MIL-ST0-883 Class B Processing. (usable Logic Program
Complies with paragraph 1.2.1 gates) Blocks (bits)
• User-programmable gate array
XC2018 1800 100 74 17878
• Low power CMOS static memory technology

•
• Standard product. Completely tested at factory
• Oesign changes made in minutes
in internal static memory cells. On-chip logic provides for
Complete user control for design cycle. automatic loading of configuration data at power-up or on
Secure design process command. The program data can reside in an EEPROM,
• Complete PC or workstation based EPROM or ROM on the circuit board oron a floppy disk or
development system hard disk.
- Schematic entry
- Auto Place/ Route (OS23) Several methods of automatically loading the required
- Oesign Editor (OS21) data are designed into the Logic Cell Array and are
- Logic & Timing Simulator (OS22) determined by logic levels applied to mode selection pins
- XACTOR In-circuit Verifier (OS24) at configuration time. The form of the data may be either
serial or parallel, depending on the configuration mode.
The programming data are independent of the configura-
DESCRIPTION tion mode selected.

The Logic Cell™ Array (LCA) is a high density CMOS The XACT development system allows the user to define
programmable gate array. Its patented array architecture the logic functions of the device. Schematic capture is
consists of three type of configurable elements: Input! available for design entry, while logic and timing simula-
Output Blocks, Configurable Logic Blocks and Intercon- tion, and in-circuit debugging are available for design
nect. The designer can define individual 110 blocks for verification. XACT is used to compile the data pattern
interface to external circuitry, define logic blocks to imple- which represents the configuration program. This data
ment logic functions and define interconnection networks can then be converted to a PROM programmer format file
to compose larger scale logic functions. to create the configuration program storage.

The Logic Cell Array's logic functions and interconnec- See the XC2018 Commercial datasheet for a full descrip-
tions are determined by the configuration program stored tion.

ORDERING INFORMATION
XC2018 - 50PG84B

I I 1 - B~MIL-STD·883,CLASS B, FULLYCOMPUANT

33 (33 MHz TOGGLE)

50 (SO MHz TOGGLE)
~ ~ ~CERAMIC PG
84-LEAD
PIN GRID ARRAY PACKAGE.

1637 02

TSCOD26 Rev:06

2-99
XC201 BB Military logic Cell Array

PIN ASSIGNMENTS

USER
OPERATION

10

10

va

va

va

10

TSC0026 Rev:06 «HIGH» IS HIGH IMPEDANCE WITH A 20-50 KO INTERNAL PULL-UP DURING CONFIGURATION 163703

2-100
 CASE OUTLINE DRAWING

Conforms to MIL-M-38S10 Appendix C, Case P-8C.

1.000±.O10

'I
1.100±.012SO
I---- .100TVP

~
\..1--' \..
t"\ ~ ~ r, :'I TYPIf:
.100

\..
("r, ~ t\ (" r, ~ t\
\..
(" t\~
\..

'-
f/
r, ("t\
f/
:'I (" t\ :'Ill
'" ~

r, r: ~ r, t"\
I--' \.. \.. f/

f/ \..1--' I--'
G
\..
t"\ r: 1.000
f/ \.. I--' I--' '- i.Ol0

{h~ tlLl\
f/ \.. \..

•
INDEX PIN
r: :P ,O\'~OB MAX r:
f/ \..
f/ \,.
/ I--' '-
("1:'\ c\
'- \,.

(' (' ~ r:'\ ~

'-"
6'~ ~ r:'\
/"L:. TA \,. \,.
_'-./
PIN NO.1 INDEX, / --Ir--!.- OSO .01.
1:.010 ±.OO2DIA
10
DIMENSIONS ARE IN INCHES
NOTE: INDEX PIN MAY OR MAY NOT BE
ELECTRICALLY CONNECTED TO PIN C2.

XC2018: 84-Pin PGA Package 1637 04

STATIC BURN-IN CIRCUITS

S.0±.2SV

30 8.06k 1.15k 1.51<

1.31< lID 1.3k 1.51<

B2 A11
C2 Cl0
Bl B11
Cl C11
02 010
01 011
E3 E9
E2 El0
El E11
F2 F11
F3 XC2018 F9
VCC vee
G3 PGA84 G9
Gl G11
715
G2 Gl0
Fl FlO
Hl H11
H2 Hl0
Jl J11
Kl K11
J2 Jl0
DONEIPROG
Ll Kl0
RESET 1-"'''-1---+--,
NOTES:
1. UNLESS OTHERWISE SPECIFIED, ALL
RESISTORS ARE METAL FILM AND ARE
4.99k RATED FOR 118 WATT AT 1500C WITH A
BUILD TOLERANCE OF 1% AND A 5%
TOLERANCE OVER LI FE.
III CAPACITOR HAS 10% TOLERANCE,
50 V RATING WITH AN X7R
lk TEMPERATURE CHARACTERISTIC.
III 30 "RESISTOR IS METAL OXIDE AND
IS RATED FOR 1 WAT 150"C WITH A
TOLERANCE OF 5%.

1637 05

TSC0026 Rev:06

2-101
XC20188 Military Logic Cell Array

XC2018B Test Specification

Absolute Maximum Ratings Limits Units

Vee Supply voltage relative to GND -0.5 to 7.0 V

VIN Input voltage with respect to GND -0.5 to Vee + 0.5 V

VTS Voltage applied to three-state output -0.5 to Vee + 0.5 V

TSTG Storage temperature (ambient) -65 to +150 °C

TSOl Maximum soldering temperature (10 sec@ 1/16 in.) +260 °C
TJ Maximum junction temperature +150 °C
1637 Thl 04
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to
Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Conditions
-55°C ~ Te ~ +125°C Group A Limits
Test Symbol Vee = 5.0 V ±10% Subgroups Min Max Units

High Level Output Voltage VOH Vee = 4.5 V, IOH = -4.0 mA 1,2,3 3.7 V
Low Level Output Voltage VOL Vee = 5.5 V, IOl = 4.0 mA 1,2,3 0.4 V
Quiescent Operating leeo CMOS Inputs, Yin = Vee = 5.5 V 1,2,3 10 mA
Power Supply Current TIL Inputs, Yin = Vee = 5.5 V 1,2,3 15 mA
Power-Down Supply Current leePD Yin = Vee = 5.5 V, 1,2,3 0.5 mA
PWR DWN =OV
Leakage Current III Vee = 5.5 V, Yin = Vee and 0 V 1,2,3 -10 10 j.tA
Input High Level TIL VIHT Guaranteed Input High 1,2,3 2.0 V
Input Low Level TTL VllT Guaranteed Input Low 1,2,3 0.8 V
Input High Level CMOS VIHe Guaranteed Input High 1,2,3 .7 Vee V
Input Low Level CMOS Vile Guaranteed Input Low 1,2,3 .2 Vee V

Switching Characteristics, General LCA

DONEIPROG
Program Width (Low) TpGW 4 See Fig. 3 9,10,11 6 j.ts
Initialization TpGI 5 9,10,11 7 j.ts

PWR OWN"
Power Down Supply VPD 1,2,3 3.5 V

1637 Thl 05.

Table 1. Electrical Performance Characteristics

TSC0026 Rev:06

2-102
 Conditions 2018-33 2018-50
-55°C ~ Tc ~ +125°C Group A Limits Limits
Test Sym VCC = 5.0 V ±10% Subgroups Min Max Min Max Units

Switching Characteristics, Peripheral Mode Programming

Controls (CS, WRT)3.4

Last Active Input to First Inactive TCA 1 See Fig. 4 9,10,11 0.5 1.0 0.5 1.0 Ils
First Inactive Input to Last Active TCI 2 9,10,11 0.5 0.5 Ils

CCLKs Tccc 3 9,10,11 75 75 ns

DIN Setup Toe 4 9,10,11 50 50 ns
DIN Hold Tco 5 9,10,11 5 5 ns

Switching Characteristics, Program Readback6

RTRIG Setup TRTH 1 See Fig. 7 9,10,11 250 250 ns

CCLK,
RTRIG Setup TRTCC 2 9,10,11 100 100 ns
RDATA Delay TCCRO 3 9,10,11 100 100 ns

Benchmark Patterns7

TplO + interconnect + 10 (TILO) + TS1 9,10,11 238 178 ns

Top. Measured on 10 cols.
Tplo + interconnect + 10 (TITO) + TS2 9,10,11 288 228 ns
Top. Measured on 10 cols.
Tplo + interconnect + 10 (TQLO) + TS3 9,10,11 410 302 ns
Top. Measured on 10 cols.
Tested on all CLBs with TICK TS4 9,10,11 85 62 ns
+ interconnect.
Tested on all CLBs with Tlcc TS5 9,10,11 66 49 ns
+ interconnect.
Tested on all CLBs with Tici TS6 9,10,11 90 67 ns
+ interconnect.
Tplo + interconnect + 10 (TRIO) + TS7 9,10,11 318 269 ns
Top. Measured on 10 rows.
Tplo + interconnect + TPL + TLI + TS8 9,10,11 274 204 ns
Top. Tested on aI/lOB's.

1637 Tbl 05b

Table 1. Electrical Performance Characteristics (Continued)

TSC0026 Rev:06

2-103
XC2018B Military Logic Cell Array

Conditions 2018-33 2018-50

-55°C ~ Tc ~ +125°C Group A Limits Limits
Test Sym Vcc =5.0 V ±10% Subgroups Min Max Min Max Units

Application Guidelines, Switching, CLB7

Logic Input to Output, TllO 1 See Fig. 1 N/A 20 15 ns

Combinatorial

Transparent Latch TITO 2 N/A 25 20 ns

Additional for Q Through TOlo N/A 13 8 ns
For G to Out

K Clock,
To Output TCKo 9 N/A 20 15 ns
Logic-Input Setup TICK 3 N/A 12 8 ns
Logic-Input Hold TCKI 4 N/A 1 1 ns

C Clock,
To Output Tcco 10 N/A 25 19 ns
Logic- Input Setup TICC 5 N/A 12 9 ns
Logic-Input Hold TCCI 6 N/A 6 1 ns

Logic Input to G Clock,

To Output TClo 11 N/A 37 27 ns
Logic-Input Setup Tici 7 N/A 6 4 ns
Logic-Input Hold TCII 8 N/A 9 5 ns

Set/Reset Direct,
Input A or D to Out TRIO 12 N/A 25 22 ns
Through For G to Out TRlo 13 N/A 37 28 ns
Master Reset Pin to Out TMRo N/A 55 45 ns
Separation of Set/Reset TRs N/A 17 9 ns
Set/Reset Pulse-Width TRPW N/A 12 9 ns

Flip-Flop Toggle Rate, FClK N/A 33 50 MHz

Q Through F to Flip-Flop

Clock HighS TCH 14 N/A 12 8 ns

Clock Lows TCl 15 N/A 12 8 ns

1637 Tbl 05c

Table 1. Electrical Performance Characteristics (Continued)

TSC0026 Rev:06

2-104
 Conditions 2018-33 2018-50
-55°C:.:;; Tc:.:;; +125°C Group A Limits Limits
Test Sym VCC = 5.0 V ±10% Subgroups Min Max Min Max Units

Application Guidelines, Switching, IOB7

Pad (Package Pin) to TPID 1 See Fig. 2 N/A 12 8 ns

Input (Direct)

I/O Clock
To Input (Storage) TLI 5 N/A 20 15 ns
To Pad-Input Setup TpL 2 N/A 12 8 ns
To Pad Input Hold TLP 3 N/A 0 0 ns
Pulse Width TLw 4 N/A 12 9 ns
Frequency N/A 33 50 MHz

Output,
To Pad (Output Enable) Top 8 N/A 15 12 ns

Three-State,
To Pad Begin hi-Z TTHZ 9 N/A 25 20 ns
To Pad End hi-Z TTON 10 N/A 25 20 ns

RESET,
To Input (Storage) TRI 6 N/A 40 30 ns
To Input Clock TRC 7 N/A 35 25 ns

Application Guidelines, Switching, Slave Mode Programming 7

CCLK,
To DOUT Tcco 3 See Fig. 6 N/A 100 100 ns
DIN Setup TDCC 1 N/A 10 10 ns
DIN Hold TCCD 2 N/A 40 40 ns
High Time TCCH 4 N/A 0.5 0.5 JlS
Low Time TccL 5 N/A 0.5 1.0 0.5 1.0 Jls
Frequency Fcc N/A 1 1 MHz

Application Guidelines, Switching, Master Mode Programming 7.-

RCLK,
From Address Invalid TARC 1 See Fig. 5 N/A 0 0 ns
To Address Valid TRAC 2 N/A 200 200 ns
To Data Setup TDRC 3 N/A 60 60 ns
To Data Hold TRCD 4 N/A 0 0 ns
RCLK High TRCH 5 N/A 600 600 ns
RCLK Low TRCL 6 I N/A 4.0 4.0 JlS

Application Guidelines, Switching, General LCA7

RESETlO
M2, M1, MO Setup TMR 1 See Fig. 3 N/A 1 1 JlS
M2, M1, MO Hold TRM 2 N/A 1 1 Jls
Width (Low) TMRW 3 N/A 150 150 ns
1637 Tbl 05d

Table 1. Electrical Performance Characteristics (Continued)

TSC0026 Rev:06

2-105
XC2018B Military Logic Cell Array

INPUT (A,B,C,D)
x x
-CDTILO~
OUTPUT (X,Y)
(COMBINATORIAL) XX
® TITO
OUTPUT (X,Y)
(TRANSPARENT LATCH)
XX~
-G)TICK o TCKI-

CLOCK(K)

- 0 Tlcc I ® Tccl -
CLOCK(C)

- (!) T ICI I ® TclI -

CLOCK (G) f-
I - - @ TCKO -

@Tcco -

@ TclO

OUTPUT (VIA FF)

AIJ
SET/RESET DIRECT (A,D)
{ @ TRIO
I
SET/RESET DIRECT (F,G)
f
CLOCK (ANY SOURCE)
@ TRLO

@TCL =1____
Timing is measured at 0.5 Vee levels with 50 pF minimum output load.

Input signal conditioning: Rise and fall times,; 6 ns, Amplitude = 0 and 3V
1637 06

Figure 1. Switching Characteristics Waveforms, CLB

TSC0026 Rev:06

2-106
 I:XIUNX

PAD
(PACKAGE PIN) _ _oJ
x----.... (IN)

OUTPUT SIGNAL

® TTHZj.-
INPUT
(DIRECT) THREE-STATE

l
(VOCLOCK)

INPUT
(REGISTERED)

163707

Figure 2. Switching Characteristics, lOB

__--II
~r- ~~
Vee (VALID)
-...,.....---1 1 \ / t
,"- __ - : -•_ ' , VPO

MO/M11M2

DONEJPROG
(OUTPUT)

USERVO
J=:? .
--U-S-ER-S-.T~A-TE-"""WO<Xxx\..-I_N-IT~I_A-.L~IZA~_T-_IO~N-_S-:r~A~T_.E-_-_-_-_-_-_-_-_-_-_-_-_""_-_-_-_-

CLOCK .~ \\...-_ _~I

1637 08

Figure 3. General LCA Switching Characteristics

TSCOO26 Rev:06

/2-107
XC20188 Military Logic Cell Array

CSO

CS1

WRT

CS2

CCLK (2)
(OUTPUT)

DIN

DOUT
(OUTPUT)

1637 09

Figure 4. Peripheral Mode Programming Characteristics

A{}-A15 VWWW
(OUTPUT) ~_ _ _ _ _ _ _ _ _ _ _ _ _--'

I+----tof+---~

DO-D7

RCLK
(OUTPUT)

CCLK
(OUTPUT)

DOUT
(OUTPUT)
BYTE n-1

CCLK and DOUT timing are the same as for slave mode.
At power-up, Vee must rise from 2.0 V to Vee min. in less than 10 ms.
1637 10

Figure 5. Master Mode Programming Switching Characteristics

TSC0026 Rev:06

2·108
 DIN zzx: BITN BITN+1

~ CD TDCC"'~ @ TCCD =:j @TCCL

J

CClK ,
GTCCH ®TCCO~
DOUT
(OUTPUT) BITN-1 xxx' - - - - - - - BITN

Configuration must be delayed at least 40 ms after Vcc min.

1637 11

Figure 6. Slave Mode Programming Switching Characteristics

DON ElP ROG

(OUTPUT)
____-L/___________________________________ _
RTRIG II
CCLK(1)

RDATA
(OUTPUT) VALID

1637 12
Figure 7. Program Readback Characteristics

Notes: 1. Xilinx maintains this specification as a controlled document. To comply with the intent of MIL·STD·883, and to assure
that you are using the most recently released device performance parameters, please request a copy of the current
revision of this Table 1 Test Specification from Xilinx.
2. PWR DWN must be active before Vcc goes below specified range, and inactive after Vcc reaches specified range.
3. Peripheral mode timing determined from last control signal of the logical AND of (~, CST, CS2, WRT) to transition
to active or inactive state.
4. Configuration must be delayed at least 40 ms after Vcc min.
5. CCLK and DOUTtiming are the same as for slave mode.
6. Dip must be high before RTRIG goes high.
7. Testing of the Applications Guidelines is modeled after testing specified by MIL·M·3851 0/605. Devices are first 100%
functionally tested. Benchmark patterns are then used to measure the Application Guidelines. Characterization data
are taken at initial device qualification, prior to introduction of significant changes, and at least twice yearly to monitor
correlation between benchmark patters, device performance, XACT software timings, and the data sheet.

fuC
8. Minimum CLOCK widths for the auxiliary buffer are 1.25 times the TClH, TClL.
9. Vcc must rise from 2.0 V to Vcc minimum in less than 10 ms for master
K1% vee
mode.
PAD
10. RESET timing relative to power·on and valid mode lines (MO, M1, M2) is
relevant only when RESET is used to delay configuration.
11. All timings except TTSHZ and TTSON are measured at 1.5 Vcc level with
11K 1%
SOpf MIN GND
50 pF minimum load output. For input signals, rise and fall times are
1637 13
less than 6 ns, with low amplitude = OV, and high = 3V. TTHz is deter·

~.
mined when the output shifts 10% (of the output voltage swing) from
VOL level or VOH level. The following circuit is used:
TTON is measured at 0.5 Vcc level with VIN = 0 for Tri·State to active
high, and VIN = Vcc for Tri·State to active low. The following load circuit
~
50pf
. . I1
MIN
.1K1%
VIN

is used:
1637 14
TSC0026 Rev:06

2-109
XC2018B Military Logic Cell Array

TSC0026 Rev:06

2-110
 XC3020B
Military Logic Celf Array M

Product Specification. See Note 1.

FEATURES Pan Logic Config· User Conflg·

Number Capacity urable I/O's uration
• MIL-ST0-883 Class B Processing. (gates) Logic Program
Complies with paragraph 1.2.1 Blocks (bits)
• User-programmable gate array
XC3020 2000 64 64 14779
• Low power CMOS static memory technology
• Standard product. Completely tested at factory
• Design changes made in minutes
in internal static memory cells. On-chip logic provides for
• Complete user control for design cycle. automatic loading of configuration data at power-up or on
Secure design process command. The program data can reside in an EEPROM,
• Complete PC or workstation based EPROM or ROM on the circuit board or on a floppy disk or
development system hard disk.
- Schematic entry
- Auto Place! Route (OS23) Several methods of automatically loading the required
- Design Editor (OS21) data are designed into the Logic Cell Array and are
- Logic & Timing Simulator (OS22) determined by logic levels applied to mode selection pins
- XACTOR In-circuit Verifier (OS24) at configuration time. The form of the data may be either
serial or parallel, depending on the configuration mode.
The programming data are independent of the configura-
DESCRIPTION tion mode sele91ed.

The Logic Cell™ Array (LCA) is a high density CMOS The XACT development system allows the user to define
programmable gate array. Its patented array architecture the logic functions of the device. Schematic capture is
consists of three type of configurable elements: Input! available for design entry, while logic and timing simula-
Output Blocks, Configurable Logic Blocks and Intercon- tion, and in-circuit debugging are available for design
nect. The designer can define individual I/O blocks for verification. XACT is used to compile the data pattern
interface to external circuitry, define logic blocks to imple- which represents the configuration program. This data
ment logic functions and define interconnection networks can then be converted to a PROM programmer format file
to compose larger scale logic functions. to create the configuration program storage.

The Logic Cell Array's logic functions and interconnec- See the XC3000 Commercial datasheet for a full descrip-
tions are determined by the configuration program stored tion.

ORDERING INFORMATION

XC3020 - 50 PG 84 8

I I I . B= MIL·STD-883. CLASS B. FULLY COMPLIANT

so (SO MHz TOGGLE) _ _ _ _ _...J. PG =CERAMIC PIN GRID ARRAY PACKAGE.

a·HEAD
163715

TSCOO85 Rev:03

2-111
XC3020B Military Logic Cell Array

PIN ASSIGNMENTS

USER
OPERATION

I I

110
110
110
110
110
110

110
110
110
110
110
110
1637 16

_ REPRESENTS A 501<0 TO 100Kn PULL-UP

• INIT IS AN OPEN DRAIN OUTPUT DURING CONFIGURATION
(I) REPRESENTS AN INPUT

TSC0085 Rev:03

2-112
 PIN ASSIGNMENTS (Continued)

PGAPin PGAPln
XC-3020 XC-3020
Number Number
B2 l'WRUfJ K10 l1ESET
C2 TCLKIN-IIO J10 OONE-l'G"
B1 NC K11 07-110
C1 VO J11 XTL 1(OUT)-BCLKIN-IIO
D2 110 H10 06-1/0
D1 110 H11 VO
E3 110 F10 DS-I/O
E2 110 G10 CSO-I/O
E1 110 G11 D4-1/0
F2 110 G9 110
F3 vee F9 vee
G3 110 F11 D3-110
G1 VO E11 CST-IIO
G2 110 E10 D2-1/0
F1 110 E9 1/0
H1
H2
J1
110
110
110
D11
D10
C11
NC
D1-1/0
RDY/lIDS'i'-J1crI(-I/O
II
K1 110 B11 DO-DIN-I/O
J2 M1-JmATA C10 DOUT-I/O
L1 MO-"RTRlG" A11 CCLK
K2 M2-110 B10 AO-WS-I/O
K3 HDC-IIO B9 A1-CS2-I/O
L2 110 A10 A2-1/0
L3 IDC"-IIO M A3-IIO
K4 VO B8 NC
L4 NC AS NC
JS WO B6 A1S-I/O
KS 110 B7 M-IIO
LS NC A7 A14-VO
K6 lNlT-IIO C7 AS-IIO
J6 GND C6 GND
J7 VO A6 A13-IIO
L7 110 AS AS-VO
K7 1/0 BS A12-I/O
L6 110 C5 A7-I/O
L8 110 M NC
K8 110 B4 NC
L9 NC A3 A11-IIO
L10 NC A2 AS-IIO
K9 VO B3 A10-IIO
L11 XTL2(IN)-VO A1 M-I/O
1637 Thl 06

Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-limited.

TSC0085 Rev:03

2-113
XC3020B Military Logic Cell Array

CASE OUTLINE DRAWING

Conforms to MIL-M-3851 0 Appendix C, Case P-SC.

1.000±.O10
1.100±.012 so . - .IOOTYP
.100
("" ("" ffi TYP
'.fJ \. V \.
(""l\ ("" l\ ("" (""l\ (""
'-
(""l\ (""
f/
A:: (" :- -,
'-f/'-
I
I-E~ ~
t'\ ("" t'\

r.
'- V
G
r. 1." r: l\j""
'-
r. 1.000
\. V \. V ±.O10

C\ ("l\ r:t\ ("l\

'-
1-E9-E rr
INDEX PIN
TYP S;'A108 MAX t\

C f".":-..£. f". ("l"\ ("

\.
r. r. I"" /"::\ r.
\. \. \. \. \. \::/\. V \.
-.l ("" /"::\
/L'> TA '- '- -'--"
PIN NO.1 INDEX. / -+Ir--~.050 ±o~g2DIA
±.010 .
10 11
DIMENSIONS ARE IN INCHES
NOTE: INDEX PIN MAY OR MAY NOT BE
ELECTRICAlLY CONNECTED TO PIN C2.

XC3020: 84-Pin PGA Package 1637 17

STATIC BURN-IN CIRCUIT

S.0±'2SV

30 ;:~ B.OSk 1.1Sk 1.5k

1.3k
(1)
1.3k
,Ir ~k ~1hhH~
<m <m<um«uu<mm<m«mm
w "hl~I~I:2lml~I~I8lI~1
Al1
1.3k 1.Sk

-*
"""lif"
T,
PWRDWN 0
z
"
CClK
DOlfT
DIN
C10
Bll

~ ~
T,
Ta
rm-
~
To ~
t-tr,-
"E1
To rm-
fa VCC
XC3020 VCC
If9
To PG84
ef,- ~
T. ~ 715
Y, W
~ ili"j--
T. if,;j-
7 -j';f-
>--t,- ~
7 -j;'6-
=IT: Ml
MO Q
DONE/PROG
RESET
Fa -
~~
0
9 le~
;;"
NOTES:
1. UNLESS OTHERWiSE SPECIFIED, ALL

--=1Q 11~ltlt ~ll~1~ltl~15131~1~l

t
RESISTORS ARE METAL FILM AND ARE
Y...J~Y ..... Y 4.99k RATED FOR 118 WATT AT 1SOa C WITH A
BUILD TOLERANCE OF 1% AND A 5%
TOLERANCE OVER LIFE.
(gJ CAPACITOR HAS 10"10 TOLERANCE,
50 V RATING WITH AN X7R
lk TEMPERATURE CHARACTERISTIC.
[II 30 0 RESISTOR IS METAL OXIDE AND
IS RATED FOR 1 WAT150 D C WITH A
TOLERANCE OF 5%.
.01 J.LF rn 1637 18

TSC0085 Rev:03

2-114
 E:XlUNX
XC3020B Test SjJeclflcatlon

Absolute Maximum Ratings Limits Units

Vee Supply voltage relative to GND -0.5 to 7.0 V

VIN Input voltage with respect to GND -0.5 to Vee + 0.5 V

VTS VoHage applied to three-state output -0.5 to Vee + 0.5 V

TSTG Storage temperature (ambient) -65 to +150 ·C

~~

TSOL Maximum soldering temperature (10 sec@ 1/16 in.) +260 ·C

TJ. Maxi~um junction temperature +150 ·C
1637 Thl07
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device ..These are stress ratings only, and funGlional operation of the device at lhese or any other
conditions beyond those listed under RecommE!nded Operating Conditions, is not implied. Exposure
to, Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Conditions
-55°C ~ Te ~ +125°C Group A Lirnits
Test Symbol Vee;= 5,OV ±10% Subgroups Min Max Units

High Level Output Voltage VOH Vee = 4.5 V,IOH == -4.0 rnA 1,2,3 3.7 V
Low Level Output Voltage VOL Vee = 5.5V, IOL '" 4.0 rnA 1,2,3 0.4 V
Quiescent Operating2 lceo CMOS Mode, Vin = Vee == 5.5 V 1,2,3 1 rnA
Power Supply Current
. TTL Mode, Vin = Vee = 5.5 V 1,2,3 15 rnA
Power-Down Supply Current ICCPD ' Vin = Vee = 5.5 V, 1,2,3 0.5 rnA
PWRDWN=OV
Leakage Current IlL Vee = 5.5 V, Vin = Vee and 0 V 1,2,3 -20 20 ~
Horizontal Long Line IRll Measured as an;average 1,2,3 2.4 rnA
Pull-up Current
Input High Level TTL VIHT Guaranteed Input High 1,2,3 2.0 V
Input Low Level TTL VILT (3uaranteed Input Low 1,,2,3 0.8 V
Input High Level CMOS VIHe Guaranteed Input High 1,2,3 .7 Vee V
Input Low Level CMOS VILe Guaranteed Input Low 1,2,3 .2 Vee V

1637Thloaa

Table 1. Electrical Performance Characteristics

TSCOOS5 Rev:03
XC3020B Military Logic Cell Array

Conditions
-55°C ~ Tc ~ +125°C Group A Limits
Test Sym Vcc = 5.0 V ±10% Subgroups Min Max Units

Switching Characteristics, Gelleral LCA

DONEIPROG
Program Width (low) TpGW 5 See Fig. 1 9,10,11 6 J.Ls
Initialization TpGI 6 9,10,11 7 J.Ls

PWR OWN3
Power Down Supply Vccpo 1,2,3 3.5 V

RESET4
M2,M1,MO Setup TMR 2 9,10,11 1 J.LS
M2,M1,MO Hold TRM 3 9,10,11 1 J.Ls
Width (low) abort TMRW 4 9,10,11 6 J.LS

Switching Characteristics, Peripheral Mode Programming 5

WRTlOW TCA 1 See Fig. 4 9,10,11 0.5 J.Ls

DIN Setup Toc 2 9,10,11 60 ns
DIN Hold Tco 3 9,10,11 0 ns
Ready/Busy TWTRB 4 9,10,11 60 ns

Switching Characteristics, Slave Mode Programming 5

CClK,
To DOUT Tcco 3 See Fig. 5 9,10,11 100 ns
DIN Setup Tocc 1 9,10,11 60 ns
DIN Hold Tcco 2 9,10,11 0 ns
High Time TCCH 4 9,10,11 0.5 J.Ls
low Time TCCl 5 9,10,11 0.5 1.0 J.LS
Frequency Fcc 9,10,11 1 MHz
1637 lbl OBb

Table 1. Electrical Performance Characteristics (Continued)

TSC0085 Rev:03

2-116
 Conditions
-55°C ~ Tc ~ +125°C Group A Limits
Test Sym VCC = 5.0 V ±10% Subgroups Min Max Units

Switching Characteristics, Program Readback 6 ,7

RTRIG Setup TRTH 1 See Fig. 7 9,10,11 250 ns

CCLK,1
RTRIG Setup TRTCC 2 9,10,11 200 ns
RDATA Delay TCCRD 3 9,10,11 100 ns

Benchmark PatternsB

TPID + interconnect + 8 (TllO) + TBl 9,10,11 135 ns

Top. Measured on 8 cols.
TCKO + TICK + TCKI + TB2 Tested on all CLBs 9,10,11 32 ns
interconnect
TCKO + TOlO + TllO + TDICK + TB3 Tested on all CLBs 9,10,11 53 ns
interconnect
TllO + TECCK + interconnect TB4 Tested on all CLBs 9,10,11 35 ns

TOKPO + Tops - TOPF + TPICK TBS Tested on all CLBs 9,10,11 73 ns

TCKO + TOLO + Tpus + TICK + Too One long line pull-up 9,10,11 73 ns
interconnect
TCKO + TOLO + Tpus + TICK + TB7 The other long line pull-up 9,10,11 83 ns
interconnect
TCKO + TOLO + Tlo + TICK + TBB No pull-up, lower long lines 9,10,11 47 ns
interconnect
TCKO + TOLO + Tlo + TICK + TB9 No pull-up, upper long lines 9,10,11 57 ns
interconnect
1637Tb10Bc

Table 1. Electrical Performance Characteristics (Continued)

TSC0085 Rev:03

2-117
XC3020B Military Logic Cell Array

Conditions
-SsoC ~ Tc ~ +12SoC Group A Limits
Test Sym Vcc =S.O V±10% Subgroups Min Max Units

Application Guidelines, Switching, elB8

Combinatorial TllO 1 See Fig. 2 N/A 14 ns
Reset to CLB output TRIO 9 N/A 12 ns
Reset Direct width TRPW 13 N/A 12 ns
Master Reset pin to CLB out TMRO N/A 30 ns

K Clock9
To CLB output TCKO 8 N/A 12 ns
Additional for Q returning TOLO N/A 11 ns
through F or G to CLB out
Logic-input setup TICK 2 N/A 12 ns
Logic-input hold TCKI 3 N/A 0 ns
Data In setup TDICK 4 N/A 8 ns
Data In hold TCKDI S N/A 6 ns
Enable Clock setup TECCK 6 N/A 10 ns
Enable Clock hold TCKEC 7 N/A 0 ns
Clock (high) TCH 11 N/A 9 ns
Clock (low) TCl 12 N/A 9 ns

Flip-flop Toggle Rate FClK N/A SO MHz

Application Guidelines, Switching, Internal Buffers8

Clock Buffer TGCK N/A 9 ns

TBUF
Data to Output Tlo N/A 8 ns
Three-state to Output
Single Pull-up Tpus N/A 34 ns
Pair of Pull-ups TpUF N/A 17 ns

Bidirectional BIDI N/A 6 ns

1637 "fbI oad

Table 1. Electrical Performance Characteristics (Continued)

TSC0085 Rev:03

2-118
 Conditions
-55°C::; Tc::; +125°C Group A Limits
Test Sym Vcc = 5.0 V ±10% Subgroups Min Max Units

Application Guidelines, Switching, IOB8,10

Pad (package pin) See Fig. 3

To inputs TClKIN, BClKIN TplDC N/A 5 ns
To inputs DIRECT IN TplO 3 N/A 9 ns

110 Clock
To 1/0 RI input (FF) TIKRI 4 N/A 11 ns
1/0 pad-input setup TpicK 1 N/A 30 ns
1/0 pad-input hold TIKPI 2 N/A 0 ns
To 110 pad (fast) TOKPo 7 N/A 18 ns
1/0 pad output setup TooK 5 N/A 15 ns
1/0 pad output hold TOKo 5 N/A 0 ns
Clock (high) TIOH 11 N/A 9 ns
Clock (low) Tlol 12 N/A 9 ns

Output
To pad (enabled fast) TOPF 10 N/A 14 ns
To pad (enabled slow) Tops 10 N/A 39 ns

Three-State
To pad begin hi-Z (fast) TTSHZ 9 N/A 12 ns
To pad valid (fast) TTSON 8 N/A 20 ns

Master Reset
To input RI TRRI 13 N/A 35 ns
To output (FF) TRPo 14 N/A 50 ns

Application Guidelines, Switching, Master Parallel Mode Programming 8,11

RClK,
To Address Valid TRAC 1 See Fig.S N/A 0 200 ns
To Data Setup TORc 2 N/A SO ns
To Data Hold TRco 3 N/A 0 ns
RClK High TRCH 4 N/A 600 ns
RClK low TRcl 5 N/A 4.0 f..lS
1637 Tbl OBe

Table 1. Electrical Performance Characteristics (Continued)

TSC0085 Rev:03

2-119
XC3020B Military Logic Cell Array

, . - -_ _ _ ~IIt_--(0TMRW)-------

MO/M1/M2
-f®'~®'~f--------
DONE/PROG
(OUTPUT)
>C®"~=-1

INIT
(OUTPUT)
__J__·C®T
USER STATE
PG1

_ _ _ _ _ _C_l_E_ARlt-ST_A_T_E_ _ _ _ _ _ _ -J/ CONFIGURE

- II .

________________________________________________--4~NOTE3~~______
\'---------/
Vee (VALID) \, r
I t V
'-----.1-,- CCPD

1637 19
Figure 1. General LCA Waveforms

ClB OUTPUT (X,V)

(COMBINATORIAL)

ClB INPUT (A,B,C,D,E)

ClBClOCK

14---- @ TCl --401<"-- @ TCH ~----~

o TDICK
ClBINPUT
(DIRECT IN)
® TECCK
ClBINPUT
(ENABLE CLOCK)

ClBOUTPUT
(FLIP-FLOP)

ClB INPUT
(RESET DIRECT)

ClBOUTPUT
(FLIP-FLOP)
1637 20

Figure 2. CLB Waveforms

TSC0085 Rev:03

2-120
 E:XIUNX

-®-TPID~~[--
VO BLOCK (I)

t CD TpICK--.... ® TIKPI]~-----
110 PAD INPUT

'!"'.t-
110 CLOCK
(IKIOK)
~--- @ T1DL - - - I 4 - - - -

110 BLOCK (RI)

RESET

110 BLOCK (0)

@TOp
110 PAD OUTPUT
(DIRECn
II
VO PAD OUTPUT
------------------~f0) TOKPO
(REGISTERED)

J---rr-®-~-SON----@-~-~,j I
VO PADTS

VO PAD OUTPUT --------~(~ ____________~r__

163721

Figure 3. lOB Waveforms

I ,
CS11CSO \ /
CS2
__---17 \~ __________________~i_______
WRT
~--------------------.

DO-D7

CCLK ,, ,, ,, ,, GROUP OF
\. ___ J \. ___ J 8 CCLKs

RDY/BUSY
_______________________ J
,,

DOUT
__~x~·_~x~____________~ 1637 22

Figure 4. Peripheral Mode Waveforms

TSC0085 Rev:03

2-121
XC3020B Military Logic Cell Array

DIN

CCLI<
=tG)'=f(i),~J 'f'.'
1-~,~--- 0 ---_114,. . . @ Tccoj,~
TCCH
0'=
_ _ _ _ _ _ __
r-
DOUT
(OUTPUT)
BITN-1 )K BITN
1637 23

Figure 5. Slave Mode Waveforms

AO-A1S
ADDRESS n ADDRESS n + 1
(OUTPUT)

\: CD TRAC

DD-D7
-------------------)~----~~~------ BYTE n

RClK
(OUTPUT)

CClK
(OUTPUT)

DOUT
(OUTPUT)

BYTE n-1
1637 24a

Figure 6. Master Parallel Mode Waveforms

TSC0085 Rev:03

2-122
 DONE/PROG
(OUTPUT) ____-L/___________________________________ _
~0 TRTH-::-1
RTRIG
t'----_ __
(1) TRTCC~
1..----""'
CCLK

@TCCRD~.
RDATA
(OUTPUT) I VALID

1637 25
Figure 7. Program Readback Waveforms

XC3020B Data Sheet Notes

1. Xilinx maintains this specification as a controlled document. To comply with the intent of MIL-STD-883, and to insure the
use of the most recently released device performance parameters, please request a copy of the current revision of this
Table 1 Test Specification (TSC 0085) from Xilinx.
2. No output current loads, no active input or long line pull· up resistors, and with the device configured with the MAKEBITS
'1ie" option.
3. PWRDWN transitions must occur during operational Vcc levels.
4. RESET timing relative to valid mode lines (MO, Ml, M2) is relevant only when RESET is used to delay configuration.
•
5. Configuration must be delayed until the INIT of all LCA's is HIGH. WRT cannot go active until RDVisOSY goes high.
6. Readback should not be initiated until configuration is complete.
7. CCLK and DOUT timing are the same as for slave mode.
8. Testing of the Applications Guidelines is modeled after testing specified by MIL-M-38S1 0/605. Devices are first 100%
functionally tested. Benchmark patterns are then used to measure the Application Guidelines. Characterization data are
taken at initial device qualification, prior to introduction of significant changes, and at least twice yearly to monitor correlation
between benchmark patterns, device performance, XACT software timings, and the data sheet.
9. The CLB K to Q output delay (TCKO) plus the shortest possible interconnect delay is always longer than the Data In hold
time requirement (TCKDI) on the same die.
10. Voltage levels of unused pads must be valid logic levels. Each can be configured with the internal pull-up resistor, config-
ured as a driven output, or driven from an external source.
11. At power-up, Vcc must rise from 2.0V to Vcc minimum in less than 10 ms. Otherwise, delay configuration using RESET.
12. All timings except TTSHZ and TTSON are measured at 1.5 V level with 50 pF minimum load output. For input signals, rise and
fall times are less than 6 ns, with low amplitude = OV, and high = 3V.
TTSHZ is determined when the output shifts 10% (of the output voltage swing) from VOL level or VOH level. The following
circuit is used:

fue
PAD

11K
SOp! MIN
1K
vCC

GND

1637 26

12. (continued)
TTSON is measured at 0.5 Vee level with VIN = 0 for Tri-State to active high, and VIN = Vcc for Tri-State to active low. The
following load circuit is used:

~VIN
~ ... I1
SOp! MIN
·1K

1637 27
TSC0085 Rev:03

2-123
XC3020B Military Logic Cell Array

TSC0085 Rev:03

2-124
 PRELIMINARY XC3090B
Subject to Change
Military Logic Cell™ Array

Product Specification. See Note 1.

FEATURES Part Logic Config- User Conflg-

Number Capacity urable 110's uration
MIL-ST0-883 Class B Processing. (gates) Logic Program
Complies with paragraph 1.2.1 Blocks (bits)
• User-programmable gate array
XC3090 9000 320 144 64160
• Low power CMOS static memory technology

•
• Standard product. Completely tested al factory
• Design changes made in minutes
in internal static memory cells. On-Chip logic provides for
• Complete user control for design cycle. automatic loading of configuration data at power-up or on
Secure design process
command. The program data can reside in an EEPROM,
• Complete PC or workstation based EPROM or ROM on the circuit board or on a floppy disk or
development system hard disk.
- Schematic entry
- Auto Placel Route (OS23) Several methods of automatically loading the required
- Design Editor (OS21) data are designed into the Logic Cell Array and are
- Logic & Timing Simulator (OS22) determined by logic levels applied to mode selection pins
- XACTOR In-circuit Verifier (OS24) at configuration time. The form of the data may be either
serial or parallel, depending on the configuration mode.
The programming data are independent of the configura-
DESCRIPTION tion mode selected.

The Logic Cell™ Array (LCA) is a high density CMOS The XACT development system allows the user to define
programmable gate array. Its patented array architecture the logic functions of the device. Schematic capture is
consists of three type of configurable elements: InpuV available for design entry, while logic and timing simula-
Output Blocks, Configurable Logic Blocks and Intercon- tion, and in-circuit debugging are available for design
nect. The designer can define individual 1/0 blocks for verification. XACT is used to compile the data pattern
interface to external circuitry, define logic blocks to imple- which represents the configuration program. This data
ment logic functions and define interconnection networks can then be converted to a PROM programmer format file
to compose larger scale logic functions. to create the configuration program storage.

The Logic Cell Array's logic functions and interconnec- See the XC3000 Commercial data sheet for a full descrip-
tions are determined by the configuration program stored tion.

ORDERING INFORMATION
XC3090 - 50 PG175 B

T11_ B= MIL·STD-883. CLASS B. FULLY COMPLIANT

50 (50 MHz TOGGLE) - - - - - - - ' - ~ PG =CERAMIC

175-LEAD
PIN GRID ARRAY PACKAGE.

1637 28

TSC0097 Rev:03

2-125
XC3090B Military Logic Cell Array

PIN ASSIGNMENTS

USER
OPERATION

PWR DWN (1\ PWR UWN (1\ PWR Ifl (1\ PWR OWN (1\ PWR OWN III B2 PWRDWi'JIII
VCC D9 vc
(HI M1 OW) M1 M' HIGH M1 OW) 814 RDATA
I(H MON) MOil MO MOLOW) 815 RTRIG(I)

DC He H[ I HD I HD 1m E14 ~
Oil OVi 116 I/O
I I I I I I H1S I/O
3ND GNC GNI ,J14 GNC

_~-lIL RESF"(I) fiES '(I) ~ '(I)

'QIj
DAJ rA_

JA lA'
JA rA
H1 IKJ
JAl IA R9 I/O
VC \199 _Vc~NJl I/CC
DATA ",·"" ••,.,.,.,··,·.,.,DATA l(1) 1(11:':"""" _~ :~

" UA I A 2 I,',•••,.,.,""',,"" UA I A 2 (I).,.,•••"""""",',,, IJA I A 2 (I) ,•••,••,." HT I/O

LK CCLK R2 ",,,',',"," LK (11"'.,."""'"

AO "2 I/U
A1 A1 M3 I/O
A2 A2 p' I/O
A3 A3 N' I/O
A15 A1S M1 IKJ
A4 A4 I/O
A14 A14 K2 I/O
AS AS K' I/O
GN[ GN[ J3 GNC
A13 A13 H2 I/O
A6 A6 H: I/O
A12 A12 F2 IKJ
A, A, E~ I/O
A' A' I/O
AS AS I/O
A10 A10 "3 I/O
A9 A9 C2 I/O
1637 29
[ ] ] ] REPRESENTS A SOKn TO 100Kn PULL-UP
* INIT IS AN OPEN DRAIN OUTPUT DURING CONFIGURATION
(I) REPRESENTS AN INPUT

TSC0097 Rev,03

2-126
 PIN ASSIGNMENTS (Continued)
PGA Pin PGAPln PGAPin PGA Pin
Number XC-3090 Number XC-3090 Number XC-3090 Number XC-3090
B2 l'WRON D13 110 R14 DONE-l'rr R3 DO-DIN-I/O
D4 TCLKIN-I/O B14 Ml-11D7i1'A N13 D7-1/0 N4 DOUT-I/O
B3 110 C14 GNO T14 XTALl (OUTj-BCLKIN-1I0 R2 CCLK
C4 110 B15 MO-RTRlG" P13 110 P3 vee
B4 110 D14 vee R13 110 N3 GNO
A4 110 C15 M2-1I0 T13 110 P2 AO-WS"-1I0
D5 110 E14 HOC-liD N12 110 M3 Al-CS2-1/0
C5 110 B16 110 P12 06-110 Rl 110
B5 110 D15 110 R12 110 N2 110
AS 110 C16 110 T12 110 Pl A2-1/0
C6 110 016 roc-liD Pll 110 Nl AS-li~
D6 110 F14 110 Nll 110 L3 110
B6 110 \ E15 110 Rll 110 M2 110
A6 110 E16 110 Tll D5-1/0 Ml Al5-I/O

•
B7 110 F15 110 Rl0 CSll"-1/0 L2 A4-1I0
C7 110 F16 110 Pl0 110 11 110
D7 110 G14 110 Nl0 110 K3 110
A7 110 G15 110 Tl0 110 K2 A14-1/0
A8 110 G16 110 T9 110 Kl AS-liD
B8 110 H16 110 R9 D4-1I0 Jl 110
C8 110 H15 lNlT-I/O P9 110 J2 110
D8 GNO H14 vee N9 vee J3 GNO
D9 vee J14 GNO N8 GNO H3 vee
C9 110 J15 110 P8 D3-1I0 H2 A13-1/0
B9 110 J16 110 R8 CST-liD Hl AS-liD
A9 110 K16 110 T8 110 Gl 110
Al0 110 K15 110 T7 110 G2 110
Dl0 110 K14 110 N7 110 G3 110
Cl0 110 L16 110 P7 110 Fl 110
Bl0 110 L15 110 R7 D2-1I0 F2 A12-1/0
All 110 M16 110 T6 110 El A7-UO
Bll 110 M15 110 R6 110 E2 110
Dll 110 L14 110 N6 110 F3 110
Cll 110 N16 110 P6 110 Dl All-liD
A12 110 P16 110 T5 110 Cl A8-1/0
B12 110 N15 110 R5 Dl-I/O D2 110
C12 110 R16 110 P5 RDY/lIDSV-RcrK-1I0 Bl 110
D12 110 M14 110 N5 110 E3 Al0-1I0
A13 110 P15 XTAL2(IN)-1I0 T4 110 C2 A9-1/0
B13 110 N14 GNO R4 110 D3 vee
C13 110 R15 11ESET P4 110 C3 GNO
A14 110 P14 vee 1637 Tbl 09

Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-limited.

Pins A2, A3, A 15, A 16, Tl, T2, T3, T15 and T16 are not connected.
Pin A 1 does nol exist.

_u
TSC0097 Rev:03

2-127
XC3090B Military Logic Cell Array

CASE OUTLINE DRAWING

Conforms to MIL-M-38510 Appendix C, Case P-BC.

o INDEX

WE10 METAL1C HEATSINK .025 REF.

ElECTRICALLY CQNIIECTED TO vee

f
.180
PIN KOVAR
.000R.TYP.
.016 REF.
!

16 GGGGGGGGGGGGGGG 0 - + + - - - - - - .
15 G0GGGGGG,GGGGGG0 0
MGGGGGGGGGGGGGGGG lYP..070 OIA
,,005

13 GGGG
12GGGG GGGG
"GGGG GGGG
I. GGGG GGGG
·GGGG GGGG
«. G 0--=GO-G=0-If---+
1.660SO±.016

GG0G 1.500±.015

7GGGG GGGG
'GGGG GGGG
'GGGG GGGG
4 G G G G !!=====F====lj.--r"""<""..,......,.~4-----i
3GGGG DielECTRIC COAT

2G0GG STAND OFF PIN

4PL
'GGGG GGGGGG
T R P N M

I. .695±OO7----!
1637 30

TSC0097 Rev:03

2-128
 I:XIUI\JX

STATIC BURN-IN CIRCUIT

1 5.0±0.25V

30 4.02k

8 ('j ~ a;1~blJd~lwldu:lal~ldJ:h ~ "l ~l"l;;:l~ld:;l~:hl!1jl~lzld~l1[l;]l~l~

~r
3 1.5«

i
1.151<
~~ 8~ / 4
~\ ~

tt ,~ ;j
715
D4 8 » '" N4
~ > g; R3
1.5«
~
~
~
~ DIN
~

•
~ ?
~ ~
~ ~
~ 4
~ ~
~ ~
~ ,.¥,
~ ~
~ ~
~ ~
~
~
~
'*-
fa-
Ts-
~ -¥s-
~ vss
XC3090
vss
~
N9
vcc VCC
PG 175
~ 4
~ ~
~
f-jjfo-
~
¥o
~ cWo-
~ irtO
~ -'fif""
Mm- "iiiT
'-j:ffi-
f-ffit
~ --'prt-
'itr -Tit
>-jjf2 iIT2-
~
~
f-N
~
*-ifr-
--j;ffz-
'Fii3"
~
~jM1 vss
DONEJPGM\
-p,g
-w
~f 8Ng
f-5& VCC\ w
R~~
MO
ifit 1.3k
C14 >:E:I: P14

~~I~ I~ ~~ R15

. '" WmOOQ i'.LwwU::U::EE5II 4.S9k

00
"~ISI&r ~1~1~1~1~15IGIGlil'" .... rl~I~I~l~l~l~l~l~lil~lil~lilr
i"'~~~~~~i~z£z~i~z

1k 1.3k 1.3k

O1~F+
rn

NOTES:
1. UNLESS OTHERWISE SPECIFIED, ALL
RESISTORS ARE METAL FILM AND ARE
RATED FOR 118 WAn AT 150"C WITH A
BUILD TOLERANCE OF 1'% AND A 5%
TOLERANCE OVER LIFE.
[gJ CAPACITOR HAS 10% TOLERANCE,
50 V RATING WITH AN X7R
TEMPERATURE CHARACTERISTIC.
rn 300 RESISTOR IS METAL OXIDE AND
IS RATED FOR 1 WAT150"C WITH A 163731
TOLERANCE OF 5%.

TSC0097 Rev:03

2-129
XC3090B Military Logic Cell Array

XC3090B Test Specification

Absolute Maximum Ratings Limits Units

Vee Supply voltage relative to GND -0.5 to 7.0 V

VIN Input voltage with respect to GND -0.5 to Vee + 0.5 V

VTS Voltage applied to three-state output -0.5 to Vee + 0.5 V

TSTG Storage temperature (ambient) -65 to +150 °C

TSOL Maximum soldering temperature (10 sec@ 1/16 in.) +260 °C

TJ Maximum junction temperature +150 °C

1637Tbll0
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure
to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

Conditions
-55°C ~ Te ~ +125°C Group A Limits
Test Symbol Vee = 5.0 V ±10% Subgroups Min Max Units

High Level Output Voltage VOH Vee = 4.5 V, IOH = -4.0 mA 1,2,3 3.7 V
Low Level Output Voltage VOL Vee = 5.5 V, IOL = 4.0 mA 1,2,3 0.4 V
Quiescent Operating 2 leeo CMOS Mode, Yin = Vee = 5.5 V 1,2,3 3 mA
Power Supply Current
TIL Mode, Yin = Vee = 5.5 V 1,2,3 15 mA
Power-Down Supply Current leePD Yin = Vee = 5.5 V, 1,2,3 2.5 mA
PWR DWN =OV
Leakage Current IlL Vee = 5.5 V, Yin = Vee and 0 V 1,2,3 -20 20 ~
Horizontal Long Line IRLL Measured as an average 1,2,3 2.4 mA
Pull-up Current
Input High Level TIL VIHT Guaranteed Input High 1,2,3 2.0 V
Input Low Level TTL VILT Guaranteed Input Low 1,2,3 0.8 V
Input High Level CMOS VIHe Guaranteed Input High 1,2,3 .7 Vee V
Input Low Level CMOS VILe Guaranteed Input Low 1,2,3 .2 Vee V

1637 Tbl l1a

Table 1. Electrical Performance Characteristics

TSC0097 Rev:03

2-130
 Conditions
-55°C ~ Tc ~ +125°C Group A Limits
Test Sym Vcc =5.0 V ±10% Subgroups Min Max Units

Switching Characteristics, General LCA

DONEIPROG
Program Width (Low) TpGW 5 See Fig. 1 9,10,11 6 /ls
Initialization TpGI 6 9,10,11 7 /lS

PWR OWN'
Power Down Supply VCCPD 1,2,3 3.5 V
RESET4
M2,M1,MO Setup TMR 2 9,10,11 1 /ls
M2,M1,MO Hold TRM 3 9,10,11 1

•
/lS
Width (low) abort TMRW 4 9,10,11 6 /lS
Switching Characteristics, Peripheral Mode Programmlng 5

WRTLOW TCA 1 See Fig. 4 9,10,11 0.5 /ls

DIN Setup Toe 2 9,10,11 60 ns
DIN Hold TeD 3 9,10,11 0 ns
Ready/Busy TWTRB 4 9,10,11 60 ns

Switching Characteristics, Slave Mode Programming 5

CCLK,
To DOUT TCCD 3 See Fig. 5 9,10,11 100 ns
DIN Setup TDCC 1 9,10,11 60 ns
DIN Hold TCCD 2 9,10,11 0 ns
High Time TCCH 4 9,10,11 0.5 /lS
Low Time TCCL 5 9,10,11 0.5 1.0 /lS
Frequency Fcc 9,10,11 1 MHz
16371blllb

Table 1. Electrical Performance Characteristics (Continued)

TSC0097 Rev:03

2-131
XC3090B Military Logic Cell Array

Conditions
-55°C ~ Tc ~ +125°C Group A Limits
Test Sym Vcc =5.0 V ±10% Subgroups Min Max Units

Switching Characteristics, Program Readback6 .7

RTRIG Setup TRTH 1 See Fig. 7 9,10,11 250 ns

CCLK,
RTRIG Setup TRTCC 2 9,10,11 200 ns
RDATA Delay TCCRO 3 9,10,11 100 ns
Clock Low TCClR 4 9,10,11 1.2 2.0 J.1S
Clock High TCCHR 5 9,10,11 0.5 J.1S
Benchmark PatternsB

Tplo + interconnect + 20 (TllO) + TBl 9,10,11 303 ns

Top. Measured on 16 cols.
TCKO + TICK + TCKI + TB2 Tested on all CLBs 9,10,11 32 ns
interconnect
TCKO + TOlO + TllO + TOICK + TB3 Tested on all CLBs 9,10,11 53 ns
interconnect
TOLD + TECCK + interconnect TB4 Tested on all CLBs 9,10,11 35 ns

TOKPO + Tops - TOPF + TPICK TB5 Tested on all CLBs 9,10,11 73 ns

TCKO + TOLO + TBUF + TICK + TB6 One long line pull-up 9,10,11 73 ns
interconnect
TCKO + TOLO + TBUF + TICK + TB7 The other long line pull-up 9,10,11 83 ns
interconnect
TCKO + TOLO + TBUF + TICK + TB8 No pull-up, lower long lines 9,10,11 47 ns
interconnect
TCKO + TOLO + TBUF + TICK + TB9 No pull-up, upper long lines 9,10,11 57 ns
interconnect
1637Tbll1c
Table 1. Electrical Performance Characteristics (Continued)

TSC0097 Rev:03

2-132
 Conditions
-SsoC ~ Tc ~ +12SoC Group A Limits
Test Sym Vcc =S.O V ±10% Subgroups Min Max Units

Application Guidelines, Switching, ClBa

Combinatorial TILO 1 See Fig. 2 N/A 14 ns

Reset to ClB output TRIO 9 N/A 12 ns
Reset Direct width TRPW 13 N/A 12 ns
Master Reset pin to CLB out TMRO N/A 30 ns

K Clock9
To CLB output TCKO 8 N/A 12 ns
Additional for Q returning TOLO N/A 11 ns
through F or G to CLB out
Logic-input setup TICK 2 N/A 12 ns
N/A

•
Logic-input hold TCKI 3 0 ns
Data In setup TDICK 4 N/A 8 ns
Data In hold (1) TCKDI S N/A 6 ns
Enable Clock setup TECCK 6 N/A 10 ns
Enable Clock hold TCKEC 7 N/A 0 ns
Clock (high) TCH 11 N/A 9 ns
Clock (low) TCl 12 N/A 9 ns

Flip-flop Toggle Rate FClK N/A SO MHz

Application Guidelines, Switching, Internal BuffersB

Clock Buffer TGCK N/A 9 ns

TBUF
Data to Output TID N/A 8 ns
Three-state to Output
Single Pull-up Tpus N/A 34 ns
Pair of Pull-ups TpLJF N/A 17 ns

Bidirectional BIOI N/A 6 ns

1637TbIlld

Table 1. Electrical Performance Characteristics (Continued)

TSC0097· Rev:03

2-133
XC3090B Military Logic Cell Array

Conditions
-55°C ~ Tc ~ +125°C Group A Limits
Test Sym Vcc = 5.0 V ±10% Subgroups Min Max Units

Application Guidelines, Switching, IOB8.10

Pad (package pin) See Fig. 3

To inputs TClKIN, BClKIN TPIDC N/A 5 ns
To inputs DIRECT IN TplD 3 N/A 9 ns

I/O Clock
To I/O RI input (FF) TIKRI 4 N/A 11 ns
I/O pad-input setup TPICK 1 N/A 30 ns
I/O pad-input hold TIKPI 2 N/A 0 ns
To I/O pad.(fast) TOKPO 7 N/A 18 ns
I/O pad output setup TOOK 5 N/A 15 ns
I/O pad output hold TOKO 6 N/A 0 ns
Clock (high) TloH 11 N/A 9 ns
Clock (low) TIOl 12 N/A 9 ns

Output
To pad (enabled fast) TOPF 10 N/A 14 ns
To pad (enabled slow) Tops 10 N/A 39 ns

Three-State
To pad begin hi-Z (fast) TTSHZ 9 N/A 12 ns
To pad valid (fast) TTSON 8 N/A 20 ns

Master Reset
To input RI TRRI 13 N/A 35 ns
To output (FF) TRPo 14 N/A 50 ns
1637lbll1.

Table 1. Electrical Performance Characteristics (Continued)

Conditions
-55°C::; Tc ~ +125°C Group A Limits
Test Sym Vcc = 5.0 V ±10% Subgroups Min Max Units

Application Guidelines, Switching, Master Parallel Mode Programming 8 •11

RClK,
To Address Valid TRAC 1 See Fig.6 N/A 0 200 ns
To Data Setup TDRc 2 N/A 60 ns
To Data Hold TRCD 3 N/A 0 ns
RCLK High TRcH 4 N/A 600 ns
RCLK low TRCl 5 N/A 4.0 Ils
1637lbllli
Table 1. Electrical Performance Characteristics (Continued)

TSC0097 Rev:03

2-134
 ,....--------oI!1--1_--,(G)TMRW)________

MO/M1/M2
-r~'~®,~[--~---
DONEIPROG
~®TPGW~
(OUTPUT)

INIT
___J___~[@TPGI
USER STATE ____________ C_LE_A~R!rS-T-A-T-E--------------~;1 CONFIGURE
(OUTPUT) - II .

PWRDWN

Vee (VALID)
-----------------------------------------------~\

Figure 1. General LCA Waveforms

\ r- NOTE3 -j

'- ____ J-,.-

, 'V
r-
Ir~t------
CCPD

1637 32
•
CLB OUTPUT (X,V)
(COMBINATORIAL)

CLB INPUT (A,B,C,D,E)

CLBCLOCK

14--- @ TCL--~

o T DICK ----1~

CLB INPUT
(DIRECT IN)

CLB INPUT
(ENABLE CLOCK)

CLBOUTPUT
(FLIP-FLOP)

CLBINPUT
(RESET DIRECT)

CLBOUTPUT
(FLIP-FLOP)
1637 33

Figure 2. CLB Waveforms

TSCOO97 Rev:03

2-135
XC3090B Military Logic Cell Array

-®-TPID~-[----
110 BLOCK (I)

tCD
110 PAD INPUT

TpICK--...·""'·I-® T I K P I J - - - - - - -
110 CLOCK
- - - ,,
(IKIOK)

~---@ TIOL---~--­
'ir-----n--
110 BLOCK (RI)

110 BLOCK (0)

@TOp
110 PAD OUTPUT
(DIRECn

110 PAD OUTPUT

-----------------~f0 T
OKPO

(REGISTERED)

J---rr-0-~-SON----@-~-~j r
IIOPADTS

110 PAD OUTPUT

--------~<~----------~~ 1637 34

Figure 3, lOB Waveforms

\
,,
CS11CSO \ / ,

CS2
7 \~------------/~!----
WRT
,
.
DO-D7

CCLK , I GROUP OF
, I
\. -_., 8 CCLKs

RDYIBUSY _______________________ JI I

DOUT _~x~_~x~ ____________ ~

1637 35

Figure 4, Peripheral Mode Waveforms

TSC0097 Rev:03

2-136
 I:XIU~~X

DOUT
(OUTPUT)
1637 36

Figure 5. Slave Mode Waveforms

•
AO-A1S
ADDRESS n ADDRESS n + 1
(OUTPUT)

\: 0) TRAC

DO-D7
----~------------~~-----+~~-----
BYTE n

~ CD -~'--'of-- ® TDRC T RCD

RCLK
(OUTPUT)

CCLK
(OUTPUT)

DOUT
(OUTPUT)
1637 37
BYTE n-1

Figure 6. Master Parallel Mode Waveforms

TSC0097 Rev:03

2-137
XC3090B Military Logic Cell Array

DONEIPROG
(OUTPUT)
_--L../___________________________________ _
RTRIG

~T~~--~r--------
CCLK

RDATA VALID
(OUTPUT)
1637 36
Figure 7. Program Readback Waveforms

XC3090B Data Sheet Notes

1. Xilinx maintains this specification as a controlled document. To comply with the intent of MIL-STD-883, and to insure the
use of the most recently released device performance parameters, please request a copy of the current revision of this
Table 1 Test Specification (TSC 0097) from Xilinx.
2. No output current loads, no active input or long line pull-up resistors, and with the device configured with the MAKEBITS
'tie" option.
3. PWRDWN transitions must occur during operational Vcc levels.
4. RESET timing relative to valid mode lines (MO, Ml, M2) is relevant only when RESET is used to delay configuration.
5. Configuration must be delayed until the TNlT of all LCA's is HIGH. WRT cannot go active until RDY/BUSY goes High.
6. Readback should not be initiated until configuration is complete.
7. DOUT timing is the same as for slave mode.
8. Testing of the Applications Guidelines is modeled after testing specified by MIL-M-38S1 0/605. Devices are first 100%
functionally tested. Benchmark patterns are then used to measure the Application Guidelines. Characterization data are
taken at initial device qualification, prior to introduction of significant changes, and at least twice yearly to monitor correlation
between benchmark patterns, device performance, XACT software timings, and the data sheet.
9. The CLB K to Q output delay (TCKO) plus the shortest possible interconnect delay is always longer than the Data In hold
time requirement (TCKDI) on the same die.
10. Voltage levels of unused pads must be valid logic levels. Each can be configured with the internal pull-up resistor, config-
ured as a driven output, or driven from an external source.
11. At power-up, Vee must rise from 2.0V to V~ minimum in less than 10 ms. Otherwise, delay configuration using RESET.
12. All timings except TTSHZ and TTSON are measured at 1.5 V level with 50 pF minimum load output. For input signals, rise and
fall times are less than 6 ns, with low amplitude = OV, and high = 3V.
TTSHZ is determined when the output shifts 10% (of the output voltage swing) from VOL level or VOH level. The following
circuit is used:

fuC
PAD

SOp! MIN 1 1 K
1K
vCC

GND

1637 39

12. (continued)
TTSON is measured at 0.5 Vee level with VIN = 0 for Tri-State to active high, and VIN = Vee for Tri-State to active low. The
following load circuit is used:

~VIN
~_.1
SOp! MIN I -II<

1637 40
Tse0097 Rev:03

2-138
 XC1736 Serial
Configuration PROM

Product Specification

FEATURES vPP

• One-Time Programmable (OTP) 36,288 x 1 bit serial

memory designed to store configuration programs for
Programmable Gate Arrays PROGRAMMING
DATA SHIFT
• Simple interface to a XILINX logic CellTM Array (lCA) REGISTER
requires only two I/O pins
• Daisy chain configuration support for multiple lCAs
• Cascadable to provide more memory for additional
configurations or future higher-density arrays
24
II
• Storage for multiple configurations for a single logic Cell
Array ROW
DECODER
• low power CMOS EPROM process
• Space-efficient, 8-pin plastic/ceramic DIP package
• PC-based Xilinx programmer for development. Produc-
tion programming support from leading programmer
manufacturers

DESCRIPTION

The XC1736 Serial Configuration PROM (SCP) provides

an easy-to-use, cost-effective configuration memory for
the Xilinx family of programmable gate arrays. Packaged
in an economical8-pin plastic DIP package, the XC1736
ClK RESET/DE DATA
uses a simple serial access procedure to configure one or
more logic Cell Arrays (lCAs). The 36,288 x 1 organiza- 1106905
tion of the configuration PROM supplies enough memory Figure 1. XC1736 Block Diagram
to configure three XC2064's, two XC2018's, two
XC3020s, one XC3030 or one XC3042. Multiple Serial
Configu ration PROMs can be cascaded to provide a larger
memory for higher density arrays. Mu Itiple configurations
for a single lCA can also be loaded from the XC 1736. DATAU8 VCC
ClK 2 7 vpp
The XC1736 can be programmed with the PC-based Xilinx
RESET/OE 3 6 CEO
XC-DSl12 Configuration PROM Programmer orwith pro-
grammers from other manufacturers. The logic Cell Array CE 4 5 GND
design file is first compiled into a standard HEX format with 11069 04
the XC-DS21 Development System. It can then be trans-
ferred to the XC-DSl12 programmer connected to the XC1736 Pin Assignments
serial port.

2-139
XC1736 Serial Configuration PROM

Table 1. XC1736 Pin Assignments

Pin Name 1/0 Description

DOUT } ADDITIONAL
DATA 0 Three-state DATA output for reading. SLAVE MODE
Input/Output pin for programming. M2 CClK lCAs (OPTIONAL)
HDC
2 ClK Clock input. Used to increment the lDC
internal address and bit counters for GENERAL·

)~
reading and programming. PURPOSE
USER 1/0
PNS
OTHER
3 RESETI Output Enable input. A lOW level on PINS
OE both the CE and OE inputs enables
the data output driver. A HIGH level on
RESET/OE resets both the address RESET
and bit counters.
LOGIC
4 CE Chip Enable input. A lOW level on CELL
both CE and OE enables the data ARRAY
output driver. A HIGH level on CE dis-
ables both the address and bit coun- +5V
ters and forces the device into a low
power mode. Used for device
Vee Vpp
selection.
DIN DATA XC1736
5 GND Ground pin. CClK ClK SERIAL
CE CONFIG·
URATION
6 CEO 0 Chip Enable Out output. This signal is DIP OE PROM
asserted lOW on the clock cycle
following the last bit read from 1106 06

the memory. It will stay lOW as long as Figure 2. Master Serial Mode Configuration
CE and OE are both lOW. It will follow
CE, but if OE goes HIGH, CEO will
stay HIGH until the entire PROM is
read again.

7 VPP Programming Voltage Supply. Used

to enter programming mode (+6V) and
to program the memory (+21V) Must
be connected directly to VCC for
normal read operation. No overshoot
above +22V permitted.

8 Vcc +5 volt power supply input.

2-140
 E:XIUNX

LCA MASTER SERIAL MODE SUMMARY CCLK will clock data out of the SCP on every rising clock
edge. At the completion of configuration, the DONE!
The I/O and logic functions of the Xilinx Programmable PROG signal will go high and reset the internal address
Gate Array, and their associated interconnections, are counters of the SCPo
established by a configuration program. The program is
loaded either automatically upon power up, or on com- If the user-programmable, dual function DIN and CCLK
mand, depending on the state ofthe three LCA mode pins. pins are used only for the configuration process, they
In Master Mode, the Logic Cell Array automatically loads should be programmed on the LCA so that no nodes are
the configuration program from an external memory. The floating or in contention. For example, both DIN and CCLK
Serial Configuration· PROM has been designed for com- can be programmed as output highs during normal opera-
patibility with the Master Serial Mode. tion. An alternate method is to program both DIN and
CCLK as inputs, with external pullup resistors attached.
Upon power-up or upon reconfiguration, an LCA will enter
Master Serial Mode whenever all three of the LCA's mode If DIN and CCLK are to be used for another function after
select pins are LOW (MO=O, M1=O, M2=O). Data are read configuration, the user must avoid contention. The Low
from the Serial Configuration PROM sequentially on a During Configuration (LDC) pin can be used to control the
single data line. Synchronization is provided by the rising SCP's CE and OE inputs to disable the SCP's DATA pin 1
edge of the temporary signal CCLK, which is generated clock cyCle before Dip is active.
during configuration.
If the LCA is to be reprogrammed after .initial power-up,
II
Master Serial Mode provides a simple configuration inter- note that the LCA requires several microseconds to re-
face. Only a serial data line and two control lines are spond after.the DiP pin ispulled low. In this case, the LOC
required to configure an LCA. Data from the Serial Con- pin can be used instead of the DIP pin to control the SCP.
figuration PROM is read sequentially, accessed via the
internal address and"bit counters which are incremented Programming The LCA With Counters Unchanged
on every valid rising edge of CCLK. Upon Completion .

Programming The LCA With Counters Reset Up<m When multiple LCA configuratipns for a single LCA are
Completion stored in a Serial Configuration PROM, the OE pin should
be tied low as shown in Figure 3. Upon power-up, the
Figure 2 shows the connections between an LCA and itS .internal address counters wm be reset and configuration
SCPo The DATA linefromthe SCP is connected to the DIN will begin With the first program stored in memory. Since
input of the LCA. CCLK is connected to the CLK input of the OE in is held low, the a.ddreSs counters are left
the SCPo At power-up or upon reconfiguration, the DIP unchanged after configuration is complete: Therefore, tp
signal goes low (pulled low by the LCA at reset, or by reprogram the LeA with another program, the DONE!
external circuitry for reconfiguration),.enabling the SCP PROG line is pulled low and configuration beginsatthe last
and its .DATA output. During.the configuration process, value of the· address counters.

DAISY-CHAIN DOur DIN DATA

TO OTHER lCA'S CClK CClK ClK
SOP CEO NC
LOA CE
Mo RESET/OE
M1
M2 DIP

1106 07

Figure 3. Address Counters Not. Reset

Notes: 1. If M2 is tied. directly to ground, it should be programmed as an input during operation.

2. If the LOA is reset during configuration; it will abort back to initialization state ..
Dip will not go high, so an external signal is required to reset the 1736 counters.

2-141
XC1736 Serial Configuration PROM

Cascading Serial Configuration PROM's where the address counters had stopped. In this case,
avoid contention between DATA and the configured 1/0
For multiple LCA's configured as a daisy-chain, or for use of DIN.
future LCA's requiring larger configuration memories,
cascaded SCP's provide additional memory. A single Extremely large, cascaded memories in some systems
SCP is large enough for daisy-chains consisting of three may require additional logic if the rippled chip enable is too
XC2064's, two XC2018's, two XC3020's, or a mixture. slow to activate successive SCP's.

After the last bitfrom the first SCP is read, the SCP asserts STANDBY MODE
its CEO output low and disables its own DATA line. The
next SCP recognizes the low level on its CE input and The XC1736 enters a low-power standby Mode whenever
enables its own DATA output. See Figure 4. CE is asserted high. In this mode the SCP consumes less
than O.5mA of current. The output remains in a high-
After configuration is complete, the address counters of all impedance state regardless of the state of the OE input.
of the cascaded SCP's will be reset when DONE/PROG
goes high, forcing the RESET/OE on each SCPto go high. PROGRAMMING MODE

If the address counters are not to be reset upon comple- Figure 5 shows the programming algorithm for the
tion, then the OE inputs can be tied to ground, as shown in XC1736. Note that programming mode is entered by
Figure 3. To reprogram the LCA with another program, the holding Vpp high for at least 2 clock edges and is exited by
DONEIPROG line goes low and configuration begins removing power from the device.

DAISY·CHAIN DOUT DIN ~-,---------..,-----­

TO OTHER LCA'S CCLK CCLK~4r~------r+-----

SCP SCP
DATA DATA
CLK CLK
LCA
CE CE
RESET/DE
MO
Ml
M2 DIP I--~---,----~-----

REPROGRAM
1106 08

Figure 4. Cascading SCP's

2-142
 ENTER PROGRAMMING MODE
1.Vcc .. Vpp-6V CE=0E",5V
2. Vpp' 21V FORATLEAST2CLK RISING EDGES
3. Vpp = 6V FOR 1 CLOCK RISING EDGE

III

INCREMENT ADDR~
COUNTER. RESETIOE
HELD LOW FOR ONE
CLOCKCVCLE

1106 09
DEVICE PASSED

Figure 5. Programming Mode

2-143
XC1736 Serial Configuration PROM

PARAMETRICS

Absolute Maximum Ratings Units

Vee Supply voltage relative to GND -0.5 to 7.0 V

VIN Input voltage with respect to GND -D.5 to Vee + 0.5 V

VTS Voltage applied to three-state output -D.5 to Vee + 0.5 V

TSTG Storage temperature (ambient) -65 to + 125 °C

TSOL Maximum soldering temperature (10 sec@ 1/16 in.) +260 °C

"Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure
to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

DC CHARACTERISTICS

Symbol Description Min Max Units

Vee Supply voltage relative to GND Comm/lnd -40°C to 85°C 4.5 5.5 V

Vpp"" Supply voltage relative to GND Military -55°C to 125°C 4.5 5.5 V

VIH High-level input voltage 2.0 Vee V

VIL Low-level input voltage 0 0.8 V

VOH High-level output voltage (IOH =- 4mA) 3.86 V

Commercial
VOL Low-level output voltage (loL = 4mA) 0.32 V

VOH High-level output voltage (IOH =- 4mA) 3.76 V

Industrial
VOL Low-level output voltage (loL = 4mA) 0.37 V

VOH High-level output voltage (IOH =- 4mA) 3.7 V

Military
VOL Low-level output voltage (loL = 4mA) 0.4 V

VPP1 Vpp programming voltage (No overshoot permitted) 20 22 V

VPP2 Vpp during programming mode 5.75 6.25 V

ICCA Supply current, active mode (Icc + Ipp) 10 rnA

ICCs Supply current, standby mode (Icc + Ipp) 0.5 mA

IL Input or output leakage current -10 10 ~

IPPp Supply current, programming mode 50 mA

""During normal read operation, Vpp must be connected 10 Vcc.

2-144
AC CHARACTERISTICS

CE
~-- ® TSCE --~
----+-.....
RESETIOE

CLK

DATA

1106 10

1
2
3
4
Symbol

TOE
TCE
TCAC
TOH
Description

OE to Data Delay
CE to Data Delay
ClK to Data Delay
Data Hold From CE, OE, or ClK
Min
Limits

0
Max

100
250
400
Units

ns
ns
ns
ns
•
5 TDF CE or OE to Data Float Delay 50 ns
6 TLc ClK low Time 200 ns
7 THC ClK High Time 200 ns
8 TSCE CE Setup Time to ClK (Guarantees Counters 100 ns
Will or Will Not Change)
9 THCE CE Hold Time to ClK (Guarantees Counters Will 0 ns
or Will Not Change)
10 THOE OE HighTime (Guarantees Counters Are Reset) 100 ns

Notes: 1. A.C. test load = 50 pF.

2. Float delays are measured with minimum tester A.C. load and maximum D.C. load.

2-145
XC1736 Serial Configuration PROM

AC CHARACTERISTICS

RESET/OE

CLK

DATA FIRST BIT

o TOOE
1106 11

Limits
Symbol Description Units
Min Max

1 TCDF ClK to Data Float Delay 40 ns

2 TOCK ClK to CEO Delay 100 ns
3 TOCE CE to CEO Delay 100 ns
4 TOOE RESET/OE to CEO Delay 100 ns

2-146
lCA SERIAL MASTER MODE CHARACTERISTICS

VCC

ClK

DIN

DONE/PGM

1106 12

Limits
Symbol Description Units
Min Max

1 TRCK Vcc iii 3V to RClK Delay' 10 160 ms

2 TlCK ClK low Time 250 ns
3 THCK ClK High Time 250 ns
4 TSD DIN Setup to ClK 100 ns
5 THD DIN Hold From ClK 0 ns
6 TOONE lCA User-Programmed Pins Active to Done Delay 3 ~s

'This time may be extended by holding the lCA's RESET input low.

2-147
XC1736 Serial Configuration PROM

PROGRAMMING CHARACTERISTICS

21V

Vpp

ClK

DATA

CE

______________ __ ~_12 ~_IC_~-~~13--~-IC----------------------

RESET/DE
1106 13

Limits
Symbol Description Units
Min Max

1 TRPP 10% to 90% Rise Time of VPp 50 70 J.!s

2 TFPP 90% to 10% Fall Time of Vpp 50 70 J.!s
3 TPGM Vpp Programming Pulse Width 0.95 1.05 ms
4 Tsvc Setup of Vpp to ClK to Enter Programming Mode 100 ns
5 THVC Holdof Vpp to ClK to Enter Programming Mode 300 ns
6 TSDP Data Setup to ClK for Programming 50 ns
7 THDP Data Hold to ClK for Programming 0 ns
8 Tscc' CE Setup to ClK for ProgrammingIVerifying 100 ns
9 THCC' CE Hold From ClK for Programming/Verifying 200 ns
10 Tscv CE Setup to VPp for Programming 100 ns
11 THCV CE Hold From Vpp for Programming 50 ns
12 TSlc OE Setup to ClK to Increment Address Counter 100 ns
13 THIC OE Hold From ClK to Incre.ment Address Counter 0 ns

'During programming CE should only be changed while ClK is high and has been high for 200ns.

2-148
ORDERING INFORMATION
XC1736 - PDBC

1106 01
POB (8 PIN PLASTIC DIP)
CD8 (8 PIN CERAMIC DIP)
~L C (COMMIIND _40° TO 85°C)
M (MILITARY TEMP -55° TO 125°)

~ .362±.02j
9.2± .5

D
8 5

J±·02
6.4 ±.5

o ~
1 4

11~

,..
r-+-+-+t---.

1111~',::~
.018
As .02 MIN

f · 5 1 MIN.

.18 MAX
r-I,--- j
~-+
.313± .01
7.95 ± .25
•
~
.009

j L .032 3MIN
r- .325 ± .025
8.26 ± .64 ---J
25

1106 02
.10 ~ T1
IN~~ES NOT DRAWN TO SCALE
2.54

8-Pin Plastic DIP Package

t .520±.01
13.2±.20
j
OJ·Ol
8 5

7.4±.20

o ~
1 4

110614
IN~~ES NOT DRAWN TO SCALE

8-Pin Ceramic Sidebrazed DIP Package

PIN 0010043

2-149
 XC1764 Serial
Configuration PROM

Advance Information

vPP
FEATURES

• One-Time Programmable (OTP) 65,536 x 1 bit serial

memory designed to store configuration programs for
Programmable Gate Arrays PROGRAMM ING
DATA SHIFT
• Simple interface to XILINX logic Cell™ Arrays (lCA) REGISTER
requires only two I/O pins
• Daisy chain configuration support for multiple XC2000
or XC3000 lCAs 32
• Cascadable to provide more memory for additional
configurations or future higher-density arrays
ROW
• Storage for multiple configurations for a single logic DECODER
Cell Array
• low power CMOS EPROM process
• Space-efficient, 8-pin plastic/ceramic DIP package
• PC-based Xilinx programmer for development. BIT
COUNTER I-----t----,L--~
Production programming support from leading
programmer manufacturers

DESCRIPTION

The XC1764 Serial Configuration PROM (SCP) provides

an easy-to-use, cost-effective configuration memory for
Xilinx programmable gate arrays. Packaged in an eco- ClK RESET! DATA
nomical 8-pin plastic DIP package, the XC1764 uses a BE
simple serial access procedure to configure one or more 1951 05
logic Cell Arrays (LCAs). The 65,536 x 1 organization of Figure 1. XC1764 Block Diagram
the configuration PROM supplies enough memory to con-
figure one XC3090 or multiple smaller LCA's. Multiple
Serial Configuration PROMs can be cascaded to provide
a larger memory for higher density arrays. Multiple con-
figurations for a single LCA can also be loaded from the
XC1764.
DATAU8
ClK 2 7
VCC
VPP
RESET/OE 3 6 CEO
The XC 1764 can be programmed with the PC-based Xilinx
CE 4 5 GND
XC-DS112 Configuration PROM Programmerorwith pro-
grammers from other manufacturers. The Logic Cell Array 1951 04

design file is first compiled into a standard HEX format with

XC1764 Pin Assignments
the XC-DS21 Development System. It can then be trans-
ferred to the XC-DS112 programmer connected to the
PC's serial port.

2-150
l:XllINX Sockets

Below are two lists of manufactures known to offer sockets a compatible PGA socket with wire-wrap pins. Note that
for Xilinx package types. This list does not imply an the board-layout then differs from a PGA board layout.
endorsement by Xilinx. Each user must evaluate the
Zero Insertion Force (ZIF) sockets, recommended for
particular socket type.
prototyping with 132 and 175 pin PGA devcies, also lack
There are no wire-wrap sockets for PLCCs. One solution the wire-wrap option. Piggy-back the ZIF socket in a
is to piggy-back a through-hole PLCC socket mounted in normal PGA wire-wrap socket.

PLCC Sockets PGA Sockets

AMP Inc. Mill-Max Mfg. Corp. Advanced Interconnections McKenzie Technology

Harrisburg, PA 17105 190 Pine Hollow Road 5 Energy Way 44370 Old Warm Springs Blvd.
(717) 564-0100 Oyster Bay, N.Y. 11771-0300 West Warwick, RI 02893 Fremont CA 94538
(516) 922-6000 (401) 823-5200 (415) 651-2700
Burndy Corp. "
Richards Ave. Precicontact IriC. AMP Inc. Methode Electronics Inc.
Norwalk, CT 06856 835 Wheeler Way Harrisburg, PA 17105 1700 Hicks Road
(20$) 852-84$7 Langhorne, PA 19047 (717) 564.0100 Rolling Meadows, IL 47150
(215) 757-1202 (312) 392-3500
Garry Electronics Aries Electronics, Inc.
9 Queen Anne Court Robinson Nugent P.D.Box 130 Mill-Max Mfg. Corp.
Langhorne, PA 19047-1803 800 East Eighth Street Frenchtown, NJ 08825 190 Pine Hollow Road
(215) 949-2300 New Albany, IN 47150 (201) 996-6841 Dyster Bay, N.Y. 11771-0300
(812) 945-0211 (516) 922-9000
Honda - MHOtronics Augat
Oeerfield:IL 60015 Samtec Inc. 33 Perry Ave. Precicontact Inc.
444 Lake Cook Road, Suite 8 P.O.Box,1147 P.D.Box 179 835 Wheeler Way
(312) 948-5600 New Albany, IN 47150 Attleboro, MA 02703 Langhorne, PA 19047
(812) 944-6733 (617) 222-2202 (215) 757-1202
ITT Cannon
10550. Talbert Ave. 3M Textool Bevmar Industries, Inc. Robinson Nugent
P.O. Box 8040 . Austin, TX 20601 Annalee Ave. 800 East Eighth Street
Fountain. Valley, CA 92728 (800) 328-7732 Carson, CA 90746 New Albany, IN 47150
(714) 964-7400 (213) 631-5152 (812) 945-0211
Thomas & Betts Corp.
Kycon Cable & Connector 920 Route 202 Bevmar Industries, Inc. Samtec Inc.
1887 O'Toole Avenue, C103 Raritan, NJ 08869 1 John Clarke Rd. P.D.Box 1147
San Jose, CA 95131 (201) 469-4000 Middletown, RI 02840 New Albany, IN 47150
(408) 4$5-1110 (401) 849-4803 (812) 944-6733
Wells Electronics, Inc.
Maxconn Inc. 1701 South Main Street Electronic Molding Corp. Texas Instruments
1855 O'Toole Ave., 0102. South Ben~,IN 46613 96 Mill Street CSD Marketing, MS 14-1
San Jose, CA 95131 (219) 287-5941 . Woonsocket, RI 02895 Attleboro, MA 02703
(408) 4$5-8666 (401) 769-3800 (617) 699-5206
Yamaichi - Nepenthe
Methode Electronics Inc. 2471 E. Bayshore Road, Garry Electronics Thomas & Betts Corp.
1700 Hicks Road Suite 600 9 Queen Anne Court 920 Route 202
Rolling Meadows, IL 47150 Palo Alto, CA 94303 Langhorne, PA 19047-1803 Raritan, NJ 08869
(312) 392-3500 (415) 856-9332 (215) 949-2300 (201) 469-4000

Mark Eyelet Inc. Yamaichi - Nepenthe

63 Wake lee Road 2471 E. Bayshore Road,
Wolcott, CT 06716 Suite 600· Palo Alto, CA 94303
1973 (415) 856-9332
(203) 756-8847
c;
2-151
 Component Selection &
Ordering Information

XC2064

XC2018

XC3020

XC3030

XC3042

XC3064

XC3090

197201

XC1736-PD8C Plastic 8 Pin, Mini-DIP -40°C to 85°C COMPATIBLE PACKAGE OPTIONS

XC1736-CD8M Ceramic 8 Pin, Mini-DIP -55°C to 125°C
A range of Xilinx LCA devices is available in identical
LCA Temperature Options
packages with identical pin-outs. A design can thus be
Symbol Description Temperature started with one device, then migrated to a larger or
C Commercial O°Cto 70°C smaller chip while retaining the original footprint and
I Industrial -40°C to 85°C PC-board layout.
M Military -55°C to 125°C Examples: PLCC 68: 2064-2018-3020-3030
B Military MIL-STD-883, Class B PLCC84: 2018-3020-3030-3042
PGA84: 2018-3020-3030-3042
PQFP 100: 3020-3030-3042
CQFP100: 3020-3030-3042
ORDERING INFORMATION PGA 132: 3042-3064
Example:

Device Type

Toggle
. T JT1L
XC2064-70PC68C

T~,..."
Range

Number of Pins
Note, however, that the XC2000 and XC3000 families
differ in the position of XTL 1 as well as three parallel
address bits (6, 7 and 11) and most of the data pins used
in parallel master mode.
XC2018 and XC3020 are not available in PGA68, since
Rate the PGA84 is the same size and offers more I/O.

Package Type Note that a PLCC in a socket with PGA footprint generates
a printed circuit board pin-out different from a PGA device.
1972

2-152
 SECTION 3

Quality, Testing, Packaging

1 Programmable Gate Arrays

2 Product Specifications

3 Quality, Testing, Packaging

4 Technical Support

5 Development Systems

6 Applications

7 Article Reprints

8 Index
 Quality Testing, and
E:XILIXX Packaging

Quality Assurance and Reliability ........................................................ 3-1

Quality Assurance Program ........................................................... 3-1
Reliability Introduction .................................................................... 3-1
Die Qualification ....................................................................... 3-2
Package Integrity and Assembly Quality .................................. 3-2
Description of Tests .................................................................. 3-4
Data Integrity ................................................................................. 3-7
Alpha Particle Sensitivity .......................................................... 3-8
Electro-Static Discharge ................................................................ 3-8
Latch-up ......................................................................................... 3-9
High-Temperature Performance .................................................... 3-9
Radiation Hardness Test Results .................................................. 3-10
Test Methodology ................................................................................ 3-11
Memory Cell Testing ...................................................................... 3-12
Interconnect Testing ...................................................................... 3-12
lOB and CLB Testing ..................................................................... 3-14
Testing the Speed of the LCA ........................................................ 3-14
Packaging ........................................................................................... 3-17
User I/O Availability ....................................................................... 3-17
SpeedlTemperature Selections ..................................................... 3-17
Ceramic/Plastic Quad Flat Pack .................................................... 3-18

1962
 Quality Assurance
and Reliability

QUALITY ASSURANCE PROGRAM customers' systems applications. An extenSive, on-going

reliability-testing program is used to predict the field per-
All aspects of the Quality Assurance Program at Xilinx formance of our devices.
have been designed in compliance with the requirements
of Appendix Aof MIL-M-38510. This program emphasizes These tests provide an accelerated means of emulating
heavily the aspects of operator training and certification, long-term system operation in severe field environments.
the use of "accept only on zero defects" lot sampling plans, From the performance of the devices during these tests,
and extensive audits of both internal departments and predictions of actual field performance under a variety of
outside suppliers. conditions can be calculated.

Xilinx utilizes the world-class wafer fabrication facilities of ThiS report describes the nature and purpose of the
Seiko-Epson's plant in Fujimi, Suwa, Japan and the high- various reliability tests performed on finished devices.
volume assembly resources of ANAM in Seoul, the Updated summaries are available upon request from the

•
Republic of Korea. Periodic quality assurance audits of Quality Assurance and Reliability Department at Xilinx.
these facilities to the full requirements of MIL-STD-883 are
routinely performed.
OUTLINE OF TESTING
Xilinx calculates its outgoing component quality level,
expressed in PPM (defective parts per million devices Qualification testing of devices is performed to demon-
shipped), using the industry-standard methods now strate the reliability of the die used in the device, and the
adopted by JEDEC and published in JEDEC Standard 16. materials and methods used in the assembly of the device.
These figures of merit are revised and published quarterly Testing methods are derived from and patterned after the
by Xilirix Quality Assurance and are available from local methods specified in MIL-STD-883.
manufacturer's representatives or from Xilinx. These
summary data are available for downloading from the Referral to the test methods of MIL-STD-883 is not in-
Xilinx Electronic Bulletin Board at (408) 559-9327 [1200/ tended to imply that non hermetic products comply with the
2400 baud; 8 data bits; no parity; 1 stop bitl supporting all requirements of MIL-STD-883. These test methods are
of the following communications protocols: ASCII, Kermit, recognized industry-wide as stringent tests of reliability
XModem, -CRC, and Telink. and are commonly used for nonmilitary-grade semicon-
ductor devices, as well as for fully compliant military-grade
products.
RELIABILITY INTRODUCTION
Hermetic packages are qualified using the test methods
From its inception, Xilinx has been committed to deliver- specified in MIL-STD-883. The Group D package qualifi-
ing the highest quality, most reliable programmable gate cation tests are performed on one lot of each package type
arrays available. A strong Quality Assurance and Reliabil- from each assembly facility every twelve months.
ity program begins at the initial design stages and is carried
through to final shipment. The final proof of our success is A summary of the reliability demonstration tests used at
in the performance of the Logic CelJTM Array (LCA) in our Xilinx is contained in Table 1.

3-1
Quality Assurance and Reliability

DIE QUALIFICA TION

Name of Test Test Conditions Lot Tolerance Percent Defective

Minimum Sample Size!
Maximum Acceptable Failures

1. High Temperature Ufe 1000 hr min. equivalent at temperature = 125°C LTPD = 5, s = 105, c = 2
Actual test temperature = 145°C
Max. rated operating voltage.
Ufe test circuit equivalent to MIL-STD-883

2. Biased Moisture Ufe 1000 hr min. exposure LTPD = 5, s = 105, c = 2

T = 85°C, RH = 85%
Max. rated operating voltage.
Biased moisture life circuit equivalent to MIL-STD-883

NON-HERMETIC PACKAGE INTEGRITY and ASSEMBLY QUALIFICATION

Name of Test Test Conditions Lot Tolerance Percent Defective

Minimum Sample Size!
Maximum Acceptable Failures

3. Unbiased Pressure Pot 96 hr min. exposure LTPD = 5, s = 105, c = 2

T = 121°C, P = 2 atm H,o sat.
4. Thermal Shock MIL-STD-883, Method 1011, Condo C LTPD = 7, s = 75, c = 2
-65°C to + 150°C
100 cycles

5. Temperature Cycling MIL -STD-883, Method 1010, Condo C LTPD=5, s=105,c=2

-65°C to +150°C
200 cycles

6. Salt Atmosphere MIL-STD-883, Method 1009, Condo A s = 25, c= 0

24 hrs

7. Resistance to Solvents MIL-STD-883, Method 2015 s = 4, c= 0

8. Solderability MIL-STD-883, Method 2003 s= 15, c=o

Table 1A_ Reliability Testing Sequence for Non-Hermetic Logic Cell Arrays

3-2
 HERMETIC PACKAGE INTEGRITY and ASSEMBL Y QUAL/FICA TlON

Name of Test Test Conditions Lot Tolerance Percent Defective

Minimum Sample Size/
Maximum Acceptable Failures

1. Subgroup D1: Physical MIL-STD-883, Method 2016 LTPD = 15, s = 34, c = 2

Dimensions

2. Subgroup D2 LTPD = 15, s = 34, c = 2

a. Lead Integrity MIL-STD-883, Method 2028
b. Seal (fine and gross leak) MIL-STD-883, Method 1014
(not required for PGA's)

3. Subgroup D3 LTPD = 15, s = 34, C = 2

a. Thermal Shock-iS cycles MIL-STD-883, Method 1011, Condo B
b. Temp. cycling-100 cycles MIL-STD-883, Method 1010, Condo C
C. Moisture Resistance MIL-STD-883, Method 1004
d. Seal (fine & gross leak) MIL-STD-883, Method 1014
e. Visual Examination MIL-STD-883, Method 1004 and Method 1010.
f. End-point electricals Group A, subgroup 1

4. Subgroup D4 LTPD = 15, s = 34, C = 2

a. Mechanical Shock MIL-STD-883, Method 2002, Cond. B

•
b. Vibration, Variable Freq. MIL-STD-883, Method 2007, Condo A
C. Constant Acceleration MIL-STD-883, Method 2001, Condo E
min, Y, only
(Cond. D for large PGAs)
d. Seal (fine & gross leak) MIL-STD-883, Method 1014
e. Visual Examination MIL-STD-883, Method 1010
f. End-point electricals Group A, subgroup 1

5. Subgroup D5 LTPD = 15, S = 34, C = 2

a. Sah Atmosphere MIL-STD-883, Method 1009, Condo A
b. Seal (fine & gross leak) MIL-STD-883, Method 1014
C. Visual Examination MIL-STD-883, Method 1009

6. Subgroup D6:
Internal Water Vapor Content MIL-STD-883, Method 1018,5000 ppm S = 3; c= Oor
water at 100°C S = 5; C = 1

7. Subgroup D7: LTPD = 15, S = 34 leads,

Lead Finish Adhesion MIL-STD-883, Method 2025 =
(3 device min.) C 0

8. Subgroup D8:
Lid Torque N/A to Xilinx packages N/A to Xilinx packages

Table 1 B. Reliability Testing Sequence for Hermetic Logic Cell Arrays

3-3
Quality Assurance and Reliability

DESCRIPTION OF TESTS damage from alternate exposure to extremes of tem-

perature or to intermittent operation at very low tem-
Die Qualification peratures. The range of temperatures is -:65°C to
+ 150°C. The transition time is longer than that in the
1. High Temperature Life This test is performed to Thermal Shock test but the test is conducted for many
evaluate the long-term reliability and life characteris- more cycles.
tics of the die. It is defined by the Military Standard
from which it is derived as a "Die-Related Test" and is 6. Salt Atmosphere This test was originally designed
contained in the Group C Quality Conformance Tests. by the US Navy to evaluate resistance of military-
Because of the acceleration factor induced by higher grade ship board electronics to corrosion from sea
temperatures, data representing a large number of water. It is used more generally for nonhermetic in-
equivalent hours at a normal temperature of 70°C can dustrial and commercial products as a test of corro-
be accumulated in a reasonable period of time. Xilinx sion resistance of the package marking and finish.
performs its High Temperature Life test at a higher
temperature, 145°C, than the more common industry 7. Resistance to Solvents This test is performed to
practice of 125°C. For comparison, the Reliability evaluate the integrity of the package marking during
Testing Data Summary in Table 2 gives the equivalent exposure to a variety of solvents. This is an especially
testing hours at 125°C. important test, as an increasing numberof board-level
assemblies are subjected to severe conditions of
2. Biased Moisture Life This test is performed to evalu- automated cleaning before system assembly opera-
ate the reliability of the die under conditions of long- tions occur. This test is performed according to the
term exposure to severe, high-moisture environments methods specified by MIL-STD-883.
which could cause corrosion. Although it clearly
stresses the package as well, this test is typically 8. Solderability This test is performed to evaluate the
grouped under the die-related tests. The device is solderability of the leads under conditions of low sol-
operated at maximum-rated voltage, 5.5 VDC, and is dering temperature following exposure to the aging
exposed to a temperature of 85°C and a relative hu- effects of water vapor.
midity of 85% throughout the test.
9. Vibration, Variable-Frequency This test is per-
Package Integrity and Assembly Qualification formed to evaluate the resistance of the completed
assembly to vibrations during storage, shipping, and
3. Unbiased Pressure Pot This test is performed at a operation.
temperature of 121°C and a pressure of 2 atm. of satu-
rated steam to evaluate the ability of the plastic encap-
sulating material to resist water vapor. MOisture pene- TESTING FACILITIES
trating the package could induce corrosion of the
bonding wires and nonglassivated metal areas of the Xilinx has the complete capability to perform High Tem-
die [bonding pads only for Xilinx LCAs]. Under ex- perature Life Tests, Thermal Shock, Biased Moisture Life
treme conditions, moisture could cause drive-in and Tests, and Unbiased Pressure Pot Tests in its own Relia-
corrosion under the glassivation. Although it is difficult bility Testing Laboratory. Other tests are being performed
to correlate this test to actual field conditions, it pro- by outside testing laboratories with DESC laboratory suita-
vides a well-established method for relative compari- bility for each of the test methods they perform.
son of plastic packaging materials and assembly and
molding techniques. SUMMARY
4. Thermal Shock This test is performed to evaluate
the resistance of the package to cracking and resis- The Table 2 testing data shows the actual performance of
tance of the bonding wires and lead frame to separa- the Logic Cell Arrays during the initial qualification tests to
tion or damage. It involves nearly instantaneous which they have been subjected. These test results dem-
change in temperature from -65°C. to +150°C. onstrate the reliability and expected long life inherent in the
nonhermetic product line. This series of tests is ongoing
5. Temperature Cycling This test is performed to as a part of the Quality Conformance Program on nonher-
evaluate the long-term resistance of the package to metic devices.

3-4
 XILINX Reliability Testing Summary

Device Types: XC2018, XC2064, XC3020 Process/Technology: 1.2 Micron Double Layer Metal CMOS
Die Attach Method: Silver Epoxy Package Type: 68 & 84 Lead PLCC
Molding Compound: Sumitomo 6300H Date: 40, 1988

Equivalent Equivalent
Mean Equivalent Failure Rate
1. High Temperature Life Test Combined Hrs/Device Device Hrs in FIT
145°C Sample Failures at T = 125°C at T = 125°C at Tj = 70°C

765 3 1,041 796,426 56

Mean Hrs Total

2. Biased Moisture Life Test Combined per Device Device Hrs
T = 85°C; RH = 85% Sample Failures atT = 85°C at T = 85°C

105 1 1000 104,988

3. Unbiased Pressure Pot Test Combined Mean Hrs Total

+ 121°C, 2 atm sat. steam Sample Failures per Device Device Hrs

504 2 504 105,860

•
4. Thermal Shock Test Combined Mean Cycles Total
-65°C/+ 150°C Sample Failures per Device Device Cycles
100 cy. (min)
524 1 469 245,700

5. Temperature Cycling Test Combined Mean Cycles Total

-65°C/+ 150°C Sample Failures per Device Device Cycles
100 cy. (min)
254 0 334 84,900

6. Salt Atmosphere Test Combined Mean Hrs Total

MIL-STD-883, Method 1009, Sample Failures per Device Device Hrs
Condo A
105 0 24 2,520

7. Resistance to Solvents Test Combined

MIL-STD-883, Method 2105 Sample Failures

28 0

8. Solderability Test Combined

MIL-STD-883, Method 2003 Sample Failures

51 0

Table 2. Reliability Testing Summary, 1.2 Micron

3-5
Quality Assurance and Reliability

XILINX XC2018, XC2064, and XC3020 Reliability Testing Summary, Initial Lots

Device Type: XC2018, XC2064, and XC3020 Processrrechnology: 1.2 Micron Double Layer Metal CMOS
Die Attach Method: Silver Epoxy Package Type: 68 & 84 Lead PLCC
Molding Compound: Nitto MP 150 SG Date: 2Q, 1988

Equivalent Equivalent
Mean Equivalent Failure Rate
1. High Temperature Life Test Combined Hrs/Device Device Hrs in FIT
145°C Sample Failures atT = 125°C at T =125°C at Tj =70°C

1,964 42 2,491 4,892,851 131

Table 2a. Reliability Testing Summary, 1.2 micron

3-6
DATA INTEGRITY This explains the basic cell, but how is the Logic Cell Array
user assured of high data integrity in a noisy environment?
Memory Cell Design We must consider three different situations: normalopera-
tion, a write operation and a read operation. In the normal
An important aspect of the Logic Cell Array's reliability is operation, the data in the basic memory element is not
the robustness of the static memory cells used to store the changed. Sincethe two circularly linked inverters that hold
configuration program. the data are physically adjacent, supply transients resultin
only small relative differences in voltages. Each inverter is
The basic cell is a single-ended five-tranSistor memory
truly a complementary pair of transistors. Therefore,
element (Figure 1). By eliminating a sixth transistor, which
whether the output is high or low, a low impedance path
would have been used as a pass transistorforthe comple-
exists to the supply rail, resulting in extremely high noise
mentary bit line, a higher circuit density is achieved.
immunity. Power supply or ground transients of several
During normal operation, the outputs of these cells are
volts have no effect on stored data.
fixed, since they determine the user configuration. Write
and readback times, which have no relation to the device The transistor driving the bit line has been carefully de-
performance during normal operation, will be slower with- signed so that whenever the data to be written is opposite
out the extra transistor. In return, the user receives more the data stored, it can. easily override the output of the
functionality per unit area. feedback inverter. The reliability of the write operation is

Vee

CONFIGURATION DATA SHIFT REGISTER

0N_l- - - - - - - - - - \ Ds

DATA CLOCK - -
CK
SEL
Q I--~--__t

------t--+--I---+-+--4----t"'----t--
Ds

DR

.CK
SEL
Q I--~--

ADDRESS
READ

•
a.-I
I
CLOCK I

PRECHARGE - - -------+----+--4------1---

CONFIGURATION
MEMORY CELL ADDRESS
CIRCUIT SHIFT REGISTER '

Q
WORDUNE
DRIVER
WORDN + 1 - - --------,---+----~--f---

110901

BITM+1

Figure 1. Configuration Memory Cell

3-7
Quality Assurance and Reliability

guaranteed within the tolerances of the manufacturing 5.3 x 107 particles/hour = 3.6 x 1010
process. 0.0015 particles/hour
Inthe read mode, the bit line, which has a significant amou nt
The 0.61 hours oftest time without error then corresponds
of parasitic capacitance, is precharged to a logic one. The
to 2.2x1 010 hours or 2.5 million years of error-free operation.
pass transistoristhen enabled bydrivingtheword line high.
If the stored value is a zero, the line is then discharged to Most ceramic packages are specified to emit less than 0.01
ground. Reliable reading ofthe memory cell is achieved by alpha particleslcm2/hrwhich is aboutthree times more than
reducing the word line high level during reading to a level the plastic compound. For an XC2064 in a ceramic pack-
that insures that the cell will not be disturbed. age, this still results in error-free operation for almost a
million years.
Alpha Particle (Soft Error) Sensitivity:

The CMOS static memory cell was designed to be insensi- The highest rate of alpha particle emission comes from the
tive to alpha particle emisSions. To verify that this design sealing glass used in cerdip packages and some ceramic
goal was achieved, the following tests were performed. packages (frit lids). For instance, KCIM glass emits about
24 alpha particles/cm2/hr. Low alpha glasses are specified
A one microcurie alpha particle source (Americum 241) at 0.8 alpha particleslcm2/hr.
was placed in direct contact with the top surface of an
XC2064 die. This allows the die to capture at least 40% of Because these glasses are used onlyforthe package seal,
the emisSions from the radiation source. The following se- they present a relatively small emitting cross section to the
quence of tests was performed: die (less than 0.1 cm2 square). A low alpha glass would
therefore cause fewer than 0.8 alpha particle hits per hour.
1. A complex pattern containing roughly 50% logic ones The acceleration factor is then 6.6x1 08 , which translates to
was loaded into the XC2064. The operating conditions about 46,000 years without an error.
were 25°C and 5.0 volts.
The memory cell of the Xilinx Logic Cell Array has been
2. A pause of variable duration was allowed. designed so that soft errors caused by alpha particles can
safely be ignored.
3. The entire contents of the XC2064 were read back and
compared with the original data.
ELECTROSTATIC DISCHARGE
Validation tests to ensure that the test setup would detect
errors were performed before and after the alpha particle Electrostatic discharge (ESD) protection for each pad is
tests. The results are as followS: provided by a circuit that uses forward and reverse biased
distributed resistor-diodes (Figure 2). In addition, inherent
Time Readback Total Time Number
capacitance integrates any current spikes. This gives suf-
Test Duration Time Exposed of Errors
ficient time for the diode and breakdown protections to
1 10 sec 70 sec SO sec 0 provide a low impedance path to the power-supply rail.
2 120see 70 sec 190 sec 0 Geometries and doping levels are optimized to provide
3 300 sec 70 sec 370 sec 0 sufficient ESD protection for both positive and negative
4 1500 sec 70 sec 1570 sec 0 discharge pulses.

Total 2210 sec

Vee
Analysis

A one microcurie source emits 3.7x1 04 alpha particles per

second. Assuming that 40% of these are captured by the
XC2064 during this experiment; this corresponds to
5.3x107 alpha particles per hour.
,.-p-A-o---,r--- I" / ' - - - - " / 'A/'-"'---......
v TO INTERNAL
CIRCUITRY

l~o
The alpha particle emiSSion rate of the molding compound
used by Xilinx is specified to emit fewer than 0.003 alpha
particles per square centimeter per hour (alpha particles/
cm2/hr). The surface area of the XC-2064 die is less than
0.5 cm 2, so less than 0.0015 alpha particles per hourwill be 1109 02
captured by the XC2064in normal operation. The error rate
acceleration in this test is therefore equal to: Figure 2. Input Protection Circuitry

3-8
LATCHUP

Latchup is a condition in which parasitic bipolar transistors

form a positive feedback loop (Figure 3), which quickly
reaches current levels that permanently damage the de-
vice. Xilinx uses techniques based on doping levels and
circuit placement to avoid this phenomenon. The cross
section of a typical transistor (Figure 4) shows several PAD
featu res. The beta of each parasitic transistor is minimized
by increasing the base width. This is achieved with large
physical spacings. The butting contacts effectively short
the n+ and p+ regions for both wells, which makes the VBE
of each parasitic very close to zero. This also makes the
parasitic transistors very hard to forward bias. Finally, each
well is surrounded by a dummy collector, which forces the
VCE of each parasitic almost to zero and creates a structu re
in which the base width of each parasitic is large, thus
making latchup extremely difficult to induce.

1109 03
HIGH TEMPERATURE PERFORMANCE

Although Xilinx guarantees parts to perform only within the

•
specifications of the data sheet, extensive high tempera-
ture life testing has been been done at 145°C with excellent Figure 3. SCR Model
results. In plastic packages, the maximum junction tem-
perature is 125°C.

PAD

NSUBSTRATE DUMMY COLLECTORS

1109 04

Figure 4. CMOS Input Circuit Layout

3-9
Quality Assurance and Reliability

RADIATION HARDNESS-GAMMA TOTAL DOSE TEST

Outline of Testing Testing closely followed the procedures of MIL-STD-

883C, Method 1019, but was not strictly in full compliance
Xilinx has conducted a series of radiation hardness tests with the requirements since the irradiation and final test
to demonstrate the capability of the 1.2 micron CMOS sites were in different locations. The devices were trans-
process being used to produce both the XC2000 and ported by air (with bias continually applied) from the
XC3000 family of devices. The test vehicle used was the location in southern California, where they had been
XC3020-70PC84C. Other devices in other packages are exposed to the radiation, to the Xilinx test facility in San
expected to show similar results. Jose. Up to two hours elapsed, from the time of exposure
to final testing, due to air transportation.
Four random devices taken from normal production lots
were individually subjected to gamma radiation levels In summary, four devices were tested following exposure
under 5V Vee bias in Power-Down Mode. The four to a Cobalt 60 gamma radiation source. The data obtained
radiation levels were 20k, 30k, 50k and 75krads (Si). Each from these tests indicate that devices are capable of
device was exposed to a different radiation level. The normal operation upto the 50krad (Si) total dose level. The
radiation was applied at the rate of 1Orads (Si) per second. test results suggest that Xilinx XC2000 and XC3000 de-
After exposure each device was functionally tested in a vices manufactured on the 1.2 micron CMOS process are
system althe irradiation site. A device failure is defined as acceptable in any application requiring a radiation design
inability to load configuration data and begin functional level of 50krad (Si) or less.
operation. The devices were also tested at Xilinx after ir-
radiation. Standard DC functionality and AC parametric Xilinx personnel did not verify the total radiation dosage
tests were performed on the Xilinx production tester. Both applied the calibration of the Cobalt 60 source, or the ap-
the system and the device tests showed device failure at plication of bias during irradiation. These factors, coupled
the 75krad (Si) level. Test results are summarized in with the two hour test time lag and the small sample size,
Table 1. make these tests not fully conclusive. Further testing is
planned.
Table 1

Gamma System
Device Exposure Functional Tester
Number Level Test Results

20krad (Si) Passed Passed

2 30krad (Si) Passed Passed
3 50krad (Si) Passed Passed
4 75krad (Si) Failed" Failed"
" Would not reconfigure
Total Dose Level: 50krad (SI)

3-10
 Test Methodology

Xilinx is committed to providing the highest level of quality time-consuming and expensive iterations in orderto reach
and reliability for the Logic Cell™ (LCA) Array. Quality is even 80% fault coverage. The cost of greater coverage is
best assured by taking the necessary steps to achieve often prohibitive. In production, many gate array vendors
zero defects. Comprehensive testing confirms that every either limit the number of vectors allowed or charge for
Logic Cell Array is free from defects and conforms to the using additional vectors.
data sheet specifications. The memory cell design as-
sures integrity of the configuration program. The replacement of all storage elements with testable
storage elements: known as scan cells, improves testabil-
ity. Although this technique can reduce the production
TESTING testing costs, it can add about 30% more circuitry, de-
crease performance by up to 20%, and increase design
As quality consciousness has grown among semicon- time.
ductor users, awareness of the importance of testability
has also increased. Testing for standard components, Logic Cell Arrays: The testability of the LogiC Cell Array
including memories and microprocessors, is accom- is similar to other standard products, including micro-
plished with carefully developed programs which exhaus- processors and memories. This is the result of the design
tively test the function and performance of each part. For and the test strategies:
reasons explained below, most application specific ICs
cannot be comprehensively tested. Without complete DeSign strategy:
testing, defective devices might escape detection and be
installed into a system. In the best case, the failure will be • Incorporates testability features because each func-
detected during system testing at a higher cost. In the tional node can be configured and routed to outside
worst case, the failure will be detected only after shipment pads
of the system to a customer. • Permits repeated exercise of the part without removing
it from the tester because of the short time to load a new
Testing advantages of the Logic Cell Array can be illus- configuration program
trated through comparison with two other application • Produces a standard product which guarantees that
specific ICs: Erasable Programmable Logic Devices every valid configuration will work.
(EPLDs) and gate arrays.
Test strategy:
EPLDs: In order to test all memory cells and logic paths of
programmable logic devices controlled by EPROM mem- • Performs reads and writes of all bits in the configuration
ory cells, the part must be programmed with many different memory, as in memory testing
patterns. This in turn requires expensive quartz lid pack- • Uses an efficient parallel testing scheme in which mul-
ages and many lengthy programltesVerase cycles. To tiple configurable logic blocks are fully tested simultane-
save time and reduce costs, this process is typically ously
abbreviated. • Is exhaustive since the circuits in every block are iden-
tical
Gate Arrays: Since each part is programmed with metal
masks, the part can only be tested with a program tailored The Logic Cell Array user can better appreciate the Logic
to the specific design. This in turn requires that the Cell Array test procedure by examining each of the testing
designer provide sufficient controllability and observability requirements:
for comprehensive testability. The design schedule must
also include time for the development of test vectors .and • All of the configuration memory bits must be exercised
a test program specification. If the gate array user requires and then verified. This is performed using readback
a comprehensive test program, then he must perform mode.
exhaustive and extensive fault simulation and test grad- • All possible process-related faults, such as short cir-
ing. This requires substantial amounts of expensive cuits, must be detected. The Logic Cell Array is config-
computer time. Additionally, ittypically requires a series of

3-11
Test Methodology

ured such that every metal line can be driven and Memory Cell Testing
observed directly from the input/output pads.
• All testing configurations must provide good controllabil- The static memory cells have been deSigned specifically
ity and observability. This is possible since all configur- for high reliability and noise immunity. The basic memory
able logic blocks can be connected to input/output pads. cell consists of two CMOS inverters and a pass transistor
This makes them easy to control by testing different used for both writing and reading the memory cell data
combinations of inputs and easy to observe by compar- (See Figure 1). The cell is only written during configura-
ing the actual outputs with expected values. tion. Writing is accomplished by raising the gate of the
pass transistor to Vcc and forcing the two CMOS inverters
These points bring out an important issue: the Logic Cell to conform to the data on the word line. During normal
Array was carefully designed to achieve 100% fault cover- operation the memory cell provides continuous control of
age. With the Xilinx testing strategy, the number of design the logic, and the pass transistor is "off" and does not affect
configurations needed to fully test the Logic Cell Array is memory cell stability. The output capacitive load and the
minimized and the test fault coverage of the test patterns CMOS levels of the inverters provide high stability. The
is maximized. In addition, the user's design time is memory cells are not affected by extreme power supply
reduced because the designer does not have to be con- excursions.
cerned about testability requirements during the design
cycle. The Logic Cell Array concept not only removes the
burden of the test program and test vector generation from
the user, but also removes the question of fault coverage
and eliminates the need for fault grading. The Logic Cell
Array is a standard part that guarantees any valid design
will work. These issues are critically important in quality-
sensitive applications. The designer who uses the Logic
Cell Array can build significant added value into his design
by providing higher quality levels.
Figure 1. Configuration Memory Cell
TESTING OF THE LOGIC CELL ARRAY

The logic cell array is tested as a standard product. Every The memory cells are directly tested in the logic cell array
device is tested for: 1) 100% functionality; 2) D.C. par- with threetest patterns that are equivalentto those used on
ametrics; and 3) speed. This allows the end-userto design a random access memory device. The first test pattern
and use the logic cell array without worrying about testing writes 95% of all the RAM cells to a logical zero and then
for a particular application. reads each RAM cell back to verify its contents. The
second test pattern writes 95% of all the RAM cells to a
The stralegy for testing the logic cell array is to test the logical one and also verifies the contents. The third pattern
functionality of every element inside the LCA. These is used to verify that all I/O and configurable logic blocks
elements consist of memory cells, metal interconnects, can have their logic value read back correctly. All RAM
transistor switches, bidirectional buffers, inverters, decod- cells are thus written and verified for both logic levels.
ers, and multiplexers. If each element is functional, then
the user's design will also be fu nctional if the proper design Interconnect Testing
procedures are used.
The programmable interconnect is implemented using
The static memory cells and the symmetry of the logic cell transistor switches to route signals through a fixed two
array make it 100% testable. The logic cell array can be layer grid of metal conductors. The transistor switches
programmed and reprogrammed with as many patterns as "on" or "off" depending on the logic value of the static
required to fully test it. This is done with as many as 50 memory cell that controls the switch. The interconnect is
configurationltest patterns. Each configurationltest pat- tested with configuration/test patterns that: 1) Test for
tern consist of: 1) A set of test vectors that configure the continuity of each metal segment; 2) Test for shorts
LCA with a hardware design that utilizes specific elements; between metal segments; and 3) Check the ability for each
and 2) A set of test vectors that exercise those specific switch to connect two metal lines. This can be accom-
elements. The symmetry of the LCA allows the test plished with a pattern similar to Figure 2. Each intercon-
engineer to develop the test for one CLB or lOB and then nect line will be set to a logic 'one' while the others are set
apply it to all others. All configuration/test patterns are to logic zero. This checks for shorts between adjacent
exercised at both Vcc minimum and maximum. interconnects while at the same time checking for continu-
ity of the line.

3-12
Print World: PATN11.LCA (2018PC84-70), XACT 2.05b Eng, Wed Mar 02 16:28:18 198!Print World: PATN11.LCA (2018PC84-7

~ TF lW~ LWtW rw~ ~W~~W ~W ~.~ ~~ ~~

II ~

u ~ u rn
;:: -<
~ ~ -.J -.JL f---1'- --l '---

ru---, u ~ U -=ii U U ID AH

(l U U U U U U UL- ~
(]
~U U
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ru jL
{(l U U U U 0 U U U U illID
1U ~_I~ ID
U ~ U rrf1 U r=f1 U rf1 U ID
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liJ ~U
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U U U U U EJ U U L~ ro~
~
ID
j[J
U U
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IJ --1LJ t:jGB
U U U 0 U U
U fl! t:J ~
~ U - U:f1
0
UJ
~~
~
~
Qtl ID
r-
•
Ill] U U U U U U U U u
in
liJ f-JLJ
ID
~
00
rr--
fil U U U U U U U U L ~ r-

ID ~ lQ u -U u Lf:l Ll ~ l~ Lf1 L} LfID

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I, I il h r I h I rJ
~ H33
~
034 ~®l ~~
tt-1
~m rS~~[0][~~ em arm l~~ m~
~I051 0 [U
Figure 2.. Interconnect Test Pattern

3-13
Test Methodology

I/O Block Testing TESTING THE SPEED OF THE LOGIC CELL ARRAY

Each I/O Block includes registered and direct input paths The speed of the device is checked with configurationltest
and a programmable three-state output buffer. The testing patterns that have been correlated to data sheet A.C.
of these functions is accomplished by several configura- values.
tion/test patterns that implement and test each option that
is available to the user. One method used to test the I/O Most of these patterns are shift registers with interconnect,
blocks is to configure them as a shift register that has a Tri- lOBs and ClBs in the data path (See Figure 4). They are
State control (See Figure 3). This allows a test pattern to designed with the idea that all elements in the path must be
check the ability of each I/O block to latch and output data fast enough for the proper data to get to the next input of
that is derived from eitherthe previous I/O block orfrom the the shift register before the next clock occurs. If any
tester. Several of these patterns are used to exercise element doesn't meet the specified A.C. value, then the
different input and output combinations allowed for each shift register will clock in the wrong data and fail the test.
I/O block. Configurationltest patterns are also used to The complexity of the logic between two shift register cells
precondition the device to test D.C. parameters such as determines the maximum frequency required for the clock
VIH, VIL, VOH, VOL, TTL standby current, CMOS standby pulse input of the shift register. This can be used to reduce
current and input/output leakage. The VOHIVOl Test is the performance requirement of the tester in use. The
done while all outputs are either all low or all High. patterns used consist of a TCKO + TllO + INTERCON-
NECT + TICK for each shift register. This increases the
Conflgurable Logic Block Testing shift register clock pulse separation time to 30 to 40 ns.
The configuration of each pattern is varied so that all of the
Each configurable logic block has a combinatorial logic interconnect, lOBs, and ClBs are tested at speed.
section, a flip-flop section, and an internal control section.
The combinatorial logic section of the logic block uses an
array of RAM cells (16x1 in or 32X1 in) as a look up table HARDWARE TESTING CONSIDERATIONS FOR THE
to implement the Boolean functions. This section is tested LCA
as an array of memory cells. Configuration/test patterns
are used to verify that each RAM cell can be logically Currently the logic cell array is being tested on Sentry
decoded as the output of the array. The flip-flop section of testers. The 68 and 84 pin versions can be tested on a 60
the logic block is tested with configuration/test patterns pin tester with 256K of extended local memory. The 3000
that configure the lCA as shift registers. Each shift series products are being tested on a 120 pin tester with
register pattern will have different data in the look-up 512K of extended local memory.
tables and will have a different pin used as the input to
each shift register. Other configuration/test patterns are
used to implement and test the internal control section.

3-14
 1:'(1Lt)'fJ(
Print World: patn01.lca (2018PC84-70), XACT 2.05b Eng, Wed Mar 02 16:02:02 1988 ',;int World: patnOl.lca (2018PC84

ru ~

U U U U U U U U U U
U U U U U U U U U
U U U U 0 U rl U 0
U U U U U U U 0 U
U U U U 0 U U 0 U
U U U U
U U U U
U rJ U U 0 U
lL] U U U U U
•
U U U U U U U U U U
U U U U U U U U U

Figure 3. lOB Test Pattern

3-15
Test Methodology

Figure 4. Speed Test Pattern

3-16
 Packaging

PACKAGE AND USER I/O AVAILABILITY

Number of User I/O Available

48 PIN 68 PIN 84 PIN 100 PIN 132 PIN 164 PIN 175 PIN
XC2064 40 58
XC2018 58 74
XC3020 58 64 64
XC3030 74 80
XC3042 74 82 96
XC3064 110

•
XC3090 142 144
11128 02

PACKAGE/SPEED/TEMPERATURE SELECTIONS

XC2064

XC2018

XC3020

XC3030

XC3042

XC3064

XC3090

197201

11128

3-17
Packaging

CERAMIC QUAD FLAT PACK (CQFP) PLASTIC QUAD FLAT PACK (PQFP)

The Ceramic Quad Flat Pack (also called Quad Cerpack) The Plastic OuadFlat Pack is an EIAJ standard package.
is a cavity down, pressed ceramic package: The leads are The leads are gull-wing on four sides. It is for surface
gull-wing, on four sides, with 25 Mil pitch. It is for surface mount Commercial applications.
mount Commercial, Industrial, and Military (including
MIL-STD-883 Class B) applications. JEDEC has devel- The initial versions will be 31 Mil (0.8 mm) pitch, 80 leads
oped a standard that Xilinx will follow. and 20 Mil (0.65 mm) pitch, 100 leads. First production is
scheduled for 401988.
The initial version will be a 164 lead package for the
XC3090. First production is scheduled for 10 1989. Other
versions for the rest of the 3000 family will follow with
production early in 1989.

FOR MORE INFORMATION ON SMT International Quality

Technologies, Inc.
The following organizations provide SMT consulting and 4300 Stevens Creek Blvd
training, component part lists, and related services: Suite 203
San Jose, CA 95129
D Brown Associates (408) 246-6071
(Surface Mounting Directory
and SMT: How to Get Started) National Training Center
Box 43 Northhampton Area College
Warrington, PA 18976 3835 Greenpond Rd
(215) 343-0123 Bethlehem, PA 18017
(215) 861-5486
Electronics Manufacturing
Productivity Facility (EMPF) Surface Mount Council
1417 North Norma Street C/O IPC
Ridgecrest, CA 93555-2510 7380 N Lincoln Ave
(619) 446-7706 Lincolnwood, II 60646
(312) 677-2850

3-18
l:XI SECTION 4

Technical Support

1 Programmable Gate Arrays

2 Product Specifications

3 Quality, Testing, Packaging

4 Technical Support

5 Development Systems

6 Applications

7 Article Reprints

8 Index
 Technical Support

Technical Seminars and Users' Group Meetings ............................... .4-1

Video Tapes ........................................................................................ 4-2
Newsletter ........................................................................................... 4-3
Technical Bulletin Board ..................................................................... 4-4
Field Application Engineers ................................................................. 4-6
Training Course ................................................................................... 4-7
XACT Manuals .................................................................................... 4-8
User's Guides ...................................................................................... 4-9

Beyond the technical data in this book, Xilinx provides a material, beginning with Technical Seminars and ending
wealth of additional technical information to LeA users. with detailed Technical Manuals.
The following pages give an overview of the existing 1962
 Technical Seminars and
Users' Group Meetings

'P0'O\o(l

1)'3.(I'Oul':I
" \'0\'3.(10
\.0(1",

1-1J.(iC'(\ 'i'lie(l

•
\>IIi\'3.(lo
,!\'o(e
'P'<»\\ "(O(i(lO \,\'3.i\'3.

1'\\'3.(1\'3. ?'3.00-J'3.

Xilinx sponsors technical seminars at locations throughout Users' Group meetings are intended for experienced
North America, Europe, and Asia. users of Xilinx Programmable Gate Arrays, and empha-
size the use of the various development system tools to
Product-oriented seminars are directed toward new and generate LCA~based designs,
potential users of Programmable Gate Arrays, These
seminars include a basic description of the Logic Cell Contact your local Xilinx sales office, sales representative,
Array architecture and its· benefits of· this technology, or distributor for information about seminars in your area.
Experienced users will also find these seminars useful fOf
learning about newly-released products from Xilinx.

4-1
 Videotapes

A one-hour videotape, entitled "Programmable Gate Ar- speed, density, and cost. Development systems and the
rays: The Ideal Logic Device," is available from Xilinx. The design methodology are discussed in the last third of the
presentation is divided into three main sections. The first presentation, including on-screen demonstrations of
portion of the videotape is an overview of the Logic Cell some of the software tools. Additional videotapes cover-
Array architecture and the development system, including ing specific details are in preparation.
some example applications. The second section contains
a description of the Xilinx product families, a more detailed VHS copies are available in NTSC, PAL, and SECAM
description of the XC3000 series architecture, a descrip- formats; contact your local Xilinx sales office, sales repre-
tion of the LCA configuration modes, and a brief discussion sentative, or distributor.
of programmable gate array performance in terms of

4-2
 Newsletter

II

customersPP~h~p-to-date
letter to su
aVls"lne~sletterinform~tio~erlyteChnical~n~ew:s-;-~;:;;;~ds":~~=:-----·
InSeptember'8 "" started a ua
8 Xlhnx
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1 softwa"re a,.b""" d gives uPdtotregistered
;and a es 0" hardXilinx 01 ,,'evam
work-arounds App r"",110", aod .
n ormation on PC I n revision levels It ware of informatl"on fgazlne articles make thO r user
uSingtiPS andLCA
Xilinx a list
s"
c one compatibility "also carries or the IS a val b
_ ________________ __________

4-3
 Xilinx Technical
Bulletin Board

..,.,,,.
~r_ 'IIVN ~~~":TI~ B)ULLETIN G)OODBYE
Enter this section to send and The file section is divided into Enter this section to read the At this time you can leave a
receive messages. several areas. Enter this "latest and greatest" information message for the system
sectio~6~~~;~d ~~!~~d and on the Xillnx Bulletin Board.
A list of bulletins is auto-
operator. See the M)SG-
Section for instructions on
TYPE:
matically displayed. how to send messages to
other bulletin board users.
E<CR> [E)NTER] TYPE:
To send a message. TYPE:
A<CR> [A)REA]
To list the existing file areas. <BULLETIN#><CR>
To display a specific bulletin
on the screen.
After choosing a file area, you
can now list all the files in this
area.
L<CR> [L)IST]
To list headers of all readable TYPE:
messages in the area. Some
messa98S are private and can F<CR> [F)ILES]
be rea only by the addressee.
To display the available files,
the size of each file in bytes
~~t:~~iedf ~~~criifi~~n of the

R<CR> [R)EPLY]
To reply to a mesage you've
just read.
L<CR> [L)IST]
To locate a file in any acces-
sable. area

• Files. can be uploaded from

any file area by typing:
U<CR> [U)PLOAD]

To provide customers with up-to-date information and an customers. Users with full privilege can read files on the
immediate response to questions, Xilinx provides a 24- bulletin board, download those of interest to their own
hour electronic bulletin board. The Xilinx Technical Bulle- systems or upload files to the XTBB. They can also leave
tin Board (XTBB) is available to all registered XACT messages for other XTBB users.

4-4
 E:XILINX

New bulletin board users must answer a questionnaire The XTBB is based on a bulletin board system called
when they first access the XTBB. After answering the FIDO. FIDO is a menu-driven system-you choose com-
questionnaire callers can browse through the bulletin and mands from menus to decide what happens next. To
general information file areas. Before exiting, they should choose a menu command, simply type the first letterof the
leave a message for the system operator requesting full command and press return <CR>. Listed below are some
access. A caller with a valid XACT protection key will be helpful hints for using the XTBB ..
given full user privileges within 24 hours.
• To perform a sequence of commands, type the firstletter
The software and hardware requirements for accessing of each command, followed by a space, and press
the Xilinx Technical Bulletin Board are: return. For example, typing F A 1 F <CR> [F)ile A)rea
1 F)iles] from the main menu will list all of the files
Baud Rate 1200 or 2400 contained in file area 1.
Character Format 8 data bits, no parity, 1 stop bit
Phone Number (408) 559-9327 • Often the user is asked a question and prompted to
Transfer Protocols ASCII, Kermit, Xmodem, choose between two options (e.g. [yes NO]). The option
-CRC, Telink displayed in all capital letters is the default choice. To
select this option, simply press return. Otherwise, type
Information contained on the XTBB is divided into three your choice and hit return. .
general categories: 1. Bulletins, 2. Files and 3. Messages.
• The XTBB has an extensive help section. To get help,
1. Bulletins contain tidbits of up-to-date information; they type ?<CR>. If you have questions about a specific com-
can be displayed on screen but cannot be downloaded. mand, type the first letter of the command followed by a
question mark and a carriage return (e.g.F?<CR». A
2. Files can contain just about anything (text, user pro- short explanation of the command will be displayed.
grams, etc.). XTBB users can download files to their
own systems or upload files to the bulletin board. • For more information, read the XTBBHLP.TXT file lo-
cated in the GENINFO file area (file area 1).
3. Messages are used to communicate with other XTBB
users; they can be general-available to everyone-or
private.

11578

4-5
E:XIUXX Field Applications Engineers

1270 Oakmead Pkwy. 3100 Arapahoe Rd. 919 N. Plum Grove Rd. 61 Spit Brook Road
Suite 201 Suite 404 Suite A Suite 403
Sunnyvale, CA94086 Boulder, CO 80303 Schaumburg, IL 60173 Nashua, NH 03060
Tel: 408-245-1361 Tel: 303-443-4780 Tel: 312-490-1972 Tel: 603-891-1096

2081 Business Center Dr. 14506 Sandy side Dr. 10704 Spiralwood CI. 65 Valley Stream Parkway
Suite 108 Austin, TX78728 Raleigh, NC 27612 Suite 140
Irvine, CA92715 Tel: 512-251-7148 Tel: 919-846-3922 Malvern, PA 19355
Tel: 714-955-0831 Tel: 215-296-8302

North America Europe

There are 9 Xilinx Field Applications Engineers in the The Xilinx European sales office in England has a resident
locations shown above. Additional technical support is Field Applications Engineer (tel 44-73081-6725).
provided by Headquarters Applications.
Dial (408) 879-5199 or (800) 255-7778. Japan
Xilinx Japan is located in Tokyo and has a resident Field
The world-wide network of Xilinx Representatives and Dis- Applications Engineer (tel 3-297-9191).
tributors also gives technical support. 11578

4-6
 Programmable Gate Array
l:XllINX Training Course

The Xilinx Programmable Gate Array Training Course is a XILINX PROGRAMMABLE GATE ARRAY
comprehensive class covering the Logic Cell Array com- TRAINING COURSE OUTLINE
ponent architecture and Xilinx development systems, with
emphasis on the XC3000 family. This course is intended
for design engineers using Programmable Gate Arrays in DAY 1: I. BASIC ARCHITECTURE
their applications who want to get "up-to-speed" as quickly LOGIC CELL ARRAY ARCHITECTURAL
as possible. OVERVIEW
XC3000 FAMILY ARCHITECTURE
CLB STRUCTURE
Courses run for a full four days, Monday through Thurs- lOB STRUCTURE
day, 9 AM to 5 PM. Course notes, binders and lunches will BASICS OF INTERCONNECT
be provided by Xilinx. A substantial amount of the class DEDICATED PINS
time will be spent performing lab exercises on the Xilinx II. DESIGN METHODOLOGY OVERVIEW
development system (2 students per development sys- III. DESIGN ENTRY
tem). These development systems will be available to the SCHEMATIC CAPTURE
students on the Friday following the class for optional PALASM TO XNF TRANSLATOR
LOGIC OPTIMIZATION
individual work and consultations with the instructor(s). Lab Exercise - Design Entry
DAY 2: IV. DESIGN IMPLEMENTATION
TUITION: The tuition fee is $850 per student. LOGIC PARTITIONING

•
AUTOMATIC PLACE AND ROUTE
ENROLLMENT: To enroll, call the Training Administrator CONFIGURATION BIT STREAM GENERATOR
at Xilinx headquarters (408) 559-7778 or contact your local BIT STREAM FORMAT PROM FORMATTER
Xilinx sales offices. V. LCA ARCHITECTURE
LCA CONFIGURATION LOADING MODES
Class size is limited, so early enrollment is recommended. VI. DESIGN IMPLEMENTATION
Students are not considered to be enrolled until a check, ADVANCED TOPICS
Lab Exercise - Design Implementation
money order or P.O. for the course tuition is received.
Please mail your payment to: DAY 3: VII. DESIGN VERIFICATION
SIMULATION
XACT DOWNLOAD CABLE
Training Administrator XACTOR2 IN-CIRCUIT DEBUGGER
Xilinx READ BACK
2100 Logic Drive VIII. XACT LCA DESIGN EDITOR
San Jose, CA 95124 lab Exercise - Simulation
DAY 4: IX. LCA ARCHITECTURE
Enrollments will be acknowledged with a confirmation XC3000 INTERCONNECT DETAILS
letter. X. SUMMARY
ESTIMATING SIZE AND PERFORMANCE
PREREQUISITES: Students are assumed to have a BENEFITS OF PGA TECHNOLOGY
Lab Exercise - Using the XACT LCA Editor
background in digital logic design and familiarity with PC's
and MS/DOS.

LOCATION: All courses are held at Xilinx corporate

headquarters in San Jose, CA. Xilinx is located approxi-
mately 10 miles from San Jose International Airport and 45
miles from San Francisco International Airport. A detailed
map, including a listing of nearby hotels, will be included
with the enrollment confirmation letter.
TECHOOC 1950

4-7
l:XlliNX XACT Manuals

LCA Development System Manual, Volume 1 and 2

LCA Macro Library

The first two binders of this 3-volume set are the LCA • Demo Board
Development System Manuals, providing exhaustive • Place and Route
reference information on: • XNFto LCA
and information on schematic capture
• Executive Program
The third volume provides detailed information on each
• LCA Editor
of the 2000 and 3000 series XACT macros, including
• Macros
schematics, block count, and examples of typical place-
• Simulator (SILOS)
ments. '
• PROM Formatter
• Bit -Stream Generator

4-8
 User's Guide

•
The Xilinx User's Guide, included with every system, is • Design Entry
a binder with several self-contained application notes Designing LCAs With Boolean Equations
giving practical and tutorial information. • Design Implementation
Configuring Xilinx Logic Cell Arrays
The Users Guide currently has the following manuals: Advanced Design Methodology
• Introduction Fundamentals of Placement and Routing
Development System Hardware Requirements • Design Verification
Basic Design Flow Simulating Bidirectionall/O's Using Silos
Introduction to Hierarchical Design and Merging Readback and Signature Analysis
• Getting Started
• Design Examples
Xilinx Programmable Gate Array Design Flow

This series of notes is being expanded.

1157B

4-9
 1157B

4-10
 SECTION 5

Development Systems

1 Programmable Gate Arrays

2 Product Specifications

3 Quality, Testing, Packaging

4 Technical Support

5 Development Systems

6 Applications

7 Article Reprints

8 Index
 Development Systems

Overview ............................................................................................ 5-3

Design Manager ................................................................................. 5-4
Design Flow .................................................................................. 5-6
Entry .............................................................................................. 5-8
Optimization and Mapping ............................................................. 5-9
Merging .......................................................................................... 5-10
Translation to LCA files .................................................................. 5-11
Placement and Routing ................................................................. 5-12
Bit Stream Generation ................................................................... 5-13
In-circuit Verification ...................................................................... 5-14
CLB Simulation .............................................................................. 5-16
Syste m Architectu re ........................................................................... 5-18
Personal Computer Platform Support ............................................ 5-18
Engineering Workstation Support .................................................. 5-20
PC Hardware Requirements .............................................................. 5-22
Macro Library ..................................................................................... 5-25
Product Briefs
DS53 XACT Design System w/DASH-LCA ................................... 5-32
DS501 XACT Design Implementation System .............................. 5-34
DS31 DASH Interface .................................................................... 5-36
DS311 TTL Library for DASH ........................................................ 5-37
DS32 SCHEMA Interface ......... ;.....•.............................................. 5-38
DS33 Daisy Interface .................. ;.............. ;................................... 5 c39
DS343 Mentor Interface ................................................................. 5-40
DS35 OrCAD/SDT Interface .......................................................... 5-42
DS351 OrCADIVST Interface ........................................................ 5-43
DS22/221 Silos Simulator .............................................................. 5-44
DS112 PROM Programmer ........................................................... 5-45
DS26 XACTOR In-Circuit Verifier .................................................. 5-46
Ordering Information .......................................................................... 5-49

1962

5-2
 Xilinx Design Flow Overview (PC or Workstation)

Step Design Entry

1 and Logic Simulation

Step Design Implementation

2

1955 01
Step
3
Real-time Design
Verification
•

5-3
Development System Overview

Logic Cell Array Design Flow

STEP 1

Design Entry
XNFNETL/ST
and OUTPUT
Logic Simulation

o Open development system supports design entry

and simulation on popular CAE systems
o Interfaces available for PC and workstation-based
environments:
o FutureNet, Schema, CASE, VIEWlogic, PCAD,
OrCAD, etc.
o Mentor, Daisy, Valid
o SilOS, CADAT, OrCAD simulators
o Standard macro library includes over 100 elements
o logic simulation can be used to verify design
function
o ABEL, CUPl, log/IC, PlDesigner state machine
designs may be merged with schematic input

Schematic entry on your PC/workstation 1955

5-4
 Logic Cell Array Design Flow

STEP 2 STEP 3

Design
Real lime
BITSTREAM
Design
Implementation FILE OUTPUT
Verification

o Complete system translates design into program- o LCA user-programmability permits real time, in-circuit
mable gate arrays debugging
o Partitions gale level design logic into Logic Cell Array o Download cable allows LCA to be programmed in-
architecture (CLB/IOB) circuit from deSigner's PC during debugging
o Automatic logic reduction and partitioning removes o XC-DS28 XACTOR In-Circuit Design Verifier reads
unused logic (e.g. unused counter outputs) and displays the internal LCA storage element states
o Logic synthesis software optimizes design for Logic
Cell Array architecture
o All programs run on IBM'" PC/AT'" or compatible
personal computer
o Automated programs run on SUN3 and Apollo
engineering workstation computers

DS28 XACTOR In-Circuit Design Verifier facilitates •

real-time, in-circuit analysis

Automated Design Implementation software

Immediate production

1955

5-5
 Design Flow

The Xilinx Design Manager-Simplifies the Design Flow

• Lets you run all Xilinx software from menus • Provides on-line help for all programs and options
• Automates the entire translation, optimization,
mapping, and merging process

IDesignEntrylTranslatelPlaceRoutelVerifylUtilitieslProfilelQuit I

tXILINX
Design Manager
Copyright 1989 Xilinx Inc.
Includes DOs/16H uersion 3.19
DOS/16M Copyright (C) 1997-1999 by Rational Syste~s. Inc.

Press ESCAPE for Help

Directory: D:\
Part: 3898PG175
Speed: -78
House: HS House

C~d:

1954 01

Design Documentation Extensive On-line Help

The Design Manager maintains an up-to-date The Design Manager contains on-line Help for
text file listing:
• Every menu
• All sub-design files (e.g., "PAL" modules, • Every program
schematics, etc.)
- Every program option
• Which program options are used to
• Design flow suggestions
translate the design

5-6
 Design
Processing Sequence Design Manager Menu Description

CD Design Entry I Create your design by running your schematic editor

while inside the Design Manager

Translate I With one mouse click, automatically

• Translate all schematic pages and "PAL" designs to
Xilinxformat
• Optimize "PAL" designs and state machines with
Logic Synthesis
• Map all logic into CLBs and lOBs
• Merge PAL designs and state machines into
schematic

® Place Route I Run XACT Design Editor and/or APR to place/route

design

@ Place Route I Run MAKEBITS program to compire design into a

configuration bitstream for an LeA

I
•
® Verify Run Simulator (e.g., SILOS) or in-circuit verifier
(e.g., XACTOR) to debug your design

The Xilinx Design Manager provides a highly automated environment for converting your designs into
working programmable gate array designs.

This sequence is illustrated - for a very simple design - on the following pages ...

5·7
Design Flow

Design Entry and XNF Translation

Schematics 1-_ -.. Schematic-to-XNF Translator 1-_ _"

(e.g., "PIN2XNF")

Xilinx Netlist Format

File(s) Containing
All Design logic

"PAL" Text Editor, PAl-to-XNF Translator

ABEL, CUPl, log/IC,I-----J'&J-~
Designs (e.g., "POS2XNF")
PlOesigner, etc.
Third-Party or OS501

1954 03

TITLE DECODE.PDS
IPAD IBUF AUTHOR
COMPANY XILINX
CLOCK DATE
CHIP DECODE PALIOH8
; Input Pins
QO dO dl
DO
; Output Pins
PAl1 out
OPAD
OUT ;Define counter states
01
D 0 D1 OUTPUT LOW STRING ZERO 'Idl * Ida'
WHEN
COUNT = 2 STRING ONE 'Idl * dO'
FILE = DECODE STRING TWO ' dl * Ida'
STRING THREE ' dl * dO'
1954 04

EQUATIONS
out = ZERO + ONE + THREE

Schematics can include any number of "PAL" devices Very simple "PAL" design included in
created with Boolean equations and/or state machines schematic at left with PAL 1 symbol

5-8
 Optimization and Mapping

__________________________________ __ ~·l. X_i_li~_~_O~_~_~_~_in_g

("XNFMAP")
__~~------____~
_
...--_________
• To Merging
Page 5-10

OS501

Optimized
XNF File
Xilinx Logic Xilinx Mapping
Synthesis Program .------t Program
("XNFOPT") ("XNFMAP")

OS501 OS501

1954 05

CLOCK

00
H - t - - - t DO

•
Place'holder
for PAL 1 logic
OBUF OPAD
NOT2
OUT

01
\-c--+----1 01 OUTPUT LOW
WHEN
COUNT =2

DECODECLB
1954 06 1954 07

A graphical representation of the top-level MAP file. A Graphical representation of the CLB containing
Unused logic (if any) has been deleted and the remaining the "PAL" logic. (In a typical PAL design, of
logic has been grouped ("mapped") into Configurable course, several CLBs would be used.)
Logic Blocks and 1/0 Blocks.

5-9
Design Flow

Merging

MAP

Xilinx MAP
•• Top-level and
lower-level
Netlist
Merge
MAP
• design modules Program
l------'------~ ("XNF MERGE") All of the Sub-designs
are Merged into
DS501 Top-level Design

1954 08

DECOOECLB 195409

The merged design contains the CLBs and lOBS for the entire design.

5-10
 Translating to a LeA File

Xilinx
LCA LCA
To Place
Translator 1 - - - - - , - - - - - - + and Route
Page 5-12
("MAP2LCA") Unrouted
Logic Cell Array
OS501 File
To Simulator
' - - - - - (Unit-delay Simulation)
Page 5-16
1954 10

D
{}
D
D
{} a0 0 0 aa0 0 D
0
{} a 0 0 0 0 a 0 0 D0 ~
ot] O[
D
D a0 00 0 0 0 0 [}
Q

0 0 0 0 0 0 0 0 QD
{}
D [
{}
0
a0 0 0 aa0 0 D
0
D
1954 11

0 00 co ro oOCXJO 00 co Cd kO
1954 02

Initially (before Place and Route) the LCA design is

unrouted, and the Configurable Logic and 1/0 blocks are
put in random locations.

5-11
Design Flow

Placing and Routing the LeA file

LCA Automatic Place LCA

and Route Program
("APR")
and/or
XACT Design Editor
Unrouted ("XACT") Placed and Routed
LCAFile LCAFile
08501 To Simulator
L-._ _ _• (Full-timing Simulation
Page 5-16

1954 12

o
For complex deSigns, interactive placement
and routing of critical logic with the XACT
Design Editor is followed by APR to
automatically place/route the remaining
deSign. If necessary, additional interactive
XACT edit on post-APR design is possible.

n fRii""'l
1954 18

A simple placed and routed design (closeup of upper-left

corner of 2064 pe68).

5-12
 Bitstream Generation

Configuration BIT To In-Circuit

Bitstream Design
Compiler ) - - - - - - - - - - Verification
("MAKE BITS") Page 5-14

DS501

1954 14

1111111100100000000000111001111001001111 The BIT file contains the binary configuration data which
programs an LCA to perform the design function.
0011111111011111111111000101111011111101
0111111010110111011110111011111110111111
0111011101101111011111110111111101111111
0011111111111111111111111111011111111111
0111001101110111011101111011111110111111

•
11111111001000000000001110011100D1001111
0011100011110111110111111111111111111111
0011111110111111111101111110111111111111
0011111111111101111111111111101111101111
0111111011101110111111101111111011111110
0111111010110111011 __ .

LCA COl')figuration Bitstream

5-13
Design Flow

Real-time, In-circuit Verification

BIT HEX
Xilinx PROM PROM
Format Generation Pr08rammer
("MAKEPROM") (Xilinx, ata 110, etc.)
Configuration
Bits ream File
DS50t

Xilinx Download Bitstream from PC

Download Cable into LCA for In-circuit Verification
~rovided with (no PROM programming)
ACT Design
Editor)

DS501

Xilinx
In-Circuit Connect Emulator Pod(s) to
Design Target System for Real-time
Verifier In-circuit Verification
("XACTOR")

DS28 1954 15

5-14
In-circuit verification lets you immediately see
how your LeA designs function ...
Program a PROM ...
TARGET SYSTEM

O XC1736
Serial
PROM

Programmed with
Configuration
Data forLCA

1954 16

Use the Download Cable ...

TARGET SYSTEM

Download Cable connects to

LCA control pins (on LCA

o
socket in your target system)

Download Cable
connects to LCA
parallel port of
IBM PC

1954 17

... Or use the XACTOR Design Verifier

The OS28 controller (left) can control up to four

OS26 emulation pods (center). A OS27 emulation
header (right) connects each pod to an LeA socket
in the target system.

5-15
Design Flow

Simulation

LCA XNF SIM

Xilinx XNF-to-
"LCA2XNF" Simulator
Translator Translator
"CLB-Ievel" Simulator
OS501 XNF File Netlist
Simulator
(SILOS,
CAOAT,
OrCAO, etc.)
OAT
OS22, OS351 or
Third Party Stimulusl---~
or Text Editor
Input
Patterns
1954 19

1954 20

Designer defines design inputs.

DECODECLB
1954 09

LCA designs are simulated at the physical CLB level with worst-case timing.
(Nets"inside" CLBs are not generally accessed.)

5-16
 Simulation

Simulation alJows design

analysis under worst-case
temperature, voltage, and
process conditions.

CLOCK

Ql

NOT2

1954 21

Each 1/0 pin and CLB output can be observed with the
simulator. Graphic or text display of signals is generated
in response to input.stimulus for verification of AC
performance and logic behavior of design.

5-17
 System Architecture for Personal Computers
& Engineering Workstations

DESIGN FLOW
An important feature of the Xilinx Development System is
The Xilinx Development System has three major the capability to incorporate design changes which are
components frequently encountered during verification. Small changes
• DESIGN ENTRY can be made to the schematics and then automatically
• DESIGN IMPLEMENTATION processed into the existing design with minimal impact
using a unique "incremental design" capability. Thus the
• HARDWARE CIRCUIT VERIFICATION
deSigner has the complete capability to develop
"production quality" Programmable Gate Arrays resident
T.he Xilinx Logic Libraries and XNF Interface Products on a PC or Engineering Workstation.
support design entry with popular schematic logic drawing
systems supplied by multiple vendors, allowing easy entry
to the Xilinx Development System. Logic entry from PERSONAL COMPUTER SUPPORT
Boolean equations or a variety of state machine language
systems, through PALASM format, is also supported in the Design Entry is supported on a variety of schematic
Design Implementation phase. capture design systems resident on IBM or compatible
personal computers ranging from PC AT to PS/2 as
defined in the hardware system requirements section.
Logic synthesis, partitioning, and optimization programs
These design systems support the Xilinx LogiC Library and
translate the design specifications into CLBs and lOBs
interface to the Xilinx Design Implementation System
unique to the LCNM architecture. Subsequent programs
through several netlist transfer programs.
perform automatic placement and routing (APR) to
complete the LCA array design.
The logic library and interface programs are supported by
Xilinx and a range of third party vendors. Xilinx has
While completely automated implementation is desirable
provided a standard interface file specification (XNF
for low complexity designs, the designer often prefers an
format) to simplify file transfers into the Xilinx Development
interactive process, especially in high performance high
System. Xilinx directly supports the FutureNet DASH or
complexity designs. This interactive editing can range
DASH-LCA (DS31), Schema II (DS32), and OrCAD SDT
from rerouting a few previously automatically routed nets,
(DS35) schematic capture products. An additional
to prerouting critical nets or preplacing CLBs prior to
collection of TTL logic macrofunctions (DS311) is
design completion using APR, to more extensive control
available with the FutureNet DASH & DASH-LCA
over logic partitioning and placement into CLBs. The new
systems.
release of Automated Design Implementation software
gives the designer an option to have direct control over
specific logic mapped into CLBs (partitioning) for better All design implementation (including logic synthesis,
distribution of logic signal routing through the LCA array. partitioning, optimization, APR, interactive XACT design
The XACTfM Design Editor is extremely versatile, ranging edits, timing analysis, and bit-stream compilation) is
from design entry to CLB and signal routing manipulations. exe<X4ed on the PC system. The new Design Manager
This combination of automated and interactive design enhar,fcement to the Design Implementation simplifies the
editing capability is a unique feature provided by Xilinx. selection of command line options with pull-down menus
and on-line help text. Application programs ranging from
schematic capture to APR can be accessed from the
Logic simulation or actual in-circuit emulation allows
Design Manager environment, while the sequence of
functional verification, while timing analysis allows
program commands is generated and stored for
verification of critical timing paths under worst case
documentation prior to execution.
conditions. The system contains a compiler to generate
bit-stream patterns which uniquely configures the LCA
array according to the deSigner's specification.
1956

5-18
 r----------,
DESIGN TIL
LIBRARY
FUTURENET
DASH4
SCHEMAII ORCAD
SDT
I ADDT'L 3RD PARTY I
I SCHEMATIC ENTRY I
ENTRY SYSTEMS
DS311 CADAT
r-------, DS31 DS32 DS35 PCAD
IAr6~/fc~~L, I I
SUSIE
VALID
~P.!-~E~I9~~R~
STATE MACHINE
LANGUAGE
I /I
XILINX LOGIC LIBRARY & XNF INTERFACE
I
I

,------L
VIEWLOGIC
-------'-
- -
I

- - - ..J

r--il---,
I PALASM
I TRANSLATOR
L ______ ..J

LOGIC REDUCTION
PARTITIONING
& OPTIMIZATION
TRANSLA TlON INTO
CLBS&IOBS

DESIGN
IMPLEMENTATION
08501

SILOS

•
GATE LEVEL
SIMULATION
DS22/221

LOGIC
SIMULATION

XILINX
PROGRAMMABLE
GATE ARRAY
HARDWARE
CIRCUIT
IMPLEMENTATION
& VERIFICATION
XACTOR DS28
IN-CIRCUIT DESIGN
VERIFIER

195601

5-19
Designer Support

WORKSTATION SUPPORT interactive XACT editor on the Apollo is being developed,

the PC version is included in the DS501-AP1.
A variety of design systems has been developed for
engineering workstations. Xilinx has developed Logic The bit-stream compiler (MAKEBITS and MAKE PROM) is
Library and Interface Products which allow designs included on the Apollo for completely automated deSign
entered schematically or in state machine language to be flow from Mentor schematic drawings to bit patterns for
implemented in Xilinx LCAs. The design flow sequences LCA configuration. Bit-stream configuration files can be
from a variety of popular design systems on three transferred from the Apollo system to a Xilinx PROM
workstations (Apollo, SUN, & DAISY Logician™) are programmer (DS112) or XACTOR In-Circuit Verifier
illustrated in the accompanying figure. (DS28) or a PC system download cable connected to the
target system.
APOLLO SYSTEM
SUN3SYSTEM
The Mentor IdeaStation™ for schematic entry and
simulation is supported on the Apollo DN3000, DN3500, The SUN3 workstation supports logic entry on FutureNet
DN4000, and DN4500 computers. Xilinx offers a Logic DASH, logic entry/unit delay simulation on several
Library and Interface product (DS343) for XNF net list file systems (including Valid, Cadnetix, ViewLogic, & Case),
transfer into the Xilinx Design Implementation System. or state machine language & Boolean equations (including
This interface also generates post placement and route ABEL, CUPL, LOG/IC, & PLDesigner). These third party
timing information aSSOCiated with logic mapped into CLBs vendors provide interface products for XNF nellist file
and the signal routing delays between CLBs. transfer into the Xilinx Design Implementation System.

The Xilinx Development System for the Apollo computer The Xilinx development system forthe Sun3 (DS501-SN 1)
(DS501-AP1) offers features identical to the PC version. offers features identical to the PC version. The automated
The Enhanced Automated Design Implementation design sequence is also completely supported on the
capability (ADI and Bit-stream Compilation) is completely SUN3 computer from design capture to generation of bit-
supported on the Apollo computer. For designers stream patterns for LCA configuraton. While the
requiring the interactive XACT edit capability, the product interactive XACT editor on the SUN3 is being developed,
currently contains PC resident software. While the the PC version is included in the DS501-SN 1.

TECHDOC 1956

5-20
 DESIGN ENTRY
i-----SUN3COMPUTffisy~EMS----i i---------------i r--------------,
I r - - - - - - - - - - - - - - , I I APOLLO 3Xee MENTOR : LOGICIAN & DEDDAIII&SYACE
I I FUTURENET I I & 4XOO NETED I PERSONAL
I I ABEL CADNETIX DASH4 I I SYSTEMS SYMED I LOGICIAN DSIM
: : f~~c ~~EI~ : : UNIT DELAY : UNIT DELAY
I I PLDesigner VIEWLOGIC I I ABEL ~1~Tul~!f~~ I
GATE LEVEL
SIMULATION
I I I I CUPL I
I I I I LOG/IC LCA TIMING I LeA TIMING
I I UNIT DELAY I I PLDesigner SIMULATION I SIMULATION
I I GATE LEVEL rl--------bTI~I__- - - -__~--~----~TI~----~~------+,

l'::::::: :':r~ ~~=tt~==~~==~:Jt::::=t1=====~==Jt~C-.:..J

BOOLEAN
EQUATIONS LOGIC
SIMULATION

TRANSLATED & ROUTED

TIMING ANNOTATION

DESIGN
IMPLEMENTATION
DS501-SN1 SUN3
-AP1 APOLLO

II
HARDWARE
CIRCUIT
IMPLEMENTATION
& VERIFICATION

r--------
I
I
I
I
I
~ ~C_S!~T§~ __

L'=====:::l XILINX
PROGRAMMABLE
GATE ARRAY

1956 02

5-21
 Development System
PC Hardware Requirements

Xilinx provides an integrated Development System for IBM-incompatibilities of some "clones", usually in BIOS or
design and implementation of Logic Cell Arrays. The LCA Keyboard Controller. Xilinx software includes system
development system operates on an IBM® PC/AFM or exercises called PMTEST and PMINFO to help test IBM
IBM PS/2 model 60 or 80 and provides a range of support compatibility and measure relative performance.
features. This provides the user with an effective,
convenient, low risk method of logic design entry,
simulation, LCA generation and verification for single chip MEMORY
logic designs of up to 9000 gates. Several popular
workstation suppliers have developed compatible In protected mode the processor uses extended address
software which allows logic diagram design entry, space, which is found above the 1 Meg address. Earlier
simulation and LCA partitioning programs to be run on versions of the Xilinx XACT Design Editor used expanded
their systems. memory (EMS or LIM standard) which is not suitable for
the higher performance required by the larger array chips.
The system configuration needed to run the Xilinx software Some of the Xilinx programs run in conventional memory
consists of a 80286 or 80386 based IBM PC or space while the larger programs have a loader program of
"compatible". The software runs under the MS-DOS about 100 K bytes, which resides in conventional base
operating system version 3.0 and later, requires a 20 memory and installs the Xilinx program in extended
Megabyte hard disk, a mouse and a color monitor. A math address space. See Figure 1. If the extended memory
co-processor can enhance performance of Automatic space is limited and becomes filled, the balance of the
Placement and Routing by 10 or 20%. program will be "backfilled" above the loader in
conventional memory. The availability of sufficient
The recommended configuration consists of: extended memory for an entire Xilinx protected mode
program makes it possible to invoke nonprotected mode
• A "386" PC/AT or PS/2 model 60 or higher programs such as text editors or utilities without
terminating a Xilinx program. For different LCA designs,
• 40 M byte hard disk drive plus a 1.2 M Byte high the XACT Design Editor has different minimal
density floppy disk drive requirements of available memory, as displayed by the
BIOS at power-up.
• Two RS-232-C serial ports

• One parallel port LCA Gates Total Memory Required for

XACT2.1
• Enhanced Graphics Adapter and Display
(EGA and EGO) 2000 or less 2.50 MBytes
3000 3.25 MBytes
Mouse 4200 4.00 MBytes
6400 5.25 MBytes
MS-DOS version 3.0 or higher 9000 6.50 MBytes

• IBM compatible BIOS and keyboard

Note that this amount of memory must be available to
Highest system performance can be obtained by using a XACT, i.e., it does not include the memory used for other
80386 based system or a PS/2 model 70. To assure resident programs.
integrity, all Xilinx software is tested on IBM systems and
several of the more "compatible" systems. Xilinx LeA Note also that the Compaq 386 has only 640K bytes of its
development software includes some of the first DOS first Megabyte available to any user.
based programs to make extensive use of the "protected"
mode of the processor. This has exposed protected mode Disk requirements for Xilinx software are a function of the

5-22
program options which the user chooses, the number and PROGRAM APROX. SIZE
type of active LeA designs and the number of other user
software packages. A high density 1.2 M byte 5.25" floppy XACT 3.5 M byte
PIN2XNF 1.5 M byte
drive is needed for installation of the Xilinx software on the
APR 1.0 M byte
hard disk. The Xilinx software is also available on PS/2 3.5"
diskettes. Some of the larger Xilinx programs are:

FFFFFF - - - - - - - - r - - - - - - - - - - ,
' + 1 16M BYTE
FFOOOO I I--------+}----------l:
EXTENDED ADDRESS
(FOR XACT SOFTWARE)

130000

120000

110000

100000 1M BYTE
ROM BIOS
FOOOO

EOOOO

00000
EXPANDED MEMORY WINDOW
h MAP ~EXPANDED=
COOOO I) ~ MEMORY =
STANDARD VIDEO
BOOOO
EXTENDED VIDEO
ACOOO 640K BYTE

90000

80000 512K BYTE

70000

60000

50000

40000 256K BYTE

30000
20000 128K BYTE

10000 64K BYTE

0000
1

1164 01 Figure 1. IBM Memory Map

The Compaq 386 reserves the 384K bytes of memory between 640K and 1M for internal use,
making them unavailable to XACT.

5-23
Development System Hardware Requirements

I/O Ports emulates the PC Mouse or has a device driver which

provides Microsoft compatibility and defines it's COM port.
The Xilinx LCA Development System requires several I/O
ports. A parallel port is needed for the software execution PC Setup
protection key. The key must be in place to allow Xilinx
software to execute but is virtually transparent, and the When the system is powered up it uses commands from
port can be used simultaneously for parallel printer or the the DOS CONFIG.SYS file to install selected device driver
Xilinx download cable. Several printer types are supported programs (such as Mouse driver) in memory and define
fortext orgraphic hard copy. Serial COM ports are used for buffer and file sizes. Examples of these statements are:
a mouse, the XACTOR In-Circuit Design Verifier and the
Configuration PROM Programmer. device=c:\lib\msmouse.sys /1
files=10
Display buffers=20

The original IBM PC provided for two display options. AfterCONFIG.SYS functions are implemented the system
Monochrome Display for text, and four color, 320x200 executes the commands found in the AUTOEXEC.BAT
pixel, 8x8 dot character, Color Graphics Display for text file. This file contains DOS commands such as:
and graphics. The interface to the displays was done by
the Monochrome Display Adapter (MDA) and Color path=c:\; ... c:\xact;c:\dash-1ca;
Display Adapter (CGA). IBM has added the higher set xact=c:\xact
resolution 16 color, 640x350 pixel, 8x14 dot character, set grmode=ega
Enhanced Graphic Display (EGD) and the corresponding set swmode=9
Enhanced Graphic Adaptor (EGA). The Xilinx LCA set minbytes=65000
Development System operates with a CGA or EGA
display, but, future software enhancements might not The first line shows the portion of the path established by
support CGA and the higher resolution EGA is therefore the XACT and DASH-LCA installation procedures. These
recommended. The use of the EGA display is necessary are the default directories created and used in the Xilinx
for FutureNet schematic capture. The PS/2 compatible installation procedures. The SET SWMODE= sets a
VGA is preferred for the higher density 3000 family LCAs. parameter defining one of several alternative ways of
The Hercules monochrome display is not compatible. switching the processor from protected to real mode.
Several alternatives are made available in order to
Mouse accommodate various "clone" idiosyncrasies. Possible
values are 9 (default), 10, 7, 4, and for 80386 based
The Xilinx Development System programs are compatible systems, 3.
with several varieties of mice. These include Mouse
Systems PC Mouse (no device driver required), Microsoft See the Xilinx installation instructions and PC manuals for
(serial or parallel), LogiTech C7 and the FutureNet mouse. additional information.
The Xilinx software will directly support any mouse which

5-24
E:XILINX LeA Macro Library Listings

PADS
PIN Input Pad0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PINO Input Pad with Registered Input 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 o ./ ./

PINR Input Pad wnh Registered and Direct Inputs 0 0 0 0 0 0 0 0 0 o ./ -
PIO InpuUOutput Pad 0 0 0 • 0 0 •• 0 0 0 0 0 00000000000 •••••• o ././ o ./ ./
PIOO Input/Output Pad with Registered Input .... 0 •• 0 •••• o ./ ./ o ./ ./
POUT Output Pad .. 0 • 0 0 0 0 0 0 0 ••••••••••••••••••••••• o ./ ./ o ./ ./
POUTZ Output Pad with 3-State Control ..........•....... o ;, i o ./ ./
POUTO Output Pad with Registered Output ......•......... o ./ -
PREG Pad with Data Register ... ; .................... . o ./ ./ o ./ ./
PREG2 Pad with 2cBit Shift Register. 0 0 0 0 •• 0 •• 0 •••••••••• o ./ -
lOB SCHEMATIC ELEMENTS
TBUF Internal Three-State Buffer ..... o.... 0 • 0 • 0 0 • 0 0 0 •• • 0 ./ f
ACLK Auxiliary Buffer ............... 0 0 • 0 , 0 •••• 0 0 0 0 0 • 0 o ./ ./ o ./ ./
GCLK Global Buffer ........ o..... 0 0 • 0 0 • 0 ••••• 0 ••• 0 •• o ./ ./ o ./ ./
IBUF Input Buffer. 0 • 0 0 • 0 • 0 0 ••••• , ••• , •• 0 ••• 0 0 0 00 ••• o · ./ o - ./
INFF
INLAT
Input Flip-Flop ..
Input Latch .....
0

0
0

0
•

•
0

0
0

0
0

0
0

0
•

0
0

0
• • • •, '

•• 0 0 0
•••••••••••

0 0 0 0 0 • 0 0 • 0 0
'

0
••••

00 0 0
o
o
-
-
../
./
o
- "
OBUF Output Buffer. to 0 •• 0 0 0 •• 0 •• 0 0 ••••• 0 •••••••••• 0 o - ./ o - ./
OBUFZ Output Buffer with Output Enable 0 0 0 • 0 0 •• 0 •• ; • 0 • 0 0 o · ./ o . ./
OUTFF Output Flip-Flop 0 0 0 • 0 • 0 •• 0 • 0 • 0 0 • 0 • 0 ••••• 0 •••••• o - i/
,OUTFFZ Output Flip~FlopwithOBUFZ ..... 0 0 • 0 •• 0 0 0 0 0 0 • 0 • o - ./
BPAD Bidirectional Package Pin Symbol. 0 0 • 0 0 0 0 0 0 0 0 0 0 • 0 0 o - ./ o - ./
IPAD Input Package Pin Symbol .0000 •• 0 0 0 •• 0 0 •••• 0 • 0 0 o -./ ' - o "./
OPAD Output Package Pin Symbol .. 0 ••• 0 •• 0 0 •• 0 0 • 0.0 0 0 0 o J ./ o - it
UPAD Unbonded Die PadSymboi.o ...•.. , ..... o· 0 0 0 0 0 0 0 ; o o - "
BUF Internal non-inverting Buffer 0 • 0 0 0 0 0 0 0 0 0 0 0 0 0 0 • 0 .0 0 o . ./ o -'./
INV Inverter .. 0 0 0 0 0 0 0 • 0 •• 0 0 •••••••••••••••• 0 ••••• 1 - ./ 1 - ./
PULLUP Input pull-up Resistor ..... 0 0 0 • 0 0 • 0 0 0 ••••• 0 •••• 0
o · ./
OINV Irwerting. Output Buffer . 0 0 0 ••••••••••••••• 0 •••• 0 0 - ./ - ./.
10FF 1/0 Pad as Flip-flop 0 0 ; 0 0 0 0 •• 0 0 •••••••••• 0 • 0 0 ••• o - ./

5-25
Macro Lists

GENERAL
GADD 1-Bit Full Adder ............................... ./ ./ ./ ./
GCOMP 2-Bit Comparator .............................. ./ ./ ./ ./
GLTGT 2-Bit Less Than/Greater Than Comparator .......... ./ ./
GEQGT 2-Bit Equal/Greater Than Comparator ............. ./ ./
GMUX 2-to-1 Mux ................................... 1 ./ ./ 1 ./ ./
OSC Crystal Osc .................................. 0 - ./ 0
GXTL Crystal Osc (XACT: 3020 GXTL20, 2018 GXTL2) .... 0 ./ ./ 0 ./ ./
GOSC Low Frequency Resistor-Capacitor Oscillator ........ ./ ./
GMAJ Majority Gate ................................. ./ ./ ./
GXOR Exclusive-OR ................................. ./ ./
GXOR2 Dual Exclusive-OR ............................ ./
GPAR Parity Test (Even = Low) ........................ ./ ./
HX83 4-Bit Binary Adder With Fast Carry ................ 6 ./
HX85 4-Bit Magnitude Comparator ..................... 7 ./
HX280 9-Bit Parity Checker / Generator .................. 3 ./
HX283 4-Bit Binary Full Adder ......................... 6 ./
HX518 8-Bit Identity Comparator ....................... 5 ./
HX521 8-Bit Identity Comparator ....................... 5 ./
HX125 Three-State Bus Buffer ......................... 0 ./
HX240 Octal Inverting Buffer, Three-State Outputs ......... 4 ./
HX241 Octal Non-inverting Buffer, Three-State Outputs ..... 1 ./
HX244 Octal Non-inverting Buffer, Three-State Outputs ..... 0 ./
HX245 Octal Bidirectional Transceiver ................... 1 ./
HX540 Octal Inverting, Three-State Outputs ............... 0 ./
HX541 Octal Non-inverting, Three-State Outputs ........... 0 ./
LATCHES
LD Data Latch ................................... ./ ./ ./ ./
LDRD Data Latch with Reset Direct ..................... ./ ./ ./ ./
LDSD Data Latch with Set Direct ....................... ./ ./ ./ ./
LRS Set-Reset Data Latch with Reset Dominant ......... ./ ./
LDM Data Latch with 2-lnput Data Mux ................. ./ ./
LDMRD Data Latch with 2-lnput Data Mux with Reset Direct ... ./ ./
LDMSD Data Latch with 2-lnput Data Mux with Set Direct ..... ./ ./
LDSRD Data Latch with Set Direct, Reset Direct ............ ./ ./
HX77 2-Bit Latch ................................... 1 ./
HX259 8-Bit Addressable Latch ........................ 8 ./
HX373 Octal Latch with Three-State Outputs .............. 4 ./

5-26
FLIP-FLOPS
DFF D Flip-Flop ...................................
FD D Flip-Flop .................................... ./ ./ ./ ./
FDRD D Flip-Flop with Reset Direct ..................... ./ ./ ./ ./
FDSD D Flip-Flop with Set Direct ....................... ./ ./
FDSRD D Flip-Flop with Set Direct, Reset Direct ............ ./ ./
FDC D Flip-Flop with Clock Enable .................... ./ ./ ./ ./
FDCRD D Flip-Flop with Clock Enable, Reset Direct ......... ./ ./ ./
FDCR D Flip-Flop with Clock Enable, R~set .......•...... ./ ./ ./ ./
FDCS D Flip-Flop with Clock Enable, Set ................ ./ ./ ./ ./
FDR D Flip-Flop with Reset .......................... ./ ./ ./ ./
FDS D Flip-Flop with Set ............................ ./ ./ ./ ./
FRS Set-Reset Flip-Flop with Reset Dominant ........... ./ ./ ./ ./
FSR Set-Reset Flip-Flop with Set Dominant ............. ./ ./ ./ ./
FDM D Flip-Flop with 2-lnput Data Mux ................. ./ ./ ./ ./
FDMRD D Flip-Flop with 2-lnput Data Mux with Reset Direct ... ./ ./ ./ ./
FDMSD D Flip-Flop with 2-lnput Data Mux with Set Direct ..... ./ ./
FDMR D Flip-Flop with 2-lnput Data Mux with Reset ........ ./ ./ ./ ./
FDMS· D Flip-Flop with 2-lnput Data Mux with Set .......... ./ ./ ./ ./
FJK J-K Flip-Flop ........................... : ..... ./ ./ ./ ,./
FJKRD J-K Flip-Flop with Reset Direct ................... ./ ./ ./ ./
FJKSD J-K Flip-Flop with Set Direct ..................... ./ ./
FJKSRD J-K Flip-Flop with Set Direct, Reset Direct .......... ./ ./
FJKS J-K Flip-Flop with Set .......................... ./ ./ ./ ./
FTO
FTORD
Self Toggle Flip-Flop ...........................
SelfToggle Flip-Flop with Reset Direct .............
./
./
./
./
./ ./
II
FTOR Self Toggle Flip-Flop with Reset .................. ./ ./ ./ ./
FT Toggle Flip-Flop .............................. .1 ./ ./ ./ ./
FTRD Toggle Flip-Flop with Reset Direct ................ ./ ./ ./
FTP Toggle Flip-Flop with Parallel Enable .............. ./ ./ ./ ./
FTPRD Toggle Flip-Flop with Parallel Enable, Reset Direct, ... ./ ./ ./ ./
FTR Toggle Flip-Flop with Reset. .................. : .. ./ ./ ./ ./
FTS Toggle Flip-Flop with Set ........................ ./ ./ ./ ./
FT2 2-lnput Toggle Flip-Flop ........................ ./ ./
FT2R 2-lnput Toggle Flip-Flop with Reset ............... ./ ./
NDFF Negative Edge Flip-Flop Primitive ................. ./ 1 ./
PDFF Positive Edge Flip-Flop Primitive .................. ./ ./

5-27
Macro Lists

DECODERS/ENCODERS
02-4 1-of-4 Decoder ............................... ./ ./ 2 ./ ./
D2-4E 1-of-4 Decoder with Enable ...................... 2 ./ ./ 2 ./ ./
74-139 1-of-4 Single Decoder with Enable, Low Output ...... 2 ./ ./ 2 ./ ./
03-8 1-of-8 Decoder ............................... 4 ./ ./ 4 ./ ./
D3-8E 1-of-8 Decoder with Enable ...................... 4 ./ ./ 5 ./ ./
74-138 1-of-8 Decoder with Enables, Low Output. .......... 5 ./ ./ 6 ./ ./
74-42 1-of-10 Decoder with Low Output ................. 5 ./ ./ 7 ./ ./
HX42 4-to-10 Line Decoder ........................... 5 ./
HX48 BCD to Seven Segment Decoder ................. 5 ./
HX138 1-of-8 Decoder/Demultiplexer .................... 5 ./
HX139 1-of-4 Decoder ............................... 2 ./
HX147 10-to-4 Line Priority Encoder ..................... 5 ./
HX148 3-to-8 Line Priority Encoder ...................... 9 ./
HX154 1-of-16 DecoderlDemultiplexer ................... 9 ./
HX278 4-Bit Cascadable Priority Encoder ................ 6 ./

MULTIPLEXERS
M3-1 3-to-1 Mux ................................... ./ ./ 2 ./ ./
M3-1E 3-to-1 Mux with Enable ......................... 2 ./ ./ 2 ./ ./
M4-1 4-to-1 Mux ................................... 2 ./ ./ 3 ./ ./
M4-1E 4-to-1 Mux with Enable ......................... 2 ./ ./ 3 ./ ./
74-352 4-to-1 Mux with Enable, Low Output ............... 2 ./ ./ 3 ./ ./
M4-2 4-to-2 Mux ................................... ./ ./
M8-1 8-to-1 Mux ................................... 4 ./ ./ 7 ./ ./
M8-1E 8-to-1 Mux with Enable ......................... 4 ./ ./ 7 ./ ./
74-151 8-to-1 Mux with Enable, Complementary Outputs ..... 4 ./ ./ 7 ./ ./
74-152 8-to-1 Mux with Low Output ..................... 4 ./ ./ 7 ./ ./
MZ8-1 8-to-1 Mux Using Three-State Buffers .............. 0 ./
HX151 8 Input Multiplexer ............................. 5 ./
HX152 8 Input Multiplexer ............................. 4 ./
HX153 Dual 4 Input Multiplexer ......................... 6 ./
HX157 Quad 2 Input Multiplexer ........................ 4 ./
HX158 Quad 2 Input Multiplexer ........................ 3 ./
HX257 Quad 2-to-1 Multiplexer with Enable ............... 2 ./
HX258 Quad 2-to-1 Inverting Multiplexer ................. 2 ./
HX352 4-to-1 Data Selector / Multiplexer ................. 5 ./

5-28
REGISTERS
Data Reg isters
RD4 4-Bit Data Register ............................ 4
RD4RD 4-Bit Data Register ............................ 2 ~ ~

RD8 8-Bit Data Register ............................ 4 ~ ~ 8 ~ ~

RD8RD 8-Bit Data Register with Reset Direct .............. 4 ~ ~

RD8CR 8-Bit Data Register with Clock Enable, Reset ........ 4 ~ ~ 8 ~ ~

HX174 Hex 0 Register with Master Reset ................ 4 ~

HX273 Octal 0 Flip-flop ............................... 4 ~

HX298 Quad 2 Input Flip-flop .......................... 4 ~

HX374 Octal 0 Flip-flops with Three-State Outputs ......... 4 ~

HX377 Octal 0 Flip-flops with Clock Enable ............... 4 ~

HX577 Octal 0 Flip-flops with Reset and Three-State Outputs 4 ~

Serial to Parallel

RS4 4-Bit Shift Register ............................ 2 ~ ~ 4 ~ ~

RS4RD 4-Bit Shift Register with Reset Direct .............. 2 ~ ~

RS4C 4-Bit Shift Register with Clock Enable .............. 2 ~ ~

RS4CRD 4-Bit Shift Register with Clock Enable, Reset Direct ... 2 ~ ~

RS4CR 4-Bit Shift Register with Clock Enable, Reset ........ 2 ~ ~

74-195 4-Bit Serial to Parallel SR with ParEna, MRLow ...... 3 ~ ~ 5 ~ ~

74-194 4-Bit Bi-Directional SR with ClkEna, ParEna, MRLow . 5 ~ ~ 12 ~ ~

RS8 8-Bit Shift Register ............................ 4 ~ ~ 8 ~ ~

RS8RD 8-Bit Shift Register with Reset Direct .............. 4 ~ ~

RS8R 8-Bit Shift Register with Reset .................... 4 ~ ~ 8 ~ ~

RS8C 8-Bit Shift Register with Clock Enable .............. 4 ~ ~

RS8CRD 8-Bit Shift Register with Clock Enable, Reset Direct ... 4 ~ ~

RS8CR 8-Bit Shift Register with Clock Enable, Reset ........ 4 ~ ~ 8 ~ ~

RS8PR 8-Bit Shift Register with Parallel Enable, Reset . . . . . . 4 ~ ~ 8 ~ ~

74-164 8-Bit Serial to Parallel SR with Master Reset Low .... 5 ~ ~ 8 ~ ~

HX164 8-Bit Serial In-Parallel Out Shift Register ........... 5 ~

HX166 Parallel Load 8-Bit Shift Register ................. 6 ~

HX179 4-Bit Parallel Access Shift Register ................ 5

HX194 4-Bit Bidirectional Universal Shift Register .......... 7 "
~

HX195 4-Bit Parallel Access Shift Register ................ 3 ~

HX198 8-Bit Bidirectional Shift Register .................. 14 - ~

HX199 8-Bit Shift Register with Clock Inhibit .............. 7 ~

HX595 8-Bit Shift Register with Three-State Register Output .. 9 ~

5-29
Macro Lists

COUNTERS
Modulo 2
C2BCP 1-Bit Binary Counter wI Clock Enable, Parallel Enable. ./ ./
C2BCPRD 1-Bit Binary Counter wi ClkEna, ParEna, Reset Direct. ./ ./
C2BCR 1-Bit Binary Counter with Clock Enable, Reset ....... ./ ./ ./ ./
C2BCRD 1-Bit Binary Counter with Clock Enable, Reset Direct .. ./ ./ ./ ./
C2BP 1-Bit Binary Counter with Parallel Enable ........... ./ ./ ./ ./
C2BR 1-Bit Binary Counter with Reset .................. ./ ./ ./ ./
C2BRD 1-Bit Binary Counter with Reset Direct ............. ./ ./ ./ ./

Modulo 4
C4BCP 2-Bit Binary Counter with Clock Enable, Parallel Enable 2 ./ ./ 3 ./ ./
C4BCPRD 2-Bit Binary Counter wI ClkEna, ParEna, Reset Direct. 2 ./ ./
C4BCR 2-Bit Binary Counter with Clock Enable, Reset ....... 2 ./ ./ 2 ./ ./
C4BCRD 2-Bit Binary Counter with Clock Enable, Reset Direct .. 2 ./ ./ 2 ./ ./
C4JX 2-Bit Expandable Johnson Counter ................ ./ ./
C4JXRD 2-Bit Expandable Johnson Counter with Reset Direct . ./ ./
C4JXC 2-Bit Expandable Johnson Counter with Clock Enable. ./ ./
C4JXCRD 2-Bit Expandable Johnson Cntr wlClkEna, Reset Dir .. ./ ./
C4JXCR 2-Bit Expandable Johnson Counter with ClkEna, Reset ./ ./
C4JCR 2-Bit Johnson Counter with Clock Enable, Reset ..... 2 ./ ./

Modulo 6
C6JCR 3-Bit Johnson Counter with Clock Enable, Reset ..... 2 ./ ./ 3 ./ ./
Modulo 8
C8BCP 3-Bit Binary Counter wI ClkEna, Parallel Enable ...... 3 ./ ./ 5 ./ ./
C8BCPRD 3-Bit Binary Counter wi ClkEna, ParEna, Reset Dir ... 3 ./ ./
C8BCR 3-Bit Binary Counter with Clock Enable, Reset ....... 3 ./ ./ 4 ./ ,/
C8BCRD 3-Bit Binary Counter with Clock Enable, Reset Direct .. 2 ,/ ,/ 4 ,/ ,/
C8JCR 4-Bit Johnson Counter with Clock Enable, Reset ..... 2 ,/ ,/ 4 ,/ ,/

Modulo 10
C10BCRD 4-Bit BCD Counter with Clock Enable, ResetDir ...... 3 ,/ ,/ 4 ,/ ,/
C10BCPRD 4-Bit BCD Counter with Parallel Enable, ResetDir .... 4 ,/ ,/ 7 ,/ ,/

74-160 4-Bit BCD Counter wi ClkEna, ParEnaL, MRLow ..... 6 ,/ ,/ 8 ./ ,/

74-162 4-Bit BCD Counter wi ClkEna, ParEnaL, Reset Low .. 7 ,/ ./
C10BPRD 4-Bit BCD Counter wi Parallel Enable, Reset Direct ... 4 ,/ ,/ 6 ./ ,/
C10JCR 5-Bit Johnson Counter with Clock Enable, Reset ..... 3 ,/ ,/ 5 ,/ ,/
HX160 Presettable Decade Counter ..................... 8 ,/
HX162 Presettable Decade Counter with Sync Clear ........ 10 ,/
HX168 4-Bit BCD Synchronous UplDown Counter .......... 11 ,/
HX390 4-Bit Decade Cpunters with Clear ................. 3 ,/

5-30
COUNTERS (Continued)
Modulo 12
C12JCR 6-Bit Johnson Counter with Clock Enable, Reset ..... .I' .I' 6 .I' .I'
Modulo 16
C16BARD 4-Bit Binary Ripple Counter with Reset Direct ........ 2 .I' .I' 4 .I' .I'
C16BCRD 4-Bit Binary Counter wI ClkEn, Reset Direct ......... 3 .I' .I' 4 .I' .I'
C16BCP 4-Bit Binary Counter wI ClkEna, Parallel Enable ...... 5 .I' .I'
C16BCPRD 4-Bit Binary Counter wI ClkEna, ParEna, Reset Direct. 5 .I' .I' 6 .I' .I'
74-161 4-Bit Binary Counter wI ClkEna, ParEnaL, MRLow .... 6 .I' .I' 8 .I' .I'
C16BCPR 4-Bit Binary Counter wI Clock Enable, ParEna, Reset . 6 .I' .I' 10 .I'
74-163 4-Bit Binary Counter wI ClkEna, ParEnaL, Reset Low . 7 .I' .I'
C16BPRD 4-Bit Binary Counter wI Parallel Enable, Reset Direct . 4 .I' .I' 5 .I' .I'
C16BUDRD 4-Bit Binary Up-Down Cntr wI ParEna, ResetDir ..... 5 .I' .I' 8 .I' .I'
C16JCR 8-Bit Johnson Counter with Clock Enable, Reset ..... 4 .I' .I' 8 .I' .I'
HX161 Presettable Binary Counter ...................... 6 .I'
HX163 Synchronous Binary Counter with Sync Clear ....... 8 .I'
HX169 4-Bit Binary Synchronous UplDown Counter ........ 7 .I'
HX393 4-Bit Binary Counters with Clear .................. 5 .I'
HX590 8-Bit Counter with Register and Three-State Output ... 13 .I'
Modulo 256
C256BCRD 8-Bit Binary Counter with Clock Enable, Reset Direct .. 7 .I' .I'
C256BCR 8-Bit Binary Counter with Clock Enable, Reset ....... 7 .I' .I'
C256BCP 8-Bit Binary Counter wI ClkEna, Parallel Enable ...... 8 .I' .I'

•
C256BCPRD8-Bit Counter wI ClkEna, ParEna, Reset Direct ...... 8 .I' .I'
C256FCRD 8-Bit Mod 256 Feedback SR wI ClkEna, ResetDir .... 6 .I' .I' 9 .I' .I'

5-31
 XC-DS53 XACT Design
Implementation System
with FutureNet DASH-LCA
Product Brief

FEATURES translated into an LCA, or automatically linked to PAL

symbols in a schematic.
• Complete bundled development system for
programmable gate array design entry and The XC-DS53 also includes the Automated Design
implementation using schematics and/or Boolean Implementation software, which permits designers to
equations efficiently implement programmable gate array designs
• FutureNet DASHTM LCA schematic editor provides without detailed knowledge of LCAs. The logic
easy-to-use hierarchical LCA design capability optimization software uses logic synthesis algorithms to
optimize for sma.llest area or highest performance.
• PALASM™format text input permits combining PLD
Automatic logic reduction and partitioning software
equations and schematics in the same design
eliminates unused logic, then partitions the design into
• Extensive macro library of over 100 logic elements Logic Cell Array physical resources (logic and I/O blocks).
(PALTM devices, TTL counters, registers, etc.) Finally, the Automatic Placement and Routing program is
• Logic optimization software uses logic synthesis invoked to arrange logic blocks within the LCA to minimize
algorithms to optimize programmable gate array signal delays on user-specified critical timing paths.
designs for density or performance
Designers can interactively place and route portions of the
• Automatic logic reduction and partitioning software physical design, if necessary, then compile a configuration
removes unused, disabled logic bitstream using the graphics-based XACT Design Editor
• Automatic placement and routing (included in the XC-DS53). XACT's timing calculator
• XACT Design Editor provides interactive physical permits point-to-point timing calculations for critical path
editing, timing calculator, design consistency analysis, or a simulator (such as the optional XC-DS22
checking, and configurationbitstream compiling SILOS Simulator) can be used to simulate design function
and timing.
• Download cable transfers configuration bitstreams
directly from PC to LCA during design debugging During in-circuit design analysis, designers can save time
• Runs on IBM® PC/ATTM or compatible computer by using a Download Cable provided with XACT to transfer
the configuration program from the PC directly into an LCA
GENERAL under development in a system.
The XC-DS53 PGA Development System provides Xilinx provides ongoing support for XACT users. Software
designers with a complete system for entering, updates (for new devices) are included for the first year.
implementing, compiling, and verifying designs for Xilinx Continued support updates are available for purchase with
programmable gate arrays. the XC-SC53 Annual Support Agreement. In addition,
Xilinx operates a technical support telephone hotline and
The FutureNet DASH-LCA schematic editor combined
an electronic bulletin board to provide software
with a Xilinx PALASM-to-LCA translator program provides
enhancements and factory support.
powerful design entry and documentation capability.
Designs can be entered as schematics, Boolean XC-OSS3 Includes:
equations, or both.
• FutureNet DASH-LCA Schematic Editor and
DASH-LCA supports unlimited levels of hierarchy and an XC-DS31 LCA Library
extensive library of standard logic macros for LCA design.
In addition, designers can flag critical timing paths to • Complete XC-DS23 Automated Design
ensure critical signals are routed with minimum delay. The Implementation software (PALASM input, logic
optional XC-DS40 TTL library adds over 50 additional optimizer, automated placement and routing)
7400 MSI TTL functions for LCA design using FutureNet • Complete XC-DS21 XACT Design Editor
DASH-LCA or DASH. (Interactive placement and routing, configuration
bitstream compiler, download cable and demo
Xilinx PALASM-to-LCA software permits text files board)
containing Boolean equations for any type of PLD to be
1963

5-32
 ------~B ~

- - - - - - - 0 QO
- - - - - - - - - < LOAD
_ _ _ _ _ _--jl"'ROO

-----------4E~ ~
ctEAR

TIL
MACRO
LIBRARY
XC·DS311
(OPTIONAL)

Logic Synthesis
Program Optimizes
for LCA Architecture
I
Optimized XNF Files

Partitions and Maps Collection

of Gate Level Logic into CLBs
and lOBs. Unused Logic Removed.

Automated CLB & lOB LCA Interactive Layout

III
Placement and Routing Graphical Editor and
within LCA; Timing Calculator
Timing Report Generation

'--_ _ _ to Target _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---I

System
Containing LCA

196301

Software Included in XC-OS53

5-.33
 XC-DS501 XACT
Design Implementation
System
Product Brief

XC-DS501 FEATURES of the design (such as decoders) with Boolean equations.

ADI software allows designers to merge multiple modes of
• Complete system for implementing programmable
design entry into a single design.
gate array designs into Logic CellTM Array
• Accepts any combination of schematic netlists and The following figure illustrates the design flow from a
PALASM2™ text files design schematic with some glue logic, a TTL macro, and a
"PLD" symbol. The "PLD" design is entered using ABEL,
• Supports input from ABEL, CUPL, Log/IC, and
CUPL, Log/IC, PLDesigner, or directly as PALASM2™
PLDesigner
Boolean Equations. The multiple mode design is combined
• PLD conversion software allows design entry with into a programmable gate array in three steps. First, the
PALASM2™ format equations schematic is converted by the nellist translator to a Xilinx
• Logic synthesis software optimizes designs for Logic Nellist Format (XNF) file. Second, the PALASM2textfile is
Cell Array architecture translated (PDS2XNF) and then optimized (XNFOPT),
• Automated logic reduction and partitioning removes resulting in a second XNF file. The design files are then
unused, disabled logic merged, partitioned into CLBs and lOBs.
• Automated placement and routing of logic minimizes The automatic placement and routing program (APR) is
design cycle time very flexible. Routing resources can be specified to
• Available on PC/ATTM, Apollo, and Sun3 computers eliminate clock skews and minimize routing delays for
• Interactive logic and routing editor critical paths.

• Boolean equation or Karnaugh map alternatives to The XACTTM Interactive Design Editor can then be used to
specify logic functions modify design placement and routing, when required to
• Point to point timing calculations for critical path meet critical timing requirements.
analysis Checks for logic connectivity and design rule violation are
• Download cable to transfer configuration programs easily performed using the XACT Design Editor. All
from PC to LCA in target system unused internal nodes are automatically configured to
minimize power dissipation.
GENERAL
Interactive point-to-pointtiming delay calculation is provided
Designers require both Advanced Design Implementation for timing analysis and critical path determination. This
(ADI) and the Interactive XACT Design Editorto implement ability enables the user to quickly identify and correct
their Logic Cell Array designs. timing problems while the design is in progress.

The Automated Design Implementation (ADI) software A download cable included with the XACT Design Editor is
converts design descriptions for programmable gate arrays useful fortransferring configuration programs serially from
into Logic Cell Array (LCA) implementations. Design the PC workstation to a Logic Cell Array installed in a
descriptions may combine both schematics and PLD system. During product development and verification this
equations. capability can be used to save the time required to write a
modified configuration program into an EPROM.
The XACT Design Editor provides an interactive placement!
routing editor to modify or complete design routing, a Xilinx provides ongoing support for users of the Design
bitstream compiler, and a download cable for in-circuit Implementation software. For the first year, software
verification. updates are included. After that, the user may purchase
the XC-SC501 Annual Support Agreement to continue to
receive the latest software releases. Xilinx also maintains
DESIGN IMPLEMENTATION PROCESS
a Technical Hotline and a user electronic bulletin board to
Designers often describe portions of their design (such as provide timely product support.
counters and glue logic) with schematics, and other portions
1952

5-34
 ------------~. 00
------------~c 00

-------------41.0...,
--------------1> .. ROO

~--------------~--------~PALASM
Text File

Logic Synthesis
Program Optimizes
for LCA Architecture
I
Optimized XNF Files

Partitions and Maps Collection

of Gate Level Logic into CLBs
and lOBs. Unused Logic Removed.

Automated CLB & lOB

Placement and Routing
within Report Generation'--L!::==~==:~=~=~r-...1
TimingLCA;
LCA Interactive Layout

nmr
Graphical Editor and
C./coi"M
•
CLB-Ievel Netlist
with Timing Delays
to Interface with
Logic Simulators

roTarget _______________________________ ~

System
Containing LCA
195201
195201 Software Included in XC-DS501

5-35
 XC-DS31 FutureNet DASH™
Schematic Entry Interface
and Design Library
Product Brief

FEATURES the schematic. A Xilinx conversion utility converts the

schematic into an XNF output file.
• Library and translator for users with the FutureNet
DASHTM Schematic Designer Once partitioned, the design may be placed and routed
• Macro library of over 100 standard logic family with the PC-based XC-DS501 XACT Design
equivalents derived from the XACTfM Macro Library Implementation System. The Xilinx symbol library
includes symbols to flag critical data and clock signals
• Library of logic symbols including all two-input, three-
which the Automatic Placement and Routing Program
input and four-input AND, OR and XOR gates plus
uses to prioritize those signals for minimum delay.
storage, inpuVoutput and clock elements
• User control for flagging critical paths for the Xilinx provides ongoing support for users of the FutureNet
Automated Placement and Routing keep DASH Schematic Designer Library. For the first year,
• Converts schematic drawings to a Xilinx Netlist software updates are included. After that, the user may
Format (XNF) output file purchase the XC-SC31 Annual Support Agreement to
• Output compatibility with XC-DS501 XACT Design continue to receive the latest software releases.
Implementation System
• Runs on an IBM'" PC/ATTM or compatible personal
computer

GENERAL
Schematic entry and automatic partitioning of Logic Cell
Array designs shortens logic reduction and product
development times. Complex designs can be specified
schematically and quickly implemented for in-circuit
design verification.

Xilinx's FutureNet DASH Schematic Designer Library pro-

vides the symbol library and conversion utility to permit
designers to enter Logic Cell Array designs with the
FutureNet DASH Schematic Designer. The Xilinx library
provides the logic, I/O, and macro symbols to be used in

1964

5-36
 XC-DS311
7400 TTL Library for FutureNet
DASH and DASH-LCA
Product Brief

FEATURES 74151 8-lnput Multiplexer

74152 8-lnput Multiplexer
• Over 507400 TIL library elements for use with 74153 Dual4-lnput Multiplexer
FutureNet DASHTM Schematic Designer 74154 1-of-16 Decoder/Demultiplexer
• Permits XC3000 family Logic CeUTM Array design 74157 Quad 2-lnput Multiplexer
using familiar 7400 MSI functions 74158 Quad 2-lnput MuHiplexer
74160 Presettable Decade Counter
• Supports XC-DS531 PGA Development Systems with
74161 Presettable Binary Counter
FutureNet DASH-LCA
74162 Presettable Decade Counter w/ Sync Clear
74163 Synchronous Binary Counterw/ Sync Clear
GENERAL 74164 Serial-In, Parallel-Out Shift Register
74166 Parallel Load 8-Bit Shift Register
The XC-DS311 7400 TIL Library is a set of over 50 74168 4-Bit BCD Synchronous Up/Down Counter
FutureNet DASH logic symbols for schematic entry of 74169 4-Bit Binary Synchronous Up/Down Counter
Logic Cell Array (LCA TM) designs. The library can be used 74174 Hex 0 Flip-Flop with Master Reset
with the XC-DS531 Development System, or with the 74179 4-Bit Parallel Access Shift Register
FutureNet DASH Schematic Designer and XC-DS31 74194 4-Bit Bidirectional Universal Shift Register
Future Net DASH Schematic Interface and Library. Use of 74195 4-Bit Parallel Access Shift Register
the XC-DS-311 Library· allows the designer to enter 74198 8-Bit Bidirectional Shift Register
compleX programmable gate array designs in terms of 74199 8-Bit Shift Register with Clock Inhibit
familiar TIL functions. 74240 Octallnv Buffer, Three-State Outputs
74241 Octal Non-Inverting Three-State Buffers
The XC-DS311TIL Library supplements the library of 74244 Octal Non-lnv Buffer, Three-State Outputs
more than 100 logic elements that are included with 74245 Octal Bidirectional Transceiver
XC-DS531. 74257 Quad 2-lnput Multiplexer
74258 Quad 2"lnput Multiplexer
Xilinx provides ongoing support for XACTusers. For the 74259 8-Bit Addressable Latch •
first year, software updates (such as support for new 74273 Octal 0 Flip-Flop
devices) are included at no charge. After that, users may 74278 4-Bit Cascadable Priority Register
purchase the XC-SC311 to continue receiving software 74280 9-Bit Parity Checker/Generator
updates. In addition, Xilinx operates a technical support 74283 4-Bit Binary Full Adder
telephone hotline and an electronic bulletin board to 74298 Quad 2-lnput Multiplexer with Storage
provide software enhancements and factory support. 74352 DuaI4-to-1 Da.ta Selector/MultipleXer
74373 Octal Latchwith Three-State Outputs
74374 Octal 0 Flip-Flops with Three-State Outputs
LIST OF TTL MACROS 74377 Octal. 0 Flip-Flop with Clock Enable
74390 Dual4-Bit Decade Counters with Clear
7442 4-10-10 Line Decoder 74393 Dual4-Bit Binary Counters with Clear
7448 BCD-to~Seven-Segment Decoder 74518 8-Bit Indentity Comparator
7477 4-Bit Latch 74521 8-Bit Indentity Comparator
7483 4-Bit Binary Adder With Fast Carry 74540 Octallnv Buffer, Three-State Outputs
7485 4-Bit Magnitude Comparator 74541 Octal Non-Inv Buffer, Three-State Outputs
74125 Quad Three-State Bus Buffer 74577 Octal 0 Flip-Flops with Reset a.nd Three-State
74138 1-of-8 Decoder/Demultiplexer Outputs
74139 Dual1 cof-4 Decoder 74590 8-BitBinary Counter with Output Register
74147 10-to-4 Line Priority Encoder 74595 8-Bit Shift Register with Output Register
74148 8-to-3 Line Priority Encoder
1957

5-37
 XC-DS32 Schema II
Schematic Entry Interface
and Design Library

Product Brief

FEATURES Once partitioned, the design may be placed and routed

with the PC-based XACT Design Implementation System.
• Library and translator for users with the Schema II The Xilinx symbol library includes symbols to llag critical
Schematic Editor data and clock signals which the Automatic Placement and
• Macro library of over 100 standard logic family Routing Program uses to prioritize those signals for
equivalents derived from the XAC"fTM Macro Library minimum delay.
• Library of logic symbols including all two-input, three-
input and four-input AND, OR and XOR gates plus Xilinx provides ongoing support for users of the Schema II
storage, input/output and clock elements Schematic Entry Interface. For the first year, software
updates are included. After that, the user may purchase
• User control for flagging critical paths for the
the XC-SC32 Annual Support Agreement to continue to
Automated Placement and Routing Program
receive the latest software releases.
• Converts schematic drawings to a Xilinx Nellist
Format (XNF) output file
• Output compatibility with XACT Design
,------------------,
SCHEMA II EDITOR
Implementation System
• Runs on an IBM~ PCIApM or compatible personal SCHEMA
computer
_________ .J
GENERAL ---------,
I I
Schematic entry and automatic partitioning of Logic Cell I XC-DS32 I
Array designs shortens logic reduction and product I SCHEMA II I
I INTERFACE I
development times. Complex designs can be specified I I
L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .J
schematically and quickly implemented for in-circuit
design verification. .
XILINX NETLIST
FORMAT
Xilinx's Schema II Schematic Entry Interface provides the
symbol library and conversion utility to permit designers to
enter Logic Cell Array designs with the Schema II
Schematic Editor. The Xilinx library provides the logic, To Xilinx XC-DS501
Design Implementation System 196501
1/0, and macro symbols to be used in the schematic. A
Xilinx conversion utility converts the schematic into an
XN F output file.

5-38
 XC-DS33 Daisy Schematic
Entry Interface, Library,
Unit-Delay Simulation
Product Brief

FEATURES Once partitioned, the design may be placed and routed

with the PC-based XC-DS501 XACT Design
• Schematic entry via the Daisy OED II and ACE Implementation System. The Xilinx symbol library
Schematic editors includes symbols to flag critical data and clock signals
• Unit-delay simulation with Daisy simulator which the Automatic Placement and Routing Program
uses to prioritize those signals for minimum delay.
• Macro library of over 100 standard logic family
equivalents derived from the XAC"fTM Macro Library
Xilinx provides ongoing support for users of the Daisy
• Library of logic symbols including all two-input, three- Schematic Interface. For the first year, software updates
input and four-input AND, OR and XOR gates plus are included. After that, the user may purchase the
storage, inpuVoutput and clock elements XC-SC33 Annual Support Agreement to continue to
• User control for flagging critical path;s for the receive the latest software releases.
Automated Placement and Routing Program
• Converts schematic drawings to a Xilinx Netlisi
Format (XNF) output file DAISY SYSTEM REQUIREMENTS
• Output compatibility with XC-DS501 XACT Design
Any Daisy workstation listed on the chart on the next page
Implementation System
can be used to produce a design netlist in the Xilinx Netlist
Format using a utility provided with the library.
GENERAL
An IBM PC/AT equipped with the XC-DS501 Design
Schematic entry and automatic partitioning of Logic Cell Implementation System is then used to physically
Array designs shortens logic reduction and product implement the design in an LCA.
development times. Complex designs can be specified
schematically and quickly implemented for in-circuit PC/AT-based Daisy workstations (such as the Daisy
design verification. ENTRY system) can have the XC-DS501 software
installed in the PC's DOS partition. Designers using •
Xilinx's Daisy schematic i.nterface provides the symbol non-PC/ATworkstations can transfer the schematic netlist
library and conversion utility to permit designers to enter to an MSDOS floppy and complete the LCA physical
Logic Cell Array designs with either OED II or ACE on design on a PC/AT computer.
Daisy workstations. The Xilinx library provides the logic,
I/O, and macro symbols to be used in the schematic. A Personal LOGICIAN® and LOGICIAN® are registered
Xilinx utility converts the Daisy format to an XNF output file. trademarks of Daisy Systems Corporation.

1967

5-39
 XC·DS343 Mentor Interface
Schematic Entry, Timing
Simulation Interface, and Library

Product Brief

FEATURES Xilinx provides ongoing support for users of the Mentor

Interface. Forthe first year, software updates are included.
• Mentor certified After that, the user may purchase the XC-SC343 Annual
• Mentor IDEA® Station can be used for schematic Support Agreement to continue to receive the latest
entry and simulation of programmable gate array software releases. Xilinx also maintains a Technical
designs Hotline and an electronic bulletin board to provide technical
• Simulation with post placement/routing LCA timing product support to LCA users.
• Macro library includes over 100 standard logic
elements (counters, multiplexers, registers, etc.)
SYSTEM REQUIREMENTS
• Primitive library includes flip-flops, latches, AND, OR,
XOR, NAND, NOR gates Mentor IDEA V6.0 or greater is required for schematic
• Xilinx Netlist Format (XNF}output is compatible with entry and simulation. The XC-DS343 Mentor Interface
XC-DS501 Design Implementation System software requires the APOLLO SR9.6 or DOMAIN/IX
operating system.

GENERAL File transfer from the Mentor system to other PC-based

Xilinx software may be accomplished using any existing
The Xilinx XC-DS343 Mentor Interface allows designers PC/Apollo link, such as the DOMAIN/PC I software
to use their Mentor IDEA Station to enter and simulate available from Mentor and Apollo.
programmable gate array schematics. The Logic Cell™
Array library includes over 100 macros for commonly used The XC-DS501-AP1 Developement System is partially
counters, registers, multiplexers, etc. resident on Apollo (DN3000, DN3500, DN4000, and
DN4500) and IBM PC System platforms. The Mentor
The resulting Mentor design files are then processed interface, Automated Placement/Routing, timing analysis,
using Xilinx's XC-DS501 Design Implementation System, and bitstream compilation are resident on the Apollo
which permits rapid design development and real-time system, while the XACT Design Editor is currently resident
in-circuit design verification. on the IBM PC system.

1958

5-40
 DESIGN
DESIGN ENTRY VERIFICATON
r-----------------------~A~ __________________________ ~-----'A'-----________.,

STATE MACHINE MENTOR GRAPHICS BOOLEAN QUICKSIM LOGIC &

LANGUAGE NETED/SYMED EQUATIONS
I TIMING SIMULATION

II I I
1~
'---
- ------ -,
r--
F
-
I
, 7 I

1\
I
:

I
L _____
NETLIST
TRANSLATION / XC·DS343
MENTOR
INTERFACE
/ - ANNOTATED
NETLIST CREATION
J~
I
I
-------------------------~ ------ --I
D ESIGN ,------------ ------------------------,
IMPLEMENTATION I I
I I
I XC·DS501 XACT I
LOGIC SYNTHESIS
I MAP TO LCA
DESIGN IMPLEMENTATION I
I SYSTEM I
I I
I I
I I

l~ ~t
I I
I I
I I
I I
I AUTOMATIC V' f>. INTERACTIVE
* POST ROUTE TIMING I
I
I
PLACE AND ROUTE
I'\r---v1 PLACE AND ROUTE ANALYSIS AND REPORTS I
I
I I
I II I I I I
I

•
I I
I • SHIPPED ON PC WITH UPGRADE I
I TO APOLLO WHEN AVAILABLE I
I I
I LCA CONFIGURATION & I
I PROM FILE GENERATION I
I I
I I
L _____________________________ - - - - - - - - - - I

1958 02

Xilinx LCA Design Flow on Mentor Graphics Workstations

5·41
 XC-OS35 OrCAO SOT
Schematic Entry Interface

Product Brief

FEATURES Once partitioned, the design may be placed and routed

with the PC-based XACT Automated Design
• Library and translator for users with the OrCAD SDT Implementation Program. The Xilinx symbol library
Schematic Editor includes symbols to flag critical data and clock signals
which the Automatic Placement and Routing Program
• Macro library of over 100 standard logic family
equivalents derived from the XACTfM Macro Library uses to prioritize those signals for minimum delay.

• Primitive library of logic symbols includes all two-

input, three-input and four-input AND, OR and XOR Xilinx provides ongoing support for users of the OrCAD
gates plus storage, input/output and clock elements Schematic Entry Interface. For the first year, software
updates are included. After that, the user may purchase
• User control for flagging critical paths for the
the XC-SC35 Annual Support Agreement to continue to
Automated Placement and Routing Program
receive the latest software releases.
• Converts schematic drawings to a Xilinx Netiist
Format (XNF) output file
• Output compatibility with XACT Design Implementa- ,------------------,
tion System I OrCAO SOT III I

• Runs on an IBM®PC/ApM or compatible personal

computer

GENERAL

Schematic entry and automatic partitioning of Logic Cell

Array designs shortens logic reduction and product
development times. Complex designs can be specified
schematically and quickly implemented for in-circuit
design verification.

Xilinx's OrCAD Schematic Entry Interface provides the

symbol library and conversion utility to permit designers to
enter Logic Cell Array designs with the SDT Schematic To Xlllnx XC·OSSOl
Oeslgn Implementallon System _ 196601
Editor. The Xilinx library provides the logic, 1/0, and macro
symbols to be used in the schematic. A Xilinx conversion
utility converts the schematic into an XNF output file.

5-42
 XC-DS3S1 OrCAD VST
Simulator Interface .
Product Brief

FEATURES in an unplaced and unrouted design. This saves design

time because logic errors can be detected and corrected
• Model library and netlist translator for users of the prior to final placement and routing. After a circuit has
OrCAD VST Simulator been placed, routed and then fully debugged using
• Supports full timing simulation of routed LCA designs, in-circuit emulation, worst case timing may be verified.
and unit-delay simulation of unrouted designs This enables the user to select the correct Logic Cell Array
speed grade for a particular application.
• Permits simulation of schematics which include PAL
logic defined with PALASM, ABEL, CUPL, Log/IC, or
Network inputs for Logic Cell Array designs are
PLDesigner.
automatically created by the XNF2VST utility from the
Input compatible with XACT Design Implementation XNF output of the XACT Design Implementation System.
System The network includes logic and routing delay parameters
• Includes unique automated Trace and Stimulus file and setup and hold times based upon the selected speed
generation grade operating under worst case conditions.
• Runs on an IBM PC/AT or compatible personal
computer

GENERAL r----

Simulation is particularly useful for testing designs or XC·OS351

OrCAD VST
design segments as well as for verifying critical timing over Simulator
Interface
worst case power supply, temperature and process
conditions.
From XC-DS501 XACT
Simulation is useful in several stages of the design cycle. Design Implementation System
After design entry, simulation may be used to debug logic
1970 01

5-43
 XC-DS22 and XC-DS221
PC-SILOSTM Simulators

Product Brief

FEATURES in-circuit emulation, worst case timing may be verified.

This enables the userto select the correct Logic Cell Array
• PC based simulator for LCA design verification speed grade for a particular application.
• Simulates any LCA design, regardless of design input
format (combined logic schematics, Boolean equa- Network inputs for Logic Cell Array designs are
tions, and state machine descriptions) automatically created by the XNF2SILO utility. The
network. includes logic and routing delay parameters and
• General purpose event driven logic and timing
setup and hold times based upon the selected speed
simulator
grade operating under worst case conditions. Simulation
• Input automatically generated from XNF file stimuli are created with a set of clock statements orwith an
• Control and observation of any physical circuit node input pattern for either pad inputs or internal nodes.
• Multiple file input for vectors and commands Simulation results are available in tabular, plotted and
graphic formats. This flexibility makes the "logic debug"
• Interactive or batch mode operation
easy for both the circuit function and timing.
• Output available in printed or tabular formats
• Runs on an IBM®PC/AT'" or compatible personal
computer
• Simulates logic complexities up to 16,000 gates
(OS22) or 5,000 gates (OS221)

GENERAL

PC-SILOS is a powerful PC based simulatorthat provides

event driven logic and timing simulation of Logic Cell™
Array designs. Simulation is particularly useful for testing
designs or design segments as well as for verifying critical
timing over worst case power supply, temperature and
process conditions.

Simulation is useful in several stages of the design cycle.

After design entry, simulation may be used to debug logic
in an unplaced and unrouted design. This saves design
time because logic errors can be detected and corrected
prior to final placement and routing. After a circuit has
been placed, routed and then fully debugged using

195~

5-44
 XC-OS112 Configuration
PROM Programmer

Product Brief

FEATURES The programming unit connects to a serial port of an IBM

PC/AT or compatible and is controlled using PC-based
• Programs XC1736 Serial Configuration PROM software included with the XC-DS112.
• Connects to serial port of IBM PC/AT or compatibles
Designers compile their Logic Cell Array designs into a
• Operates from PC via software provided with standard HEX format file USing the PC-based XACT
programming unit development system. The· programming software
• Accepts HEX format data files created by the DS501 provided with the XC-DS112 is then used to download the
XACT Design Implementation System HEX file into the programming unit and program a
XC1736.
GENERAL
Since the XC-DS112 software is separate from the XACT
Designers using the Xilinx XC1736 Serial Configuration software, the XC-DS112 software and programming unit
PROM-an 8-pin mini-DIP PROM used to configure can be installed on a PC otherthan the oneusedfordesign
programmable gate arrays-can program the XC 1736 development-such as a PC located in a manufacturing
with the XC-DS112 Configuration PROM Programmer. area.

XC-DS112
PROGRAMMER PC
(0625 RECEPTACLE) (OB25 PLUG)

2 ••- - - - 2 TxD (FROM PC)

3 .. 3 RxD (TO PC)
[4 • 4 RTS

•
5 .. 5 CTS
+V -'VV"- 6 .. 6 DSR
GND 7 • 7 GND
[ ·8 .. 8 DCD
20. 20 DTR

196001

XC-DS112 Interface to PC

1960

5-45
 XC-DS26, XC-DS27, XC-DS28
XACTOR™ In-Circuit
Design Verifier
Product Brief

FEATURES device isolation and configuration is controlled with mouse

or keyboard commands and may be supplemented with
• Real time in-circuit verification in user's target system user-defined setup files for easy system debugging.
• Concurrent emulation of up to four devices
Readback of device configuration may be performed on
• Readback and display of Logic Cell™ Array internal
command for verification of the configuration process and
storage element states
interrogation of the internal states. The state of all internal
• Device status display with automatic update of storage elements is displayed after readback has been
asynchronous events performed. Status displays showing the state of all
• Control and I/O pin isolation from target system isolation switches and control signal states are provided.
• Support for daisy chain programming of up to seven The status display includes automatic reporting of
devices in a daisy chain . asynchronous status changes in the target system.
• Support for multiple device and package types
UNIVERSAL IN-CIRCUIT EMULATOR PODS
• Runs on an IBM® PC/ATTM or compatible personal
computer Additional pods may be connected to the XACTOR
controller, up to a maximum of four pods per controller.
GENERAL Pod headers are interchangeable for different device and
package types. Each pod provides a direct in-socket
The XACTORTM real-time in-circuit design verifier connection without disruption of the target system. Test
provides interactive target system emulation of up to four points are provided to allow connection of a logic analyzer
Logic Cell Arrays from the host PC system. In-circuit or other test equipment to aid in the system debugging.
"debug" provides a powerful productivity enhancement to
simulation, providing capabilities to verify functionality in
the target system at full speed with all other circuits and
system software.

The design verifier is composed of a microcomputer-

based controller, and from one to four universal emulation
pods, each with an emulation header. The controller is
connected to the host PC through a serial port and
provides local storage of configuration programs, control
of individual device configurations, and control of the
isolation of the pod device(s) from the target system. The
user can set the state and isolation for each of the control
signals to provide debugging of target hardware. Four
general 110 pins are available to provide test points which
may also be isolated from the target system.

Target Logic Cell Arrays can be programmed individually

or in a daisy chain. Daisy chains of up to seven devices
may be supported from any of the four pods. Individual

1968

5-46
 Development Systems
Ordering Information
Further information is available from your local distributor
sales office or the nearest Xilinx sales representitive.

ORDERING GUIDELINES
To design with XilinxTM programmable gate arrays, designers should have as a minimum:
• XC-DS501 XACTTM Design Implementation System, plus
• LCA Interface and library for their schematic editor
(see DS300 Optional Libraries and Interfaces, below)
PC-based designers who wish to use the Xilinx-provided FutureNet® DASH-LCA schematic editor can purchase all of
the above from Xilinx as the "XC-DS53 XACT Design Implementation System with FutureNet DASH-LCA."

Workstation-based DS501 customers will initially received the PC version of the interactive XACT Design Editor; the
workstation version of the XACT Design Editor will be provided as a no charge upgrade when available.

DS500 DESIGN IMPLEMENTATION DEVELOPMENT SYSTEMS

XC-DS501 XACT Design Implementation System for IBM PC/AT
XC-SC501 Annual Software Support Agreement
Bundled system equivalent to DS21 plus DS23-contains graphical interactive LCA editing tool
plus all non-graphical, automated implementation tools.
• Design Manager provides convenient front-end for all Xilinx programs
• Accepts any combination of schematic netlists (XNF format) and PALASM-compatible text files
(also accepts input form ABEL, CUPL, PLDesigner, and Log/IC)
• Automatic placement and routing program reduces design implementation time
• LogiC synthesis software efficiently optimizes designs for LCA
• Automatically eliminates unused, disabled logic
• Bitstream compiler compiles design into LCA programming bitstream
• Graphical LCA design editor permits interactive editing of design placement/routing

•
• Download cable facilitates in-circuit debugging of LCA designs

XC-DS501-AP1 XACT Design Implementation System for Apollo workstation and PC/AT
XC-SC501-AP1 Annual Software Support Agreement

XC-DS501-SN1 XACT Design Implementation System for Sun® 3 workstation and PC/AT
XC-SC501-SN1 Annual Software Support Agreement

AP1 and SN1 versions contain PC-based XACT Design Editor and workstation-based
enhanced automated design implementation software (includes bitstream compiler). Designer
must have access to a PC/AT to run the XACT Design Editor for interactive placement/routing
editing. An update to the workstation version of XACT Design Editor will be shipped when
available.
• Accepts any combination of schematics netlists (XNF format) and PALASM-compatible text
files (also accepts input from ABEL, CUPL, PLDesigner, and Log/IC)
• Automatic placement and routing program reduces design implementation time
• Logic synthesis software efficiently optimizes designs for LCA
• Automatically eliminates unused, disabled logic
• Bitstream compiler generates LCA programmable bitstream on workstation system.

5-47
Development Systems

DS500 DESIGN IMPLEMENTATION DEVELOPMENT SYSTEMS (Con't)

XC-DS53 XACT Design Implementation System with FutureNet DASH-LCA
XC-SC53 Annual Software Support Agreement
Includes al/ software required to enter programmable gate array schematics, place/route
designs, and compile designs into configuration bitstreams to program LCA devices
Includes DS501 XACT Design Implementation System plus a FutureNet DASH-LCA schematic
editor (a version of FutureNet DASH4 solely for LCA designs) plus a DS31 FutureNet library
and interface
Design Manager provides convenient front-end for all Xilinx programs
Includes support for PALASM®-compatible Boolean equation entry
(also accepts input from ABEL, CUPL, PLDesigner, and Log/IC)
Runs on IBM® PC/ATTM or compatible

DS100 OPTIONAL HARDWARE PRODUCTS

XC-DS112* Enhanced Serial Configuration PROM Programmer
XC-SC112 Annual Software Support Agreement

DS200 OPTIONAL DESIGN IMPLEMENTATION & VERIFICATION TOOLS

XC-DS21 XACT Design Editor for IBM PC
XC-SC21 Annual Software Support Agreement
• Graphics-based interactive LCA design editor
• Timing calculator, bitstream compiler, and macro library
• Download cable, demo board and 2 LCA devices
XC-DS23 Automated Design Implementation (A.D.I.) software for IBM PC
XC-SC23 Annual Software Support Agreement
• Accepts any combination of schematic netlists (XNF format) and PALASM-compatible text files
• Logic synthesis software efficiently optimizes designs for LCA
• Automatically eliminates unused, disabled logic
• Automatic placement and routing program reduces design implementation time
XC-DS22 P/C-SILOSTM Simulator (16,OO(), gates) with LCA interface
XC-SC22 Annual Software Support Agreement
XC-DS221 P/C-SILOSTM Simulator (5,000 gates) with LCA interface
XC-SC221 Annual Software Support Agreement
XC-DS28 XACTORTM In-Circuit Design Verifier (Controller Hardware and Software)
Order one XC-DS28 Controller, from one to four XC-DS26 Emulation Pods, and one XC-DS27
Emulation Header (of desired package type) per Emulation Pod
• Runs on IBM PC/AT or compatible (connects to serial port)
• Controller supports up to four XC-DS26 Emulation Pods
• XC-DS26 Emulation Pod accepts any XC-DS27 Emulation Header
• XC-DS27 Emulation Header connects Emulation Pod to LCA socket in target system
XC-DS26 Emulation Pod for XACTOR (accepts any XC-DS27 Emulation Header)
XC-DS27-PD48 Emulation Header, 48 Pin DIP package
XC-DS27-PC68 Emulation Header, 68 PinPLCC package
XC-DS27-PG68 Emulation Header, 68 Pin Grid Array package
XC-DS27"PC84 Emulation Header, 84 Pin PLCC package
XC-DS27-PG84 Emulation Header, 84 Pin Grid Array package
XC-DS27-PG132 Emulation Header, 132 Pin Grid Array package
XC-DS27-PC175 Emulation Header, 175 Pin Grid Array package

• XC-OS112 is an enhanced version of former XC-OS81 serial configuration PROM programmer

5-48
 E:XIUNX

DS300 OPTIONAL LIBRARIES AND INTERFACES

XC-DS31 FutureNet DASH Schematic Interface and Library
XC-SC31 Annual Software Support Agreement
XC-DS311 TTL Library for FutureNet DASH and DASH-LCA
XC-SC311 Annual Software Support Agreement
XC-DS32 Schema 11+ Schematic Interface and Library
XC-SC32 Annual Software Support Agre.ement
XC-DS33 Daisy® Schematic and Unit-delay Simulation Interface and Library
XC-SC33 Annual Software Support Agreement
XC-DS343* Mentor®-certified Schematic and Full-timing Simulation Interface and Library
XC-SC343 Annual Software Support Agreement
XC-DS35 OrCAD/SDT® Schematic Interface and Library
XC-SC35 Annual Software Support Agreement
XC-DS351 OrCADIVST® Simulation Interface
XC-SC351 Annual Software Support Agreement

XC-MANUAL Additional Xilinx Development System Documention

• Complete XACT LCA Development System Reference Manuals (Volumes I, II)
• LCA User's Guide Manual (including several Application Notes)
• XACT Macro Library Manual

• XC-OS343 is an enhanced version of former XC-OS34 which now includes full timing simulation 1961

5-49
The Programmable Gate Array Company

XC3090 Die
 SECTION 6

Applications

1 Programmable Gate Arrays

2 Product Specifications

3 Quality, Testing, Packaging

4 Technical Support

5 Development Systems

6 Applications

7 Article Reprints

8 Index
 Applications

Introduction ......................................................................................... 6-1

Estimating Size and Performance ....................................................... 6-3
Incorporating PLD Equations Into LCAs ............................................. 6-7
The XC2000 User's Guide to the XC3000 Family ............................... 6-11
Designing with the XC3000 Family ..................................................... 6-12
Designing with the XC2000 Family ..................................................... 6-13
Additional Electrical Parameters ......................................................... 6-14
LCA Performance ................................................................................ 6-16
Start-up and Reset .............................................................................. 6-19
Metastable Recovery .......................................................................... 6-20
Battery Backup for Logic Cell Arrays .................................................. 6-22
Compact Multiplexer and Barrel Shifter .............................................. 6-23
Majority Logic, Parity ........................................................................... 6-24
Multiple Address Decoding ................................................................. 6-25
Binary' Adders, Subtractors, and Accumulators .................................. 6-26
Adders and Comparators .................................................................... 6-27
Conditional Sum Adder ....................................................................... 6-30
Building Latches Out of Logic ............................................................. 6-31
Synchronous Counters, Fast and Compact ........................................ 6-32
30 MHz Binary Counter ....................................................................... 6-33
Up/Down Counter ................................................................................ 6-34
Loadable Up/Down Counter ................................................................ 6-35
30 MHz Counter with Synchronous Reset .......................................... 6-36
Fast Bidirectional Counters for Robotics ............................................. 6-37
40 MHz Presettable Counter ............................................................... 6-38
Asynchronous Preset in XC3000 CLBs .............................................. 6-40
FrequencylPhaseComparator for Phase-Locked-Loops ................... ,6-41
Gigahertz Presettable Counter............................................................ 6-42
100 MHz Frequency Counter .............................................................. 6-44
Serial Pattern Detectors ...................................................................... 6-45
Serial Code Conversion ...................................................................... 6-46
8-Bit Format Converter .......................................... :............................. 6-48
Megabit FIFO in Two Chips ................................................................ 6-50
State Machines ................................................................................... 6-52
Complex State Machine in One LCA .................................................. 6-53
Self-Diagnosing Hardware .................................................................. 6-54
PS/2 Micro Channel Interface ............................................................. 6-57
High-Speed Bar Code Reader ............................................................ 6-59
DRAM Controller with Error Correction ............................................... 6-61
Logic Analyzer/In-Circuit Emulator ...................................................... 6-67 1962
 Applications

INTRODUCTION Gate Arrays offer maximum flexibility and a high level of

integration, but burden the user with high risk, high cost,
The following pages show examples of systems and sub- and a long delay from finished design to working prototype.
systems solutions using Xilinx Programmable Gate Ar- Generating test vectors and worrying about testability is
rays. Some of these designs have been implemented, a another price the gate array user has to pay.
few are in production, but most are conceptual designs.
These are intended to demonstrate the devices' capabili- Programmable Gate Arrays offer a very large number of
ties, to highlight special advantage, to emphasize the best flip-flops (128 inthe CLBs and another128 inthe IOBofthe
design methods, and in general to stimulate the designer's 3020, a total of more than 800 in the 3090). Different from
imagination. the situation with Gate Arrays, these LCA flip-flops cannot,
or do not have to be, traded off against logic. Logic coexists
A Xilinx programmable gate array can implement virtually with the flip-flops in the form of function generators. The
any digital design. Xilinx offers a software package that function generators are surprisingly versatile pieces of
covers the gamut from schematic capture through logic logic, unlimited in theirflexibilty, limited only by their fan-in
optimization to automatic place and route and to the gen- of four or five signals.
eration of a programming bit stream. The designer can use
these tools and achieve a working LCA design while pay- When the logic has five inputs or less and is interspersed
ing very little attention to the architectual details of the Xil- with flip-flops driven by a common clock, the Xilinx Pro-
inx programmable gate array. grammable Gate Arrays are extremely efficient. Certain
high fan-in functions like ALUs tend to be less efficient, and
Such an approach, however, will not always achieve the bus-oriented designs have to be routed carefully to take
highest possible performance and the lowest possible advantage of the long lines and 3-state drivers of the 3000-
cost. For specific, well-structured designs it may pay to series.
work out a good match with the LCA architecture. This
chapter gives several examples of such solutions. The Fortunately, the user normally has some freedom in struc-
XC2000 and XC3000 family programmable gate arrays turing the system design. Wheneverpossible, this freedom
have inherent features different from those of LSTIL MSI should be used to improve either the performance or the
Circuits, or PAL devices, or conventional gate arrays. efficiency of the implementation.
Th esefourtechnologies all have different structures which
lea.d to different strengths and weaknesses when they are
being used to implement any specific type of logic.
GENERAL TOPICS
TTL-MSI was originally defined to fit into a 16-pin package
and to provide a maximum of flexibility, so that each stan-
dard part could be used in a myriad of applications. Some
Most designers want to estimate density and performance
before they begin an LCA design, and some want to know
II
functions are therefore overdesigned (counters and shift the definition of equivalent gates. Finally, there is interest
registers have parallel inputs and outputs, when few appli- in converting existing PAL designs to LCAs. All these
cations need both) and some are crippled by the 16-pin subjects are covered in the beginning of this chapter.
limitation (notably the up-down counters).
While the data sheets provide worst-case guaranteed
PAL devlcessufferfrom the rigidity of their AND-OR archi- parameters, many designers need additional information
tecture and from the fixed assignment of flip-flops to output about input and output characteristics, power consump-
pins. While the numberof inputs is generous, ideal for wide tion, crystal oscillator design, and the exact interpretation
decoding, the limited number of product terms that can be of certain ac parameters. CLB flip-flops show excellent
ORed together makes many designs inefficient and slow. recoveryfrom metastable problems, an important concern
The number of flip-flops available in PALs is very limited. with asynchronous interfaces.

6-1
Applications

COMBINATORIAL FUNCTIONS Using the fast flip-flops and distributed logic in the LCA to
their best advantage, a synchronous presettable counter
The 5-input function generator of the XC3000 family CLBs of arbitrary length has been demonstrated to run at
offers unlimited flexibility to implement anyone of the more 40 MHz. This is much faster than any available popular
than 4 billion (2 32) possible functions of up to five variables microprocessor peripheral counter/timer.
in one CLB, all with the same combinatorial delay. The
4-input function generator in the XC2000 family can imple- State Machine design is another example in which the
ment anyone of the 64K (2 16) possible functions of four creative use of CLB resources can result in a straightfor-
variables. The logic designer should take advantage of this ward and easily understood solution.
flexibility while avoiding the possible speed penalty im-
posed by the limitation to only five or four inputs. This may As explained in the beginning of this chapter, the CLB flip-
lead to logic partitioning that is different from traditional flops are "metastable-resistant," they resolve metastable
design orfrom MSI or PAL implementation. situations typically within a few nanoseconds. Designers
are nevertheless encouraged to avoid asynchronous de-
Majority logic is just one example in which the CLB excels: signs whenever possible. The combination of very fast
A 5 input majority function wou Id use 29 gates when imple- CLB flip-flops with relatively slow and layout-dependent
mentedwith 2-input NANOs and inverters, but itfits into the interconnects can lead to internal decoding spikes and
combinatorial portion of one 3000 series CLB. glitches that cannot be observed with an oscilloscope, but
which can play havoc with internal asynchronous logic.
Address decoding is the classical strength of PAL devices.
The high-speed, low-skew global clock lines and the indi-
It is done efficiently in LCAs if the complete function in-
vidual Clock Enable inputs on each CLB favor synchro-
cludes the combination of several addresses or groups of
nous design approaches that are inherently safer and more
addresses.
predictable.
ALUs consume many LCA resources, but adders or sub-
tractors can be implemented quite efficiently, even using SYSTEMS DESCRIPTIONS
carry-look-ahead for functions that exceed a width of eight
bits.
LCAs are universal programming building blocks, that are
SEQUENTIAL FUNCTIONS used in a wide variety of systems.

An 8-digit frequency counter implemented in a 2064 is a

LCAs offer an abundance of flip-flops, from 119 in the simple illustration. A PS/2 Micro Channel Controller and a
XC2064t0928intheXC3090. EachCLBflip-flop(64inthe DRAM Controller/Error Corrector demonstrate the versa-
XC2064, 128 in the XC3020, 640 in the XC3090) has a tility of the LCA in speed-critical applications.
''free'' combinatorial function generator available as its in-
put. This simplifies the design of shift registers and count- Article reprints from the trade press indicate the broad
ers. range of LCA applications.

The "Corner Bender" serial-parallel or parallel-serial con- The purpose of this applications chapter is not to provide
verter design, is a two-dimensional shift register array that cookbook solutions, but rather to stimulate the imagina-
fits very efficiently into an XC2064 or half of an XC3020, tion, convey ideas and demonstrate that LCAs offer a bet-
with 100% utilization of the CLB flip-flops. ter solution for a large variety of digital designs.

6-2
 Estimating Size and
E:XllIXX Performance

BY DAVE LAUTZENHEISER

INTRODUCTION
If the desired programmable gate array has enough I/O
Programmable gate arrays are available in a range of pins, the next step is to count the required storage ele-
densities and speed grades. Before committing resources ments. Table 1 shows both logic block storage elements
to design implementation, the user should estimate which and I/O block storage elements. Logic block storage
Programmable Gate Array best fits the specific applica- elements should be considered first, since they are the
tion. Such size and performance estimates cannot be most flexible. If the number of storage elements required
expected to provide exact details, but they provide useful is less than the number of logic storage elements, the
guidelines for device selection and cost estimates. A desired functions can probably be performed in the chosen
complete design will always be the final test for both Logic Cell Array.
density and performance.
In some cases, the I/O block storage elements can also be
Design fit estimates can be done in two steps. The first is used to meet storage element requirements. In particular,
a quick I/O and storage element count, with no regard for if the number of additional storage elements required
performance. The second step counts logic blocks based beyond the available logic storage elements is less than
on details of the intended circuit, and includes gross the number of unused I/O pins, then the desired functions
performance estimates, still without regard for routing may still fit into the chosen device.
delays. Performance estimates should always be consid- The following two examples illustrate the Step One quick
ered "best-case," recognizing that actual system perform- estimation procedure:
ance can only be verified on a completed design.
Example 1. An 8-bit microprocessor peripheral.
STEP 1 : I/O and Storage Element Fit
Function I/O requirements
A quick initial estimate ofthe fit of a system into a Program-
mable Gate Array can be made by counting the required 8 bit data bus 8
5 bus-control signals 5
input and output pins and internal storage elements. Table
16 bits of output 16
1 lists Xilinx's XC2000 and XC3000 series Logic Cell Array
4 bits of output control 4
(LCA) devices and their respective I/O and storage ele-
2 internal control registers
ment counts. To estimate a fit, first count the required Interrupt control logic
inputs and outputs and compare the total with the I/O pin
count of the desired device. Ifthe desired functions require TOTAL 33
more I/O than listed for a device, one must either select a
larger device or package, or reduce the I/O requirements.
Even the smallest Xilinx Logic Cell Array, the XC2064,

Logic I/O
passes the I/O test. It has 58 user I/O in its 68 pin PLCC
package.
II
Maximum Block Block
Function Storage Elements
Device 110 Storage Storage
Control registers (assume 8 bits) 16
XC2064 58 58 58
Buffered input shift register 16
XC2018 74 100 100
Miscellaneous control logic 10
XC3020 64 128 128
XC3030 80 200 160
TOTAL 42
XC3042 96 288 192
XC3064 120 448 240
XC3090 144 640 288
All of the storage elements can be put into logic storage in
the XC2064. The XC2064 should fit this application,
Table 1. I/O and Storage Element Summary provided the desired performance can be achieved.

6-3
Estimating Size and Performance

Example 2. A memory controller for a 32 bit high With two storage elements per logic block, the XC3042
performance processor. can provide up to 288 storage elements. Based on this
estimate, the desired functions should fit into the device.
Function 1/0 Requirements Some caution is indicated for two reasons. First, the 1/0
count is very near the limit of the device. This could cause
32 bit processor data bus 32 some routing congestion in the 1/0 area, making a higher
32 bit processor memory bus 32 pincount device a better choice. Second, high perform-
32 bit memory bus 16 (muxed)
ance requires making the best use of a device's features.
32 bit control register
The 32-bit bus may impose critical performance require-
32 bit DMA control
Address multiplexing control ments. Only the XC3064 and XC3090 allow a 32 bit
RAS/CAS/Refresh generation 3 internal bus, based on the number of available Long Lines.
Memory error check and correct Choosing the XC3064 could address the 1/0 requirements
Processor and memory timing 10 as well as the performance needs.

TOTAL 93 STEP 2: Logic Block Requirements

After establishing design fit by counting 1/0 and storage

Based on this 1/0 count, the XC3042 with 96 pins would be elements, it may be necessary to make a more detailed
marginal. An XC3064 with up to 120 1/0 pins may be analysis of the blocks required. The macro library sum-
required. mary table in the development system section of this data
book may be used to determine specific Configurable
Function Storage Elements Logic Block (CLB) counts for each function to be imple-
mented.
32 bit DMA (two-32 bit Counters) 64
Refresh generation (minimum) 10
The macro list shows the various gates and functions
32 bit control register 32
available with each design library. Each entry in the list
32 bit processor memory Address 32
Error check and correct 44 includes the required number of logic blocks to implement
Miscellaneous control 20 that function. Where there are differences between
XC2000 and XC3000 family block counts, these are noted.
TOTAL 202 To develop a rough block count, the designer simply
tabulates all ofthe blocks required by each ofthefunctional
elements in the design. Figure 1 shows a portion of a
schematic and the block count from the macro list.

8-BIT DATA BUS

REGISTER SHIFT SHIFT REGISTER

REGISTER REGISTER WITH 3-STATE
OUT IN OUTPUTS

VO SERIAL DATA
CPU

AO CONTROL REGISTER RD4 2CLBs

A1
READIWRITE DECODER HXl38 SCLBs

DECODER REGISTER RDS 4CLBs

SHIFT REGISTER OUT RSSPR 4CLBs
113301
SHIFT REGISTER IN RSS 4CLBs

REGISTER IN 3·STATE HX374 4CLBs

TOTAL 23 CLBs

6-4
In many schematics there are collections of random gates Estimating the block count for integrating PLD devices is
which need to be considered, along with the higher level more difficult. Each PLD output should be counted as at
functions such as counters, decoders and multiplexers. least one block. PLD devices using five or fewer of the
The following technique can be used to estimate the logic inputs, will require only one block per output for the
blocks required for random logic. Begin at an output point XC3000 family (four inputs for the XC2000 family). For
and move back along the path collecting gates until the complex equations using more than five (or four) inputs, a
number of inputs is 4 for XC2000 family devices, or 5 for conservative estimate is to use three blocks per output pin.
XC3000 family devices. These gates can be marked in
some way to show that they occupy a single logic block. Decisions about the appropriate device can be reviewed
Blocks identified by this method are added to the block as more information is collected. Block count estimates
count from the macro list analysis. Figure 2 shows an which are near the limit of a device, either in block count or
example of this gate collecting technique. in I/O and storage element count, may suggest use of the
next higher density device.

8~==:t:::::r- __
TC
8b
CET-_----------------........:::'£.::=4.==I-./
CEP

D3--++------L~

D Q Q2

D Q

•
D Q Q o

1133802 CP

Figure 2. Six CLBs Are Required to Implement a 74161 Binary Counter

6-5
Estimating Size and Performance

Estimating Performance Allowing 30% for routing (10 nsec) and 8 nsec for setup
gives a total delay of 48 nsec. This should allow operation
After selecting the right programmable gate array based at a system clock rate of up to 20 MHz.
on logic resources, an estimation of performance is often
the next step. If the system clock rate is less than 20% of
.•11' Summary
the flip-flop toggle rate of the selected device, then the
performance goals can usually be met easily. In cases of The final determination whether a logic device meets the
higher system clock rates or very complex functions, a goals for integration and performance can come only after
more detailed analysis may be required. the design has been completed. For Programmable Gate
Arrays, estimating logic capacity and performance should
The macro library for each device family includes the
precede device selection. If the design fits, the program-
number of logic block levels used for each listed function,
mable gate array development system, and the simplicity .
and the LeA datasheet specifies the block delay for each
of in-system design verification allow cost effective and
level.
rapid design implementation.
Some routing delay must be added to the block delay.
Such routing delays can add 25-50% to the block delays. Of course, speCifications sometimes change during the
execution of a design. Logic changes may result in
As an example, a circuit might have three levels of blocks different requirements for 1/0 and logic blocks. In such
in the path from one clock edge to another. For a device cases the Xilinx products product line simplifies the
with 10 nsec block delays, this gives 30 nsec delay from migration to a compatible array that meets the new
the first clock to the setup required for the next clock. requirements.

6-6
 Incorporating PLD
Equations into LeAs

Application Brief BYTHOMASWAUGH

The ideal design environment allows entering a design in programs comprise the tools necessary to create designs
many different ways, independent of the target techno logy, that integrate schematics and equations.
then mapping that design into the technology that best
suits the application. The design entry system should
support the integration of several design entry methods. INCORPORATING BOOLEAN EQUATIONS
For example, a designer should be able to enter a combi- INTO SCHEMATICS
nation of schematics, Boolean equations, and state ma-
There are a number of ways in which PLD equations can
chines, using whichever method best expresses the logic
be used in designing LCAs. Perhaps the best way is to
in any part of the design. Once the design is entered, the
incorporate PLDs into a schematic (see Figure 1).
designer should then be ableto optimize itforthe particular
technology in which it is to be implemented. Xilinx's
Programmable Gate Array design tools support the inte-
gration of both schematics, state machines and Boolean
equations into a design. PALASM ~
DESIGN FILE ~
Some designs or parts of designs are more easily ex-
pressed in Boolean equations or state machines than in PDS2XNF
schematics. A simple yet effective illustration of this is a
seven segment decoder deSign, which expressed sche- UNOPTIMIZED
XNFFILE ~
~ SCHEMATIC·TO-XNF
TRANSLATOR PROGRAM
SUCH AS
matically requires many AND and OR gates, but ex- SCH2XNF (SCHEMA) OR
PIN2XNF (FUTURENET)
pressed with equations requires only a text file. The

~n~'" I '~
XC-DS23 Automatic Design Implementation (ADI) soft- ,...---"---, SCHEMATIC
ware allows designers to integrate designs entered using NETLIST
TRANSLATED TO
a schematic editor with Boolean equations expressed in XNF FILE 1...----,,_--' AN XNF FILE
the PALASM2 format. Designers can enter Boolean equa-
tions directly using a text editor or they can create them
with ABEL or CUPL using their PALASM translators. The
XNFMERGE
ability to create a design using schematics, equations,
state machines, or a combination of the three makes the
design entry process more flexible and more powerful.

There are four programs in the XC-DS23 that help the

designer incorporate Boolean equations into a deSign. A
translator program called PDS2XNF translates PALASM2
design files into Xilinx Nellist Format (XNF) files. XNF is a
113501
dp XNF2LCA
II
standard interface between the Xilinx Development Sys- Figure 1. Design Flow of PLDs in a Schematic
tem and various design entry packages, e.g., schematic
editors. An optimization program called XNFOPT opti-
mizes the logic for Xilinx's Logic Cell Array (LCA) ar,gu1ec-
ture for highest efficiency in terms of density or speed. A Xilinx provides PLD symbols for both Schema 11+ and
program called XNFMERGE, merges various hierarchi- DASH-LCA, so that designers can call up PLD symbols
cally related design files such as schematics and PLD into their schematics. The user attaches a special attribute
designs into one flattened file. After merging, a program called a "FILE=" parameter to each PLD symbol. This
called XNF2LCA partitions a deSign's logic and assigns parameter (FILE= file_name) references an optimized
the logic to the elements of the LCA: configurable logiC XNF file that contains the translated Boolean equations for
blocks (CLBs) and input/output blocks (lOBs). These four that particular PLD (see Figure 2).

6-7
 5'
8
OPA:)
-ao
a:i"
OPAO
cc
,....
"
o
PALI0H8 .S'
c
19 !!l.
18 0"
17 ::J
I/)
::~ seq_'
5'
14 0"
,....
IJ
12
~
OPAD

OPAD
se ,,_

08UF OPAO

OPAD

OPAD

OPAD

OPAO

I OPAO
OPAD

I' 'I
I . ~08U! • ~o
~

Figure 2. FutureNet Schematic of a Counter with a 7·Segment Decoder

 TITLE 7SEG.PDS LeA. The logic represented by Boolean equations such as
AUTHOR BART REYNOLDS AND THOMAS WAUGH these must be optimized using the XNFOPT program
COMPANY XILINX before it can be translated into an LCA. The schematic
DATE APRIL 8, 1988 portion of the design is also translated into an XNF file.
CHIP 7SEG PALI0H8
The schematic XNF file is considered the top level of the
;Input Pins 1 2 3 4 5 6 7 8 9 10 design hierarchy, since it contains references to other XNF
NC NC DO Dl D2 D3 NC NC NC NC files like optimized XNF files from PLD designs. The
;Output Pins 11 12 13 14 15 16 17 18 19 20 XNFMERGE program merges lower level XNF files into
NC NC G F E D CB A NC the top level XNF file from the schematic to form one
flallened file that can be partitioned into the LCA architec-
;Input combinations ture, then placed and routed just like any other design.

STRING ZERO '/D3 * /D2 * /Dl * /DO'

STRING ONE '/D3 * /D2 * /Dl DO' DESIGNING LOGIC CELL ARRAYS WITH BOOLEAN
*
STRING TWO '/D3 * /D2 * Dl * /DO' EQUATIONS
STRING THREE '/D3 * /D2 * Dl * DO'
STRING FOUR '/D3 * D2 * /D1 * /DO' Another method of using equations to design LCAs is to
STRING FIVE '/D3 * D2 * /Dl * DO' express the LCA completely in terms of Boolean equations
STRING SIX '/D3 * D2 * Dl * /DO' without regard for a particular PLD type (shown in Figure
STRING SEVEN '/D3 * D2 * Dl * DO' 4). The PDS2XNF program will translate PLD equations
STRING EIGHT ' D3 * /D2 * /D1 * /DO' into an XNF file, even if the PLDdesign file does not cor-
STRING NINE ' D3 * /D2 * /Dl * DO'
respond to an existing PLD device. The PDS2XNF pro-
STRING TEN ' D3 * /D2 * Dl * /DO'
gram recognizes some features that are not permissible in
STRING ELEVEN ' D3 * /D2 * Dl * DO'
STRING TWELVE ' D3 D2 * /D1 * /DO' the standardPALASM2 format, including unlimited signal
* names in the design pinlist, internal signals not named in
STRING THIRTEEN ' D3 * D2 * /Dl * DO'
STRING FOURTEEN 'D3 * D2 * D1 * /DO' the pinlist, arbitrarily complex equations, and 32 character
STRING FIFTEEN 'D3 * D2 * D1 * DO' signalnames.LCA design with equations does not allow
the use of all the features of the LCA (e.g., input flip-flops
EQUATIONS on XC3000 lOBs), but it is a useful and convenientway of
A = ZERO + TWO + THREE + FIVE + SIX + SEVEN designing LCAs. completely and quickly using BooJean
+ EIGHT + NINE + TEN + TWELVE + FOURTEEN equations.
+ FIFTEEN
B = ZERO + ONE + TWO + THREE + FOUR + SEVEN
+ EIGHT + NINE + TEN + THIRTEEN
C = ZERO + ONE + THREE + FOUR + FIVE + SIX
+ SEVEN + EIGHT + NINE + TEN + ELEVEN
+ THIRTEEN
D = ZERO + TWO + THREE + FIVE + SIX + EIGHT
+ ELEVEN + TWELVE + THIRTEEN + FOURTEEN
PALASM
DESIGN FILE
c;J
GJ •
E = ZERO + TWO + SIX + EIGHT + TEN + ELEVEN
+ TWELVE + THIRTEEN +.FOURTEEN + FIFTEEN
UNOPTIMIZED
F = ZERO + FOUR + FIVE + SIX + EIGHT + NINE XNFFIL£
+ TEN + ELEVEN + TWELVE + FOURTEEN
+ FIFTEEN
G TWO + THREE + FOUR + FIVE + SIX + EIGHT
+ NINE + TEN + ELEVEN + THIRTEEN
+ FOURTEEN + FIFTEEN

Figure 3. PALASM2 Design File Referenced in the

Schematic

The PLD design file, entered in the PALASM2 format (see

OPTIMIXED
XNF FILE

XNFFILE
MAPPED INTO.
GJ
8 XNF2LCA

LOA.
LeA TECHNOLOGY
Figure 3), is translated into the Xilinx Netlist Format using 1135 Q2
the PDS2XNF program and then optimized for the LCA
architecture using the XNFOPT program. PLD equations
like the ones shown below are in a sum-of-products form Figure 4. Flow Chart of Direct Translation of PLD
that does not always map efficiently into the CLBs of an Equations

6-9
Incorporating PLD Equations Into LCAs

DESIGN OPTIMIZATION into the PALASM2 Format. This PALASM2 formatfile can
then be translated into an XNF file and optimized like a
The cornerstone of the PLD conversion software is a PLD equation file originally entered in PALASM2.
program called XNFOPT. PLD equations are usually
expressed in a sum-of-products form that is not optimally
suited forthe CLB architecture, with blocks of 4 or 5 inputs SUMMARY
that perform any function of those inputs. The XNFOPT
program is used to optimize logic so that the logic fits In many cases, designs are most easily expressed using
efficiently into the CLBs and lOBs of the LCA. XNF files a combination of logic equations and schematics. Soft-
translated from PLD equation design files should always ware tools in Xilinx's ADI package give deSigners the
be optimized using the XNFOPT program; in some situ- capability to integrate equation and schematic entry meth-
ations XNFOPT may be used to optimize a design from a ods. The benefits of these logic synthesis tools are simpler
schematic as well, although there are some caveats. and more powerful design entry, more efficient use of LCA
logiC, and clearer design documentation.
There are some designs for which optimization using the
XNFOPT program is inappropriate. XNFOPT is meant for

~
synchronous designs, not asynchronous ones. XNFOPT
ABELORCUPL
significantly alters logic, so it may not preserve a deSign's DESIGN FilE ~
asynchronous timing dependencies. Furthermore, al-
though optimized logic is functionally equivalent to the ABEL OR CUPl TO PDS

I'M~r'l
original deSign, the structure may be significantly changed
making debugging more difficult. It is generally a good
idea to first simulate a design functionally to insure its PALASM
DESIGN FILE
correctness before optimizing it. Logic in an XNF file that
is expressed as CLB or CLBMAP primitives cannot be op-

I '~' I
timized, as it is already partitioned into the LCA architec-
ture.
UNOPTIMIZED
The XNFOPT program can be directed to optimize a XNF FILE

design for speed or for density. Optimizing for density

':f I
reduces the number of CLBs used by the deSign, while
optimizing for speed reduces the number of levels of logiC
used by the design. In its default mode of operation,
XNFOPT optimizes for density, using the -L option directs
XNFOPT to optimize for speed.
OPTIMIXED
XNF FILE
I
XNF2lCA

STATE MACHINES

Xilinx LeA designs can be entered as state machines

~~~~~l6INTO ~
~
lCA TECHNOLOGY
113503
through either the ABEL or CUPL PLD entry language.
Data 1/0's ABEL software and Logical Devices' CUPL
software offer options that convert their source design files Figure 5. Converting PLD Designs from ABEL or CUPL

6-10
 The XC2000 User's
Guide to the XC3000 Family.

In late 1987 Xilinx introduced the XC3000 family which, 1 additional horizontal long line per row.
within a year grew to five members: the XC3020, XC3030, 1 additional vertical clock line per column.
XC3042, XC3064 and XC3090.
• All CLB inputs and outputs have access to both horizon-
Designers already familiarwiththe original XC2000 family
tal and vertical routing channels:
may be interested in the following synopsis of the differ-
ences between the 2000 and 3000 families. • Capability of magic box is enhanced.

COMBINATORIAL LOGIC:
• Both horizontal long lines have 3-state bus drivers.

• Combinatorial logic is wider (5 inputs vs. of 4 in XC2000 • Bi-directional buffers are evenly distributed and used
family). only when needed to boost a signal.

CLB STORAGE ELEMENTS: OTHER DIFFERENCES

• There are two storage elements in a CLB. • Crystal oscillator has a "+ 2" option (50% duty cycle)
• Storage element is a flip-flop only, the latch option is • Oscillator output can be connected to the general inter-
eliminated. connect.
• Data input of either flip-flop can come from the combina- • Added fast, dedicated CMOS input buffer for the global
toriallogic output, (F or G,) or from the one direct data and alternate clocks.
input, DIN of each CLB.
• Capability of the edge magic box is enhanced.
• Clock input can be driven from local lines in addition to
• Each edge has two 10CLKS, clock source multiplexers
global and alternate clock lines,
are located in each corner.
• Enable Clock signal eliminates need for clock gating.
• 10CLK can be synchronized to the global and alternate
• Asynchronous set is removed but asynchronous reset is clock. 10Bon adjacent chip edges can be driven from the
retained, consistent with TTL-MSI design practices. same clock source.
• No flip-flop inputs are shared with combinatorial logic. • All 10CLK clock drivers can be inverted.
• Clock, Enable Clock, and Reset are commonto both flip- • Two vertical long-lines in each column and one long-line
flops. on each horizontal and vertical edge can each be split
into two half long-lines. (On the XC3020 this can only be

•
lOBs done with one long-line on each edge.)
• Both direct input (I) and registered input (Q) are available
simultaneously. DIFFERENCE IN CONFIGURATION
• Inputstorage element can be flip-flop or latch. • Parallel peripheral mode is added.
• Output signal and 3-state control signal can be inverted. • Modified timing for slave mode avoids hold time.
• Output signal can be either direct or registered. • No RCLK output in master serial mode, use CCLK.
• Output buffer has a programmable passive pull-up to • Modified pinout for master and peripheral mode, all data
prevent floating input. pins are on the right hand edge.
• Output buffer has option to slow down the output transi- • INIT state brought out as output.
tion to reduce transient noise.
• Done and Reset, programmable one clock early or late.
ROUTING RESOURCES: • PWRDN does not affect "House Cleaning".
1 additional horizontal local line per row.

6-11
 Designing with the
XC3000 Family

Application Brief BY THOMAS WAUGH

CLOCKING THREE·STATEBUFFERS

Global and Alternate Clocks Buffers Active High three-state is the sarne as active low enable.
There are two high-fanout,low-skew clock resources. The
In other words: A "1" on the T pin of a TBUF or an OBUFZ
global clock originates from the GClK buffer in the upper
three-states the output, and a "0" enables it.
left corner of the chip and the alternate clock originates
from the AClK buffer in the lower right corner of the chip.
Input/Output Blocks (lOBs)
These resources drive nothing but the K pins (clock pins) Unused lOBs should be left unconfigured. They default to
of every register in the device. They cannot drive logic inputs pulled High with an internal resistor.
inputs. In the rare case where this connection is required,
tap a signal off the input to the clock buffer and route it to lOB pullup resistors cannot be used with lOB outputs, only
the logic inputs. on pins that are inputs exclusively.

The global and alternate clocks each have fast CMOS Configurable logic Blocks (CLBs)
inputs, called TClKIN and BClKIN respectively. Using
these inputs provides the fastest path from the PC board ClBs have two flip-flops (not latches). They share a com-
to internal flip-flops and latches because the signal by- mon clock, a common reset, and a common clock enable
passes the input buffer. CMOS levels on the input clock signal.
signal must be guaranteed.
Asynchronous preset can be achieved by the asynchro-
To specify the use of TClKIN or BClKIN in a schematic, nous reset, by just inverting D and Q of the flip-flops.
connect an IPAD symbol directly to a GClK or AClK
symbol. Placing an IBUF between the IPAD and GClK or
AClK will prevent the TClKIN and BClKIN from being ROUTING RESOURCES
used.
Horizontal Long Lines

Always use GCLK and ACLK for the highest fanou~ clocks. The number of Horizontal long Lines (Hll) per device is
double the number of rows of ClBs.
I/O Clocks
The number of TBUFs that drive each Horizontal long
There are a total of eight different I/O clocks, two per edge Line is one higher than the number of columns on the
on each of the four edges. device.

I/O storage elements can be configured to be latches or Part Rows x TBUFs

flip-flops. Clocking polarity is programmable perclock line, Name Columns CLBs HLL. per HLL
not per lOB. A clock linethattriggers aflip-floponthe rising
edge can be an active low latch Enable (latch transpar- 3020 8x8 64 16 9
ent) and vice versa. 3030. 10 x 10 100 20 11
3042 12 x 12 144 24 13
Crystal Oscillator 3064 16 x 14 224 32 15
Connects to alternate clock buffer, AClK, not to GClK. 3090 20 x 16 320 40 17

Continued on the opposite page

6-12
 Designing with the
E:XILIXX XC2000 Family

Application Brief BY THOMAS WAUGH

CLOCKING CONFIGURABLE LOGIC BLOCKS (CLBS)

Global and Alternate Clocks Buffers CLBs have one storage element that can be configured as
a flip-flop or a latch.
There are two high-fanout, low-skew clock resources. The
global clock originates from the GCLK buffer in the upper CLB storage elements have both an asynchronous set and
left corner of the chip and the alternate clock originates an asynchronous reset.
from the ACLK buffer in the lower right corner of the chip.

The global clock buffer, GCLK, drives the Band K pins of ROUTING RESOURCES
the Configurable Logic Block (CLB).
Horizontal Long Lines
The alternate clock buffer, ACLK, drives the B, C, and K There is one Horizontal Long Line per routing channel.
pins of the Configurable Logic Block (CLB). The crystal
oscillator drives the ACLK. There are no internal three-state buffers on the chip.

Always use GCLK and ACLK for the highestfanout clocks. Vertical Long Lines

1/0 Clocks There are three Vertical Long Lines per routing channel,
one general purpose, one for the global clock net and one
There are four different 1/0 clocks, one per edge. for the alternate clock net.

1/0 flip"flops are positive-edged triggered. CLB pins with Direct Access to Long Lines
A- Horizontal Long Line above the CLB.
INPUTIOUTPUT BLOCKS (lOBS) B- Global clock buffer, Middle and Left Vertical Long
Line.
Unconfigured lOB outputs must not be left floating. Con- C- Middle and Left Vertical Long Line.
figure them as outputs and drive them from internal logic D- Horizontal Long Line below the CLB.
or leave them unconfigured and pull them up with an X- To Left Vertical Long Line.
external resistor. Y- To Middle Vertical Long Line.

Designing with the XC3000 Family (Continued)

T and I pins of TBUFs have limited interconnect resources.

Never use fewer than .four TBUFs per Horizontal Long

Line. When using TBUFs for multiplexing applications,
CLB Pins with Direct Access to Long Lines
A-
EC-
Lower Horizontal Long Line.
Left Middle Vertical Long Line.
•
B- Left Middle Vertical Long Line.
using fewer than four wastes resources. Use CLBs for
C- Right Middle Vertical Long Line
multiplexing instead.
K- Rightmost and Leftmost Vertical Long Lines
(ACLK and GCLK).
Vertical Long Lines
E- Right Middle Vertical Long Line.
There are four Ve rtical Long Lines per routing channel, two D- Upper Horizontal Long Line.
general purpose, one for the global clock net and one for RD- Left Middle Vertical and Lower Horizontal
the alternate clock net. Long line.
1976

6-13
 Additional
E:XILINX Electrical Parameters

Application Brief

The XILINX LCA data sheets specify worst case device OUTPUTS
parameters, 100% tested in production and guaranteed
over the full range of supply voltage and temperature. All LCA outputs are true CMOS with n-channel transistors
pulling down, p-channel transistors pulling up. Unloaded,
Some users may be interested in additional data that is not these outputs pull rail-to-rail.
100% tested and, therefore, not guaranteed. Here are
results from recent bench measurements:
DC Parameters

Output Impedance
PULL-UP RESISTOR VALUES
Sinking, near ground: 25n
Sourcing, near Vcc: son
lOB Pull-ups 40 to 150 kn
DONE Pull-up 2to 8 kn Output Short Circuit Current
Long Line Pull-up(each) 3 to 10 kn Sinking current by the LCA 96 mA
Sourcing current by the LeA 60mA
These values were measured with the node pulled LOW.
At a logic HIGH the resistor value is 5 to 10 times higher. The data sheets guarantee the outputs only for 4 mA at320 mV
in order to avoid problems when many outputs are sinking
current simultaneously.
INPUTS
AC Parameters Fast' Slow'
Hysteresis
Unloaded Output Slew Rate 2.8 V/ns 0.5 V/ns
All inputs, except PWRDN, and XTL2 when configured as
Unloaded Transition Time 1.45 ns 7.9 ns
the crystal oscillator input, have limited hysteresis, typi- Additional rise time for 812 pF 100 ns 100 ns
cally in excess of 200 mV for TTL input thresholds, in normalized 0.12 ns/pF 0.12 nspF
excess of 100 mV for CMOS thresholds. Additional fall time for 812 pF 50 ns 64 ns
normalized 0.06 ns/pF 0.08 nspF
Required Input Rise and Fall Times
, "Fast" and "Slow" refer to the output programming option.
For unambiguous operation, the input rise time should not
exceed 200 ns, the inputfall time should not exceed 80 ns. There is good agreement between output impedance and
loaded output rise and fall time, since the rise and fall time is
These values were established through a worst-case test slightly longer than two time constants.
with internal ring oscillators driving all I/O pins except two,
thus generating a maximum of on-Chip noise. One of the
remaining 1/0 pin was then tested as an input for single-
edge response, the other one was the output monitoring
the response. This specification may, therefore, be overly
pessimistic, but, on the other hand, it assumes negligible
PC board ground noise and good Vcc decoupling.

6-14
 E:
Power Dissipation: Vcc T Fr~q

LCA power dissipation is largely dynamic, due to the 4.5V 25°C 687 kHz
charging and discharging of internal capacitances. The 5.0V 25°C 691 kHz
dynamic power, expressed in mW per MHz of actual node 5.5V 25°C 695 kHz
or line activity is given below. 4.5V -30°C 966 kHz
4.5V +130°C 457 kHz
Clock line frequency is easy to specify, but the designerwill
usually have great difficulty estimating the average fre-
quency on other nodes.
CRYSTAL OSCILLATOR
Two extreme cases are:
The on-chip oscillator circuit consists of a high-speed, high
gain inverting amplifier between two device pins, requiring
1. Binary counter, where half the total power is dissipated
an external biasing resistor R1 of 4 MQ.
in the first flip-flop.
A series-resonant crystal Y1 and additional phase-shifting
2. A shift register with alternating zeros and ones, where
components R2, C1 , C2 complete the circuit.
the whole circuit is excercised at the clocking speed.

Dynamic Power Fundamental Frequency Operation up to 24 MHz:

(mW/MHz)
C1 = C2 = 34 pF
R2 = 1 KO up to 12 MHz, 8000 to 520 0 for 15 to 24 MHz
Output with 50 pF load' 1.9
Global Clock (XC3020) 1.7
Global Clock (XC3090) 3.6
Third Overtone Operation from 20 MHz to 72 MHz:
CLB with Local Interconnect 0.36
Replace C2 with a parallel resonant LC tank circuit tuned
Horizontal Long Line (XC3020) 0.09
Horizontal Long Line (XC3090) 0.15 to ~ 2/3 of the desired frequency, i.e., twice the crystal fun-
Vertical Long Line (XC3020) 0.08 damental frequency.
Vertical Long Line (XC3090) 0.19
Input without Pull-up 0.075

Frequency LCTank
'Add 2.5 mW/MHz for every 100 pF of additional load (MHz) L (IlH) C (pF) Freq (MHz) R2 (0) C1 (pF)

32.00 60 20.6 430 23

Example: Dynamic Power 35.00 44 24.0 310 23
XC3020 with (mW/MHz) 49.00 31 28.6 190 23
72.00 18 37.5 150 12
3 outputs at 5 MHz 28
20 outputs at 0.1 MHz 4
Global Clock at 20 MHz 34
10 CLBs at 5 MHz 18

•
40 CLBs at 0.2 MHz 3
16 Vertical Long Lines at 1 MHz 1
20 Inputs at 4 MHz 6

Total 94mW

CCLK Frequency Variation

R1
Configuration Clock (CCLK) is the internally generated
R2
free-running clock that is responsible for shifting configu-
ration data into and out of the device.

CCLK frequency is fairly stable over Vee, varying only

0.6%.for a 10% change in Vcc, but is very temperature I C2_C(JL
3RD
OVERTONE

dependent, increasing 40% when the temperature drops

from 25°C to -30°C, decreasing 40% when the tempera-
ture increases from 25°C to +130°C. 115802
Crystal Oscillator

6-15
 LeA Performance

Application Brief

ESTIMATING CLB PERFORMANCE -50 -70 -100

clock-to-output 12 ns 8 ns 7 ns
Since the delays in LCA-based designs are lay-out de- routing 12 ns 8 ns 6 ns
pendent, the data sheet cannot give all the answers logic set-up 12 ns 8 ns 7 ns
needed to predict the worst case guaranteed perform- clock period 36 ns 24ns 20 ns
ance. clock frequency 28 MHz 42 MHz 50 MHz

The timing calculator in )(ACT is a better tool, and a 3. An additional level of combinatorial logic plus routing
simulation using SILOS, after the design has been routed, reduces performance further:
will be the final arbiter for worst-case performance.
-50 -70 -100
Still, most designer want to evaluate the possible perform- clock-to-output 12 ns 8 ns 7 ns
ance, well before they have finished the design. routing 12 ns 8 ns 6 ns
logic delay 14 ns 9 ns 7 ns
Here are some guidelines for XC3000 family devices: routing 1 ns 1 ns 1 ns
logic set-up 12 ns 8 ns 7 ns
1. A simple synchronous design-like a shift register, clock period 51 ns 34ns 28 ns
where a flip-flop feeds a flip-flop in the next vertical or clock frequency 20 MHz 29 MHz 36 MHz
horizontal CLB through the one level of combinatorial
logic in front of the target flip-flop: Therefore, as a rule of thumb, the system clock rate should
not exceed one third to one half of the specified toggle rate.
-50 -70 -100
clock-to-output 12 ns 8 ns 7 ns Simple deSigns, like shift registers and simple counters,
routing 1 ns 1 ns 1 ns can run faster, approximately two thirds of the specified
logic set-up 12 ns 8 ns 7 ns toggle rate.
clock period 25 ns 17 ns 15 ns
These numbers assume synchronous clocking from the
clock frequency 40 MHz 59 MHz 67 MHz
global clock lines. Remember, these are all worst-case
2. A similar design with flip-flops several rows or columns numbers, guaranteed over temperature and supply volt-
apart would add routing delay: age. Nobody should design with typical numbers.

I- SINGLE LEVEL
~-
TWO-LEVEL
-I
CLOCK TO OUTPUT SETUP CLOCK TO OUTPUT COMBINATORIAL SETUP

I- TCKO -4 I+- TICK

-+-- TCKO ----l I+- TILO
----l I+-- TICK
--I
ClB ClB ClB

INTERCONNECT
0 0 0 a 0 0

C~CK-*--------------------------------~------------------------------~ 1159 04

Figure 1. Critical Timing Parameters for Clocked CLB Driving Clocked CLB Directly (Single Level)
and Driving it Through Additional Combinational Logie (TWO-Level)

6-16
 E:XIIJNX

DESIGNING FOR HIGHEST DATA TRANSFER RATE time is:

BETWEEN 3000 FAMILY LeAs
20-3-6 = 11 ns for the -70 device
Worst case analysis of a synchronous data transfer be- 30-5-9 = 16 ns for the -50 device
tween 3000 family devices postulates that the sum of
clock-to-output propagation delay of the sending device, Under these assumptions, the worst case (shortest) value
plus the input-to-clock set-up time of the receiving device, for the clock period is:
must be less than the clock period.
22 + 11 = 33 ns, I.e., max 30 MHz for the -70 device
The inherent freedom in clock and signal routing makes it 31 + 16 = 47 ns, I.e., max 21 MHz for the -50 device
impossible to give exact values for an unprogrammed LCA
without specifying certain restrictions: Bypassing the input flip-flop in the lOB and going directly
to the DI input of the closest CLB is another, non-obvious,
Onthe transmitting LCA, the clock-pinto output-pin propa- way of improving performance by 8 ns forthe -70 device,
gation delay is minimized if TCLKIN or BCLKIN are chosen by 12 ns for the -50 device.
as clock inputs. They are CMOS-level only, and offer the
shortest on-chip clock delay. Ifthis is notfast enough, there are design methodS that can
improve the performance. Let us assume a -70 device.
The clock-pin to output delay is then The easiest and safest method is to increase the clock
delay on the receiving LCA, thus reducing the apparent
3 + 6 + 13 = 22 ns for the -70 part input set-up time. Changing to a direct input (instead of
5+9+18=31 nsforthe-50part TCLKIN) adds 4 ns to the clock delay, thus subtracts at
least 3 ns from the input set-up time.
On the receiving LCA, the input-pin to clock-pin set-uptime
is the specified I/O pad input set-up time (parameter TPICK More aggressive methods of increasing clock delay inside
in the lOB switching characteristic table of the XC3000 or outside the receiving LCA must be used with care, since
family data sheet) minus the actual delay for clock buffer- they might reduce the "best case" set-up time (fast proc-
ing and routing. ess, low temperature, high Vcc) to a value of less than
zero, i.e., make it a hold time requirement, which, in
Assuming the same clock buffer choice on the receiver as conjunction with a best case very fast transmitting device,
on the transmitter, the longest input-pin to clock-pin set-up can lead to problems.

T OKPO ~

CLOCK

I+- TClKIN -+-

Figure 2. CrItical TIming Parameters for Data Transfer Between LeAs

T GClK-of
115903
•
6-17
LeA Performance

INPUT SET-UP TIME ON A 3000 SERIES LCA IS WHY ARE THERE NO GUARANTEED MIN. DELAY
BETTER THAN THE SPECIFICATION. SPECIFICATIONS?

The Xilinx 3000 series data sheet specifies a worst case IC manufacturers do not usually guarantee minimum
input set-up time of 20 ns for the -70 speed grade propagation delay values, though some specify a token
(parameter #1 on page 41), but this is the data input pad min delay of 1 ns. There are compelling reasons:
set-up time with respect to the internal lOB clock, not with
respect to the clock input pad. These short delays are extremely difficult to measure on a
production tester. Even if it were possible, the necessary
Any delay from clock pad to lOB clock must be subtracted tester guard-banding might make the result
fromthe specified set-up value in orderto arrive atthe true meaningless.The spread between a conservative worst-
systems set-up time as seen on the device package pins case maximum value and a similarly conservative worst-
(pads) for data and clock. Since the internal clock delay case (best-case?) minimum value would be surprisingly
can be manipulated by the user, Xilinx cannot specify the large. There are five reasons:
systems set-up time.
1. Temperature. CMOS propagation delays decrease
The shortest possible clock delay from the package pin to approximately 0.3% per degree C.
the lOB clock is achieved by selecting the CMOS
compatible clock inputs TClK or BClK. The guaranteed 2. Supply Voltage. CMOS propagation delays are roughly
max value for their delay is 9 ns (XC3000-70), the sum of inverse proportional to Vcc.
3 ns for pad-to-ClKIN plus 6 ns for the clock buffer and
clock distribution. 3. Test Guardband. The max delay test is performed at a
temperature well above TMAX and a supply voltage
Xilinx does not guarantee any shortest values for all these well below Vee MIN. The accepted max delay is
parameters. An unrealistic worst-worst case analysis also less than the data sheet value. Equally conserva-
might, therefore, assume two extreme values: tive methods applied at the opposite extremes would
give very short values.
20 ns set -up time for a slow data input with an infinitely
fast clock path
4. Process Variations. lCAs are sorted into a few speed
9 ns hold time for an infinitely fast data input combined classes. A part marked-50 might have barely missed
with a slow clock path. the -70 specification in only a few or perhaps only one
parameter. IC manufacturers may sometimes mark
That is a meaningless mathematical exercise. In reality, down (call a -70 part a -50 part) in order to adjust
all these delays track very well over temperature, supply production yield to market demand. This increases the
voltage and processing variations, never deviating more spread even more.
than 30% from each other's normalized value. When one
parameter is at its absolute max value, any other parame- 5. Process Evolution. As IC technology improves, smaller
ter will be between 54% and 100% of its max value (54= geometries reduce not only device size and cost, but
100 x 0.71 1.3). The longest required set-up time for the also propagation delay. Tight min. specifications would
data input with respect to the CMOS compatible clock be a hindrance to progress.
input is, therefore, 15 ns (20 ns minus 54% of 9 ns).

Finally, it can be argued that a proper synchronous design

What is the shortest set-up time, Is there a danger of
is insensitiveto minimum propagation delay values. When
malfunction due to a positive hold time?
the clock skew is small, ( Xilinx clock networks guarantee
extremely small clock skew values, less than 2ns over a
The fastest delay parameter is always longer than 10% of
big chip like the XC3090) the designer can safely ignore
the specified guaranteed max value for the fastest
the minimum delay issue. No Xilinx ClB or lOB input has
available version of this device. The fastest value occurs
a hold time requirement.
at the lowest temperature and highest supply voltage.

The shortest data set-up time with respect to the CMOS In the past, designers have faced far greater uncertainties
compatible clock input is, therefore, 1.1 ns (10% of 20 ns when they populated PC boards with a variety of SSI, MSI
minus 9 ns). This is still a positive value, sometimes called and PAL devices, each from a different production run,
a negative hold time. each with different power dissipation and junction tem-
perature. Such problems do not exist inside the lCA
There will never be a hold time requirement if the user where delays track, and the temperature is the same for all
selects the CMOS compatible clock input option. elements.

6-18
 Start-Up and Reset

Application Brief

INTERNAL LOGIC DURING CONFIGURATION SYNCHRONOUS RESET AFTER CONFIGURATION

During configuration, all 1/0 pins not used forconfiguration After configuration is completed, the LCA becomes active
are 3-stated and all internal flip-flops and latches are held in response to a rising edge of CCLK. All outputs that go
reset until the chip goes active. Even multiple LCAs active will do so simultaneously, but they are obviously not
hooked up in a daisy chain will go active simultaneously as synchronized to the system clock. Some designs might
a result of the same CCLK edge. This is well documented. require a reset pulse synchronous with the system clock to
avoid start-up problems due to asynchronous timing be-
Not documented is how the internal combinatorial logic tween the end of internal reset and the system clock.
comes alive during configuration: As configuration data is
shifted in and reaches its destination, it activates the logic The circuit below generates a short global reset pulse in
and also "looks at" the inputs .. Even the crystal oscillator response to the first system clock after the end of configu-
starts operating as soon as it sees its configuration data. ration. It consumes one CLB plus one output pin, and it
Since all flip-flops and latches are being held reset, and all also precludes the use of the "LDC" pin as 1/0.
outputs are being held 3-stated, there is no danger in this
"staged awakening" of the Chip. The user can take
During Configuration:
advantage of this to make sure that the chip comes to life
with the internal output 3-state control signal on the output LDC (Low) holds D High, but Q is held Low by internal
driver already active before the end of configuration, so reset.
that there is no chance of any output glitch. RESET is pulled High by internal and external resis-
tors.
FAST RECOVERY FROM RESET
End of Configuration before first System Clock:
Recovery from Reset is not specified in our data sheets
LDC pin goes active High, Q stays Low, D stays High.
because it is very difficult to measure in a production
RESET is still pulled High by external resistor.
environment.
Result of first System Clock after end of Configuration:
Here are benchmark values:
The CLB can be clocked immediately (i.e. within 0.2 ns) Q is clocked High, which forces D Low.
after the end of the internal direct reset (rd). Output driver goes active Low and forces RESET Low.
This resets the whole chip until the Low on Q
The CLBcan be clocked no earlier than (worst case) 25 ns causes RESET to be pulled High again
after the release (rising edge) of the externally applied The whole chip has thus been reset by a short pulse •
Global Reset (acting Low) signal. instigated by System Clock.

1971 01
HIGH -+.-l>'-'--+-
f lOB _
~::.:.:.:.:.:-:.:.:.:-:.:-:.:-:-:.:.:.:.:::
Figure 1. Synchronous Reset

6-19
Additional Electrical Parameters

Metastable Recovery

Applications Brief BY PETERALFKE &PERRYWU

CLB FLIP-FLOPS RECOVER SURPRISINGLY FAST When an asynchronous event frequency of approxi-
FROM METASTABLE PROBLEMS mately 1 MHz is being synchronized by a 10 MHz clock,
the CLB flip-flOp will suffer an additional delay of
A specter is haunting digital design, the specter of metas-
tability. From a poorly understood phenomenon in the 4.2 ns statistically once per hour
seventies, it has developed into a scary subject for every
designer of asynchronous interfaces. Now Xilinx offers 6.6 ns statistically once per year
data and a demonstration kit to help users analyze and
8.4 ns statistically once per 1000 years
predict the metastable behavior of LCAs.

Whenever a clocked flip-flop synchronizes a truly asyn- Thefrequency of occurrence of these metastable delays is
chronous input, there is a small but finite probability that proportional to the product of the asynchronous event
the flip-flop output will exhibit an unpredictable delay. This frequency and the clock frequency.
happens when the input transition not only violates the
If, for example, a 100 kHz event is synchronized by a 2
setup and hold-time specification, but actually occurs
MHz clock, the above mentioned delays (besides being far
within the tiny timing window where the flip-flop "decides"
more tolerable) will occur 50 times less often.
to accept the new input. Under these circumstances the
flip-flop enters a symmetrically balanced state, called The mean time between metastable events lasting longer
metastable, (meta = between) that is only conditionally than a specified duration is an exponential function of that
stable. The slightest deviation from perfect balance will duration. Two points measured onthat line, allow extrapo-
eventually cause the outputs to'revert to one of the two lation to any desired MTBF (mean time between failure).
stable states, but the delay in dOing so depends not only on
the gain bandwidth product of the circuit, but also on the
MTBF
original balance and the noise level of the circuit; it can,
SEC
therefore, only be described in statistical terms.
10 '1

The problemforthe system designer is not the illegal logic 10 '0

level in the balanced state (it's easy enough to translate
10'
that to either a 0 or a 1), but the unpredictable timing of the
final change to a valid logic state. 10·
1 YEAR
10 7
The basic phenomenon is as unavoidable as death and
1 MONTH
taxes, but the probability of erroneous operation can be 10·
determined, and the impact of various countermeasures
10'
can be evaluated quantitatively, if two fundamental flip- 1 DAY

flop parameters are known, i.e., the metastability capture 10'

window, and the metastability recovery rate. 1 HOUR
10'

Xilinx has evaluated the XC3020 CLB flip-flop with the help 10 2
of a mostly self-contained circuit on the Demonstration
10'
Board that is available to any Xilinx customer.

The result of this experimental evaluation shows the Xilinx 4 6 NS

1160 01
CLB flip-flop superior in metastable performance to many
popular MSI or PLD devices. Metastable MTBF as a Function
of Additional Acceptable Delay

6-20
Metastable Recovery

MEASURING METASTABLE RECOVERY Every ns in additional acceptable delay reduces the

frequency of metastable events by a factor 40.
The excellent metastable recovery rate of Xilinx lCA flip-
flops was measured in a working XC3020-70 on the Xilinx The MTBF curve was then normalized to a reasonable
evaluation board. Since metastability can only be meas- combination of clock and asynchronous data rates, using
ured as a statistical event, the device was configured with the generally accepted theory that, everything else being
eight concurrent detectors: equal, the frequency of metastable events is proportioned
to the product of the two frequencies at the D and ClK
Eight D flip-flops are clocked from a common high speed inputs of the flip-flop under test.
source. Their D inputs are driven from a common, lower
frequency asynchronous signal. Each flip-flop feeds the
D inputs of two more flip-flops, one of them clocked on the Assuming that the metastable window is 0.1 ns wide, and
opposite clock edge. This cuts the clock rate forthe experi- the clock is 10 MHz, one data change in 1000 will fall into
ment in half, from 50 MHz to a more manageable 25 MHz. the metastable window. A 1 MHz data rate gives an MTBF
A comparator detects when 01 differs from D = 00 = 02. of 1 ms for an additional delay of zero. Each additional ns
of acceptable delay increases the MTBF by a factor 40,
This can only be the result of 00 having a clock-to-output see diagram on the previous page. It is difficult to measure
delay in excess of a half clock period minus a set-up time. the exact width of the window, but it hardly matters. If the
Varying the clock frequency and monitoring the pulse rate assumption of 0.1 ns were wrong by a factor of 10, it would
at the detector gives an indication of the probability of only move the graph horizontally by 0.624 ns.
metastable delays.
Over the past fifteen years this writer has made many
The deliberate skew on the D-inputs of the eight flip-flops attempts to pin-point, demonstrate and quantify metas-
under test makes it extremely unlikely that more than one table behavior. Success came with the integration of
flip-flop will go metastable on anyone clock edge. The multiple test circuits, multiple detectors and a common
eight detector outputs can, therefore, be ORed together read-out, all in one Logic Cell Array.
and drive a counter with LED read-out. As expected, no
metastable events were observed at clock rates below After so many inconclusive attempts, any repeatable re-
25 MHz since a half clock period of 20 ns allows for propa-
sults would have been appreciated, but these results also
gation delay plus set-up time.
show the metastable response of LCA flip-flops to be
superior to any othercircuil documented so far. There is
Increasing the clock rate brought a sudden burst of metas-
a reason. lCA flip-flops are dedicated circuits, small and
table events around a clock rate of 27 MHz. Careful adjust-
very fast, with an extremely short loop delay. TTL flip-flops
ment of the clock frequency gave repeated, reliable meas- are bigger and slower, and gate arrays and gate-array-like
urements showing that a 500 ps decrease in the relevant
structures that construct their flip-flops by interconnecting
half clock period increased the frequency of metastable
gates are bound to be far inferior.
occurrences by a factor of 41. In order to be conservative,
to compensate for favorable conditions at room tempera-
ture, and to avoid any possibility of overstating a good Metastability is still a treacherous subject, but lCAs offer
case, the measurement was interpreted as follows: the closest thing to an acceptable solution.

D o 0,
CLB/----;",r......,
00
J
//////1,
,

,
:1
NON-METASTABLE

METASTABLE
,
:
,,

!f
•
, :
,,
CLOCK
,
/ ,
D 02 CLOCK
- I
: :
1/
.
COUNT PlLSE IFMETASTA8lE

REPEATED EIGHT TIMES

6-21
 Battery Backup for
Logic Cell Arrays

Application Brief BY DAVID P. LAUTZENHEISER

Logic Cell Arrays use a high performance low power Figures.1 and 2 show two circuits which satisfy the above
CMOS process. They can, therefore, preserve the pro- requirements. In Figure 1, discrete components are used
gram contents stored in the internal static memory cells to perform the switching while the power sensing is per-
even during a loss of primary power. This is accomplished formed by a linear circuit, the TL7705A, made by Texas
by forcing the device into a low-power non-operational Instruments. This circuit lets the user adapt the Vcc pass-
state while supplying Vee from a battery. transistor to the load required. The same switching ar-
rangement might also be used to battery back-up addi-
There are two primary considerations for battery backup tional circuits, such as RAMs. The user also has control
which must be accomplished by external circuits: over the timing of the PWRDWN signal after Vee has re-
turned. While the LCA only requires microseconds to
• Control of the Power-Down (PWRDWN) pin and return to a normal state, other circuits may want to have a
longer RESET period.
• Switching between primary Vee supply and battery.

Important considerations are: Figure 2 uses a single chip solution, the DS1259 from
Dallas Semiconductor Corporation,
• Insure that PWRDWN is asserted logic Low prior to Vcc 4350 Beltwood Parkway South, Dallas, Texas 75244,
falling, held Low during the primary Vee loss time, and Telephone (214) 450-0400.
returned High after Vee has retumed to a normal level. The user only needs to supply the device and battery to ac-
PWRDWN edges must not be slow rising or falling. complish the desired function. The DS 1259 provides up to
250 mA of Icc with a drop of less than 0.2 Volt.
• Insure "glitch-free" switching of the power connections
to the LCA from the primary Vee to the battery voltage
In both circuits, the user must supply both bulk and high
and back.
speed decoupling. Use a large bulk capacitor in conjunc-
• Insure that during normal operation the LCA Vee is tion with a high speed 0.1 IlF capacitor for each Vcc pin.
maintained at an acceptable level, 5.0 Volts ± 5% (±1 0% Both capacitors should have low leakage to insure long
for Industrial and Military). battery life.

+ BATTERY
(3.•••V) C>----Dt-------,
FROM Vee Cl--1r-----------{; :r-i-,.-..,....-o TO Vee
SOURCE 10 " OF L.CA

+-_ _-V1~K~-~r-4_---~__Oro~
PIN OF LCA
• BATTERY 2 Vbat
(3_.4V)
6 RST DSl25D
• Vee
7 SENSE 7 GND
2 RESIN • GNO Pi'1-'1",-1_ _ _ _-o~~~~~~~N

19n 01 19n 02

Figure 1. Discrete Battery Backup Clrcul~ Figure 2. Integrated Battery Backup Circuit

6-22
 Compact Multiplexer and
Barrel Shifter

Application Brief

FOUR-INPUT MULTIPLEXER IN ONE CLB FOUR-BIT BARREL SHIFTER IN ONLY FOUR CLBs

Since the function generator in the XC3000 series CLB A four-input barrel shifter has four data inputs, four data
has only five inputs, it cannot directly implement a 4 input outputs and two control inputs that specify rotation by 0, 1,
multiplexer which needs four data inputs and two select 2 or 3 positions. A brute force design would use four 4-
inputs. input multiplexers, since each output can receive data
from any input. Each four multiplexer requires two
Registering one of the select inputs in the same CLB frees XC3000 family CLBs, for a total of eight CLBs.
up one input and puts a complete 4-input multiplexer into
one CLB. It is even possible to register the multiplexer There is, however, a smarter method that reduces the
output. deSign to .only four CLBs. The key to this approach lies in
the signal cross-overs althe input and output of the second
This non-obvious trick increases the apparent delay of the level CLBs.
registered select input, but that will be acceptable in the
majority of applications. Since it reduces not only the size Eight-Bit Barrel Shifter in 12 CLBs
but also the through-delay of the 4-input multiplexer by
50%, this approach is definitely worth considering. The 4-Bit Barrel Shifter design can be extended to eight
bits. A first level shifter consisting of four CLBs rotates the
eight inputs by one position, controlled by the least signifi-
cant control input. Two interleaved 4-Bit Barrel Shifters
o 0 then take the eight outputs from the first level and rotate
them by 0, 2, 4 or 6 positions.

l'

197801
So di o 0 3'

•
80 8,
1978 02

6-23
Additional Electrical Parameters

Majority Logic,
Parity

Application Brief

MAJORITY LOGIC, N-OF·X DECODING PARITY

Majority logic has interesting mathematical features, but Two CLBs can generate the parity for nine inputs, or can
has not become popular because its traditional logic check a nine-bit input for odd or even parity with a through-
implementation is quite complicat~ and expensive. delay of two cascaded CLBs. Three CLBs can check
Since LCAs can generate any functiQn of five variables at 13 inputs; four CLBs can check 17 inputs; five CLBs can
the same cost and the same delay, they can easily decode check 21 inputs; six CLBs can check 25 inputs; all with the
majority logic. same delay of two cascaded CLBs.
We can define the output F, Gto be Low for 0, 1, or2inputs
High, to be High for 3, 4, or 5 inputs High.

MajOrity logic is a special case of "N-of-X Deepding." A

3000-series CLB can directly encode any "N of 5" inputs
active. This concept can be cascaded so that three LCBs
encode any "N of 7" inputs active. 9 INPUTS

OPOOREVEN

1139 02 Figure 2. Parity

5-INPUT MAJORITY FUNCTION:

F. ABC + ABO + ABE + ACO + ACE
+AOE +SCO+ BOE + SCE+ CDE

NOF7

113901 Figure 1. N of X, e.g., Majority logic

The first-level blocks can only nave 3 inputs, since the two
outputs can only encode4 different states: none, one, two,
or three active.

6~24
 Multiple Address Decoding

Application Brief

A 3000-series CLB can decode a 5-bit address in any Address Block Detection
conceivable way, or it can decode a 4-bit address in two
different ways, each without any restrictions. The idea mentioned above is not restricted to detecting
three specific addresses, it can also detect th ree groups of
8 0
addresses, as long as none of them straddles the bounda-
II ~I ries defined by the individual CLBs. If they do, this circuit
cannot detect three address blocks, but can still detect any
one address block in an 8-bit address.

Suppose we want to decode the block of 8-bit addresses

starting at 24 and including 68 (hex).

With one CLB we encode the least significant address

nibble into a 2 bit output called LS:
~IIIIWA !@"al inputs 0 through 3 generate LS = 1
114001 inputs 4 through 8 generate LS = 2
,Figure 1. Multiple Address Decoding inputs 9 through F generate LS = 3

With another CLB we encode the most significant address

Three 3000-series CLBs can decode three distinct
nibble into a 2 bit output called MS:
addresses in an 8-bit address field: One CLB decodes the
lower 4 bits and encodes the result on its two outputs inputs 0, 1, 7, 8 through F generate MS 0 =
(00 = no match). The second CLB decodes and encodes input 2 generates MS = 1
the upper 4 bits in a similar way. input 3,4,5 generate MS = 2
input 6 generates MS = 3
The third CLB encodes the four signals into two outputs
(00 = no match). This works for any three distinct The third CLB then encodes these signals
addresses, even when some share the same upper or
lower nibble. MS LS Output

This scheme can be expanded to a 16-bit wide address, 0 x 0

using sevenCLBs. 1 2,3 1

•
2 x 1
3 1,2 1
MSB 1 - - - - - - , 3 3 0

The solution can be generalized:

Three CLBs can decode anyone block of an 8-bit address.

LSB

114002
Figure 2.

6-25
 Binary Adders, Subtractors
E:XllJXX and Accumulators

Application Brief

There are many different ways to implement binary descendents. These signals can reduce the ripple carry
adders, subtractors and accumulators in Xilinx LCAs, delay. Both CP and CG are outputs from an arithmetic
using different trade-offs between size and speed. block (often of four bits). Both these outputs can be
generated immediately since they are not affected by any
Most compact, but slowest is the bit-serial function that incoming carry that might arrive late. As the names imply,
operates on one bit pair per clock cycle, generating sum Carry Generate is active if the block creates an overflow
and carry. The sum is fed back into the shiftregister, the (carry), e.g. if the 4-bit sum, regardless of incoming carry,
carry is stored for the subsequent bit time. exceeds F. Carry Propagate is active if the block does not
generate a carry by itself, but would generate a carry as a
The most compact combinatorial (parallel) adder, result of an incoming carry. In our 4-bit example this
subtractor, or accumulator consists of cascaded CLBs. occurs when the sum is exactly F.
Each CLB (XC2000 or XC3000 family) is a full adder,
accepting one operator bit pair (A, B) and an incoming There is an even faster algorithm. As originally described
carry. The CLBgeneratesthe sum and the outgoing carry. by J. Sklansky in the June 1960 issue of the IRE Transac-
A 16-bit function requires 16 CLBs. It performs an tion on Electronic Computers, Conditional-Sum Addition
operation in 16 combinatorial delays. can save time at the expense of higher logic complexity.
Matt Klein of Hewlett Packard recently modified this algo-
The 5-input function generator of the XC3000 family can rithm to fitthe XC3000 architecture. His design requires 41
add a carry to two operator pairs. Three CLBs can thus CLBs to add or accumulate two 16 bit numbers in only
handle two input bit pairs, generating two sum outputs and three(!) combinatorial delays. With careful layout, such an
the outgoing carry. A 16-bit function requires 24 CLBs. It adder! accumulator can run at 30 MHz.
performs an operation in 8 combinatorial delays.
Note that all Xilinx adder structures can also be an accu-.
Carry Propagate and Carry Generate are intermediate mulator without any size or speed penalty. Conventional
signals that can speed up the operation as shown on gate arrays and other gate array-like structures usually
pages 6-27 and 6-28. Such a 16 bit function requires 30 configure flip-flops out of gates. The flip-flop set up time
CLBs. It performs an operation in 6 combinatorial delays. must then be added to the combinatorial propagation
delay. Xilinx LCAs hide the flip-flop set up time in the com-
The concept of Carry Propagate and Carry Generate has binatorial propagation delay of the CLB. Adders and
been made popular by the 74181 ALU and its accumulators thus operate at the same speed.

1979

6-26
 Adders and
Comparators

Application Brief BY PETERAlFKE

The LCA-structure accommodates 1-bit and 2-bit adders For eight bits, this look-ahead carry scheme is of marginal
very efficiently. A 1-bit adder with 3 inputs (A ;B, Cin) use, it reduces only the carry delay, and only by one CLB
generating 2 outputs (S, Cout) fits exactly in one 2000 delay. For this small speed improvement it uses two
series CLB, where the flip-flop might be used for storing the additional CLBs (14 instead of 12). See truth table on page
carry in a bit serial adder. A 3000-series CLB can even 6-24.
include an additional control input, either ADD/SUB-
TRACT or ADD ENABLE. A 16-bit adder benefits from carry-Iookahead. Simply
cascading di-bit adders uses 24 CLBs at a max propaga-
A two-bit adder requires three 3000 series CLBs. The five tion delay of 8 CLBs from Cin to Cout orto S14, 15. A look-
inputs AO, BO, A 1, B1, and Cin are common to all three ahead carry scheme uses 30 CLB at a max prop delay of
CLBs, the outputs are SO, S1, and Cout. The propagation 5 CLBs from Cin to Cout(6 delays to S14, 15).
delay is only one CLB combinatorial delay, as little as 10
ns. Two such adders can be cascaded to form a four bit
adder in 6 CLBs with a through-delay of two CLBs, i.e.,
25 ns (allowing for some interconnect delay).

Four two-bit adders can be cascaded to form a byte-wide C,"

adder, using 12 CLBs with a through-delay of 4 CLBs, but A, 1--+-+---+8,
B, 1-t-+-+-_8, 14 CLBs
there is also a slightly faster design using a carry look- A,
B, 3 Delays to COUT
ahead technique: The third and fourth di-bit adders are
4 Delays to S6, S7
changed, they no longer generate Carry out, but now each
generates two outputs as a function of the four A and B
inputs (ignoring Cin). These two outputs are called Carry
Generate (when the addition exceeds a binary 3) and
.,
A, H-+---+8,
Carry Propagate (when the addition is exactly 3). These
outputs from two di-bit adders are combined with Cin and
generate the Carry inputs to the fourth di-bit adder and its
.,
A,
1--+-1--1-- s,

carry out. The whole 8 bit adder uses 14 CLBs and has a C,

through-delay of four CLB delays from input to S6 and S7,

only three CLB delays from input to Cout.

•
I--++-+-+--- s,
I I--I--+--I-++s,
I
C,
A N-
o- S,
So co
CP

B
A
B
0-
:=:
I-

r-
I-
C,
co
CP

C2

I-+---s,
I-+---s,
A2=: S3
B
A:=:
B3 - I-
I-
COUT

1141 01 1141 02
Figure 1. 4-Bit Adder Figure 2. 8-Bit Adder with Carry Lookahead

6-27
 e.

I
-J '-

So -
=: s,
-J I-
I f-
-J - A.
4
_ S.
e2 B. _ f- S9
A. _
B. _ I--

~
~ -
l-
f-
~
=:
-J S3
S2 ~ -
-J I- e,o
-J f-

C. I
~ -
4

I
I -
I-- A,o-
B,o- -
I--

S"
s,o
A,,_
~
B,,_ r--
S.
S5
== I--
C'2

== ~
~ -
-
~ r--
~ - I -
C. L.t
A'2- S'2
B'2- S'3
I
-
A'3-
I--
I - B'3-
eG~
=: t--
S.
~
~
-
~

-
S7 ~

== r-- e,.

30 CLBs I
5 Delays to COUT
r--
-J t--
6 Delays to S14, S15 5,.
A,.-t I- 5'15
B'4-t
A,;=: -
B'5
1141 03

Figure 3. 16-81t Adder with Carry Lookahead

6-28
Adders and Comparators

Adder Logic Truth Tables Bit-Serial Adder, Subtractor, Comparator

After adjusting the subscripts appropriately. the truth table The CLB architecture is ideally suited for bit-serial arithme-
for the three CLBs generating 8 2 and S3 is identical with tic. where the function generator performs the serial arith-
that for the CLBs generating So and S1; and the truth table metic (LSB first). and the associated flip-flop stores the
for the bottom three CLBs is identical to that of the three carry or borrow.
CLBs generating S4 and S5'

The 16-bit adder is a natural extension of the 8-bit adder. A I---*"---*I 0 Q

B
Inputs ADDISUBTRACT
Outputs C, A, B, A B,
S,=1 1 0 0 x x
0 1 0 x x
0 0 1 x x CLOCK - - - , - - - - - '
1 1 1 x x 1141 04
S,=1 x 1 1 0 0 Figure 4. Serial Adder/Subtractor
1 x 1 0 0
1 1 x 0 0
x 0 0 1 0 A bitcserial identity comparator detects only whether the
0 x 0 1 0 two operands are equal or not. without determining which
0 0 x 1 0
x 0 0 0 1 one (if any) is larger. The bit stream can come in LSB or
0 x 0 0 1 MSB first. the flip-flop gets set for any difference between
0 0 x 0 1
x 1 1 1 1 A and B. and stays set until the end of the word. then gets
1 x 1 1 1 reset before the beginning of the next word. This "differ-
1 1 x 1 1
ence detector" can also be implemented as a latch and
C,=1 x x x 1 1
x 1 1 1 0
folded into the combinatorial logic.
1 x 1 1 0
1 1 x 1 0 Abit-serial magnitude comparator distinguishes between
x 1 1 0 1
A = B. A > B and A < B. It can operate LSB first or MSB first.
1 x 1 0 1
1 1 x 0 1 if the logic is adjusted:
Inputs LSB first: Start with both flip-flops reset
Outputs C. A, B, A, B,
if A > B set Ox. reset Oy
S._1 1 0 0 x x
0 1 () x x if A < B set Oy, reset Ox
0 0 1 x x
1 1 1 x x MSB first: Start with both flip-flops reset
S5=1 x 1 1 0 0
1 x 1 0 0 if A > Band Oy = 0: set Ox
1 1 x 0 0
x 0 0 1 0
if A < B and Ox = 0: set Oy
0 x () 1 0
Result in both cases:
0 0 x 1 0
x 0 0 () 1 Qx Qy
() x 0 0 1
0 () x () 1 o 0
x 1 1 1 1 o 1

•
1 x 1 1 1
1 1 x 1 1
1 0
x 1 Impossible
CG,=1 x x 1 1
x 1 1 1 0
x 1 1 () 1
CP,=1 x Q 1 1 0 A Ox
x 1 0 1 0
x 1 1 1 0
x 1 0 0 1 B

Inputs
Lower Higher Oy
Outputs C,. CP CG CP CG
Lower x x 1 x x
Carry 1 1 x x x Oy
Higher x x x x 1 1141 05 CLOCK _ _ _ _ _...1
Carry x 0 1 1 x
1 1 0 1 x Figure 5. Serial Magnitude Comparator

6-29
 Conditional Sum Adder
Adds 16 Bits in 33 ns

Application Brief BY MATI KLEIN, HEWLETI·PACKARD

This circuit is based on a 1960 paper by J. Sklansky (see subscripts denote the binary positiDn (weight), and super-
page 6-26). With careful placement and routing the total scripts describe the assumed input condition:
delay can be kept below 33 ns.
0: carrry into this position is assumed inactive
The block diagram below shows each CLB and its inputs "0: carry into the position one lower is assumed inactive
and outputs. 1 : carrry into this position is assumed inactive
"1: carry into the position one lower is assumed inactive
27 of the CLBs each generate one function of up to 5
variables, 14 of the CLBs each generate two functions of A complete LCA file is available from Xilinx Applications
four varibles. In accordance with the original paper all and will be published in XCELL.

r::l _ A2B:.
CoAoBo =t:r r+~~----------~==~------------------,

CoAoBoA'B,tt

A2B:.A, B3

A,.B,.A 15 B15

1988 01

16-Bit Conditional Sum Adder

6-30
 Building Latches
Out of Logic

Application Brief

Since the 3000-series, unlike the 2000-series, cannot Sand R (again 16 different flavors) or we use multiple S
configure its CLB flip-flops into latches, there must be and multiple R, either ORed, or ANDed, or XORed. We
other ways to design latches. Obviously, the I/O block can can also have two D inputs, each with its own Enable; or
be configured with latches on either the input, the output, we can have two D inputs, a Select input and an Enable
or both. Beyond that, every CLB can form a latch. input; orwe can have an Enable and three D inputs defined
in any arbitrary way. Majority gating could be one way: if
The five-input logic structure allows an amazing diversity none or one is active, reset the latch; if,two or three are
of latch designs: four examples are documented in the active, setthe latch. Or, if none is active, reset; if oneortwo
3000-series Macro Library on page 15 and 16. Here are are active, hold; if three are active: set. Orwe can assign
additional ideas: positive or negative weights to the D inputs.

With F fed back to close the feedback path, there are four Since there are 65,536 differentfunctions offourvariables,
control inputs left. We might call them Set, Reset, Data there are many different ways to define a latch, not
and Enable, defining them such that Sand R are independ- counting pin rotations and active High/active Low vari-
ent of E, but D is activated by E. We can still define any of ations.
these four inputs as active High or active Low. That gives
us 16 different latch designs, all with the same basic All these latches have the same timing characteristics:
characteristics and the same timing. propagation delay from input to output = 14/9 ns for the
50/70 MHz part. Set-up time to the end of Enable, or min.
We can also eliminate D and have two Enables, affecting Enable width = 19/14 ns assuming 5 ns interconnect delay.

D SET SET 1
EN.D EN.SET SET 2
SET RESET RES 1
RESET EN.RES. RES2

D1
EN.01
02
01
02
SEL.
01
D2
03
EN
II
EN.02 EN.

114201

Figure 1. Latched Logic

6-31
Additional Electrical Parameters

Synchronous Counters,
Fast and Compact

Application Brief

FULLY SYNCHRONOUS 4·BIT COUNTER USES FULLY SYNCHRONOUS 5·BIT COUNTER USES
ONLY TWO CLB'S TO COUNT ANY CODE ONLY THREE CLBS

This four-bit counter operates synchronously and has a Three 3000-series CLBs can implement a modified shift-
Count Enable(Clock Enable) input. Count length, count register counter with the following features:
direction, and even the code sequence can be selected
through configuration. There are 15!, i.e. more than 10,2 • Fully synchronous operation
different possible sequences. All four outputs are avail-
able. This counter cannot be preset to an arbitrary value, • Count Enable Asynchronous clear
but it can be cleared by an asynchronous input.
• Count-Modulus defined during configuration: 2 ... 32
ANY SEQUENCE: • Only one meaningful output, as, but with complete
BINARY freedom to define its waveform
GRAY
BCD 00 through 04 form a linear shift register counter. The 5
X3 input combinatorial function FO determines the modulus
X3·GRAY (there are no illegal or hang-up states). The 5-input
BIQUINARY combinatorial function Fl decodes the counter in any
ETC.
conceivable way, synchronizes and de-glitches Fl. as
114301 Examples:
Figure 1. Synchronous 4-Bit Counter in 2 CLBs
+ 28 counter with output High at times
T2, 3, Tl0, T22 through T27
The advantage of a Gray code is its glitch-less decoding,
since only one bit changes on any code transition. A Gray
+ 19 counter with output Low at times
counter can also be read "onethe-fly" without the well-
T9, T12, T15, T18.
known problems of reading a binary counter e.g., on its
transition between 7 and 8, where any code might be read.

1(·;·:···········
.......................................................;.:.;.:.:.:.:.:.:.:.: .......................................................................:.:.:.:.:.:.:::::.;.:.:.:...:.:...........
Decimal Binary Gray X3 Binary X3 Gray
0,
i
0 0000 0000 0011 0010 i 03
0,
1 0001 0001 0100 0110 ~~ 0,
2 0010 0011 0101 0111 00
3 0011 0010 0110 0101
4 0100 0110 0111 0100
5 0101 0111 1000 1100
6
7
8
0110
0111
1000
0101
0100
1100
1001
1010
1011
1101
1111
1110
~(}&--
°3
02
0,
F, Os ENCODED OUTPUT
(ANY PATIERN)

9 1001 1101 1100 1010 00

10 1010 1111 0 27
e.g .• ~
11 1011 1110
12 1100 1010
13 1101 1011 1144 01

14 1110 1001
15 1111 1000 Figure 2. Synchronous 5-Bit Counter in 3 CLBs

6-32
 30 MHz Binary Counter Uses
Less Than One CLB per Bit

Application Brief BY PETERALFKE

Borrowing the concept of Count Enable Trickle/Count The least significant tri-bit thus stops the remaining
Enable Parallel that was'pioneered in the popular 74160 counter chain for 7 out of 8 incoming clock pulses, allowing
TTL -MSI counter, a fast non-Ioadable synchronous binary ample time forlhe CEO-CET ripple-carry chain to stabilize.
counter of arbitrary length can be implemented efficiently Max cloCk rate is determined by the first tri-bit's Clock-to-
in the XC3000 series CLBs. For best partitioning into CEOdelay (TOKO +TllO), plu5the CEP input set-uptime
ClBs,the counter is segmented into a series of tri-bits. forall othertri-bits (TICK), pluS the routing delay ofthe CEP
net. In a-70 device this sum can be below 32 ns. The
The least significant (i.e. the faslest changing) tri-bithas a highertri-bits are not speed critical if they propagate the
Count Enable Output (CEO) thaJ is routed to all the Count CET signalin less than eight clock periods, easilyachiev-
Enable Parallel (CEP) inputs of the whole counter. able for counters as long as 20 tri-bits, i.e. 60 bits.

Each Count Enable Output from any other tri-bit drives the The two least significant .tri-bits each have a single Count
next more significant Count Enable Trickle (CET) input Enable input; they fit, therefore, in only two ClBs, each.
The clock causes any tri-bit to increment if all its Count The highertri-bits have two Count Enableinputs (CEP and
Enable inputs are active. CEO is active when all three bits CET) and require tHree ClBs.
are set AND CET isHigh. CEP does not affect CEO.

ETC

1980 01 30 MHz Non-LoadabJe Binary Counter, Expandable up to 60 Bits

~
•
O.
. ., '" 'D", . , ' °c
00 '

1980 02 First and SilcondTri-Bits Use Two CLBs Each

CET~
Q" ".
OB,' :
CEO

00

1980 03
All More Significant Trl-Blts Use Three elBs

6-33
 Up/Down Counter Uses
Less Than One CLB per Bit

Application Brief BY PETERALFKE

A fully synchronous resettable but non-Ioadable up/down chronous outputs; i.e., all flip-flops clock on the same
counter of arbitrary length can be implemented with only edge.
one XC2000 CLB per bit. This design cascades the toggle
information from the least significant toward the most The better functionality of the XC3000 CLBs can cut the
significant position. Such an architecture reduces the cascaded toggle control delay in half by looking at two
maximum clock rate for longer counters, from 30 MHz for counter bits in parallel. This doubles the max frequency for
2 bits, to 10 MHz: for 8 bits, down to 5 MHz for 16 bits, a given counter size. A 16-bit counter in a -70 part can
assuming a -70 part. This simple design is, therefore, not count 10 MHz, guaranteed worst case.
suited for high speed clocking, but it generates fully syn-

UP/DOWN "'\

I ,.........
Count Enable
IN
I
) >-n X
Count Enable
0 UT

I
1 1))- D Q
y

>
1981 01

CEO

eEl -t--t+---.---+-----t--+----'

1981 02

6-34
 Loadable Up/Down Counter
E:XllINX Uses One CLB per Bit

Application Brief BY PETERALFKE

The five-input function generator of the XC3000 family control circuit is moved to a separate CLB which serves
CLBs makes it possible to build expandable fUlly two counter bits simultaneously. This cuts the effective
synchronous /oadab/e up/down counters of arbitrary ripple delay in half. A 16-bit counter in a ~70 part can count
length using only two CLBs per two bits, Le. one CLB per 10 MHz, guaranteed worst case.
bit.
The CEP/CET speed enhancement cannot be used on up-
The basic concept is similar to the non-Ioadable up/down down counters that might reverse their direction of count in
counter described on the previous page. The function any position. They can, therefore, not guarantee a defined
generator driving the counter flip-flop has two additional number of clock periods for the ripple-carry chain to
inputs (Parallel Enable and Data). The cascaded toggle stabilize.

ca--~~============~-----'
u~~--~~~===r,
CEO

II
PE--~--~------------~----~
1982 01

6-35
 30 MHz Binary Counter with
I:XlllNX Synchronous Reset

Application Brief BYPETERALFKE

In many applications, design modularity is more important A shorter counter (6 bits or less) drives the CEP net from
than highest clock speed and best space efficiency. This the Qo output, achieving a 40 MHz speed. A longer
applications brief· describes a counter design that uses counter generates a 1-in-4 duty cycle on CEP and runs at
identical CLB primitives, one CLB per bit. The Count 30 MHz up to 12 bits long, or at 25 MHz up to 18 bits long
Enable Trickle/Count Enable Parallel concept, introduced as shown below. In order to achieve this performance,
by the 74160 family, is changed here to a one-bit block CEP and R must be driven by long lines.
size. Any block increments only if both Count Enables are
High, but the outgoing count enable (COUT) is not a
function of CEP. The CEP input thus prevents erroneous
counts while the ripple carry chain is settling.

ETC TO 017

RESET~·~~-----+++------~~------HH-------+~------~~
CLOCK--~------+-~----~~-------r~------+-~----~~

00 01
198301

CEP

R~~~.------------~
CLOCK-..::tr;----------------~-----I>

CLB PRIMITIVE, ONE PER BIT

o 198302

6-36
 Fast Bidirectional Counters
for Robotics

Application Brief BY PETERALFKE

The position of a robotics arm is usually determined by Communication between these two parts of the counter is
three shaft encoders consisting of up/down pulse genera- through a carefully controlled mailbox. Whenever the 4,bit
tors and counters. Ata maximum speed of 5 meters per up/down counter reaches plus or minus 8, it sets a carry or
second and a resolution of 1 micron, these counters must a borrow flip-flop. The shift register counter accepts these
resolve 0.21-1S pulses and should have a capacity of at least inputs synchronously, with a max delay of 1 microsecond.
2 million steps. The counters must have an easy interface
When the microprocessor wants to read the counter, it first
to the microprocessor so that the count value can be read
disables the interaction between the two parts of the
on-the-fly, without ambiguity.
counter. Then both parts are transferred into 240I,Jtput
The established microprocessor peripheral counters have registers and the counter interaction is enabled again.
severe limitations. They are too short, lack up/down con- This mechanism insures reliable read-out, even if the
trol or quadrature clock inputs, and cannot be read easily. counter is oscillating around certain critical values.
Now Xilinx suggests a design that packs three 22-bit The problem of a traditional up/down counter is that it can
counters into one Logic Cell Array, the XC3020. Max count oscillate between two values where all (or most) counter
rate is 8 MHz, and Ihecount values can easily be read on- bits change at the incoming count rate. This makes a reli-
the-fly. The counter architecture is somewhat unconven- able microprocessor interface virtually impossible.
tionaLEach counter consists of two parts:
In this design the most significant 20 bits otthe counter do
1; A conventional up/down 4-bit Grey-code counter with a not have this problem, and the least significant 4 bits count
cilpacity from -8.to +7. Thiscounter is asynchronous to in a Grey code, where only one bit changes on any clock
the system clock, affected only by the incoming clocks. transition. Such counters can safety be read on-the-fly.
This safe and compact design puts one additional burden
2. A 20-bit up/down counter in the form of a 20-bit recircu-
on the microprocessor: The two parts of thecountermust
lating shift register, a serial adder/subtractor, and a
be added in software, since they have independent signs.
carry/borrow flip"flop. This shift register forms the most
Significant part of the counter. Synchronous with the Speed can be increased to 20 MHz by changing the parti-
LCA clock, itis easily synchronized to the microproces- tioning from 4/20 bits to 8/16 bits. The up/down count
sor clock. At a 20 MHz clock rate it recirculates once, control can be implemented in several different ways.
and can be incremented, decremented, and also read
or preset, once per microsecond.

CLOCKS

Handshake

1984 01
Figure 1. Triple 22-.8it Up/Down Counter with Microprocessor Interface

6-37
l:xuxxx 40 MHz Presettable Counter

Application Brief BYPETERALFKEANDPERRYWU

This application note describes a new counter architecture Carry Propagation:

used to implement a very high speed presettable. up to
40- bit long binary counter in an XC3020 Programmable • Since a presettable counter only decodes one state, TC,
Gate Array. The design can easily be modified to imple- the decision to toggle any of the more significant bits can
ment two 20-bit counters, orthe equivalent BCD counters. be delayed and thus pipe lined without any problem.

Traditional counter designs always represent a comJ?ro- The counter is divided into a number of small sections,
mise between two conflicting goals: highest clock speed/ each two bits (a dibit) long, implemented as a synchronou s
event resolution on one hand, sophisticated features (like presettable down-counter, with carry-in (=count enable),
preset to any arbitrary value, or decode any state) on the parallel enable and two data inputs. Terminal count (0.0)
other hand. is decoded with an additional input coming from the next
higher section. The least significant section decodes the
Asynchronous ripple counters offer highest speed, but state prior to TC, its output activates the parallel enable for
cannot be decoded in one clock period, thus cannot be all counters. The carry function between sections is
made programmable. pipelined. The carry flip-flop is set when carry-in is active
and the dibit is in state 00. The carry flip-flop stays set for
Synchronous counters allow decoding and presetting in only one clock period, its output drives the carry-in function
one clock period, but pay for this with complex carry logiC. of the next higher section. As a result of this pipe lining, the
Carry propagation is always the limiting factor in the counter can be made arbitrarily long, without any speed
traditional design of presettable synchronous counters, penalty. Note that each dibit, except the first, makes its
since the complete carry chain must reach a steady state transition n clock pulses later than required by the binary
before the next incoming clock edge. Brute force parallel code sequence (n is the relative position of the dibit, n=O
decoding of all previous states becomes unmanageable forthe input dibit). This code violation has no impact on TC
beyond 8 stages, but cascaded decoding introduces decoding. This counter can be four times faster than
additional delays. Either approach reduces the inherent presently available standard microprocessor peripherals
resolution of the counter. like the 8254 and 9513. Typical applications are in
instrumentation and communications, e.g., as the fre-
Decoding Terminal Count (TC) in order to preset the quency determining counter in a phase-locked-loop fre-
counter again, poses a similar problem. The design quency synthesizer.
described in this paper separates the two functions of the
carry chain into: Different from conventional synchronous counters, the
speed ofthis design is independent of its length. All speed-
• One which decodes the terminal count of the whole
critical paths are single-level, their interconnect delay can
counter and generates a Parallel Enable signal
be kept below 9ns, which means that a -70 device can
• One which propagates the carry signal from the less
count at a 40 MHz rate (worst case).
significant to the more significant bit positions, and
causes the appropriate flip-flop to toggle.
MSB + - LSB
Cascaded TC Decoding:
n=2 n=l n=O
1 1
• The TC decoder must receive inputs from all counter 010
bits, but only the LSB timing is critical, the more signifi- o 0 1
o 0 0
cant bits have been stable before. TC can, therefore, be o 1 1
010
decoded in a slow gating chain that starts at the most

1~Wf1
significant end of the counter.

il
c~~ ; ( ~
PE
1145 02 - - CARRIES
40 BITS TC
1145 01

6-38
 ......................} ................. ................................................;:..•.
CI-"-~----+--~----;~

PE----.---'

Do------L..I
bJU
PE

D1
1.1;;

.............................
:;
i
o co

TO-------------------------~;----------'

CI ~ Carry In
CO ~ Carry Out
PI':
~ Parallel Enable (Active Low)
TI ~ Terminal Count In
TO ~ Terminal Count Out
'-----TI
::..... ..............)
Any Dibit Except the Least Significant 1145 04

.... ~." ....................,.,.........................1'

a
CARRY

DO RD

....•.•.•.......•;; . . . . . . . . . . . . . . .J
fiE TO ALL 0lBIT8

TI

a
CE ~ Clock Enable TERM.
COUNT

RD
PRESET----------------------------------------------;~--------------------~~----J

Least Significant Dibit 114505

PRESET

START/STOP
HIGH

Least Significant Dibit Most Significant Dibit

Synchronous Presettable Counter--40 Bits in 60 CLBs 114503

6-39
40 MHz Counter

Since this circuit was first published in mid 1988, several In the unlikely case where this might cause a problem,
designers have used it to create fast counters. most TC pipeline flip-flops can be eliminated. They were
inserted to simplify modeling and because they are
There have also been many questions about the rather available for free.
terse description and about an error in the schematic
drawing (the AND gate generating PEl that has been cor- Why Is the least significant dibit different?
rected in this printing.
In orderto achieve a40 MHz clock rate, the PE Signal must
What Is the function of the TC pipeline flip-flop, be made as fast as possible. It has to come directly from
formerly called Q3? a flip-flop output so that the sum of clock-to-output delay,
routing delay, and input set-up time is kept below 25 ns.
The unconventional idea behind this counter design is that
Terminal Cou nt decoding can be "rippled" from the MSB to The position of the LSB TC pipeline flip-flop is, therefore,
the LSB, i.e. against the direction of carries. This is changed, so that it detects the TC-1 state (in a down-
possible because the high order bits reached theirTC long counter, that is state 1).
before the LSB does.
The flip-flop output is made active Low PE so that the
There is, however, a potential problem when the counter asynchronous clear input can be used to force the counter
is being preset to a value with a string of LSB zeros. Let's into loading.
assume the worst case where the preset value is all Zeros
except a single One in the MSB position: For operation below 30 MHz the least significant dibit can
be like all the other dibits, but PE must be excluded from
When this counter reaches the all-zero Terminal Count, the AND gate generating PE, and the user may want to
PE is activated and the counter is preset. This action adjust the polarity of the last TC pipeline flip-flop to
should obviously de-activate the TC decoding, but in the facilitate the preset function mentioned above.
given example a simple ripple decoder would have a very
long delay. It might take 400 ns for the MSB= 1 condition Where should this design be used?
to ripple down through a 40 bit decoding chain. Such a
delay would defeat the concept of the counter, reducing its This counter design achieves high performance by using
max clock rate to 2.5 MHz. A better way must be found to several logic ''tricks''. It generates incorrect outputs when
de-activate TC within 25 ns. undigested carries sit in the carry flip-flops. That makes
this design useless for any parallel application like DMA
The TC pipeline flip-flop and the inclusion of PE in the AND counters.
gate that detects TC, reliably de-activate TC and thus PE
one clock after they have been activated. This has one For the intended application, timebase counters or
side effect, however: It makes it illegal to presetthe counter frequency synthesizers, this design offers the highest
to very small numbers (less than 10 for a 20-bit counter), possible count speed.
since the TC-pipeline takes that many clock pulses to
become active again.

Asynchronous Preset in XC3000 CLBs

The XC3000 CLB lacks the asynchronous preset capabil- 3. If the circuit really needs asynchronous preset and
ity available in the XC2000 CLB. Some designers are look- clear(or asynchronous data transfer) in a flip-flop, the
ing for this feature. Here are several solutions: problem must be solved on a system level:
1. If asynchronous preset is needed, but no asynchro- The design can usually be transformed into a synchro-
nous clear: nous solution where all flip-flop changes occur as a result
of the same clock edge.
Turn the flip-flop upside down, i.e. invert the D input
and the Q output and considerthe asynchronous clear Truly asynchronous parallel data transfer into several
a preset. These inversions of D and Q come for free clocked flip-flOps is inherently unreliable and must be
in a Xilinx LCA. Note, however, that the flip-flop will avoided. If, however, the transfer pulse is synchronized
now come alive in the apparent preset state. with the clock, it should not be too difficult to change the
design to utilize the clock for loading.
2. If the circuit needs both asynchronous preset and
clear, chances are that the function can be performed Asynchronous data transfer was popular in early TTL MSI
by a latch. The XC3000 CLB can implement complex Circuits deSigned in the late sixties, e.g., the 7494 and
latches in its fu nction generators (see page 6-31). 7496. It is time to getaway from the limitations of the past.

6-40
 Frequency/Phase
Comparator for
Phase-Locked-Loops

Application Brief BY PETERALFKE

A Phase-Locked-Loop (PLL) manipulates a local voltage- only to pull in a small phase error, but also to correct a large
controlled oscillator (veO) so that it is in phase with a ref- frequency error. It may not generate false outputs when
erence signal. One popular application is a programmable the input is at a multiple or fraction of the desired fre-
frequency synthesizer for radio communications. Here a quency.
crystal oscillator is divided down to a low reference fre-
quency of 5 kHz, for example. The well-known circuit shown in Figure 1 performs this
function. It generates "pump-up" pulse when the veo
A programmable divider scales the veo frequency down frequency is too low, "pump-down" when its too high. The
to the same reference frequency. The two counter outputs multiple feedback network assures proper operation even
are compared to generate a signal that, when required, at large frequency errors.
modifies the veo frequency up or down until the two com-
parator inputs are not only of the same frequency, but also Figure 2 shows this circuit implemented in two eLBs plus
in phase. two lOBs, directly driving the integrator (low pass filter)
controlling the veo. The LeA solution has been
This frequency/phase comparator must have a wide cap- breadboarded at 10 MHz. It achieved a phase error of less
ture range, i.e. it must generate the appropriate output not than 2 ns.

............................................................"'::

FROM

DIVI~~g+---++-_....J
BYN

t.. . ,. .~.~.~. ~. :-. ,. .:-:. . .,. . . .:. . . . .:-. . . . :.:-. . . :-. . . . . . . . . . . . . . . . . . . ". . . . . . . . . . . . .J

III
FROM
REFERENCE +--++-_....J
FREQUENCY

198501

Figure 1. Digital Frequency/Phase Detector

ToveD

+2.5 V

1985 02 INTEGRATOR

Figure 2. Frequency/Phase Detector Using Four Blocks

6-41
 Gigahertz
Presettable Counter

Application Brief BY PETERALFKE

Some frequency synthesizers for communications, e.g., a smart but slow counter (in the LCA) to achieve the
cellular telephone networks, require a clock frequency of performance of a fast and smart, fully presettable counter.
hundreds of megahertz, up to a gigahertz. Obviously, the
LCA cannot operate quite that fast, but with the help of a The prescaler divides by either n or n + 1, depending on
2-modulus prescaler, the LCA can implement a fully pre- the state of the control input. In other words, it "swallows"
settable ultra-fast counter, resolving time in increments of one additional clock pulse if told so by the control input. By
one clock period, as small as 1 ns at 1 GHz. keeping the control input active forthe appropriate number
of prescaler output periods, the LCA can fine tune the total
Prescaling is the obvious method to adapt a slow device to divide ratio to any integer number.
a high clock rate. Simple prescaling by a fixed number,
e.g. 8, 16, or 64, however, reduces not only the clock rate, Well, there are some impossible numbers:
but also the resolution. If, for example, the GHz clock of a When the prescaler divides by either n or n + 1, then the
phase-locked-loop synthesizer is first divided by 64, then system cannot divide by certain numbers below n (n-1).
the whole presettable counter is clocked at this lower rate.
For a 25 kHz channel spacing, the PLL must, therefore, An 8/9 prescaler has blind spots below 56
operate at 25 kHz + 64, i.e. less than 400 Hz. This results A 64/65 prescaler has blind spots below 4,032
in slow response and might produce excessive phase A 128/129 prescaler has blind spots below 16,256
jitter.
This limitation is usually of no practical consequence in a
A "Pulse Swallowing" 2-modulus prescaler, originally real design:
described in 1970 by John Nichols of Fairchild Semicon-
ductor Applications, avoids this drawback. Pulse swallow- The prescaler-LCA combination can divide by any integer
ing combines a fast but dumb counter (the prescaler) with number higher than the values above.

INPUT
200 MHz OUTPUT
0.280 ~s
0.285 ~s
0.290 ~s
Example 1:
200 MHz clock, 12-bit
20.475 ~s
presettable time base generator 20.480 ~s
achieves 5 ns output resolution.

INPUT
450 TO OUTPUT
1000 MHz TO 25 kHz
PHASE-LOCKED-
LOOP
Example 2:
450 to 1000 MHz clock, 16-bit
presettable counter achieves
25 kHz channel spacing with a
25 kHz phase comparator frequency.

6-42
 E:XIUNX

o ori------------------TC=PE
CP

06 °7

Os
°4 00

°6
03
°2
°1
00
CLBM7
°4
03
°2
°1
°0 Os

°2

°0
°1 °4
1988 01

00
°1 TO
°2

03

TC
00 01
PE+----~ ...
Dl~------_L__J

°1

1988.02 PE

3-Bit Presettable Down Counter with 9-Bit Presettable Down Counter with
Pipelined Terminal Count, Locking Up on TC Decoded Terminal Count (Te)

6-43
 100 MHz Frequency Counter

Application Brief BY PETERALFKE

The block diagram below describes a complete 100 MHz nously, each decade consisting of a synchronous BCD
frequency counter in an XC3020. counter.

A 32,768 kHz crystal oscillator generates a time base of The high resolution of 100 MHz or 10ns is achieved by
two seconds. The frequency to be measured clocks an 8- using the divide-by-two flip flop driven by the alternate
digit BCD counter. At the end of the measuring period of clock buffer. This is the simplest and therefore fastest flip-
two seconds the counter content is transferred into four flop on the device.
shift registers, and the counter is then reset before the
beginning of the next measuring period. The shift register The whole frequency counter uses 51 of the 64 CLBs in an
drives a multiplexed 8-digit, 7 segment LED or LCD XC3020:
display.

The oscillator uses three lOBs, since the dedicated crystal Time Base 8 CLBs
oscillator input is already used as signal input. BCD Counter 16 CLBs
5 Shift Registers 20 CLBs
The time base is already generated by a.16 bit binary 7-Segment Encoder 4 CLBs
counter consisting of four asynchronously c~scaded 2-bit Leading Zero Suppressor 1 CLB
synchronous counters. The control unit eliminates the Control 2CLBs
clock ripple delay by re-synchronizing the time base out-
put. The eight counter decades are cascaded asynchro-

XC3020
r--r+-r--,
fin LSD
(0 ...1ooMHz)
i..
'61
a:
-=:E
IIII I
50 MHz
a-Digit en
BCD
Counter .
..,
CD

I:
....
aI
a-Digit
MSD co
LED

Matrix
I!!
!
~I: Leading
aI"
.!!O Zero
0 Suppress
..,t
0
4 U
I:
W

.
C
E
en2'
,:.

1129 01

Figure 1. Block Diagram

6-44
 &XILINX

l:XllINX Serial Pattern Detectors

Application Brief BY PETERALFKE

FIXED PATTERN DETECTOR ously shifted-in pattern, using only one XC3000-series-
CLB per pattern bit. The output of the comparators are
This circuit compares a serial bit-stream against a prede- ANDed with 3-state buffers on a long line. The desired
termined (configured) pattern. Two bits are compared in pattern is first shifted through the DIN input into the Y-flip-
each XC3000-series CLB. The outputs of the comparator flop, and then routed to the DIN input of the next CLB.
are ANDed in with 3-state buffers on a long line.
When the complete pattern has been shifted in, it is trans-
Data is shifted through DIN into the Y-flip-flop, then shifted ferred with one clock pulse to the X-flip-flops, using the
through the upper half of the combinatorial array into the lower half of the function generator. Data to be detected is
X-flip-flop of the same CLB. From there it is routed to the then shifted inthrough the DIN input intotheY-flip-flop, and
DIN input of the next CLB. from there to the DIN input of the next CLB. The upper half
of the function generator compares the content of Ox and
The lower half of the combinatorial array compares the
content of the two flip-flops against data supplied on the A Oy, and indicates a match on the CLB output. For identity
and D inputs. A match is indicated on the G output and comparison, these outputs are ANDed through 3-state
buffers driving a long line.
routed to a 3-state buffer driving a long line.

DYNAMIC PATTERN DETECTOR OR CORRELATOR This circuit can also be used as acorrelator, inwhich case
the outputs must be summed in a Wallace-type adder.
This circuit compares a serial bit stream against a previ-

LONG
~-...,. LINE

•
LONG
LINE

DIN
DIN

114701 114702

Figure 1. Fixed Pattern Detector Figure 2. Serial Comparator Finds Pattern Match or
Correlates Patterns

6-45
Incorporating PLD Equations Into LCAs

Serial Code Conversion

Binary to BCD

Application Brief BY PETERALFKE

CONVERTJSHIFT

1146 03
Figure 1. Binary to BCD (MSB First)

The LCA architecture with its powerful function generators

evenly interspersed between flip-flops lends itself very
well to serial code conversion, where data is shifted into a
MODIFY
register in one format, and shifted out of the same register
in a converted format.

A binary to BCD converter requires 3 CLBs for every 4 bits

of BCD output (i.e., for every digit). Data is shifted in
serially, most significant bit first. Each shift thus doubles
f----~D °3
the content of the register.

In order to stay a valid BCD number, a 4-bit number of 5 or

greater must not just be shifted, but must be converted into
the proper BCD representation of its doubled value: A·
"one" is shifted into the next higher decade and the 5 is
converted into a 0, a 6 into a 2, a 7 into a 4, an 8 into a 6,
a 9 into an 8. When the binary LSB has been shifted in,
BCD data is available in parallel form, ·or it can be shifted
out serially with the conversion logic disabled.

MODIFY: 5~OJ 6'-'2, 7-+4, 8-+6,9 ...... 8

SHIFT MODIFY
0 2 - 0 3 - 0 0 · 'lI
°1-02-~ XNOR a..
° 0 _ 0 , _ °0
03----+°34---- 03

114601b

114601a

Figure 2. Binary to BCD converter 3 CLB's per 4 Bits:

MSB First

6-46
 Serial Code Conversion
BCD to Binary

Application Brief BY PETERALFKE

CONVERT/SHIFT

o·
o

114604
Figure 1. BCD to Binary (LSB First)

The LCA architecture with its powerful function generators ......... J

evenly interspersed between flip-flops lends itself very

~U
well to serial code conversion, where data is shifted into a .---
register in one format, and shifted out of the same register
in a converted format.

A BCD-to-binaryconverter requires 3 CLBs per digit. BCD

data is shifted in, least significant bit first. Once the
r-- .---
-

complete BCD word has been shifted in, the conversion

CONVERT
process begins, shifting out binary data, LSB first. MODIFY

Each shift divides the content by two. When the LSB of a

BCD digit is a "one", shifting it one position down would --~
give it a weight of 8 in the lower decade instead of the
weight of 5 appropriate for a 10 divided by 2. A value of 3
.--- ,..--

is therefore subtracted from the content of the decade °1-<1 D °11---

whenever a "one" is being shifted into it.

This design can be made smaller and faster by starting the r-- --
~U
conversion before the most significant BCD digit is being -
shifted in. Since these converters can be laid out with very
°1-<1
short interconnect delays, they can operate at up to 60%

•
°2-<1
of the specified toggle frequency, i.e. 42 MHz for the -70
parts.
r-t
- --
MODIFY: 0 -to- 5, 2-+ 6, 4-+ 7,6 ...... 8, 8 -+ 9 ~
-
~J
D 0,
°2-<1
SHIFT MOOIFY
° 1 -0 0 - c : l ' 1 '---
02 - 0 1 - 01 XOR 02
0 3 -0 2 - c : l ' 3 AND (c:l'10R c:l'2)

1146 02b
0'0 - 0 3 - 03 OR (01 • 02)

-:J
114602a -
Figure 2. BCD to Binary converter 3 CLB's per 4 Bits:
LSB First

6-47
Incorporating PLD Equations Into LeAs

"Corner Bender" or
a-Bit Format Converter

Application Brief BY PETERALFKE

Pulse Code Modulation (PCM) has become the dominat-

ing encoding method in digital telephony. Analog signals
are sampled at 8 kHz and represented by their 8-bit digital
equivalent, using a logarithmic encoding scheme, Il-Iaw in
the US and Japan, A-Law in the rest of the world using the XC2064
OR 8
CCITT standard. 1/2 XC3020

These eight bits are usually transmitted serially (the T1

standard time-multiplexes 24 channels on a single wire at
1.544 MHz. The CCITT standard time-multiplexes 32
channels at 2.048 MHz.
1122 03
In the central office or PBX, however, the eight bits
OUT
representing one particular sample must be routed
together. The telephone system thus uses a large number
of serial-to-parallel and parallel-to-serial converters, all I0
operating on 8-bit words, all running synchronously. Eight CORNER

Sop converters with 8 data inputs and 8 data outputs can I0 BENDER

easily be combined in one package. Eight serial data I0

streams are shifted in simultaneously. After eight clock
pulses the eight serial words can be shifted out in parallel,
one word per clock pulse, and newserial bits can be shifted
I0
I0
I0
J}
shifted in simultaneously. It is interesting to note that the
same circuit can also accept parallel words and shift them I0
out in eight serial streams. The difference between Sop I0
and P-S is not in the circuit, but in the mind ofthe beholder.

Such a "Corner Bender" is available as a standard part, the 1 71 1 10 1

Plessey MJ 1410 8-Bit Format Converter. Its drawbacks 1 71 1 10 1
are high power consumption (max 500 mW) and slow I 71 1 10 1
speed (2.4 MHz guaranteed worst case), a result of its
71 1 101
nMOS heritage.
71 1 10 1
This design can be simplified and made to fit into an 71 1 101
XC2064 or half an XC3020. 71 I I01
71 I I01
112201 ~
OUT

6-48
"Corner Bender" or S-Bit Format Converter

The LCA implementation of a 2-dimensional shift register I I

is straight forward: -- ---- I I
I I
-- ---- I I
A common clock drives all flip-flops, organized in an -- ---- I I
I I
8x8 array. In mode A each flip-flop receives data from its -- ---- I I
"left" neighbor, in mode B each flip-flop receives data from -- - --- I I
its neighbor above. -- - --- I I
I I
- - ---- I I
For the first eight clock pulses the array is in mode A, I I
receiving 8 bit streams and right-shifting them into the
array. Forthe next eight clock pulses, the array is in mode PHASE A
B, down-shifting the previously received 64 bits.

New serial data can be shifted in from one side while old
parallel data is being shifted out at the opposite side.
There is no need for any ofthe additionalflip-flops required
by the older designs.

After eight clock pulses the mode control is again changed

to A and old data is shifted out on the right side while new
data is shifted in from the left.

This design uses only 64 flip-flops, and a mode control

Signal derived from a divide-by-8 counter.

The physical routing of the input signals can be done on- PHASE B
112202
chip, but the eight bottom output pins must externally be
wire-ored with the eight right-hand outputs.

The design fits exactly into one XC2064 or into half of an

XC3020 and can run at up to 35 MHz.

6-49
Incorporating PLD Equations Into LCAs

Megabit FIFO in Two Chips:

I:XUXNX One LCA and One DRAM

Application Brief BYPETERALFKE

A bit serial FIFO buffer is a general-purpose tool to relieve This FIFO DRAM controller consists of:
system bottlenecks, e.g., in LANs, in communications, and
in the interface between computers and peripherals. • An input/output buffer with synchronizing logic
Small FIFOs are usually designed as asynchronous shift
registers, but a larger FIFO with more than 256 locations • A 20-bit write pointer (counter)
is better implemented as a controller plus a two-port RAM, • A 20-bit read pointer (counter)
or as a controller plus a single port RAM, either SRAM or
DRAM. • A 20-bit fulVempty comparator
SRAMs are fast and easy to use, but at least four times • A 10-bit refresh counter
more expensive than DRAMs of equivalent size. Dynamic
RAMs offer low cost data storage, but require complex • A 5-to-1, 10-bit address multiplexer
timing and address multiplexing, which makes them unat-
• Control and arbitration logic
tractive in small designs. For FIFOs with more than 256K
bit capacity, a DRAM offers the lowest cost solution, if the The write pointer defines the memory location where the
controller can be implemented in a compact and cost- incoming data is being written, the read pointer defines the
effective way. A Xilinx XC3020 Logic Cell Array can easily memory location where the next data can be read. The
perform all the control and addressing functions with many identity comparator Signals when the FIFO is getting full or
gates left over for additional features. empty.

DIN
CLK
CLK I---------------D
DOUT

READY

CONTROL
10 DRAM
BUSY MUX A

3 RAS
~-------_,~----~CAS
WE
1130 01
Figure 1. Megabit FIFO Controller In an XC3020

6-50
Megabit Serial FIFO in Two Chips

When write and read pointer become identical as a result

of a write operation, then the FIFO is full, and further write
)D--i SHiFT-REGiSTER-COUNTER

operation must be prevented until data has been read out.

When the two pointers become identical as a result of a = +-1 COMPARATOR
read operation, then the FIFO is empty and further read
operation must be prevented until new data has been
written in. With a single-port RAM, read and write opera-
tions must be inherently sequential, and there is no danger
of confusing the full and empty state, a problem that has 113002
plagued some two-port designs.
Figure 2. Shift-Register-Counter and Free Row-Column
A straightforward design would use synchronous binary MUX
counters for the two pointers, but it is far more efficient to
use linear shift register counters. Such counters require register counter is pseudo-random anyhow, this is no
far less logic and are faster since they avoid the carry problem. It's an elegant and efficient trick).
propagation problems of binary counters. LSR counters
have two peculiarities: they count in a pseudo-random Both 20-bit pointers,plus their 20-bit identity comparator,
sequence and they usually skip one state, I.e., a 20-bit LSR plus the Row/Column multiplexer thus fit into only 20
counter repeats after 220_1 clock pulses. In a FIFO CLBs; refresh timer and refresh address counter and
Controller, both these features are irrelevant, the address multiplexer use another 15 CLBs and the data buffer plus
sequence is arbitrary, provided both counter sequence control and arbitration logic might take another 15 CLBs,
identically. The loss of one memory location is more than for a total of 50 CLBs, an easy fit in an XC3020.
compensated by the two bits (one incoming, one outgoing)
stored in the controller. This design can easily be modified for 256K DRAMs.
Other variations are: multiple parallel bits, e;g., byte-
This design fits two shift register counter bits in one parallel operation, or byte parallel storage with bit-serial
3000-series CLB, the identity comparator uses the combi- I/O. The latter case requires special attention when the
natorial portion of the same CLB. FIFO is emptied after a non-integer number of bytes had
been entered, requiring direct communication between
The RAS/CAS multiplexing of the 20-bit address is per- the input Serial-to-Parallel converter and the output PIS
formed without any logic by tapping every other bit of the converter.
shift register counter and using the 10 outputs before the
incrementing shift as Row address, after the incrementing This applications brief shows that the XC3020 can be
shift as Column address. (The Column address of any programmed to control one or a few DRAMs as a large
position is thus identical with the Row address of the FIFO of up to a Megabyte, with data rates up to 16 Mbps
following position, but since the binary sequence of a shift serially or 2 Megabytes per second byte-parallel.

,-- D or-- ,-- D or--

DIN DiN

READ
ADDRESS

r--l D or-- D 0 WRITE

F ADDRESS

U
COMPARE

~D o~
~
L J -D o....J
TWO
ADDRESS
BITS
COMPo
f-----

DIN DIN

READ ADDRESS WRiTE ADDRESS

113003
Figure 3. 2-Bit Slice of Two Counters and Comparator in Two ClBs

6-51
 State Machines

Application Brief BYPETERALFKE

State machine design is a methodology that defines the SIMPLE STATE MACHINE RUNS AT 30 MHz
contents of all flip-flops for any possible state of the design.
then defines all possible paths that can cause the design This simple state machine uses only eleven CLBs. It has
to go from one state to another. In its simplest form this is up to 16 states. and eight outputs. each decoding/encod-
just a rigorous way of designing synchronous logic. like 4- ing any combination of states. It performs a 2-way branch
bit counters. For complex designs. the state machine ap- from any state to anyone of two freely assigned states.
proach gives the designer a tool to investigate all possible (possibly including the present state) determined by con-
operating conditions and avoid overlooked hang-up states trol input C. (Avoid the branch by making both destination
or undesired transitions. Xilinx LCAs with their abundance states equal). .
of flip-flops lend themselves wellto state machine designs.
This design can also perform an 8-way branch from any
state so programmed to either one of two selected quad-
SIMPLE, FAST STATE MACHINES rants (0 .. 3. 4 ... 7. 8... 11 or 12 ... 15). Control inputs A.B then
determine the location within the quad~ant.
Using the 5-input function generator of the XC3000-70
family devices as a 32 bit ROM. a state machine with up to Examples:
32 states without any conditional jumps uses only 5 CLBs
and operates at up to 50 MHz. • From state@. if C=High. go to ® else go to ®
• From state rJ). if C=High. go to @else stay in rJ)
The 5 registered CLB outputs drive the 5 function genera- • From state ®. unconditionally go to ®
tor inputs of the 5 CLBs in parallel. This implements a fully • From state ®. execute the truth-table below
programmable sequencer similar to the synchronous
counter shown in the left column of page 6-23. AS C=Low C=High
For a smaller number of states. some inputs can be used 00 @
as conditional jump inputs. Encoding these condition 10 @
codes may require an additional level of logic which 01 @
reduces the maximum clock rate to 30 MHz.
11 @

ACTIVE 4·WAY BRANCH

A
B 6CLBs 4CLBs
WITH WITH 8
C-=~~~~~~~~ COMMON COMMON
INPUTS INPUTS

198601

30 MHz State Machine, 16 States, 2-Way/B-Way Branch, B Outputs

6-52
 Complex State Machine
in One LCA

Application Brief BY PETERALFKE

Simple and fast state machines can easily be implemented EPROM address bits. For reliable operation with asyn-
in a Xilinx LCA. as shown on the previous page. This page chronous control inputs, they must be synchronized in an
shows how an external EPROM can be the source of the input register.
next address in a complex state machine. This look-up
table can easily be hidden in the EPROM required to store This rudimentary state machine can thus· have 240
the LCA configuration data. different states, and can jump from any state to anyone of
128 arbitrarily defined hext states, controlled by the 7 bit
Assume that an XC3020 is configured in Master Parallel condition code.
Mode, where it reads its configuration data out of a 256K
(32K x 8) EPROM, starting at the top address location
This basic design uses no CLBsin the LCA, just lOBs, but
7FFF (32K) through 77FF (about 30K). The remaining
it allows a number of states and. a multi-way branch
94% of the EPROM can be used as next-state lookcup
complexity far in excess of any normal need. For most
table with a capacity of 240 states.
states, almost all of the 128 possible next states will be
programmed to be identical.
The state address isreiid out ofthe EPROM, then manipu-
lated (decoded, encoded, etc.) in the XC3020 LCA. The
result is combined with incoming control information to The user has the logic resources of the LCA available to
generate a new EPROM address. The EPROM can be add features like:
considered as having 240 locations, each 128 bytes wide.
Each byte is a potential next state value, only one of which • State decoding/encoding
will be chosen bY the 7 bit condition code. • Stack registers
• Loop counters
In the simplest case, the EPROM output d~ta is just • More sophisticated branch logic, etc.
latched in the LCA and is fed back as the most significant
part of the new EPROM address. Since the top 16 address This design is straightforward, inexpensive, compact and
locations are used for configuration data,the state codes very flexible. Its speed is limited by the EPROM access
are limited to 240 different values, .0 ... 239. time which can be as low as 100ns. For higher speed- at
a higher cost- the EPROM can be shadowed by fast
The seven control inputsform the seven least significant SRAMS.

27C256
EPROM

ADORES ~-';;;--"-----1
\.r---'---'!!'ic-'-----I G
LCA

R
STATE
OUTPUTS

E .,,/'-,...- CONDITION
CODES
•
198701

6-53
Incorporating PLD Equations into LCAs

Programmable Gate Arrays

£XILINX and Self-Diagnosing
Hardware

Application Brief BY RICHARD B. RAVEL

SELF-DIAGNOSING HARDWARE DIAGNOSTIC HARDWARE

Most designers would agree that it is desirable to incorpo- The circuitrywhich is most easily diagnosable is that which
rate self-diagnostics into their circuit boards, and they is immediately accessible by the microprocessor. In many
would do it more often if the cost of additional components cases, however, some of this circuitry cannot be tested
and board space were acceptable. It is obviously best to directly due to the specific design. Testing this logic, as
consider diagnostics at the beginning of a project so that well as other unrelated circuitry, requires additional logic
the board is designed with testability in mind. This not only on the board specifically for the purpose of diagnostics.
makes a board more manufacturable, but it makes it easier This is typically noldone because of board space and cost
to find failures in the end-user environment. considerations.

Programmable Gate Arrays are used in many different The logic which typically surrounds a microprocessor is
applications, and have the unique capability of having their the I/O control, memory control, bus control, and interrupt
specific functions defined by the systems in which they control logic. The peripheral control logic is the most
reside. Xilinx Logic Cell Arrays (LCAs) can also be re- difficult to diagnose using the microprocessor. I/O control
programmed, in-system, as many times as necessary. functions are usually implemented with dedicated periph-
This ability to dynamically re-configure the logic of the LCA eral controller chips, since they are cost effective and
makes board-level self-diagnostics a practical goal. An readily available. If they do not give the designer enough
LCA can perform diagnostic functions at power-up or in flexibility to perform all of the required functions, logiC is
test modes, and perform normal functions when the board added to the board. Some peripheral controller chips allow
is determined to be operational. (See the application note the designer to include diagnostic readback firmware.
on "Configuring Xilinx Logic Cell Arrays" in the Program- This firmware, however, would usually not include access
mable Gate Array User's Guide.) This approach to diag- to the supplemental circuitry which might be required.
nostics based on reprogrammable gate arrays adds no Even when this readback capability is available, its scope
additional cost to the circuit board. is limited.

This concept is really not new. Board-level self-diagnos- Peripheral control logic is usually diagnosable by writing
tics became popular with the advent of microprocessors. speCial programs for the microprocessor, and adding
A special diagnostic program written for the microproces- special circuitry that the microprocessor can access
sor and stored in its normal EPROM could be invoked at specifically for this purpose. Adding special logic for this
power-up, by the press of a button, or by a special purpose is certainly not desirable and, with the use of Logic
command. This approach adds little cost to the system Cell Arrays, not necessary.
because it requires only a small amount of EPROM stor-
age. For example, when a PC is initially powered-up, all of The Logic Cell Arrays can perform many different periph-
the system RAM is tested. Further initialization of the PC eral control functions, and can also be the primary inter-
will not take place unless this memory is 100% functional. face between a microprocessor and its peripherals. In
If there is a memory failure, it can be isolated to the specific these microprocessor designs, as previously mentioned,
IC. The LCA allows an extension of this idea. The there would usually be circuitry on the board to which the
microprocessor will still have some special programs for microprocessor mayor may not have immediate access.
diagnostics, but now the diagnostics can extend well The LCA, as the bus and I/O controller for example, would
beyond the immediate reach of the microprocessor, with- easily be able to access this logic as an extension of the
out adding circuitry just for this purpose. microprocessor.

6-54
SELF-TEST TECHNIQUES LOOPBACK

LCAs can be used to implement hardware diagnostics. Many designs have special drivers and receivers on a
When the board is initially powered-up, the Logic Cell board to which there is no direct access. A special
Array can be programmed with a special diagnostic loopback test connector is usually needed to test these
configuration. The LCA can then be used in conjunction drivers and receivers. This connector must be installed
with the microprocessor to test the peripheral circuitry. before and removed aftertesting. This usually means that
This LCA configuration can include the ability to commu- this test is only performed as a last resort, when all other
nicate status information about the peripherals and other tests have failed to find a fault. The Logic Cell Array's user-
circuitry to the microprocessor that might otherwise re- configurable interconnections allow the drivers and receiv-
quire additional logic. ers to be tested without any additional test connectors or
manual intervention. To fully test this circuitry, it is only
The remainderofthis paperwill focus on several examples necessary to connect traces on the printed circuit board
of how the Logic Cell Array can be used to perform board- from the drivers and receivers to I/O pins on the Program-
level self-diagnostics. mable Gate Array. This allows the LCA, with a diagnostic
configuration loaded, to drive the receivers and to read the
data from the drivers without the use of a loopback test
connector. Refer to Figure 1.

L
)
~DRE~
v J
"
A 1/0
\
J.lp
"
CONTROL
v
CONTROL
PGA I PERIPHERAL

A "-
\
~AT~ I
L
1131 01

Figure 1. Diagram of LCA Used in LOOPBACK Testing

•
6-55
Incorporating PLD Equations into LCAs

TESTING I/O AND MEMORY ERROR DETECTION board is fully functional, it can re-program the LCAs for
CIRCUITRY their normal functions and the board can begin normal
operation.
A microprocessor can use the LCA to drive the peripherals
and additional supporting logic in non-standard ways. This
is often valuable in diagnosing circuitry. For example,
INTERRUPT VECTORS
during normal operation of a serial communications chan-
nel, it is not possible to force an error in the transmission Interrupt circuitry is also difficult to test, as. there is not
of the data. This can easily be done, however, when an always a straight-forward method of generating all of the
LCA is used as an I/O controller. It can be programmed interrupt requests. With a Logic Cell Array as the interrupt
with a special diagnostic configuration that can force parity controller in the system, it can be configured with a special
errors, overrun errors, and CRC/checksum errors in the test configuration that can sequence through all of the
data stream which should be caught by the error detection different interrupts. It can even generate multiple inter-
circuitry. This, along with special diagnostic firmware for
rupts in sequences that test interrupt prioritization logic.
a microprocessor, allows full testing of serial (or parallel)
Refer to Figure 2.
communications channels.

This same concept can be applied to testing standard

memory when the LCA is performing memory control TIMEOUT INTERRUPTS
functions or has write access to the memory. With a
diagnostic configuration in the LCA, it can force data into .J Some systems include timeout interrupts such as watch-
the memory with incorrect parity or check bits. The normal dog timers that do not occur in normal operation. This type
circuitry and firmware for reading the memory should then of timeout interrupt is difficult to generate during normal
detect the errors, and the operation of the error correcting operation. Again, using a Programmable Gate Array as an
logic can be verified. interrupt controller allows the designer to easily force this
type of interrupt and verify that the detection circuitry and
As soon as the microprocessor has determined that the error recovery routines are functioning correctly.

TIMER

ADDRESS
DISK

A "- INTERRUPT MEMORY REFRESH

J.lP CONTROL CONTROL
LCA
SERIAL PORT
A "-
DATA CLOCK

\ LCA WILL PRESENT

DIAGNOSTIC INTERRUPT
VECTORS HERE

Figure 2. LCA Used as an Interrupt Controller 1131 02

6-56
 E:.XILINX

PS/2 Micro Channel Interface

Application Brief BY ROB STRANSKY

18M's new general-purpose microcomputer, the Personal Utilities, an add"on card's addressing and other optional
System 2, is available in several models, from the low-end configuration data are established ar1d stored in CMOS
Model 25 to the high-end Model 80. These third-genera- battery-backed memorY on the main board.
tion PCs haveseveral new and innovative features, includ-
ing 3 1/2 inch floppy disk drives, high-resolution VGA Upon power-up, this information is loaded into Program-
graphics, and a 20 MHz 80386 processor as the main mable Option Select (POS) registers residing on the
engine for the Model 80. Among the most interesting adapter cards:
features is the Micro Channel interface,the bus
specification for the interface between the system and Figure 1indicate.s one way in which a Programmable Gate
adapter cards. The Micro Chan riel's streamlined charac- Array can be usedfor the POS register Section of a Micro
teristics and flexibiHty provide PS/2 designers and users Channel adapter card.. The Micro Channel interface
with many advantabes over previous PC architectures. includes logiC to decode the address, status, andcontrol
signals associated with the bus to identify the appropriate
One key aspect Of this architecture is the ability to POS register to be accessed. These signals determine if
configure the system without the need for DIP switches on the· card is being addressed, and wheth.er the. current
the bus adapter cards .. Defined with System Configuration operation is a read or write. .

co~RoL ------------~~--~~------~--_"

READ
. ENABLE

RD EN

READI GATED
STATUS WE
LINES
WRITE
DECODE
LATCtlES 1-----'--+-" WRITE
STROBES SYSTEM
CARD BIDIRECTIONAL
SELECT DATA BUS

ADDRESS REGISTER 1-__-f.N_____~--------l

INPUTS DECODES

111901 Figure 1. Micro Channel Interface B.lock Dlagr..m

6-57
Incorporating PLD Equations Into LeAs

The Micro Channel specification reserves two P~S regis- to the adapter with the highest priority.
ters for the upper and lower bytes of the Adapter
Identification (10). Six other byte-wide P~S registers can As can be seen by the logic in Figure 2, this priority level
hold additional configuration information; some of the bits (ARB 100:3) is driven onto the bus via an open collector
within these are specifically dedicated to channel status driver. The logic then turns around and accepts the driven
information. Some applications will require the use of only bus as input. The cycle may repeat a few times before the
portions of these six registers. adapter with the highest priority level actually gains control
of the bus. For proper operation each haH of the cycle must
A second key ~spect of the Micro Channel architecture is complete in 50 ns, a performance that can be achieved in
its ability to arbitrate the bus access of multiple adapters. the 70 MHz Programmable Gate Array devices.
The Micro Channel specification clearly defines the logic
required for this arbitration. Each adapter in the system is Implementation of the P~S registers, arbitration, logic and
assigned a priority level. These levels vary from the control sections typically requires only 1/3 to 2/3 of a single
highest priority "-2" to the lowest priority "P'. This "-2, -1, XC2018 or XC3020; the remainder of the PGA is available
0,1, 2... A, B, ... F" scheme defines unique priority levels. for implementing the unique functionality of the, specific
The higher levels are primarily used for memory refresh or adapter card. Some Xilinx users have developed the
error recovery. The lower levels are reserved for the standard interface and stored it as a recallable macro
System Board processor and spares. The middle levels funcUon in the Xilinx development system. Applications
are used for DNA Ports 0-7, typically used for high speed including hard disk controllers, communication control-
transfers. The priority level assigned to any adapter is lers, and specialized memory controllers have been devel-
stored in one of its P~S register nibbles. The arbitration oped forthe PS/2 using Xilinx Programmable Gate Arrays.
logic must be very fast in order to grant control of the bus

COMPLETE LATCH

~ 0.0.
ARB BUS 3
ARB 10·3

~ 0.0.
ARB BUS 2
ARB 10·2 1--/
r
bn I~
r
0.0.
ARB BUS 1
ARB 10·1

~ , 0.0.
ARB BUS 0
../
~
ARB 10·0

~
~
WON COMPETfTlON
-' FOROHANNEl

ARB/·ENT
'.
Figure 2. Local Arbiter Logic 111902

6-58
 E:XIUNX

High-Speed Bar Code

Reader Interface

Application Brief BY DAVE LAUTZENHEISER

Bar code readers have become familiar to the average The block diagram in Figure 1 shows the functions per-
consumer due to their widespread use in point-of-sale formed in the PGA. For each type of sensor, the specific
systems, such as those used in most grocery stores. controls and data signals have different functions and
Additionally, many industrial applications are now using timing relationships. In addition, the amount of data can
bar codes to identify materials in various phases of manu- vary depending on the specific application. In different
facturing, inventory and distribution. Bar codes can be scanner interfaces, the counter control logic, edge detect
automatically read and processed to provide for computer- circuitry and the operation of the black area and white area
ized control and optimization of virtually all phases of a counters can be modified to fit the needs of the particular
manufacturing process. In many industrial applications, scanner. The bus control logic and the data loading into
the performance requirements of the bar code system are the interface memory remain virtually unchanged, provid-
significantly higher than those of the point-of-sale system. ing a consistent interface to the processor.

As an example, consider an industrial application where Implementation of the interface logic can be accomplished
material on a conveyor is being scanned to read bar code with either an XC2000 or XC3000 family device. Because
data. If the conveyor is moving at 5 meters/second, and a there are processor and memory data and address bus
barcode label with 30 bars is 25 mm long, that label passes structures, the XC3000 family would provide a simpler
a point scanner i n 5 milliseconds, or 166 microseconds per solution. Even with a master clock rate of 10 or 15 MHz,
bar. If the minimum bar width is 12% of the average time the 16-bit counters forthe black and white areas are easily
period, it must be detected and its width determined in 20 implemented as up counters with reset capability. Edge
microseconds. For a maximum bar width five times the detection is performed with either simple gating, or syn-
minimum, the time period is 100 microseconds. If a chronization to the master clock. Memory FIFO control
multiple scan system is being used, the active period for a also involves counters, but these operate at a much slower
bar is reduced proportional to the scan rate. rate. A new word is written to memory only after a bar in
the target has been passed.
For this type of scanning system, some pre-processing of
the scan data is required to insure that a processor can At the completion of a scan an End Of Label is signalled by
decode the label into code numbers and process them forcing a data entry in the RAM of FF hex. An interrupt to
accordingly. In addition, systems may be required to the processor can be generated based onthe End Of Label
operate with a variety of different bar code scanners or or End Of Scan condition. The microprocessor then
sensors for different objects or labels, at different scan normalizes the absolute timing information for black and
rates. Traditionally, different logic and micro computer white bars stored in the FIFO in order to extract the
coding dedicated to each application was designed. encoded data. This allows for variations in scan speed,

•
scan angle, etc.
Programmable Gate Arrays provide a method of imple-
menting the scanner specific interface logic in a cost This type of interface represents only one of several
effective, compact manner. At the same time, system methods that can be used to pass the information to the
design flexibility is provided while meeting the perform- host processor. For other types of systems, different
ance constraints of the system. Designers of bar code techniques may be used. Regardless of the technique, the
processing systems can design a single interface card that flexibility of the PGA provides significant advantages over
utilizes the programmability of the PGA to define the logic a fixed logic solution.
for a specific scanner in software as part of the system
initialization.

6-59
Incorporating PLD Equations into LCAs

ON/OFF
COUNTER MEMORY
CONTROL BAR FIFO ADDRESS
LOGIC CONTROL

DATA

PROCESSOR
ADDRESS

PROCESSOR
DATA

MEMORY
ARRAY

PROCESSOR ACCESS
MASTER
ARBITRATION CONTROL SIGNAL
CLOCK
CONTROL
GENERATOR

1126 01
Figure 1. Bar Code Reader Interface

6-60
 DRAM Controller
with Error Correction and
Detection
Application Note BYTOMWAUGH

AN INTRODUCTION TO MEMORY CONTROL AND to incorporate error detection and correction into the
ERROR CORRECTION memory system. This solution decreases system perform-
ance and adds the cost of redundant memory, but pre-
The need to design memory controllers for systems that
vents parity errors from causing system failures.
have a large amount of memory is a common design
challenge that engineers must deal with today. Almost all
large memory systems· use dynamic random access OPTIONS FOR DRAM CONTROLLER DESIGN
memory (DRAM) because of its density and low cost.
While designing large memory systems with static random There are a number of options available to the engineer
access memory (SRAM), would make the design task designing a memory system that requires DRAM control.
easier, the drive to produce more cost effective products (The following options apply to the design of error detec-
forces the engineer to design with DRAMs, despite their tion and correction circuits as well.) The simplest option is
inherent drawbacks. The memory cell of a DRAM is a a standard off-the-shelf LSI memory controller. The
capacitorthat holds a charge corresponding to the value of manufacturers of these devices. provide an integrated
the data bit. Since all capacitors leak charge, a DRAM cell solution to DRAM control by combining CPU interface
will gradually lose its charge, and its stored value, unless logic with the necessary memory access/memory refresh
it is recharged. This recharging, known as refreshing, arbitration on a single chip. However, each memory
must typically be performed once every 2 to 4 ms depend- system has unique timing and protocolrequirements, and
ing on the DRAM. Refreshing is one of the DRAM it is extremely difficult for these standard parts to accom-
controller's two. primary functions. The other function is to modate the requirements of every system. This realization
arbitrate between requests for memory read and write has driven many DRAM controller manufacturers to incor-
accesses from the system's central processing unit and porate some degree of programmability into their parts to
requirements for memory refreshes. make them more flexible. Unfortunately, this has made the
parts more complex, hungrier for power, and more expen-
In addition to its need for periodic refreshing, the. DRAM sive. Even so, they simply cannot meet every system's
exhibits another problem that SRAM and other memory requirements without employing external "glue logic."
devices do not-greater susceptibility to soft errors. A soft
error is the loss of a data bit in a memory cell in which the The need to match the DRAM controller to the specific
memory cell is not physically damaged. Rewriting the data requirements of the system has forced many engineers to
in the cell corrects the error. This type of error is different consider two optionsfbr creating their own controllers:
from a hard errorwhich is caused by a memory cell that has SSI!MSI packages or custom gate arrays. The use of SSI!
failed permanently. Soft errors in DRAMs are usually MSI is low risk, but wastes space and power; while the use
caused by alpha particles (helium nUClei), which are nor- of the custom gate array provides a highly integrated
mally present in the atmosphere, but which are more often solution, but at considerable risk and expense. Non- •
emitted by radioactive impurities in the IC packages of the recurring engineering costs (NRE), testing and simulation
DRAMs themselves. If an alpha particle hits a memory costs, inventory risk, and a long design cycle make the
cell, it can corrupt the cell's charge, causing a data bit error. custom gate array option unattractive for most designs.
Most people believe that the likelihood of such an error is Recent architectural advances in high density user pro-
so low that it can be safely ignored .. While this may have grammable logic have created a third option. Xilinx's 3000
been true for the smaller memory systems of the past, it familyof programmable gate arrays brings unprecedented
may no longer be so. The size of some memory systems density to programmable logic, with devices containing as
today can make the likelihood of soft errors unacceptably many 9000 usable gates. The architecture of the 3000
high. The probability of a soft error can be reduced by family devices make them particularly well-suited to
device and packaging improvements and by reduction in memory controller applications.
signal noise. Another method of dealing with soft errors is

6-61
Incorporating PLD Equations into LeAs

WHY IMPLEMENT A DRAM CONTROLLER WITH A (ECC) with an LCA. The example is an 8 MHz8086-based
PROGRAMMABLE GATE ARRAY? system that directly addresses 1 MB of memory comprised
of forty-four 256 KB DRAM chips: thirty-two for data and
There are several reasons why one would want to design
twelve for the correction bits. A single LCA can serve as
a DRAM controller with a Xilinx Logic Cell™ Array. First,
both the DRAM controller and the ECC, which performs
the true programmability of the LCA gives the designer the
single bit error correction and double bit error detection.
freedom to design the DRAM controller to the exact
There are several features of the 3000 family architecture
specifications of the memory system. There is no need for
that make this design possible. These include five input
the external "glue logic" often necessary with standard
configurable logic blocks (CLBs) with two storage ele-
solutions, because any necessary design tweaking is
ments, internal buses, and flexible input/output blocks
implemented internally. The LCA solution has the advan-
(lOB).
tage of the SSI/MSI or custom gate array solution in that it
can be configured to meet unique system requirements.
There is no loss in integration as with the SSI/MSI solution, DESIGN OVERVIEW
and the cost and risks of the custom gate array solution can
be avoided. Second, the density of the 3000 family of The DRAM Controller/ECC uses a 16 MHz clock synchro-
LCAs makes it possible to implement DRAM control and nized with the processor's clock, and sits between the
error detection/correction in a single LCA. This is tradition- 8086 microprocessor with its 8288 bus controller and the
ally a two chip solution using standard parts: a DRAM system memory (Figure 1). The 8288 decodes the proc-
controller and a separate error correction and detection essorstatus lines (S2, S1, SO) and tells the DRAM Control-
unit. It can of course be implemented in a single custom ler whether it is to perform a read or write access to the
gate array, but again with the earlier caveats. Finally, the memory. (It is also possible to incorporate the bus control-
CMOS LCA consumes less power than traditional stan- ler logic into the larger LCAs). The DRAM Controller then
dard "programmable" controllers which are typically imple- performs the appropriate access issuing Row Address
mented in NMOS or bipolar processes. Strobe (RAS), Column Address Strobe (CAS), and Write,
if necessary. The Error Checker and Corrector generates
DESIGN EXAMPLE check bits on each write, and checks for and corrects
errors on each read. The controller also signals the 8086
The following design example shows the implementation if the memory access requires a wait state or if a non-
of a DRAM controller and an error checker/corrector correctable error is detected.

8284
CLOCK
XILINX LeA BANKO
GENERATOR iCLK
------ READY
SO f--
f---t>
8288
BUS CASH.L
W
t; (512K BYTES)

~
Sl CONTROLLER 6+16=22
READY ------ RESET BANK 1
f---t>
=: RAS 0.1 256K DRAMS

-
(512K BYTES)

r~
S2 MRDC READ
AMWC WRITE OUT 0-8 AO-8
CEN HOLD
8086 CHECK DATA
DEN BITS BITS

~
DATA
A19 BANK SELECT BITS
BITS
Al6-18 Al6-18
CBO·5 ~
(CHECK BITS)

ADO-15
ENABLE
v-- I"'" ADO-15
MULTI-BIT
ERROR
r-- T08086NMI

WAIT r--
74LS245 16
DATA BUS

112709

Figure 1. System Overview

System overview of DRAM Controller with error correction and detection.

6-62
 ~XIUNX

SYSTEM TIMING address and data on a multiplexed bus to be latched from

the same I/O pin. Figure 4 is a bit sliced view of an lOB
Rgures 3a-3c show the timing involved in some of the used to latch the multiplexed Address/Data bus. In this
different memory cycles. The Word Write (Figure 3a) design, the address is latched into the lOB input flip-flop
requires no wait states as shown. The check bits from the with the 8086's ALE. The data from the 8086 can enterthe
ECC are written to memory along with the data. The Read same input pin and go directly to the ECC circuit via the lOB
cycle (Figures 3b & 3c) requires a minimum of one wait direct input-there is no need for external latches.
state. The insertion of a wait state is unavoidable because
of the time it takes the 120 ns DRAMs to output the data.
Another feature of the lOBs is the output flip-flops with
If the ECC detects no errors in the data, the WAIT signal
three-state buffer enables. This feature permits bit error
is released and the read operation is completed. If an error
correction using only one I/O pin. Figure 5 shows a bit
is detected, the insertion oftwo more wait states is required
sliced view of how the ECC is accomplished. A memory
to allow time to correct the error. The insertion of the two
read cycle provides the best example for showing the
additional wait states effects system performance, but this
capabilities of the lOB structure. During a read, the lOB
is the trade-off for having error correction, which avoids the
output is three-stated, permitting the DRAM data on the
fatal system errors that occur with parity-checking-only
Data Bus to enter the ECC via the lOB direct input. If the
solutions.
ECC detects a data bit error, it corrects the error and
latches the corrected data word into the output flip-flops of
DESIGN FOCUS the lOBs. The Data Bus is then three-stated by turning off
the DRAM outputs. The corrected word, latched in the
The 3000 family LCA architecture has a number of fea- outputs of the flip-flops, is then released onto the Data Bus
tures that are essential to the DRAM controller design. The by enabling the three-state buffer. This allows the cor-
first such feature is the dual data input paths in the lOBs, rected data to be read by the 8086 at the same time it is
one registered and one direct. This structure permits the being written back to the DRAM.

r-------------------- r - - - - - - t - - O U T P U T ENABLE
I
r- -4- -iQ---~ - - - - - - -- ---- CORRECTED DATA OUT
I I I ~-+--FROMERROR
CHECKER/CORRECTOR
]
I I I

~-1
I L. ___ .J: q..---t-- OUTPUT CLOCK
I DIRECT INPUT DATA TO ERROR

REGISTERED INPUT
CHECKER'CORRECTOR
ADDRESS TO INTERNAL
BUS VIA THREE STATE
.-------+---.- g~~~~~~~~~ECTOR
BUFFER r---'
10 QL __ _
I I
I I
I I

I I ___ 40---
L J
I ALE
IL _______________________ _

112706 112707

Figure 4. Address and Data Latching Figure 5. Data In and out through ECC •
Latching Data off a Multiplexed Address and Data Bus. Data Flow through the ECC The data from the bus goes
The Input/Output block configuration shown above illus- into the LCA, where it is corrected in the ECC. The
trates how the direct and registered inputs in the lOBs corrected data is then put back onto the bus via the lOB
can be used to latch a multiplexed address/data bus output flip-flop.
into the LCA. The address is latched into the lOB flip-
flop; the data flows directly into the ECC logic.

6-63
Incorporating PLD Equations into LeAs

T1 T2 T3 T4

8086
CLOCK

ALE ~~__________________________________________

CONTROLLER
CLOCK

RAS

CAS

--------~(~--------------------------------~>~----
DATA FROM
BOB6

112703
Figure 3a. Word Write Timing

T2 T3 TW TW TW T4

8066
CLOCK ' - -____-'

CONTROLLER
CLOCK

MS ~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~ 1 - . - -_ _ ----11
CAS
'------'I
w
~
WAIT ~L._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - '
ERROR DETECTED CORRECTED DATA LATCHED CORRECTED DATA RELEASED
I/O 3·STATED
DATA BUS -----------<
1127 04
Figure 3b. Word Read Timing with Errors Detected

g I B I ffl I R I
c~~~ ~__~r--l~ ____~r--l~____~r--l~____~r--l~_____
RAS~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

CAS

WAIT 1'--________________--'
DATAb~2~ ______________ ~(~___________________________'>~-------
1127 05
Figure 3c Word Read Timing with No Errors Detected

6·64
 E:XILINX

Figure 2 is a block level diagram of the DRAM Controller by this block include the row address and column address
and ECC that reside in the LCA. A functional description strobes (RAS and CAS), the WRITE Signal, the WAIT state
of each block follows: signal for the processor, the HOLD signal that isolates the
processor from the memory, the clock for the refresh
The refresh timer is driven by the 16 MHz clock to provide address counter, and the select control for the address
a signal that tells the DRAM controller that the memory select.
needs refreshing. Each of the 256 rows of memory in this
system must be refreshed every 4 ms. The controller The refresh address counter is an eight bit counter that
attempts to refresh eight rows every 125 I1sec, so that all provides the eight bit addresses necessary to refresh the
256 rows are refreshed in 4 ms. The refreshing technique DRAMs.
employed in this design is a unique combination of burst
and hidden refreshing to show the flexibility of the The address selector selects which address is sent to the
LCA-based solution. There is no need to force a system to DRAM. During a read or write cycle the timing generator
conform to the constraints of an off-the-shelf part. The select control signal tells the address selectorto select the
Hidden Refresh is performed when the 8086is doing a read DRAM row address, strobe it with the RAS, and then select
from or write to somewhere other than memory, like an 1/0 the column address and strobe it with the CAS. During a
port. This involves giving the DRAM a refresh address from refresh, the address selector selects the address from the
the refresh address counter via the address selector and a refresh address selector and strobes it into the DRAM with
RAS pulse low from the timing generator. The Burst RAS.
Refresh is performed only if it has not received its eight
required refreshes during the 125 I1sec refresh period. During a write cycle, the error checker/corrector (EGG)
When a Burst Refresh is required, the controller will isolate generates six check bits using a modified Hamming code
the memory from the 8086, insert wait states, and provide for each sixteen bit data word and writes them to memory
the number of refreshes it needs in order to complete the along with the data. Use of a modified Hamming code
eight refreshes required during the refresh period. permits single bit data correction and double bit error
detection. During a read cycle, the ECC compares the
The timing generator, a state machine triggered by Ad- check bits read back from memory with new check bits
dress Latch Enable (ALE) at the beginning of the proces- generated from the data read back. If the comparison
sor cycle, produces all the timing required to perform the yields a correctable error, the ECCwill correct it. Ifthe error
memory accesses and refreshes. The signals generated is not correctable, it will flag the NMI on the processor.

DATA BUS 16
TO DRAM DATA

TIMING DO-I5
REFRESH TIMER CBO·5 TO DRAM DATA
GENERATOR
ECC ERROR CHECKER!
BURST REQUEST CONTROLS CORRECTOR
HIDDEN REQUES,T1--~
MULTI· BIT ERROR TOB086NMI
RESET
BANK SELECT W
RASO.l TO DRAM
ALE
CASH.L
MRDC
WAIT TOB086
AMWC HOLD TO BUS CONTROLLER
III
MUX CONTROL b==:rAADD5iDRRiEEiS~siiM~Uu:xK]
16MHz
INCREMENT
AI·9
OUT 0·8 TO DRAM ADDRESS
AIO·IS
REFRESH REFRESH
ADDRESS ADDRESS 0·7
COUNTER
INCREMENT
COUNTER
112702
Figure 2. LCA Block Diagram
Block diagram of the DRAM controller functions implemented in the LCA.

6-65
Incorporating PLD Equations into LeAs

Perhaps the most important feature of the LCA architec- CONCLUSION

ture for implementing a DRAM Controller is its intemal
three-state bus capability. The three-state buffer enables Although the bottom-up design of a DRAM controller is a
onto the horizontallonglines allow the designer to imple- complex task, it is necessary in cases in which off-the-shelf
ment an internal bus in the LCA. This feature permits the controllers do not meet the requirements of the system.
implementation of the Address Selector without using any SSIIMSI and custom gate array solutions involve trade-
CLBs. Figure 6 shows a bit slice view. The row, column, offs and compromises. Designing a DRAM controller and
and refresh addresses all have access onto the internal ECC with an LCA is a straightforward application and a
bus, and to the outputs that lead to the DRAMs. By good fit for the 3000 family architecture. The Program-
controlling the three-state enables, only one address is mable Gate Array offers the flexibility. necessary to match
allowed onto the bus at a time. This feature is essential to the many different memory systems, the integration desir-
this design, and has many other applications including able for board level designs today, and the cost effective-
performing wired-AND functions and address decoding. ness required to make a competitive product.

INTERNAL BUS
----------~------------------~------------------T----!gg::S~LlNE

ROW COLUMN REFRESH

ADDRESS ADDRESS ADDRESS
ROW COLUMN REFRESH
ENABLE ENABLE ENABLE
1127 OS

Figure 6. Address Multiplexing Using Three-State Enables onto Internal Buses

6-66
 Logic Analyzer/In-Circuit
Emulator

Application Brief BYBRADFAWCETI

Logic analyzers and in-circuit emulators are similar types ger or breakpoint occurs. Triggers and breakpoints might
of electronic test equipment. Each involves the monitoring be defined as a single event in the target system, or some
of certain digital signals within the system being tested. For ordered sequence of multiple events. Usually, trigger and
general-purpose logic analyzers, these signals can be any breakpoint conditions are simply stored in registers and
nodes on the board being tested that the user selects. then continuously compared to the target system signals
Anothercategory of logic analyzers, sometimes called bus that are being monitored. Typically, logic analyzers and
analyzers, are designed to plug into a specific microcom- in-circuit emulators use many SSI/MSI latches and com-
puter bus (such as a PC-bus or Multibus) and monitor and parators to perform these functions.
control the activity on that bus. In-circuit emulation of a
specific component (usually a microprocessor) involves The large numberof logic functions and registers available
monitoring and controlling the signals input and output by in the Xilinx Programmable Gate Arrays make them ideal
the device being emulated. for implementing these trigger and breakpoint functions
within a single device. Furthermore, the interface logic for
A record of the activity on the nodes being tested by the controlling the trace memory can also be integrated into the
analyzer is stored in a memory buffer called '1race mem- PGA. This application can take advantage olthe re-config-
ory"; this activity is called "acquisition mode." In some urable nature of the PGA architecture. (Effectively, the
cases, the analyzer might also be contrOlling some of the Programmable Gate Array can perform different functions
target system's functions, such as single stepping a clock within the same system at different times by loading differ-
or interrupting a processor. After tracing is completed, the ent configuration programs. This can lead to fewer pack-
trace memory is then read and displayed by control logic in ages on the printed circuit board and increased reliability.)
the analyzer; this is the "analysis mode." Trigger and One configuration of the PGA could be used for acquisition
breakpoint logic is integraltothisoperation;the userspeci- mode operation, capturing data, searching for the triggers
fies when the tracing of signals in the target system should and breakpoints, and filling the trace memory. When the
begin (triggering) and end (the breakpoint). Hence, a de- breakpoint is reached, a different configuration could be
scriptionolthe combination of Signals that make upthetrig- loaded into the same PGA forthe analysis mode; the PGA
gers and breakpoints must be stored in the analyzerbefore now controls the reading of the captured data from the
beginning operation, and the state of the target system trace memory. Additional functions, such as control of the
must be continuously monitored to determine when a trig- user interface, also could be incorporated into the PGA.

ADDRESS

DATA
DATA
TRACE
MEMORY
MEMORY
SYSTEM TRIGGER ADDRESS
UNDER
INPUT AND
CONTROL
GENERATION

II
TEST CAPTURE BREAKPOINT
LOGIC LOGIC CONTROL
CONTROL

CONTAOI.
CONTROLLER
PGA
ACQUISITION MODE

ADDRESS

DATA
DATA
TRACE
MEMORY
MEMORY
USER USER ADDRESS CONTAOL
INTERFACE INTERFACE GENERATION
CONTROL +
CONTROL
CONTROL

CONTROL
CONTROlLER
PGA
ANALYSIS MODE

1128 01 Figure 1. Logic Analyzerlln-Circuit Emulator

6-67
 E:XILIXX

The Programmable Gate Array Company

l:XllJXX SECTION 7

Article Reprints

1 Programmable Gate Arrays

2 Product Specifications

3 Quality, Testing, Packaging

4 Technical Support

5 Development Systems

6 Applications

7 Article Reprints

8 Index
 Article Reprints

Building Tomorrow's Disk Controller Today ........................................ 7-1

The Acid Test ...................................................................................... 7-5
Programmable Logic Betters the Odds ............................................... 7-8
Using LCAs in a Satellite Earth Station ............................................... 7-12
Faster Turnaround for a T1 Interface .................................................. 7-17
Two, Two, Two Chips in One ..................................................; ........... 7-19
LCA Stars in Video .............................................................................. 7-22
Taking Advantage of Reconfigurable Logic ........................................ 7-24

1962
Electronic
Products
~o,;_,","""~,,rp"."" ,,,h,,,',,.
Building Tomorrow's Disk
Controller Today

Jim Reynolds, President, Dave Randall, Chief Engineer, Andromeda Systems, Canoga Park, CA

Reprogrammable logic with a flexible architecture could be surface mounted onto a 35-in. 2 dual-width board.
enables a controller to keep up with today's high- The only answer appeared to be VLSI custom or semicus-
capacity, high-speed disk drives tom devices like gate arrays. But gate array definition
requires absolute design accuracy, and so a prototype
Computer manufacturers historically have relied on ad- must be constructed long before custom-tooled ICs can be
vances in CPU and semiconductor memory tech nology for specified and manufactured. Paradoxically, the prototype
increasing system throughput. At the same time, they itself required highly integrated logic.
accepted as inevitable the hardware-bound I/O bottle-
neck. This position is becoming untenable with recent To break thatfrustrating circle, il was necessary to convert
advances in magnetic disk technologies, which have led to directly from schematic capture to a silicon breadboard of
a proliferation of high-capacity, high-speed drives. multiple electrically programmable logic devices (EPLDs).
Because many logic functions would be added to the
Full performance from these drives needs sophisticated
prototype after the initial test, EPROM-based PALs were
controllers like Andromeda Systems' new Storage Module
considered, like the EP1200 from Altera, which licenses
Device Controller (SMDC). With a 1-Mbyte data cache
the technology from Monolithic Memories.
and dynamic read-ahead algorithms, the SMDC dramati-
cally reduces average disk access time and significantly
improves overall system performance (see box, "The The EP1200 could provide the minimum functionality on
Storage Module Device Controller"). The design and the silicon breadboard, but not the level of device integra-
performance benefitted greatly from using Xilinx's Logic tion for the production circuit board. To implement the
Cell Arrays (LCAs). various state machines and other logic of the design, each
target gate array would need three EP1200s. The result-
Very early in the design, it was clear that its high-perform- ing schematic capture and simulation would then be used
ance caching scheme needed more SSIIMSI logic than to fabricate the gate arrays for Ihe final product.

CACHE MEMORY
1-MBYTE DRAM PERIPHERAL

... EXPANSION
PORT
f

I
CACHE
ADDRESS
MAPPER

!
I
>----0 DISK
CONTROLLER
-
O-BUS
INTERFACE
~ ~
... STORAGE
MODULE
DEVICE
LCA3 INTERFACE
LCA.1 LCA2
O-BUS AND DMA CACHE SM&~~~:g~I~~~AL ..
CONTROLLER CONTROLLER CONTROLLER

i r i
J
65C802 MICROPROCESSOR
USER
SERVICE
II
I
PORT

STATIC EEPROM
RAM

114801

Figure 1. On Andromeda Systems' new Storage Module Device Controller, Xilinx Logic Cell Arrays handle the Q-bus interface
and direct memory access (DMA) Control, RAM/data-cache control, and SMD and peripheral expansion port control.

7-1
Article Reprints

Fortunately, this circuitous design path was bypassed by

using Xilinx's LCA (see box, "Xilinx's programmable gate
array"). There are two basic differences between LCAs
and other EPLDs. First, the LCA has the flexible architec-
ture of a gate array. Second, LCAs employ static memory
to hold the logic configuration data.

The LCAs brought several significant advantages to the

controller design. Since the Xilinx 2064 LCA has 64
configurable logic blocks and the EP1200 only 20, a single
LCA could replace the three target gate arrays, elimination
the fabrication delays and costs of custom tooling.

Furthermore, the position of the LCAs on the board could Figure 2. The user service port can create color bar graphs
be determined before their internal logic configuration was that dynamically show various attributes of the data cache,
designed. Other than dedication input and output pins, such as read times, forward block reads, and 110
only a general idea of the function of each LCA was completion rates.
needed. The board layout and the internal LCA logic
design could proceed in parallel, greatly reducing develop- Aside from the LSI circuitry, the only other logic on the
ment time. Most design changes could be implemented SMDC board are TIL bus transceivers, SMD interface
merely by reprogramming the LCAs. Thus, u!>e of the drivers, and a few PALs.
LCAs allowed the design to go directly from schematic
capture to a production board, skipping the wire-wrapped
The RAM of the data cache is in ZIPs. Most of the interface
prototype.
logic was surface mounted to the board. Despite the
The first LCA on the SMDC is the Q-bus interface and board's small size, these VLSI devices permit several
direct memory access (DMA) controller (see Fig. 1). All but advanced features.
5 of the 64 internal logic blocks were used. The LCA holds
the DMA addressing logic, the bus registers, and the The SMDC's user service port connects directly to termi-
interrupt logic. nals or modems. No special test programs for specific
system environments are needed to communicate with the
RAM/data-cache control is the job of the second LCA. It controller. Users can define drives, assign logical units,
controls the cache and has the interface between the disk format drives, and do other more esoteric functions.
controller IC and the DMA logic. It signals cache-write
enables, multiplexes memory addresses, and enable
This port can monitor the operation of the controller while
DMA reads and writes.
the drive is in operation. The user can display color bar
The third LCA controls the SMD port and peripheral graphs that dynamically show various attributes of the data
expansion port. The expansion port is just a group of cache, such as read times, forward block reads, and 1/0
programmable I/O connections. Since the LCA is pro- completion rates. Caching parameters can·be adjusted,
grammable, the control logic forthe expansion port can be letting the user tune the system for optimum performance.
reconfigured for any desired 1/0 interface. Thus, this port
provides for future expansions (like adding a tape drive, Firmware can alter the configuration data for the LCAs,
optical disk, or extra cache memory) at a fraction of the modifying the circuit schematic and not the board. Since
cost of a separate controller. Unused logic in this LCA will the firmware is in EEPROMs, the service port can accept
permit on-board functions to be added in future microcode microcode upgrades in the field via modem. PROM set
revisions to the controller. replacement and on-shelf obsolescence are avoided.

7-2
 E:XILINX

THE STORAGE MODULE DEVICE CONTROLLER Andromeda divides the cache into 1,024 granules. The
information kept for each 1-Kbyte granule depends on
Designed for LSI-11 and MicroNAX II systems, select criteria, which include:
Andromeda Systems' Storage Module Device Controller
(SMDC) for Winchester drives supports two SMD or The time data is first accessed
SMDE drives at data rates up to 25 Mbits/s. Another The number of times data is read
Andromeda controller, the ESDC, works with the En- The time of the most recent read
hanced Small Device Interface, the ESDI, for Winches- The size of the read.
ters or floppy-disk drives. Both controllers use the stan-
dard DU device driver and work with such operation sys- This information is then entered into an equation that
tems as RT-11, TSX+, RSX, RSX-11M, MicroRSX, approximates how probable it is that the granule will be
RSTS, MicroRSTS, Ultrix, DSM, Unix, and MicroVMS. requested again soon. Those granules with low proba-
bilities are designated to be overwritten by the next disk-
The SMDC achieves more performance and flexibility read operation. During cache accesses, a memory
than did previous generations of disk controllers. It in- mapper translates logical memory addresses into the
cludes data caching, high data-transfer rates, a periph- physical addresses of the appropriate granule in much
eral expansion port, field-Ioadable microcode, and a user the same waythatthe Micro-Vax II memory management
service port. State-of-the-art VLSI components and unit would.
packaging techniques fit the entire controller within the
35 sq in. of a dual-width a-bus board (see figure).
PREDICTIVE CACHING
Using Digital Equipment's Mass Storage Control Proto-
col (MSCP), the SMDC can partition two drives into as In a novel departure from· most caching schemes, the
SMDC caching mechanism not only looks at the past, but
many as 16 logical units with up to 32 Gbytes each. On-
tries to gaze into the future as well. Asthe system re-
board intelligence comes from a 65C802 microproces-
quests the data that has been pre-fetched into the cache,
sor, and all the processor's code resides in just two
EEPROMs. The majority of the remaining logic is imple- the controller retrieves not only the requested data, but
mented with Xilinx programmable Logic Cell Arrays also preemptively reads extra sequentiafblocks when
(LCAs). Data integrity is ensured by 48-bit error detec- specific probability conditions are met. As a result, the
on-board cache's typical hit rate is over 80%. In other
tion and correction logic. An expansion port can be con-
nected to accessory modules, allowing control of devices words, the data being sought by the applicatiOn wil.l be
like tape drives, optical disks, or extra cache memory. ready and waiting in the cache over 80% Onlle time.

The performance of the SM DC is greatly enhanced with Approximately 90% of the disk access time is due more
a 1-Mbyte data cache and unique caching algorithms. to average seek times and rotational latency than to the
actual data tran$fer rate. However, when a cache hit
occurs, the access time depends only on the speed ofthe
DMA channel responsible for sending the data to the
a-bus.

That DMA channel operates as fast as a-bus specifica-

tions allow.,....to be specific, at a rate of upt04 Mbytes/s.
Consequently, with the SMDC cache, see.k time andro-
tationallatency are reduced to zero over80% ofthe time.
This reduces the average time for a four-blockread from
27 ms to less than 6 ms.

In the majority of computer systems, mass-storage ac-

cess time is undoubtedly the largest component of
throughput. In this situation, use of the SMOC
enormously improves total system performance.

$$$$$
Andromeda Systems' Storage Module Device Controller
is available now for $2, 195. (The company's ESDI con-
troller is available for $1,995.) For more information,call
Don Talmadge at 818-709-7600,or circle 336 for the
SMOC and 337 forthe ESDC.

7-3
ArUcla Reprints

XILlNX'S PROGRAMMABLE GATE ARRAY

The Xilinx programmable gate array, known as a Logic

Cell Array (LCA) , is a high-density CMOS IC that combines
0 g Qg
user programmability with the flexibility of a gate array
CONFIGURABLE
architecture and the economy and testability of standard LOGIC BLOCK~

o
products. Elements of the array include three categories
of configurable elements: 1/0 blocks, configurable logic
blocks, and programmable interconnections (see figure). -[} 0 0 0
I/O blocks provide an interface between the external

0 oro 0
package pin and the internal logic. Each block includes a -[}
programmable input path and output buffer. The array of
configurable logic blocks contains the functional elements
-[} 4---INTERCONNECT AREA-----+-
from which the user's logic is constructed. Each array
-[}
includes a combinatorial section, storage elements, and
internal routing and control logic. Programmable intercon-
nection resources connect the inputs and outputs of the
-[} 0 010 0
I/O .blocks and configurable logic blocks into the desire
-[}
networks.

An LCA is configured by programming static memory cells -[} 0 0 0 0

that determine the logic functions and interconnections.
On-chip logic provides for automatic loading of the con- 1148 02
figuration program at power-up or upon command. A
personal computer-based development software package
generates the configuration program. Other tools include
a simulator, in-circuit, and schematic capture package. Reprinted with permission of Electronic Products.

7-4
 FJectronic Engineering

TlMF~ The Acid Test

By Steven K. Knapp, Field Applications Engineer, Xilinx Inc.

Using an EPLD vendor's application, the same circuit The configurable logic blocks contain combinatorial logic
was built with a Logic Cell Array. The comparison plus storage elements. The combinatorial logic within
provides real insight to the differences between these each block implements any possible single function of four
two technologies. variables, or any two functions of up to three variables.
The storage element is configurable as an edge-triggered
As with a processor, a PLD's architecture determines its flip-flop, or as a level-sensitive latch, both with asynchro-
functional logic density and its performance. nous SET and RESET inputs. The programmable inter-
connect allows each of th e storage elements to be clocked
Among processors, general-purpose microprocessors either synchronously or asynchronously.
and application-oriented devices like digital signal proces-
sors share many similar internal logic structures and Three levels of programmable interconnect resources
functions. DSPs have a more rigid architecture, designed provide the interconnection between blocks:
for particular applications, while general-purpose micro-
processors address a much wider set of applications. The • Direct interconnect allows fast connections between ad-
same situation exists in the world of PLDs. jacent blocks.

Until recently, the sum-of-products (SOP, also known as • General-purpose Signals travel through an array of
AND-OR) structure was the only one available for PLDs. switching matrices that yield an efficient means of con-
Its simple, fixed architecture fits a variety of low-density, necting scattered random logic.
high-speed applications. These include fast, wide logic
functions found in decoders, multiplexers and counters. • Long metal lines that traverse the chip distribute clock or
other signals with high fan-out or requirements for mini-
Some recently introduced high-density PLDs are based on mum skew.
extensions of the conventional AND-OR architecture.
Examples include the MMI 64R32 MegaPAL and the The best way to illustrate the difference between the Logic
Altera EP1800 Erasable Programmable Logic Device Cell Array and the more conventional AND-OR architec-
(EPLD). tures is through a design example.

Like a DSP processor, the sum-ol-products architecture of An X-V position controller design was originally developed
these devices efficiently meets certain needs. However, by Altera as an application example for its EP1800. The
this architecture is not suitable for higher-density, register- design is fairly simple, and illustrates the capability of
intensive random logic structures commonly found in logic programmable logic to address the problems faced by
designs. logic designers. The example can be used to demonstrate
the capabilities of both the Altera EPLD, and the Xilinx
Logic Cell Array.
LOGIC CELL ARRA V
X-V position controllers are employed in a variety of design
The Programmable Gate Array differs vastly from the applications to control motors for printers, plotters, robot-
conventional sum-of-products architecture. Its flexible, ics, and numerical controllers. The controller compares
register- and I/O-rich, array-style architecture addresses a
wider set of common logic design problems.
the desired location loaded from an external processor
with the present motor position stored within the PLD.
Based on the results of the comparison, the controller
II
Its Logic Cell Array architecture consists of three basic drives two four-phase stepper motors (an X- and a
programmable elements: inpuVoutput blocks, configur- V-position motor) to its desired position.
able logic blocks and programmable interconnects.
In this design, X- and V-position data is loaded into the
Each 1/0 block can be individually configured as a direct or device from an external microprocessor. The 1,800-gate
registered input, a direct or three-state output or as a EPLD has no input storage elements, so the data must be
bidirectional 1/0. held valid by some external device until both motors reach

7-5
Article Reprints

their final position. Since the Logic Cell Array has inputflip- final location. This also signals the processor that further
flops which hold the X- and the V-position data,.it offers a motor action may be taken. A master RESET signal resets
simpler interface to the processor. . the present position to zero.
The desired position data is compared against the present
position data. The result of the comparison drives the RESOURCE REQUIREMENTS
7-bit upldown counters which, in turn, drive the state-
machine motor control. The stepper motors used in the . Based on the requirements of the deSign, the X-V position
application have 7.5 degree fullstep increments with op- controller example requires 47 of the 48 macrocells in the
tional3.75 degree half-step increments available. A 7-bit 1,800-gate EPLD and all of its 64 1/0 pins. A number of the
binary up-down counter is required to keep track of the 96 1/0 pins are used simply because a register is hard-
motor steps required to rotate each motor a full 360 connected to the pin. The two 7-bit counter, for example,
degrees. . use 141/0 pins because they cannot be buried. The X-V
controller design uses 98 percent of the macrocells and
In the EPLDdesigns, seven macrocells are used toimple- 100 percent of its 1/0 pins.
ment the binary upldown counter for each half of the
position controller. Because of the low-frequency clock The same design (plus the input data registers) fits in 49
(500 kHz), this same counter requires only seven Logic configurable logic blocks and 27 inpuUoutput blocks in a
Cell Array logic blocks. If this were a high-speed counter, Logic Cell Array (the MASTER RESET input uses the
a few additional blocks would perform some level of carry- Logic Cell Array's dedicated master reset pin). Fewer 1/0
look-ahead. pins are requ ired, since the 7-bit upldown counters and the
state-machines were buried in the Logic Cell Array design.
If the desired position is greater than the present pOSition,
the state-machine-based motor control drives the stepper The X-V controller design would occupy 77 percent olthe
motor clockwise. lithe position is less, the controllerdrives 1,200-gate XC2064's logic blocks and 47 percent of its
the motor counter-clockwise. 1/0 pins. Or if the 1,800-gate Logic Cell Array were used,
the X-V controller would occupy just 49 percent of the logic
Four EPLD macrocells are required to implement the blocks and 36 percent of its 1/0. The remaining logic and
state-machine for each half of the position controller, while 1/0 blocks can be used to build chip select logic to make a
seven Logic Cell Array logic block.s are required to imple- clean interface to the microprocessor.
ment the same function.
The architectural differences between the two technolo-
To signal the processor that the entire operation is com- gies allow a design which requires an entire 1,800-gate
plete, an open drain interrupt signal is generated when EPLD to fit in just a portion of a 1,200-gate Logic Cell Array.
both the X-and the V-position motor have reached their The EPLD can perform anyone of the required tasks quite

CLOCKWISE-X

CW

HALF-8T STATE-
X-8IDE . T·BIT 7-BIT MACHINE
DATA UP/DOWN COMPARE
LATCH COUNTER CCW
X-8IDE

DONE-X

HALF-8TEP-X

X-GLOCK
OPEN-DRAIN
INTERRUPT
CLOCK
GENERATOR
-;--- - - -" --
1148 03

The schematic above Illustrates the X-axis half of the p~sltlon controljer used as the design example. The other half Is
identical to this cirCUit, and drives the Y axis instead of the x.

7-6
 E:XIUNX

well. The sum-of-products architecture allows EPLDs to equal gate counts will differ on functional density within a
implement fast counter, decoders, and multiplexers in a system because of differences in architecture. A better
single pass. Combining these elements into a larger, more way to determine density is to countthe types and amounts
complex system with additional passes through the array of various resources on the chip, and compare those with
however, hurts both performance and density. the needs of your application .

The flexible Logic Cell Array architecture allows entire • Understand which PLD architecture best suits your ap-
plication. The sum-of-products (AND-OR) architecture is
complex systems to be implemented efficiently and
well suited to applications that require ANDing of a large
quickly. Given the same 1,800 gates of logic, and
number of inputs, like those found in address decoders
1,800-gate Logic Cell Array could implement an X-Y-Z
and some counters. The interconnect structure of an
position controller in the same density used to implement
an X-V controller in an EPLD. AND-OR PLD makes single-pass logic functions quick
and efficient. However, the complex random logic require-
ments of higher-density logic design stretches the limits of
CONCLUSION conventional AND-OR devices because of the feedback
requirements.
The benefits of programmable logic devices within any
• Determine your 1/0 and register requirements. In most
design are generally undeniable. Both devices shown in
AND-OR PLDs, outputs are hard-connectors to the regis-
the design example (the EP1800 EPLD, and the XC2064
ters within the device. Therefore, each register either uses
Logic Cell Array) replace many SSI/MSI components.
orwastes an 1/0 pin and vice versa. In the Logic Cell Array,
However, not all PLDs are created equal. A designer 1/0 and registers are separated by programmable inter-
should contemplate his system needs and goals when connects. Therefore, entire register resources like count-
deciding which PLD to use. Like making the correct choice ers and shift registers can be buried without using or
of a system processor, the correct PLD choice will have an wasting 1/0 pins.
impact on the final system performance. Major enhancements in high-density PLDs will stem from
architectural. innovations rather than process-related
Some guidelines and cautionary notes are necessary for developments. Regardfess of which production process is
designers new to the PLD approach. These are: used, all PLD manufacturers are searching forthe optimal
mix of high performance, high density, and production cost
• Be wary of PLD gates counts. As mentioned before, not
to best meet deSigner's logic needs.
all PLDs are created equal. Equivalent gate counting is
used by many manufacturers to compare their devices Reprinted with permission from Electronic Engineering
against a competitor's. Two devices with approximately Times.

MegaPAL MegaPAL EPLD EPLD LCA LCA

Claimed Gate 1,500 5,000 1,200 1,800 1,200 1,800
Density
Architecture AND-OR AND-OR AND-OR AND-OR Array Array
Developed By MMI MMI Altera Altera Xilinx Xilinx
Inputs (max.) 32 64 36 64 58 74
Outputs (max.) 16 32 24 48 58 74
Storage Elements 16 32 28 48 64 100
Elements 0 0 12 0 58 74
Speed For
16-lnput AND
(ns, On-through- 40 50 50 50 45 45
Off, fastest)
Register-To-
Register Clock 16 16 20 23.2 58.8 58.8
Frequency (Max. MHz)
Quiescent
Power(W) 1.4 3.25 0.Q15 0.001 0.025 0.025

Packages 40DIP 84 PLCC 40DIP 68CJCC 48DIP 68 PLCC

44 PLCC 88PGA 44 CJCC 68 PLCC 68 PLCC 84 PLCC
44 PLCC 68PGA 68PGA
Process Bipolar Bipolar CMOS CMOS CMOS CMOS
114804 Technology Fuse Fuse EPROM EPROM SRAM SRAM

Shown above is data on several types of high-density EPLDs. Though the MegaPAL devices offer the most gates, they
are bipolar, fuse-based design, and so are not reprogrammable. .

7-7
ESD:
THE EleCtroniC System DeSign MagaZIne
Programmable Logic
Betters the Odds for
Bet-Slip Readers
by Cliff Dutton, GTECH Corp., Providence, RI

In countries throughout the world, the vitality of the on-line the sensor interface. Similar difficulties hindered direct
lottery industry is enhanced by seasonal and special comparison of achieved resolution. To accurately evalu-
promotional games. But new games require new bet-slips, ate these parameters, each sensor had to be designed into
and bet-slip readers must be able to accommodate fre- prototype readers; This involved driver and frame acqui-
quent changes in format. To accomplish this, program- sition clock signal generation.
mable gate arrays are replacing older, less flexible archi-
tectures. Because lotteries have no standard bet-slip size, as many
"standards" as possible need to be accommodated. Thus,
In the development of GTECH's Solid State Reader, many it was necessary to maintain flexibility in the format of the
existing technologies were evaluated, but they imposed target image.
unacceptable limitations on bet-slip processing, restricting
bet-Slip formats to rows and columns. Moreover, the
process of reading the coupons was dependent on com- PROTOTYPING A SYSTEM
plex moving parts, and the reading elements were ex-
The implementation of a prototype system had one goal:
posed to the external environment.
to prove the feasibility of recognizing handmade marks in
To maximize flexibility and minimize board space, Xilinx's an imaging system. Because the volume of readers is
(San Jose, CAl Logic Cell Array (LCA) was chosen forthe potentially high, component costs were a serious issue.
Solid State Reader. The LCA, touted by the company as
a "programmable gate array," represents a novel program- BOARD 1 MAIN CPU
mabie logic device that is notable for its reprogrammable COMMUNICATIONS
PROCESSOR LINK
architecture. This architecture provides flexibility through- MEMORY
out the product's life span, which allows on-line bet-slips to CONTROL LOGIC

be produced with marks in any arrangement. Each bet-slip

reader at every terminal can be configured on-line to read
any bet-slip from an active suite of eight different bet-slips.
BOARD 3 BOARD 2

Figure 1 shows three lottery bet-slips. Some of the CLOCK

ANALOG SIGNAL
GENERATOR
CONDITIONING
pertinent features of the European Lotto game slip (a) CIRCUITS AND DRIVER
CIRCUITS
include strobe marks along the top edge, the OCRB-3
characters (bottom center), and the name and address
field (bottom right). In the sample bet-slip from a lottery in
BOARD 4
the U.S. (b), there are no OCR characters or name and
IMAGE SENSOR BOARD
address information. However, there is an area from
which handwritten information must be extracted. Apart
from the different features, the aspect ratios of bet-slips
are not standard. Modern bet-Slip processing systems PRECISION OPTICS

must be able to read all of the different formats in many

aspect ratios. A format that forgoes the usual row and
column arrangement (c) is also depicted.

As there are no standard architectures or interfaces for

image sensors, GTECH evaluated many image sensor
approaches. However, direct comparison of sensor per-
formance could not be made in the application environ- Figure 2. The goal of developing a prototype bet-slip proces-
ment. For example, comparisons of sensor sensitivity at sor (shown above) was to prove that handmade marks could
the pixel level were impossible due to the differences in be recognized in an imaging system. Four boards were
sensor-interface electronics. If degraded sensitivities initially developed for this modular design: CPU/memory,
were evident, they could derive from either the sensor or clock-driver, analog amplifier, and sensor mounting.

7-8
 l:XIUNX
First, a working model was developed. To balance devel- In the initial design, flexibility did not exist. Even though
opment costs, a set of printed circuit boards based on TIL modularity protected the design from becoming obsolete,
logic devices was manufactured. Partitioned functionally, significant design alterations were required to accommo-
the board set supported modular design changes. Fourpc date different sensors. Because sensor clock signals are
boards were initially developed: a CPU/memory board, a multiphase, new clock generators would be needed for
clock-driver board, an analog amplifier board, and a sen- new sensors. Also, bugs were difficuH to find, and circuit
sor mounting board (Figure 2). board modifications were required to eradijate such bugs.

(a)

$1.00
• ~[jl~
•
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[i][iHl§l [i]@IJji]§l [i]@I~Jji] [i]@I~Jji] [i]@IJji][iJ

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[i]~~[i4] [i]~~[i4] [i]~~[il [i]~~[il [i]~[i4][il
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1!l[il[2l[il [i][il[il[il I!l[il[il[il [i][il[2l[il I!l[il[il[il
[i]~HHl [i]~HHl [i][iHHl [i][iHllil [i]@I[ij1il
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I I!mI!IJ I!mI!IJ I!mI!IJ I!mI!IJ I!mI!IJ I
(b)

II
(c)

Figure 1. Betting slips for lotteries come in varied shapes and sizes. (a) Shown here are lotto slips from Europe
and (b and c) the United States. Such variety in slip design must be accommodated in the developement of bet-slip readers.

7-9
Article Reprints

Finally, the target image aspect ratio was fixed because Semicustom and full-custom technologies would have
the clock generation 'circuits were implemented in hard- solved all the functional problems, but they lack flexibility.
ware. Because the development of the reader was ongoing, the
commitment to custom implementations was out of the
Aspect ratios of target images are important because only question. In addition, nonrecurring engineering (NRE)
necessary information on the image needs to be proc- costs were prohibitive and the devices could not be
essed. If the tjrget image is 2:1 and the imaging format is adapted to changing sensortechnologies or changing bet-
1:1, for example, then half the image is useless. A better slip reading requirements.
solution would mirror the aspect ratio of the target image
in the image format. Xilinx's LCAs permit a two-board set to be designed
without sacrificing functional modularity. In addition,
To overcome the limitations of hardwired logic and reduce counting algorithms can be implemented in the LCAs.
board space, several technologies were evaluated. These Finally, LCAs allow for a multiple-iteration development
included programmable logic arrays (PLAs), field pro- cycle.
grammable logic devices (FPLDs), semicustom and
fullcustom devices, and Xilinx's Logic Cell Array (LCA).
PUTTING A BUG TO REST
Size constraints indicated the necessity for semicustom of
full-custom integration, but traditional LSI technologies Initially, the TTL-based system was implemented infourpc
violated the flexibility constraint. Although full-custom was boards. However, it contained a bug. For every horizontal
attractive, design costs were prohibitive and did not permit line, an extra pixel pulse was being supplied. Although this
iterative development. Standard PLDs did not allowforthe was confusing to the eye, it was compensated for in
variety of register-like functions that the clock generation firmware. Because the redesign of the clock driver board
logic required. was a significant task, the bug was allowed to live through
many iterations of the development cycle. When the
Programmable logic arrays were attractive for some logic design of the clock generation circuit was translated into
functions and would have been the least costly. However, the LCA, it was a trivial matter to delete a single horizontal
PLAs did not allow the multiple register implementation clock pulse and put the bug to rest in an aftemoon.
necessary for clock generation. Thus, the counting algo-
rithms would have remained external to any integration of Using the LCA also provided the ability to vary the clock
the combinatorial logic. Also, although the PLA architec- generation circuitry to evaluate different sensors. Be-
ture would have saved board space, it would not have cause there is no standard architecture for solid-state
preserved the functional modularity achieved in the first digital imaging devices, clock requirements vary for differ-
implementation. Thus, it would have been impossible to ent sensors. In a standard imaging application, it might be
evolve a PLA-based system in response to changes in possible to source the appropriate support chips for each
sensor technology. Finally, any required changes would sensor from the manufacturer. But because development
have to be performed by field replacement. With over of the reader involved nonstandard video speeds in a
35,000 lottery terminals installed on five continents, this noninterlaced mode, it was impossible to use standard
was unacceptable. support chips. If it had been necessary to develop a clock
driver pc board for every sensor evaluated, it would have
Field programmable logic devices, an update of the been impossible to evaluate more than one sensor in the
PLA-style architecture allowing limited reprogrammability, development time. Because LCAs were used, varying
appeared to provide some of the flexibility needed. If the multiphase clocks could be generated for different sensors
problem were merely a straight combinatorial one, FPLDs under evaluation. Thus, the turnaround time for a design
could have been used. However, the difficulty in support- change in the clock generation circuits was reduced from
ing both registers and counting algorithms ruled out their one to Sixweeks to one day.
use.

7-10
 SINGLE MAIN BOARD
The Solid State Reader does not rely on standard video
COMMUNICATIONS
PROCESSOR LINK output. Thus, the 4:3 standard aspect ratio for broadcast
MEMORY
television is not a requirement. All image processing is
internal to the system. Real-time display of the image is
ANALOG never required. Therefore, only those areas of the sensor
CIRCUITS
that may contain relevant information need to be required.
Information-bearing areas of a bet-slip vary with the bet-
slip deSign, so it is helpfulto redefine the area ofthe sensor
that is acquired for processing.

SENSOR
Because the clock driver circuitry, the memory addressing
SOARD logic, and the frame-grabber logic are all implemented in
IMAGE SENSOR BOARD the reconfigurable LeA, it is possible to acquire only
certain areas of the image. As each sensor has different
horizontal and vertical clock pulses, this flexibility cannot
PRECISION OPTICS
be achieved in hardwired logic.

Figure 3 illustrates the current architecture of the Solid

State Reader. Because of the functions consolidated in
the LeA, the system was reduced from four pc boards to
two. This could have been done using other technologies,
114806 but they would not have preserved the functional modular-
ity of the system. The LeA-based design provides both
Figure 3. GTECH's Solid State Reader uses Logic Cell size reduction and functional modularity,
Arrays (LCAs) to maximize flexibility and minimize board
space. Frame·grabber, memory addressing, and sensor clock
driver functions are cOl)solidated in the LCA. By reducing the Reprinted with permission from ESD: The Electronic
number of chips, the required number of boards shrinks from System Design Magazine.
four to two.

•
7-11
 Using Programmable Logic
Cell Arrays In a Satellite
Earthstation
Dave Farrow, MIA-Com Telecommunications, Germantown, MD

Conventional programmable logic devices (PLDs) include 3 Mbls transmission rate. The earthstation product, called
several interesting variations of latch-based AND-OR an OPT (for On-Premises Terminal) is a "small-aperture"
plane architectures in various technologies, all of which satellite earthstation, permitting efficient employment in a
are useful for low-gate-density applications. Typically, a large number of remote locations, as illustrated in
PLD can replace five to ten SSI/MSI parts. Figure 1.

A newer digital logic technology with an array architecture Two main components comprise the OPT: an indoor unit
and flexible interconnection offers the programming flexi- and an outdoor u nit. The outdoor unit includes the antenna
bility of PLDs plus the gate density of low-end gate arrays. and associated radio-frequency equipment.
Architecturally, these devices have some Similarities to
gate arrays: they contain an internal matrix of logic blocks At the outset of the design process, the indoor unit was
and a ring of configurable I/O interface blocks. Unlike intended to be contained in a small chassis that cou Id
conventional gate arrays, each part is a standard off-the- support three standard-size boards. The boards originally
shelf unit that can be programmed by the user. The planned for the system included one board each for
configuration program is automatically loaded into an on- controlling data traffic, transmit functions, receive func-
chip static memory at power-up from either an on-board tions, and demodulation. However, the chassis provided
EPROM or an external source such as a floppy disk. space for only three boards.

Project goals included the use of an existing proprietary

THE EARTHSTATION SYSTEM custom chip design from a previous application. MIA-Com
also investigated whether the design could be fit on only
MIA-Com recently employed one of these "programmable two boards, by using a gate array. Board design itseH was
gate arrays" in the design of a satellite earthstation, in- driven by three primary factors: resource availability, cost,
tended to network commercial facsimile operations. The and schedule. Since reducing the number of required
network handles traffic at 56 kbls, multiplexed into 26 boards would reduce design time and keep product costs
channels and convolution ally encoded, yielding an overall lower, MIA-Com decided to go with the gate array.

EACH ON-PREMISES GROUPS OF ON-PREMISES UP TO 5,000 HUB

TERMINAL HAS ITS OWN TERMINALS SHARE A ON-PREMISES
TRANSMIT FREQUENCY RECEIVE FREQUENCY TERMINALS

Figure 1. Satellite System 1148 07

7-12
 OTY. DESCRIPTION ITEM port controller and handles base-band X.25 data. Due to
3 8-BIT SHIFT REGISTER 74HCT164
the use of semicustom and programmable technology, the
remaining three functions were all merged onto the other
6 4-BIT COUNTERS 74HCT163 board, which we call a "satellite channel interface" (see
4 DUAL D FLIP-FLOP 74HCT74
Figure 2).

2 OUAD2:1 MULTIPLEXER 74HCT157 We used a gate array for the transmit function, which
otherwise would have required about 70 chips. For the
1 OUADXOR 74HCT86
receive function, we originally planned to use an existing
1 HEX INVERTER 74HCT04 full-custom ASIC (previously designed by MIA-Com) for
forward error correction, and an additional 25 SSIIMSI
1 OUADNOR 74HCT02
parts for the receive logic. However, due to chassis
2 OUADOR 74HCT32 constraints, the high density of components would have
necessitated a multi-layer board for the initial design.
3 OUADAND 74HCT08
Furthermore, based on previous experience, the likeli-
1 OCTAL LATCH 74HCT374 hood of changes in the design specification was too high
to risk a custom or semicustom solution for the initial
1 OCTAL BUFFER 74HCT244
design. Therefore, we originally planned to produce the
251Cs high-density boards in quantity and to reduce the cost of
the system at a later date, by first transferring the receive
Table 1. Standard Off·the-Shelf Equivalents to the Logic logic into a gate array and then replacing the expensive
1148 08 Contained In the LCA. high-density four-layer board with a tWO-layer board.

While the design criteria were being prescribed and board-

The completed design employs a full custom IC, a gate level functionality was being determined, we also investi-
array, and programmable logic, and subsists on only two gated the newer programmable gate-array technology.
boards. On one board, an Intel processor acts as a traffic- The programmable part, the Xilinx Logic Cell Array (LCA),

TRANsMmER

ADDRESS ADDRESS

a:
o
f/)w

f:l~
g~
a: w
a. ...
Oz
a:-
o
:iii

KEY !TIl LOGIC-CELL ARRAY

o FULL-CUSTOM CHIP
•
o GATE ARRAY

114809 Figure 2. Block Diagram of Satellite Channel Interface.

7-13
Article Reprints

UNIQUE WORD SENSE

STATE
MACHINE
(4 STATES)

15
::;~
0:::>
tt:o
LLO
::;
W
0

a:
0
::;o(/)
r'
DATA

MAG
DATA

TPP
DATA

Oa:(/)
a:O w
LL-g
::;a:
a.
{ WR
RD
DEMUX-SGN DATA

DEMUX-MAG DATA

KEY: [j DEMULTIPLEXER

[j DESCRAMBLER
DEMUX-CLK
Iffil TIME-DIVISION MULTIPLEXER
(SYNCRONIZATION CIRCUITS)
1148 10

Figure 3. A Schematic of the Digital Systems Incorporated into the LeA.

is architecturally similarto a gate array and is supported by in-circuit emulator for debugging.
a PC/AT-based workstation.
Ouroriginal schematic was based on conventional LS and
We determined that the internal organization of the LCA HCT parts; it included JK flip-flops and large counters
fitted the design requirements of the receive function. (implemented by cascading common 4-bit counters),
Specifically, the LCA provides many more flip-flops than rather than gate-level elements. Since that method of
other programmable logic devices, so that one chip con- design was inefficient for the LCA, we redesigned the
tained enough functionality for our needs. Further, the receive circuit at the gate level and then implemented it in
LCA provided the required density savings, and its repro- software via the cell array editor.
grammability obviated the risks associated with late engi-
neering changes. When engineering management was Using an LCA reduced the amount of hardware overhead
presented with the design alternatives, we decided to normally associated with LKS and HCT technology. It was
prototype a reduced portion of the receive circuit and thus not necessary to waste control inputs, to cascade count-
evaluate the reconfigurable Chip. ers, or to determine whatto do with unused bits of multi-
plexers. In our design, 25 SSI/MSI gate-equivalents did
To implement the design, MIA-Com acquired the Xilinx not even use up all the resources available in one LCA.
XACT PC-based LCA development system. The system Table 1 indicates the parts that we actually employed in the
includes a macro library, with some of the required logic present design. Putting these functions in the LCA re-
already defined. After several days of experimenting with sulted in an 88% utilization of the internal cells, and a 60%
the design tools, it took us one day to enter and only two utilization of the I/O cells. Thus it still remains feasible to
hours to debug the design. We uses Xilinx's XACTOR add further functionality to the system, with no PCB

7-14
 I:XILINX

changes. We plan to do so in the future. Figure 3 is a The fourth state is entered every time a unique word is
schematic of the circuit placed in the LCA. Since the missed; the system stays in the fourth state until the unique
design is not 110 limited, there was no necessity to multi- word is found or is missed 11 consecutive times. If the
plex any of the input or output lines; but additional logic unique word is found, the system returns to state three; if
could have been added, should 110 multiplexing been it is not found after 11 attempts, then the first state (the
needed. Note also that the descrambling circuit can easily search mode) is initiated again. This method of operation
be reconfigured, or made more complex. Changing the ensures that the demultiplexer will remain locked even in
descrambler can be achieved merely by reprogramming the presence of random bit errors in the data stream.
the LCA.
After the unique word is detected, the receiver locks onto
One criticism leveled againstthe LCA is that it requires 12K the data. The LCA chip then de scrambles the data stream.
bits of storage space to program the part during power-up. The data is originally scrambled by the transmitterto place
However, in our deSign, a 27C64 EPROM (used for a look- a fairly equal number of ones and zeros into the transmit-
up table) was already on the board. A portion of this ted carrier. If this is not done, the transmitted carrier may
EPROM was available to store the LCA configuratic:>" not contain an even distribution of spectral components,
program at no additional cost. Since the 12K bits of which makes it difficult for a demodulator to acquire the
storage space are used to program all the RAM cell carrier. The descrambling process is. merely the reverse
locations in the LCA, adding furtheffunctionality to the of the 9-bit scrambling procedure.
LCA would not require more storage space. .
A single channel is isolated from the others by demultiplex-
ing the descrambled data stream. The demultiplexing
ARCHITECTURE function is performedthrough a pair of counters that count
the bits between unique words and tell the demultiplexer
From the OPT, transmission is executed in the SCPC when data is available. .
(single channel per carrier) mode. All scrambling, encod-
ing, and error-code generation are performed by Once the incoming data stream has been descrambled
MIA-Corn's proprietary transmit gate array. The gate array and demultlplexed, it moves on to the MIA-Com proprie-
contains registers, allowing it to be programmed to. trans- tary convolutional decoder, a custom chip where error
mit in different schemes and protocols, including scpe detection.and correction is done on a per-channel basis.
mode. . . Decoded data is passed on to.a microp~sor forda:ta
extraction. .
a
The qPT' receives' TDtvI (time <fiViSiO~; multiplexed)
bitstre~m coJilpOsec;l of 56 kb/s data ch~n'1~IS in a mOdu- TeSTING THELCA
lated 3cMHz carrier. The bitstream contains a UW (unique
word), anddataand.pl:!:fity bits)or each channel III each To test the TOM synchronizer, the LCA wasloaCJed via the
frame .. The received carrier is demodulated by analog Xilinx in-circuiteJilulator and set into the test bed. We
circuitry on the SCI, which passes the c;ligital bitstreamto tested with a satellite Simulator and found one deSign
the LCA. . error. Both isolation and remedy of the fault were simple
to perform, due to the reconfigurability' of the part. 'Fault
To isolate the .UW and lock onto the data, the LeA contains location was eased by choosing internal test' nodes and
several counters and astate machine,configured in TOM connecting them to I/O pads. This' technique made it
sY!'lChronizer. The state machine controls.h.esynchron- possible to find the fault very quickly. '
iztion algorithm,~hich manipulates the framElS.
a
By u$ing satellitesimulatorwe were able to Insert errors
The TOM synchronizer moves betWEl~~ four states (see into.thedatastream. We measured the time to lose sync
Figure 4). The first state entails acquiring "~;ync" by and the time to acquire sync, anddetermine<Jthat the
recognizing the unique word in the unsynchronized data ripple counterWas a little too slow forthe reqliired function.
stream.. Otlce the. unique word is acquired without errors, Sillcewe were using an in-circuit ernulatQr,itwa:s'~ery
the sElCOnd state occurs.' .7[he circuit verifies "sync" by .easy to' reprograrnthe device. After the' design was
detecting the unique word again one frame later. in. the debugged, we left the'simulatof(>n-Ifne for a wf;leK to
bitstream, Upon second d.etectlol),tt19 circuit,s qonsid- ensure a thorough test of the Xilinx part under operational
ere.d in sync; and the synchronizer shifts to the third stat~ conditions: Our concern was how well the lCA:would
the syncstat~heredataarEi,anowed to peoce.ed as long retain its configuration, since this information is stor~d by
as the system detects at least one uniqueword in every 1.1 RAMc~lls. HOV'f,ever, in our. environment,it performed
frames. flawlessly.

7-15
Article Reprints

UNIQUE WORD UNIQUE WORD

MISS >1 DETECT

UNIQUE
WORD MISS

UNIQUE
WORD DETECT

UNIQUE UNIQUE
WORD MISS WORD DETECT

114811

Figure 4. State Machine for the Time·divislon Multiplexer.

OPEN·END I;)EVELOPMENT basic digital circuitry. For example, designers must be

able to recognize the worst-case timing scenarios of their
Late into the design cycle we began to add additional networks. Delay and system-speed considerations can
planned functions to the LCA. Because we knew we could now be checked with the Xilinx Simulator, but atthe time of
add these extra features, we finished the PCB layout and our deSign, the simulator was still in beta test; we calcu-
ordered PC boards without waiting for the final design. lated the circuit behavior with preliminary timing software.
Then the process of adding putting functions into the LCA Since then the simulator has been revised and its present
was begun. version would have spotted our timing error.

Normally this. time would have been used to design a test Rather than packing complete deSign into the front end of
fixture. Instead, another LCA design was created to an ASIC development, as is required for conventional gate
support a test implementation. Before the PCB was arrays, the LCA offers the flexibility to indicate roles forthe
delivered, the test fixture simulating the system was built, part. Designers can specify the lID pins for the LCA then
primarily around the second Xilinx part. In the process of send the PC board to fabrica\ion. While the board is in
building the fixture, we discovered an error in the PCB fabrication, designers can build into the LCA the gate-level
layout, even before it was delivered. It was possible to fix logic they want and continue to make changes up until, and
the error by reconfiguring the LCA. even after, the PCB is delivered.

When the board was delivered, a new version of our logic After final product delivery, the on-board logic can still be
design had been implemented in the Xilinx LCA, including reconfigured to match specific customer needs-without
the demultiplexing and descrambling functions. having to cast custom silicon for a few dozen units or
changing the PC artwork. Great NRE savings are passed
back to the customer. In summary, the LCA has proved to
CONCLUSIONS
be an extremely efficient, useful, and cost-effective exten-
The flexibility of the Xilinx LCA lowers design costs, sion to our semicustom design capabilities.
reduces project schedule risks, and reduces inventory
risks. Using the LCA does not requir~ much design Reprinted with permission from VLSI System Design.
sophistication, but rather a good general knowledge of

7-16
ESD: Faster Turnaround
for a T1 Interface

by Carl Erite, Teltrend Inc., St. Charles, IL

Important design considerations for an interface system to design requirements-high integration, high density, high
a digital T1 network (which carries voice, data, video and performance,low cost, low risk and quick time-to-maiket.
fax traffic at rates up to 56 Kbytes/sec) include conserving
board space, improving throughput and reducing power The Xilinx devices implement a digital phase-locked loop,
consumption. The user interface is achieved via a conven- as well as the T1 transmilterand receiver. A Hitachi
tional four-wire loop providing independent transmit and microprocessor provides overall intelligence to handle T1
receive capabilities. In designs that Teletrend Inc. initially Controls, network code manipulation and other tasks.
conS.idered for a single;.user T1 interlace; 5.000 gates of
conventional SSIIMSI glue logic were to be integrated The dual digital phase-lock loop provides the key function
using two custom gate arrays. However, a short develop- of the system. Data on the user interface is encoded with
ment cycle and low market risks were also desired. This the clock signals, a process that may occur at various
led to a search for an aHetnative to th time-consuming send/receive data rates. Data extraction from the user
process of casting two gate arrays. interface must be phase-locked and, at the same time,
data must by synchronized with the T1 network clock. A
Upon completing the initial circuit deSign, a breadboard Xilinx LCA implements the phas!,-Iocked loop that syn-
was built using CMOS SSIIMSI logic components. After chronizes both the interface and the T1 network.
the breadboard was working, integration path decisions
were needed. Instead of. hard-tooling two custom gate The second LCA transmits data onto the T1 network.
arrays, designers detennined that three standard, pro- Here, data transmits serially at 1.544 Mbits/sec in one of
grammable Xilinx L?gic Cell Arrays (LCAs) met all of the the 24 assigned time slots. A unique data word to be

RECEIVE DATA AT BAUD RATES FROM TRANSMIT· r----

1.2K TO 56K ARE PI1ASE·LOCKED TO DATA
THE RECOVERED BAUD RATE CLOCK AT 1.544 I
AND TO THE T1 NETWORK CLOCK. MBlTSiSEC I
T1
TRANSMITTER
I
RECEIVE DATA
DUAL PI1ASED· I
lOCKED I
LOOP I
STANDARD 4 WIRE FOR I
USER INTERFACE RECEIVER
FOR SUBSCRIBER
LOOP SERVICE ------- T1 NETWORK CLOCK i
LOGIC TO I
TRANSMIT I
TO USER I
TRANSMIT DATA
I
I
I
I
I
I
I
RECEIVE I
DATA
AT 1.544 I
T1 RECEIVER MBITSISEC I
WITH a-BIT
r--
CONTROl
MICRO-
PROCESSOR
CRCERROR
CORRECTION ,
I
L ___ _
T1 SWITCH
1148 12 WITH ONE
ASSIGNED
TIME SLOT
Figure 7. Teltrend's digital TI interface is built around three user-programmable Xilinx Logic Cell Arrays in lieu of two conventional
gate arrays. One LCA implements a dual digital phase-lock loop around four-wire loop; other LCAs form both the transmitter and
reciever logic circuits, including error correction.

7-17
Article Reprints

transmitted is held in the LCA while logic synchronization higher performance in critical timing paths and higher
determines the start 9f the first time slot or the beginning overall device utilization. In all three designs, LCA logic
ofthe data frame. The assigned time slot is found by resource utilization exceeded 95% ...
counting titne slots from the start of a complete frame.
After locating the assigned time slot, data is transmitted All three deSigns are flip-flop intensive,involving multiple
onto the T1 network. counters, shHters, registers and other memory-oriented
functions. The LCAs provide more flip-flops per. device
A third LCA, complementary to the transmitter function, than any other programmable logic alternative. Only a few
receives data. It also furnishes complete error correction simple8-blt.registers were implemented externally with
for incoming data. Time-slot detection logic dete.rrnines octal devices. Next-generation designs will. use Xilinx's
the start of data for the assigned ch~nnel. Serial data compatible higher density devices to achieve greater logic
comes from the T1 network. After the LCA performs 8-bit density in the same socket.
error correction, the data passes to the processor and user
interface. Overall, the ability to enter the original design using the
Xilinx LCA XACT design system ensured that all the
The first iteration of the design was extrpcted directly form integrated logic functioned as desired before the part was
the CMOS breadboard schematics using the Xilinx XACT placed in the system. With a conventional gate array, the
system running on an IBM PCIAT. The working design for design might still be waiting for silicon, since turnaround
the first device was completed in two weeks, with some times for production quantity gate arrays typically range
time-critical elements moved off the Chip. Designs for the from 8 to 16weeks (production quantities).
second and third parts took about the same time, but Reprinted with permissiol1 from ESO: The Electronic Sys-
additional interaction during the design process resulted in tem Oesign Magazine. .

7-18
 Two, Two, Two Chips in One

By Tom Liehe, Principal Design Engineer, Test Instrument Division, Honeywell Inc., Denver:Colo.

Designers at Honeywell picked the RAM·based Xlllnx Errors on tape typically are caused by tape defects, dirt,
LCA for Its shon development cycle, and realized head clogs, etc. Because these error bursts can be
savings In board real estate through Its dynamic thousands of bits long, sophisticated ECC techniques are
reprog ram mablllty. . required. Initially, two basic circuits, using Reed-Solomon
algorithms and TTL technology, were designed. These
Advances in one technology often lead to improvements in were the ECC encoder and decoder.
other, mor'e dated design and manufacturing practices. A
recent example of this occurred at Honeywell during the The write portion of the circuitry (the encoder) uses a byte-
development of a high-capacity digital tape recorder. wide linear feed~back shift register (LFSR) to create a
58-byte code word form each 64-byte incoming message
Honeywell's original objective was to design the VLDS block. During operation, parity check bits are computed
(very large data storage) recorder, taking maximum ad- based on the data within a block of the message to be
vantage ofthe available analog technology currently being encoded. These check bits are appended to the block to
used in standard VCRs for home use. The recorder create the code word.
developed under this program uses digital rotary technol-
ogy to record large amounts of data on a standard VHS During decoding, the code words are checked for errors by
video cassette. It transfers data at a rate of 4 Mbauds, and regenerating the parity bits which are then compared with
is able to store 5.2 Gbauds of information on a single BHS the check bits. If they match, it is assumed that no errors
tape. Its major planned application is in capturing and have occurred. If they do not, the pattern of mis-matches
storing digital medical images, such as those produced by (called the syndrome of the error) is used to compute the
a CAT scanner. corrected form of the message block.

When this recorder was in the prototype stage, it became The ECC decoder (the read circuit) required a partial
apparent that the addition of an error-correction circuit syndrome generator and the solution of a set of simultane-
would significantly enhance system performance. This ous non-linear equations to determine error locations and
requirement dictated the design of an entirely new and values. ThiS error-determination step is performed by a
major logic circuit to accomplish the desired error correc- special-purpose processor with a microinstruction se-
tion. quencer,a finite field arithmetic unit, two discrete registers
and an eight-word memory. The correction step is then
Design of this circuitry would not normally be a problem, accomplished in circuitry whereby the error values are
but at this. stage of development, there were several exclusive-ORedwith the message althe address given by
challenges. First, the design allowed almost no circuit the previously computed error 10caUons.
board space for addition ofthe error correction code (ECC)
circuitry. Second, very tight deadlines were being faced if Using wrapped-wire t~cliniques, a working prototype of
the promised delivery date was to be met. the ECC circuitry was developed. However, it was quickly
recognized that the long leadUme required to design and
The entire system was housed in a 19-inch-wide by fabricate a factory-programmed gate array to replace this
20-inch-deep rack-mounted cabinet. The cabinet already prototype TTL cirCUit was not practical with the tight
contained eight separate circuit boards, and there was delivery schedule.
room enough for only one additional board to incorporate
the ECC circuitry. Space was at a premium. The goal was An option ,considered, but not chosen, was to design and •
to design and manufacture a 10-12 corrected bit error rate fabricate a conventional gate array. The considerable
circuit that could be contained on one circuit card. The design time required, together with the inherent risks
targeted time for completion of this work was tnree associated with masking and manufacturing a custom
months. logic circuit, made this an unattractive alternative.

7-19
Article Reprints

XILINX'S LCA ANOTHER BENEFIT

Finally, the search for an alternative solution led to the Another significant. benefit derived from the use of the
discovery of a programmable gate array known as the Xilinx LCA was reduced power consumption. The original
logic cell array (LCA) , designed and manufactured by bipolar IC design consumed approximately 12 Wof power.
Xilinx Inc. (San Jose, Calif.). The LCA is a standard, off- Through the use of CMOS technology, the replacement
the-shelf device that is custom configured to the LCA consu mes only 50 mWof power. It should be pointed
customer's requirements by means of the Xilinx develop- out that the bipolar version was capable of operating at
ment system. This development package consists of a .a much higher clock rate than the LCA. However, the clock
personal-computer-based software system combined rate used this particular design was only.2 MHz. The
with an in-circuit emulator. speed of the LCA was, therefore, adequate for the VLDS
application.
Use of theLCA seemed to be the ideal solution to the time
constraints. SO,a Xilinx XC2064 LCA was sected. In this Because the required logic circuitry was already designed
device, any logic function having up to four variables can and tested, the development of the configuration program
be implemented in anyone of the 64 configurable logic for the LCA went very smoothly. It took only two days to
blocks (CLBs). Optionally, results can be stored in either configure the circuit using the Xilinx XACT LCA develop-
a latch or a flip-flop. Thus, implementation of the design ment system running on a standard, IBM-compatible per-
can be constrained by a fixed set of standard logic ele- sonal computer. The primary effort involved was the
ments. partitioning of the logic to match the capabilities of the LCA.

The I/O pins of this device also can be configured as For a regular, repetitive design, a small portion of the logic
registered inputs. The large number of flip-flops, plus the was defined. This portion was then copied .and minor
ability of each CLB to function as four-input exclusive- modifications were made to complete the design. The
ORs, made this LCA ideal for ECC circuit implementation. byte-oriented nature of the RS ECC circuitry lent itself to
easy entry. Starting with tables showing the bits to be
exclusive-ORed, the entire circuit was entered in a few
MULTIFUNCTION CAPABILITY hours.
One of the real benefits of this LCA is its multifunction The software simulation capability, which enabled the
capability. The capability of performing a number of modeling of physical delays and logic functions, resulted
functions with the same device provides optimum utiliza- in a very high design confidence factor before the first
tion of circuit board space. This was a real bonus with the hardware checkout. The simulator provided both tabular
VLDS recorder. At any given time, the VLDS operates in output and logic analyzer style waveforms, which aided
only the read or the write mode~t is never required to do .considerably in the visualization of the circuit perform-
both simultaneously. Consequently, the same LCAcouid ance. A high-level language program was used to gen-
be reconfiguredelectronicalfy to perform one function in erate expected results of the encoder, and to perf9rm
the write mode, and a completely different fUl1ction in the partial syndrome generator simulations. This greatly
read mode. This versat1lity eliminated the need for two aided the evaluation of the simulation output.
separate circuits, and thereby conserved space.
By using the in-system emulation feature, configurations
The LCA has a usable density of 1,000- to 1,SOO-gate were. loaded directly from the PC to an LCA mounted in
equivalents, and is capable of replacing up to 75 SSI/MSI the target system; Thus, the usual step of programming
devices, five to 15 PALctype devices, or some combination an EPROM from which the LCA can boot itself was elimi-
of both. Inthe VLDS, the entire ECC en.codel' and the nated. Initial design Checkout of the ECC circuitry was
partial syndrome generator portion of the ECC decoder performed using the emulator connected to the wrapped-
wererepJaeed by the LCA. The initial encodercircuitused wire board containing the diserete IC version.
eight identical PALs, each of which implemented a 1-bit
slice of the Shift register, and four PROMS. The original There was a problem with the encoc;ler circuit that was
partial syndrome generator design useclsix PALs and four delaying data for an extra byte. Correcting this problem
74LS374 tri-state octal flip-flops to .store the four syn- required re.moving the input flip-flops or) the LCA. The
dromes. Thus, the LCA replaced a total of 14 PALs, four entire process ofreentering the LCA editor. removing the
2S6k x 8 PROMs and four 74LS374s, or a total of 22 mouse and reloading the new cOnfiguration took no more
20-pin Dips; than five minutes.

7-20
 E:XIUNX

Compared with the time required to rework any other type using equivalent discrete ICs. And finally, the ability to
of hardware, the LCA is the only way to go. Also, taking into perform design entry, simulation, emulation and in-system
consideration the high costs associated with reworking a testing through the software development system facili-
factory-programmed gate array, or even a semi-custom tated quick and easy implementation of the user's ideas.
PLD, the LCA technology is an extremely cost-effective
alternative. Today, the Honeywell VLDS offer error correction as
powerful as most major computer tape subsystems. It is
In summary, the Xilinx part was well suited for our applica- ideally suited for the newly developing imaging technolo-
tion because of its high flip-flop count and its ability to be gies used in electronic office documents, advanced geo-
configured in exclusive-OR trees. Additionally, its capabil- physical analysis and computer-aided graphic arts. With-
ity of being electronically reconfigured while in the system outthe Xilinx logic cell array however, Honeywell could still
(when switching from write to read) offered significant be waiting for a custom gate array.
savings.
Reprinted with permission from Electronic Engineering
Further, power consumption was much lower than when TImes.

•
7-21
ESD:
THE Electronic System Design Magazine
LeA Stars in Video

by Rusty Woodbury, Interactive Educational Video, Salt Lake City, UT.

Reprinted with permission from ESD: The Electrical Sys- mines howto increment the counter. All of these functions,
tem Design Magazine. plus logic to generate the read/modify/write cycle timing,
are implemented in a single LCA that replaces nine MSI
The market for tools and overlay products for video pic- parts, four of which are PLDs.
tures generated from laser disks is in its infancy. Appli-
cations for this emerging video-based technology can re- Two more LCAs implement a three-bit ALU. This tech-
quire high resolution and high performance, and the wide nique achieves ultra-high-speed screen writes for both
variety of video disk players employed means that prob- horizontal and vertical lines. For many applications, these
lems associated with varied noise characteristics must be are the most common lines drawn, so a special control bit
overcome. What works with one particular brand and is used to simultaneously modify pixels. Horizontal lines
model in the factory may falter with another brand in the can be written at 14 Mpixels/sec instead of the normal
field. 2 Mpixels/sec-a seven-fold improvement. Though more
logic could be placed in these two devices, a bit-sliced logic
The Xilinx Logic Cell Array (LCA) helps to solve the approach permits continuous enhancements. Moreover,
problem of meeting different system requirements be- a board layout can be defined at the beginning of the
cause the device elevates hardware to the same level of product cycle while logic enhancements are made inter-
programmability as software. Before the LCA, once a nally in the LCA. Nearly 30 SSI/MSI devices were inte-
design had been committed to hardware, revisions to the grated into the LCAs.
design could only be implemented via software changes.
A fourth LCA fully implements the graphics engine. To
Interactive Educational Video (lEV) has implemented read out data to the screen, scan counters pOint to mem-
three separate designs and logic replacements with the ory. A shift register serializes at a rate of 14 Mpixels/sec.
LCA. These functions reside on IBM PC expansion cards, USing traditional MSI devices, these functions require
where space limitations would ordinarily preclude such a about 10 chips.
design. Although application-specific video ICs could
perform similar functions, they cost more than the LCA and The second design fabricated by lEV is a graphics con-
offer lower performance. troller (Figure 6). Using an external genlock IC, the LCA
relies on an NTSC composite sync signal to generate
The first application is a graphics engine that uses four timing signals forthe CRT display. Instead of using PLDs,
LCAs. Here, the LCAs replace over 50 SSI/MSI chips, lEV uses the LCA to implement digital counter and timers.
including four traditional programmable logic devices The result is higher performance and reduced complexity.
(PLDs). The previous generation board has only half the function-
ality and demands four times the board space. To further
One LCA functions as the address generator for the video reduce complexity, the same hardware can be used with
memory. By relying on a pair of high-speed counters to a different configuration program to match a particular
locate horizontal and vertical coordinates, memory write video disk player's noise characteristics. Withoutthe LCA,
functions (which implement line drawing) can perform at this design needs eight PALs plus 12 to 15 MSI devices.
high rates. Given the slope, starting point and length of
a line, the logic simply increments counters that point to In another lEV design, a PC serial port emulator integrates
video memory locations. Scanning and writing to the a subset of the IBM PC serial port functions onto the
screen are interleaved. The data written to memory graphics card, making an IBM serial card unnecessary.
corresponds to a particular color and, by simple incre- With the given space restrictions, this implementation
mental additions to the slope of the address pOinter count- proves particularly cost-effective. Seven PLDs are re-
ers, powerful line drawing functions are easily imple- quired to match this design.
mented.
Reprinted with permission from ESD: The Electronic Sys-
Important to the design is the decision logic, which deter- tem Design Magazine.

7-22
 E:XIUNX

XC206.4 LOGIC CELL ARRAY

GRAPHICS
ADDRESS
AND -~-..j OVERLAY
VIDEO
CONTROL
DOT
CLOCK

COMPOSITE
SYNC TV
INPUT CAMERA
EXTERNAL SYNC
COMP~~~~ - - - 7 - - - -.....- - - - - . . j GENERATOR
INPUT
VD HD

14.318 MHZ
INPUT

FROM 3301 -'--~--I

\---=-,.,. HB

I
1---;,-. BFW

\---..,.c.----,.,:--'"+ GVB'

POSITION I--~_GHB
DETECT,

114813
II
FigureS., IEVimplementatedari nelligenf GraphICS Overlay Controller.micropr6cessor peripherafwith one XG2t:l64logic Cet!·'
Array, replacing eight PALs and 12 MSI devices. Th.e controller generates all timing for a video graphicsoverfay by deriving the
, necessary timin~ from the underlying video disk~giiaf.
 Taking Advantage of
Reconfigurable Logic
An abbreviated version of this paper was published in the High
by Bradly K. Fawcett, Xilinx Inc., San Jose, CA Performance Systems Programmable Logic Guide, 1989.

The availability of programmable logic devices based on suit is smaller, more powerful, less expensive, and more
static memory cells now allows the implementation of reliable systems. As an added benefit, use of reconfig-
"soft" hardware-hardware whose functions can be urable LCAs simplifies hardware design and shortens a
changed while resident in the system. When using most product's time-to-market.
current IC component technologies, hardware is indeed
"hard"; once a given logic function is implemented in
hardware, changing that logic is difficult, requiring modifi- RECONFIGURING FOR SYSTEM DIAGNOSTICS
cations to printed circuit board traces, the addition or
replacement of components, and other costly measures. System self-diagnostics can be implemented by using
However, with static-memory-based programmable logic, programmable gate array configurations dedicated to
changes can be made to a system's logic functions simply testing functions. When the system is powered-up or
by reconfiguring the programmable logic in the system. placed in a test mode, its programmable gate arrays are
This capability can lead to significant advantages for the configured with logic functions dedicated to testing other
system designer. These include both product-related circuitry in the system. Once the testing is successfully
benefits, in the form of smaller, less expensive, and more completed, another configuration program is loaded into
reliable systems, and design-related benefits, such as the programmable gate array to implement the actual logic
increased design flexibility, decreased risk, and faster of the particular end application intended for that system.
design cycles. Typically, very little additional logic is required to add self-
diagnostic functions in this manner (usually just some
Programmable logic devices capable of being reconfig- additional memory to hold the extra configuration pro-
ured in the system are available to system designers in the grams). Such self-diagnostic capabilities make products
form of programmable gate arrays from Xilinx, Inc. The easier to manufacture, increase system reliability, and
Xilinx Logic Cell Array (LCA) architecture features three simplify system maintenance, with little, if any, additional
types of user-configurable elements: an interior array of cost.
logic blocks, a perimeter of I/O blocks, and programmable
interconnection resources. Configuration is established Designers at Tellabs Inc. (Usle, IL) used this strategy in a
by programming internal static memory cells that deter- voice compression module, an optional unit for the
mine the logic functions and interconnections. The con- Crossnet 440 T1 multiplexer. The design includes two
figuration programs can be loaded automatically at power- XC2018 devices, 1800-gate programmable gate arrays
up or upon command at any time. Several available con- (Figure 1). During normal operation, one LCA provides all
figuration loading modes accommodate various system the interface logic for the board's microcontroller, RAM,
requirements. The benefits of a static-memory-based and system backplane, arbitrating accesses to the RAM
device include high density, high performance, testability, from the controller and the main system. The second LCA
and the flexibility inherent to a device that can be pro- contains most of the "glue logic" for the data compression
grammed while resident in a system. Designers have operation. However, both LCAs can be loaded with special
taken advantage of this capability in a wide range of diagnostic configurations. In the test mode, the first LCA
applications. connects the microcontroller to the RAM for memory
testing, and monitors controls on the system backplane.
The flexibility inherent in reconfigurable Logic Cell Arrays The second LCA can receive timing information from the
(LCAs) can be used to create systems that are also more microcontroller instead of the system backplane, verify the
flexible and, therefore, more powerful. Often systems will data paths, and check the contents of the 32K-bit EPROM
include multiple configuration programs for their LCAs, used to implement the code converter's companding algo-
allowing varying operations to be efficiently performed rithm. Actually, two different test configurations have been
with a minimal amount of hardware. For example, recon- generated, and other diagnostic LCA configurations are
figurable logic can be used to implement system sejfe planned for a future upgrade. All the configurations are
diagnostics, create systems capable of being reconfigured present in memory on the board; the microcontroller
for different environments or operations, or implement handles the downloading of LCA configuration programs.
"dual-purpose" hardware for a given application. The re-

7-24
ADAPTABLE SYSTEM DESIGNS system with logic that selects the appropriate configura-
tion at the appropriate time. Many different types of appli-
A similar use of reconfigurable logic is the implementation cations benefit from this approach.
of a single hardware design that can be adapted for varying
tasks or environments. In such systems, any of a number The Freeland Medical Division of Good Technologies Inc.
of potential configuration programs can be downloaded (Indianapolis, IN) used reconfigurable LCAs in this man-
into a system's LCAs to alter the logic for particular ner when designing a "frame grabber" board for the Cine'
applications or operations as needed. Hence, more func- View family of digital imaging systems. A mix of seven
tions are implemented with fewer components, hardware XC2064, XC2018, and XC3020 LCAs are used on this
design costs can be amortized over a greater number of AT-format board, providing graphics control and interfac-
systems, and design cycle times are greatly reduced. The ing a PC-compatible computer to the video output of
manufacturer could select the configuration program to be medical equipment such as ultrasound scanners and
included in the system dependent on the intended end magnetic resonance imaging systems. In orderto support
application or customer, or, alternatively, all the different different video formats from the varying types of medical
LCA configuration programs could be included in the instruments, several different LCA configuration programs

MICRoCONTROLLER

A
~t A
ADDRESS + CONTROL
"-
XC2018 256x4
v ~ v
DATA
LCA A "- RAM
~ v
CHANNEL
195301 SIGNALING

An LeA contains interface logic for the micro-controller, memory, and system backplane.

MICROCONTROLLER

"

fJ
XC2018 LCA
TIMING NIBBLE/
TIMESLOT /I "- TIMESLOT
AND INTERCHANGE
CONVERSION LOGIC
CONTROL

I'LAW
DATA
tJ
CODE
CONVERTER
LINEAR DATA
t
DSP
III
ROM
1953 02

A second LeA implements the glue logic for the data compression circuit.

Figure 1. LeAs in a voice compression system can be reconfigured to implement internal system diagnostics.

7-25
Taking Advantage of Reconfigurable Logic

are available for the LCA devices in the system. When logic consists of an 8051. microcontroller and a 3000-gate
system operation begins, the user selects the desired XC3030 LCA; four channels are implemented on each
video format (monochrome or RGB color, for example); card. Using a keyboard, the user can select from among
the appropriate LCA configuration program is then loaded three communication protocols for each channel: a Data
to match that format. Thus, one hardware design can Service Unit (DSU) interface, an Office Channel Unit
support virtually any video format, without having to in- (OCU) interface, or a secondary-mode OCU interface
clude customized hardware for each one. (Figure 2). A fifth 8051 processor controls the user inter-
face and the downloading of the appropriate LeA configu-
A similar scheme was used on Tellabs' channel interface ration programs.
cards forthe Crossnet 440 T1 multiplexer. Each channel's

.--- PARALLEL·TO-
SERIAL SIR
r--- 8-BIT SELF-
CENTERING FIFO
-
-
r-- CLOCK
f-IDATA
8051 XC3030 LCA

--
PROCESSOR

SERIAL-TO- 8'BIT SELF-

r-- CLOCK
'---
PARALLEL SIR r--------- CENTERING FIFO
r-- DATA

1953 03

DSU mode block diagram

~DATA+
,----. PARALLEL-TO-
SERIAL SIR
BIPOLAR
VIOLATION
GENERATOR
RETURN-TO-
ZERO
GENERATOR ~DATA-

8051
XC3030 LCA
PROCESSOR

~ SERIAL-TO-
PARALLEL SIR I+- TRANSPARENT DATA AND
CONTROL CODE TRANSLATER
~ 3-BIT
FIFO
~DATA+
I---DATA-
~CLOCK

1953 04
OCU mode block diagram

r---t
PARALLEL-TO-
SERIAL SIR
RETURN-TO-
ZERO
GENERATOR
I--
I- =: DATA +
DATA-

t I
8051
PROCESSOR
I
FRAME BIT
GENERATOR
I XC3030 LCA

~
FRAME SYNC
I RECOVERY

-
~-
DATA +
~ SERIAL-TO- 3·BIT DATA-
PARALLEL SIR FIFO
I+- - CLOCK

Secondary OCU block diagram 1953 05

Figure 2. By reconfiguring an XC3030 LCA, each channel in a multiplexer from

Tellabs can implement any of three communication protocols.

7-26
Reconfigurable logic can be used to adapt add-in circuit Several other applications involving the use of Xilinx LeAs
boards to the environment of a particular computer. In to implement adaptable hardware have been described in
such systems, configuration programs can be down- recent articles:
loaded by the host processor (from a floppy disk or
modem, for example), allowing simple installation proce- • Tektronix Inc. (Wilsonville, OR) employed an XC2018
dures and easy field upgrades. Several recently an- LCA for the printer interface logic in their Phaser Card
nounced personal computer products illustrate this capa- printer controller. 1 Interfaces to several different types
bility. Buffalo Product's (Salem, OR) More Memory mem- of printers can be implemented through reconfiguration
ory expansion card for PC/XT or PC/AT compatible sys- of the LCA.
tems employs a 1200-gate XC2064 LCA for the bus and
memory interface and control logic. An installation pro- • The FASTPACKET data multiplexer from Stratacom
gram analyzes system parameters (bus width, type of card Inc. (Campbell, CAl uses LCAs to incorporate its four
slot, available address spaces, etc.) and then loads the serial channel interfaces. 2 Different communication
appropriate configuration program to match the system's protocols can be accommodated through reconfigura-
requirements. Similarly, the Mach II/SE (Figure 3), an tion of ttie LCAs. A speCial configuration of the LCAs
accelerator board for the Macintosh II from Dove Comput- also provides for bit error rate testing without the use of
ers (Wilmington, NC), uses an XC2018 LCA for all its external test equipment.
interface logic; different LCA configurations are used to
support different memory sizes and speeds. The Reconfiguring an LCA in a graphics controller for a laser
MultiScreen card from Mobius Technologies Inc. disk system from Interactive Educational Video
(Oakland, CAl, a monitor interface board, includes an (Salt Lake City, UT) allowed a single hardware design
XC2018 LCA for controlling the video output. Different to be matched with various video disk players' noise
LCA configurations support different monitor types, allow- characteristics. 3
ing for variations in timing requirements and screen reso-
lution. As new monitors are introduced in the market, GTECH Corp. (Providence, RI) designed a lottery bet-
additional LCA configuration programs will be developed slip reader using LCA technology that can be reconfig-
and distributed on floppy disks. ured to accommodate variations in bet-slip size and
format without hardware alterations.4

Figure 3. The Dove Computer Mach IIISE includes a micro-processor, floating-point co-processor, memory, bus drivers, and an
LCA that holds all the interface logic.

7-27
Taking Advantage of Reconfigurable Lclgic

CONFIGURABLE TEST EQUIPMENT the test patterns and the pins of the memory device being
tested. Different LCA configurations are used for testing
In a similar manner, programmable gate arrays often are different types of memory devices. An extended vector
used to implement configurable test equipment, wherein memory option uses an XC2018 LCA as a FIFO buffer
different LCAconfigurations are used to program the same between the extended memory and the pattern control
hardware to perform varying types of tests. logic. Upon command, this LCA can be reconfigured to
create a cyclic redundancy code (CRC) checker used to
Innovage Microsystems (Calgary, Alberta) chose pro- verify the test patterns stored in the extended memory.
grammable gate arrays for test circuitry used in the Fluke
90 Series (John Fluke Mfg. Co., Everett, WA) and Inno- Designers of telecommunications test equipment have
vage Microsystems' own Tracer-4 series of microproces- also discovered the advantages of reconfigurable logic.
sor board testers. These portable test instruments facili- Three LCAs are used in the PC-based TC2000-B1
tate the trouble-shooting of microprocessor-based T1/PCM tester from LP Com, a Tektronix subsidiary
boards; testers are available for a number of popular (Mountain View, CAl. The LCAs provide clock and timing
microprocessor types (Z80, 8086, etc.). As shown in generationforthe receiver/transmitter, interface logic, and
Figure 4, an LCA provides interface and control logic bit error generation logic. The logic can be altered by
between a resident microcontroller and the unit-under-test downloading different LCA configuration programs to
interface card. An 1800-gate XC2018 LCA is used in the support several user-selected operating modes. When
8-bit series, and a 2000-gate ~C3020 is used in the analyzing DS1 lines, any standard framing mode can be
16/32-bit series of testers. Different configuration pro- selected (D1 D, D2, D3/4, or ESF). In DS1 bit error testing
grams are stored in the system's ROM during production, (BERT) mode, any AT&T standard or user-defined test bit
dependent on the type of microprocessor targeted for that pattern can be specified. The use of reconfigurable LCAs
tester, allowing the same basic hardware configuration for allowed the logic to be packed into just two boards; LP
all tester types. A keypad allows the user to choose from Com engineers estimate that the design would be at least
a variety of pre-programmed trouble-shooting modes; the twice as complex with traditional logic devices.
microcontroller downloads one of seven different available
configuration programs to the LCA, dependent on the type Sage Instruments (Freedom, CAl used a similar strategy
of test selected. Use of the LCA allowed Innovage in their Model 930A Communication Test Set, a general
Microsystems to increase the functionality of their testers purpose channel access test system. Four LCAs are used
while reducing the number of components by 49%, as to implement data interface, channel signalling, diagnos-
compared to previous models. tic, and microprocessor interface functions, respectively.
The LCA that handles channel signalling has two possible
Semiconductor Test Solutions (Santa Clara, CAl included configurations to support two different signaling formats,
reconfigurable logic in several optional units for their STS RBS (robbed-bit signalling) and DMI (digital multiplex
6000 and 8000 series of Sentry-compatible IC testers. For interface). The data interface and channel signalling LCAs
example, an optional memory test unit uses the XC2018 are both reconfigured to support bit error rate testing.
LCA to interface between the internal memory that holds

XC2018 UNIT·UNDER· r-..I'-'

~
~
/!
SYSTEM OR TEST
PROCESSOR XC3020 "-rI/ INTERFACE
LCA CARD TEST CLIP
L
'--
UNIT UNDER TEST

(ROM)
II II
CONFIGURATION
FILE #1
CONFIGURATION
FILE #2
. .. CONFIGURATION
FILE #7

MICROPROCESSOR BOARD TESTER

1953 06

Figure 4. In Innovage Microsystem's microprocessor board tester, an LeA is configured for the appropriate
microprocessor type and selected diagnostic test.

7-28
By reconfiguring a 3000-gate XC3030 LCA, an error- when writing data to the tape, and then reprogrammed to
correction channel designed by Wiltron Co. (Morgan Hill, perform a different function when reading from the tape.
CAl can support either of two error checking and correc- Honeywell's Test Instruments Division (Denver, CO) in-
tion (ECC) formats, one for Digital Data System (DDS) and corporated this scheme in their VLDS (Very Large Data
one for Adaptive Data Port (ADP) network configurations. Storage) recorder.5 An XC2064 LCA is configured to
The circuit is incorporated into several products, including perform error code generation in write mode, and then
Wiltron's Model 9966 Digital Services Test Unit for testing reconfigured to perform error code checking and correc-
DDS-like services. Use of the LCA also provides insurance tion in read mode. This type of application is especially
against evolving standards; new LCA configuration pro- cost-effective; about twice the logic would be required to
grams can be developed if standards for ECC formats and implement the same functions with traditional logic de-
network configurations change. vices.

A similar strategy can be used in the deSign of most logic

DUAL·PURPOSE HARDWARE analyzers, microprocessor in-circuit emulators, and simi-
lar test equipment. Each involves the monitoring and
In the examples sited above, programmable gate arrays control of nodes within the system being tested. In the
are reconfigured to implement internal system diagnos- "acquisition mode", the target system is active and a
tics, adapt a circuit to the external environment, or com- record of the target's activity is stored in a memory buffer
pletely change the functions of a system. Some logic called trace memory. Trigger and breakpoint logic speci-
designers have taken this concept one step further- fies when tracing begins and ends. A history of the sys-
programmable gate arrays are reconfigured as part ofthe tem's operation can then be read from trace memory and
normal operation 01 the system. displayed to the user, the "analysis mode". In an LCA-
based system, programmable gate arrays could be used
For example, at any given time, a tape recorder can either to implement the multiplexer, registers, and comparators
read or write, but it never does both simultaneously. of the trigger and breakpoint logic, interface to the system
Consequently, a programmable gate array within a digital undertest, and control the writes to the trace memory while
tape recorder could be configured to perform one function in acquisition mode. Those same LCAs could be reconfig-

ADDRESS "-

DATA
DATA

: TRIGGER
MEMORY " TRACE
MEMORY
INPUT ADDRESS v
SYSTEM AND GENERATION
CAPTURE BREAKPOINT
UNDER LOGIC + CONTROL
TEST LOGIC CONTROL
CONTROL
/1

CONTROL "
/1
CONTROLLER
PGA ~

ACQUISITION MODE
ADDRESS

DATA
DATA
/1
v TRACE
MEMORY MEMORY

II
ADDRESS 'I
USER
SYSTEM INTERFACE GENERATION
UNDER PGA CONTROL ..I\.,
CONTROL +
TEST CONTROL
CONTROL

" CONTROL
CONTROLLER
v
"
1953 07
ANALYSIS MODE

Figure 5. An LeA can be reconfigured to support both acquisition mode and analysis mode operations in a logic analyzer.

7-29
Taking Advantage of Reconfigurable Logic

ured to control reading trace memory and displaying its RECONFIGURABLE LOGIC EASES DESIGN
contents when in the analysis mode (Figure 5). For ex-
ample, Data I/O's MESA-1, an in-circuit verifier for LCA While not every system requires reconfigurable logic to
designs, uses LCAs exclusively to implement its logic implement its digital functions, the design-related benefits
(Figure 6). of static-memory-based programmable logiC apply to all
deSigns. The ability to reconfigure programmable gate
Intel's Development Tools Operation (Hillsboro, OR) used arrays resident in the target system significantly eases the
a slightly different tactic when designing a series of in- debugging process, reducing overall development time
circuit emulators for derivatives of the 80386 processor. and shortening the product's time-to-market. A download
The emulators contain six LCAs. Four of them comprise cable provided with the basic development system allows
the bus event recognition circuitry used to define and configuration programs to be downloaded directly from a
detect triggers and breakpoints; three of these are largely PC to an LCA device resident in the target system; the
filled with comparators, and the fourth holds the breakpoint actual download operation requires less than 1 00 millisec-
state machine. When preparing for an emulation, these onds. Thus, the designer can immediately check the
four LCAs can be reconfigured in the system, dependent results of design changes in the target system. Often,
on the type of breakpoints and triggers being specified. A design changes can be implemented and tested in just a
DMA channel is used to download the LCA configuration few minutes time. '
programs. A fifth LCA holds the bus interface state ma-
chines; as a future product upgrade, Intel deSigners may In essence, Xilinx programmable gate arrays provide a
generate another optional configuration program for that flexible means of "breadboarding" logic designs, as well as
LCA to add additional tracing capabilities. a cost-effective means of implementing the logic in the
final product. Temporary modifications to the logic, such
as routing an internal node to an otherwise unused I/O pad,
THE ULTIMATE RECONFIGURABLE SYSTEM can be quickly implemented for debugging purposes and
then removed from the production design. Devices are
A system composed entirely of programmable gate arrays reusable simply by downloading a new configuration.
could be configured to implement any given logic func- There is no lengthy wait for a custom device to be manu-
tions. This concept has been incorporated into a new ASIC factured, and no waste of components as with one-time-
design tool that provides real-time in-circuit emulation of
complex ASIC designs. The RPM Emulation System, from
Quickturn Systems Inc. (Mountain View, CAl, is a worksta-
tion-based design verification tool that combines auto-
matic ASIC netlist conversion software with emulation
hardware based on 9000-gate XC3090 LCAs (See
Figure 6). The RPM Emulation System can be configured
with up to four emulation modules with over thirty XC3090
LCAs each, allowing emulation of ASIC designs of up to
100,000 gates. Once the ASIC design is converted for
emulation, existing complex VLSI devices may be
internally connected to the emulation logic with
Component Adapter boards, orthe design may be plugged
into a target system with an In-Circuit Interface consisting
of cables, an active Pod, and ASIC Plug Adapters. The
netlist conversion software reads the netlist (a variety of
popular formats and libraries are supported), partitions the
design for programming each XC3090 LCA, places and
routes the design into the matrix of XC3090 LCAs, and
checks the timing to determine the maximum speed of
correct functional operation. The Control Panel user
interface on the workstation guides the designer through
the emulation set-up and provides the controls for the
integral Logic Analyzer and Stimulus Generator, allowing
quick access to any node in the design during debugging.
Thus, using the RPM Emulation System, a designer can Figure 6. The internal logic of Data 110's MESA-1 in-circuit
emulate and debug the logiC operation of any large digital debugger is implemented entirely in Xilinx programmable
design before committing to a custom implementation. gate arrays.

7-30
programmable solutions; there is not even the inconven- Buffalo Products' design of the More Memory board
ience of long erase times using ultraviolet lights, as with mentioned above. During testing of the board using vari-
EPROM-based logic. The designer receives nearly instan- ous manufacturers' PC clones, problems caused by in-
taneous feedback on the effects of design modifications. compatibilities in some PC models were corrected as they
Furthermore, since the LCA's configuration can be verified were found through reconfiguration of the LCA device.
in the target system, extensive simulation is not required;
typically, simulation is used only for critical timing path
analysis under worst-case conditions. FIELD UPGRADES SIMPLIFIED

The ability to implement easily modifications to the logic Similarly, field upgrades can be easily implemented
enables and encourages experimentation during the through changes to LCA configuration programs.
design cycle, resulting in better designs. For example, the Andromeda Systems (Canoga Park, CAl took full
use of Xilinx LCAs allowed GTECH Corp. to evaluate advantage ofthis capability in their Storage Module Device
different image sensors during the design of a betcslip Controller, a disk controller for LSI-11 and MicrolVAX
reader for the lottery industry.4 Since there are no standard systems. 8 The configuration programs for three XC2064
architectures or interfaces for image sensors, different devices are stored in EEPROM that can be altered using
interface logic was required for each sensor type. By a service port that connects directly to terminals or
incorporating the sensor interface logic in LCAs, a single modems. The interfaces to the disk, processor bus,
hardware implementation could be reconfigured for each service port, and cache memory are implemented in the
sensor type, allowing the sensitivity and resolution of each LCAs (Figure 7). Modifications to the logic, such as
to be measured under identical conditions. adjusting the caching algorithm to match the requirements
of a particular application, can be made without removing
The flexibility of in-circuit reconfiguration greatly reduces the disk controllerfrom the system; new LCA configuration
design risks. The inevitable last-minute bug fixes and programs can be sent to the controller us.ing a modem.
specification changes can be implemented by changing
an LCA's configuration program rather than altering the In many cases, compatible programmable gate arrays
hardware. MIA-Com Telecommunications (Germantown, with a range of densities are available in identical pack-
MD), for example, was able to correct an error in the PCB ages. (For example, the 2000-gate XC3020, 3000-gate
layout without changing the board by reconfiguring an LCA XC3030, and 4200-gate XC3042 are all available in 84-pin
used to implement the channel interface logic within a PLCC and PGA packages.) So if logic needs exceed the
satellite earthstation. 7 This flexibility proved critical during current LCA device, during either initial design or a product

PERIPHERAL
CACHE MEMORY
EXPANSION
1M BYTE DRAM
PORT

CACHE
ADDRESS
MAPPER

Q-BUS
INTERFACE SMD
INTERFACE

II
65C802 MICROPROCESSOR USER
SERVICE
PORT
STATIC EEPROM
RAM

1953 08

Figure 7_ In Andromeda Systems' SMDG disk controller, LGA configurations can be

downloaded to EEPROM through a modem port for easy field upgrades.

7-31
Taking Advantage of Reconfigurable Logic

upgrade (due to the addition of new product features, for SUMMARY

example), a higher-density device can be placed in the
same PCB location, with no modifications required to the The advent of programmable logic that can be reconfig-
circuit board. ured while resident in a system has freed the designer from
the "hard" nature of traditional logic ICs. With program-
The reconfigurable nature of the programmable gate array mable gate arrays, adaptable systems that adjust to
also allows for the design of its own in-circuit debugging changing environments or varying tasks can be created,
tools, such as Xilinx's XACTOR and Data I/O's MESA-1 and hardware design is simplified. New system architec-
(Figure 8).9 Similar in many ways to microprocessor in- tures that take advantage of reconfigurable logic will
circuit emulators, these sophisticated verification tools continue to emerge as programmable gate array densities
provide for easy, fast debugging and testing. Since con- and performance levels continue to increase.
figuration programs can be downloaded into an LCA at will,
LCA devices in the target system can be replaced or
functionally duplicated by an LCA device in an in-circuit REFERENCES
debugger; LCA activity can then be controlled and moni-
tored by the user. 1. Loring Wirbel, ''Tek Takes Color Printer to the Office,"
Electronic Engineering Times, Nov. 14, 1988.

2. David Smith, "User-Programmable Chips Take on a

Broader Range of Applications," VLSI Systems Design,
July, 1988.

3. Rusty Woodbury, "LeA Stars in Video," ESD: The

Electronic System Design Magazine, Feb., 1987.

4. Cliff Dutton, "Programmable Logic Betters the Odds for

Bet-Slip Readers," ESD: The Electronic System Design
Magazine, Oct., 1987.

5. Tom Liehe, ''Two, Two, Two Chips in One," Electronic

Engineering Times, Nov. 17, 1986.

6. Loring Wirbel, "Quickturn Offers ASIC Emulator," Elec-

tronic Engineering Times, Nov. 14, 1988.

7. Dave Farrow, "Using Programmable Logic Cell Arrays

in a Satellite Earthstation," VLSI Systems Design, April,
1987.

8. Jim Reynolds, "Building Tomorrow's Disk Controller

Today," Electronic Products, Dec. 15, 1987.

Figure 8. The reconfigurability of LeAs allows for the design 9. John Novellino, "Development Tool Trouble-Shoots
of their own in-circuit verification tools, such as the MESA-1 PGAs in the Target System," Electronic Design, Jan. 26,
from Data 110. 1989.

TECHOOC 1953

7-32
 SECTIONS

Index

1 Programmable Gate Arrays

2 Product Specifications

3 Quality, Testing, Packaging

4 Technical Support

5 Development Systems

6 Applications

7 Article Reprints

8 Index
 Index

Index ................................................................................................... 8-1

Sales Office Listing ............................................................................. 8-3

1962
 Index

abort .............................................................. 2-15, 2-67 DRAM controller ..................................................... 6-61

accumulator ........................................................... 6-26 EditNet ............................................................ 2-7,2-60
adder ...................................................................... 6-22 electrostatic discharge ............................................. 3-8
alpha particle ............................................................ 3-8 error correction .............................................. 6-61, 7-19
ASIC ........................................ ;................................ 1-9 FIFO ....................................................................... 6-50
Automatic Place & Route ....................................... 5-17 flat pack .................................................................. 3-18
bar code reader ...................................................... 6-59 frequency comparator ............................................ 6-41
barrel shifter ........................................................... 6-23 frequency counter ........................ 6-38, 6-41,6-42,6-44
battery back-up ............................................. 6-22, 2-27 FutureNet ............................................................... 5-38
BIOI ..... ,........................................................... 2-60, 2-7 in-circuit verification ............................................... 5-36
Boolean equations .......................................... 5-35, 6-7 initialization ................................................... 2-14, 2-66
buffers .................................................................... 2-10 input ............................................................... (see lOB)
bulletin board .................................................... 3-1.4-4 input protection ............................................... 2-27.3-8
burn-in .................................................................. 2-100 interconnect .................................. 2-7, 2-13. 2-59.2-60
busing .....................................................................2-11 lOB ........................................................ 2-3, 2-56, 6-14
carry generate, carry propagate ............................. 6-26 lOB timing ............................................ 2-42, 2-86,6-14
CLB ................................................................. 2-5, 2-57 latches .................................................................... 6-31
CLB timing ........................................... 2-40, 2-84, 6-16 latch-Up ..................................................................... 3-9
code conversion .............................................. ,...... 6-46 length count .................................................. 2~17,2-67
combinatorial functions ................................... 2-6, 2-58 library ..................................................................... 5-25
comparator ............................................................. 6-27 logic analyzer ......................................................... 6-67
conf.iguration ................................................. 2,14, 2-66 logic synthesis ......... ;.................................... 5-13, 5-34
configuration data .................................................. 2-16 long lines ....................................................... 2-11, 2-60
configuration memory ..................... 2-2, 2-55, 3-7. 3-11 macros ................................................... ;............... 5-25
configuration pins ................................................... 2-32 magic box ....................................................... 2-9, 2-60
cost .......................................................................... 1-9 majority logic .......................................................... 6-.24
counters ........................... 6-32-6-38, 6-41, 6-42. 6-44 MAKEBITS .................................................... 2-17, 5-21
crystal oscillator ............................................ 2-13. 2-62 MAKEPROM ................................................. 2-17.5-21
Daisy ................................................................. :.... 5-40 master mode timing ...................................... 2-45, 2-88
daisy chain ............................................................. 2-20 master parallel mode .................. 2-14.2-19,2-66,2-68
design considerations ............................................ 6-12 master serial mode .......... 2-14, 2-18.2"66,2-69.2-141
diagnostic ............................................................... 6-54 memory cell ..................................... 2-2, 2-55. 3-7, 3-11
direct inputs ............................................................ 2-1 0 memory requirements .............................................. 5,1
disk controller .........................................................;. 7-1 Mentor .................................................................... 5-42
DON E ............................................................ 2-23,2-72
download ............................................................ ,... 5-21
metastability ........................................................... 6-20
Micro Channel ........................................................ 6-57
III
8-1
Index

MIL-STD-883 ........................................................... 3-1 reliability ................................................................... 3-1

military .................................................................... 2-95 RESET ....................................... 2-15, 2-23, 2-67, 6-14
minimum specifications .......................................... 6-18 retention ................................................................. 2-27
modes ........................................................... 2-14, 2-66 Schema 11 ............................................................... 5-39
multiplexer ..................................................... 2-12, 6-23 schematic capture ......................................... 5-1 0, 5-37
OrCAD ................................................................... 5-43 self test ................................................................... 6-54
ordering information .......................... 2-29, 2-91,2-152, serial PROM ............................................. 2-139, 2-150
5-47,5-49 SILOS ...........................................................5-21, 5-33
oscillator ..................................... 2-13, 2-23, 2-62, 6-15 simulation ............................................................... 5-21
output ............................................................. (see lOB) sizing ........................................................................ 6-3
output inversion ........................................................ 2-4 slave mode ................................. 2-14, 2-20, 2-66, 2-71
output slew rate ........................................................ 2-3 slave mode timing ......................................... 2-47, 2-90
package dimensions ..................................... 2-50, 2-92 sockets ................................................................. 2-151
package pins .......................................................... 2-33 soft errors ................................................................. 3-8
packages ..................... 2-49, 2-101, 2-114, 2-128, 3-17 specifications ................................................ 2-37, 2-82
PALASM ....................................................... 5-13, 5-34 start-up ................................................... ,...... 2-17, 6-19
part numbers .......................................................... 2-49 state machine ................................................ 6-52, 6-53
pattern detector ..... ................................................. 6-45 subtractor ............................................................... 6-26
PC requirements ...................................................... 5-1 supply voltage ............................................... 2-26, 2-76
PC-SILOS .............................................................. 5-33 switch matrix ................................................... 2-9, 2-60
PDS2XNF .............................................................. 5-34 T1Interface ............................................................ 7-17
performance ........................................ 2-24, 2-74,6-16 temperature ........................................... 2-26, 2-76, 3-9
peripheral mode .......................... 2-14, 2-20, 2-66, 2-70 testing .................................................................... 3-11
peripheral mode timing ................................. 2-47, 2-89 three-state buffers .................................................. 2-12
phase comparator .................................................. 6-41 threshold ....................................................... 2-15, 2-71
pin description ................................... 2-30, 2-78, 2-140 tie option ................................................................ 2-17
pinouts .......................................................... 2-80, 2-33 timing ................................................... 2-40, 2-84, 6-16
PIP .................................................................. 2-8, 2-60 timing calculator .......... ........................................... 2-24
power dissipation .............. 2-26, 2-28, 2-64, 2-77, 6-16 timing, CLB ................................................... 2-25, 2-84
power distribution .......................................... 2-24, 2-64 timing, interconnect ....................................... 2-26, 2-75
power-down ......................................... 2-15, 2-27, 2-72 timing, lOB .................................................... 2-25, 2-86
power-on ....................................................... 2-15, 2-67 timing, PROM ....................................................... 2-145
preamble ....................................................... 2-15, 2-67 toggle frequency ........................................... 2-72, 2-23
prescaler ................... ............................................. 6-42 training course ......................................................... 4-7
process .................................................................. 1-14 TIL - MSllibrary .................................................... 5-44
PROM programmer ................................................ 5-46 video control ........................................................... 7-22
PROM programming ............................................ 2-142 wired-AND .............................................................. 2-12
quality ....................................................................... 3-1 XACT Design Editor ...................................... 5-19, 5-32
radiation ................................................................. 3-10 XACTOR ................................................................ 5-36
re-program .................................................... 2-23, 2-72 XNF2LCA ............................................................... 5-16
readback ....................................................... 2-22, 2-72 XNFMERGE .................................................. 5-17, 5-34
readback timing ............................................. 2-47, 2-90 XNFOPT ....................................................... 5-16, 5-34
reconfigure ............................................................. 7-19

8-2
 Sales
Offices

SALES OFFICES DOMESTIC SALES CONNECTICUT INDIANA MASSACHUSETTS

EUROPE ALABAMA Lindco Associates, Inc. Arete Sales Inc. Mill-Bern Associates, Inc.
Cornerstone 2260 Lake Ave Suite 250 2 Mack Road
XILlNX, Ltd. Technology Marketing Professional Park Fort Wayne, IN 46805 Woburn, MA 01801
Station House Associates, Inc. Suite C-l0l (219) 423-1478 (617) 932-3311
Bepton Road, Midhurst 3315 So. Memorial Pkwy. Woodbury CT, 06798 FAX: 219-420-1440 TWX: 710-332-0077
Sussex GU 299RE Suite 5 (203) 266-0728 FAX: 617-932-0511
England Huntsville, AL 35801 FAX: 203-266-0784 Arete Sales Inc.
Tel: 0730816725 (205) 883-7893 918 Fry Road Suite B MICHIGAN
FAX: 073081 4910 FAX: 205-882-6162 DELAWARE Greenwood,lN 46142
(317) 882-4407 A. P. Associates
JAPAN ARIZONA Micro Comp, Inc. FAX: 317-888-8416 810 E. Grand River
1421 S. Caton Avenue Brighton, MI48116
XILINX K. K. Ouatra Associates Baltimore, MD 21227 IOWA (313) 229-6550
Kybashi No.8 4645 S. Lakeshore Dr., (301) 644-5700 TWX: 816-287-310
Nagaoka Bldg. 8F Suite 1 TWX: 510-600-9460 Advanced Technical Sales FAX: 313-229-9356
20-9 Hatchobori Nichome Tempe, AZ 85282 FAX: 301-644-5707 375 Collins Road N.E.
Chuo-ku, Tokyo 104, Japan (602) 820-7050 Cedar Rapids, IA 52402 MINNESOTA
Tel: 03-297-9191 TWX: 910-950-1153 FLORIDA (319) 393-8280
FAX: 03-297-9189 FAX: 602-820-7054 FAX: 319-393-7258 Com-Tek
Technology Marketing 6525 City West Parkway
ARKANSAS Associates, Inc. KANSAS Eden Prairie, MN 55344
NORTH AMERICA 8000 Orange Ave., Suite 111 (612) 941-7181
Bonser-Philhower Sales Orlando, FL 32809 Advanced Technical Sales TWX: 310-431-0122
XILlNX, INC. 4614 S. Knoxville Avenue (407) 857-3760 610 N. Mur-Len, Suite 8 FAX: 612-941-4322
2100 Logic Drive Tulsa, OK 74135 TWX: 510-600-4721 Olathe, KS 66062
San Jose, CA 95124 (918) 744-9964 FAX: 407-857-6412 (913) 782-8702 MISSOURI
(408) 559-7778 TWX: 510-600-5274 FAX: 913-782-8641
TWX: 510-600-8750 Technology Marketing TWX: 910-350-6002 Advanced Technical Sales
FAX: 408-559-7114 CALIFORNIA Associates, Inc. 1810 Craig Road, Suite 213
1239 E. Newport Center Dr., LOUISIANA (Northern) SI. Louis, MO 36146
XILlNX, INC. SC Cubed Suite 107 (314) 878-2921
1270 Oakmead Parkway 468 Pennsfield Place Deerfield Beach, Fl33442 Bonser-Philhower Sales FAX: 314-878-1994
Suite 201 Suite lOlA (305) 427-1090 689 W. Renner Rd., Suite III
Sunnyvale, CA 94086 Thousand Oaks, CA 91360 FAX: 305-427-1626 Richardson, TX 75060 NEVADA
(408) 245-1361 (805) 496-7307 (214) 234-8438
FAX: 408-245-0517 FAX: 805-495-3601 Technology Marketing TWX: 910-867-4752 Norcomp
Associates, Inc. FAX: 214-437-0897 (Excluding Clark County)
XILlNX, INC. SC Cubed 1110066 SI. No., Suite 25 3350 Scott Blvd., Suite 24
2659 Townsgate Road 1786217th. SI. #207 Largo, FL 34643 LOUISIANA (Southern) Santa Clara, CA 95054
Suite 101 Tustin, CA 92680 (813) 541-1591 (408) 727-7707
Westlake Village, CA 91361 (714) 731-9206 FAX: 813-545-8617 Bonser-Philhower Sale.s TWX: 510-600-1477
(805) 494-5026 FAX: 714-731-7801 10700 Richmond, Suite 150
FAX: 805-496-0239 GEORGIA Houston, TX 77042 Quatra Associates
Ouest-Rep Inc. (713) 782-4144 (Clark County)
XILlNX, INC. 9444 Farnham SI., Suite 107 Technology Marketing TWX: 910-350-3451 4645 S. Lakeshore Dr.,
61 Spit Brook Rd. San Diego, CA 92123 Associates, Inc. Suite 1
Suite 403 (619) 565-8797 6655 Jimmy Carter Boulevard MAINE Tempe, AZ 85282
Nashua, NH 03060 FAX: 619-565-8990 Suite 2420 (602) 820-7050
(603) 891-1096 Norcross, GA 30071 Mill-Bern Associates, Inc. FAX: 602-820-7054
FAX: 603-891-0890 Norcomp (404) 446-3565 2 Mac Road
3350 Scott Blvd., Suite 24 FAX: 404-446-0569 Woburn, MA 01801 NEW HAMPSHIRE
XILlNX, INC. Santa Clara, CA 95054 (617) 932-3311
65 Valley Stream Parkway (408) 727-7707 IDAHO (Southwest) TWX: 710-332-0077 Mill-Bern Associates, Inc.
Suite 140 TWX: 510-600-1477 FAX: 617-932-0511 2 Mack Road
Malvem, PA 19355 FAX: 408-986-1947 Thorson Company Northwest Woburn, MA 01801
(215) 296-8302 12301 N.E. 10th Place MARYLAND (617) 932-3311
FAX: 215-296-8378 COLORADO Bellevue, WA 98005 TWX: 710-332-0077
(206) 455-9180 Micro Comp, Inc. FAX: 617-932-0511
XILlNX, INC. Front Range Marketing 1421 S. Caton Avenue
919 North Plum Grove Road 3100 Arapahoe Rd" ILLINOIS Baltimore, MD 21227-1082
Suite A Suite 404 (301) 644-5700
Beta Technology Sales, Inc. TWX: 510-600-9460

•
Schaumburg, IL 60173 Boulder, CO 80303
(312) 605-1972 (303) 443-4780 1009 Hawthorne Drive FAX: 301-644-5707
TLX: 510-601-5973 TWX: 910-940-3442 Itasca, IL 60143
FAX: 312-605-1985 FAX: 303-447-0371 (312) 250-9586
TWX: 62865853
FAX: (312) 250-9592

8-3
Sales Offices

NEW JERSEY (Northern) OHIO SOUTH CAROLINA WASHINGTON AUSTRIA

Parallax Bear Marketing, ·Inc. The Novus Group, Inc. Thorson Company Northwest Eljapex Ges. m.b.h.
734 Walt Whitman Road P.O. Box 427 5337 Trestlewood Lane 12340 N.E. 8th Place Eitnergasse 6
Mellville, NY 11747 3623 Brecksville Road Raleigh, NC 27610 Suite 201 A-1232Wien
(516) 351-1000 Richfield, OH 44286-0177 (919) 833-7771 Bellevue, WA 98005 Austria
FAX: 516-351-1606 (216) 659·3131 TWX: 510~oo-OS58 (206) 455-9180 (01) 86 3211
FAX: 216-659-4823 FAX: 919-839-0791 FAX: 206-455-9185 FAX: (01) 86 3211 200
NEW JERSEY (Southern) TWX: 810-427-9100 TWX: 910-443-2300
SOUTH DAKOTA BELGIUM & LUXEMBURG
Delta Technical Sales, Inc. Bear Marketing, Inc. WASHINGTON
3901 Commerce Avenue 240 W. Elmwood Drive Com-Tek (Vancouver, WA only) Le Mar Rodelco
Suite 180 Suite 1002 6525 City West Parkway Limburg Stirum 243
Willow Grove, PA 19090 Centerville, OH 45459-4248 Eden Prairie, MN 55344. Thorson Company Northwest 1810Wemmel
(215) 657-7250 (513) 436-2061 (612) 941-7181 6700 S.W. 105th Ave., Belgium
TWX: 510-601-1856 FAX: 513-436-9137 TWX: 310-431-0122 Suite 104 (02) 460-0560
FAX: 215-65~-378t FAX: 612-941-4322 Beaverton, OJl.97005 FAX: (02) 460-0271
OKLAHOMA (503) 644-5900
NEWMEXICQ TEXAS FAX: 503-644-6919 BRAZIL
Bonser-Philhower Sales
Quatra Associates 2727 E. 21st Street Bonser-Philhower Sales WASHINGTON D.C. Intemational Trade
9704 Admiral Dewey N.E. Suite 602 8240 MoPac Expwy., Development Corporation
Albuquerque, NM 87111 Tulsa, OK 74114 Suite 135 Micro Comp, Inc. 450 San Antonio Road
(505) 821-1455 (918) 744-9964 Austin, TX 78759. 1421 S. Caton Avenue Suite 32
FAX: 918-749-0497 (512) 346-9186 Baltimore, MD 21227 Palo Alto, CA 94306
NEW YORK (Metro) TWX: 910-997-8141 (301) 644-5700 (415) 856-8686
OREGON FAX: 512-346-2393 TWX: 510-600-9460 Telex: 650-282-9742
Parallax FAX: 301-644-5707.
734 Walt Whitman Road Thorson Company Northwest Bonser-Philhower Sales
WEST VIRGINA
CANADA
Mellville, NY 11747 6700 S. W. 105th Ave., 10700 Richmond, Suite 150
(516) 351-1000 Suite 104 Houston, TX 77042
(713) 782-4144 Bear Marketing, Inc. BRITISH COLUMBIA
FAX: 516-351-1606 Beaverton, OR 97005
(503) 644-5900 TWX: 910-350·3451 1563 East Dorothy Lane (Vancouver)
NEW YORK FAX: 503-644-5919 FAX: 713-789-3072 Suite 104
.Thorson Company Northwest
Kettering, OH 45429
Gen-Tech Electronics PENNSYLVANIA (Eastern) Bonser-Philhower SaI!!S (513) 299-5877 12301 N.E.l0th Place
Bellevue, WA 98005
4855 Executive Drive 689 W. Renner Rd., Suite 101 FAX: 513-299-0756
(206) 455-9180
Liverpool, NY 13088 Delta Technical Sales, Inc. Richardson, TX 75080
(315) 451-3480 122 New York Road (214) 234-8438 WISCONSINIWestern)
ONTARIO
TWX: 710-545-0250 Suite 9 TWX: 910-867-4752
FAX: 315-451-0988 Hatboro, PA 19040 FAX: 214-437-0897 Com-Tek
Electro Source, Inc.
(215) 957-0600 6525 City West Parkway
Gen-Tech Electronics TEXAS (EI Paso County) Eden Prairie, MN 55344 320 March Road, Suite 500
FAX: 215-957-0920
(612) 941-7181 Kanata, Ontario K2K 2E3
41 Burning Tree Lane (613) 592-3214
Rochester, NY 14526 PENNSYLVANIA (Western) Quatra Associates TWX: 310-431-0t22
(716) 381-5159 FAX: 613-592-4256
9704 Admiral Dewey N.E. FAX: 612-941-4322
Bear Marketing, Inc. Albuquerque, NM 87111
(505)821-1455 Electro Source, Inc.
Gen-Tech Electronics 300 Mt. Lebanon Blvd. WISCONSIN (Eastern)
230 Galaxy Boulevard
70 Sandoris Circle Pittsburg, PA 15234
(412)531-2002 UTAH Beta Technology Sales, Inc. Rexdale, Ontario M9W 5R8
Rochester, NY 14622 (416) 675-4490
(716) 467-5016 FAX: 412-531-2008 9401 Beloit, Suite 304C
Front Range Marketing Milwaukee, WI 53227 TWX: 06-989271
Gen-Tech Electronics (414) 543-6609 FAX: 416-675-6871
PUERTO RICO 7050 Union Park Center
5 Arbutus Lane Suite 440
QUEBEC
Binghampton, NY 13901 Mill-Bern Associates, Inc. Midvale, UT 84047
(607) 648-8833 2 Mac Road (801) 566-2500 INTERNATIONAL Electro Source
Woburn, MA 01801 FAX: 801-566-2951
NORTH CAROLINA (617) 932-3311
SALES 6600 TransCanada Hwy
VERMONT Suite 420 Point Claire
TWX: 710-332-0077
AUSTRALIA Quebec H9R 4S2
The Novus Group, Inc. FAX, 617-~32-0511 (514) 630-7486
5337 T restlewoOd Lane Mill-Bern Associates; Inc.
ACDIITRONICS FAX: 514-630-7421
Raleigh, NC 27610 Technology Marketillg 2 Mac Road
(919) 833-7771 Associates, Inc. 106 Belmore Rd. Noith
Woburn, MA 01801
(617) 932-3311 Riverwood, N.S.W; 2210 DENMARK
TWX: 510-600-0558 1280 S. W. 36ih Ave., Tel: Sydney 534-6200 .
FAX: 919'856-1644 Suite 201 TWX, 710-332-0071 Dana"ech KS .
FAX: Sydney 5:\4-4910
Pompano Beach, FL 33069 FAX: 617-932-0511
NORTH DAKOTA' (305) 977-9006 POBox 1361
ACD/ITRONICS Smedeland 8
TWX: 510-601-0120 VIRGINA
Com-Tek '. Uni12, 17-1.9 Melrich Road ?SOOGlostrup
FAX: 305-Q77-9044
Micro Comp, Inc. Beyswater VIC 3153 ' Denmark
6525 City West Parkway Tel: (02) 4345 47
RHODE ISLAND 1421 S. Caton Avenue P.O. Box 139
Eden Pmirie, MN 55344 Tel: Melbourne (03) 762 7644
(612) 941-7181 FAX: (02) 4345 67
Baltimore, MD 21227
Mill-Bern Associales, Inc. (301) 644-5700 Fax: Melbourne (03)762 5446
TwX: 310-431-0122
FAX: 612-941-4322 2 Mack Road TWX: 510-600-9460
ACD1ITRONICS
Woburn, MA01801 FAX: 301·644-5707
(617) 932-3311 55 Noreen Street
Chapel Hill OLD 4069
TWX: 710-332-0077 Tel: OLD 8781488
FAX: 617-932-0511
Fax: OLD 878 1490

8-4
 i:'1t'P' ¥f\t,){
v:dLdP,,%,q,

FINLAND GERMANY ISRAEL KOREA SWEDEN

OY SW-Instruments AB Metronik E.I.M International Ltd. Excel-Tech D.I.P. Electronics AS

Ala Portti IC Leonhardsweg 2 8, Emil Zola Street 410-5 Hapjeong-Dong P.O. Box 15046
SF-02210 Espoo, Finland Postfach 13 28 P.O. Box 4000 Mapo-Gu S-104 65 Stockholm, Sweden
Tel: (08) 4110 41 8025 Unterhaching Petach Tiqva Seoul, Korea Tel: (08) 44 91 90
FAX: (08) 0319 55 Munch en, Germany Tel Aviv, Israel Tel: 82-2-3357823 FAX: (08) 43 00 47
Tel: (089) 611080 Tel: (3) 92 33257 FAX: 82-2-3357825
FRANCE TLX: 897434 FAX: (3) 924 4857 SWITZERLAND
FAX: (089) 611 6468 TLX: 381144 E.I.M.I.L. Shinhwa Corp.
Reptronic Room 902, Bang-hyoup Bldg. Data Comp AG
11, Escalier des Ulis Metronik ITALY 43-8 Kwanchul-Dong Silbernstrasse 10
91400 Orsay, France Semerteichstrasse 92 Chongro-ku CH-8953 Dietikon
Tel: (16) 928 8700 4600 Dortmund 30 ACSIS S.R.L. Seoul, Korea Switzerland
FAX: (16) 928 1750 Dortmund, Germany Via Alberto Mario. 26 Tel: (01) 7405140
Tel: (0231) 423037/38 20149 Milano, Italy THE NETHERLANDS Telex: 827750
R.T.F. Gentilly TLX: 8227082 Tel: (02) 4390832 FAX: (01) 7413423
9, rue d'Arcueil TLX: 326566 Rodelco BV Electronics
94253 Gentilly Cedex, Metronik FAX: (02) 4697607 Takkebijsters 2 TAIWAN
France Osterbrooksweg 61 P.O. Box 6824
Tel:(16)46641110 2000 Schenefeld Celdis Italiana S.PA 4802 HV Breda Molecatex, Inc.
TLX: 2010169F Hamburg, Germany ViaF.i1l Gracchi 36 Netherlands 21F 258 Sec3
FAX: (16) 4 66 4419 9 Tel: (040) 8304061 20092 Ciniselio Balsamo Tel: (076) 784911 Nankin9 East Road
TLX: 2162488 Milano, Italy TLX: 54195 Taipei, Taiwan R.O.C.
R.T.F. (Radio Television Tel: (02) 61 8391 FAX: (076) 710029 Tel: (02) 7410400
Francaise SA) Metronik TLX: 334887 FAX: (02) 7217461
13, rue Lhote Siemensstrasse 4-6 FAX: (02) 61 73513 NORWAY TLX: 29214 MTEX
33000 Bordeaux. France 6805 Heddesheim
Tel: 56 52 9959 Mannheim. Germany Celdis Italiana S.P.A. B.I.T. Elektronikk AS Jeritron Ltd.
TLX: 560827 Tel: (06203) 4701-03 Via Massarenti 219/4 P.O. Box 36 Lerbyen 5/F Fu San Building
FAX: 56 4817 83 TLX: 465053 40138 Bologna, Italy N-3401 Lier, Norway 1182 Cheng-Teh Road
Tel: (051) 533336 Tel: (03) 847099 Taipei, Taiwan. R.O.C.
R.T.F. Ouest Metronik FAX: (03) 84 55 10 Tel: (02) 8823154
3, rue de Paris Laufamholzstr. 118 Celdis Italiana S.PA FAX: (02) 8820710
35510 Cesson Sevigne, 8500 NQrnberg 30 Via Savelli 15 SINGAPORE
France NOrnberg, Germany 35100 Padova, Italy Sertek Int'I Inc.
Tel: 99 83 64 85 Tel: (0911) 590061162 Tel: (049) 77 209 9 Excel Associates Ltd. 15/F, 135 Sec 2
TLX: 741127 TLX: 626205 Singapore Representative Chien Kuo N. Road
FAX: 99 83 8Q 83 Celdis Italiana S.PA Office Taipei 10479
Metronik ViaG. Pitre' 11 111 North Bridge Road Taiwan R.O.C.
R.T.F. Sud Ouest LOwenstr. 37 00162 Roma, Italy #11-04/06 Peninsula Plaza Tel: 2 501 0055
Avenue de la Mairie 7000 Stuttgart 70 Tel: (06) 42 897 1 Singapore 0617 Fax: 2501 2521
31320 Escalquens, France Stuttgart, Germany Tel: 3366577 Telex: 23756 Sertek
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locations throughout 12900 Saratoga Ave. 6885 Flanders Drive Corporation Electronics Corp.
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