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Chapter 4 - Synchronous MOD Counters

This document discusses the design of a synchronous MOD-6 counter with an arbitrary counting sequence. It describes 4 steps to design such a counter: 1) Determine the desired states from the state diagram, 2) Specify the number of flip-flops and counting procedure, 3) Develop an excitation table with inputs and next states, 4) Design logic circuits to create the correct inputs using Karnaugh maps, and 5) Simplify the expressions and draw the final logic circuit. The goal is to generate a counter that counts through a specific sequence, such as 000, 010, 011, 001, 100, 110, while avoiding unwanted states like 101 and 111.

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Minh Phú
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Download as PDF, TXT or read online on Scribd
66 views

Chapter 4 - Synchronous MOD Counters

This document discusses the design of a synchronous MOD-6 counter with an arbitrary counting sequence. It describes 4 steps to design such a counter: 1) Determine the desired states from the state diagram, 2) Specify the number of flip-flops and counting procedure, 3) Develop an excitation table with inputs and next states, 4) Design logic circuits to create the correct inputs using Karnaugh maps, and 5) Simplify the expressions and draw the final logic circuit. The goal is to generate a counter that counts through a specific sequence, such as 000, 010, 011, 001, 100, 110, while avoiding unwanted states like 101 and 111.

Uploaded by

Minh Phú
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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HCMC University of Technology and Education

Faculty of Electrical & Electronic Engineering

Lecture:
DIGITAL SYSTEMS
Chapter 4:
Synchronous MOD Counters

Assoc. Prof. Nguyen Thanh Hai, PhD


1
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Synchronous MOD Counters


Synchronous Counter Design with arbitrary Mod
A MOD counter can be designed to count
an arbitrary MOD with a synchronous clock
pulse.
For example, an MOD-6 counter may be
required to follow the counting sequence
000, 010, 011, 001, 100, 110, in which
states 101 and 111 are called “undesired
states”.
According to this counting procedure, the
two undesired states 101 and 111 have the
next state 000 or maybe we have no need
to use the states 101 and 111.
2
Assoc. Prof. Nguyen Thanh Hai, PhD
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Synchronous MOD Counters


To design this MOD-6 synchronous counter, we use the following
steps:
1. Based on state diagram to know 6 desired states for
designing synchronous counter
2. Determine 3 FF numbers and MOD-6 counter procedure

3
Assoc. Prof. Nguyen Thanh Hai, PhD
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Synchronous MOD Counters


Step 3: show the excitation truth table with all present and next
states corresponding to the J, K inputs

No Pre-State Next-state Inputs

St C B A C B A JC KC JB KB JA KA
0 0 0 0 0 1 0 0 X 1 X 0 X
1 0 0 1 1 0 0 1 X 0 X X 1
2 0 1 0 0 1 1 0 X X 0 1 X
3 0 1 1 0 0 1 0 X X 1 X 0
4 1 0 0 1 1 0 X 0 1 X 0 X
5 1 0 1 0 0 0 X 1 0 X X 1
6 1 1 0 0 0 0 X 1 X 1 0 X
7 1 1 1 0 0 0 X 1 X 1 X 1

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Assoc. Prof. Nguyen Thanh Hai, PhD
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Synchronous MOD Counters


Step 3: show the excitation truth table with all present and next
states corresponding to the J, K inputs

No Pre-State Next-state Inputs

St C B A C B A JC KC JB KB JA KA
0 0 0 0 0 1 0 0 X 1 X 0 X
1 0 0 1 1 0 0 1 X 0 X X 1
2 0 1 0 0 1 1 0 X X 0 1 X
3 0 1 1 0 0 1 0 X X 1 X 0
4 1 0 0 1 1 0 X 0 1 X 0 X
5 1 0 1 0 0 0 X 1 0 X X 1
6 1 1 0 0 0 0 X 1 X 1 0 X
7 1 1 1 0 0 0 X 1 X 1 X 1

5
Assoc. Prof. Nguyen Thanh Hai, PhD
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Synchronous MOD Counters


A A A A A A
* Step 4: Design
CB 00 11 CB X0 X1 CB 00 X1 a logic circuit to
CB 0 2 0 3 CB X2 X3 CB 1 2 X3 create the
CB X6 X7 CB 16 1 7 CB 06 X7 correct logic
CB X4 X5 CB 0 4 15 CB 0 4 X5 level at each J,K
input using
J C  AB KC  A  B J A  BC Karnaugh maps
for each one of
A A A A A A
inputs, then
CB 10 01 CB X0 X1 CB X0 11
simplify the
CB X2 X3 CB 0 2 1 3 CB X2 0 3 Boolean
CB X6 X7 CB 16 1 7 CB X6 1 7 expression as in
CB 1 4 05 CB X4 X5 CB X4 15 Figures (a), (b),
…, (f)
JB  A KB  A  C KA  C  B 6
Assoc. Prof. Nguyen Thanh Hai, PhD
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Synchronous MOD Counters


* Step 5: From the Karnaugh maps, one may have the simplified
expressions and then draw the logic circuit

7
Assoc. Prof. Nguyen Thanh Hai, PhD
HCMC University of Technology and Education
Faculty of Electrical & Electronic Engineering

Synchronous MOD Counters

The End

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Assoc. Prof. Nguyen Thanh Hai, PhD

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