UNIVERSITY OF THE EAST

College of Engineering
Computer Engineering Department

EXPERIMENT NO. 4
Magnitude Comparator

Course Code: NCP 3201 Program:

Course Title: Introduction to HDL Date Performed: 09/27/2022
Date Submitted:10/04/2022
Name: Dante, Christian Joie C. Professor: Nelson C. Rodelas

Learning Outcomes:
At the end of the experiment, the student should be able to:
1. Develop VHDL programs for 1-Bit and 2-Bits Comparator.
2. Construct an EPWave of a 1-Bit and 2-Bits Comparator.

Discussion:
 A magnitude digital Comparator is a combinational circuit that compares two
digital or binary numbers to find out whether one binary number is equal, less
than, or greater than the other binary number. We logically design a circuit for
which we will have two inputs one for A and the other for B and have three output
terminals, one for A > B condition, one for A = B condition, and one for A < B
condition.
 Block Diagram

 1-Bit Magnitude Comparator Schematic Diagram

  Truth Table of 1-Bit Magnitude Comparator
A B G L E
0 0 0 0 1
0 1 0 1 0
1 0 1 0 0
1 1 0 0 1

 Copy and paste the following code to the design area.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity comparator_1bit is
Port ( A,B : in std_logic;
G,L,E: out std_logic);
end comparator_1bit;

architecture behavioral of comparator_1bit is

begin
G <= A and (not B);
L <= (not A) and B;
E <= A xnor B;
end behavioral;

 Create the test bench of the design code.

 Save and Run the Program.
Take note of the following coding errors:
• One possible mistake is incorrect spacing.
• Always log out of your EDAPlayground account after completing a program.
• Always alter the top entity's and title's names because the top entity's and title's
names must be the same. Furthermore, testbench names like SampleCode1 must
be the same as the top entity name.
• The design's name must be the same as the design's name after beginning
architecture (for example, Design or_
• There must be no spaces in the design's name.
• You must input all the codes, or an error will occur.

Activity:
1. Create the VHDL Module of the 2-Bit Comparator.
2. Produce the EPWave of the 2-Bit Comparator.
3. Write the design code. (Separate page)
 4. Screenshot of EPWave for Decoder. (Separate page)
Question:
1. What are your observations from using EDA Playground in describing the code
for 1-Bit and 2-Bit Comparator?
 1-Bit Comparator a single-bit comparator is a comparator that compares just two
bits. It has three outputs to produce less than, equal to, and greater than
between two binary integers and two inputs for each pair of single-bit numbers.
 2-Bit Comparator a magnitude comparator is a comparator that compares two
binary integers with two bits each. To generate less than, equal to, and greater
than between two binary values, it has four inputs and three outputs.
TESTBENCH:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity Experiment4 is
end Experiment4;

architecture Experiment4TB of Experiment4 is

component comparator_1bit
Port (
A : in STD_LOGIC;
B : in STD_LOGIC;
G : out STD_LOGIC;
L : out STD_LOGIC;
E : out STD_LOGIC);
end component;

signal A : STD_LOGIC := '0';

signal B : STD_LOGIC := '0';
signal G : STD_LOGIC;
signal L : STD_LOGIC;
signal E : STD_LOGIC;

begin

UUT: comparator_1bit port map (

A => A,
B => B,
G => G,
L => L,
E => E);

--Stimulus Process
stim_proc: process
begin

A <= '0';
B <= '0';
wait for 100 ns;

A <= '0';
B <= '1';
wait for 100 ns;
A <= '1';
B <= '0';
wait for 100 ns;

A <= '1';
B <= '1';
wait for 100 ns;

wait;
end process;
end Experiment4TB;

DESIGN:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity comparator_1bit is
Port ( A,B : in std_logic;
G,L,E: out std_logic);
end comparator_1bit;
architecture behavioral of comparator_1bit is
begin
G <= A and (not B);
L <= (not A) and B;
E <= A xnor B;
end behavioral;
2Bit Comparator
CODES:
Testbench: --Outputs
LIBRARY ieee; signal A_less_B : std_logic;
USE ieee.std_logic_1164.ALL; signal A_equal_B : std_logic;
use ieee.numeric_std.all; signal A_greater_B : std_logic;
ENTITY Expt4_2bit IS BEGIN
END Expt4_2bit;
-- Instantiate the comparator in VHDL
ARCHITECTURE behavior OF uut: comparator_2bit PORT MAP (
Expt4_2bit IS
A => A,
B => B,
COMPONENT comparator_2bit
A_less_B => A_less_B,
PORT(
A_equal_B => A_equal_B,
A : IN std_logic_vector(1 downto
A_greater_B => A_greater_B);
0);
B : IN std_logic_vector(1 downto
0); -- Stimulus process
A_less_B : OUT std_logic; stim_proc: process
A_equal_B : OUT std_logic; begin
A_greater_B : OUT std_logic); -- test cases for A_less_B
for i in 0 to 3 loop
END COMPONENT; A <=
std_logic_vector(to_unsigned(i,2));
--Inputs
B <=
signal A : std_logic_vector(1 downto
std_logic_vector(to_unsigned(i+1,2));
0) := (others => '0');
wait for 20 ns;
signal B : std_logic_vector(1 downto
0) := (others => '0'); end loop;
 A_equal_B: out std_logic;
-- test cases for A_greater_B A_greater_B: out std_logic
for i in 0 to 3 loop );
A <= end comparator_2bit;
std_logic_vector(to_unsigned(i+1,2));
architecture comparator_structural of
B <= comparator_2bit is
std_logic_vector(to_unsigned(i,2));
signal tmp1,tmp2,tmp3,tmp4,tmp5, tmp6,
wait for 20 ns; tmp7, tmp8: std_logic;
end loop;
-- test cases for A_equal_B begin
for i in 0 to 3 loop -- A_equal_B
A <= tmp1 <= A(1) xnor B(1);
std_logic_vector(to_unsigned(i,2));
tmp2 <= A(0) xnor B(0);
B <=
A_equal_B <= tmp1 and tmp2;
std_logic_vector(to_unsigned(i,2));
-- A_less_B
wait for 20 ns;
tmp3 <= (not A(1)) and B(1);
end loop;
tmp4 <= A(1) xnor B(1);
tmp5 <= (not A(0)) and B(0);
wait;
A_less_B <= tmp3 or (tmp4 and tmp5);
end process;
-- A_greater_B
tmp6 <= (not B(1)) and A(1);
END;
tmp7 <= A(1) xnor B(1);
tmp8 <= (not B(0)) and A(0);
Design:
library IEEE;
A_greater_B <= tmp6 or (tmp7 and
use IEEE.std_logic_1164.all;
tmp8);
entity comparator_2bit is
end comparator_structural;
port (
A,B: in std_logic_vector(1 downto 0);
A_less_B: out std_logic;