1 2 3 4 5

u1 u2 u3 u11

U1
When /romEnable is low we want ROM. Z80 CPU
1 40 a10
A11 A10
A When /ramEnable is low we want RAM. a11 2
A12 A9
39 a9
A
a12 3 38 a8
A13 A8
a13 4 37 a7
A14 A7
a14 5 36 a6
A15 A6
a15 6 35 a5
U2 CLK A5
clk 7 34 a4
UM61512 64k RAM D4 A4
d4 8 33 a3
D3 A3 VCC VCC
1 32 VCC d3 9 32 a2
NC VCC D5 A2
2 31 a15
VCC d5 10 31 a1
NC A15 D6 A1
3 30VCC VCC d6 11 30 a0
A14 CE2 VCC A0
a14 4 29 VCC 12 29 GND
A12 /WE /wr D2 GND R13 R14
a12 5 28 a13 d2 13 28 /m1
A7 A13 D7 /RFSH 10K 10K
a7 6 27 a8 R15 d7 14 27
A6 A8 D0 /M1
a6 7 26 a9 10K d0 15 26 /reset
A5 A9 D1 /RESET
a5 8 25 a11 d1 16 25 /busrq
A4 A11 /rd /INT /BUSRQ
a4 9 24 17 24
A3 /OE /NMI /WAIT /wait
a3 10 23 a10 /int 18 23
A2 A10 /ramEnable /HALT /BUSAK
a2 11 22 19 22
A1 /CE /MREQ /WR
a1 12 21 d7 20 21 /busak
A0 IO8 /nmi /IORQ /RD
a0 13 20 d6 /wr
IO1 IO7
B d0 14 19 d5 B
IO2 IO6 /halt /rd
d1 15 18 d4
IO3 IO5
d2 16 17 d3 /mreq
GND IO4
GND
C2 SW3 /ioreq
1uF /INT

CH376S USB Pen-Drive Module

U10
CH376S_Module GND
1 2 U11
d0 DO GND GND 16C550 - UART
3 D1 GND 4
d1 GND
5 D2 VCC 6 1 40
d2 VCC d0 D0 VCC VCC
7 D3 /INT 8 2 39
d3 d1 D1 /RI VCC
9 D4 A0 10 3 38
d4 a0 U3 d2 D2 /CD GND
11 D5 /CS 12 4 37
d5 /csUsb 28C256 - 32K EEPROM d3 D3 /DSR GND
13 14 5 36
28

10 11 d0
d6 D6 /RD /rd A0 D0 d4 D4 /CTS
VCC

15 D7 /WR 16 a0 9 12 d1 6 35
d7 /wr A1 D1 d5 D5 RESET uartReset
C a1 8 13 d2 7 34 C
A2 D2 d6 D6 /OP1 uartOp1
17 17 18 18 a2 7 15 d3 8 33
A3 D3 d7 D7 /DTR uartDtr
19 GND TX 20 a3 6 16 d4 9 32
A4 D4 RCLK /RTS uartRts
21 RX 22 22
d5 10 31
a4 5
romON goes high on reset
17
A5 D5 uartRx RX /OP2 romOn
a5 4 18 d6 11 30
A6 D6 uartTx TX INT
a6 3
A7 D7
19 d7
a3 12
CS0 /RXRDY
29 NOTE: Swapped over pins 34 & 31 in v1.2
a7 25 13 28
A8 /m1 CS1 A0 a0
a8 24 14 27
A9 /ioreq /CS2 A1 a1
a9 21 15 26
A10 /BAUDOUT A2 a2
a10 23 16 25
A11 xtal1 XTAL1 /AS GND
a11 2 17 24
A12 xtal2 XTAL2 /TXRDY
a12 26 18 23
A13 /wr /IOW /DDIS
a13 1 19 22
A14 GND IOW IOR GND
a14 20 21
GND GND /IOR /rd
27
VCC 22
/WE
GND

/rd /OE
NOTE: INT & RESET are positive-logic.
20
/romEnable /CS
14

D D

TITLE:
Main chips REV: 1.2

Company: 8bitstack.co.uk Sheet: 1/1

Date: 2020-05-11 Drawn By: johnsquires
1 2 3 4 5
 1 2 3 4 5

u7 u8.2
Reset button
CPU clock - up to 4MHz crystal VCC

R5
1M
A C1 SW1 A
10uF Reset U7.6
U7.1 U7.2 74HC14 inverter
74HC14 inverter 74HC14 inverter

14
VCC
13 12 /reset
14

14
clk

GND
VCC

VCC
1 2 3 4

7
GND

GND
R8
7

7
10K U7.4
R6 74HC14 inverter
470R

14
VCC
9 8
uartReset

GND
X1 GND

7
CPU XTAL
4 3

C5
8pF C6
8pF

VCC
B B
Note that externalNMI is positive edge triggered.

UART clock - 7.3728 MHz NMI button SW2

/NMI
externalNmi
xtal1 xtal2 U8.2
74HC02 - NOR

6
7 14
R9 GND VCC
R7 10K R4
1K5 10K
X2
UART 7.3728MHz GND
4 3 GND

4
C C18
C17 C
22pF
47pF

/nmi
D D

TITLE:
Clock and reset REV: 1.0

Company: 8bitstack.co.uk Sheet: 1/1

Date: 2020-05-11 Drawn By: johnsquires
1 2 3 4 5
 1 2 3 4 5

Assuming /MREQ is low, we want ROM when: u5 u6

(1) A15 is low

(2) A14J is low (this is the jumpered version of a14)

VCC
U5.1

14
74HC32 - OR

VCC
A (3) /FFJ is low (this is the jumpered version of the FF) 1 U5.2
A

14
a15 3 74HC32 - OR

VCC
(4) /RD is low 2 4 U5.3

14
a14j 6 74HC32 - OR
5 9
Otherwise we want RAM.

7
P2 /romOnj

GND
P1 rom jumper 8
a14 jumper 10 /wantROM

7
/rd

GND
/wantROM = 1 or 2 or 3 or 4 a14 1 /romOn 1
/romOnj 2
2

7
GND
a14j GND 3
/romEnable = /MREQ or /wantROM GND 3 U8.3

VCC
74HC02 - NOR
U6.1

14
14
/ramEnable = /MREQ or NOT /wantROM

VCC
9 74HC32 - OR
/wantROM 10 1
8 3

GND
2 /ramEnable

7
VCC
U5.4 /mreq

14

7
74HC32 - OR

GND
12
B /wantROM B
11
13 /romEnable
/mreq

7
U7.5

GND
74HC14 inverter

14
VCC
11 10
romOn /romOn

GND
VCC

7
U6.4

14
74HC32 - OR
/ioreq 12

VCC
U8.1
11 U6.2

14
74HC02 - NOR
13 74HC32 - OR
14
VCC

3 4
1 6
/m1 /csUsb

7
GND
2 5
GND

U8.4
74HC02 - NOR
7

14
VCC
12

7
GND
a4 13
C 11 C
GND
7

U7.3
74HC14 inverter

14
VCC
5 6
GND

GND
I/O for Serial UART we want: For I/O for USB Drive we want:

VCC
(1) /IOREQ is low (1) /IOREQ is low U6.3

14
74HC32 - OR
(2) /M1 is high (2) /M1 is high 9
GND 8
(3) a3 is high (3) a3 is low (or don't care) 10
GND
(4) a4 is low (or don't care) (4) a4 is high

7
GND
base uart port = 00001000 = 8 base USB port = 00010000 = 16
D D

This leaves ports 32, 64 and 128 available for other peripherals.
TITLE:
Of course this simplistic scheme means that you could write to multiple ports at the same time, so beware!
ROM / RAM / IO select logic REV: 1.0

Company: 8bitstack.co.uk Sheet: 1/1

Date: 2020-06-11 Drawn By: johnsquires
1 2 3 4 5
 1 2 3 4 5

H1
TTL Serial
A 1 - VCC A
uartTx 2 TX
uartRx 3 RX
VCC 4 VCC
uartRts 5 /RTS
GND 6 GND R10
1K

LED4
user1

uartDtr

H2
Header-Female-2.54_1x36 VCC VCC VCC VCC

B B
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
R1 R2 R3 R16
1K 1K 1K 1K
GND

/mreq
a15
a13
a11
a14
a12
a10
/busak
(out) /reset

/rd

d7
d6
d5
d4
d3
d2
d1
d0
a9
a8
a7
a6
a5
a4
a3
a2
a1
a0
/wr

LED6 LED1 LED2 LED3

VCC

/busrq
/m1

/ioreq
externalNmi
/wait

Halt /ROM /DISK power

/halt /romOn uartOp1 GND

VCC
C C

C13 C12 C10 C3 C4 C7 C8 C9 C11

104 104 104 104 104 104 47uF 104 104

GND

D D

TITLE:
Connectors REV: 1.0

Company: 8bitstack.co.uk Sheet: 1/1

Date: 2020-05-04 Drawn By: johnsquires
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