EECS 16B Notes

Spring 2020
 EECS 16B Notes @ 2020-02-27 20:35:52-08:00

Contents

Contents ii

List of Figures iii

1 16A review and prerequisites 1

1.1 The language of circuits . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Current-voltage characteristic . . . . . . . . . . . . . . . . . . . . 2
1.3 Linear algebra . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Transistor Circuits 5
2.1 m o s f e t behavior at a low level . . . . . . . . . . . . . . . . . . . 5
2.2 An n m o s inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 A c m o s inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 A c m o s inverter chain with capacitance . . . . . . . . . . . . . . 10

3 Transient Analysis 15
3.1 RC transient in an inverter chain . . . . . . . . . . . . . . . . . . 15
3.2 Uniqueness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4 Differential equations with inputs 21

4.1 RC with exponential input . . . . . . . . . . . . . . . . . . . . . . 21
4.2 General scalar differential equation . . . . . . . . . . . . . . . . . 23

5 Vector differential equations and second-order circuits 25

5.1 Guess-and-check for RC filter with cosine input . . . . . . . . . . 25
5.2 Second-order filter with two capacitors . . . . . . . . . . . . . . 26
5.3 General state-space linear ODEs . . . . . . . . . . . . . . . . . . . 26

6 Diagonalization to solve vector differential equations 31

6.1 Solution technique . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2 Numerical example from RCRC circuit . . . . . . . . . . . . . . . 32
6.3 Introduction to inductors . . . . . . . . . . . . . . . . . . . . . . . 34
6.4 Example: RL circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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EECS 16B Spring 2020 EECS 16B Notes

List of Figures

1.1 Current and voltage annotated on a passive element. . . . . . . . . 1

1.2 I-V characteristic of a resistor. . . . . . . . . . . . . . . . . . . . . . . 2
1.3 I-V characteristic of a voltage source. . . . . . . . . . . . . . . . . . . 2
1.4 I-V characteristic of a current source. . . . . . . . . . . . . . . . . . . 3

2.1 Physical construction of a simple m o s f e t. . . . . . . . . . . . . . . . 5

2.2 Currents and voltages labeled on an n m o s transistor. . . . . . . . . 6
2.3 I-V characteristic of an n m o s transistor at different values of v GS . . 6
2.4 Regions of an n m o s I-V characteristic. . . . . . . . . . . . . . . . . . 7
2.5 Currents and voltages labeled on a p m o s transistor. . . . . . . . . . 7
2.6 I-V characteristic of a P M O S transistor at different values of vGS . . 8
2.7 A inverter built using an n m o s transistor. . . . . . . . . . . . . . . . 8
2.8 Truth table of the n m o s inverter. . . . . . . . . . . . . . . . . . . . . 9
2.9 A inverter built using the c m o s design.. . . . . . . . . . . . . . . . . 10
2.10 Equivalent circuit of Figure 2.9 when vin  VDD . . . . . . . . . . . . 10
2.11 A chain of inverters, which is kind of similar to a computer. . . . . . 11
2.12 An inverter taken from a chain with a capacitor modeling the next
stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.13 An inverter outputting VDD with load capacitor. . . . . . . . . . . . 11
2.14 Energy stored in a capacitor can be computed by an integral under
the V  Q/C curve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.15 c m o s load capacitor forced from voltage VDD to 0. . . . . . . . . . . 12

3.1 Model of n m o s transistor with G-S capacitance. . . . . . . . . . . . 15

3.2 Model of p m o s transistor with G-S capacitance. . . . . . . . . . . . 16
3.3 A c m o s inverter at three levels of abstraction. . . . . . . . . . . . . . 16
3.4 Two consecutive c m o s inverters, part of a longer chain. . . . . . . . 16
3.5 Input signal to the first inverter of Figure 3.4 . . . . . . . . . . . . . 17
3.6 Analog redrawing of Figure 3.4, showing switch actions of the first
inverter, as well as a distinguished node. . . . . . . . . . . . . . . . . 17
3.7 Sketch of transient from t1 to t2 in Figure 3.6. . . . . . . . . . . . . . 19

4.1 An amp with three knobs to adjust playback. . . . . . . . . . . . . . 21

4.2 RC circuit as a filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

iii
L i st o f F i g u r e s

5.1 Filter with two resistors and two capacitors. . . . . . . . . . . . . . . 26

5.2 Decomposition of x® along eigenbasis directions v®1 and v®2 . . . . . . 28

6.1 Illustration of multiplication actions of A, Λ, V, and V −1 . . . . . . . 32

6.2 Parallels between capacitors and inductors. . . . . . . . . . . . . . . 34
6.3 RL circuit, which is similar to an RC circuit (cf. Figure 4.2). . . . . . 35

iv
EECS 16B Spring 2020 EECS 16B Notes

Lecture 1

16A review and prerequisites

1.1 The language of circuits

Electrical circuits are models, specifically, abstractions of underlying physics-
based descriptions of realities that govern behavior of an electrical system
under analysis. Mathematically, circuits are collections of nodes joined by branch
elements. Between every pair of adjacent nodes there is a voltage difference,
measured in volts, as well as a current, measured in amps. You should be able to
explain, both in approximate physical terms, and, if possible, by a mechanical
analog, what voltage and current are. Given a circuit drawing, you should
be able to write a comprehensive set of voltage-current constraints that fully
predicts what is happening in the circuit. For a well-posed circuit model with
N nodes, one preferred method is Nodal Analysis, which involves writing N − 1
linearly independent KCL node equations, and incorporating KVL and element
branch consraints while writing the node equations.

Figure 1.1: Current and voltage annotated on a passive element.

Understand how current and voltage are annotated on a circuit. Our terms
are “voltage across branch element X” and “current through branch element
X.” The phrases “voltage through. . . ” or “current across. . . ” do not make sense.
Understand, as shown in Fig. 1.1, that the reference directions for voltage

1
1. 16A review and prerequisites

Figure 1.2: I-V characteristic of a resistor.

Figure 1.3: I-V characteristic of a voltage source.

and current are such that power absorbed by a circuit element is given by the
formula vi.

1.2 Current-voltage characteristic

Resistor
As shown in Fig. 1.2, resistors enforce a proportionality relationship between
current and voltage:
V  RI (1.1)
I  GV (1.2)
The ratio V/I is called resistance. The ratio I/V is called conductance.

Voltage source
As shown in Fig. 1.3, a voltage source will provide any current (or none at all)
to maintain its target voltage.

Current source
As shown in Fig. 1.4, a current source will provide any voltage (or none at all)
to maintain its target current.

2
 1.3. Linear algebra

Figure 1.4: I-V characteristic of a current source.

Circuit-solving techniques
Be familiar with the following methods for solving circuits:

• Series elements, e.g. two resistors in series

• Parallel elements, e.g. two resistors in parallel.
• Voltage and current dividers
• Kirchoff’s voltage and current laws
• Norton and Thévenin equivalent circuits
• Nodal analysis
• Power calculations

1.3 Linear algebra

Know what a vector is. Know what eigenvalues and eigenvectors are, and know
how to solve for the eigenvalues and eigenvectors of a matrix, by solving for the
null space of A − λI, where λ is an indeterminate. Know why this technique
works.

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EECS 16B Spring 2020 EECS 16B Notes

Lecture 2

Transistor Circuits

2.1 m osfet behavior at a low level

Transistors are nonlinear circuit elements that are integral to building digital
electronics. We’ll focus on a class of transistor called m o s f e t (metal-oxide
semiconductor field-effect transistor), of which there are two types, n m o s and
p m o s. For the most part, we will view m o s f e ts from a digital perspective as
voltage-controlled switches (more on that later), but we’ll first have a look at
the analog world under the hood.
The physical makeup of a m o s f e t is shown in Figure 2.1. It is a device
built on a silicon substrate with three terminals: source (S), drain (D), and gate
(G). What makes a transistor a transistor is 2) mediated by gate voltage. (No
current enters the gate of a mosfet: IG = 0.) 1) a current-voltage characteristic
between drain and source, These quantities are labeled on Figure 2.2. Notice
that voltages are understood with reference to their difference from VS , so:

• D-S current-voltage characteristic is between ID and vDS  vD − vS ,

• parameterized by vGS  vG − vS .

Figure 2.1: Physical construction of a simple m o s f e t.

5
2 . T r a n s i sto r C i rc u i t s

Figure 2.2: Currents and voltages labeled on an n m o s transistor.

Figure 2.3: I-V characteristic of an n m o s transistor at different values of vGS .

The role of vGS in n m o s

Figure 2.3 depicts several current-voltage characteristics of an nmos, parame-
terized by v GS . There’s a lot happening on this graph in both the vertical and
horizontal directions. Here’s a self-guided tour:
• Notice the horizontal line lying along the positive vDS -axis. This is the plot
of the I-V characteristic when vGS < vt,n , where v t,n > 0 is the threshold
voltage for an n m o s transistor. The current-voltage characteristic is
I  0, the transistor is behaving as a current source corresponding to zero
current—in other words, it’s an open circuit. The transistor is “off.” 1
• Notice that three I-V curves, parameterized by how much vGS exceeds
v t,n , lie above the line I  0. Each of them is intersected by what looks
like the eastern half of a dotted upward-facing parabola rising from the
origin. This parabola divides the quadrant into two regions, one left and
1 English semantics for “on” and “off” in circuits can be counterintuitive. An open circuit/switch

is off, and vice versa.

6
 2.1. m o s f e t behavior at a low level

region # on/off? v GS predicate v DS predicate name

0 off v GS < v t,n any
1 on v GS > v t,n low “linear region”
2 on v GS > v t,n high “saturation”

Figure 2.4: Regions of an n m o s I-V characteristic.

Figure 2.5: Currents and voltages labeled on a p m o s transistor.

one right. The left region is called region 1; the right region is called
region 2.
• Focus on region 1, which is called the Linear Region. Notice that in region
1 near the origin, ID and vDS are proportional for every value of vGS . The
slope G  ID /vDS increases for higher values of vGS . This means that
the D-S resistance R  G −1 transitions from ∞ to a finite (perhaps small)
value as v GS increases past v t,n . A resistor that can alternate between
finite and infinite resistance is called a switch: in the Linear Region the
transistor is a voltage-controlled switch.
• Focus on region 2, which is called Saturation, Here the ID increases only
very weakly as vDS increases.For a given VDS , ID increases with increasing
vGS : the transistor behaves approximately as a voltage-controlled current
source!
These characteristics are summarized in Figure 2.4. Regions 0 and 1 can be used
to implement a switch. Region 2 is used for analog electronics—dependent
sources, amplifiers, etc.

pmos transistors: opposite of n m o s

Another kind of m o s f e t is the p m o s. They have a similar construction as
nmos transistors, but their behavior is opposite, and for the “on” condition of
VGS < Vt,p , Vt,p < 0. Figure 2.5 and Figure 2.6 are the counterparts of Figure 2.2
and Figure 2.3, respectively.
For most of this class, we’ll use more idealized models of these transistors
in digital logic settings. In the voltage-controlled switch perspective, n m o s

7
2 . T r a n s i sto r C i rc u i t s

Figure 2.6: I-V characteristic of a P M O S transistor at different values of v GS .

Figure 2.7: A inverter built using an n m o s transistor.

transistors open at lower voltages and close at higher voltages, and p m o s

transistors close at lower voltages and open at high ones.

2.2 An nmos inverter

One building block we need to understand digital logic is the inverter, which
is a circuit that outputs a high voltage when its input is a low voltage, and
vice versa. The high voltage represents a digital value of 1 (true), and the low
voltage represents a digital value of 0 (false).
It’s possible to build an inverter using an n m o s transistor, as shown in
Figure 2.7. The high voltage is called VDD , which stands for the voltage supplied
by the high power rail, and in this example has a value of 1 volt.2 In this example,
our reference voltage will be ground—0 volts.
2 For obscure historical reasons.

8
 2.3. A c m o s inverter

vin vout
0 VDD
VDD 0

Figure 2.8: Truth table of the n m o s inverter.

Analysis
• (Case v in  0) The transistor, as a switch, is off. As a result, the terminal
vout is connected directly to VDD by a resistor. Because no current flows
into the voltage terminal, by Ohm’s law there can be no voltage drop
across the resistor. Therefore vout  VDD .

• (Case vin  VDD ) The transistor, as a switch, is on. The terminal vout has a
short to ground, so v out  0.

Figure 2.8 shows the truth table of this circuit and verifies that this circuit is
indeed an inverter.

Power consumption
When vin  0, the circuit consumes no power, as we have established that there
is no current through the resistor between VDD and vout . When v in  VDD , there
is a path from VDD through the resistor, then the transistor, to ground. The
circuit consumes power V I  VDD 2
/R. While this might not necessarily be a lot,
in computing applications with countless transistors, it adds up, and moving
heat away from a dense circuit poses engineering challenges. Dense digital
circuits were made possible by the discovery of the CMOS inverter architecture,
which avoids a path from VDD to ground.

2.3 A cmos inverter

Figure 2.9 shows an inverter circuit that exemplifies the cmos design strategy
of using p m o s and n m o s transistors together.

Analysis
• (Case vin  VDD )

– The p m o s having as its source VDD and vout as its drain VGS,1  0,
which is higher than Vt,p . Therefore there is no path from VDD to
vout .
– The n m o s having vout as its drain and ground as its source has
VGS,2  VDD , which is higher than Vt,n . Therefore, due to the
terminal’s short to ground, vout  0.

9
2 . T r a n s i sto r C i rc u i t s

Figure 2.9: A inverter built using the c m o s design..

Figure 2.10: Equivalent circuit of Figure 2.9 when v in  VDD .

The equivalent circuit once the switch model has been applied is shown
in Figure 2.10.
• (Case vin  0)
– The p m o s, having VGS,1  −VDD < Vt,p , turns on.
– The n m o s, having VGS,2  0 < Vt,n , turns off.
Therefore Vout  VDD .

Power consumption
All currents are zero in this model, so no power is consumed.

2.4 A cmos inverter chain with capacitance

Contrary to our last conclusion, inverters in real electronics certainly do consume
some power. We’ll pretend digital circuits are chains of inverters (Figure 2.11)—

10
 2.4. A c m o s inverter chain with capacitance

Figure 2.11: A chain of inverters, which is kind of similar to a computer.

Figure 2.12: An inverter taken from a chain with a capacitor modeling the next
stage.

Figure 2.13: An inverter outputting VDD with load capacitor.

although this model won’t teach you how to build a computer, it is close enough
to real c m o s networks to illustrate when and where power is expended.

We will concentrate our analysis on just one stage of the c m o s inverter

chain. A single inverter is shown in Figure 2.12, with a capacitor between vout
and ground to model the next stage’s load. Figure 2.13 shows the equivalent
circuit when the output of this inverter settles at VDD .

11
2 . T r a n s i sto r C i rc u i t s

Figure 2.14: Energy stored in a capacitor can be computed by an integral under

the V  Q/C curve.

Figure 2.15: c m o s load capacitor forced from voltage VDD to 0.

Potential energy in a capacitor

The energy stored in the capacitor when it has voltage VDD is given by the
formula
1
Ecap  2
CVDD , (2.1)
2
which can be derived by using the facts that 1) that voltage is energy per unit
charge and 2) a capacitor obeys Q  CV, and integrating through the total
∫ CVDD
charge stored in the capacitor: 0 v C dq (Figure 2.14).
When the inverter’s input changes from low to high, the output must change

12
 2.4. A c m o s inverter chain with capacitance

from VDD to 0 (Figure 2.15). That means that the load capacitor must discharge
fully, burning 21 CVDD
2
of potential energy as heat.

Total energy supplied

Even though the capacitor only stores and discharges 12 CVDD 2
, an up-down
cycle costs CVDD . This is because the voltage source must offer Q  CVDD of
2

charge at VDD energy per unit charge. Where does this go? Let’s follow the
energy as the output changes from 0 to 1 and back to 0.
1. (q C  0, v C  0)
2. Voltage source loads CVDD of charge at VDD energy per unit charge, at a
2
total expense of CVDD . Half of its energy output is burned by “parasitic”
resistance en route to the capacitor, and the other half is stored in the
capacitor.
3. (q C  CVDD , v C  VDD )
4. Transistors toggle, and the capacitor drains, generating 12 CVDD
2
of heat on
the pull-down circuit.
5. (q C  0, v C  0)

Where does the energy in a device go?

With reference to our chain-of-inverters model, power consumption in digital
devices is mainly explained by three phenomena:

• If the inverter flips every cycle at a clock speed of f s , the circuit will burn
2
f s CVDD charging its capacitors.
• Leakage: a transistor that’s “off” isn’t 100% off, and a small amount of
current flows and burns some energy.
• Short-circuit current (smaller): when the input is flipping between 0 and
1, there’s a very short instant during which both transistors may be on,
and some current flows through the momentary VDD -ground short.

13
EECS 16B Spring 2020 EECS 16B Notes

Lecture 3

Transient Analysis

(For this lecture, a m o s f e t transistor is considered to transition between “on”

and “off” at v GS  21 VDD .)
We’ll enrich our analog model of mosfets as voltage-controlled switches by
acknowledging capacitance between the mosfet’s gate and source. Figure 3.1
and Figure 3.2 depict n m o s and p m o s transistors in this model.
Figure 3.3 summarizes the three levels of abstraction with which we are
able to reason about cmos inverters. On the very left is a digital symbol for an
inverter that hides how the inverter works. In the center is the construction of an
inverter using complementary mosfets. On the right is a fairly faithful analog
representation of an inverter that will allow us to interrogate the assumptions
that, thus far, have enabled us to treat the analog circuit as a digital one.

3.1 RC transient in an inverter chain

Let’s return to the case study of a chain of inverters, this time focusing on just
two consecutive inverters. In Figure 3.4 three wires are labeled as follows:

Figure 3.1: Model of n m o s transistor with G-S capacitance.

15
3 . T r a n s i e n t A na lys i s

Figure 3.2: Model of p m o s transistor with G-S capacitance.

Figure 3.3: A c m o s inverter at three levels of abstraction.

Figure 3.4: Two consecutive c m o s inverters, part of a longer chain.

• vin is the input to the first inverter,

• vo1 is the output of the first inverter (and the input to the second), and

• vo2 is the output of the second.

The digital logic interpretation is that vo2 is the double negation of vin , that is,
vo2  vin .
We will study what happens when vin is driven by the input depicted in
Figure 3.5. It will begin having remained at 0 for a long time, change to vDD
at time t1 , then return to 0 at time t2 > t1 . Figure 3.6 shows the actions of the
switches of the first inverter’s transistors at times t1 and t2 . For the rest of this
section, we’ll just concentrate on what happens to v o1 .

16
 3.1. RC transient in an inverter chain

Figure 3.5: Input signal to the first inverter of Figure 3.4

Figure 3.6: Analog redrawing of Figure 3.4, showing switch actions of the first
inverter, as well as a distinguished node.

Before t1
As v in  0 well before t1 , we can assume that the circuit has settled, and the
output of the first inverter is vDD .

After t1 , before t2
At t1 , the pull-up switch opens, and the pull-down switch closes. KCL applied
to the distinguished (red) middle node of Figure 3.6 requires the outgoing
currents to sum to zero. Using Ohm’s Law once and the capacitor current-
voltage relationship twice, we have the following equation:

v o1 d d
+ CN v o1 + C P v o1 − v DD  0


(3.1)
RN dt dt
d 1
vo + vo  0 (3.2)
dt 1 R N (C N + C P ) 1

This is a differential equation that we will analyze with initial condition

vo1 (t1 )  VDD . For equations of this sort we will identify a characteristic
quantity τ as follows:

τ  R N (C N + C P ) (3.3)

17
3 . T r a n s i e n t A na lys i s

The International System of Units means that τ is measured in Ohm-Farads,

or seconds. For this reason, τ is called the time constant of the system. A
time constant on the order of tens of picoseconds is considered state-of-the-art
for modern devices, arising from resistances on the order of kiloOhms and
capacitances on the order of femtofarads. Rewriting using τ,

d 1
v o1  − v o1 (3.4)
dt τ

We will refer to the constant of proportionality between d

dt vo1 and vo1 as λ.

d
vo  λvo1 (3.5)
dt 1

There are many heuristic techniques to propose a solution to this differential

equation. One of them is called Separation of Variables, which involves
∫ dvo ∫
equations such as v o1  λ dt. The resulting solution form, where A is a
1

constant that remains to be determined, is all that you will need to know about
this variety of differential equation:

vo1 (t)  Ae λt (3.6)

(As an aside, you can verify that vo1 (t)  Ae λt is a solution— differentiating
both sides with respect to t results in ddt vo1 (t)  Aλe λt  λ(Ae λt ).) Our next
goal is to determine A. We can do so by choosing A to meet the initial condition
vo1 (t1 )  VDD . Substituting v o1 (t)  Ae λt ,

Ae λt1  VDD (3.7)

−λt1
A  VDD e (3.8)
 
vo1  VDD e −λt1 e λt (3.9)
 
t−t1
−
 VDD e τ
(3.10)

Figure 3.7 is a sketch of vin and vo1 after t1 and before t2 . Notice that v o1
doesn’t immediately jump to 0 like the digital model assumes. Rather, v o1
decays exponentially toward 0 at a rate predicted by τ. Discharging a capacitor
takes time, and digital devices’ clock speed is limited by how quickly binary
values settle in between logic gates.

After t2
We will try to write a differential equation describing the evolution of vo1 at
time t2 and beyond. Figure 3.6 shows that at time t2 , the pull-up switch closes,
and the pull-down switch opens. KCL applied to the same central node yields

18
 3.2. Uniqueness

Figure 3.7: Sketch of transient from t1 to t2 in Figure 3.6.

the following differential equation:

vo1 − VDD d
+ (C P + C N ) vo  0 (3.11)
RP dt 1
d 1 v DD
vo + vo  (3.12)
dt 1 R P (C P + C N ) 1 R P (C P + C N )

The previous solution for vo1 , which is valid up until time t2 , may be evaluated
at t2 for a boundary condition valid past t2 :
 
t2 −t1
−
vo1 (t2 )  VDD e τ
(3.13)

A solution for vo1 from t2 onwards is:

 
t−t2
−
v o1  VDD + vo1 (t2 ) − VDD e τP
,


(3.14)

where τP  R P (C P + C N ).

3.2 Uniqueness
We solved a differential equation. Differential equations are universal and
ubiquitous in science and engineering.
A theorem states that a large class of differential equations with boundary
conditions have unique solutions. These differential equations are of the form

d
x  f (x, t), x(0)  x0 , (3.15)
dt
where

19
3 . T r a n s i e n t A na lys i s

 
∂ f
1. for all values of t, f (x, t) is differentiable with respect to x and  ∂x (x, t) <

M for some nonnegative real number M; and
2. for all values of x, f (x, t) has a finite number of discontinuities in t in any
unit interval [t0 , t0 + 1].

If these conditions hold, then our differential equation has a unique solution.
Note that these conditions are in fact quite loose, and are more than
enough to certify that unique solutions exist to differential equations of the
form ddt x  f (x)  λx. It is important that we have proofs of existence and
uniqueness because methods such as Separation of Variables are not inherently
rigorous. Only once we have verifed that a proposed solution satisfies the
differential equation and boundary condition may we claim that it is a solution.
Because these problems have unique solutions, we may be certain that the
model we are using is physically deterministic—it tells precisely what must
happen, not just what may happen.

20
EECS 16B Spring 2020 EECS 16B Notes

Lecture 4

Differential equations with inputs

4.1 RC with exponential input

In this section we will derive, in a more hands-on way, the behavior of an RC
circuit forced by an exponential input. If you have ever used an ampwith knobs
for treble and bass (Figure 4.1), then you have interacted with two circuits
similar to the one shown in Figure 4.2. The resistor with a arrow is a variable
resistor, or potentiometer,1 that might be controlled by one of the amp’s knobs.
In Figure 4.2,
• vin represents the amp’s analog input,
• v o is used to drive the speakers after subsequent amplification, and
• R represents the setting on one of the potentiometers.
By studying the distinguished (green) node, we can write the following differ-
ential equation:
d 1 1
v o (t)  − v o (t) + vin (t). (4.1)
dt RC RC
1 Electric guitars use this circuit component, which guitarists call “pots,” to blend the pickups’

signals.

Figure 4.1: An amp with three knobs to adjust playback.

21
4 . D i f f e r e n t i a l e q uat i o n s w i t h i n p u t s

Figure 4.2: RC circuit as a filter.

We’ll constrain vin to have the following form:

vin (t)  Vin e st . (4.2)

While it seems that this form is arbitrary, it will prove insightful, because e st is
an eigenfunction for input-output behavior of this circuit, i.e. we expect
v o (t)  Vo e st . (4.3)
We can determine Vo by substituting our parameterization of v o into Equa-
tion 4.1, whose LHS. . .
d d
v o (t)  Vo e st (4.4)
dt dt
 sVo e st (4.5)
. . . is equated with the RHS:
1 1
sVo e st  − Vo e st + Vin e st . (4.6)
RC RC
Now we can isolate Vo .
1 1
sV0 + Vo  Vin (4.7)
RC RC !
 
1 1
Vo  Vin (4.8)
RC s + RC
1

Substituting λ  − RC
1
,
1
Vo  s Vin (4.9)
1− λ

All together, our solution for v o (t) is the following:

1
v o (t)  Vo e st  s Vin e st . (4.10)
1− λ

22
 4.2. General scalar differential equation

Suppose that we have an initial condition for v o at time 0.

v o | t0  v 1 (4.11)

Then our solution, taking this fact into account, will be

!
t
− RC 1 Vin e st
v o (t)  Ae + , (4.12)
RC s + RC1

where A remains to be determined, viz. by evaluating both sides at t  0:

!
1 Vin
v1  A + (4.13)
RC s + RC
1
!
1 Vin
A  v1 − . (4.14)
RC s + RC
1

This concludes our example. A solution to a linear differential equation will,

generally, have the following structure:

v(t)  v homogeneous (t) + vparticular (t), (4.15)

where v homogeneous (t) corresponds to the initial condition, and v particular (t) to
the input term.

(4.16)

4.2 General scalar differential equation

We will verify that the following general differential equation:
d
x(t)  λx(t) + u(t); x(t0 )  x0 (4.17)
dt
has the following solution, which is a sum of a homogeneous and a particular
term:
∫ t
λ(t−t0 )
x(t)  e x0 + e λ(t−τ) u(τ) dτ. (4.18)
t0

We can check the initial condition x(t0 )  x0 : the former term evaluates to
x0 and the latter to 0. Next, we can verify that ddt x(t)  λx(t) + u(t) holds by
differentiating.
  ∫ t 
d
x(t)  λe λ(t−t0 ) + u(t) + λe λ(t−τ)
u(τ) dτ (4.19)
dt t0

The two terms in curly braces sum to λx(t), so Equation 4.17 is satisfied.

23
EECS 16B Spring 2020 EECS 16B Notes

Lecture 5

Vector differential equations and

second-order circuits

5.1 Guess-and-check for RC filter with cosine input

Last lecture we derived the folowing equation modeling the input-output
properties of an amp: (where R is set by a potentiometer)
d 1 1
vout (t)  − vout (t) + vin (t); vout | t0  V (5.1)
dt RC RC
In this section we will try to determine the result in vout when v in has the
following sinusoidal form:
vin (t)  Vin cos (ωt) (5.2)
This defines a sinusoid with amplitude Vin and a frequency of ω, which is
angular frequency, in rad/ s. Angular frequency is related to cycles/second by
ω  2π f , where f is in units of Hz.

We can solve for vout by guessing that the particular
solution—-the summand
that corresponds to vin —has the form A cos ωt + φ . The second summand of
vout is the homogeneous solution, which corresponds to the initial condition. It
1
has the form Be − RC (t−t0 ) .
1
vout (t)  A cos ωt + φ + Be − RC (t−t0 )


(5.3)
Substitution into the differential equation and initial conditions result in the
following constants:
Vin
A q (5.4)
ω2 (RC)2 + 1
φ  − tan−1 (ωRC) (5.5)
B  v out | t0 − A cos ωt0 + φ


(5.6)

25
5 . V e c to r d i f f e r e n t i a l e q uat i o n s a n d s e co n d - o r d e r c i rc u i t s

Figure 5.1: Filter with two resistors and two capacitors.

5.2 Second-order filter with two capacitors

Perhaps a “better” filter could be constructed by using two capacitors and two
resistors instead of just one. Figure 5.1 depicts the proposed circuit, which is
a “second-order circuit” or “second-order” filter, with values C 1  C 2  1 µF,
R 1  13 MΩ, and R 2  21 MΩ. KCL at the two dotted-circled upper nodes yields:

d v1 − vin (t) v 1 − v2
C1 v1 + + 0 (5.7)
dt R1 R2
d v2 − v1
C2 v2 + 0 (5.8)
dt R2
In order to view this system of differential equations in state-space form, we
will isolate derivatives on the LHS and emphasize that the RHS consists of
linear combinations of v1 , v2 , and vin (t):
  !    
d 1 1 1 1 1
v1  −v1 + + v2 + vin (t) (5.9)
dt R1 R2 C1 R2 C1 R1 C1
   
d 1 1
v2  v1 − v2 (5.10)
dt R2 C2 R2 C2

Written in matrix-vector form with physical parameters substituted,

      
d v1 −5 2 v1 3
 + v (t) (5.11)
dt v2 2 −2 v2 0 in

5.3 General state-space linear ODEs

Generally, a system of linear differential equations similar to the one derived
above has the following form:

d ®
x®  A x® + bu(t), (5.12)
dt

26
 5.3. General state-space linear ODEs

where x® is a vector and A is a 2 × 2 matrix.

Suppose that A has an eigenvector v® for an eigenvalue λ. We propose the
following solution to the homogeneous problem ddt x®  A x®:

x®(t)  v®e λt (5.13)

and verify that “ ddt x®” and “A x®” for this candidate solution are equal:

d  λt 
v®e  λ v®e λt (5.14)
dt  
A v®e λt  λ v®e λt (5.15)

Detour: diagonalization of A
Let’s additionally assume that A has two linearly independent eigenvectors:

A v®1  λ 1 v®1 (5.16)

A v®2  λ 2 v®2 (5.17)

These two relationships can be expressed simultaneously using matrices that

consolidate the eigenvectors (side by side) and eigenvalues (on a diagonal):

 λ1
 
0
v®2  v®1
  
A v®1 v®2 (5.18)
0 λ2

Calling the former two matrices V and the latter Λ,

AV  VΛ (5.19)

Because we chose two linearly independent eigenvectors to constitute V, V is

invertible. Stating A in terms of its eigenvectors and eigenvalues is called the
eigenvector-eigenvalue decomposition of A:

A  VΛV −1 (5.20)

Second-order homogeneous solution from modes

Generally, x®(0) will be a linear combination of v®1 and v®2 :

x®(0)  x̃1 (0) v®1 + x̃2 (0) v®2 (5.21)

These coefficients can be solved by inverting V:

 
x̃1 (0)
 V −1 x®(0) (5.22)
x̃2 (0)

27
5 . V e c to r d i f f e r e n t i a l e q uat i o n s a n d s e co n d - o r d e r c i rc u i t s

Figure 5.2: Decomposition of x® along eigenbasis directions v®1 and v®2 .

We can build a homogeneous solution for x®(t) by superposing one-dimensional

solutions in each eigenvector’s respective direction:

x®(t)  v®1 e λ1 t x̃1 (0) + v®2 e λ2 t x̃2 (0) (5.23)

e λ1 t
  
0 x̃1 (0)
V (5.24)
0 e λ2 t x̃2 (0)

To verify the initial condition, we can observe that the diagonal matrix of
exponentials becomes an identity matrix at time 0:

  
 1 0 x̃1 (0)
x®(0)  v®1 ,

v®2 (5.25)
0 1 x̃2 (0)

which is true by construction (Equation 5.21).

Modal decomposition
In the previous section, we wrote x®(0) in eigenbasis-aligned coordinates x̃1 (0)
and x̃2 (0). In this section, we will follow x̃1 and x̃2 as functions of t. Recall that
the eigenbasis-aligned coordinates are defined as follows:

 
 x̃1
x®  v®1 ®
 V x̃.

v®2 (5.26)
x̃2

In reverse,

x̃®  V −1 x®. (5.27)

28
 5.3. General state-space linear ODEs

®
We can use the Chain Rule to obtain a differential equation for x̃:

d ® d
x̃  V −1 x (5.28)
dt dt
 
®
 V −1 A x® + bu (5.29)
®
 V −1 AV x̃® + V −1 bu (5.30)
λ1
 
0 ® ® ®
 x̃ + b̃u, b̃  V −1 b (5.31)
0 λ2

This vector differential equation is effectively scalar in each variable, in which

scalar techniques can be applied separately. The separation of x into its
eigenbasis-aligned components is called modal decomposition; x̃1 v®1 and x̃2 v®2 are
the two modes of this system.

29
EECS 16B Spring 2020 EECS 16B Notes

Lecture 6

Diagonalization to solve vector

differential equations

In the last lecture, a second-order low-pass filter circuit using two resistors and
two capacitors led us to the following differential equation:
d ®
x®  A x® + bu, (6.1)
dt
 
v (t)
where x®  1 and x®(0) or x®(t0 ) is known. We represented x® as a linear
v2 (t)
combination of A’s eigenvectors v®1 (for eigenvalue λ 1 ) and v®2 (for eigenvalue
λ2 ):
x®  v®1 x̃ 1 + v®2 x̃2 (6.2)
 
 x̃1
 v®1  V x̃®

v®2 (6.3)
x̃2
We will assume that λ1 and λ 2 are distinct, which implies that A has an
invertible matrix of linearly independent eigenvectors V.We established that
λ
 
0
AV  VΛ, V  v®1 v®2 , Λ 1 .
 
(6.4)
0 λ2

® and
These findings are summarized in Figure 6.1, which shows how x®, A x®, x̃,
Λx̃® are related by matrix multiplication (along arrows).

6.1 Solution technique

A system
d ®
x®  A x® + bu; x®(t0 ) (6.5)
dt
is solved as follows:

31
6 . D i ag o na l i z at i o n to s o lv e v e c to r d i f f e r e n t i a l e q uat i o n s

Figure 6.1: Illustration of multiplication actions of A, Λ, V, and V −1 .

1. Compute eigenvalues λ 1 and λ 2 of A, as well as their respective eigenvec-

tors v®1 and v®2 .

2. Construct V  v®1 v®2 and define x̃®  V −1 x.

 

λ
 
0
3. Construct Λ  1 and b̃  V −1 b. Solve the differential equation
0 λ2
d ®
x̃  Λx̃® + b̃u with initial condition x̃(t0 )  V −1 x(t0 ). (More on this
dt
later.)

®
4. Recover a solution for x® using x®  V x̃.

6.2 Numerical example from RCRC circuit

Equation 5.11 captured a second-order low-pass filter using
   
−5 2 3
A and b®  . (6.6)
2 −2 0
 
v1
We will solve the differential equation for x®  using the technique of the
v2
previous section.

Eigenvalues and eigenvectors

We will solve for eigenvectors λ as roots of det (λI − A), the characteristic
polynomial of A.

λ+5
 
−2
det  λ 2 + 7λ + 6  0 (6.7)
−2 λ+2

32
 6.2. Numerical example from RCRC circuit

This quadratic equation in the indeterminate λ is called the characteristic equation

of A. It has the following roots:

λ 1  −1; λ 2  −6. (6.8)

Next we will solve for an eigenvector belonging to eigenvalue λ 1 , by choosing a

nonzero vector from the null space of λ 1 I − A:
 
4 −2
λ1 I − A  (6.9)
−2 1
 
1
v®1  (6.10)
2

. . . and, mutatis mutandis, for λ 2 :

 
−1 −2
λ2 I − A  (6.11)
−2 −4
 
2
v®2  (6.12)
−1

Differential equation in new coordinates

In our example,
 
1 2
V , so (6.13)
2 −1
1 2

−1
V  5
2
5 . (6.14)
5 − 15

Our differential equation in x̃® will be

d ® ®
x̃  Λ x̃® + V −1 bu (6.15)
dt   3
−1 0 ®
 x̃ + 56 . (6.16)
0 −6 5

With t0  0, x̃® is solved as follows:

®  homogeneous solution + particular solution



x̃(t) (6.17)
" #
e λ1 t e λ1 (t−τ)
  ∫ t
0 ® + 0 ®
 x̃(0) b̃u(τ) dτ, (6.18)
0 e λ2 t 0 0 e λ2 (t−τ)

viz., in individual components,

( ∫t
x̃1 (t)  e λ1 t x̃1 (0) + e λ1 (t−τ) b̃ 1 u(τ) dτ
∫0t (6.19)
x̃2 (t)  e λ2 t x̃2 (0) + 0
e λ2 (t−τ) b̃ 2 u(τ) dτ

33
6 . D i ag o na l i z at i o n to s o lv e v e c to r d i f f e r e n t i a l e q uat i o n s

Figure 6.2: Parallels between capacitors and inductors.

Solution in original coordinates

A solution for x®(t) may be reconstituted from eigenbasis-aligned coordinates
using the following equation:
 
 x̃1 (t)
x®(t)  v®1 .

v®2 (6.20)
x̃2 (t)

6.3 Introduction to inductors

Inductors are a branch element that are analogous to capacitors. Figure 6.2
compares them with capacitors, and the parallels are repeated below.

q  charge (Coulomb) λ  flux (Weber = Volt-second) (6.21)

d d
qi λv (6.22)
dt dt
q λ
v i (6.23)
C L
1 2 1 2
EC  Cv EL  Li (6.24)
2 2

34
 6.4. Example: RL circuit

Figure 6.3: RL circuit, which is similar to an RC circuit (cf. Figure 4.2).

6.4 Example: RL circuit

Figure 6.3 shows a circuit with a time-varying voltage source, a resistor, and an
inductor. KCL at the marked upper right node yields
v − vin
+ i  0. (6.25)
R
In addition, from the current-voltage relationship of an inductor,

d
L i  v. (6.26)
dt
d
Eliminating v and isolating i, we have
dt
d R vin
i− i+ . (6.27)
dt L L
The state variable for an inductor is i, and this differential equation may be
solved the same way we solved RC circuits.

35