DIGI - 260

Lab 8
Digital to Analog Conversion
Rev 04 By Gianna Smith Mar 23, 2023

Name :

Lab Objectives:
1. Predict the analog output from a current-mode DAC.
2. Construct a DAC circuit and characterize its performance.
3. Add output conditioning circuitry (ie, op-amp based I-V converter) to enable
mapping a DAC output to a specified range of voltages.
4. Sample a sinusoid to a specified discretization levels.
5. Use VHDL to create a function generator.

Duration:
Two 3-hour lab periods.

Equipment Required:
- Alpha prototyping board.
- Bench power supply
- Oscilloscope
- MAX 7000AE CPLD
- DAC 0808
- LM 741 op amp
- Resistors : 4.7 k (x3), others TBC

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Procedure B1 : Construct A Current-Mode DAC Circuit

B-1-1. Install pin numbers on the diagram in Figure 1.

B-1-2. Build the circuit in Figure1. Install decoupling capacitors on the supply pins
as well as on the compensation pin 16. You can use the Alpha board +5V for
Vcc. You will need to supply the -12 V using the bench power supply.
Be very careful...reverse polarity will destroy the IC !
Use the Alpha board logic switches for the DAC inputs. Use the Alpha logic
indicators to monitor the binary input codes.

Notice from the figure that RL = R1 = R2 = 4.7 k.

Alpha Logic Switches and Indicators

D
GN

Figure 1

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B-1-3. Write out the expression for the DAC output current found on page 7 of the
National Semiconductor DAC 0808 datasheet (note that National
Semiconductor was acquired by Texas Instruments but the online
datasheet stills says National Semiconductor).

B-1-4. Use this expression to predict the theoretical output current from the DAC and
the resulting output voltage with R L = 4.7k for the digital codes indicated in
Table 1. Show your calculations on the following page.

Note: Compute your theoretical values to four sig figs of accuracy

B-1-5. Measure the actual output voltages from the DAC for the digital codes listed
in Table 1 using the bench Voltmeter.

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Digital code I out V out V out

MSB …..LSB Theoretical Theoretical Measured

0000 0000

0000 0001

0000 0010

0000 0100

0000 1000

0001 0000

0010 0000

0100 0000

1111 1100

1111 1101

1111 1110

1111 1111

Table 1

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Calculations :

Instructor Demo / Sign-

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Procedure B2 : Output Loading

B-2-1. Begin by setting the DAC output to its maximum value by applying a binary
input code of 1111 1111 to the DAC inputs. Connect the downstream loads
listed below to the DAC circuit in Figure 1 (ie, in parallel to the 4.7 k
I-V
converter resistor R L). Measure the output voltage for each case with
the bench DC Voltmeter :

Downstream Load V out

Measured
( RD downstream )

∞ 
(ie., open circuit downstream
from I-V converter)

100 k

10 k

1 k

470 

330 

Instructor Demo / Sign-

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Procedure B3 : Add An Op-Amp I-V Converter to the DAC Output

B-3-1. Design an op amp I-V converter to replace the I-V load resistor RL in
Figure 1 that results in an output voltage range of exactly 0V to +10V for
a digital input of 0000 0000 to 1111 1111, respectively. Use a 741C op-
amp using supplies of +/- 12V (you will need to use the bench power supply
to feed in the +/- 12V ). Note that the calculated value of the feedback
resistor must be calculated to four sig figs of accuracy. Show op-amp pin
numbers on your design below. Also write down the transfer relation for the
I-V converter in the space provided.

Op-Amp V-I Converter Design :

I-V Converter Transfer Relation

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B-3-2. Replace the RL I-V converter in Figure 1 with the op-amp I-V converter you
designed in B-3-1. Note that the value of the feedback resistor must be precise
in its value to four sig figs of accuracy and so you will have to go to some
trouble to contrive this value by means of series and parallel combinations of
fixed resistors.

Use of an adjustable potentiometer is not a good idea for this since pots are
usually not accurate to this level of precision. Show your final solution to this
problem below together with a measured value of the contrived resistance:

Final Measured Resistance:

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Now re-test the effect of adding downstream loads to the DAC circuit which
now has the op-amp I-V converter instead of RL. Again, begin by applying a
constant binary input code of 1111 1111 to the DAC input. Then measure V out
from the op-amp amp output for the various downstream load resistances
listed below :

Downstream Load V out

Measured
( RD downstream )

∞ 
(ie., open circuit downstream
from I-V converter)

100 k

10 k

1 k

470 

330 

B-3-4. What three improvements does the op-amp I-V converter bring to the basic
circuit of Figure 1?

Instructor Demo / Sign-Off

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Procedure B4 : Discretization of a Sinusoidal Waveform

B-4-1. You will be designing a VHDL function generator to produce four types of
output waveforms similar to other commercial function generators:

1. Arbitrary DC level output

2. Square-wave
3. Triangle wave
4. Sinusoidal wave

All of these modes will produce an output voltage from 0V to 10 V with 8-bit
precision. The first three of these are relatively straightforward to code in
VHDL but the sinusoidal output signal will need to be digitized by means of
a look-up table.

As a preliminary step to this, consider the figure below showing one cycle of
the final unipolar sinusoidal output signal after the DAC input code has been
converted to current and the current then transformed to a voltage by the I-V
op-amp circuit.

Our objective is to discretize the sinusoid and find the binary input codes for
the DAC which can be entered into VHDL code. A discretization in time of
of 40 samples per period is chosen as a reasonable compromise between the
amplitude precision of the sinusoidal waveform and the complexity of the
VHDL look-up table. As seen in Figure 2, the 40 samples per period result in
the first sample having a decimal value of 5.000 V, a minimum value of
0.000V and a maximum value of V max = 10.000 V after passing through the
DAC and I-V converter.

Figure 2

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In order to facilitate the discretization process, Figure 3 shows the sinusoidal

waveform normalized to a DAC input code running from 00 to FF. Since the
basic equation of a sinusoid , ie,

y = A sin ( t ) = A sin ( (2 / T) t )

runs from a minimum value of -A to a maximum of +A (and therefore a peak-

to-peak value of 2A) we must first adapt it to run from 0.000 to 1.000 (decimal).

If we can find such an equation for the sinusoid then it is an easy matter to find
the required binary codes for the DAC by simply multiplying the decimal values
of the sinusoid at the sampling points by the decimal value 255, converting the
result to binary and finally truncating the number to the closest integer binary
value.

Figure 3

In terms of its time axis values, note that Figure 3 is presented in terms of
sample number, not time in seconds. The basic sine equation above must
therefore also be adapted in respect to the sin function argument. To this end
notice that a time axis could be created by the transformation

t = ( N - 1)

where N is the sample number, and T = 40s. The function can then be evaluated
using a calculator for integer time values from 0s through 39s.

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Derive an equation for the sinusoid in Figure 3 which runs from a minimum
value of 0.000 to a maximum of 1 over the sampling range shown in Figure 3 :

Check the validity of your equation above by evaluating your expression (by
Hand) for the following values of N .

N=1:

N = 11 :

N = 15 :

N = 21 :

N = 36 :

N = 41 :

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Fill out the following chart with the decimal values presented to the fifth decimal
place (ie, 0.XXXXX except the maximum value which would be 1.00000) and using
hexadecimal notation for the closest 8-bit binary approximation.

Binary Values for Sampled Sinusoid

Sample Decimal Closest 8-bit binary value Sample Decimal Closest 8-bit binary value
Table 2 Value
# Value using Hex notation # using Hex notation

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Instructor Demo / Sign-Off
21
2 22

3 23

4 24

5 25
6 26

7 27

8 28

9 29

10 30

11 31

12 32

13 33

14 34

15 35

16 36

17 37

18 38

19 39

20 40

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Procedure B5 : Design and Build a VHDL-Based Function Generator

B-4-1. Design and build a VHDL-based function generator controller having the
following specification and pinout :

1)
Power supply is VDD = +3.3 V DC.
2)
Digital output pins are A 1 (MSB) to A 7 (LSB) and feed into the DAC
0808 designed in the previous sections.
3)
Input pin CLK is the system clock which is derived from the Alpha clock.
4)
Lines DCBA (where D is MSB) are asynchronous digital input pins that
control the DC output level when in Mode 00.
5)
The function generator controller supports four modes of operation
controlled by two active-HIGH mode select pins M1 and M2 as follows :

M2 M1 Mode

0 0 DC output voltage
0 1 Square Wave

1 0 Triangle Wave

1 1 Sine Wave

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When in “Sine Wave” mode the sinusoid executes one cycle per 40 Alpha
clock pulses.
When in “Triangle Wave” mode the waveform counts up for 20 Alpha clock
pulses and down for 20 Alpha clocks (ie, a symmetrical triangle wave.
When in “Square Wave” mode the output is +10 V for 20 Alpha clock pulses
and 0V for 20 Alpha clocks (ie, 50% duty cycle square wave).
When in “DC Voltage” mode the output voltage is determined by the
asynchronous digital inputs on DCBA.

6)
Active-HIGH output enable control. When OE is HIGH the digital output
lines A1 thru A8 are enabled. When OE is LOW then all output lines are
LOW.

Instructor Demo / Sign-Off