DSDV MODULE -3

The Basic Latch

 Basic latchis a feedback connection of two NOR gates or two NAND gates
 It can store one bit of information
It can be set to 1 using the S input and reset to 0 using the R input

The Gated Latch

 Gated latch is a basic latch that includes input gating and a control signal
 The latch retains its existing state when the control input is equal to 0
 Its state may be changed when the control signal is equal to 1. In our
discussion we referred to the control input as the clock
 We consider two types of gated latches:
o Gated SR latch uses the S and R inputs to set the latch to 1 or reset it to
0, respectively.
o Gated D latch uses the D input to force the latch into a state that has the
same logic value as the D input.

Gated S/R Latch

 Gated D Latch

Setup and Hold Times

 Setup Time tsu
The minimum time that the input signal must be stable prior to the edge of
the clock signal.
 Hold Time th
The minimum time that the input signal must be stable after the edge of the
clock signal.
Flip-Flops
o A flip-flop is a storage element based on the gated latch principle
o It can have its output state changed only on the edge of the controlling
clock signal
o We consider two types:
o Edge-triggered flip-flop is affected only by the input values present
when theactive edge of the clock occurs
o Master-slave flip-flop is built with two gated latches
o The master stage is active during half of the clock cycle, and the slave
stage is active during the other half.
 o The output value of the flip-flop changes on the edge of the clock that
activates the transfer into the slave stage.

Master Slave flip flop are the cascaded combination of two flip-flops among which
the first is designated as master flip-flop while the next is called slave flip-flop
(Figure 1). Here the master flip-flop is triggered by the external clock pulse train
while the slave is activated at its inversion i.e. if the master is positive edge-
triggered, then the slave is negative-edge triggered and vice-versa. This means that
the data enters into the flip-flop at leading/trailing edge of the clock pulse while it is
obtained at the output pins during trailing/leading edge of the clock pulse. Hence a
master-slave flip-flop completes its operation only after the appearance of one full
clock pulse for which they are also known as pulse-triggered flip-flops.

The internal structure of a master-slave JK flip-flop interms of NAND gates and an

inverter (to complement the clock signal) is shown in Figure 2. Here it is seen that
the NAND gate 1 (N1) has three inputs viz., external clock pulse (Clock), input J and
output Q̅; while the NAND gate 2 (N2) has external clock pulse (Clock), input K and
output Q as its inputs.

Further the outputs of N1 and N2 gates are connected as the inputs for the criss-cross
connected gates N3 and N4. These four gates together (N1, N2, N3 and N4) form the
master-part of the flip-flop while a similar arrangement of the other four gates N 5,
N6, N7 and N8 form the slave-part of it.

From figure it is also evident that the slave is driven by the outputs of the master (M 1
and M2), which is in accordance with its name master-slave flip-flop. Further the
master is active during the positive edge of the clock due to which M 1 and M2 change
their states; depending on the values of J and K. However at this instant the outputs
of the overall system (master-slave JK flip-flop) remains unchanged as the slave will
be inactive due to positive-edge of the clock pulse. Similar to this, the slave decides
on its outputs Q and Q̅ depending on its inputs M1 and M2, during the negative edge
of the clock during which the master will be inactive.

The truth table corresponding to the working of the flip-flop shown in Figure 2 is
given by Table I. Here it is seen that the outputs at the master-part of the flip-flop
(data enclosed in red boxes) appear during the positive-edge of the clock (red
arrow). However at this instant the slave-outputs remain latched or unchanged. The
same data is transferred to the output pins of the master-slave flip-flop (data
enclosed in blue boxes) by the slave during the negative edge of the clock pulse
(blue arrow). The same principle is further emphasized in the timing diagram of
master-slave flip-flop shown by Figure 3. Here the green arrows are used to indicate
that the slave-output is nothing but the master-output delayed by half-a-clock cycle.
Moreover it is to be noted that the working of any other type of master-slave flip-
flop is analogous to that of the master slave JK flip-flop explained here.
Excitation Tables
Conversions of flip-flops
Registers and Counters

• An n-bit register is a cascade of n flip-flops and can store an n-bit binary data

• A counter can count occurrences of events and can generate timing intervals for
control purposes

A Simple Shift Register

Parallel-Access Shift Register

Shift registers:

In digital circuits, a shift register is a cascade of flip-flops sharing the same clock, in
which the output of each flip-flop is connected to the "data" input of the next flip-
flop in the chain, resulting in a circuit that shifts by one position the "bit array"
stored in it, shifting in the data present at its input and shifting out the last bit in the
array, at each transition of the clock input. More generally, a shift register may be
multidimensional, such that its "data in" and stage outputs are themselves bit arrays:
this is implemented simply by running several shift registers of the same bit-length
in parallel.

Shift registers can have both parallel and serial inputs and outputs. These are often
configured as serial-in, parallel-out (SIPO) or as parallel-in, serial-out (PISO). There
are also types that have both serial and parallel input and types with serial and
parallel output. There are also bi- directional shift registers which allow shifting in
both directions: L→R or R→L. The serial input and last output of a shift register can
also be connected to create a circular shift register
Shift registers are a type of logic circuits closely related to counters. They are
basically for the storage and transfer of digital data.

Buffer register:

The buffer register is the simple set of registers. It is simply stores the binary word.
The buffer may be controlled buffer. Most of the buffer registers used D Flip-flops.

Figure: logic diagram of 4-bit buffer register

The figure shows a 4-bit buffer register. The binary word to be stored is applied to
the data terminals. On the application of clock pulse, the output word becomes the
same as the word applied at the terminals. i.e., the input word is loaded into the
register by the application of clock pulse.
When the positive clock edge arrives, the stored word becomes:
Q4Q3Q2Q1=X4X3X2X1
Q=X
Controlled buffer register:
If goes LOW, all the FFs are RESET and the output becomes, Q=0000.
When is HIGH, the register is ready for action. LOAD is the control input. When
LOAD is HIGH, the data bits X can reach the D inputs of FF‘s.
Q4Q3Q2Q1=X4X3X2X1 Q=X
When load is low, the X bits cannot reach the FF‘s.

Data transmission in shift registers:

A number of ff‘s connected together such that data may be shifted into and shifted
out of them is called shift register. data may be shifted into or out of the register in
serial form or in parallel form. There are four basic types of shift registers.
1. Serial in, serial out, shift right, shift registers
2. Serial in, serial out, shift left, shift registers
3. Parallel in, serial out shift registers
4. Parallel in, parallel out shift registers

Serial IN, serial OUT, shift right, shift left register:

The logic diagram of 4-bit serial in serial out, right shift register with four stages.
The register can store four bits of data. Serial data is applied at the input D of the
first FF. the Q output of the first FF is connected to the D input of another FF. the
data is outputted from the Q terminal of the last FF.

When serial data is transferred into a register, each new bit is clocked into the first
FF at the positive going edge of each clock pulse. The bit that was previously stored
by the first FF is transferred to the second FF. the bit that was stored by the Second
FF is transferred to the third FF.

Serial-in, parallel-out, shift register:

In this type of register, the data bits are entered into the register serially, but the data
stored in the register is shifted out in parallel form.
Once the data bits are stored, each bit appears on its respective output line and all
bits are available simultaneously, rather than on a bit-by-bit basis with the serial
output. The serial-in, parallel out, shift register can be used as serial-in, serial out,
shift register if the output is taken from the Q terminal of the last FF.

Parallel-in, serial-out, shift register:

For a parallel-in, serial out, shift register, the data bits are entered simultaneously
into their respective stages on parallel lines, rather than on a bit-by-bit basis on one
line as with serial data bits are transferred out of the register serially. On a bit-by-bit
basis over a single line.
There are four data lines A,B,C,D through which the data is entered into the register
in parallel form. The signal shift/ load allows the data to be entered in parallel form
into the register and the data is shifted out serially from terminalQ4 Parallel-in,
parallel-out, shift register
In a parallel-in, parallel-out shift register, the data is entered into the register in
parallel form, and also the data is taken out of the register in parallel form. Data is
applied to the D input terminals of the FF‘s. When a clock pulse is applied, at the
positive going edge of the pulse, the D inputs are shifted into the Q outputs of the
FFs. The register now stores the data. The stored data is available instantaneously
for shifting out in parallel form.

Bidirectional shift register:

A bidirectional shift register is one which the data bits can be shifted from left to
right or from right to left. A fig shows the logic diagram of a 4-bit serial-in, serial
out, bidirectional shift register. Right/left is the mode signal, when right /left is a 1,
the logic circuit works as a shift-register.the bidirectional operation is achieved by
using the mode signal and two NAND gates and one OR gate for each stage.
A HIGH on the right/left control input enables the AND gates G1, G2, G3 and G4
and disables the AND gates G5,G6,G7 and G8, and the state of Q output of each FF
is passed through the gate to the D input of the following FF. when a clock pulse
occurs, the data bits are then effectively shifted one place to the right. A LOW on the
right/left control inputs enables the AND gates G5, G6, G7 and G8 and disables the
And gates G1, G2, G3 and G4 and the Q output of each FF is passed to the D input
of the preceding FF. when a clock pulse occurs, the data bits are then effectively
shifted one place to the left. Hence, the circuit works as a bidirectional shift register

Figure: logic diagram of a 4-bit bidirectional shift register

Universal shift register:

A register is capable of shifting in one direction only is a unidirectional shift register.
One that can shift both directions is a bidirectional shift register. If the register has
both shifts and parallel load capabilities, it is referred to as a universal shift registers.
Universal shift register is a bidirectional register, whose input can be either in serial
form or in parallel form and whose output also can be in serial form or I parallel
form.
The most general shift register has the following capabilities.

1. A clear control to clear the register to 0

2. A clock input to synchronize the operations
3. A shift-right control to enable the shift-right operation and serial input and output
lines associated with the shift-right
4. A shift-left control to enable the shift-left operation and serial input and output
lines associated with the shift-left
5. A parallel loads control to enable a parallel transfer and the n input lines
associated with the parallel transfer
6. N parallel output lines
7. A control state that leaves the information in the register unchanged in the
presence of the clock.

A universal shift register can be realized using multiplexers. The below fig shows
the logic diagram of a 4-bit universal shift register that has all capabilities. It consists
of 4 D flip-flops and four multiplexers. The four multiplexers have two common
selection inputs s1 and s0. Input 0 in each multiplexer is selected when S1S0=00,
input 1 is selected when S1S0=01 and input 2 is selected when S1S0=10 and input 4 is
selected when S1S0=11. The selection inputs control the mode of operation of the
register according to the functions entries. When S1S0=0, the present value of the
register is applied to the D inputs of flip-flops. The condition forms a path from the
output of each flip-flop into the input of the same flip-flop. The next clock edge
transfers into each flip-flop the binary value it held previously, and no change of
state occurs. When S1S0=01, terminal 1 of the multiplexer inputs have a path to the
D inputs of the flip-flop. This causes a shift-right operation, with serial input
transferred into flip-flopA4. When S1S0=10, a shift left operation results with the
other serial input going into flip-flop A1. Finally when S1S0=11, the binary
information on the parallel input lines is transferred into the register simultaneously
during the next clock cycle
 Figure: logic diagram 4-bit universal shift register

Function table for the register:

Counters:
Counter is a device which stores (and sometimes displays) the number of times
particular event or process has occurred, often in relationship to a clock signal. A
Digital counter is a set of flip flops whose state change in response to pulses applied
at the input to the counter. Counters may be asynchronous counters or synchronous
counters. Asynchronous counters are also called ripple counters
In electronics counters can be implemented quite easily using register-type circuits
such as the flip-flops and a wide variety of classifications exist:
Asynchronous (ripple) counter – changing state bits are used as clocks to subsequent
state flip-flops
 Synchronous counter – all state bits change under control of a singleclock
 Decade counter – counts through ten states per stage
 Up/down counter – counts both up and down, under command of a control
input
 Ring counter – formed by a shift register with feedback connection in a ring
 Johnson counter – a twisted ring counter Cascaded counter
 Modulus counter.

Each is useful for different applications. Usually, counter circuits are digital in
nature, and count in natural binary Many types of counter circuits are available as
digital building blocks, for example a number of chips in the 4000 series implement
different counters.
Occasionally there are advantages to using a counting sequence other than the
natural binary sequence such as the binary coded decimal counter, a linear feed-
back shift register counter, or a gray-code counter.
Counters are useful for digital clocks and timers, and in oven timers, VCR clocks,
etc.

Asynchronous counters:
An asynchronous (ripple) counter is a single JK-type flip-flop, with its J (data) input
fed from its own inverted output. This circuit can store one bit, and hence can count
from zero to one before it overflows (starts over from 0). This counter will increment
once for every clock cycle and takes two clock cycles to overflow, so every cycle it
will alternate between a transition from 0 to 1 and a transition from 1 to 0. Notice
that this creates a new clock with a 50% duty cycle at exactly half the frequency of
the input clock. If this output is then used as the clock signal for a similarly arranged
D flip-flop (remembering to invert the output to the input), one will get another 1 bit
counter that counts half as fast. Putting them together yields a two-bit counter:
Two-bit ripple up-counter using negative edge triggered flip flop:
Two bit ripple counter used two flip-flops. There are four possible states from 2 – bit
up- counting I.e. 00, 01, 10 and 11.
· The counter is initially assumed to be at a state 00 where the outputs of the tow
flip-flops are noted as Q1Q0. Where Q1 forms the MSB and Q0 forms the LSB.

· For the negative edge of the first clock pulse, output of the first flip-flop FF1 toggles
its state. Thus Q1 remains at 0 and Q0 toggles to 1 and the counter state are now
read as 01.

· During the next negative edge of the input clock pulse FF1 toggles and Q0 = 0. The
output Q0 being a clock signal for the second flip-flop FF2 and the present transition
acts as a negative edge for FF2 thus toggles its state Q1 = 1. The counter state is now
read as 10.

· For the next negative edge of the input clock to FF1 output Q0 toggles to 1. But this
transition from 0 to 1 being a positive edge for FF2 output Q1 remains at 1. The
counter state is now read as 11.

· For the next negative edge of the input clock, Q0 toggles to 0. This transition from 1
to 0 acts as a negative edge clock for FF2 and its output Q1 toggles to 0. Thus the
starting state 00 is attained. Figure shown below
Two-bit ripple down-counter using negative edge triggered flip flop:

A 2-bit down-counter counts in the order 0,3,2,1,0,1…….,i.e, 00,11,10,01,00,11

…..,etc. the above fig. shows ripple down counter, using negative edge triggered J-K
FFs and its timing diagram.
• For down counting, Q1‘ of FF1 is connected to the clock of Ff2. Let initially all the
FF1 toggles, so, Q1 goes from a 0 to a 1 and Q1‘ goes from a 1 to a 0.
• The negative-going signal at Q1‘ is applied to the clock input of FF2, toggles Ff2
and,therefore, Q2 goes from a 0 to a 1.so, after one clock pulse Q2=1 and Q1=1, I.e.,
the state of the counter is 11.
• At the negative-going edge of the second clock pulse, Q1 changes from a 1 to a 0
and Q1‘ from a 0 to a 1.
• This positive-going signal at Q1‘ does not affect FF2 and, therefore, Q2 remains at
a 1.Hence , the state of the counter after second clock pulse is 10
• At the negative going edge of the third clock pulse, FF1 toggles. So Q1, goes from
a 0 to a 1 and Q1‘ from 1 to 0. This negative going signal at Q1‘ toggles FF2 and, so,
Q2 changes from 1 to 0, hence, the state of the counter after the third clock pulse is
01.
• At the negative going edge of the fourth clock pulse, FF1 toggles. So Q1, goes from
a 1 to a 0 and Q1‘ from 0 to 1. . This positive going signal at Q1‘ does not affect FF2
and, so, Q2 remains at 0, hence, the state of the counter after the fourth clock pulse is
00.
Counters in Shift Registers

Basically, counters in shift registers are classified into two types such as ring counter
as well as Johnson counter.
Ring Counter
Basically, this is a shift register counter in which the first FF output can be connected
to the second FF and so on The last FF output is once more fed back to the first flip
flop input, that is ring counter.
The data model in the shift register will move until the CLK pulses are applied. The
circuit diagram of the ring counter is shown above. This circuit can be designed with
4-FFs, so the data model will do again after each 4- CLK pulses as shown in the
following truth table. Generally, this counter is used for self-decoding, there is no
additional decoding is not necessary to decide the status of the counter.

Johnson Counter
Basically, this is a shift register counter in which the first FF output can be allied to
the second FF and so on and the last flip flop’s inverted output can be once more fed
back to the first flip flop’s input.
The circuit diagram of the Johnson Counter is shown above, and this circuit can be
designed with 4-D flip-flops. A Johnson counter with n-stage defers a calculate
series of 2n dissimilar states. Because this circuit can be built with 4-FFs, and the
data model will do again each 8-CLK pulses as shown in the following truth table.

The main benefit of this counter is, it requires n-number of FFs evaluated to the ring
counter to move a given data for producing a series of 2n states.

Applications of Shift Registers

The shift register applications include the following.

 The main benefit of this counter is, it requires n-number of FFs evaluated to the
ring counter to move a given data for producing a series of 2n states.
 A PISO shift register is used for converting parallel to serial data.
 The SISO and PIPO shift registers are used for generating time delay toward
digital circuits.
 These registers are used for data transfer, manipulation and data storage.
 The SIPO register is used for converting serial to parallel data therefore in
communication lines
Design of synchronous counters:
For a systematic design of synchronous counters. The following procedure is used.
Step 1:State Diagram: draw the state diagram showing all the possible states state
diagram which also be called nth transition diagrams, is a graphical means of
depicting the sequence of states through which the counter progresses.
Step2: number of flip-flops: based on the description of the problem, determine the
required number n of the flip-flops- the smallest value of n is such that the number
of states N≤2n--- and the desired counting sequence.
Step3: choice of flip-flops excitation table: select the type of flip-flop to be used and
write the excitation table. An excitation table is a table that lists the present state (ps)
the next state(ns) and required excitations.
Step4: minimal expressions for excitations: obtain the minimal expressions for the
excitations of the FF using K-maps drawn for the excitation of the flip-flops in terms
of the present states and inputs.
Step5: logic diagram: draw a logic diagram based on the minimal expressions
Design of a synchronous 3-bit up-down counter using JK flip-flops:
Step1: determine the number of flip-flops required. A 3-bit counter requires three
FFs. It has 8 states (000,001,010,011,101,110,111) and all the states are valid. Hence no
don‘t cares. For selecting up and down modes, a control or mode signal M is
required. When the mode signal M=1 and counts down when M=0. The clock signal
is applied to all the FFs simultaneously.
Step2: draw the state diagrams: the state diagram of the 3-bit up-down counter is
drawn as
Step3: select the type of flip flop and draw the excitation table: JK flip-flops are
selected and the excitation table of a 3-bit up-down counter using JK flip-flops is
drawn as shown in fig.

Step4: obtain the minimal expressions: From the excitation table we can conclude
that J1=1 and K1=1, because all the entries for J1and K1 are either X or 1. The K-maps
for J3, K3,J2 and K2 based on the excitation table and the minimal expression
obtained from them are shown in fig.

Step5: draw the logic diagram: a logic diagram using those minimal expressions can
be drawn as shown in fig.
Design of a synchronous modulo-6 gray cod counter:
Step 1: the number of flip-flops: we know that the counting sequence for a modulo-6
gray code counter is 000, 001, 011, 010, 110, and 111. It requires n=3FFs (N≤2n, i.e.,
6≤23). 3 FFs can have 8 states. So the remaining two states 101 and 100 are invalid.
The entries for excitation corresponding to invalid states are don‘t cares.
Step2: the state diagram: the state diagram of the mod-6 gray code converter is
drawn as shown in fig.

Step3: type of flip-flop and the excitation table: T flip-flops are selected and the
excitation table of the mod-6 gray code counter using T-flip-flops is written as
shown in fig.
Step4: The minimal expressions: the K-maps for excitations of FFs T3,T2,and T1 in
terms of outputs of FFs Q3,Q2, and Q1, their minimization and the minimal
expressions for excitations obtained from them are shown if fig

Step5: the logic diagram: the logic diagram based on those minimal expressions is
drawn as shown in fig.
 MOD 10 Synchronous Counter using D Flip-flop

Step 1: Find the number of Flip-flops needed

The number of Flip-flops  required can be determined by using the following

equation: M ≤ 2N 

where, M is the MOD number and N is the number of required flip-flops.

Here, MOD number is equal to 10. i.e., M = 10

Therefore, 10 ≤ 2N => N = 4

Therefore, to design a MOD 10 or Decade Counter, 4 flip-flops will be required.

Step 2: Write the excitation table of the flip-flop

Excitation table of D flip-flop is:

Step 3: Write the circuit state table by using excitation table

Circuit state table for designing MOD 10 Synchronous Counter using D Flip-

flop will be
Step 4: Prepare K Map for each flip-flop input in terms of flip-flop outputs as the
input variables In this case inputs of the flip-flops are:  DA, DB, DC & DD

K Map for DA :

Therefore,  DA = QAQD/ + QBQCQD

K Map for DB  : 

Therefore, DB = QBQC/ + QBQD/ + QB/QCQD

K Map for  DC:

Therefore, DC = QCQD/ + QA/QC/QD

K Map for  DD :

Therefore, DD = QD/ 

Step 5: Draw the circuit using flip-flops and other gates correspond to the
minimized expressions Circuit for MOD 10 or Decade Synchronous Counter using 
D Flip-flop:

In this way "MOD 10 Synchronous Counter using D Flip-flop" can be designed.

The following is the complete logic diagram for decade counter using SR FF.
The expression for all four SR flip flops are obtained as below. In following
Kmap Q3Q2Q1Q0=ABCD
S3=Q2Q1Q0

R3=Q3Q0
S2=Q2’Q1Q0

R2=Q2Q1Q0
S1=Q3¯¯¯¯¯¯Q1¯¯¯¯¯¯Q0
R1=Q1Q0R1=Q1Q0

S0=Q0¯¯¯¯¯¯
R0=Q0