Modeling and Characterization of On-Chip Transformers

Sunderarajan S. Mohan, C. Patrick Yue, Maria del Mar Hershenson, S. Simon Wong, and Thomas H. Lee

Center for Integrated Systems, Stanford University, Stanford, CA 94305

Abstract mutual coupling coefficient and high series resistance are accept-
able while all capacitances need to be minimized [3].
We present a scalable analytical model for on-chip transform-
The tapped transformer (Fig. 1.a) is best suited for three-port
ers that is suitable for design optimization and circuit simula-
applications. It permits a variety of tapping ratios to be realized.
tion. We also provide simple and accurate expressionsfor eval-
This transformer relies only on lateral magnetic coupling. All wind-
uating the self inductance and the mutual coupling coefficient
ings can be implemented with the top metal layer, thereby minimiz-
(k). The model agrees very well with measurements for a vari-
ing port-to-substrate capacitances. Since the two inductors occupy
ety of transformer configurations.
separate regions, the self-inductance is maximized while the port-
to-port capacitance is minimized. Unfortunately, this spatial sepa-
1 Introduction ration also leads to low mutual coupling (k !z 0.3 - 0.5).
The interleaved transformer (Fig. 1.b) is best suited for four-
The rising demand for low-cost radio frequency integrated circuits port applications that demand symmetry. Once again, capacitances
(RF-IC’s) has generated tremendous interest in on-chip passive com- can be minimized by implementation on top level metal so that high
ponents. Transformers are important elements in RF designs for resonant frequencies may be realized. The interleaving of the two
impedance conversion, impedance matching and bandwidth enhance- inductances permit moderate coupling ( k M 0.7) to be achieved
ment. Although on-chip transformers have been employed in RF- at the cost of reduced self-inductance. This coupling may be in-
IC’s [l, 21, models for providing design guidelines have not been creased at the cost of higher series resistance by reducing the tum
reported. In this paper, we present an analytical model for mono- width (tu) and spacing (s).
lithic transformers that is suitable for circuit simulation and design The stacked transformer (Fig. 1.c) uses multiple metal layers
optimization. We also provide simple expressions for calculating and exploits both vertical and lateral magnetic coupling to pro-
the mutual coupling coefficient (k). vide the best area efficiency, the highest self-inductance and high-
We first discuss different on-chip transformers and discuss their est coupling ( k M 0.9). This configuration is suitable for both three
advantages and disadvantages (52). We then present an analytical and four terminal configurations. The main drawback is the high
model along with expressions for the elements in it and the mutual port-to-port capacitance, or equivalently a low self-resonance fre-
coupling coefficient (53). In 54 we present experimental verifica- quency. In some cases, such as narrowband impedance transform-
tion for the model and finally summarize our findings in 55. ers, this capacitance may be incorporated as part of the resonant
circuit. Also, in modem multi-level processes, the capacitance can
2 Monolithic Transformer Realizations be reduced by increasing the oxide thickness between spirals. For
example, in a five metal process, 50 - 70% reductions in port-to-
Fig. 1 illustrates three common configurations of monolithic trans- port capacitance can be achieved by implementing the spirals on
formers. The different realizations offer varying trade-offs among layers five and three instead of five and,four. The increased vertical
the self inductance and series resistance of each port, the mutual separation will reduce k by less than 5%. One can also trade off
coupling coefficient, the port-to-port and port-to-substrate capac- reduced coupling for reduced capacitance by displacing the centers
itances, resonance frequencies, symmetry and area. Our models of the stacked inductors (Fig. l.d,l.e).
and coupling expressions allow these tradeoffs to be systematically
explored, thereby permitting transformers to be customized for a
variety of circuit design requirements. 3 Analytical Transformer Model
The desired characteristics for a transformer are application de- Fig. 2 presents the analytical models for tapped and stacked trans-
pendent. Transformers can be configured as three or four terminal formers. The expressions for the series resistances (R,,,, Rs,i,
devices. They may be used for narrowband or broadband appli- Rs,t, R s , b ) , the port-substrate capacitances (cox,,,Cox,it Cox,t,
cations. For example, in single sided to differential conversion, &,b. Cox,,,)and the crossover capacitances (CO,,,, Cov,i, CO,)
the transformer might be used as a four terminal narrowband de- are taken from [4]. Note that the model accounts for the increase
vice. In this case, a high mutual coupling coefficient and high self- in series resistance with frequency due to skin effect. Patterned
inductance are desired along with low series resistance. On the ground shields (PGS) are placed beneath the transformers to iso-
other hand, for bandwidth extension applications, the transformer late them from resistive and capacitive coupling to the substrate
is used as a broadband three terminal device. In this case, a small [5]. As a result, the substrate parasitics can be neglected.

19.3.1
0-7803-4774-9/98/$10.00 0 1998 IEEE IEDM 98-531

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 The inductance values are computed using a modified version The predictions of the analytical models were compared with
of Wheeler’s formula [6]. This expression does not take into ac- measurements for a variety of transformers. Fig. 4 shows good
count the variation in inductance due to conductor thickness and agreement for a tapped transformer (L0=3nH, Li=2nH, k=0.35)
frequency. In practical inductor and transformer realizations, the fabricated on a quartz substrate which has negligible parasitic ca-
thickness is small compared to the lateral dimensions of the coil pacitances. Fig. 5 - 7 show good agreement for stacked trans-
and has only a small impact on the inductance. For typical conduc- formers (Lt=20nH, Lb=20nH) with various shifts (k=0.9, k=0.55,
tor thickness variations (0.5pm-2.Opm), the change in inductance IC=0.3). The stacked transformers are fabricated on the third and
is within a few percent for practical inductor geometries. The in- second layers of a triple-metal 0.5pm CMOS epi-process with the
ductance also changes with frequency due to changes in current dis- pattemed ground shields (PGS) being implemented on the polysil-
tribution within the conductor. However, over the useful frequency icon layer.
range of a spiral, this variation is negligible [4]. When compared to Just as in the modeling of any distributed system, the lumped
field solver simulations, the inductance expression exhibits a max- circuit model breaks down at higher frequencies. The model is ac-
imum error of 8% over a broad design space (OD varying from curate up to the self-resonance frequencies of the individual ports,
100pm to 480pm, L varying from 0.5nH to 100nH, w varying which is the useful range for transformers applications. The close
from 2pm to 0.30D, s varying from 2pm to w and ID varying match between measured and modeled S-parameters over a wide
from 0.20D to 0.80D). range of coupling coefficients, processes and configurations con-
For the tapped transformer, the mutual inductance is determined firms the accuracy, scalability and robustness of the models pre-
by first calculating the inductance of the whole spiral (LT), the in- sented.
ductance of the outer spiral (Lo),the inductance of the inner spiral
(Li), and then using the expression M = (LT- Lo - Li)/2. For
the stacked transformer, the spirals have identical lateral geome-
5 Conclusions
tries and therefore identical inductances. In this case, the mutual We have presented an analytical model for on-chip transformers.
inductance is determined by first calculating the inductance of one The model has been compared to measurement results over a va-
spiral (Lt), the coupling coefficient (k) and then using the expres- riety of configurations, processes and coupling coefficients. The
sion M = ICLt. In this last case the coupling coefficient is given predicted and measured S-parameters show very good agreement.
by k M (0.9 - d,/AD) ford, < 0.7AD, where d, is the center-to- The model is scalable and robust and can be easily incorporated in
center spiral distance and AD is the average diameter of the spirals. an optimization algorithm.
As d, increases beyond 0.7AD, the mutual coupling coefficient be-
comes harder to model. Eventually, k crosses zero and reaches a
minimum value of approximately -0.1 at d, M AD. As d, in- 6 Acknowledgments
creases further, IC asymptotically approaches zero. At d, M 2AD, The authors are grateful to Dr. Christopher Hull and Dr. Paramjit
IC M -0.02, indicating that the magnetic coupling between closely Singh for help during layout and to Rockwell Inc. for fabricating
spaced spirals is negligible. the dice. Finally, they would like to thank the Stanford Nanofab-
The self inductances, series resistances and mutual inductances rication Facility staff for their assistance in processing. This work
are independent of whether a transformer is used as a three or four has been supported in part by the industrial sponsors of the Center
terminal device. The only elements that require recomputation are for Integrated Systems and NSF contract MIP-9313701.
the port-to-port and port-to-substrate capacitances. This situation
is analogous to that of a spiral inductor being used as a single or
dual terminal device. References

[l] J. Zhou et al., “A fully integrated CMOS 900MHz LNA using

4 Experimental Verification monolithic transformers,” in ISSCC’98, pp. 132-133.

The measurements were conducted on structures designed for op- [2] J. R. Long et al., “A 1.9 GHz low-voltage silicon bipolar
eration as three terminal devices. One of the ports was grounded receiver front-end for wireless personal communications sys-
while the other two ports were terminated in the 500 environ- tems,” IEEE JSSC, vol. 30, pp. 1438-1448, Dec. 1995.
ment of the test equipment. Two-port s-parameter measurements
[3] T.H. Lee, The Design of CMOS Radio-Frequency Integrated
were obtained using an HP8720B Network Analyzer and coplanar
Circuits, Cambridge University Press, Cambridge, 1998.
ground-signal-ground probes.
The expression for k is verified in the experiment shown in 141 C. P. Yue et al., “A physical model for planar spiral inductors
Fig. 3, which plots the coupling coefficient between two stacked on silicon,” in Pmc. IEEE IEDM’96, pp. 155-158.
20nH spirals as a function of shift. Good agreement between mea-
[5] C. P. Yue et al., “On-chip spiral inductors with pattemed
sured and modeled values of IC (Fig. 3) is observed. In practical
ground shields for Si-based RF IC’s,” IEEE JSSC, vol. 33,
transformers, the lateral dimensions are much larger than the verti-
pp. 743-752, May 1998.
cal dimensions. In such cases, variations in the vertical dimension
result in k changing by less than 10% and can therefore be ne- [6] H. A. Wheeler, “Simple inductance formulas for radio coils,”
glected. Proc. of the IRE, vol. 16, no. 10, pp. 1398-1400, Oct. 1928.

19.3.2
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 (a) (b) (c) (4 (e)
Figure 1: On-chip transformer realizations. (a)Tapped, (b)interIeaved, (c)stacked with top spiral overlapping the bottom one,
(d)stacked with top and bottom spirals laterally shifted, (e)stacked with top and bottom spirals diagonally shifted.

9.375p,n~'AD~'
LT ~~ODT-~ADT 9.375p,n2AD2
Port1 Port1 110D-7AD
9.375p,no'AD,'
LO llOD, -7AD, Lt
0.9 - dJAD
9.375p,niaADi'
k m

-
Li IlODi -7ADi

M
Rs,o

%,i

CO",O 1) * w2
cox,,
Cox,i .w

(a) Tapped transformer physical model. (Subscript '0' refers (b) Stacked transformer physical model. (Subscript 't'
to outer spiral, 'i' to inner spiral and 'T' to whole spiral) refers to top spiral and 'b' to bottom spiral)

Figure 2: Analytical models for transformers. (p=DC metal resistivity, 6=skin depth, to%,+=oxide thickness from top metal
to substrate, t,,b=oxide thickness from bottom metal to substrate, tox,t-b=oxide thickness from top level metal to bottom
level metal, k is the coupling coefficient, n=number of turns, OD=outer diameter, AD=average diameter(= (OD 10)/2), +
ID=inner diameter, [=length of spiral, w=turn width, t=metal thickness, A=area, A,=overlapped area of top and bottom
spirals, &=center-to-center spiral distance)

-
U
.
1.0 . . ,

I I I

BI 8 11 I 0.09 I 0.81 I 0.79

CI 42 I 0 I 42 I 0.35 I 0.55 I 0.57
DI 57 I 0 I 57 I 0.48 I 0.42 I 0.45
El 50 I 5 0 I '71 I 0.59 I 0.31 I 0.28
0.0
0.0
i 0.2 0.4 0.6
0.8

dnorm

Figure 3: Coupling coefficient (k)versus normalized shift (dnorm)for 20nH inductors on a patterned ground shield [5]. (n = 11.75,
OD = 180pm, w = 3.2pm, AD = 120pm, tt = 2.lpm, tb = 0.6pm, pt = 3pf2. cm, pb = 5pf2. cm, to+ = 3.5pm, to+ = 2.2pm,
t0x.t-b = 0 . 8 ~ 4

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 v)

-1.0 1
0.8 1.2 1.6 2.0
I
2.4
-1.0
0.8
' 1.2 1.6 2.0
I
2.4
-1.0
0.8
' ' '
1.2 1.6 2.0
J
2.4
Frequency (GHz) Frequency (GHz) Frequency (GHz)
Figure 4: Tapped transformer on quartz wafer. (no = 2.5, ni = 4.25, OD, = 290pm, ODi = 190pm, AD, = 247pm, AD; = 112pm,
w = 13pm, t = 2pm, p = 3pR . cm, t, = 3.5pm, tox,$-b = 0.8pm)

1.o
l . o r ]

0.5 0.5
I I'
-= 0.0

-0.5

-1.0
-051'3E.I
-1 0
talc
, , 1
0.5 1.o 1.5 00 0.5 10 1.5
Frequency (GHz) Frequency (GHz) Frequency (GHz)
Figure 5: Stacked transformer on PGS with top spiral overlapping the bottom one. (Transformer A in Fig. 3).

1.o 1.o

0.5 0.5

m= 0.0 -2 0.0

-0.5 -0.5

-1.0 -1.0 -1.0

0.5 1 .o ( 0.5 1.o 1.5 0.0 0.5 1.0 1.5
Frequency(GHz) Frequency (GHz) Frequency (GHz)
Figure 6: Stacked transformer on PGS with top and bottom spirals laterally shifted. (Transformer C in Fig. 3).

1.0

0.5 0.5 0.5

-s 0.0

-
-1 0
0
--- 5tm (S )talc
/ ~ 1, , 1 ~
-1 0
M
0
(S )calc
5 , ~ , 1 ~ -05 1
-1 0
~1 rm ( S )talc

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