MEL G642 VLSI ARCHITECTURE

ASSIGNMENT 1
Implement 5-stage MIPS pipelined processor in Verilog along with a hazard units which resolves
data hazards. This processor supports load word (lw), store word (sw), jump (j), set on less than
immediate (slti) and nor (nor) instructions only. The processor should implement forwarding to
resolve data hazards. The processor has Reset, CLK as inputs and no outputs. The processor has
instruction Fetch, Decode, Execution, Memory and Writeback units. The processor also contains
four pipelined registers IF/ID, ID/EX, EX/MEM and MEM/WB. When reset is activated the PC,
IF/ID, ID/EX, EX/MEM and MEM/WB registers are initialized to 0, the instruction memory and
register file get loaded by predefined values. When the instruction unit starts fetching the first
instruction the pipeline registers contain unknown values. When the second instruction is being
fetched in IF unit, the IF/ID registers will hold the instruction code for first instruction. When the
third instruction is being fetched by IF unit, the IF/ID register contains the instruction code of
second instruction, ID/EX register contains information related to first instruction and so on.
(Assume 32-bit PC. Also Assume Address and Data size as 32-bits)

The instruction and its 32-bit instruction format are shown below:
slti DestinationReg, S ourceReg, ImmediateData
Instruction format - Opcode:RS:RT/RD:IMMEDIATE
Opcode:-31:26
RS:-25:21
RT/RD:-20:16
IMMEDIATE:-15:0
Example:- slti R2,R0,2 ⇒ R2=R0 < 2
Opcode for slti = 6’d10

nor DestinationReg, SourceReg1, SourceReg2

Instruction format - Opcode:RS:RT:RD:SHAMT:FUNCT
Opcode:-31:26
RS:-25:21
RT:-20:16
RD-15:11
SHAMT:- 10:6
FUNCT:-5:0
Example:- nor R2,R0,R1 ⇒ R2 = R0 NOR R1
Opcode for nor =6’d0
Shamt for nor =00000
Function field for nor =100111

lw DestinationReg,SourceReg,Offset
Instruction format - Opcode:RS:RT/RD:IMMEDIATE
Opcode:-31:26
RS:-25:21
RT/RD:-20:16
IMMEDIATE:-15:0
Example:- lw R2,R0,2 ⇒ R2=DMEM[R0+2], Here DMEM stands for data memory
Opcode for lw=6’d35

sw SourceReg1, SourceReg2, Offset

Instruction format - Opcode:RS:RT/RD:IMMEDIATE
Opcode:-31:26
RS:-25:21
RT/RD:-20:16
IMMEDIATE:-15:0
Example:- sw R2,R0,2 ⇒ DMEM[R0+2] = R2, Here DMEM stands for data memory
Opcode for sw=6’d43

j address
Instruction format - Opcode:Address
Opcode:-31:26
Address:-25:0
Example:- j 8 ⇒ PC = (PC + 4)[31:28] concatenated with 8 sign-extended to 28 bits [The resulting
value of the PC should be the highest 4 bits of the (PC + 4) concatenated with a 28-bit sign-
extended value of the operand].
Opcode for sw=6’d2

Assume the register file contains 32 registers (R0-R31) each register can hold 32-bit data. On reset
register file should get initialized such that R1 = 32, R2 = 28, R3 = 24 … R9 = 0 and R0, R10 to
R31 are initialized to 0. Ensure R0 is always 0. Each location in DMEM has 8 bit data. So, to store
a 32-bit value you need 4 locations in the DMEM, in big-endian format. The DMEM should get
initialized with values DMEM[0]=32’d0, DMEM[4]=32’d1, DMEM[8]=32’d2,.......,
DMEM[36]=32’d9. Here 32’dx stands for representing a decimal integer x as a 32-bits binary data.
On reset ensure that the instruction memory gets initialized with the following instructions, starting
at address 0:
slti R9,R4,16
slti R8,R3,4
lw R3,R9,0
nor R1,R7,R4
nor R2,R3,R6
L: jL

The above code should run correctly on the processor implementation. Ensure that you handle the
data hazards present, if any.

A partial block-level representation of 5-stage pipelined processor is shown below.

 Instructi Instructi Execut Memo Write
on on e ry Back(W
Fetch(I Decode( (EXE) (MEM) B)
F) ID)

IF/I ID/E EX/ME MEM/W

D X M B

CL
K RESET

As part of the assignment, three files should be submitted in a zipped folder.

1. PDF version of this document with all the Questions below answered with the file name as
IDNO_NAME.pdf.

2. Design Verilog Files for all the Sub-modules (instruction fetch, Register file, forwarding unit).

3. Design a Verilog file for the main processor.

The name of the zipped folder should be in the format IDNO_NAME.zip

______________________________________________________________________________
_______

Name: Alay Shah ID No: 2021H1230177G

 Questions Related to Assignment

1. Draw the complete Datapath and show control signals of the 5-stage pipelined processor.
Answer:

2. List the control signals used and also the values of control signals for different
instructions in a tabular format as follows:
Answer:

Instructions Control Signals

RegWrite RegDst ALU_src ALU_op Branch Mem_read Mem_Write MemtoReg

slti 1’b1 1’b0 1’b1 2’b11 1’b0 1’b0 1’b0 1’b0
nor 1’b1 1’b1 1’b0 2’b10 1’b0 1’b0 1’b0 1’b0
lw 1’b1 1’b0 1’b1 2'b00 1’b0 1’b1 1’b0 1’b1
sw 1’b0 1’b0 1’b1 2'b00 1’b0 1’b0 1’b1 1’b0
j 1’b0 1’b0 - - 1’b1 1’b0 1’b0 1’b0
3. Implement the Instruction Fetch block. Copy the image of Verilog code of the Instruction
fetch block here

Answer:
4. Implement the Instruction Decode block. Copy the image of Verilog code of the
Instruction decode block here

Answer:

5. Implement the Register File and copy the image of Verilog code of Register file unit here.

Answer:
6. Determine the condition that can be used to detect data hazard?

Answer: EX Hazard Detection

1a. EX/MEM.RegWrite = 1

and EX./MEM RegisterRd ≠ $zero

and EX/MEM.RegisterRd = ID/EX.RegisterRs
1b. EX/MEM.RegWrite = 1

and EX./MEM RegisterRd ≠ $zero

and EX/MEM.RegisterRd = ID/EX.RegisterRt
MEM Hazard Detection
2a. MEM/WB.RegWrite = 1

and MEM/WB.RegisterRd ≠ $zero

and MEM/WB.RegisterRd = ID/EX.RegisterRs

and not ( EX/MEM.RegWrite = 1

and EX/MEM.RegisterRd ≠ $zero

and EX/MEM.RegisterRd = ID/EX.RegisterRs )

2b. MEM/WB.RegWrite = 1

and MEM/WB.RegisterRd ≠ $zero

and MEM/WB.RegisterRd = ID/EX.RegisterRt

and not (EX/MEM.RegWrite = 1

and EX/MEM.RegisterRd ≠ $zero

and EX/MEM.RegisterRd = ID/EX.RegisterRt )

These conditions are used for Forwarding.

7. Implement the forwarding unit and copy the image of Verilog code of forwarding unit
here.

Answer:
 8. Implement complete processor in Verilog (using all the Datapath blocks). Copy the image
of Verilog code of the processor here. (Use comments to describe your Verilog
implementation)

Answer:
9. Test the processor design by generating the appropriate clock and reset. Copy the image
of your testbench code here.

Answer:

10. Verify if the register file is getting updated according to the set of instructions
(mentioned earlier).

Copy verified Register file waveform here (show only the Registers that get updated, CLK, and
RESET):

11. What are the total number of cycles needed to issue the program given above on the
pipelined MIPS Processor? What is the CPI of the program?

Answer: The total number of cycles needed to issue the program is 9.

nor R2, R3, R6 Write backstage is considered for total no. of cycles required.

CPI=9/6=1.5.
12. Make a diagram of the pipelined processor executing each instruction in the program
given above. Also show in which cycles and instructions are stalls and forwarding required.

Answer:

13. Consider the following delay elements for the pipelined MIPS Processor. Which unit
should one consider for the greatest speedup of the overall processor? How fast should it
be? What is the cycle time of the improved processor?

Data memory should be considered for the greatest speedup of the overall processor.

Make its speed double to get speed up.

The improved cycle time of the processor will be 200ps

 Elements Parameter Delay(ps)

Register clk-to-Q tpcq 35

Register setup tsetup 20

Multiplexer tmux 25

ALU tALU 200

Memory read tmemread 250

Memory Write tmemwrite 220

Register file read tRFread 160

Register file write tRFWrite 100

AND tAND 15

Equality Comparator teq 40

Using the improved cycle time and the CPI of the program calculated in Question 11, find
the execution time of the program given above.

Answer:- as per iron’s law,

ET= no. of instruction* CPI* cycle time

ET=6*1.5*200=1.8ns

Unrelated Questions

What were the problems you faced during the implementation of the processor?

Answer: I faced some problems during implementing Forwarding Unit.

Did you implement the processor on your own? If you took help from someone whose help
did you take? Which part of the design did you take help for?

Answer: I took some help from my friends for implementing Forwarding Unit.
Honor Code Declaration by student:

● My answers to the above questions are my own work.

● I have not shared the codes/answers written by me with any other students. (I might have
helped clear doubts of other students).
● I have not copied other’s code/answers to improve my results. (I might have got some doubts
cleared from other students).

Name: Alay Shah Date: 25/03/2022

ID No.: 2021H1230177G