Analog Signal Processing Laboratory (EEL305) Manual

NMAM Institute of Technology,

Nitte
(Deemed to be University)

Department of Electrical & Electronics

Engineering

Analog Signal Processing

Lab Manual
21EEL305

Name
USN
Sem /
Section

Prepared by : Gururaj.K

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 Analog Signal Processing Laboratory (EEL305) Manual

Analog Signal Processing Laboratory

Course Code : 21EEL305 Credits : 01

Contact Hours : 0-0-2-0 CIE Marks : 50
Total Contact Hours : 25 SEE Marks : 50

Course Learning Objectives:

1. To study the MOSFET characteristics

2. To design and test biasing circuits of MOSFET
3. To use MOSFET as an amplifier and verify its frequency response
4. To design and test MOSFET based oscillator circuit
5. To design and test Opamp circuits
List of Experiments: -
1. Study of MOSFET characteristics and determine transconductance & output
resistance.
2. Design different types of biasing circuits and validate the operating point
3. Design Common Source (CS) MOSFET amplifier to determine frequency
response
4. Application of MOSFET as a switch
5. Design MOSFET source follower to determine input & output impedance
6. Design and test MOSFET based RC phase shift oscillator
7. Design MOSFET based differential amplifier to determine differential and
common mode gains
8. Design and testing of capacitor coupled voltage follower and inverting amplifier
for gain, frequency response, 𝑍𝑖𝑛
9. Design and testing of capacitor coupled non inverting amplifier and difference
amplifier for gain, frequency response and 𝑍𝑖𝑛 calculation
10. Design and testing of unipolar op amp circuits for gain, frequency response and
𝑍𝑖𝑛 calculations

Course Outcomes:
At the end of the course student will be able to
1. Verify MOSFET characteristics and biasing circuits to validate operating point
2. Use MOSFET for amplifier applications to determine the gain, frequency
response, input & output impedances
3. Design MOSFET based oscillator circuits to generate required frequency signals.
4. Use of Opamp to design application specific circuit
5. Use of Opamp to design unipolar application specific circuit

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 Analog Signal Processing Laboratory (EEL305) Manual

Course Outcomes Mapping with Program Outcomes & PSO

Programme Outcome → 1 2 3 4 5 6 7 8 9 10 11 12 PSO

Course Outcome ↓ 1 2
21EEL305.1 1 2 3 1 2
21EEL305.2 1 1 2 3 1 1 2
21EEL305.3 1 1 2 3 1 1 2
21EEL305.4 1 1 2 3 1 2
21EEL305.5 1 1 2 3 1 1 2

1: Low, 2: Medium , 3: High

TEXT BOOKS:-
1. Sedra /Smith, “Microelectronic Circuits” 6th Edition, Oxford University
Press-New Delhi,2013.
2. David A Bell, Operational Amplifier and Linear IC’s, Oxford University
Press-New Delhi, 3rd Edition, 2011
REFERENCE BOOKS:
1. Jacob Millman & Christos C. Halkias, “Integrated Electronics”, McGraw
Hill Publications, 2nd Edition, 2011.
2. Nashelesky & Boylestead, “Electronic Devices & Circuit Theory”, PHI,
11TH Edition.2015.
3. Ramakanth Gayakwad, Operational Amplifier and Linear IC’s, 4 th edition,
Prentice Hall, 2000.

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 Analog Signal Processing Laboratory (EEL305) Manual

Experiment 1:
Study of MOSFET characteristics and determine
transconductance & output resistance
Aim: To study MOSFET characteristics and determine transconductance & output
resistance

Apparatus Required

Component Description Quantity

MOSFET 2N7000 1
RPS Regulated DC Power Supply 0-30V, 2A 2
Voltmeter DC Voltmeter 0-15V 2
Ammeter DC Ammeter 0-60mA 1
Rheostat 0-100Ω 2

Circuit Diagram

Figure 1.1 Experimental Setup

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 Analog Signal Processing Laboratory (EEL305) Manual

Procedure to find transconductance

 Rig up the circuit as shown in the circuit diagram Fig. 1.1

 Switch on th e RPS keeping voltage setting in minimum position and
current setting in required load current position
 Keep both rheostats Rh1 and Rh2 in minimum position
 Set V𝐺𝐺 to 3V and V𝐷𝐷 to 6V in RPS
 Set V𝐷𝑆 by varying rheostat Rh2 , vary V𝐺𝑆 in step using rheostat Rh1 and
note down drain current 𝐼𝐷 for each case. (Note: In each case V𝐺𝑆 made
zero before taking next reading in order to maintain constant junction
temperature)
 Repeat above step for different values of V𝐷𝑆
 Tabulate the readings
 Note the value of threshold voltage (V𝐺𝑆𝑡ℎ )
 Plot a graph of 𝐼𝐷 against V𝐺𝑆 as in Fig. 1.2
 Calculate transconductance

𝜕𝐼𝐷
𝑔𝑚 =
𝜕𝑉𝐺𝑆|𝑉𝐷𝑆

Procedure to find output resistance

 Rig up the circuit as shown in the circuit diagram

 Switch ON the RPS keeping voltage setting in minimum position and
current setting in required load current position
 Set V𝐺𝑆 by varying rheostat Rh1, vary V𝐷𝑆 in steps using rheostat Rh2 and
note down drain current 𝐼𝐷 for each case. (Note: In each case V𝐷𝑆 made
zero before taking next reading in order to maintain constant junction
temperature)
 Repeat the above step for different values of V𝐺𝑆
 Tabulate the readings
 Plot a graph of 𝐼𝐷 against V𝐷𝑆 for different VGS as in Fig. 1.3
 Calculate output resistance

𝜕𝑉𝐷𝑆
𝑟𝑜 =
𝜕𝐼𝐷|𝑉𝐺𝑆

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 Analog Signal Processing Laboratory (EEL305) Manual

Observations

𝑉𝐷𝑆 = 2𝑉 𝑉𝐷𝑆 = 3𝑉
𝑉𝐺𝑆 (𝑉) 𝐼𝐷 (𝑚𝐴) 𝑉𝐺𝑆 (𝑉) 𝐼𝐷 (𝑚𝐴)
0.0 0.0
0.5 0.5
1.0 1.0
1.3 1.3
1.4 1.4
1.5 1.5
1.6 1.6
1.7 1.7
1.8 1.8
1.9 1.9
2.0 2.0
2.1 2.1
2.3 2.3
2.5 2.5

Table 1.1: Transfer Characteristics

Expected Waveform

Figure 1.2 Transfer Characteristics

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 Analog Signal Processing Laboratory (EEL305) Manual

𝑉𝐺𝑆 = 1𝑉 𝑉𝐺𝑆 = 1.8𝑉

𝑉𝐷𝑆 (𝑉) 𝐼𝐷 (𝑚𝐴) 𝑉𝐷𝑆 (𝑉) 𝐼𝐷 (𝑚𝐴)
0.0 0.0
0.1 0.1
0.2 0.2
0.3 0.3
0.4 0.4
0.5 0.5
0.6 0.6
0.7 0.7
0.8 0.8
0.9 0.9
1.0 1.0
1.5 1.5
2.0 2.0
2.5 2.5
3.0 3.0
3.5 3.5
4.0 4.0
4.5 4.5
5.0 5.0
5.5 5.5
6.0 6.0

Table 1.2: Output Characteristics

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 Analog Signal Processing Laboratory (EEL305) Manual

𝑉𝐺𝑆 = 2𝑉 4.5
𝑉𝐷𝑆 (𝑉) 𝐼𝐷 (𝑚𝐴) 5.0
0.0 5.5
0.1 6.0
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
𝑉𝐺𝑆 = 3𝑉
𝑉𝐷𝑆 (𝑉) 𝐼𝐷 (𝑚𝐴)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.5
2.0
2.5
3.0
3.5
4.0
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 Table 1.3: Output Characteristics

Expected Waveform

Figure 1.3 Output Characteristics

 Analog Signal Processing Laboratory (EEL305) Manual

Experiment 2:
Design of MOSFET biasing circuit
Aim: To design MOSFET biasing circuit and validate the operating point

Apparatus Required

Component Description Quantity

MOSFET 2N7000 1
RPS Regulated DC Power Supply 0-30V, 2A 2
Voltmeter DC Voltmeter 0-15V 2
Ammeter DC Ammeter 0-60mA 1
Rheostat 0-100Ω 2
Resistance As per calculation (560kΩ,100kΩ,10kΩ, 1,1,1,1
100 Ω)

Circuit Diagram

Figure 2.1 MOSFET biasing circuit

Design parameters

𝑉𝐷𝐷 = 10𝑉 , 𝑉𝐷 = 5𝑉 , 𝐼𝐷 = 0.5𝑚𝐴 , 𝑔𝑚 = 100𝑚𝑆 , 𝑉𝑡 = 1.5𝑉

Step1: Examine 𝑉𝐺 and 𝑉𝐷𝑆

Determine 𝑅𝐷
𝑉𝐷𝐷 − 𝑉𝐷
𝑅𝐷 = = Ω
𝐼𝐷

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 Analog Signal Processing Laboratory (EEL305) Manual

Determine 𝑅𝑆

Assume 𝑉𝑆 = 0.05𝑉𝐷𝐷

𝑉𝑆 = 𝑉

𝑉𝑆
𝑅𝑆 = = Ω
𝐼𝐷

Parameter Observed Value

𝑉𝐺
𝐼𝐷
𝑉𝐷𝑆

Table 2.1 Observations in

Step1

Figure 2.2 Experiment Setup

Procedure
 Rig up the circuit as shown in step1
 Keep voltage and current knob in minimum and maximum positions
respectively and switch on the RPS 𝑉𝐷𝐷 and 𝑉𝐺𝐺
 Turn voltage knob of RPS 𝑉𝐷𝐷 till it increases to 10V and 𝑉𝐺𝐺 till it increases to
3V
 Vary 𝑉𝐺 using rheostat until drain current 𝐼𝐷 is 0.5mA
 Tabulate the values of 𝑉𝐺 , 𝐼𝐷 and 𝑉𝐷𝑆

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 Analog Signal Processing Laboratory (EEL305) Manual

Step2: Determine theoretical 𝑉𝐺

𝑊
𝑔𝑚 = √2 ∗ 𝐾 ′ 𝑛 ∗ ∗ 𝐼𝐷
𝐿

𝑅𝑒𝑎𝑟𝑟𝑎𝑛𝑔𝑖𝑛𝑔

𝐾 ′𝑛 ∗ 𝑊 𝑔𝑚 2
=
𝐿 2 ∗ 𝐼𝐷
′
𝐾 𝑛∗𝑊
= 𝐴/𝑉 2
𝐿
Substituting above value in 𝐼𝐷 equation as follows to find 𝑉𝐺𝑆

1 𝐾 ′𝑛 ∗ 𝑊
𝐼𝐷 = ∗ ∗ (𝑉𝐺𝑆 − 𝑉𝑡 )2
2 𝐿

𝑉𝐺𝑆 = 𝑉

Theoretical value of 𝑉𝐺 is

𝑉𝐺 = 𝑉𝐺𝑆 + 𝐼𝐷 ∗ 𝑅𝑆

𝑉𝐺 = 𝑉

Step3: Voltage divider

Assume 𝑅1 = 560𝑘Ω
𝑅2
𝑉𝐺 = 𝑉𝐷𝐷 ∗
𝑅1 + 𝑅2

𝐻𝑒𝑛𝑐𝑒, 𝑅2 = Ω

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 Analog Signal Processing Laboratory (EEL305) Manual

Calculated Value Observed Value

𝑉𝐺 (𝑉𝑅2 ) = 𝑉
Table 2.2 Observations in Step3

Figure 2.3 Voltage Divider

Procedure
 Rig up the circuit as shown in step3
 Keep voltage and current knob in minimum and maximum positions
respectively and switch on the RPS 𝑉𝐷𝐷
 Turn voltage knob of RPS 𝑉𝐷𝐷 till it increases to 10V
 Measure voltage 𝑉𝐺 using multimeter
 Tabulate the results

Step4: Realization of biasing circuit

Calculated Value Observed Value

𝑉𝐺 = 𝑉
𝐼𝐷 = 𝐴
𝑉𝐷𝑆 = 𝑉
Table 2.3 Observations in Step4

Figure 2.4 Voltage Divider

 Rig up the circuit as shown in step4

 Keep voltage and current knob in minimum and maximum positions
respectively and switch on the RPS 𝑉𝐷𝐷
 Turn voltage knob of RPS 𝑉𝐷𝐷 till it increases to 10V

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 Analog Signal Processing Laboratory (EEL305) Manual

 Measure voltage 𝑉𝐺 , 𝑉𝐷𝑆 and 𝐼𝐷 using multimeter

 Plot the load line and obtain the Q point

Figure 2.5 MOSFET biasing circuit

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 Analog Signal Processing Laboratory (EEL305) Manual

Experiment 3:
Design Common Source (CS) MOSFET amplifier to
determine frequency response
Aim: To determine maximum signal handling capacity, plot frequency response of an

Common Source amplifier

Apparatus Required

Component Description Quantity

MOSFET 2N7000 1
RPS Regulated DC Power Supply 0-30V, 2A 1
AFO Audio Frequency Oscillator 1
DSO 100MHz, 1GS/s 1
Resistors As per calculation (560kΩ,100kΩ,10kΩ, 1,2,1,1
100 Ω)
Capacitors As per calculation (1uF,200nF,220uF) 1,1,1

Circuit Diagram

Figure 3.1 CS Amplifier

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 Analog Signal Processing Laboratory (EEL305) Manual

Design parameters and calculations same as in experiment 3

Step1: Voltage Divider

Calculated Value Observed Value

𝑉𝐺 (𝑉𝑅2 ) = 𝑉
Table 3.1 Observations in
Step1

Figure 3.2 Voltage

Divider

Procedure
 Rig up the circuit as in Step1
 Keep voltage and current knob in minimum and maximum positions
respectively and switch on the RPS 𝑉𝐷𝐷
 Turn voltage knob of RPS till it increases to 10V
 Measure voltage 𝑉𝐺 using multimeter
 Tabulate the result

Step2: Realization of biasing circuit

Calculated Value Observed Value

𝑉𝐺 = 𝑉
𝑉𝐷𝑆 = 𝑉
Table 3.2 Observations in Step2

Figure 3.3 Biasing circuit

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 Analog Signal Processing Laboratory (EEL305) Manual

Procedure
 Rig up the circuit as in Step2
 Keep voltage and current knob in minimum and maximum positions
respectively and switch on the RPS 𝑉𝐷𝐷
 Turn voltage knob of RPS till it increases to 10V
 Measure voltage 𝑉𝐺 and 𝑉𝐷𝑆

Step3: Capacitance Calculations

To calculate 𝐶𝑆

𝐿𝑒𝑡 𝑓𝑝2 = 𝐹𝐿 = 100𝐻𝑧

𝑔𝑚
𝜔𝑝2 =
𝐶𝑆

𝐶𝑆 = 𝐹

Select 𝐶𝑆 = 220𝜇𝐹

To calculate 𝐶1

𝐿𝑒𝑡 𝑓𝑝1 = 10𝐻𝑧

1
𝜔𝑝1 =
𝐶1 ∗ (𝑅1||𝑅2 )

𝐶1 = 𝐹

Select 𝐶1 = 1𝜇𝐹

To calculate 𝐶2

Where 𝑅𝐿 = 100𝑘Ω

𝐿𝑒𝑡 𝑓𝑝3 = 50𝐻𝑧

1
𝜔𝑝3 =
𝐶2 ∗ (𝑅𝐷 + 𝑅𝐿 )

𝐶2 = 𝐹

Select 𝐶2 = 200𝑛𝐹

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 Analog Signal Processing Laboratory (EEL305) Manual

Step4: To determine Maximum Signal Handling Capacity (Vinmax)

 Rig up the amplifier circuit as shown in circuit diagram Fig. 3.1

 Keep voltage and current knob in minimum and maximum positions
respectively and switch on the RPS 𝑉𝐷𝐷
 Adjust bias voltage 𝑉𝐷𝐷
 Switch ON AFO. Set the AFO to 1kHz sine wave. The amplitude of the input
𝑉𝑖𝑛 is varied from very small voltage value and the output is observed in DSO
for every increase in input voltage
 For a particular value of input voltage, the output starts clipping
 The input voltage just before the output starts clipping is noted down. This is
the maximum signal handling capacity 𝑉𝑖𝑛𝑚𝑎𝑥

Observed maximum signal handling capacity 𝑉𝑖𝑛𝑚𝑎𝑥 = V

Step5: To plot Frequency Response

 The amplitude of input voltage is set to a value less than 𝑉𝑖𝑛𝑚𝑎𝑥 obtained in the
last step of above procedure
 The frequency is varied from 50Hz to 1MHz in steps and output amplitude is
noted each time. Ensure that input voltage is kept constant
 Gain in dB is calculated using the formula
𝑉𝑜𝑢𝑡
𝐴𝑣 = 20 log
𝑉𝑖𝑛
 Frequency response is plotted in semilog graph sheet

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 Analog Signal Processing Laboratory (EEL305) Manual

𝑉𝑖𝑛 = 𝑉
𝑉𝑜𝑢𝑡
Frequency (Hz) 𝑉𝑜𝑢𝑡 (𝑉) Gain 𝐴𝑣 = Gain in dB 𝐴𝑣𝑑𝐵 = 20 log 𝐴𝑣
𝑉𝑖𝑛
50
100
500
1k
4k
8k
10k
25k
50k
75k
100k
250k
500k
1M
Table 3.3 Frequency Response

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 Analog Signal Processing Laboratory (EEL305) Manual

Experiment 4:
Application of MOSFET as a switch
Aim: To demonstrate switching action of MOSFET Common Source amplifier

Apparatus Required

Component Description Quantity

MOSFET 2N7000 1
RPS Regulated DC Power Supply 0-30V, 2A 2
Resistor 1kΩ 1
Potentiometer 10kΩ 1
Voltmeter DC Voltmeter 0-10V 2
Ammeter DC Ammeter 0-10mA 1

Circuit Diagram

Figure 4.1 MOSFET as a Switch

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 Analog Signal Processing Laboratory (EEL305) Manual

Procedure
Step1:

 Rig up the circuit as in Figure 4.1

 Keep voltage and current knob in minimum and maximum positions
respectively and switch on the RPS 𝑉𝐷𝐷 and 𝑉𝐺𝑆
 Keep potentiometer 𝑅𝐿 in minimum position
 Turn voltage knob of RPS 𝑉𝐷𝐷 till it increases to 5V
 Apply 𝑉𝐺𝑆 = 0.5 V by turning voltage knob of RPS.
 Measure 𝑉𝐷𝑆 and 𝐼𝐷
 Tabulate the result

Parameter Expected Value Observed Value

𝑉𝐺𝑆 0.5V
𝑉𝐷𝑆 5V
𝐼𝐷 0A

Step2:

 Rig up the circuit as in Figure 4.1

 Keep voltage and current knob in minimum and maximum positions
respectively and switch on the RPS 𝑉𝐷𝐷 and 𝑉𝐺𝑆
 Keep potentiometer 𝑅𝐿 in minimum position
 Turn voltage knob of RPS 𝑉𝐷𝐷 till it increases to 5V
 Turn voltage knob of RPS 𝑉𝐺𝑆 till it increases to 5V
 Measure 𝑉𝐷𝑆 and 𝐼𝐷 for all the cases as shown in table
 In each case, measure the resistance using multimeter by disconnecting 𝑉𝐷𝐷
 Tabulate the result and plot load line

𝑅𝐿 𝑉𝐺𝑆 𝑉𝐷𝑆 𝑉𝐷𝐷 Measured value of resistance using

(𝑅𝐷 + 𝑅𝐿 ) =
𝐼𝐷 Multimeter
Minimum
Intermediate
Maximum

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 Analog Signal Processing Laboratory (EEL305) Manual

Figure 4.2 Load Line

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 Analog Signal Processing Laboratory (EEL305) Manual

Experiment 5:
Design MOSFET source follower to determine Input &
Output impedance
Aim: Testing of FET Source follower and determination input and output impedances

Apparatus Required

Component Description Quantity

MOSFET 2N7000 1
RPS Regulated DC Power Supply 0-30V, 2A 1
AFO Audio Frequency Oscillator 1
DSO 100MHz, 1GS/s 1
Resistors As per calculation (560kΩ,10kΩ,100kΩ) 2,1,1
Capacitors As per calculation (1uF,22uF) 1,1

Circuit Diagram

Figure 5.1 Source Follower

Design calculation
Given 𝑉𝐷𝐷 = 10𝑉 , 𝐼𝐷 = 0.5𝑚𝐴 , 𝑓𝐿 = 10𝐻𝑧 , 𝑉𝑡 = 1.5𝑉 , 𝑅𝐿 = 100𝑘Ω

To find 𝑅𝐷 :

𝐿𝑒𝑡 𝑉𝑆 = 0.5 ∗ 𝑉𝐷𝐷

𝑉𝑆
𝑅𝑆 = = 10𝑘Ω
𝐼𝐷

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 Analog Signal Processing Laboratory (EEL305) Manual

To find 𝑅1 and 𝑅2 :

𝐿𝑒𝑡 𝑉𝐺 = 0.5 ∗ 𝑉𝐷𝐷

𝑅1 = 𝑅2 = Ω

Theoretical Gain
𝑅𝐿
𝐴𝑣 = 1
𝑅𝐿 +
𝑔𝑚

To calculate 𝐶1
𝑅𝑖𝑛
𝐿𝑒𝑡 𝑋𝐶1 = 𝑎𝑡 𝑓𝐿 = 10𝐻𝑧
10
𝑅𝑖𝑛 = 𝑅1||𝑅2

𝐶1 = 𝐹

Select 𝐶1 = 1𝜇𝐹

To calculate 𝐶2
𝑅𝑜
𝐿𝑒𝑡 𝑋𝐶2 = 𝑎𝑡 𝑓𝐿 = 10𝐻𝑧
10
𝑅𝑜 = 𝑅𝐿 ||𝑅𝑆

𝐶2 = 𝐹

Select 𝐶2 = 22𝜇𝐹

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 Analog Signal Processing Laboratory (EEL305) Manual

Step1: Voltage Divider

Calculated Value Observed Value

𝑉𝐺 = 5𝑉
Table 5.1 Observations in Step1

Figure 5.2 Voltage

Divider

Procedure
 Rig up the circuit as in Step1
 Keep voltage and current knob in minimum and maximum positions
respectively and switch on the RPS 𝑉𝐷𝐷
 Turn voltage knob of RPS till it increases to 10V
 Measure voltage 𝑉𝐺 using multimeter
 Tabulate the result

Step2: Realization of biasing circuit

Calculated Value Observed Value

𝑉𝑆 = 5𝑉
Table 5.2 Observations in Step2

Figure 5.3 Biasing circuit

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 Analog Signal Processing Laboratory (EEL305) Manual

Procedure
 Rig up the circuit as in Step2
 Keep voltage and current knob in minimum and maximum positions
respectively and switch on the RPS 𝑉𝐷𝐷
 Turn voltage knob of RPS till it increases to 10V
 Measure voltage 𝑉𝑆

To determine Maximum Signal Handling Capacity (Vinmax)

 Rig up the amplifier circuit as shown in circuit diagram

 Keep voltage and current knob in minimum and maximum positions
respectively and switch on the RPS 𝑉𝐷𝐷
 Adjust bias voltage 𝑉𝐷𝐷
 Switch ON AFO. Set the AFO to 1kHz sine wave. The amplitude of the input
𝑉𝑖𝑛 is varied from very small voltage value and the output is observed in DSO
for every increase in input voltage
 For a particular value of input voltage, the output starts clipping
 The input voltage just before the output starts clipping is noted down. This is
the maximum signal handling capacity 𝑉𝑖𝑛𝑚𝑎𝑥

Observed maximum signal handling capacity 𝑉𝑖𝑛𝑚𝑎𝑥 = V

Input Voltage 𝑉𝑖𝑛 Output Voltage 𝑉𝑜𝑢𝑡 Desired Gain Observed gain 𝑉𝑜𝑢𝑡 /𝑉𝑖𝑛
0.9

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Circuit Diagram to determine Input Impedance

Figure 5.4 Input Impedance

To determine Input Impedance:

 Rig up the amplifier circuit as shown in circuit diagram 5.4.

 Turn ON RPS and apply 𝑉𝐷𝐷 =10V
 Turn ON AFO and apply 𝑉𝑖
 Note down peak amplitude of voltage 𝑉𝑖 and corresponding current 𝐼𝑖
 Turn OFF AFO and turn OFF RPS
 Calculate input impedance from tabulated data

Input Voltage 𝑉𝑖 Input current 𝐼𝑖 𝑅𝑖 = (𝑉𝑖 ⁄√2)⁄ 𝐼𝑖

Circuit Diagram to determine Output Impedance

Figure 5.5 Output Impedance

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To determine Output Impedance:

 Rig up the amplifier circuit as shown in circuit diagram 5.5 (without 𝑅𝐿 )

 Turn ON RPS and apply 𝑉𝐷𝐷 =10V
 Turn ON AFO and apply 𝑉𝑥
 Note down peak amplitude of voltage Vx and corresponding current 𝐼𝑥
 Turn OFF AFO and turn OFF RPS
 Calculate output impedance from tabulated data

Output Voltage 𝑉𝑥 Output current 𝐼𝑥 𝑅𝑜 = (𝑉𝑥 ⁄√2)⁄ 𝐼𝑥

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Experiment 6:
Design and test MOSFET based RC phase shift
oscillator
Aim: Testing for the performance of MOSFET based RC Phase shift Oscillator for required
frequency 𝑓𝑜

Apparatus Required

Component Description Quantity

MOSFET 2N7000 1
RPS Regulated DC Power Supply 0-30V, 2A 1
AFO Audio Frequency Oscillator 1
DSO 100MHz, 1GS/s 1
Resistors As per calculation (560kΩ,100kΩ,100Ω, 1,2,1,1,3
100kΩ,10kΩ)
Capacitors As per calculation (1uF,200nF,220uF, 1,1,1,3
10nF)

Circuit Diagram

Figure 6.1 RC Phase Shift Oscillator

Design value calculation refer experiment MOSFET biasing and CS amplifier

frequency response

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Step1: Voltage Divider

Calculated Value Observed Value

𝑉𝐺 (𝑅2 ) = 1.56𝑉
Table 6.1 Observations in Step1

Figure 6.2 Voltage

Divider

Procedure
 Rig up the circuit as in Step1
 Keep voltage and current knob in minimum and maximum positions
respectively and switch on the RPS 𝑉𝐷𝐷
 Turn voltage knob of RPS till it increases to 10V
 Measure voltage 𝑉𝐺 using multimeter
 Tabulate the result

Step2: Realization of biasing circuit

Calculated Value Observed Value

𝑉𝐺 = 1.56𝑉
𝑉𝐷𝑆 = 5𝑉
Table 6.2 Observations in Step2

Figure 6.3 Biasing circuit

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Procedure
 Rig up the circuit as in Step2
 Keep voltage and current knob in minimum and maximum positions
respectively and switch on the RPS 𝑉𝐷𝐷
 Turn voltage knob of RPS till it increases to 10V
 Measure voltage 𝑉𝐺 and 𝑉𝐷𝑆

Oscillator circuit design calculation

𝑓𝑜 = 650 𝐻𝑧

Let 𝐶 = 10𝑛𝐹

Calculate R using relationship

1
𝑓𝑜 =
2𝜋 ∗ 𝑅 ∗ 𝐶 ∗ √6
R= Ω

Select R = 10kΩ

Procedure:
 Rig up the circuit as shown in the circuit diagram 6.1.
 Switch on the supply to RPS keeping in zero setting.
 Apply bias voltage VDD
 Make initial setting in the CRO.
 Connect the probe across amplifier output and ground. Observe sinusoidal
oscillations on the CRO for proper undistorted sine-wave adjust pot
 Plot the graph and calculate frequency of oscillations obtained

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Lissajous Pattern:
To measure the phase shift at different stages

 To observe Lissajous pattern keep CRO in X-Y mode, connect the probe at
node ’0’ to X-channel and repeat the following by connecting Y-channel
 Connect probe at node ’1’ for 60 degree Phase shift

Theoretical Phase shift Observed Value

60 degree 𝑋1
𝜃 = sin−1 ( ) =
𝑋2

Table 6.3 Observations for 60 degree phase shift

 Connect probe at node ’2’ for 120 degree

Theoretical Phase shift Observed Value

120 degree 𝑋1
𝜃 = 180 − sin−1 ( ) =
𝑋2

Table 6.4 Observations for 120 degree phase shift

 Connect probe at node ’3’ for 180 degree

Theoretical Phase shift Observed Value

180 degree 𝑋1
𝜃 = 180 − sin−1 ( ) =
𝑋2

Table 6.5 Observations for 180 degree phase shift

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(a) 60 degree phase shift

(b) 120 degree phase shift

(c) 180 degree phase shift

Figure 6.4 Lissagious pattern

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 Analog Signal Processing Laboratory (EEL305) Manual

Experiment 7:
Design MOSFET based differential amplifier to
determine differential and common mode gains
Aim: To determine differential and common mode gain of FET differential amplifier

Apparatus Required

Component Description Quantity

MOSFET 2N7000 2
RPS Regulated DC Power Supply 0-30V, 2A 2
AFO Audio Frequency Oscillator 1
DSO 100MHz, 1GS/s 1
Resistors As per calculation

Circuit Diagram

Figure 7.1 Differential amplifier

Design Calculation:
Design parameters

𝑉𝐷𝐷 = 𝑉𝑆𝑆 = 10𝑉 , 𝐼𝐷1 = 𝐼𝐷2 = 0.5𝑚𝐴 , 𝑉𝑡ℎ = 1𝑉

Assuming 𝑉𝐷1 = 𝑉𝐷2 = 5𝑉 , 𝑉𝑆 = 1.5𝑉 , 𝑅𝐺1 = 𝑅𝐺2 = 100𝑘Ω

𝑉𝐷𝐷 − 𝑉𝐷1
𝑅𝐷1 = 𝑅𝐷2 = = Ω
𝐼𝐷1

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𝐼𝑆 = 𝐼𝐷1 + 𝐼𝐷2
𝑉𝑆𝑆 − 𝑉𝑆
𝑅𝑆 = = Ω
𝐼𝑆

Select 𝑅𝑆 = 8.2𝑘Ω

Step1: DC Biasing

Figure 7.2 DC Biasing Circuit

Procedure
 Rig up the circuit as shown in step1
 Apply +10V in 𝑉𝐷𝐷 and -10V in 𝑉𝑆𝑆
 Tabulate 𝑉𝐷1 , 𝑉𝐷2 and 𝑉𝑆

Node Expected Value Observed Value

𝑉𝐷1 5V
𝑉𝐷2 5V
𝑉𝑆 -1.5V

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Step2: To measure differential gain

Figure 7.3 Differential mode gain circuit

Procedure
 Rig up circuit as shown in step2
 Connect Ch1 of DSO to AFO and Ch2 to 𝑉𝐷1 , apply 1k Hz sine such that
undistorted output is observed in Ch2.
 Measure peak voltage along with phase angle
 Connect Ch2 to 𝑉𝐷2 and measure peak voltage along with phase angle
 Calculate the differential gain ( 𝑉𝑖𝑛2 =0V)

𝑉𝑖𝑛 𝑉𝐷1(𝑝) 𝑉𝐷2(𝑝) 𝐴𝐷

𝑉𝐷2 − (−𝑉𝐷1 )
𝐴𝐷 =
𝑉𝑖𝑛1 − 𝑉𝑖𝑛2

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Step3: To find Common Mode gain

Figure 7.4 Common mode gain circuit

Procedure
 Modify the circuit connections by disconnecting the ground connection at point
𝑉𝑖𝑛2 and connect this point to 𝑉𝑖𝑛1 as shown in Step3
 This circuit configuration is known as differential amplifier with a common-
mode input signal.
 Measure and record the peak values
 Calculate the common-mode gain 𝐴𝑐𝑚 and calculate the CMRR (Common
Mode Rejection Ratio) (dB)

𝑉𝑖𝑛 𝑉𝐷1(𝑝) 𝑉𝐷2(𝑝) 𝐴𝑐𝑚

𝑉𝐷2 − 𝑉𝐷1
𝐴𝑐𝑚 =
𝑉𝑖𝑛

𝐴𝐷
𝐶𝑀𝑅𝑅 = 20 ∗ 𝑙𝑜𝑔
𝐴𝑐𝑚

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 Analog Signal Processing Laboratory (EEL305) Manual

Experiment 8:
Design and testing of capacitor coupled voltage follower
and inverting amplifier for gain, frequency response, Zin.
Aim: To design and study capacitor coupled voltage follower and inverting amplifier.

Apparatus Required

Component Description Quantity

Op Amp µA741 2
Potentiometer 10kΩ 2
Resistors 220 Ω, 1kΩ, 3.3kΩ, 10kΩ, 47kΩ, 100kΩ (each 1 each
0.25W)
Capacitors 0.1µF,0.00212uF, 1µF, 4.7µF, 10µF, 100µF 1 each
Multimeters 1
DSO 20MHz 1
AFO 1
Power Supply 0 to ±30V, 50mA 1
0 to 12V, 50mA 1

Capacitor Coupled Voltage Follower:

Design: Design a capacitor coupled voltage follower using uA741 C with
𝐼𝐵(max) = 500nA. The lower cut-off frequency for the circuit is to be 150Hz and the
load resistance is 1kΩ.

Circuit Diagram

Figure 8.1 Capacitor Coupled Voltage Follower

0.1𝑉𝐵𝐸
𝑅1(𝑚𝑎𝑥) = 𝐼 = 140𝑘Ω, so let 𝑹𝟏 = 𝟏𝟎𝟎𝒌𝛀
𝐵(𝑚𝑎𝑥)
𝑅
𝑋𝐶1 = 101 𝑎𝑡 𝑓1 Hence 𝐶1 = 0.1𝜇𝐹

𝑋𝐶2 = 𝑅𝐿 𝑎𝑡 𝑓1 gives 𝐶2 = 1𝜇𝐹

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Procedure:
 Construct the capacitor coupled voltage follower circuit shown in Fig. 8.1 using
the component values determined.
 Set the power supply voltage to ±15 V, and adjust the signal generator to produce
a ±1 V peak to peak, 1 kHz sinusoidal input to the amplifier. Record the output
voltage amplitude on the laboratory record sheet and calculate the voltage gain.
 Maintaining the input voltage constant, reduce the signal frequency until vo ≈
0.707 vo. Record the lower cut-off frequency (f1).
 Return the signal frequency to 1 kHz. Connect a 100kΩ in series with the amplifier
input. Check the effect on the output voltage and Calculate Zin.
 Remove the 100kΩ and replace C2 with a 0.01μF capacitor. Repeat Procedure 1-
3.

Observation
𝑉𝑜 =
𝑉𝑂
𝐴𝐶𝐿 = =
𝑉𝑖

𝑓1 =

𝑉𝑜 =
𝑉𝑂
𝑉𝑧𝑖 = =
𝐴𝐶𝐿
𝑉𝑂 × 100𝑘
𝑍𝑖𝑛 = =
𝑉𝑖 − 𝑉𝑧𝑖

𝑓1 =

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Capacitor Coupled Inverting Amplifier:

Design an inverting amplifier using 741 op-amp. The voltage gain is to be 50. The output
amplitude is to be 2.5 V. The signal frequency range is to be 150Hz to 1.5kHz and the
load resistance is 220Ω.

Circuit Diagram

Figure 8.2 Capacitor Coupled Inverting Amplifier

Design:
Voltage Gain Av = 50, V0 = 2.5V,
For 741 op-amp 𝐼𝐵(max) = 500𝑛𝐴. Select 𝐼1 = 100 × 𝐼𝐵(max) = 50𝜇𝐴
𝑉0
𝑉𝑖 = = 50𝑚𝑉
𝐴𝑂𝐿
𝑉𝑖 𝑉𝑜
𝑅1 = = 1𝑘Ω 𝑅2 = = 50𝑘Ω = 47𝑘Ω + 3𝑘Ω
𝐼1 𝐼1
𝑅1
𝑋𝐶1 = 𝑎𝑡 𝑓1 𝐶1 = 10𝜇𝐹
10

𝑋𝐶2 = 𝑅𝐿 𝑎𝑡 𝑓1 𝐶2 = 4.7𝜇𝐹

𝑋𝐶𝑓 = 𝑅2 𝑎𝑡 𝑓2 𝐶𝑓 = 0.00212𝜇𝐹

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Procedure:

 Construct the inverting amplifier circuit shown in Fig. 8.2 using the component
values determined. Connect the power supply, signal generator, and oscilloscope
as illustrated.
 Set the power supply voltage to ±15 V, and adjust the signal generator to produce
a 1V peak to peak, 1 kHz sinusoidal input (vi) to the amplifier. Record the output
voltage amplitude (vo) on the laboratory record sheet and calculate the amplifier
gain.
 Maintaining the input voltage constant, reduce the signal frequency until vo
approximately equals 0.707 of the vo level at f = 1 kHz. Record the lower cutoff
frequency (f1).
 Still maintaining the input voltage constant, increase the signal frequency until vo
approximately equals 0.707 of the vo level at f = 1 kHz. Record the upper cutoff
frequency (f2).
 Return the signal frequency to 100 Hz. Connect a 1 kΩ in series with the amplifier
input. Check the effect on the output voltage and calculate Zin.

Observation
𝑉𝑜 =
𝑉𝑂
𝐴𝐶𝐿 = =
𝑉𝑖

𝑓1 =

𝑓2 =

𝑉𝑜 =
𝑉𝑂
𝑉𝑧𝑖 = =
𝐴𝐶𝐿
𝑉𝑂 × 1𝑘
𝑍𝑖𝑛 = =
𝑉𝑖 − 𝑉𝑧𝑖

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Experiment 9:
Design and testing of capacitor coupled non inverting
and difference amplifier for gain, frequency response and
Zin calculation
Aim: To design and study capacitor coupled non inverting amplifier and difference amplifier

Apparatus Required

Component Description Quantity

Op Amp µA741 2
Potentiometer 10kΩ 2
Resistors 220 Ω,1kΩ, 3.3kΩ, 10kΩ, 47kΩ, 100kΩ, (each 2 each
0.25W)
Capacitors 0.1µF, 0.2µF, 1µF, 4.7µF, 10µF, 100µF 1 each
Multimeters 1
DSO 20MHz 1
AFO 1
Power Supply 0 to ±30V, 50mA 1
0 to 12V, 50mA 1

Capacitor Coupled Non-Inverting Amplifier:

Design an op-amp non-inverting amplifier to have a gain of 10. Signal amplitude is to
be 0.5 V. The lower cut-off frequency for the circuit is to be 150Hz and the load
resistance is 1kΩ

Circuit Diagram

Figure 9.1 Capacitor Coupled Non-Inverting Amplifier

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Design:
For 741 opamp, 𝐼𝐵(max) = 500𝑛𝐴. Select 𝐼2 = 100 × 𝐼𝐵(max) = 50𝜇𝐴
𝑉𝑖
𝑅3 = = 10𝑘Ω
𝐼2
𝑉𝑂 𝐴𝐶𝐿 ×𝑉𝑖
𝑅2 + 𝑅3 = = = 100𝑘Ω Select 𝑅2 = 100𝑘Ω to give gain >10
𝐼2 𝐼2
0.1𝑉𝐵𝐸
𝑅1(𝑚𝑎𝑥) = = 140𝑘Ω Select𝑅1 = 100𝑘Ω
𝐼𝐵(𝑚𝑎𝑥)

𝑅1
𝑋𝐶1 = Hence 𝐶1 = 0.1𝜇𝐹
10

𝑋𝐶2 = 𝑅𝐿 𝑎𝑡 𝑓1gives 𝐶2 = 1𝜇𝐹

Procedure:

 Construct the capacitor coupled non-inverting amplifier circuit shown in Fig. 9.1
using the component values determined. Connect the power supply, signal
generator, and oscilloscope as illustrated.
 Set the power supply voltage to ±15 V, and adjust the signal generator to produce
a 1 V peak to peak, 1 kHz sinusoidal input (vi) to the amplifier. Record the output
voltage amplitude (vo) on the laboratory record sheet and calculate the amplifier
gain.
 Maintaining the input voltage constant, reduce the signal frequency until vo
approximately equals 0.707 of the vo level at f = 1 kHz. Record the lower cutoff
frequency (f1).
 Return the signal frequency to 1 kHz. Connect a 100kΩ in series with the amplifier
input. Check the effect on the output voltage and calculate Zin.

Observation
𝑉𝑜 =
𝑉𝑂
𝐴𝐶𝐿 = =
𝑉𝑖

𝑓1 =

𝑉𝑜 =

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𝑉𝑂
𝑉𝑧𝑖 = =
𝐴𝐶𝐿
𝑉𝑂 × 100𝑘
𝑍𝑖𝑛 = =
𝑉𝑖 − 𝑉𝑧𝑖

𝑓1 =

Difference Amplifier:
Design a difference amplifier using 741 op-amp. The voltage gain is to be 50. The output
amplitude is to be 2.5 V. The lower cutoff frequency is 150Hz and the load resistance is
220Ω.

Circuit Diagram

Figure 9.2 Capacitor Coupled Difference Amplifier

Design:
Voltage Gain Av = 50, V0 = 2.5V, 𝑓1 = 150 𝐻𝑧
For 741 op-amp 𝐼𝐵(max) = 500𝑛𝐴. Select 𝐼1 = 100 × 𝐼𝐵(max) = 50𝜇𝐴
𝑉0
𝑉𝑖 = = 50𝑚𝑉
𝐴𝑂𝐿
𝑉𝑖 𝑉𝑜
𝑅1 = = 1𝑘Ω 𝑅2 = = 50𝑘Ω = 47𝑘Ω + 3.3𝑘Ω , 𝑅3 = 𝑅1, 𝑅4 = 𝑅2
𝐼1 𝐼1
𝑅1
𝑋𝐶1 = 𝑎𝑡 𝑓1 𝐶1 = 10𝜇𝐹
10

𝑅3 +𝑅4
𝑋𝐶2 = 𝑎𝑡 𝑓1 𝐶2 = 0.2𝜇𝐹
10

𝑋𝐶3 = 𝑅𝐿 𝑎𝑡 𝑓1 𝐶3 = 4.7𝜇𝐹

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Procedure:

 Construct the difference amplifier circuit shown in Fig. 9.2 using the component
values determined. Connect the power supply, signal generator, and oscilloscope
as illustrated.
 Set the power supply voltage to ±15 V, and adjust the signal generator to produce
a 1V peak to peak, 1 kHz sinusoidal input (vi) to the amplifier. Record the output
voltage amplitude (vo) on the laboratory record sheet and calculate the amplifier
gain.
 Maintaining the input voltage constant, reduce the signal frequency until vo
approximately equals 0.707 of the vo level at f = 1 kHz. Record the lower cutoff
frequency (f1).
 Still maintaining the input voltage constant, increase the signal frequency until vo
approximately equals 0.707 of the vo level at f = 1 kHz. Record the upper cutoff
frequency (f2).
 Return the signal frequency to 100 Hz. Connect a 1 kΩ in series with the amplifier
input. Check the effect on the output voltage and calculate Zin.

Observation
𝑉𝑜 =
𝑉𝑂
𝐴𝐶𝐿 = =
𝑉𝑖

𝑓1 =

𝑓2 =

𝑉𝑜 =
𝑉𝑂
𝑉𝑧𝑖 = =
𝐴𝐶𝐿
𝑉𝑂 × 1𝑘
𝑍𝑖𝑛 = =
𝑉𝑖 − 𝑉𝑧𝑖

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Experiment 10:
Design and testing of unipolar op amp circuits for gain,
frequency response and Zin calculations
Aim: To design and study unipolar op amp circuits

Apparatus Required

Component Description Quantity

Op Amp µA741 2
Potentiometer 10kΩ 2
Resistors 1kΩ, 3.3kΩ, 10kΩ, 47kΩ, 100kΩ, 220kΩ (each 1 each
0.25W)
Capacitors 0.1µF, 1µF, 4.7µF, 10µF, 100µF 1 each
Multimeters 1
DSO 20MHz 1
AFO 1
Power Supply 0 to ±30V, 50mA 1
0 to 12V, 50mA 1

Capacitor Coupled Inverting Amplifier:

Design an inverting amplifier using 741 op-amp. The voltage gain is to be 50. The output
amplitude is to be 2.5 V. The signal frequency range is to be 150Hz to 1.5kHz and the
load resistance is 220Ω.

Circuit Diagram

Figure 10.2 Capacitor Coupled Inverting Amplifier

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Design:
Voltage Gain Av = 50, V0 = 2.5V, 𝑉𝐶𝐶 = 24𝑉
For 741 op-amp 𝐼𝐵(max) = 500𝑛𝐴. Select 𝐼1 = 𝐼2 = 100 × 𝐼𝐵(max) = 50𝜇𝐴
𝑉0
𝑉𝑖 = = 50𝑚𝑉
𝐴𝑂𝐿
𝑉𝑖 𝑉𝑜
𝑅1 = = 1𝑘Ω 𝑅2 = = 50𝑘Ω = 47𝑘Ω + 3.3𝑘Ω
𝐼1 𝐼1
𝑉𝐶𝐶 ⁄2
𝑅3 = 𝑅4 = = 240𝑘Ω Select 𝑅3 = 𝑅4 = 220𝑘Ω
𝐼2
𝑅1
𝑋𝐶1 = 𝑎𝑡 𝑓1 𝐶1 = 10𝜇𝐹
10

𝑋𝐶2 = 𝑅𝐿 𝑎𝑡 𝑓1 𝐶2 = 4.7𝜇𝐹

𝑋𝐶𝑓 = 𝑅2 𝑎𝑡 𝑓2 𝐶𝑓 = 0.00212𝜇𝐹

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 Analog Signal Processing Laboratory (EEL305) Manual

Procedure:

 Construct the inverting amplifier circuit shown in Fig. 1.3 using the component
values determined. Connect the power supply, signal generator, and oscilloscope
as illustrated.
 Set the power supply voltage to 24V, and adjust the signal generator to produce a
1V peak to peak, 1 kHz sinusoidal input (vi) to the amplifier. Record the output
voltage amplitude (vo) on the laboratory record sheet and calculate the amplifier
gain.
 Maintaining the input voltage constant, reduce the signal frequency until vo
approximately equals 0.707 of the vo level at f = 1 kHz. Record the lower cutoff
frequency (f1).
 Still maintaining the input voltage constant, increase the signal frequency until vo
approximately equals 0.707 of the vo level at f = 1 kHz. Record the upper cutoff
frequency (f2).
 Return the signal frequency to 100 Hz. Connect a 1 kΩ in series with the amplifier
input. Check the effect on the output voltage and calculate Zin.

Observation
𝑉𝑜 =
𝑉𝑂
𝐴𝐶𝐿 = =
𝑉𝑖

𝑓1 =

𝑓2 =

𝑉𝑜 =
𝑉𝑂
𝑉𝑧𝑖 = =
𝐴𝐶𝐿
𝑉𝑂 × 1𝑘
𝑍𝑖𝑛 = =
𝑉𝑖 − 𝑉𝑧𝑖

Department of E&E NMAM Institute of Technology, Nitte

 Analog Signal Processing Laboratory (EEL305) Manual

Capacitor Coupled Non Inverting Amplifier:

Design an op-amp non-inverting amplifier to have a gain of 10. Signal amplitude is to
be 0.5 V. The lower cut-off frequency for the circuit is to be 150Hz and the load
resistance is 1kΩ

Circuit Diagram

Figure 10.3 Capacitor Coupled Non Inverting Amplifier

Design:
For 741 opamp, 𝐼𝐵(max) = 500𝑛𝐴. Select 𝐼1 = 𝐼2 = 100 × 𝐼𝐵(max) = 50𝜇𝐴
𝑉𝐶𝐶 ⁄2
𝑅1 = 𝑅2 = = 240𝑘Ω Select 𝑅1 = 𝑅2 = 220𝑘Ω
𝐼1

𝑉𝑖
𝑅4 = = 10𝑘Ω
𝐼2
𝑉𝑂 𝐴𝐶𝐿 ×𝑉𝑖
𝑅4 + 𝑅3 = = = 100𝑘Ω Select 𝑅3 = 100𝑘Ω to give gain >10
𝐼2 𝐼2
𝑅1 ||𝑅2
𝑋𝐶1 = Hence 𝐶1 = 0.1𝜇𝐹
10

𝑋𝐶2 = 𝑅𝐿 𝑎𝑡 𝑓1gives 𝐶2 = 1𝜇𝐹

Department of E&E NMAM Institute of Technology, Nitte

 Analog Signal Processing Laboratory (EEL305) Manual

Procedure:

 Construct the capacitor coupled non-inverting amplifier circuit shown in Fig. 10.3
using the component values determined. Connect the power supply, signal
generator, and oscilloscope as illustrated..
 Set the power supply voltage to 24 V, and adjust the signal generator to produce
a 1V peak to peak, 1 kHz sinusoidal input (vi) to the amplifier. Record the output
voltage amplitude (vo) on the laboratory record sheet and calculate the amplifier
gain.
 Maintaining the input voltage constant, reduce the signal frequency until vo
approximately equals 0.707 of the vo level at f = 1 kHz. Record the lower cutoff
frequency (f1).
 Return the signal frequency to 1 kHz. Connect a 100kΩ in series with the amplifier
input. Check the effect on the output voltage and calculate Zin.

Observation
𝑉𝑜 =
𝑉𝑂
𝐴𝐶𝐿 = =
𝑉𝑖

𝑓1 =

𝑉𝑜 =
𝑉𝑂
𝑉𝑧𝑖 = =
𝐴𝐶𝐿
𝑉𝑂 × 100𝑘
𝑍𝑖𝑛 = =
𝑉𝑖 − 𝑉𝑧𝑖

𝑓1 =

Department of E&E NMAM Institute of Technology, Nitte

 Analog Signal Processing Laboratory (EEL305) Manual

Department of E&E NMAM Institute of Technology, Nitte