Computer Systems Architecture Page 1 of 5

06 Memory Organization

Multiple Choice Questions

1. The ALU is the component of the CPU where __________ and ________.
a) data is stored; instructions are interpreted
b) data is held temporarily; calculations are made
c) calculations take place; instructions are executed
d) programs are decoded; instructions are fetched
e) programs are decoded; instructions are executed

2. The Control Unit determines the ___________________

a) particular instruction to be executed by reading the contents of the program
counter
b) particular instruction to be executed by interpreting the source code
c) particular instruction to be executed by reading the IN BOX or I/O interface
d) outcome of an instruction by interpreting the ALU output
e) outcome of an instruction by reading the IN BOX or I/O interface

3. A register is a single permanent storage location within the CPU use for _________
a) general purpose operations
b) specifically designed for fetching instructions
c) specifically designed for arithmetic operations
d) specifically designed for I/O operations
e) a particular, defined purpose

4. Registers differ from regular main memory in that they _________.

a) very in size, serve a particular purpose, wired differently but are addressed the
same
b) are usually smaller is size, but are wired for special functions and serve a
specific function
c) very in size, serve a wider purpose, wired differently and are addressed
differently
d) very in size, serve a particular purpose, wired differently and are addressed
differently
e) have constant size, serve a particular purpose, wired differently and are
addressed differently

5. The Control unit contains the following registers:

a) execution time, instruction, PSW and memory data
b) execution, instruction, PSW and memory data
c) program counter, instruction, memory address and memory data
d) execution time, instruction, memory address and memory data
e) program counter, instruction, memory address and PSW

6. Status registers use ________ to communicate problems

a) an 8-bit super fast registers
b) flags
c) floating point values
d) integer values

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e) I/O

7. For simplification, the text views the I/O interface as

a) a pair of I/O registers: one for input; one for output
b) a functional component
c) a separate function utilizing an abstract algorithm
d) part of the ALU
e) part of the Control Unit

8. What operation is NOT supported by most registers?

a) data movement between registers and memory
b) data from another register can be added to or subtracted from the value
previously stored
c) shifting and rotations
d) data validation
e) data in a register can be tested for zero; positive or too large to fit

9. Memory is composed of
a) 1-bit cells and each cell is addressable
b) 16-bit cells and each cell is addressable
c) rows of 8-bit cells where each bit is addressable
d) rows of 1-bit cells or more and only addressable in rows
e) either multiple or single 8-bit addressable cells; addresses are calculated
as needed

10. The Memory Data Register (MDR) is designed such that it

a) is physically connected to each cell in memory
b) is logically connected to all registers
c) can be activated by the program counter
d) is effectively connected to every cell in the memory unit
e) can be activated by the computer hardware

11. The Memory Data Register (MDR) and the Memory Address Register (MAR) are
designed such that it
a) the MDR activates the Bus Interface Unit while the MAR reads bits that are
activated
b) the MDR activates the desired address line while the MAR reads bits that are
activated
c) the MAR activates the desired address line while the MDR reads bits that
are activated
d) the MAR copies the contents of a line into a buffer while the MDR processes
the buffer
e) the MDR copies the contents of a line into a buffer while the MAR processes
the buffer

12. The address decoder has the job of _________.

a) simultaneously opening the address line and incrementing the next instruction
counter
b) locating the next instruction in memory
c) calculating the optimum address line for the MDR to process

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d) decoding instructions and locating the desired memory location

e) interprets the address from the MAR and activates a single address line
into memory

13. When retrieving or storing data at a particular memory location, the first step in the
CPU memory interaction is to __________.
a) allocate the MAR the necessary number of bits to retrieve the address line
b) transfer data from some register to the MDR (for a WRTE) OR transfer data
from the MDR to some register (for a READ)
c) send a message to the Control Unit stating there is a READ (or WRITE
condition)
d) copy an address from some register to the MAR
e) copy an address from some register to the MDR

14. When retrieving or storing data at a particular memory location, the two actions that
occur simultaneously are___________.
a) (1) copy an address from some register to the MAR and (2) send a message to
the control unit stating there is a READ (or WRITE condition)
b) (1) copy an address from some register to the MAR and (2) send a
message to the memory unit stating there is a READ (or WRITE
condition)
c) (1) copy an address from some register to the MDR and a message to the
memory unit stating there is a READ (or WRITE condition)
d) (1) Load (or read) the MAR with data to be transferred, and (2) send a
message to the memory unit stating there is a READ (or WRITE condition)
e) (1) Set the READ (or Write bit) in the PSW and (2) Load (or read) the MDR
to some register in memory

15. The two factors that determine the capacity of the address space are ________.
a) the number of bits in the memory address register and the number of
bits in the address field
b) the size of memory and the number of bits in the address field
c) the number of bits in the memory address register and the size of memory
d) the word length format and the hardware
e) the word length format and the software

16. The number of address that the MAR can access is ________ the size of the address
field
a) always 2k where k is the number of bits
b) at least 2k where k is the number of bits
c) at most 2k where k is the number of bits
d) at least 2k -1 where k is the number of bits
e) variable and changes with physical memory modules

17. Dynamic RAM is ___________ compared to static RAM

a) more expensive, requires less electrical power and can be made smaller with
more capacity
b) less expensive, requires more electrical power and can be made smaller
with more capacity

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c) less expensive, requires less electrical power and can be made smaller with
more capacity
d) less expensive, requires less electrical power and has less capacity
e) utilized in laptop computers and is utilized as cache memory

18. EEPROM and Flash ROM _________.

a) are Read Only Memory and can never be changed
b) are Read Only Memory and can be changed one time
c) are cheap but are limited in access time
d) implement non-volatile, rewritable memory
e) implement volatile, rewritable memory

19. The fetch-execution cycle is________.

a) significantly influences the cost of CPU manufacturing
b) the basis for every capability of a computer
c) the basis for most capabilities of a computer
d) one of many important factors determining the capability of ALL computers
e) one of many important factors determining the capability of MOST computers

20. The first step in every instruction, according to text, is _____________.

a) increment the program counter
b) transfer the address into the Memory Data Register
c) transfer the value into the Memory Data Register
d) decode the instruction
e) transfer the address of the instruction to the Memory Address Register

21. In the notation of the text, IR [ address ]  MAR means________.

a) read the data located in the address and place it into the MAR
b) transfer the IR into the MAR
c) transfer the address part of the instruction into the MAR
d) transfer the op-code of the instruction into the MAR
e) transfer the content of the IR into the MAR

22. The execution cycle is _________.

a) different for every instruction
b) the same for every instruction
c) software based, while the fetch portion is hardware based
d) hardware based, while the fetch portion is software
e) both (a) and (d)

23. The last action taken by the CPU in the fetch-execution cycle is:
a) simultaneously IR[address] MAR and MDR  IR
b) IR[address] MAR
c) MDRMAR
d) PC + 1  PC
e) MDRIR

24. The action that occurs simultaneously is:

a) IR[address] MAR and instruction being transferred is sent to the MDR
b) PC  MAR and the instruction being transferred is sent to the MDR

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c) MDR  IR and the instruction being transferred is sent to the MDR

d) IR[address] MDR and MAR  IR
e) IR[address] MAR and PC + 1  PC

25. The LOAD instruction takes __________ steps to execute

a) 4
b) at least 4
c) 5
d) at least 5
e) 6

26. All instructions take ___________ steps to complete

a) 4
b) at least 4
c) 5
d) at least 5
e) an undetermined number, depends on the instruction

27. The physical connection that makes it possible to transfer data from one location to
another is called a _________.
a) registers AND the bus interface unit
b) registers
c) bus interface unit
d) bus
e) control unit

28. What is NOT a true about Buses?

a) connecting computer peripherals and the CPU
b) transferring data from the CPU and memory
c) connecting the power supply and RAM with the motherboard
d) might be a tiny fraction of an inch long
e) vary in length from fractions of an inch to several hundreds of feet long

29. When a bus connects a specific source to a specific destination they are called
_______ buses.
a) 'source – destination'
b) integrated
c) limited
d) dedicated
e) point-to-point

30. The cable that connects the serial or parallel port to the printer is an example of a
______bus.
a) 'source – destination'
b) integrated
c) limited
d) dedicated
e) point-to-point

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