Computer Arithmetic

Data can be fixed point or floating

representation, Signed or unsigned representation.
Signed and Unsigned
representation
Negative integers in binary number systems must be encoded
using signed number
representations. In mathematics, negative numbers are denoted by a minus sign
them. In contrast, numbers are (-") before
exclusively represented as bit sequences in
hardware, with no additional symbols. computer
Signed binary numbers (tve or -ve) can be
represented in one of three ways:
1. Sign-Magnitude form
2. 1's complement form
3. 2's complement form

Ifk bits are used to represent the number (for

magnitude), then the range of number that can
be represented by signed, 1s complement and 2's
complement are.
Signed representation: range from -(2k-)-1) to(2)-1), for k bits.
1'scomplement representation: range from -(2k-)-1) to(2k-).1), for k bits.
2's complementation representation: range from -(2) to (2k-)-1), for k bits.

If k=3, total number of bits are 4.

Signed magnitude =+7

1's Complement =+7

2's complement representation =+7to -8

Fixed point representation

This representation has fixed number of bits for integer part and for fractional part. For
example, if given fixed-point representation is XXXX.XXXX, then you can store minimum
value is 0000.0001 and maximum value is 9999.9999. There are three parts of a fixed-point
number representation: the sign field, integer field, and fractional field. Binary or decimal
point is fixed.
 Floating point representation
In the fixed point representation binary or decimal point is the same place.
0.23, 5.12 and
10010.11101 and 0.1110.

Decimal floating point is represented as

Exponent
Mantissa

6.0210 X1023

Base or
radix

Binary floating point

1.0010, x 21011

General format of floating point representation is

Mx BE
M is mantissa, B is the base or radix and E is exponent. Base is a
constant, it need not store.
Floating point number is stored as word (M,E) pair signed fixed point number. Suppose for a
number system M and E are represented as 3-bit signed magnitude and base is 2. M and E
can be +0, ±1, +2, 3, Floating point number N is represented as
combination of (M,E) that
can be (xXXX, XXX).

Zero is represented by (M, E)=(x00,xxx).

The smallest positive number is represented by (001,111) = 1x 2-3 = 0.125

The largest positive number is represented by (011,011) = 3 x 28 = 24.0

Largest negative number is represented by (111,011) =-3 x 23 = -24.0

Precision: The smallest number that can be represented by number system, distance between
two adjacent number on a number line. For example, 0.125 is the precision of above number
system.

Range: Distance between the largest positive and negative number represented by number
system. For given number system range is + 24 to -24.
 Overflow: Conditionwhen we try to represent the number which value is out of the range of
given number system. If we try to represent 50 by using above representation it will show the
overflow condition.
Underflow: Condition when we try to represent the number which value is less than the
precision of that number system. For example if try to represent the nunber less than 0.125 it
will be under flow.

Normalizing the Mantissa

Before a floating-point binary number can be stored correctly, its mantissa must be
normalized. The process is basically the same as when normalizing a floating-point decimal
number. For example, decimal 1234.567 are normalized as 1.234567 x 10° by moving the
decimal point so that only one digit appears before the decimal. The exponent expresses the
number of positions the decimal point was moved left (positive exponent) or moved right
(negative exponent).
Similarly, the floating-point binaryvalue 1101.101 is normalized as 1.101101 x 2² by moving
the decimal point 3 positions to the left, and multiplying by 2. Here are some examples of
normalizations:

Binary Value Normalized As Exponent

1101.101 |1.101101 3

.00101 1.01 3

|1.0001 1.0001
10000011.0 1.0000011 7

IEEE754 (floating point representation)

1bit for the sign, 8 bits for the exponent, and 23 bits for the
IEEE Short Real: 32 bits mantissa. Also called single precision.
(single precision)

IEEE Long Real: 64 bits 1 bit for the sign, 11 bits for the exponent, and 52 bits for the
(double precision) mantissa. Also called double precision.
The bits in an IEEE 754 (32 bit) are arranged as follows, with the most significant bit
(MSB)
on the left:
 2322
Signt
Exponent Mantissa (23 bit)
(8 bits)
IEEE 754 (32-bit )

A 32-bit floating point number

number Nis given conforming to the IEEE 754 standard represented the real
by the formula

N= (-12E-127 (1. M)
provided that 0< E<255
The exponent is the 8-bit excess-127 code, hence the
127. The base of the floating point number is 2. Inactual exponent value is computed as E
actually 1.M, where the 1to the left of the binary pointthisis format
an
the complete mantissa is
implicit or hidden leading bit
that is not stored with the number. It is
representation.
represented in the form of 1.M, it is normalized

Nonzero floating point number in this format have

magnitude ranging from
2-126(1.0) to 2+127 (2 - 2-23) that is, from 1.18 × 10-38 to 3.40
For 32-bit following set of x 1038 approximately.
interpretation:
If E= 255 and M#0,then N = NaN. Not a valid floating number
If E= 255 and M= 0,then N =
(-1)Soo Overflow (o)
If 0 <E<255 then N= (-1)2E-127 (1. M)
Valid floating point number
If E = 0 and M # 0, then N
=(-1)$2E-126 (0. M). Underflow
If E= 0and M = 0, then N =(-1)$0.
Number is zero

Ex. Number N= -317 -3-7S

1step change in to binary -11.11 =-1.111 x 21

Compare with standard representationN = (-1)2E-127 (1. M)
E-127 =1, that gives E =128 =(10000000)
S=1

M=1110000000......

In IEEE 754 format it will be represented as

I0O000|0|0| 1|ITO0o000000o|00|000|0O000
 Computer Arithmetic
Fixed point Arithmetic
Adder
The basic building block for most
arithmetic circuits is the full adder. A fulladder is a logic
circuit that produces a two-bit sum (Si and
CiHl) of three one-bit binary numbers (Xi, Yi and
Ci). Table A.1shows the truth table a
for full adder. Alogic symbol and
of a full adder are shown in gate-level real1zation
Figure A.1
Inputs are Xi, Yiand Ci
Outputs are Si and Ci+1

Sum Si=XY:G+X
YCi + XiYCi +X:YG
Carry Ci+l =XiYi + YCi +XC:

Xi
Yi
Si
Ci
X Yi

Ci+1 FA
C -
-

Ci1

S
Full Adder
Full Adder
(Block Diagram) (Gate level realization )

Figure A.1: Full adder block diagram and gate level realization
TableA.1: Full Adder TruthTable
Xi Yi Ci Si(Sum) Ci+1 (Carry)
0 0 0
0 0
0
1 1
1 1 1
1 0 1 0 1
 /

1
1 1 1 1

The design of logical circuit may be time or pace iteration. In time iteration circuit is simple
but ncreased time. However, in space iteration increased hardware with reduced time.
Basic block diagram for time iterative design is given below for 4-bit addition. Two 4-bit data
Xand Yare stored in 4-bit shift registers and 4-bit result S is stored in 4-bit shift register:.

FA
Y Carry

Serial adder
(time iteration implementation)

Figure A.2 Serial adder

The addition of two n-bit binary
numbers (X= Xn-1, ---XI, XO and Y=
adders cascaded, as shown in figure A.3.Yn-1,....,
and can be calculated with n full Yo )
called a ripple-carry adder., since Such a circuit is
carries produced by lower-order stages
ripple through the must propagate or
higher-order stages before completing the addition operation.
Xn-1 Yn-1
X1 Y1 Xo Yo

Cn FA n-1
Cn-1 FA1 FAo
Ca
Co

Sn-t
S1
So
n-bit ripple carry adder

Figure A.3: n-bit ripple carry adder

 umber.
Yo d using
Y2 X1 Y
X3 Y3 X2
add the
m treats
FAO Co
FA3 FA2 FA1
C1 þr 1's in
C4 C
e at the

S
So In this
S2
blier are
4-bit ripple carry adder er steps

carryadder ined by
Figure A.4:4-bit ripple here the
een.

4-bit ripple carry adder:

Time computation for
gate delays,
o stage:
after l gate delay, c, is available after 2
s, is available

after 4 gate delays.

1st stage:
available after 3 gate delays, c, available
s,
ontains
2ndstage: after6 gate delays.
available after 5 gate delays, c, available Ind one
s,
delays
3rd stage after 7 gate delays, c, available after 8 gate
s,available case (X =
and structure but are slow. n the worst propagate
Ripple-carry adders are
simple in operation least-significant full adder must
=0...01), a carry produced in the
1...11) and (Y significant ones.
through the more available afte r 2n gate
after 2n -1 gate delays c is
s. is available
For an n-bit adder,
delays.
High-Speed Adders: addition. These inchude
perform high speed
have been developed to adders and carry
Several adder designs carry-completion adders, conditional-sum acceptance in the
wide
carry-lookahead adders (CLAs),Carry-lookahead adders have gainedconveniently implemented in
adders, carry skip adder. because they can be
select and
to their speed
design of ALUs due
integrated-circuit form.
 / ITnoinnad ..

Carry propagation network:

The main part of an
generate) adder is the carry
and p (carry
propagate)
produce the g, p, and s terms. network. Rest is ust a set of gates to
signals and the sum produce the g(carry
carry-in (Co) to carry-out Most of the delay in the bits. One gate delay is required
for high speed
adder. (C).is Therefore, main target isconsumed
skip adder, carry There to
in
propagate the delay to
reduce the carry from
store adder anddifferent type of fast adders like look propagation time
parallel preftx adder etc. ahead carry adder, carry

Pa-l
&n-2Pn-2 Pi+l
P Po
C, 8o|
Carry Network
Co
C-l
C

S;
Carry Propagation Network

gi =Xi Yi
(carry generate)
Pi= X{ yi (carry
propagate)
Ci+1 = git pi Ct

Carry will go into

i is
propagated by position it1if it is
ith position. It is generated in position i or if a carry that is
represented by table below. enters in position

gi PiAction with carry

0
annihilated or killed
propagate
1 generate
1
Impossible
 Signed Multiplier

-mnf's complement signed representation number.

inht to left and using

Carry propagation
length
Bit
12 11 10 9
position 7 6 4 3 2
0 1
Cout 1 0
1 0 1
1 1

Carry propagation Carry is killed Carry propagated

length p=xy Carry generated
g=xy
After revisiting the ripple carry
adder, carry network can be redrawn as given below.

8n-1 Pn-i 81-2 Pn-2 Pi

C,
Carry Propagation Network of ripple carry
adder

Total time required (latency) for ripple carry adder is :

1 gate delay for production of p and g
signals, plus
2(n-1) gate delay for carry propagation, plus
lgate delay for generation of the sum bits.
The refore,total time to produce the sum ofn bit adder will be 2n
gate delay.
 Carry-lookahead adder:
Let us consider the design of a
4-bit adder. The carries can be
Cq= 9o +Po Co implemented as
Cz = 91tpi C 91 +p1 go +P1Po Co
C3 = g2tp2 Cz = 92+ P2 91
+P2P19go + P2P1poCo
C4 = 93 +P3 C3 = g3 +P3 92+ P3P21 +
P3P2P19o + p3PzPiPoCo
From the above equations, it is clear that to generate the all
carries (c, to
(AND and OR) is required which is very easy to design and fabricate. Basicc) two gate delay
4-bit carry lookahead adder with 4-bit carry lookahead block diagram of
generator given below. To generate
the final sum bits, total 4 gate delay required. One gate delay is
for g andp signals, two gate delay
for carry generation network and one gate delay for sum bits.

83 P3 81P, 8oPo

82
4-bit Carry lookahead
generator Co

4-bit Carry lookahead adder

(CLA)

4-bit Carry lookahead adder

(CLA)

S So
S
 mu them operationst8
isusedfor inyolvescanning the algorithmtreats
whichof Booth
mine tinn.The of0's or1'sin
-n atthe

Inthis
are

Carry lookahe ad carry adder is not ster

prefe rred bevond 4bits. Consider a 32
bit adder ned
here
c= 9otpo Co
, seen
C2 = 91 tPi Cy = 91tP1 9o
+pipoco
C3= 92+P2 Cz = g2+p2
91+p2P19ot P2P1PoCo
C4 = 3+P3 C3 = g3 + p3 g2+
P:P2g1tp3P2P19go +P3P2P1PoCo
32 inputAND
C31 = 930 + P30 g29 + P30P29928.tP29P28.
3. PoCo hultip
opera

aple.

32 input OR

Fabrication of 32-bit AND and OR gate is very dificult, therefore CLA is not preferred beyond
4-bit. Cascaded (carry ripple through) design can be used for higher size adder using 4-bit CLA
as a basic element.

Single level design of 16-bit adder using 4-bit CLA is given below.

Ys-1 g-11 Yo-3 0-3

Y2-1s 2-15

4-bit CLA 4-bit CLA

4-bit CLA G2 4-bit CLA
C6
So-3
S12-15 Sg-i1
16-bit CLA

DelaycaBculation: C
p, 2 gate for carry propagation from
the C:(1gate delay for g and
3 gate delay to generate
to C)
propagate carry from C4 to C&
2gate delay for
 Led
from Cg to Ci2
2 gate delay for propagate carry
th
to C16
delay for propagate carry from C12 (KOR) gate
2 gate available after 1gate pot
S;s will be
9 gate delay and sum
Carry C6 is avaiable after khe
delay).
delay (total 10 gate adder built from 4 bit
adder
show the 16-bit
adder: igure given below therefore,
Two level 16-bit g and p, where k is level,
generate the two signals
block. 2nd Jevel carry logic the first
k=1 for second 4-bit block and so on. In
blocks) k=0, and
for first level (first 4-bit
adder block
P3P2P19o
på =P3P2P1Po and go = 93 tP3g2 t PsP291+
P7PePsg4
Pi=PP6PsP4 and gi = g7 t Prg6 t pP6gs +
P11P10 P9I8
p = P11P1o P9P8 and g = g11 + P11g1o + P11P10 99 +
P15P14 P13I12
p= P1sP4P13P12 and g = 915 + P15914 t P1sP14I13 +

Y4-7 DÍ-3 Mo-3

V2-15 2-15

4-bit CLA C12 4-bit CLA 4-bit CLA 4-bit CLA Co

ial

S12-15 Sg-11 S4-1 So-3 Pr

8 p
1
Carry look ahead logic

Po
2 level 16-bit CLA

Carry C6 is formed by the carry look-ahead circuit.

These expressions for C16, C12, Cg, C4 are identical in from of the C4, Cg, Cz, CË of basic carry
lookahead circuit. Therefore, carry look-ahead circuit given in two level logic is same as 4-bit
basic caTy look-ahead generate logic.
 1000
Multinlier

Delay calculation
1gate delay to produce g and p signals.
2 gate delay to produce the signals gå and p,.
2 gate delay to produce any carrier cks Cub,Co. C.. Therefore C16 will be available after 5 gate
delay after x, y and Co are applied as input to adder.
C12 is available after 5gate delay which willtake other 2gate delay to propagate up to C1sthe
and other one (XOR) gate delay to produce the Sit, therefor total 8 gate delay to produce
final sum bits.
In two level 16-bit CLA requires 5 and8 gate delay to produce C16 and S15 respectively,
however a 16-bit adder designed by cascading 4-bit adder takes 9 and 10 gate delay to
produce them.
Similarly, higher bit adder like 32-bit and 64-bit adder can be designed by using 16-bit adder
and multi-level or cascaded design.
We can include the logic for overflow, carry, sign and zero status by designing external
circuit.

Signed Addition/Subtraction:
Follow circuit can be used for signed addition/ subtraction. This also includes the overflow,
carry and zero status. These can be used check the status of result and make any correction if
required.

X3 Y3 X2 Y2 X1 Xo Yo

C4 - FA FA FA FA
C3 C C1 Co
V 3+

N S2 S1 So

V= Overflow S3 =Sign
Z= Zero C4 =Carry
Status bits

Study yourself:
Carry skip adder and carry store adder, and compare with carry propagate (ripple) adder.
for first level (first 4-bit
blocks) k = 0, and k =1 for second 4-bit
adder block block and so on. In the first
Po =P3P2P1Po and
g = 93 +P392 +
PsP291 t P3P2P19o
pi=piP6PsP4 and
gi = g7 tp796 t
prP6gs t PP6PsJ4
pi =P11P10PP8 and gi = 911+ P11J10 +
Pi1P10g + P11P10P998
p=P1sPi4P13P12 and
g3 = 915 + P1s914 t
P1sPi4g13 t P1sP14P13912

Y12-15 2-15 Y&-11 -11

Yo-3 X0-3
6 4-bit CLA 4-bit CLA 4-bit CLA C
|4-bit CLA
S12-15 Sg-11 S4-7
So-3
Carry look ahead logic

Po 8,
2 level 16-bit CLA
Carry C1sis formed by the carry
look-ahead circuit.
C16 = 9 t psgt t ppgi +ppipig× +
These expressions for C16, C12, Cg, C4
pap2pipico
are identical in from of the C4, C3,
lookahead circuit. Therefore, carry look-ahead circuit Cz, C of basic
basic carry look-ahead generate logic. given in two level logic is samecarry
as 4-bit