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114 views

Not Redistribute: Primetime Workshop

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Available Formats

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You are on page 1/ 89

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CUSTOMER EDUCATION SERVICES

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PrimeTime

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Workshop

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Lab Guide
10-I-034-SLG-017 2021.06-SP1
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©

Synopsys Customer Education Services

690 E. Middlefield Road

Mountain View, California 94043
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Workshop Registration: https://training.synopsys.com

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Primetime Workshop

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1

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PrimeTime Flow

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Learning Objectives
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After completing this lab, you should be able to:
Restore a previously saved PrimeTime session
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OPTIONALLY, Take advantage of helpful PrimeTime

commands that will make you more efficient when using

PrimeTime interactively and show you how to find more
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information on commands, variables and your design

library
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Validate a restored save-session.

Exercise recommended Primetime flow
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Interpret key components of a timing report for setup

and hold timing checks
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Lab Duration:
45 minutes

PrimeTime Flow Lab 1-1

Synopsys 10-I-034-SLG-017
Lab 1

Overview

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Restore a PrimeTime

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session.

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Learn helpful commands.

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[OPTIONAL Task]

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Validate a restored saved
session and Exercise
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Interpret a setup and hold
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timing report.
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Relevant Files and Directories

All files for this lab are located in the lab1_flow directory under your home
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directory.
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lab1_flow/ Current working directory

common_setup.tcl multi-tool shared setup file
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pt_setup.tcl tool-specific PrimeTime setup file

pt_scripts/ Run file directory

pt.tcl Run file
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.synopsys_pt.setup automatically-read PT setup file.

orca_savesession Saved session directory

RUN.tcl Run script for orca_savesession

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Answers / Solutions
This lab guide contains answers and solutions to all questions. If you need some
help with answering a question or would like to confirm your results, check the back
portion of this lab.

Lab 1-2 PrimeTime Flow

Instructions

Your goal is to get used to PrimeTime by validating a restored save session,

exercising the recommended flow, and analyzing the setup/hold reports.

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Task 1. Restore a PrimeTime Sesssion

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Invoke a previously saved PrimeTime session to perform STA.

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Invoke PrimeTime from the lab1_flow workshop lab Unix directory.

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unix% cd lab1_flow

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unix% pt_shell

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Restore a previously saved PrimeTime session. This step will read in the
design netlist, libraries, and constraints. The design is now ready for

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analysis.

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Note: The orca_savesession below is a Unix directory.
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Note: The orca_savesession can be recreated, if needed,
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using: pt_shell -f RUN.tcl | tee -i run.log
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Note: Any PARA-124 Errors during the execution of RUN.tcl

(within the parasitics_command.log file) can be safely
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ignored for the purpose of our labs.

Note: PrimeTime supports command, option, variable and file

completion. Type a few letters and then hit the tab key.
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pt_shell> restore_session orca_savesession

Generate coverage analysis report

pt_shell> report_analysis_coverage
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Question 1. What is the name of the design under analysis?

...............................................................................................
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Question 2. How many setup and hold violations does ORCA have?
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...............................................................................................

PrimeTime Flow Lab 1-3

Primetime Workshop © 2021 Synopsys, Inc.
Lab 1

Generate global timing report

pt_shell> report_global_timing

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Question 3. How many are reg-reg setup and hold violations?

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………… .................................................................................

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Lab 1-4 PrimeTime Flow

Task 2. [OPTIONAL TASK] Explore Helpful Commands

Execute the following three history short cut commands:

pt_shell> history

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pt_shell> !!

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pt_shell> !2

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Question 4. Describe the difference between the last two history

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commands above.

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...............................................................................................

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Use up and down arrows to scroll through the history event list as an

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alternative to the previous step.
Type the following to see all the available key bindings (in the default emacs
editing mode).

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pt_shell> list_key_bindings
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Explore the page mode alias; execute the following command, which will
generate a report that scrolls off the screen:
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pt_shell> report_timing –group [get_path_group

*]
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Turn on page mode.

pt_shell> page_on
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pt_shell> !rep
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Use the space bar and Enter keys to page through a long report. Quit from
a long report in page mode by typing “q”. If you want to turn off page mode,
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use the command alias page_off.

Send a timing report to a separate window with the view Tcl procedure.
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pt_shell> view report_timing –group [get_path_group *]

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PrimeTime Flow Lab 1-5

Primetime Workshop © 2021 Synopsys, Inc.
Lab 1

Find the command to restore a PrimeTime session and then display help
information on this command.

pt_shell> help restore*

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pt_shell> man restore_session

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pt_shell> restore_session –help

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Note: The following is an alternative way to display syntax help.

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pt_shell> help –v restore_session

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Question 5. From the last command above, does the command
restore_session accept switches?

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...............................................................................................

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The time unit in PrimeTime is determined by the main technology library.

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To find the time unit for ORCA, first list all libraries in memory.
Note: The * in the following report indicates the main library.
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pt_shell> list_lib
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Generate a report for the main library which will state the time unit.
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Note: Use copy and paste to avoid mistyping the lib name. The
time unit is at the very top of the report.
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pt_shell> report_lib cb13fs120_tsmc_max

Question 6. What is the time unit used for timing reports (as well as all
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other reports) for the ORCA design?

...............................................................................................
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Note: Do not forget to use “q” to quit from a long report in page
mode and return to the pt_shell prompt without reading
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the entire report!

Display units used by the current design.

pt_shell> report_units

Lab 1-6 PrimeTime Flow

Task 3. Validate an Existing PrimeTime Session

In this task, you will validate the inputs that have been read into PrimeTime:
the current design and libraries, the backannotation and constraints.

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Verify that the current design is your top-level module: ORCA

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pt_shell> current_design

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Compare the unix paths of the libraries to what has been read into PrimeTime

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pt_shell> printvar search_path

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pt_shell> printvar link_path

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pt_shell> list_libraries

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Question 7. Have the 4 libraries in the link_path been
successfully read into PrimeTime?

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.................................................................................

Question 8. Which library defines the defaults for time units,

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operating conditions, and other delay calculation
information?
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.................................................................................
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Question 9. What time unit is used?

.................................................................................
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Verify that the nets are completely annotated.

pt_shell> report_annotated_parasitics
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Question 10. Are there any nets that are not annotated?
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.................................................................................
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Question 11. What option to report_annotated_parasitics

would be good to use as a ‘next step’ in debugging
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the missing nets?

.................................................................................

PrimeTime Flow Lab 1-7

Primetime Workshop © 2021 Synopsys, Inc.
Lab 1

Verify that the design is completely constrained.

pt_shell> check_timing

Question 12. What option to check_timing would be good to

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use as a ‘next step’ in debugging the missing
constraints?

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.................................................................................

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Verify that the checks in your cells are completely exercised; look at possible
causes for your findings.

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pt_shell> report_analysis_coverage

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pt_shell> report_case_analysis

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Question 13. Is it logical that many of your timing checks are untested?

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...............................................................................................

Quit PrimeTime.
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pt_shell> quit
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Lab 1-8 PrimeTime Flow

Task 4. Execute the Run Script and Analyze the run

Execute the run script logging the results to the log file run.log.

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UNIX> pt_shell –f ./pt_scripts/pt.tcl | tee –i

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run.log

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Question 14. Were there any errors during the execution of the

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run script?

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.................................................................................

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If there are any errors, address these first before moving on to the next step.

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Evaluate your log file. With a text editor, open your log file. Search for the
update timing messages (UITE-214), print_message_info output,

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and the quit output. Then, in your profile directory, examine the file
tcl_profile_sorted_by_cpu_time.

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Question 15. What step required the most CPU time?

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.................................................................................
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Question 16. What commands were causing UITE-214
messages?
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.................................................................................
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.................................................................................
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Question 17. Can any of the timing updates be avoided?

.................................................................................
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Question 18. Why might the quit command output be a good

place to start before reviewing your log file?
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.................................................................................
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PrimeTime Flow Lab 1-9

Primetime Workshop © 2021 Synopsys, Inc.
Lab 1

Task 5. Analyze STA Reports

Generate and intepret two STA reports for setup and hold for SYS_CLK.

Invoke PrimeTime and restore the session that you saved in the previous

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task

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unix% pt_shell

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pt_shell> restore_session my_savesession

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Execute the following to display the clocks in ORCA:

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pt_shell> report_clock

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Question 19. How many clocks are in ORCA?

..............................................................................................

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Create a single, “short” timing report for setup for the clock SYS_CLK. Use
command-line expansion (the tab key) to expand both the command AND
.
the options –group and –path.
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pt_shell> report_timing –group SYS_CLK –path

short
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Note: The lines containing the data path cells and their delays are
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removed from the data arrival section making this report

“short”.
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Note: The above command generates a report for setup by

default.

Question 20. There are at least 4 clues that this report is for setup and not
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for hold. How many can you identify?

...............................................................................................
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...............................................................................................
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Question 21. Identify the instance names of the start and end point
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flip-flops.

...............................................................................................
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Lab 1-10 PrimeTime Flow

Question 22. The clock skew for this timing path is 0.511ns; which two
lines in the report can you use to calculate this?

...............................................................................................

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Question 23. How does this clock skew affect slack (i.e. does the clock

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skew help or hurt slack)?

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...............................................................................................

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Question 24. How large is the violation in comparison to the clock period?

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...............................................................................................

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Generate a timing report for hold time.

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The following is a short cut that will execute the last command in history
starting with the letters “rep” and add the switch –delay min (which will

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generate a report for hold time).

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pt_shell> !rep –delay min

Question 25. D
There are at least 4 clues that indicate this is a hold report
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and not a setup report. How many can you find?
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...............................................................................................
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Question 26. How does the clock skew in this hold report affect slack (i.e.
does the clock skew help or hurt slack)?
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...............................................................................................
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Quit PrimeTime.
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pt_shell> quit
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This completes Lab 1. Return to lecture.

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PrimeTime Flow Lab 1-11

Primetime Workshop © 2021 Synopsys, Inc.
Lab 1 Answers / Solutions

Answers / Solutions

Question 1. What is the name of the design under analysis?

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The design is ORCA.

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Question 2. How many setup and hold violations does ORCA have?

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There are 23 setup and 53 hold violations.

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Question 3. How many are reg-reg setup and hold violations?

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There are 9 setup and 53 hold violations of type reg-reg.

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Question 4. Describe the difference between the last two history

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commands above.

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The command !2 repeats the 2nd command executed in
history. The command !! repeats the last executed
command in history.

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Question 5. From the last command above, does the command

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restore_session accept switches?
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Yes, it accepts a session name, allowing a user to specify
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which of many saved sessions to restore.

Question 6. What is the time unit used for timing reports (as well as all
other reports) for the ORCA design?
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1ns.
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Question 7. Have the 4 libraries in the link_path been successfully read

into PrimeTime?
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Yes – the four libraries specified with link_library are

the same as those displayed with list_libraries.

Question 8. Which library defines the defaults for time units, operating
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conditions, and other delay calculation information?

cb13fs120_tsmc_max – the asterisk to the left of the library

(from list_libraries) indicates ‘main library’
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Lab 1-12 PrimeTime Flow

Question 9. What time unit is used?

pt_shell> report_lib cb13fs120_tsmc_max

****************************************
Report : library

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Library: cb13fs120_tsmc_max

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****************************************

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Time Unit : 1 ns

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pt_shell> report_units
****************************************
Report : units

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Design : ORCA
****************************************

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Units
---------------------------------------------

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Capacitive_load_unit : 1e-12 Farad

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Current_unit : 1e-06 Amp
Resistance_unit : 1000 Ohm
Time_unit : 1e-09 Second
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Question 10. Are there any nets that are not annotated?
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Yes: there are some internal driverless nets and some

boundary pin-to-pin nets that are not annotated.
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Question 11. What option to report_annotated_parasitics

would be good to use as a ‘next step’ in debugging the

missing nets?
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report_annotated_parasitics –help shows

options; the -list_not_annotated option shows
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the net names; you might want to focus in on the pin-to-pin

nets by using the –pin_to_pin_nets option.
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Question 12. What option to check_timing would be good to use as

a ‘next step’ in debugging the missing constraints?

check_timing –help displays a list of options: the

–verbose option lists the unconstrained endpoints

PrimeTime Flow Lab 1-13

Primetime Workshop © 2021 Synopsys, Inc.
Lab 1 Answers / Solutions

Question 13. Is it logical that many of your checks are untested?

Yes – test_mode, scan_en, and power_save are

constrained off – performing STA on additional modes
might enable more checks to be tested.

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Question 14. Were there any errors during the execution of the run
script?

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No. The “run script” is setup such that any errors will

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terminate the script in the middle of execution. If the script

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completes, no errors occurred during execution of the run
script. Moreover, from the “Diagnostics Summary”

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messages at the end of the log file from the quit command,
there were no errors during the run.

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Question 15. What step required the most CPU time?
For this lab, sourcing the constraints took the most CPU

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time. (From the “tcl_profile_sorted_by_cpu_time” file)

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Question 16. What commands were responsible for UITE-214
messages?

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update_timing –full and a call to a macro
PLL_SHIFT which invoked update_timing
.
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Question 17. Can any of the timing updates be avoided?

Yes, there is an update_timing both before and after
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set_propagated_clocks – the one before

set_propagated_clocks is unnecessary. One

update_timing command is in pt.tcl – the other is in a
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constraint file (orca_pt_other.tcl) sourced by

orca_pt_constraints which is sourced by pt.tcl
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Question 18. Why might the quit command output be a good place to
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start before reviewing your log file?

It gives a high-level summary of potential trouble spots:
messages, both warning and information, timing updates,
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and performance statistics.

Question 19. How many clocks are in ORCA?

There are 6 clocks in ORCA.

Question 20. There are at least 4 clues that this report is for setup and
not for hold. How many can you identify?
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The most glaring clue is the “library setup time” in the

generated report. The more subtle clues are:

The clock edges used for the data arrival and data
required are 0ns and 8ns respectively (and not 0ns and
0ns as for hold time).

Lab 1-14 PrimeTime Flow

The “Path Type” in the header is max which indicates

that this report is for setup (a “Path Type” of min
indicates a hold report).
Finally, the data arrival time is after the data required
time and the slack is violated (whereas if this was a

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report for hold, the slack would be met!)

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Question 21. Identify the instance names of the start and end point

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flip-flops.

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Startpoint: I_ORCA_TOP/I_BLENDER/s3_op2_reg[18]
(rising edge-triggered flip-flop clocked by SYS_CLK)

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Endpoint: I_ORCA_TOP/I_BLENDER/s4_op2_reg[31]

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(rising edge-triggered flip-flop clocked by SYS_CLK)
Path Group: SYS_CLK
Path Type: max

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Min Clock Paths Derating Factor : 0.900

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Question 22. The clock skew for this timing path is 0.511 ns. Which lines
in the report can you use to calculate this?

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Point Incr Path
-----------------------------------------------------------------

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clock SYS_CLK (rise edge) 0.000 0.000
clock network delay (propagated) 3.247 3.247
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I_ORCA_TOP/I_BLENDER/s3_op2_reg[18]/CP (sdnrb1) 0.000 3.247 r
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I_ORCA_TOP/I_BLENDER/s3_op2_reg[18]/Q (sdnrb1) 0.516 & 3.763 r
...
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I_ORCA_TOP/I_BLENDER/s4_op2_reg[31]/D (sdnrb1) 8.242 & 12.004 f

data arrival time 12.004
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clock SYS_CLK (rise edge) 8.000 8.000

clock network delay (propagated) 2.736 10.736
ps

.....
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Question 23. How does this clock skew affect slack (i.e. does the clock
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skew help or hurt slack)?

The clock skew hurts the slack for setup in this specific
©

timing report. The clock latency to the start point flip-flop

causes the data to arrive 0.511ns later causing a larger
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setup timing violation..

Question 24. How large is the violation in comparison to the clock

period?
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The clock period is 8ns. The violation is 0.987. It is

approximately 12% of the clock period.

PrimeTime Flow Lab 1-15

Primetime Workshop © 2021 Synopsys, Inc.
Lab 1 Answers / Solutions

Question 25. There are at least 4 clues that indicate this is a hold report
and not a setup report. How many can you find?

The most glaring clue is the highlighted “library hold time” in

the report below. The more subtle clues are:

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The clock edges used for the data arrival and data

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required are 0ns and 0ns respectively.

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The “Path Type” in the header is min which indicates
that this report is for hold time.

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Finally, the data arrival time is before the data required

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time and the slack is violated.

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Question 26. How does the clock skew for this hold report affect slack
(i.e. does the clock skew help or hurt slack)?

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From the report, you can see (after applying the clock

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network delay) that the capture clock edge arrives later
than the launch clock edge. This hurts the hold slack,
causing a violation.

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Point Incr Path
-------------------------------------------------------------------
.
clock SYS_CLK (rise edge) 0.000 0.000
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clock network delay (propagated) 2.360 2.360
I_ORCA_TOP/I_PARSER/out_bus_reg[10]/CP (sdcrq1) 0.000 2.360 r
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I_ORCA_TOP/I_PARSER/out_bus_reg[10]/Q (sdcrq1) 0.353 & 2.713 r

...
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I_ORCA_TOP/I_BLENDER/rem_green_reg/D (sdcrn1) 0.142 & 2.855 f

data arrival time 2.855
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clock SYS_CLK (rise edge) 0.000 0.000

clock network delay (propagated) 3.206 3.206
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clock reconvergence pessimism -0.216 2.990

I_ORCA_TOP/I_BLENDER/rem_green_reg/CP (sdcrn1) 2.990 r
library hold time 0.006 2.997
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data required time 2.997

-------------------------------------------------------------------
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data required time 2.997

data arrival time -2.855
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--------------------------------------------------------------------
slack (VIOLATED) -0.142
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Lab 1-16 PrimeTime Flow

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2

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Constraining

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Methodology

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Learning Objectives
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After completing this lab, you should be able to:
Validate constraints by checking for
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Constraint Completeness and

Untested timing checks

Identify and interpret constraints in a timing report

Clock constraints
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Interface constraints
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©
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Lab Duration:
30 minutes

Constraining Methodology Lab 2-1

Synopsys 10-I-034-SLG-017
Lab 2

Overview

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Restore session and Validate

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Constraints

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Interpret constraints in a timing
report from an input port.

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Interpret constraints in a timing
report to an output port.

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Relevant Files and Directories

All files for this lab are located in the lab2_constraints directory under your
home directory.
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lab2_constraints/ Current working directory

orca_savesession/ Session to restore for labs

.synopsys_pt.setup PT setup file
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RUN.tcl Run script for orca_savesession

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Answers & Solutions

This lab guide contains answers and solutions to all questions. If you need some
op

help with answering a question or would like to confirm your results, check the back
portion of this lab.
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Lab 2-2 Constraining Methodology

Instructions

Task 1. Validate constraints

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Invoke PrimeTime from the lab2_constraints directory and restore the
PrimeTime session using the orca_savesession directory.

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Note: The orca_savesession can be recreated, if needed,

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using: pt_shell -f RUN.tcl | tee -i run.log

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Note: Any PARA-124 Errors during the execution of RUN.tcl can

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be safely ignored for the purpose of our labs.

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Check for constraint completeness

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pt_shell> check_timing -verbose

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Question 1. Are all registers in the design clocked?

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…………. ...............................................................................
.
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Question 2. Are there any missing constraints? Can you explain?

...............................................................................................
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Check for the untested timing checks in the design

pt_shell> report_analysis_coverage
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Question 3. Nearly two thirds of the setup/hold checks are untested! –

What are the 2 causes?
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...............................................................................................
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Question 4. Why are there unexercised min_pulse_width checks?

...............................................................................................
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Question 5. How many output delay constraints are there for setup and
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for hold and are these constraints met or violated?

...............................................................................................
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Constraining Methodology Lab 2-3

Primetime Workshop © 2021 Synopsys, Inc.
Lab 2

Task 2. Analyze a Timing Report For Input Delay

Constraint
Generate a report for the input delay constraints applied to the port pad[0].

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pt_shell> report_port –input_delay pad[0]

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Question 6. What are the min and max arrival times to pad[0]?

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...............................................................................................

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Question 7. What is the name of the external start point clock
constraining pad[0]?

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...............................................................................................

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Generate a timing report for setup starting at the port pad[0].

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Answer the following questions using this report.

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Use your job aid labeled “timing reports” for help recalling the
appropriate switch for report_timing.
.
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Question 8. Which lines in the timing report did you use to ensure the
reported path starts at the port pad[0] and is for setup?
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...............................................................................................
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Question 9. List all user specified constraints in this timing report.

...............................................................................................
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Question 10. Where must the clock latency be included for the start point
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clock PCI_CLK?

...............................................................................................
©
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Question 11. Describe the direction of the port pad[0] (i.e. is it an input,
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output or inout port).

...............................................................................................
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Question 12. Describe the end point of this timing path (i.e. is it an output
port or an internal flip-flop).
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...............................................................................................

Lab 2-4 Constraining Methodology

Generate a new report from the same port pad[0] for setup, which also
shows the details of the calculated clock network delay.
Use the job aid labeled “timing reports” for help recalling the
appropriate switch for report_timing. Remember to take
advantage of history commands.

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Question 13. How large is the clock source latency versus the clock
network latency for the end point clock PCI_CLK?

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...............................................................................................

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Question 14. Where has the clock PCI_CLK been defined (the clock

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definition point)?

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...............................................................................................

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Generate a report starting at the port pad[0] for hold time.
Question 15. Does the value of the input external delay constraint match

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your expectations?

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...............................................................................................
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©
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Constraining Methodology Lab 2-5

Primetime Workshop © 2021 Synopsys, Inc.
Lab 2

Task 3. Analyze a Timing Report For Output Delay

Constraint
Generate a report for the output delay constraints applied to the port
pad[0].

e
ut
Question 16. What are the min and max output delay constraints for this
port?

ib
...............................................................................................

tr
is
Question 17. How will the negative min output delay constraint be applied
to this port (i.e. will it impose a positive or negative hold

ed
requirement)?

tr
...............................................................................................

no
Question 18. What is the name of the external end point clock constraining
this port?

o
...............................................................................................

D
Generate a “short” timing report ending at the port pad[0] for hold time.
.
nc
Question 19. Describe the start point of this timing path (i.e. is it an input
port or an internal flip-flop).
,I

...............................................................................................
ys

Question 20. Does the path group for this timing path match your
ps

expectations?
no

...............................................................................................

Question 21. Does the “data required time” match your expectations?
Sy

...............................................................................................
©

Optionally, apply the following constraint which will impose a positive output
delay constraint for hold on pad[0] and then re-execute the steps in this
ht

task to see the affect.

pt_shell> set_output_delay –min 1.0 –clock PCI_CLK

pad[0]
op

Quit PrimeTime.
C

This completes Lab2. Return to lecture.

Lab 2-6 Constraining Methodology

Answers / Solutions

Question 1. Are all registers in the design clocked?

e
Yes. There are no clock pins reported following the

ut
message Information: Checking 'no_clock'.

ib
Question 2. Are there any missing constraints? Can you explain?

tr
Yes. There are 2 output ports reported to be missing their

is
output delays.
Warning: There are 2 endpoints which are not constrained for

ed
maximum delay.

tr
sd_CKn

no
sd_CK

The above warning can be ignored since these 2 are the

o
clock output ports (Use the report_clock command to

D
confirm) that should not be constrained for output delay.
Question 3. Nearly two thirds of the setup/hold checks are untested! –
.
What are the 2 causes?
nc

constant_disabled and false_path. (Using

report_analysis_coverage -status
ys

untested -check “setup hold”)

Question 4. Why are there unexercised min_pulse_width checks?
ps

min_pulse_width checks are exercised only if the pins

have clocks. Since these are non clock asynchronous pins

like “set or clear”, no clocks have been defined on them.
Sy

(Use the command report_analysis_coverage -

status untested -check min_pulse_width to
confirm)
©

Question 5. How many output delay constraints are there for setup and
ht

for hold and are these constraints met or violated?

From report_analysis_coverage, there are 75

output delay constraints for both setup and hold; 14 output
yr

delay constraints for setup are violated; 39 output delay

constraints for hold are violated. Remember to verify that all
op

output ports are constrained for both setup as well as for

hold.
C

Constraining Methodology Lab 2-7

Primetime Workshop © 2021 Synopsys, Inc.
Lab 2 Answers / Solutions

pt_shell> restore_session orca_savesession

pt_shell> report_analysis_coverage

e
ut
ib
tr
is
ed
tr
Question 6. What are the min and max arrival times to pad[0]?

no
The min and max arrival times are 2ns and 8ns respectively
(with the same constraint for both rise and fall data

o
transitions at the port pad[0]).
Question 7.
D
What is the name of the external start point clock
constraining pad[0]?
.
nc

The name of the clock is PCI_CLK.

,I
ys

Question 8. Which lines in the timing report did you use to ensure the
reported path starts at the port pad[0] and is for setup?
ps

pt_shell> report_timing –from pad[0]

Startpoint: pad[0] (input port clocked by PCI_CLK)

Endpoint: I_ORCA_TOP/I_PCI_CORE/d_out_i_bus_reg[0]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Sy

Path Group: PCI_CLK

Path Type: max
©

Question 9. List all user specified constraints involved in this timing

report.
ig

The clock period is a constraint. The clock PCI_CLK is

propagated (not ideal). The input external delay (which
yr

comes from an input delay constraint).

op
C

Lab 2-8 Constraining Methodology

Question 10. Where must the clock latency be included for the start point
clock PCI_CLK?

The clock network delay is zero. Therefore, the only other

place to represent the external clock latency is as a part of

e
the input delay constraint (i.e. the input external delay).

ut
The appropriate way to model this is to use the switches
–network_latency_included and

ib
–source_latency_included for
set_input_delay.

tr
is
Question 11. Describe the direction of the port pad[0] (i.e. is it an input,
output or inout port).

ed
The port pad[0] is an inout port; therefore, it is both a

tr
timing path start point as well as a timing path end point!
Point Incr Path

no
-----------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.000 0.000
clock network delay (propagated) 0.000 0.000

o
input external delay 8.000 8.000 r

D
pad[0] (inout) 0.000 8.000 r
Question 12. Describe the end point of this timing path (i.e. is it an output
.
port or an internal flip-flop).
nc

The end point is a rising-edge triggered flip-flop clocked by

PCI_CLK (it is actually a timing model that looks like a flip-

flop with setup and hold timing checks).

ps
no
Sy
©
ht
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op
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Constraining Methodology Lab 2-9

Primetime Workshop © 2021 Synopsys, Inc.
Lab 2 Answers / Solutions

Question 13. How large is the clock source latency versus the clock
network latency for the end point clock PCI_CLK?

Shown below is only the data required time section of the

timing report. The source latency is 0ns. The clock

e
network latency is 2.951ns (17.951 – 15.00).

ut
pt_shell> !rep –path full_clock

ib
tr
is
ed
tr
no
o
D
.
nc
,I
ys
ps
no
Sy
©
ht
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op
C

Lab 2-10 Constraining Methodology

Question 14. Where has the clock PCI_CLK been defined (the clock
definition point)?

The clock PCI_CLK is defined at the input port pclk. The

clock definition point separates the clock source latency

e
from the clock network latency.

ut
ib
Question 15. Does the value of the input external delay constraint match

tr
your expectations?

is
Yes. From report_port above, the input external delay

ed
should be 2ns with respect to the rising edge of PCI_CLK.
This is confirmed in the timing report below.

tr
no
pt_shell> report_timing -delay min -from pad[0]

o
Startpoint: pad[0] (input port clocked by PCI_CLK)

D
Endpoint: I_ORCA_TOP/I_PCI_CORE/d_out_i_bus_reg[0]
(rising edge-triggered flip-flop clocked by PCI_CLK)
Path Group: PCI_CLK
.
Path Type: min
nc
Min Data Paths Derating Factor : 0.900
Min Clock Paths Derating Factor : 0.900
,I

Point Incr Path

-------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.000 0.000
ps

clock network delay (propagated) 0.000 0.000

input external delay 2.000 2.000 r
pad[0] (inout) 0.000 2.000 r
no

pad_iopad_0/PAD (pc3b03) 0.044 2.044 r

pad_iopad_0/CIN (pc3b03) 0.662 & 2.706 r
Sy
©
ht
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op
C

Constraining Methodology Lab 2-11

Primetime Workshop © 2021 Synopsys, Inc.
Lab 2 Answers / Solutions

Question 16. What are the min/max output delay constraints for this port?

pt_shell> report_port –help

Usage:
report_port # Report port info

e
[-verbose] (Show all port info)

ut
[-design_rule] (Only port design rule info)
[-drive] (Only port drive info)

ib
[-input_delay] (Only port input delay info)
[-output_delay] (Only port output delay info)

tr
[-wire_load] (Only port wire load info)
[-nosplit] (Don't split lines if column overflows)

is
[port_list] (List of ports)

ed
pt_shell> report_port –output_delay pad[0]
Output Delay

tr
Min Max Related Related
Output Port Rise Fall Rise Fall Clock Pin

no
------------------------------------------------------------
pad[0] -1.00 -1.00 4.00 4.00 PCI_CLK --

o
D
Question 17. How will the negative min output delay constraint be
applied to this port (i.e. will it impose a positive or negative
hold requirement)?
.
nc

In lecture, it was stated that a negative hold output delay

constraint will impose a positive hold requirement.
,I

Question 18. What is the name of the external end point clock
ys

constraining this port?

The port pad[0] is constrained with respect to PCI_CLK.

Question 19. Describe the start point of this timing path.

The start point of the timing path is an internal flip-flop.

pt_shell> report_timing –delay min –to pad[0]

-path_type short
ht
ig

Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_out_buf_reg[0]
(rising edge-triggered flip-flop clocked
yr

by PCI_CLK)
op

Endpoint: pad[0] (output port clocked by PCI_CLK)

Lab 2-12 Constraining Methodology

Question 20. Does the path group for this timing path match your
expectations?

Yes. The path group is PCI_CLK which is the same as the

external capture clock name.

e
Question 21. Does the “data required time” match your expectations?

ut
Yes. The capture clock edge is zero, which is appropriate

ib
for hold. The hold requirement of 1ns is positive, and the

tr
propagated clock network delay is 0ns. The data required
section of the timing report is shown below.

is
ed
tr
no
o
D
.
nc
,I
ys
ps
no
Sy
©
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Constraining Methodology Lab 2-13

Primetime Workshop © 2021 Synopsys, Inc.
Lab 2 Answers / Solutions

# Answers for optional step

pt_shell> report_port -output_delay pad[0]
. . .

e
ut
ib
tr
is
ed
pt_shell> report_timing –to pad[0] –delay min –path short
. . .

tr
no
o
D
.
nc
,I
ys
ps
no
Sy
©
ht
ig
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op
C

#From the above report, you can see that using a positive hold constraint
#for an output delay INCREASES the positive slack. This confirms that
#specifying a negative hold constraint for an output delay actually
#specifies the hold requirement on the output port.

Lab 2-14 Constraining Methodology

e
ut
3

ib
Generating Reports

tr
is
ed
tr
no
o
Learning Objectives
D
.
nc
After completing this lab, you should be able to:
Generate summary reports for the violations in
,I

ORCA
ys

Analyze timing reports for setup and hold

Apply the correct timing report switches
ps

Identify half clock cycle paths

no
Sy
©
ht
ig
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op
C

Lab Duration:
45 minutes

Generating Reports Lab 3-1

Synopsys 10-I-034-SLG-017
Lab 3

Overview

e
ut
Restore a PrimeTime

ib
session.

tr
is
ed
Generate various summary
reports.

tr
no
Generate and analyze

o
timing reports.

D
.
nc
,I
ys

Relevant Files and Directories

All files for this lab are located in the lab3_reports directory under your home
directory.
no

lab3_reports/ Current working directory

orca_savesession/ Session to restore for labs

RUN.tcl Run script for orca_savesession
©

.synopsys_pt.setup PT setup file

ht
ig

Answers & Solutions

This lab guide contains answers and solutions to all questions. If you need some
op

help with answering a question or would like to confirm your results, check the back
portion of this lab.
C

Lab 3-2 Generating Reports

Instructions

Task 1. Setup PrimeTime For Lab 3

e
ut
Invoke PrimeTime from the lab3_reports (which is a symbolic link to the
lab2_constraints) workshop lab directory.

ib
Restore the PrimeTime session using the orca_savesession directory.

tr
Note: The orca_savesession can be recreated, if needed,

is
using: pt_shell -f RUN.tcl | tee -i run.log

ed
Note: Any PARA-124 Errors (in parasitics_command.log) during
the execution of RUN.tcl can be safely ignored for the

tr
purpose of our labs.

no
Find the variable that controls the significant digits for many reports and set it
to 4 significant digits. [Hint: aa significant]

o
Question 1. What is this variable’s default value? [Hint: man page]

D
.....................................................................................
.
nc
,I
ys
ps
no
Sy
©
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Generating Reports Lab 3-3

Primetime Workshop © 2021 Synopsys, Inc.
Lab 3

Task 2. Generate Summary Reports

From lab 1, we know that there are setup violations in ORCA.

Answer the following questions by generating the appropriate summary

e
reports:

ut
Question 2. Identify the top five setup violations with the worst

ib
slack. The required details are the endpoint names
and the slack.

tr
is
.....................................................................................

ed
Question 3. List the 2 clock domains that have violating setup
timing paths, and the 5 clock domains that have

tr
violating hold timing paths (ORCA has 6 clock
domains in total).

no
.....................................................................................

o
Question 4. Identify how many hold violations are on input paths,

D
how many on output paths, and how many are
register-to-register violations.
.
nc
.....................................................................................
,I

Generate a report for the worst slack for setup to each bit of a 16-bit bus
ending at the output ports sd_DQ[0] to sd_DQ[15] (the output ports are
ys

all constrained by a single clock, SD_DDR_CLK).

Question 5. List the end point with the largest margin (the best
slack).
no

.....................................................................................
Sy

Generate a high-level overview of the quality of the design

Question 6. Which clock group has the highest number of violating
©

paths?
ht

.....................................................................................
ig
yr
op
C

Lab 3-4 Generating Reports

Task 3. Analyze Timing Reports for Setup and Hold

Turn page mode on.
Execute the following command to generate a timing report for PCI_CLK:

e
ut
pt_shell> report_timing –group PCI_CLK

ib
Question 7. Does this timing path meet or violate timing?

tr
is
.....................................................................................

ed
Question 8. What type of timing path is this - internal flip-flop to
flip-flop, input, or output timing path?

tr
.....................................................................................

no
Generate a timing report for hold time for the same clock group PCI_CLK.

o
pt_shell> report_timing –group PCI_CLK –delay min

Question 9. D
What type of timing path is this - internal flip-flop to
.
nc
flip-flop, input, or output timing path?
,I

.....................................................................................
ys

Question 10. How many cells are on the data path of this timing
path?
ps

.....................................................................................
no

Question 11. The cell delays used are rise delays. Offer one reason
why this would result in a worse slack for hold than
Sy

using fall delays?

.....................................................................................
©

In the next step, you will continue to explore and confirm your
ht

answer for the above question.

Question 12. What additional information do you need to confirm

your answer for the above question?

…. ...........................................................................................
C

Generate another timing report for the same timing path for hold time but with
a fall transition at the end point (instead of a rise transition).
Use copy and paste to avoid mistyping the end point and start
point pin names.

Generating Reports Lab 3-5

Primetime Workshop © 2021 Synopsys, Inc.
Lab 3

Use the job aid labeled “timing reports” to find the appropriate
switches for report_timing.

Question 13. Which lines in this report did you use to confirm that
the correct path has been reported?

e
ut
.....................................................................................

ib
Question 14. Was the guess correct – the faster fall delays results in
a faster data arrival time but a smaller hold time

tr
requirement and thus a better slack?

is
.....................................................................................

ed
tr
no
o
D
.
nc
,I
ys
ps
no
Sy
©
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C

Lab 3-6 Generating Reports

Task 4. Apply the Correct Timing Report Switches

Answer the following questions by experimenting and exploring in PrimeTime.
Use the job aid labeled “timing reports” for help identifying the

e
appropriate commands and switches.

ut
Question 15. Write the command to generate a single timing report

ib
for each path group for setup.

tr
.....................................................................................

is
Question 16. Write the command to generate a single timing report

ed
for setup for each path group which has a violation.

tr
.....................................................................................

no
Question 17. What are the names of the two path groups that have
violating timing paths in ORCA (the answer will come
from the result of the previous question)?

o
D
.....................................................................................

Question 18. Write the command to generate a timing report with

.
nc
the worst slack for setup to any output port constrained
by the clock PCI_CLK.
,I

.....................................................................................
ys

Question 19. There are a few latches in ORCA; write the command
ps

to identify the data pins of these latches.

.....................................................................................

Question 20. Write the command to generate a timing report for hold
Sy

to the D pin of the latched_clk_en_reg latches.

.....................................................................................
ht
ig
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op
C

Generating Reports Lab 3-7

Primetime Workshop © 2021 Synopsys, Inc.
Lab 3

Task 5. Identify Half-Clock Cycle Paths

The clock SDRAM_CLK constrains many half clock cycle paths in ORCA (i.e. it
constrains paths from a falling edge triggered flip-flop to a rising edge triggered flip-
flop and vice versa).

e
ut
These paths must be carefully monitored for various reasons (e.g. the duty cycle of
SDRAM_CLK is not yet well defined or for analysis of the clock skew).

ib
tr
Execute the following command to report the clock period for SDRAM_CLK
and use this information to answer the following questions:

is
ed
pt_shell> report_clock SDRAM_CLK

tr
Question 21. Given that the first number under the waveform

no
column is the first rising edge for the clock
SDRAM_CLK and the second number is the falling
edge – what duty cycle has been defined for this

o
clock?

D
.....................................................................................
.
nc
Question 22. Describe the specific clock edges that will be used in a
timing report for setup for a timing path constrained by
the rising edge of SDRAM_CLK to the falling edge of
,I

SDRAM_CLK.
ys

.....................................................................................
ps

Question 23. For this same timing path, describe the specific clock
no

edges that will be used in a timing report for hold

timing checks.
Sy

.....................................................................................

Confirm the information in the following table by generating the appropriate

timing reports for the half clock cycle timing paths constrained by the clock
ht

SDRAM_CLK.
ig

Worst
Launch Capture Launch Capture Worst Hold
yr

Setup
clock edge clock edge clock edge clock edge Slack
Slack
op

Rise 0ns Fall 3.75ns 0.680ns Rise 7.5ns Fall 3.75ns 3.558ns
C

Fall 3.75ns Rise 7.50ns 0.635ns Fall 3.75ns Rise 0ns 3.514ns

Lab 3-8 Generating Reports

Question 24. Which switch is useful for generating the worst 10

timing reports for each of these half clock cycle timing
paths?

.....................................................................................

e
ut
Question 25. Why does PrimeTime report “no constrained paths?”
(hint – the options PrimeTime is using are shown

ib
immediately following the report_timing
command)

tr
is
.....................................................................................

ed
Question 26. What additional option must you use to report the
worst 10 timing paths?

tr
.....................................................................................

no
Quit PrimeTime.

o
D
.
nc
,I

This completes Lab 3. End of Day-1.

ys
ps
no
Sy
©
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Generating Reports Lab 3-9

Primetime Workshop © 2021 Synopsys, Inc.
Lab 3 Answers / Solutions

Answers / Solutions

Question 1. What is this variable’s default value?

e
ut
set_app_var report_default_significant_digits -
default

ib
report_default_significant_digits = "2"

tr
pt_shell> set report_default_significant_digits 4

is
ed
Question 2. Identify the top five setup violations with the worst slack.
The details that are required are the endpoint names and

tr
the slack.

no
The following command will list all setup violations sorted
by slack. Use page mode to quit from the long report
because the only information desired are the top 5

o
violations.

D
# No need to type the entire command name!
pt_shell> report_analysis –status violated –check setup -nosplit
.
nc
Constrained Related Check
Pin Pin Clock Type Slack
,I

I_ORCA_TOP/I_BLENDER/s4_op2_reg[31]/D CP(rise) SYS_CLK setup -0.9872

I_ORCA_TOP/I_BLENDER/s4_op1_reg[31]/D CP(rise) SYS_CLK setup -0.8410
ys

I_ORCA_TOP/I_BLENDER/s4_op2_reg[30]/D CP(rise) SYS_CLK setup -0.8305

I_ORCA_TOP/I_BLENDER/s4_op1_reg[15]/D CP(rise) SYS_CLK setup -0.6918
ps

I_ORCA_TOP/I_BLENDER/s4_op1_reg[30]/D CP(rise) SYS_CLK setup -0.6843

Question 3. List the 2 clock domains that have violating setup timing
paths, and the 5 clock domains that have violating hold
Sy

timing paths (ORCA has 6 clock domains in total). (the

following answer just shows the path group headers – the
names of the endpoints have been removed to conserve
©

space.
pt_shell> report_constraint –all_violators \
ht

-max_delay -min_delay
ig
yr

max_delay/setup ('PCI_CLK' group)

max_delay/setup ('SYS_CLK' group)
op

min_delay/hold ('PCI_CLK' group)

min_delay/hold ('SDRAM_CLK' group)

min_delay/hold ('SD_DDR_CLK' group)
min_delay/hold ('SYS_2x_CLK' group)
min_delay/hold ('SYS_CLK' group)

Lab 3-10 Generating Reports

Question 4. Identify how many hold violations are on input paths, how
many on output paths, and how many are register-to-
register violations.

pt_shell> report_global_timing

e
ut
Hold violations
------------------------------------------------------

ib
Total reg->reg in->reg reg->out in->out

tr
------------------------------------------------------

is
WNS -2.5189 -0.1420 -2.5189 -0.1281 -0.6657

ed
TNS -71.9799 -3.5616 -58.2729 -0.5954 -9.5499

tr
NUM 121 59 39 7 16

no
------------------------------------------------------

o
Question 5. List the end point with the largest margin (the best slack).

D
The output port sd_DQ[0] has the largest margin at
1.5994ns.
.
nc
Generally, the following command will only generate a single
report for every end point because nworst is, by default, 1 and
,I

there is only a single clock constraining every output port.

However, because increasing the value of max_paths causes an
ys

implicit slack_lesser 0 to be used, and because all the slacks

to this endpoint are positive, PrimeTime will not report any paths
ps

unless we change the value of slack_lesser to a large positive

number – in this case, 100.
no
Sy

pt_shell> report_timing -path end -max 16 -slack_lesser 100 -to sd_DQ*

Endpoint Path Delay Path Required CRP Slack

-----------------------------------------------------------------------------
sd_DQ[6] (inout) 10.4130 f* 11.7192 0.0000 1.3061
ht

sd_DQ[5] (inout) 10.4130 f* 11.7192 0.0000 1.3061

sd_DQ[4] (inout) 10.4130 f* 11.7192 0.0000 1.3061
ig

sd_DQ[3] (inout) 10.4130 f* 11.7192 0.0000 1.3061

sd_DQ[15] (inout) 10.4110 f* 11.7192 0.0000 1.3082
yr

sd_DQ[13] (inout) 10.4110 f* 11.7192 0.0000 1.3082

sd_DQ[14] (inout) 10.4110 f* 11.7192 0.0000 1.3082
op

sd_DQ[12] (inout) 10.4110 f* 11.7192 0.0000 1.3082

sd_DQ[11] (inout) 10.4110 f* 11.7192 0.0000 1.3082
sd_DQ[9] (inout) 10.4110 f* 11.7192 0.0000 1.3082
C

sd_DQ[2] (inout) 10.4055 f* 11.7192 0.0000 1.3137

sd_DQ[1] (inout) 10.4055 f* 11.7192 0.0000 1.3137
sd_DQ[10] (inout) 10.4034 f* 11.7192 0.0000 1.3158
sd_DQ[8] (inout) 10.4034 f* 11.7192 0.0000 1.3158
sd_DQ[7] (inout) 10.4034 f* 11.7192 0.0000 1.3158
sd_DQ[0] (inout) 10.3279 f* 11.7192 0.0000 1.3913

Generating Reports Lab 3-11

Primetime Workshop © 2021 Synopsys, Inc.
Lab 3 Answers / Solutions

Question 6. Which clock group has the highest number of violating

paths?

e
report_qor –only_violated

ut
ib
Timing Path Group 'SDRAM_CLK' (min_delay/hold)
---------------------------------------------

tr
Levels of Logic: 2

is
Critical Path Length: 0.8941

ed
Critical Path Slack: -2.5189

tr
Total Negative Slack: -56.1877

no
No. of Violating Paths: 44

Question 7. Does this timing path meet or violate timing?

o
It violates timing with a slack of -3.6801 ns.
Question 8.
D
What type of timing path is this - internal flip-flop to flip-flop,
input, or output timing path?
.
nc

This is an output timing path ending at the output port

named pad[1].
Question 9. What type of timing path is this - internal flip-flop to flip-flop,
ys

input, or output timing path?

This is an input timing path. The end point looks like a flip-
flop.
no

Question 10. How many cells are on the data path of this timing path?
Sy

There are 2 cells on this data path, the start point

is pad[0] port.
©
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Lab 3-12 Generating Reports

Question 11. The cell delays used are rise delays. Offer one reason why
this would result in a worse slack for hold than using fall
delays?

Typically, fall delays are faster than rise delays and would

e
offer a worse slack for hold! However, it’s the combination

ut
of data arrival time and the amount of hold time that causes
the amount of slack.

ib
Question 12. What additional information do you need to confirm your

tr
answer for the above question?

is
Generate another timing report where the data arrival time

ed
is calculated with fall transition at the end point and
compare the two reports. In this way you can confirm

tr
whether it’s the data arrival time or hold time that
contributed to the worst slack. You will explore this in the

no
next lab step.

o
D
.
nc
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ys
ps
no
Sy
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ht
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Generating Reports Lab 3-13

Primetime Workshop © 2021 Synopsys, Inc.
Lab 3 Answers / Solutions

Question 13. Which lines in this report did you use to confirm that the
correct path has been reported?

Note: The backslash in the command below is a line continuation

character.

e
pt_shell> report_timing -group PCI_CLK -delay_type min_fall \

ut
-input_pins -from pad[0] -to I_ORCA_TOP/I_PCI_CORE/d_out_i_bus_reg[0]/D

ib
tr
Startpoint: pad[0] (input port clocked by PCI_CLK)

is
Endpoint: I_ORCA_TOP/I_PCI_CORE/d_out_i_bus_reg[0]
(rising edge-triggered flip-flop clocked by PCI_CLK)

ed
Path Group: PCI_CLK

tr
Path Type: min
Min Data Paths Derating Factor : 0.9000

no
Min Clock Paths Derating Factor : 0.9000

o
Point Incr Path

D
------------------------------------------------------------------------------
clock PCI_CLK (rise edge) 0.0000 0.0000
.
nc
clock network delay (propagated) 0.0000 0.0000
input external delay 2.0000 2.0000 f
,I

pad[0] (inout) 0.0000 2.0000 f

pad_iopad_0/PAD (pc3b03) 0.0436 2.0436 f

pad_iopad_0/CIN (pc3b03) 0.7329 & 2.7764 f
ps

I_ORCA_TOP/I_PCI_CORE/U24783/C1 (aor211d1) 0.0165 & 2.7929 f

I_ORCA_TOP/I_PCI_CORE/U24783/Z (aor211d1) 0.2481 & 3.0410 f
no

I_ORCA_TOP/I_PCI_CORE/d_out_i_bus_reg[0]/D (sdcrq1) 0.0040 & 3.0450 f

data arrival time 3.0450

clock PCI_CLK (rise edge) 0.0000 0.0000

clock network delay (propagated) 3.6278 3.6278

clock reconvergence pessimism 0.0000 3.6278

I_ORCA_TOP/I_PCI_CORE/d_out_i_bus_reg[0]/CP (sdcrq1) 3.6278 r
ig

library hold time -0.0596 3.5682

data required time 3.5682

------------------------------------------------------------------------------
data required time 3.5682
C

data arrival time -3.0450

------------------------------------------------------------------------------
slack (VIOLATED) -0.5232

Lab 3-14 Generating Reports

Question 14. Was the guess correct – the faster fall delays results in a
faster data arrival time but a smaller hold time requirement
and thus a better slack?

No! The data arrival time is slower with the fall transitions

e
along the path (3.045 ns versus 2.9144ns) and the hold

ut
time requirement is less negative (-0,0596 ns versus -
0.1542 ns). This combination has caused the slack to be

ib
better than the original timing report with rise transitions (-
0.5591 vs -0.5232 ns). Recall that hold time (and

tr
setup time) are a function of the transition at the data pin of

is
the flip-flop.

ed
Question 15. Write the command to generate a single timing report for
each path group for setup.

tr
pt_shell> report_timing –group [get_path_group *]

no
Question 16. Write the command to generate a single timing report for

o
setup for each path group which has a violation.

D
pt_shell> report_timing –group [get_path_group *]
.
–slack_lesser_than 0
nc

# When using PrimeTime interactively – abbreviate

# command names or switches by typing enough letters to

# distinguish from other commands or switches – or,

# better yet, use command expansion by pressing tab
ps

pt_shell> report_timing –slack_less 0

Question 17. What are the names of the two path groups that have
violating timing paths in ORCA (the answer will come from
Sy

the result of the previous question?

The two path groups are PCI_CLK and SYS_CLK.

Question 18. Write the command to generate a timing report with the
ht

worst slack for setup to any output port constrained by the

clock PCI_CLK.
ig
yr

pt_shell> help all_*

pt_shell> all_outputs -help

pt_shell> report_timing –to [all_outputs –clock
C

PCI_CLK]
# Or, another way to do the same thing
pt_shell> report_timing –to [all_outputs] –group
PCI_CLK

Generating Reports Lab 3-15

Primetime Workshop © 2021 Synopsys, Inc.
Lab 3 Answers / Solutions

Question 19. There are a few latches in ORCA; write the command to
identify the data pins of these latches.

pt_shell> all_registers –level_sensitive –data_pins

e
ut
Question 20. Write the command to generate a timing report for hold to
the D pin of the latched_clk_en_reg latches.

ib
tr
# Use copy and paste to avoid mistyping the long end point pin name

is
pt_shell> report_timing –delay min \

ed
-to I_ORCA_TOP/I_BLENDER*/latched_clk_en_reg/D

tr
Question 21. Given that the first number under the waveform column is

no
the first rising edge for the clock SDRAM_CLK and the
second number is the falling edge – what duty cycle has
been defined for this clock?

o
D
The rising edge of SDRAM_CLK is at 0ns, the falling edge
at 3.75ns and the period is 7.50ns. The duty cycle is 50%.
.
Question 22. Describe the specific clock edges that will be used in a
nc
timing report for setup for a timing path constrained by the
rising edge of SDRAM_CLK to the falling edge of
,I

SDRAM_CLK.
ys

Use the following clock waveform for this and the next
question. The clock edges will be 0ns to 3.75ns.
ps
no

Hold Setup
Sy

Hold
0ns 3.75ns 7.5ns
Setup
©

0ns 3.75ns 7.5ns

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0ns 3.75ns 7.5ns

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op

0ns 3.75ns 7.5ns

Lab 3-16 Generating Reports

Question 23. For this same timing path, describe the specific clock edges
that will be used in a timing report for hold timing checks.

The clock edges will be 7.5ns to 3.75ns.

e
ut
# Commands for the final task

ib
# The backslash is a line continuation character

tr
# The switch –delay min_max will generate one report for setup

is
and

ed
# one for hold
report_timing -rise_from [get_clocks SDRAM_CLK] \

tr
-fall_to [get_clocks SDRAM_CLK] -delay_type min_max

no
report_timing -fall_from [get_clocks SDRAM_CLK] \
–rise_to [get_clocks SDRAM_CLK] -delay_type min_max

o
D
Question 24. Which switch is useful for generating the worst 10 timing
reports for each of these half clock cycle timing paths?
.
nc
The switch –max_paths 10 to the above command.
Question 25. Why does PrimeTime report “no constrained paths?”
,I
ys

The –max_paths option implicitly sets another option:

slack_lesser_than 0, which, because slack is positive,
ps

results in no constrained paths.

Question 26. What additional option must you use to report the worst 10
no

timing paths?
Sy

Since there are no violating paths that could be reported in

this case, add the option: slack_less_than 100
©
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Generating Reports Lab 3-17

Primetime Workshop © 2021 Synopsys, Inc.
Lab 3 Answers / Solutions

This page was intentionally left blank.

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no
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.
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ps
no
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Lab 3-18 Generating Reports

e
ut
4

ib
Constraining Multiple

tr
is
Clocks

ed
tr
no
o
Learning Objectives
D
.
nc
After completing this lab, you should be able to:
Apply the commands taught in lecture to gather
,I

information about the design clocks

Use the GUI for another view of the design clocks and
their relationships
ps
no
Sy
©
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Lab Duration:
45 minutes

Constraining Multiple Clocks Lab 4-1

Synopsys 10-I-034-SLG-017
Lab 4

Overview

Get to know the design

e
clocks in the shell.

ut
ib
tr
Get to know the design

is
clocks in the GUI.

ed
tr
Identify a false violation
due to incorrectly

no
constrained clocks.

o
D
Fix the problem and confirm
.
the results.
nc

Relevant Files and Directories

,I
ys

All files for this lab are located in the lab4_clocks directory under your home
directory.
ps

lab4_clocks/ Current working directory

orca_savesession/ Initial Saved ORCA session

orca_savesession_violations/ Saved ORCA session with an
Sy

issue
RUN.tcl Run script for ORCA
©

.synopsys_pt.setup PT setup filef

scripts/
Variable script
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orca_pt_variables.tcl
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Lab 4-2 Constraining Multiple Clocks

Instructions

Task 1. Get to Know the Design Clocks

e
ut
Make sure your current directory is lab4_clocks
Invoke PrimeTime (pt_shell).

ib
Restore the session saved in ./orca_savesession

tr
Take advantage of command and file name completion by typing

is
a few letters and then using the tab key.

ed
Use the commands taught in lecture to answer the following questions.

tr
Use the job aid labeled “Clocks and More” for help recalling the
specific commands.

no
Question 1. How many clocks are in this design and how
many of these are generated?

o
D
...........................................................................

Question 2. Which input ports have defined, master clocks?

.
nc

...........................................................................
,I

Question 3. Which output ports have defined, outgoing

clocks?
ps

...........................................................................
no

Question 4. Are the clocks propagated or ideal?

...........................................................................
Sy

Question 5. Which 3 clock pairs have constrained timing

paths?
©
ht

...........................................................................
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Constraining Multiple Clocks Lab 4-3

Primetime Workshop © 2021 Synopsys, Inc.
Lab 4

Task 2. Use the GUI to Report Clock Relationships

If your design has many clocks, the GUI may simplify the task of understanding
how the clocks are related.

e
Start the GUI by executing the following command.

ut
ib
pt_shell> start_gui

tr
Note: The original pt_shell session is still running in the terminal

is
window. You can keep the GUI open and use either the
shell or the GUI interface as appropriate to the desired

ed
tasks.

tr
Look at clock domain crossings: Open the “clock domain matrix” from the
pull-down menu: Clock Clock Analyzer.

no
The ClockAnalyzer window that opens (expand if needed by clicking on the
plus signs to the left of the clocks) should match the information from

o
check_timing when reporting the clock crossings in the design. Mouse

D
over the blocks in the matrix to see information on what type of false paths
exist. It is sometimes easier to digest this information as a graphical matrix
table in comparison to the text output from
.
nc
check_timing –override clock_crossing –verbose.
The left part of the window lists each master clock and any generated clocks
,I

that are created from each master clock.

Question 6. What is the master clock for SYS_2x_CLK?

...........................................................................
no

...........................................................................

Question 7. SYS_2x_CLK is defined on which pin/port (its

“source”)? (note: you may have to drag the

clock matrix out of the way, exposing more
©

columns of information about the clocks)

...........................................................................
ig

Question 8. The master clock for SYS_2x_CLK is defined

on which pin/port?
yr
op

...........................................................................

Explore in more detail by displaying the clock schematic for SYS_2x_CLK:

select the clock, then right mouse button->Schematic of Selected

Clocks. Expand the fanin for the schematic for the MUX called
I_CLOCK_GEN/U20 [Hint: To locate/highlight U20, use Select -> By Name]
by double-clicking the input stubs, as shown in the following screen captures.

Lab 4-4 Constraining Multiple Clocks

Continue the double clicks until the fanin is exhausted [Example: an input port
has been reached]

e
ut
ib
tr
is
ed
tr
no
o
D
.
nc
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Double-click input pin

stubs
Result of double-clicking input pin
no

stubs
Sy
©
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op

Question 9. What port is connected to the select pin of the

MUX I_CLOCK_GEN/U20?
C

...........................................................................

Constraining Multiple Clocks Lab 4-5

Primetime Workshop © 2021 Synopsys, Inc.
Lab 4

Question 10. Does seeing the schematic give you insight into
the clocking scheme for test?

...........................................................................

e
Explore clock relationships with the abstract clock graph: Close the

ut
schematic window, then, on the TopLevel window, select Clock-> Clock
Graph for All Clocks. If necessary, display a toolbar next to the

ib
schematic by pressing the F8 key. Display various elements by checking the
toolbar and pressing Apply.

tr
Find a pair of muxed clocks: In the Abstract Clock Graph toolbar, select Mux

is
and click Apply.

ed
In the Abstract Clock Graph, find instance I_CLOCK_GEN/U10 of mx02d1.
[Hint: To locate/highlight U10, use Select -> By Name]

tr
Question 11. What clocks drive I_CLOCK_GEN/U10?

no
...........................................................................

o
From the clock graph window, ‘zoom into’ an interesting object by displaying

D
a schematic for it: Select I_CLOCK_GEN/U10, then Schematic
Schematic View. .
Question 12. What port drives the select line to
nc
I_CLOCK_GEN/U10?
,I

...........................................................................
ys

Go back to the Abstract Clock Graph.

Question 13. From the abstract clock graph window, is it

possible to open and display the same clock
schematic for SYS_2x_CLK you displayed in
no

the clock analyzer [Right Click on SYS_2x_CLK

and find the option]?
Sy

...........................................................................
©

Close the Clock Analyzer window by clicking on the small “X” in its upper right
corner.
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Close the Clock Schematic and Clock Analyzer windows by clicking on the
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small “X” in the upper right corner.

yr
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Lab 4-6 Constraining Multiple Clocks

Task 3. Use the GUI to explore detail of timing paths

Investigate paths between launch and capture clocks – in this case, you will look at
network latency for the launch and capture paths clocked by SYS_CLK.

e
Propagate all the clocks to have the clock network delays calculated by

ut
Primetime before examining paths, by executing these commands in the
shell, which remains open behind the GUI (this will take a minute or so to

ib
complete). Tell PrimeTime to save the arrival times for all pins (this is what

tr
you will examine). Then, define a collection of timing paths to examine.

is
set_propagated_clock [all_clocks]

ed
set timing_save_pin_arrival_and_slack true

tr
update_timing
set my_paths [get_timing_paths –max 10 -group

no
SYS_CLK
-path full_clock_expanded]

o
D
Enter your collection of violating paths from the pull-down menu
Timing Path Analyzer.
.
nc
Enter your collection of timing paths and click
Apply
,I
ys
ps
no
Sy

Bring up a histogram of your ten timing paths.

Right mouse
ht

click on ALL and

select Create
ig
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Constraining Multiple Clocks Lab 4-7

Primetime Workshop © 2021 Synopsys, Inc.
Lab 4

From the histogram, bring up the Path Inspector on a selected path.

e
ut
ib
tr
is
ed
tr
1: Select
the set of

no
paths with
the worst
slack by

o
left

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clicking the
leftmost
bar.
.
nc
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ys
ps
no

2: Select the
Sy

worst path,
then click on
©

“Inspector”
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Lab 4-8 Constraining Multiple Clocks

In the Path Inspector, examine clock reconvergent pessimism: In the data

required and data arrival section, scroll down until you find CRP. Then, scroll
across until you find the percent of delay for the CRP.

e
ut
ib
tr
is
ed
tr
no
o
D
.
nc
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ys

Question 14. What percent of the capture delay comes from

CRP?

...........................................................................
no

Question 15. Is this percent representative of all designs?

...........................................................................
©
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Constraining Multiple Clocks Lab 4-9

Primetime Workshop © 2021 Synopsys, Inc.
Lab 4

Look at a schematic of the path by clicking on the Schematic tab on the

bottom of the path inspector window.

e
ut
ib
tr
is
ed
tr
no
In the schematic window, find the CRP (clock reconvergent pessimism) point.
This is the last pin before the launch and capture paths diverge.

o
Note: Mouse “gestures” or “strokes” are available for easier

D
zooming: While pressing the middle mouse button drag the
cursor vertically for ‘zoom full’; Drag diagonally up across
.
an object to zoom in, and down across an object to zoom
nc
out.
,I

To see arrival times on this pin, if necessary, you may have to first ‘expand’
the pin’s buffer. (PrimeTime may ‘collapse’ buffer trees into a single buffer).
ys
ps
no
Sy
©
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Lab 4-10 Constraining Multiple Clocks

View the arrival times (and any other attributes of interest) by selecting the
output pin of the buffer just before the register, then by selecting
View->Property [and by changing the list from being the default “Basic” to the
“Application”]

e
Question 16. How wide is the arrival window for thee buffer

ut
output pin?

ib
...........................................................................

tr
is
Question 17. Does this match what we saw earlier in the data
arrival data required section of the path

ed
inspector?

tr
...........................................................................

no
Examine the path waveform: Click on the Waveform tab at the bottom of the
Path Inspector window.
Question 18. What can you add to the wavforms by clicking

o
the right mouse button in the waveform

D
window?
.
...........................................................................
nc

Close the GUI while keeping the original pt_shell session going in the
,I

terminal window:
ys

File Close GUI (in the main GUI window)

Or
no

pt_shell> stop_gui (in the pt_shell window)

Exit PrimeTime.
©
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Constraining Multiple Clocks Lab 4-11

Primetime Workshop © 2021 Synopsys, Inc.
Lab 4

Task 4. Report a False Violation

Bring up PrimeTime and restore the saved session
orca_savesession_violations

e
Determine the number and type of timing violations in ORCA:

ut
report_analysis_coverage

ib
tr
Question 19. How many, and what kind of violations does
ORCA have?

is
ed
...........................................................................

tr
Generate a “short” timing report for the worst slack for an out_setup timing
check.

no
Question 20. How will you identify the endpoint port which
has the worst slack for out_setup (use the job
aid labeled “Timing Reports” for help recalling

o
the two appropriate switches)?

D
...........................................................................
.
nc
Question 21. Which clocks (launch and capture) are involved
in this violation?
,I

...........................................................................
ys

From task 1, you know that SD_DDR_CLK is a generated clock

defined at an output port. The purpose of defining outgoing

clocks is that PrimeTime calculates source latency for this clock
no

and include this latency as part of the data required time.

Look at the data required time section of the timing report from the last step
and notice that no clock latency is reported.
Confirm this with the following command:
©
ht

# This report will return nothing as PrimeTime has

not
ig

# calculated source latency for SD_DDR_CLK

pt_shell> report_clock –skew SD_DDR_CLK

Question 22. Why has PrimeTime not calculated source

latency for the outgoing clock SD_DDR_CLK?

...........................................................................

Lab 4-12 Constraining Multiple Clocks

After speaking with the designer, it turns out there was a

miscommunication. The designer was expecting you to turn on
a variable that will propagate all clocks!

e
ut
There is a variable that can be used to make all clocks propagated. Use the
Tcl procedure aa to help you identify the appropriate variable:

ib
aa propagate

tr
is
Question 23. What is the name of this variable?

ed
...........................................................................

tr
Question 24. Using a man page, explain what this variable

no
will do?

...........................................................................

o
D
Use the man page for check_timing to find the name of the additional
check that will flag all ideal clocks.
.
The following command opens the man page in a pop-up window with a scroll
nc
bar that simplifies viewing long reports.
,I

pt_shell> vman check_timing

The above command is an alias created in the

.synopsys_pt.setup file. It uses a command called view that is

available on SolvNet, Doc Id 014947.
no

The alias vman will not work if the “wish” executable, the main
Sy

executable in the Tk package, is not installed and made available

in your lab environment
©

Question 25. How will you modify check_timing to add a

check to validate that all clocks are propagated?
ht

...........................................................................
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Quit PrimeTime.
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Constraining Multiple Clocks Lab 4-13

Primetime Workshop © 2021 Synopsys, Inc.
Lab 4

Task 5. Re-Execute the Run Script to reduce violation

You are provided with the file ./scripts/orca_pt_variables.tcl that
will accomplish the following two things.

e
Adds to the default checks performed by check_timing the check that

ut
will flag ideal clocks.

ib
All created clocks will be created as propagated clocks.
Execute the run script ./RUN.tcl from the lab4_clocks Unix directory

tr
is
Log the results to the log file run.log.

ed
unix> pt_shell –f ./RUN.tcl | tee –i run.log

tr
Invoke PrimeTime and restore the newly saved session in the Unix directory

no
./orca _savesession
Use the appropriate commands to confirm the information below:

o
The out_setup violations have been reduced.
All clocks are propagated.
D
.
Execute check_timing to confirm it is performing its default checks in
nc
addition to the check for ideal clocks.
,I

The source latency is now calculated for SD_DDR_CLK.

The timing report to sd_DQ[3] includes this calculated source latency.

There will be additional violations (more setup violations as well
ps

as out_hold violations) that you can ignore.

Quit PrimeTime.
Sy

This completes lab 4. Return to lecture.

Lab 4-14 Constraining Multiple Clocks

Answers / Solutions

Question 1. How many clocks are in this design and how many of these
are generated?

e
ut
This information can be gathered from report_clock, or
using the following commands.

ib
tr
pt_shell> sizeof_collection [all_clocks]

is
6

ed
pt_shell> sizeof_collection [get_generated_clocks *]
3

tr
no
Question 2. Which input ports have defined, master clocks?

o
pt_shell> rpt_clock_ports

D
Port Name Direction Clock Name Is Generated
-------------------------------------------------------
.
nc
pclk in PCI_CLK false
sys_clk in SYS_CLK false
,I

sdr_clk in SDRAM_CLK false

sd_CK out SD_DDR_CLK true
ys

sd_CKn out SD_DDR_CLKn true

Question 3. Which output ports have defined, outgoing clocks?

From the same report, sd_CK and sd_CKn.

Question 4. Are the clocks propagated or ideal?
Sy

Use report_clock to see that all the design clocks are

propagated.
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Constraining Multiple Clocks Lab 4-15

Primetime Workshop © 2021 Synopsys, Inc.
Lab 4 Answers / Solutions

Question 5. Which 3 clock pairs have constrained timing paths?

pt_shell> check_timing -over clock_crossing -verbose

Information: Checking 'clock_crossing'.

e
Information: There are 4 clocks having domains interacting.

ut
* all paths are false paths

ib
# part of paths are false paths

tr
is
From Clock Crossing Clocks
------------------------------------------------------------

ed
PCI_CLK SYS_CLK*
SDRAM_CLK SD_DDR_CLK#, SYS_CLK*

tr
SYS_2x_CLK SDRAM_CLK*, SYS_CLK
SYS_CLK PCI_CLK*, SDRAM_CLK*, SYS_2x_CLK

no
Question 6. What is the master clock for SYS_2x_CLK?

o
D
SYS_CLK
Question 7. SYS_2x_CLK is defined on which pin/port (its “source”)?
.
nc

I_CLOCK_GEN/I_CLKMUL/CLK_2X (You may have to

drag the window containing the matrix out of the way in
,I

order to see the source pins)

Question 8. The master clock for SYS_2x_CLK is defined on which

pin/port?
ps

sys_clk
no

Question 9. What port is connected to the select pin of the MUX

I_CLOCK_GEN/U20?
Sy

test_mode
©

Question 10. Does seeing the schematic give you insight into the
clocking scheme for test?
ht
ig

Yes – two clocks come into the mux: one from the clock
generator, one directly from the port. The test_mode
yr

port controls the select line, making it possible to bypass

the clock generator during test mode and letting the design
op

be driven directly from the port.

Question 11. What clocks drive I_CLOCK_GEN/U10?

SYS_CLK and SYS_2x_CLK

Lab 4-16 Constraining Multiple Clocks

Question 12. What port drives the select line to I_CLOCK_GEN/U10?

power_save

e
Question 13. From the abstract clock graph window, is it possible to

ut
display the same clock schematic you displayed in the
clock analyzer?

ib
Yes. Select the clock SYS_2x_CLK (you may have to

tr
zoom in to select just the clock), then press right mouse

is
button and select Path Schematic for Selected
Paths. You may have to expand input or output stubs (by

ed
double clicking on them) to get the exact same schematic.

tr
Question 14. What percent of the capture delay comes from CRP?
4.18%

no
Question 15. Is this percent representative of all designs?
No, this number is dependent on the particular design and

o
on the particular path.

Question 16.
D
How wide is the arrival window for the buffer output pin?
.
It is 2.86939 minus 2.40107, or about .468.
nc

Question 17. Does this match what we saw earlier in the data arrival data
,I

required section of the path inspector?

Yes.
ys

Question 18. What can you add to the waveforms by clicking the right
ps

mouse button in the waveform window?

You can add input pins and output pins, allowing you to see
no

the detail for the whole path.

Question 19. How many, and what kind of violations does ORCA have?
Sy

There are 23 setup violations, 53 hold violations, and 32

out_setup violations.
Question 20. How will you identify the endpoint port which has the worst
ht

slack for out_setup?

pt_shell> report_timing -path short -to [all_outputs]

OR
pt_shell> page_on
op

pt_shell> report_analysis_coverage -status violated -check out_setup

Constraining Multiple Clocks Lab 4-17

e
ut
ib
tr
is
ed
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Question 21. Which clocks (launch and capture) are involved in this

no
violation?

pt_shell> report_timing -to sd_DQ[6] -path short

o
D
Startpoint: sdr_clk (clock source 'SDRAM_CLK')
Endpoint: sd_DQ[6] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK
.
nc
Path Type: max
Min Clock Paths Derating Factor : 0.90
,I

Point Incr Path

------------------------------------------------------------
ys

clock SDRAM_CLK (fall edge) 3.75 3.75

clock source latency 0.00 3.75
ps

sdr_clk (in) 0.00 3.75 f

...
no

sd_DQ[6] (inout) 6.66 10.41 f

data arrival time 10.41
Sy

clock SD_DDR_CLK (rise edge) 7.50 7.50

data required time 6.75

------------------------------------------------------------
ht

data required time 6.75

data arrival time -10.41
ig

------------------------------------------------------------
slack (VIOLATED) -3.66
yr

------------------------------------------------------------
slack (VIOLATED) -3.66
op

Question 22. Why has PrimeTime not calculated source latency for the
C

outgoing clock SD_DDR_CLK?

The clocks (specifically the master clock) must be

propagated for PrimeTime to calculate the source latency
for generated clocks. All clocks in this design are ideal.

Lab 4-18 Constraining Multiple Clocks

Question 23. What is the name of this variable?

pt_shell> aa propagate
********* Commands **********

e
ut
remove_propagated_clock # Remove a propagated clock
specification

ib
set_propagated_clock # Specify propagated clock latency

tr
********* Variables **********

is
case_analysis_propagate_through_icg = "false"

ed
timing_all_clocks_propagated = "false"

tr
timing_clock_gating_propagate_enable = "false"
timing_propagate_interclock_uncertainty = "false"

no
timing_propagate_through_non_latch_d_pin_arcs = "false"

o
Question 24. Using a man page, explain what this variable will do?

D
All clocks created after this variable is set to true will be
.
created as propagated clocks.
nc

The clocks will be set to propagated in the next task.

Question 25. How will you modify check_timing to add a check to

validate that all clocks are propagated?

The added check is named ideal_clocks. You can

add this check to the variable

timing_check_defaults using lappend such that
no

it is executed automatically with check_timing.

This will be done in the next task.

# Answers for TASK 5 STEP 1

# Add the following to ./scripts/orca_pt_variables.tcl

lappend timing_check_defaults ideal_clocks

set timing_all_clocks_propagated true

yr
op
C

Constraining Multiple Clocks Lab 4-19

# Answers for Task 5 Step 4

# Out_setup violations should be reduced.
pt_shell> report_analysis_coverage

e
# All clocks should be propagated

ut
pt_shell> report_clock

ib
# The command check_timing does not flag ideal clocks

tr
pt_shell> check_timing
Information: Checking 'no_clock'.

is
Information: Checking 'no_input_delay'.

ed
Information: Checking 'partial_input_delay'.
Information: Checking 'ideal_clocks'.

tr
. . .
# The source latency is being calculated for SD_DDR_CLK

no
pt_shell> report_clock –skew SD_DDR_CLK

# The source latency is applied to the timing report to

o
SD_DQ[3]

D
pt_shell> report_timing -to sd_DQ[3] -path short
.
nc

Startpoint: sdr_clk (clock source 'SDRAM_CLK')

Endpoint: sd_DQ[3] (output port clocked by SD_DDR_CLK)

Path Group: SD_DDR_CLK
ys

Path Type: max

Min Clock Paths Derating Factor : 0.9000
ps

Point Incr Path

--------------------------------------------------------
clock SDRAM_CLK (fall edge) 3.7500 3.7500
Sy

clock source latency 0.0000 3.7500

sd_DQ[6] (inout) 6.6630 10.4130 f

data arrival time 10.4130
ht
ig

clock SD_DDR_CLK (rise edge) 7.5000 7.5000

clock network delay (propagated) 4.9692 12.4692
yr

clock reconvergence pessimism 0.0000 12.4692

output external delay -0.7500 11.7192
op

data required time 11.7192

--------------------------------------------------------
C

data required time 11.7192

data arrival time -10.4130
--------------------------------------------------------
slack (MET) 1.3061

Lab 4-20 Constraining Multiple Clocks

e
ut
5

ib
Additional

tr
is
Constraints

ed
tr
no
o
Learning Objectives
D
.
nc
After completing this lab, you should be able to:
Apply user specified annotated delays to explore time
,I

borrowing with latches

Debug PTE-070 messages regarding non-unate cells

Lab Duration:
30 minutes

Additional Constraints Lab 5-1

Synopsys 10-I-034-SLG-017
Lab 5

Overview

Debug PTE-070 Information

e
ut
Messages.

ib
tr
is
Explore time borrow with
latches.

ed
tr
no
Relevant Files and Directories

o
D
All files for this lab are located in the lab11_specific directory under your home
directory.
.
nc
lab5_additional/ Current working directory
orca_savesession/ Saved session for ORCA
,I

RUN.tcl Script to create orca_savesession

logs/ Log files from run script

.synopsys_pt.setup PT setup file

Lab 5-2 Additional Constraints

Instructions

Task 1. Debug PTE-070 Information Messages

e
ut
Invoke PrimeTime from the lab5_additional Unix directory.
Restore the session saved under ./orca_savesession.

ib
Shown below is the full message regarding a non-unate path on the clock

tr
network.

is
In the next step, you will be asked to generate a timing report through this

ed
pin. In order to copy and paste and avoid typos – either find this message in
the log file from another terminal window or use the Unix command grep

tr
from within PrimeTime as shown below.

no
# From ./logs/run.log
Information: A non-unate path in clock network detected.

o
Propagating both inverting and noninverting senses of clock

D
'SDRAM_CLK' from pin
'I_ORCA_TOP/I_SDRAM_IF/sd_mux_dq_out_0/Z'. (PTE-070)
.
nc
,I

pt_shell> sh grep –A 1 –B 1 PTE-070 logs/run.log

Note: The command sh (or alternatively exec) allows you to

execute Unix commands from within the PrimeTime shell.
ps

Generate a timing report for setup through the above pin and answer the
no

following questions.
The following alias has been created in the PrimeTime setup file
Sy

and will generate a timing report in a pop-up window with a scroll

pt_shell> vrt –through <through pin>

ht
ig

Question 1. Which lines in the timing report did you use to validate it is for
setup and the timing path start point is the source for the
yr

clock SDRAM_CLK?
op

...............................................................................................
C

Additional Constraints Lab 5-3

Question 2. How does this timing report confirm that the pin in the
warning above is on a data path (i.e. a clock source being
used and constrained as a data path) and not on a clock
path?

e
...............................................................................................

ut
Question 3. Which sense is propagated through the above pin (i.e.

ib
positive unate or negative unate)? Look for a small arrow in
the timing report which will locate the specific pin of interest.

tr
is
...............................................................................................

ed
Generate at least one additional timing report to show the use of a negative
unate timing arc through the pin of interest.

tr
Question 4. Which lines in the timing report did you use to validate it is for
setup, the timing path start point is the source for the clock

no
SDRAM_CLK and that the timing arc is negative unate for
the pin of interest?

o
D
...............................................................................................

Question 5. Explain why this warning can be ignored (and suppressed)

.
nc
for these timing paths?

...............................................................................................
,I
ys

Do not quit PrimeTime.

Task 2. Explore Time Borrow and Latches

ps
no

There is only one latch in this design.

Use the following commands to find it:

Take advantage of command and option completion with the tab

key.
©
ht

pt_shell> all_registers –level_sensitive

pt_shell> !! –clock_pin
yr

pt_shell> all_registers –level_sensitive –data_pins

Question 6. What is the name of the clock pin for this latch?
C

...............................................................................................

Question 7. What are the names of the three data pins?

...............................................................................................

Lab 5-4 Additional Constraints

Generate a timing report starting at the latch for setup time (be specific by
using the clock pin as the start point and not just the cell name!).
This lab will refer to this timing report as “path segment #2”.
The function of this latch in the ORCA design is to generate a clock gating

e
signal to turn on and off the clock SYS_CLK.

ut
Question 8. Describe how you know this latch is not experiencing time
borrow from the previous stage?

ib
tr
...............................................................................................

is
Generate a timing report for the previous stage (this lab will refer to this

ed
timing report as “path segment #1”).
Use the D input pin of the latch as the end point of this timing path.

tr
Question 9. How much more time can path segment #1 take before it

no
would start borrowing time from path segment #2?

...............................................................................................

o
Force path segment #1 to borrow time from path segment #2 by annotating a
net delay of 4ns as shown below:
D
.
nc
# Use cut and paste to avoid typos on the pin name
pt_shell> set_annotated_delay -net 4 \
,I

-to
ys

I_ORCA_TOP/I_BLENDER/latched_clk_en_reg/D
ps

Generate the timing report for path segment #1 again (take advantage of the
up and down arrows to scroll through the history event list).
no

Question 10. How much time is path segment #1 borrowing from path
Sy

segment #2?

Question 11. What is the slack for path segment #1?

...............................................................................................
ig
yr
op
C

Additional Constraints Lab 5-5

Re-generate the timing report for path segment #2.

Note: The start point of the timing path will now be the D pin of the
latch (not the clock pin as used before) because you are
interested in reporting the timing path that includes time
borrow.

e
ut
pt_shell> report_timing -from \

ib
tr
I_ORCA_TOP/I_BLENDER/latched_clk_en_reg/D

is
ed
Question 12. Does the time given to path segment #1 now match your
expectations?

tr
...............................................................................................

no
Change the latch behavior for transparency; that is, make it transparent when
data arrives between the opening and closing edges of the clock.

o
D
set_app_var timing_enable_through_paths true
.
Repeat your timing report to the latch D pin. Notice that, even though the
nc
latch is transparent, you can still specify the D pin as an endpoint.
,I

report_timing -to \
ys

"I_ORCA_TOP/I_BLENDER/latched_clk_en_reg/D"
ps

Question 13. What is the startpoint?

. ..............................................................................................
Sy

Do a timing report FROM the startpoint you just identified.

I_ORCA_TOP/I_PARSER/blender_clk_en_reg/CP
ht

Question 14. What is the path endpoint?.

...............................................................................................
yr

Question 15. What are the transparency open and close edges?.
op

...............................................................................................
C

Question 16. Did data arrive between them?.

...............................................................................................

Lab 5-6 Additional Constraints

Question 17. Was there time borrowing?.

...............................................................................................

Question 18. Was slack positive?.

e
ut
...............................................................................................

ib
Quit PrimeTime.

tr
is
This completes Lab 5. Return to lecture.

Additional Constraints Lab 5-7

Answers / Solutions

Question 1. Which lines in the timing report did you use to validate it is
for setup and the timing path start point is the source for the

e
clock SDRAM_CLK?

ut
pt_shell> report_timing –through I_ORCA_TOP/I_SDRAM_IF/sd_mux_dq_out_0/Z

ib
Startpoint: sdr_clk (clock source 'SDRAM_CLK')

tr
Endpoint: sd_DQ[0] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK

is
Path Type: max

ed
Question 2. How does this timing report confirm that the pin in the

tr
warning above is on a data path (i.e. a clock source being
used and constrained as a data path) and not on a clock

no
path?

If no report was generated (“path is unconstrained”), this

o
pin is on a clock path. Because a timing report was

D
generated, this pin is on a data path.
.
nc

Question 3. Which sense is propagated through the above pin (i.e.

positive unate or negative unate)? Look for a small arrow

in the timing report which will locate the specific pin of
ys

interest.
ps

A positive unate timing arc (fall to fall) is reported through

this pin.
no

# Shown are the relevant lines in the data path

I_ORCA_TOP/I_SDRAM_IF/buffd7G5B2I36/Z (buffd7) 0.1634 & 7.1373 f

Lab 5-8 Additional Constraints

Question 4. Which lines in the timing report did you use to validate it is
for setup, the timing path start point is the source for the
clock SDRAM_CLK and that the timing arc is negative unate
for the pin of interest?

e
pt_shell> pt_shell> report_timing \

ut
-rise_through I_ORCA_TOP/I_SDRAM_IF/sd_mux_dq_out_0/Z
Startpoint: sdr_clk (clock source 'SDRAM_CLK')

ib
Endpoint: sd_DQ[0] (output port clocked by SD_DDR_CLK)
Path Group: SD_DDR_CLK

tr
Path Type: max

is
…

ed
I_ORCA_TOP/I_SDRAM_IF/buffd7G5B2I36/Z (buffd7) 0.1634 & 7.1373 f

tr
I_ORCA_TOP/I_SDRAM_IF/sd_mux_dq_out_0/Z (mx02d4) <- 0.4928 & 7.6301 r

no
Question 5. Explain why this message can be ignored for these timing
paths?

o
D
The message indicates that both senses of the clock will be
used when propagating the clock through this mux – this is
the default behavior. However, because the clock is being
.
nc
used as data, PrimeTime actually propagates both senses
(both positive and negative unate), even in older versions of
,I

PrimeTime. This is what is desired and therefore this

information message can be ignored.
ys
ps

Question 6. What is the name of the clock pin for this latch?
no

pt_shell> all_registers –level_sensitive –clock_pins

Additional Constraints Lab 5-9

Question 7. What are the names of the three data pins?

pt_shell> all_registers –level_sensitive –data_pins

{"I_ORCA_TOP/I_BLENDER/latched_clk_en_reg/D",

e
"I_ORCA_TOP/I_BLENDER/latched_clk_en_reg/SC",

ut
"I_ORCA_TOP/I_BLENDER/latched_clk_en_reg/SD"}

ib
tr
# For step 2, generate a timing report for path segment 2

is
pt_shell> report_timing -from
I_ORCA_TOP/I_BLENDER/latched_clk_en_reg/EN

ed
tr
no
Question 8. Describe how you know this latch is not experiencing time
borrow from the previous stage?

o
If this latch were experiencing time borrow, there would be

D
a line in the report stating the amount of time given to the
start point (i.e. to the previous stage). This line is not
present in this timing report.
.
nc

# For step 3, generate a timing report for path segment 1

pt_shell> report_timing -to

I_ORCA_TOP/I_BLENDER/latched_clk_en_reg/D
ps

Question 9. How much more time can path segment #1 take before it
no

would have to start borrowing time from path segment #2?

It can take 3.465ns more before it would start borrowing

Question 10. How much time is path segment #1 borrowing from path
ig

segment #2?
yr

Path segment #1 is borrowing 0.5306ns from path segment

#2. This is noted in the data required time section of the
op

timing report.
C

Lab 5-10 Additional Constraints

Question 11. What is the slack for path segment #1?

The slack is zero. PrimeTime borrows exactly as much as

is needed to make the slack equal zero.

e
ut
Question 12. Does the time given to path segment #1 match your
expectations?

ib
Yes – the time given to start point in the timing report for

tr
path segment #2 will match the time borrowed in the timing

is
report for path segment #1.

ed
pt_shell> report_timing -from I_ORCA_TOP/I_BLENDER/latched_clk_en_reg/D
pt_shell> report_timing -to I_ORCA_TOP/I_BLENDER/latched_clk_en_reg/D

tr
no
Question 13. What is the startpoint?

I_ORCA_TOP/I_PARSER/blender_clk_en_reg/CP

o
D
Question 14. What is the path endpoint?
.
I_ORCA_TOP/I_BLENDER/U794/A (a gating check)
nc

Question 15. What are the transparency open and close edges?
,I

6.6454 and 10.4433

Question 16. Did data arrive between them?

yes – at time 7.1759

Question 17. Was there time borrowing?

no
©

Question 18. Was slack positive?.

yes
ig

The timing report through the transparent latch is on the

next page:
yr
op
C

Additional Constraints Lab 5-11

pt_shell> report_timing -from I_ORCA_TOP/I_PARSER/blender_clk_en_reg/CP

Startpoint: I_ORCA_TOP/I_PARSER/blender_clk_en_reg
(rising edge-triggered flip-flop clocked by SYS_CLK)
Endpoint: I_ORCA_TOP/I_BLENDER/U794
(rising clock gating-check end-point clocked by SYS_CLK)
Last common pin: I_CLK_SOURCE_SYS_CLK/Z

e
Path Group: **clock_gating_default**

ut
Path Type: max
Min Clock Paths Derating Factor : 0.9000

ib
Point Incr Path

tr
------------------------------------------------------------------------
clock SYS_CLK (rise edge) 0.0000 0.0000

is
clock network delay (propagated) 2.7139 2.7139

ed
I_ORCA_TOP/I_PARSER/blender_clk_en_reg/CP (sdcrb1) 0.0000 2.7139 r
I_ORCA_TOP/I_PARSER/blender_clk_en_reg/Q (sdcrb1) 0.4621 & 3.1759 r
I_ORCA_TOP/I_BLENDER/latched_clk_en_reg/D (slnlq1) 4.0000 * 7.1759 r

tr
------------------------------------------------------------------------
transparency window #1

no
clock SYS_CLK (fall edge) 4.0000
clock latency 2.3250 6.3250

o
clock reconvergence pessimism 0.3203 6.6454

D
transparency open edge 6.6454

clock SYS_CLK (rise edge) 8.0000

.
clock latency 2.3596 10.3596
nc
clock reconvergence pessimism 0.3203 10.6800
library setup time -0.2367 10.4433
,I

transparency close edge 10.4433

available borrow at through pin 3.2674

------------------------------------------------------------------------
ps

I_ORCA_TOP/I_BLENDER/latched_clk_en_reg/D (slnlq1) 0.0000 7.1759 r

I_ORCA_TOP/I_BLENDER/latched_clk_en_reg/Q (slnlq1) 0.3164 H 7.4924 r
I_ORCA_TOP/I_BLENDER/U794/B1 (ora21d4) 0.0263 & 7.5186 r
no

data arrival time 7.5186

clock SYS_CLK (rise edge) 8.0000 8.0000

clock network delay (propagated) 1.6425 9.6425
clock reconvergence pessimism 0.2160 9.8585
I_ORCA_TOP/I_BLENDER/U794/A (ora21d4) 9.8585 r
©

clock gating setup time -0.2000 9.6585

data required time 9.6585
ht

------------------------------------------------------------------------
data required time 9.6585
ig

data arrival time -7.5186

------------------------------------------------------------------------
yr

slack (MET) 2.1398

op
C

Lab 5-12 Additional Constraints

e
ut
7

ib
Path-Based Analysis

tr
is
ed
tr
no
o
Learning Objectives
D
.
nc
After completing this lab, you should be able to:
Improve PrimeTime accuracy using
,I

Path mode PBA

Lab Duration:
30 minutes

Path-Based Analysis Lab 7-1

Synopsys 10-I-034-SLG-017
Lab 7

Introduction

Report violating paths

e
ut
ib
Perform interactive PBA on

tr
collection

is
ed
Perform Exhaustive PBA

tr
no
o
D
Relevant Files and Directories
All files for this lab are located in the lab7_pba directory under your home
.
nc
directory.

Lab7_pba/ Current working directory

,I
ys

.synopsys_pt.setup automatically-read PT setup file

orca_savesession Saved session directory

Lab 7-2 Path-Based Analysis

Instructions

Task 1. Report violating paths in the current design

e
ut
In this task, we will report the worst violating slacks calculated during
worst_slew propagation for the design.

ib
tr
Change into the working directory for this lab:

is
unix% cd lab7_pba

ed
tr
Bring up PrimeTime and restore a saved session called
orca_savesession.

no
unix% pt_shell

o
pt_shell> restore_session orca_savesession/

Note:
D
The orca_savesession can be recreated, if needed,
.
using: pt_shell -f RUN.tcl | tee -i run.log
nc

Note: Any PARA-124 Errors during the execution of RUN.tcl can

be safely ignored for the purpose of our labs.

Identify the number of setup violations and identify the worst violating path to
an endpoint.
ps

pt_shell> report_analysis_coverage –check setup \

-status violated
Sy

Question 1. How many setup checks are violated?

Question 2. Identify the size of the worst violating slack and the
ht

endpoint to which it is reported?

.................................................................................
yr
op
C

Path-Based Analysis Lab 7-3

Task 2. Perform path m ode PBA

In this task, we will interactively recalculate the slack for the worst violating
path reported.

e
Determine the worst setup slack violation using PBA mode path

ut
ib
pt_shell> report_timing –to
I_ORCA_TOP/I_BLENDER/s4_op2_reg[31]/D –pba_mode path

tr
OR

is
pt_shell> set path [get_timing_path –to

ed
I_ORCA_TOP/I_BLENDER/s4_op2_reg[31]/D –pba_mode
path]

tr
pt_shell> report_timing $path

no
o
Question 3. How does report_timing indicate that the path

D
is recalculated?.
.................................................................................
nc

Question 4. How much is the worst slack violation after

interactive path-based analysis –pba_mode path ?

.................................................................................
ps

Question 5. Did the PBA slack improve or become worse than

the GBA slack or was there no change to the slack
no

number? Are the results as expected?

.................................................................................

Note: PBA does not change the PrimeTime database, so you

cannot use report_analysis_coverage. In this lab,

you can use either report_timing or
ht

get_timing_paths commands with the

–pba_mode option.
ig
yr
op
C

Lab 7-4 Path-Based Analysis

Task 3. Performing Exhaustive PBA

In this task, we will run the design under exhaustive PBA mode.

Identify the top ten setup violations and the violating endpoints for the clock

e
group “SYS_CLK” design.

ut
ib
pt_shell> redirect –tee GBA.rpt { report_timing \
-path summary -group SYS_CLK -max_paths 10 -nosplit}

tr
is
Next, run the exhaustive PBA on the setup violation reported for the design

ed
and generate a summary report :

tr
pt_shell> redirect –tee PBA.rpt { report_timing \

no
-path summary -group SYS_CLK \
-max_paths 10 -nosplit -pba_mode exhaustive }

o
D
Compare GBA.rpt to PBA.rpt and check :
Question 6. How many violating paths are returned by GBA and
.
by PBA?
nc

.................................................................................
,I
ys

pt_shell> sizeof_collection [get_timing_paths \

–slack_less 0 -group SYS_CLK -max_paths 10]
ps

pt_shell> sizeof_collection [get_timing_paths \

–slack_less 0 -group SYS_CLK -max_paths 10 \

Question 7. What is the value of worst violation after exhaustive

PBA; what is the associated timing path endpoint
ht

name?
ig

.................................................................................
yr

Question 8. Are there any UITE-480 warnings?

.................................................................................
C

Path-Based Analysis Lab 7-5

Task 4. [OPTIONAL Task] Generate GBA vs. PBA

Summary Reports
In this optional task, we will generate the global, qor and constraint reports using
GBA, PBA mode path and PBA mode exhaustive for comparison.

e
ut
redirect -tee GBAsummary.rpt {

ib
report_global_timing

tr
report_qor

is
report_constraint -all_violators

ed
}

tr
no
redirect -tee PBApath.rpt {
report_global_timing - pba_mode path

o
report_qor -pba_mode path

path D
report_constraint -all_violators - pba_mode
.
nc
}
,I
ys

redirect -tee PBAexhaust.rpt {

report_global_timing -pba_mode exhaustive
ps

report_qor -pba_mode exhaustive

report_constraint -all_violators -pba_mode

exhaustive
Sy

}
©
ht

This completes Lab 7. End of Day-2.

ig
yr
op
C

Lab 7-6 Path-Based Analysis

Answers / Solutions

Question 1. How many setup checks are violated?

e
ut
Question 2. Identify the size of the worst violating slack and the
endpoint to which it is reported?

ib
tr
Slack to endpoint
I_ORCA_TOP/I_BLENDER/s4_op2_reg[31]/D: -0.7737

is
ed
Question 3. How does report_timing indicate that the path is
recalculated?

tr
The Path Type is followed by ‘recalculated’. See the
following example:

no
o
D
pt_shell> report_timing -to I_ORCA_TOP/I_BLENDER/s4_op2_reg[31]/D
-pba_mode path
.
****************************************
nc

Report : timing
,I

-path_type full
ys

-delay_type max
ps

-max_paths 1
-pba_mode path
no

****************************************
Sy

(rising edge-triggered flip-flop clocked by

SYS_CLK)
ht

Endpoint: I_ORCA_TOP/I_BLENDER/s4_op2_reg[31]
ig

(rising edge-triggered flip-flop clocked by

SYS_CLK)
op

Path Group: SYS_CLK

Path Type: max (recalculated)
C

Path-Based Analysis Lab 7-7

Question 4. How much is the worst slack after interactive path-based

analysis –pba_mode path?
-0.7711

Question 5. Did the PBA slack improve or become worse than the GBA

e
slack or was there no change to the slack number? Are the

ut
results as expected?

ib
The slack improved as expected.
(Remember that when a path is recalculated, the slack can

tr
only remain the same or improve.)

is
ed
Question 6. How many violating paths are returned by GBA and by
PBA?

tr
By GBA : 9 violating paths

no
By PBA: 8 violating paths

o
D
Question 7. What is the value of worst violation before and after
exhaustive PBA; what is the associated timing path
endpoint name?
.
nc

With PBA :
,I

I_ORCA_TOP/I_BLENDER/s4_op2_reg[31]/D
-0.7737
ys

With PBA:
ps

I_ORCA_TOP/I_BLENDER/s4_op2_reg[31]/D
-0.7711
no

Question 8. Are there any UITE-480 warnings?

No, there are no UITE-480 warnings – PBA exhaustive

Lab 7-8 Path-Based Analysis

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