A B C D E

ZZZ2 JDCIN1 ZZZ1 ZZZ3 ZZZ4 ZZZ5 ZZZ6

PCB DCIN Cable LA-6101P LS-6101P LS-6102P LS-6103P LS-6104P

DAZ@ 45@ M/B FUN/B FP/B LED/B PWR/B
DA2@ DA2@ DA2@ DA2@ DA2@
11/03 Add DC-IN Cable P/N : DC301009N00 12/04 Change PJP1 to JDCIN1
1 1
11/18 Change PCB P/N from DA60000G300 to DA60000G200
02/26 Change LA-6101P P/N from DA60000G200 to DA60000G210
02/26 Add DAZ P/N and other small board P/N
02/26 Change DAZ P/N from DAZ0D9001001 to DAZ0D900101

Compal Confidential
2 NAU00 LA-6101P Schematics Document 2

Intel Arrandale Processor with DDRIII + Ibex Peak-M

SV M/B

2010-03-09 3

Rev : 1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics
Date: Tuesday, March 09, 2010 Sheet 1 of 48
A B C D E
 A B C D E

Compal Confidential
Model Name : NAU00
File Name : LA-6101P
1
Intel Memory Bus (DDRIII)
1

Clock Generator Fan Control Dual Channel 204 Pin DDRIII SO-DIMM x2
Arrandale
IDT: 9LRS3199AKLFT Page 37 SV 1.5V DDRIII 800/1066/1333 BANK 0, 1, 2, 3
SILEGO: SLG8SP587
Processor 6.4G/8.5G/10.6G
133/120/100/96/14.318MHZ to PCH Page 10,11
100M/133M/166M(CFD)
48MHZ to CardReader
Page 12 rPGA988A
Page 4,5,6,7,8,9

HDMI Conn. CRT Conn. LVDS Conn.

Page 24 Page 23 Page 22
FDI x8 DMI x4 USB Conn.x3 CardReader Bluetooth Camera FingerPrint
100MHz 100MHz Port 0,3 (USB) Realtek RTS5138 Port 11 Port 2 UPEK TCS5BB6A2
1GB/s x4 2.7GT/s Port 1 (eSATA) Port 5 Port 9
Page 31 Page 28 Page 35 Page 22 Page 36
2
HDMI Level Shifter 2

ASmedia AM1442T LVDS USB

Page 24
3.3V 48MHz
Intel
CRT HD Audio 3.3V 24MHz
Ibex Peak-M
HDMI SATA Gen1 1.5GT/S ,Gen2 3GT/S 100MHz 3G Card
PCH Port 13
100MHz ABD PCIE Gen1 2.5GT/S PCI-Express X1 FCBGA 1071Pin SPI Page 32
Port Port Port Page 13,14,15,16,17,18,19,20,21

New Card Mini Card LAN(GbE) BIOS ROM HDD SSD e-SATA Conn.
Port 3 WLAN Atheros 8151
Page 37
4MB Port 0 Port 1,5 Port 4
Port 2 Port 1
Page 32 Page 26 LPC Mini card slot
Page 13 Page 25 Page 32 Page 31
3 33MHz 3

HDA Codec
Realtek ALC259
RJ-45 Page 29
Page 27
CPU XDP ENE KB926E0
Page 35 Page 33
Small Board
Int. Speaker
Phone Jack x 2
Int. Digital MIC
RTC Ckt. Power/B Thinklight/B Page 30 Page 30
Page 35 Touch Pad Int.KBD
Page 35 Page 36
LS-6104P LS-6103P

Power On/Off Ckt.

Page 34
EC I/O Buffer EC ROM Function/B FP/B
Page 33 128kB Page 36 LS-6101P LS-6102P
4
DC/DC Interface Ckt. 4

Page 38

Power Ckt. G-Sensor Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title
Page 34 Page 25 Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics
Date: Friday, February 26, 2010 Sheet 2 of 48
A B C D E
 A B C D E

Voltage Rails SIGNAL

STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
VIN Adapter power supply (19V) N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
B+ AC or battery power rail for power circuit. N/A N/A N/A
+CPU_CORE Core voltage for CPU ON ON OFF S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+1.05VS 1.05V switched power rail for PCH ON OFF OFF
+1.1VS_VTT 1.1V switched power rail (1.05 for AUB CPU) ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.5V 1.5V power rail for DDRIII ON ON OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8VS 1.8V switched power rail ON OFF OFF Board ID / SKU ID Table for AD channel
+3VALW 3.3V always on power rail ON ON ON* Vcc 3.3V +/- 5%
+3V 3.3V power rail for PCH ON ON ON Ra/Rc/Re 100K +/- 5%
+3V_LAN 3.3V power rail for LAN ON ON ON* Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VS 3.3V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+5VALW 5V always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+5VS 5V switched power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+5V 5V power rail for PCH ON ON ON 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+VSB VSB always on power rail ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+RTCVCC RTC power ON ON ON 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
7 NC 2.500 V 3.300 V 3.300 V
2 2

BOARD ID Table
Board ID PCB Revision
External PCI Devices * 0 0.1
Device IDSEL# REQ#/GNT# Interrupts 1
2
3
4
5
6
7

EC SM Bus1 address EC SM Bus2 address

3 3
Device Address Device Address
Smart Battery 0001 011X b

Ibex SM Bus address

Device Address

Clock Generator 1101 0010b

(9LRS3199AKLFT, SLG8SP587)
DDR DIMM0 1001 000Xb
DDR DIMM2 1001 010Xb
ISL90727 0101 1100b
ISL90728 0111 1100b

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics1.0
Date: Friday, February 26, 2010 Sheet 3 of 48

A B C D E
 5 4 3 2 1

JCPU1E

JCPU1A R1 AJ13
PEG_IRCOMP RSVD32
PEG_ICOMPI B26 1 2 49.9_0402_1% RSVD33 AJ12
PEG_ICOMPO A26
DMI_PTX_HRX_N0 A24 B27 R2 AP25
DMI_PTX_HRX_N1 DMI_RX#[0] PEG_RCOMPO EXP_RBIAS RSVD1
C23 DMI_RX#[1] PEG_RBIAS A25 1 2 750_0402_1% AL25 RSVD2 RSVD34 AH25
DMI_PTX_HRX_N2 B22 AL24 AK26
DMI_PTX_HRX_N3 DMI_RX#[2] RSVD3 RSVD35
A21 DMI_RX#[3] PEG_RX#[0] K35 AL22 RSVD4
PEG_RX#[1] J34 AJ33 RSVD5 RSVD36 AL26
DMI_PTX_HRX_P0 B24 J33 AG9 AR2
DMI_PTX_HRX_P1 DMI_RX[0] PEG_RX#[2] RSVD6 RSVD_NCTF_37
D23 DMI_RX[1] PEG_RX#[3] G35 M27 RSVD7

DMI
DMI_PTX_HRX_P2 B23 G32 L28 AJ26
DMI_PTX_HRX_P3 DMI_RX[2] PEG_RX#[4] RSVD8 RSVD38
D A22 DMI_RX[3] PEG_RX#[5] F34 J17 SA_DIMM_VREF (CFD Only) RSVD39 AJ27 D
PEG_RX#[6] F31 H17 SB_DIMM_VREF (CFD Only)
DMI_HTX_PRX_N0 D24 D35 G25
DMI_HTX_PRX_N1 DMI_TX#[0] PEG_RX#[7] RSVD11
G24 DMI_TX#[1] PEG_RX#[8] E33 G17 RSVD12
DMI_HTX_PRX_N2 F23 C33 E31 AP1
DMI_HTX_PRX_N3 DMI_TX#[2] PEG_RX#[9] RSVD13 RSVD_NCTF_40
H23 DMI_TX#[3] PEG_RX#[10] D32 E30 RSVD14 RSVD_NCTF_41 AT2
PEG_RX#[11] B32
DMI_HTX_PRX_P0 D25 C31 AT3
DMI_HTX_PRX_P1 DMI_TX[0] PEG_RX#[12] RSVD_NCTF_42
F24 DMI_TX[1] PEG_RX#[13] B28 RSVD_NCTF_43 AR1
DMI_HTX_PRX_P2 E23 B30
DMI_HTX_PRX_P3 DMI_TX[2] PEG_RX#[14]
G23 DMI_TX[3] PEG_RX#[15] A31

PEG_RX[0] J35 RSVD45 AL28

PEG_RX[1] H34 AM30 CFG[0] RSVD46 AL29
PEG_RX[2] H33 AM28 CFG[1] RSVD47 AP30
H_FDI_TXN0 E22 F35 AP31 AP32
H_FDI_TXN1 FDI_TX#[0] PEG_RX[3] CFG[2] RSVD48
D21 FDI_TX#[1] PEG_RX[4] G33 AL32 CFG[3] RSVD49 AL27
H_FDI_TXN2 D19 E34 AL30 AT31
H_FDI_TXN3 FDI_TX#[2] PEG_RX[5] CFG[4] RSVD50
D18 FDI_TX#[3] PEG_RX[6] F32 AM31 CFG[5] RSVD51 AT32
H_FDI_TXN4 G21 D34 AN29 AP33
H_FDI_TXN5 FDI_TX#[4] PEG_RX[7] CFG[6] RSVD52

PCI EXPRESS -- GRAPHICS

E19 FDI_TX#[5] PEG_RX[8] F33 AM32 CFG[7] RSVD53 AR33
H_FDI_TXN6 F21 B33 AK32 AT33
FDI_TX#[6] PEG_RX[9] CFG[8] RSVD_NCTF_54
Intel(R) FDI
H_FDI_TXN7 G18 D31 AK31 AT34

RESERVED
FDI_TX#[7] PEG_RX[10] CFG[9] RSVD_NCTF_55
PEG_RX[11] A32 11/12 Delete R3(@),R4(@),R5(@),R6(@) AK28 CFG[10] RSVD_NCTF_56 AP35
PEG_RX[12] C30 AJ28 CFG[11] RSVD_NCTF_57 AR35
H_FDI_TXP0 D22 A28 AN30 AR32
H_FDI_TXP1 FDI_TX[0] PEG_RX[13] CFG[12] RSVD58
C21 FDI_TX[1] PEG_RX[14] B29 AN32 CFG[13]
H_FDI_TXP2 D20 A30 AJ32
H_FDI_TXP3 FDI_TX[2] PEG_RX[15] CFG[14]
C18 FDI_TX[3] AJ29 CFG[15] RSVD_TP_59 E15
C H_FDI_TXP4 G22 L33 AJ30 F15 C
H_FDI_TXP5 FDI_TX[4] PEG_TX#[0] CFG[16] RSVD_TP_60
E20 FDI_TX[5] PEG_TX#[1] M35 AK30 CFG[17] KEY A2
H_FDI_TXP6 F20 M33 H16 D15 11/17 Delete R7,R8
H_FDI_TXP7 FDI_TX[6] PEG_TX#[2] RSVD_TP_86 RSVD62
G19 FDI_TX[7] PEG_TX#[3] M30 RSVD63 C15
PEG_TX#[4] L31 RSVD64 AJ15
<15> H_FDI_FSYNC0 F17 FDI_FSYNC[0] PEG_TX#[5] K32 RSVD65 AH15
<15> H_FDI_FSYNC1 E17 FDI_FSYNC[1] PEG_TX#[6] M29
PEG_TX#[7] J31 B19 RSVD15
<15> H_FDI_INT C17 FDI_INT PEG_TX#[8] K29 11/17 Delete R9,R10 A19 RSVD16
PEG_TX#[9] H30
<15> H_FDI_LSYNC0 F18 FDI_LSYNC[0] PEG_TX#[10] H29 A20 RSVD17
<15> H_FDI_LSYNC1 D17 FDI_LSYNC[1] PEG_TX#[11] F29 B20 RSVD18
PEG_TX#[12] E28 RSVD_TP_66 AA5
PEG_TX#[13] D29 U9 RSVD19 RSVD_TP_67 AA4
PEG_TX#[14] D27 T9 RSVD20 RSVD_TP_68 R8
PEG_TX#[15] C26 RSVD_TP_69 AD3
AC9 RSVD21 RSVD_TP_70 AD2
PEG_TX[0] L34 AB9 RSVD22 RSVD_TP_71 AA2
PEG_TX[1] M34 RSVD_TP_72 AA1
PEG_TX[2] M32 RSVD_TP_73 R9
PEG_TX[3] L30 RSVD_TP_74 AG7
PEG_TX[4] M31 C1 RSVD_NCTF_23 RSVD_TP_75 AE3
PEG_TX[5] K31 A3 RSVD_NCTF_24
PEG_TX[6] M28
PEG_TX[7] H31 RSVD_TP_76 V4
PEG_TX[8] K28 RSVD_TP_77 V5
PEG_TX[9] G30 RSVD_TP_78 N2
PEG_TX[10] G29 J29 RSVD26 RSVD_TP_79 AD5
PEG_TX[11] F28 J28 RSVD27 RSVD_TP_80 AD7
B B
PEG_TX[12] E27 RSVD_TP_81 W3
PEG_TX[13] D28 A34 RSVD_NCTF_28 RSVD_TP_82 W2
PEG_TX[14] C27 A33 RSVD_NCTF_29 RSVD_TP_83 N3
PEG_TX[15] C25 RSVD_TP_84 AE5
C35 RSVD_NCTF_30 RSVD_TP_85 AD9
B35 RSVD_NCTF_31
IC,AUB_CFD_rPGA,R1P0 AP34
CONN@ VSS

DMI_PTX_HRX_N[0..3] <15>
DMI_PTX_HRX_P[0..3] <15>
IC,AUB_CFD_rPGA,R1P0
DMI_HTX_PRX_N[0..3] <15>
CONN@
DMI_HTX_PRX_P[0..3] <15>

H_FDI_TXN[0..7] <15>
H_FDI_TXP[0..7] <15> CFG0 - PCI-Express Configuration Select CFG4 - Display Port Presence

*1:Single PEG *1:Disabled; No Physical Display Port

0:Bifurcation enabled attached to Embedded Display Port
0:Enabled; An external Display Port
device is connected to the Embedded
Display Port
CFG3 - PCI-Express Static Lane Reversal
*:Default
A
*1 :Normal Operation A
0 :Lane Numbers Reversed
15 -> 0, 14 -> 1, ...

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (1/6) DMI,FDI,PEG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics
Date: Tuesday, March 09, 2010 Sheet 4 of 48
5 4 3 2 1
 5 4 3 2 1

JCPU1B 11/12 Delete R11,R12,R15,R16 (Layout Spacing) Processor CLK

H_COMP3 AT23 COMP3 CLK_CPU_BCLK
BCLK A16 CLK_CPU_BCLK <18>

MISC
H_COMP2 AT24 B16 CLK_CPU_BCLK# Reference Input Input Associated
COMP2 BCLK# CLK_CPU_BCLK# <18>
H_COMP1 CLK_CPU_ITP_R
Clock Frequency PLL

CLOCKS
G16 COMP1 BCLK_ITP AR30 PAD T17 @
AT30 CLK_CPU_ITP#_R PAD T18 @ 10/21 Delete R13,R14, Add T17,T18
H_COMP0 BCLK_ITP#
AT26 COMP0
E16 CLK_CPU_DMI BCLK/BCLK# 133MHz Processor/Memory
PEG_CLK CLK_CPU_DMI <14>
D16 CLK_CPU_DMI#
@ SKTOCC#_R PEG_CLK# CLK_CPU_DMI# <14> /Graphic
T1 PAD AH24 SKTOCC#
A18 CLK_CPU_DP_R R572 1 2 0_0402_5%
DPLL_REF_SSCLK CLK_CPU_DP#_R R573 1
D
DPLL_REF_SSCLK# A17 2 0_0402_5% PEG_CLK/
10/30 Delete Net : CLK_CPU_DP, PCI Express/ D
H_CATERR# AK14 100MHz
CATERR# CLK_CPU_DP# PEG_CLK# DMI/FDI

THERMAL
Delete R17,R18
SM_DRAMRST# F6 SM_DRAMRST# <10>
R19 1 2 H_PECI_R AT15 DPLL_REF_SSCLK/ Embedded
<18> H_PECI 0_0402_5% PECI SM_RCOMP_0
SM_RCOMP[0] AL1 11/05 Delete R21(@) DPLL_REF_SSCLK# 120MHz Displayport
AM1 SM_RCOMP_1 +1.1VS_VTT
SM_RCOMP[1] SM_RCOMP_2
SM_RCOMP[2] AN1
H_PROCHOT# AN26 R25 1 2 10K_0402_5%
<33,47> H_PROCHOT# PROCHOT# PM_EXTTS#0 R27
PM_EXT_TS#[0] AN15 1 2 10K_0402_5%

DDR3
MISC
AP15 PM_EXTTS#1_R R28 1 2 0_0402_5%
PM_EXT_TS#[1] PM_EXTTS#0_1 <10,11>
R29 1 2 H_THERMTRIP#_R AK15
<18> H_THERMTRIP# THERMTRIP# +1.1VS_VTT
0_0402_5%

AT28 XDP_PRDY#
PRDY# XDP_PREQ# XDP_PRDY# R20 @ 51_0402_5%
PREQ# AP27 1 2
XDP_TMS R22 1 @ 2 51_0402_5%
AN28 XDP_TCLK XDP_TDI R23 1 @ 2 51_0402_5%
H_CPURST# TCK XDP_TMS XDP_PREQ# R24 @ 51_0402_5%
AP26 RESET_OBS# TMS AP28 1 2

PWR MANAGEMENT
AT27 XDP_TRST# XDP_TCLK R26 1 @ 2 51_0402_5%
TRST#

JTAG & BPM

R32 1 2 H_PM_SYNC_R AL15 AT29 XDP_TDI
<15> H_PM_SYNC 0_0402_5% PM_SYNC TDI XDP_TDO
TDO AR27
AR29 XDP_TDI_M 11/25 Change R36 from mount to @ (Follow NIWE2)
R34 1 H_CPUPW RGD_1 TDI_M XDP_TDO_M
2 AN14 VCCPWRGOOD_1 TDO_M AP29
0_0402_5% XDP_TRST# R30 1 2 51_0402_5%
AN25 XDP_DBR#_R R36 1 @ 2 0_0402_5% XDP_DBRESET#
DBR# XDP_DBRESET# <15>
C R37 1 2 H_CPUPW RGD_0 AN27 C
<18> H_CPUPW RGD VCCPWRGOOD_0
0_0402_5%
AJ22 XDP_DBR#_R C500 1 2 @ 0.1U_0402_16V4Z
R40 1 PM_DRAM_PW RGD_R BPM#[0]
<15> PM_DRAM_PW RGD 2 AK13 SM_DRAMPWROK BPM#[1] AK22
0_0402_5% AK24
BPM#[2]
BPM#[3] AJ24
R620 1 2 1K_0402_1% VCCP_POK_R AM15 AJ25 ESD Recommend XDP_TDO_M
<45> VCCP_POK VTTPWRGOOD BPM#[4]
BPM#[5] AH22

1
R621 1 2 560_0402_5% AK23
BPM#[6] R35
AM26 TAPPWRGOOD BPM#[7] AH23
10/30 Add R620,R621 (Follow NIWE2) 0_0402_5%

R42 PLT_RST#_R
10/21 Delete Net : XDP_OBS[7:0]
<17,33> PLT_RST# 1 2 AL14

2
1.5K_0402_1% RSTIN# 2009/2/4 XDP_TDI_M
1

Delete dampling resistor for

2009/2/4 R43 power noise and Layout space 10/28 Delete R31,R33(@),R38(@),R39
#414044 DG 750_0402_1% IC,AUB_CFD_rPGA,R1P0 issue
Update Rev1.11 CONN@ Delete Net : XDP_TDI_R,XDP_TDO_R
10/21 Delete R41
2

Delete Net : H_PWRGD_XDP,H_PWRGD_XDP_R

+3VALW

+1.1VS_VTT 10/21 Delete JP1,R52,R56,R57,R59,C1

5

Delete Net : H_CPUPWRGD,H_PWRGOOD_R,

+1.5V_1 2 VCCP_POK
PBTN_OUT#_XDP,CLK_CPU_XDP,CLK_CPU_XDP#
P

B B VCCP_POK <45> B
4 H_CATERR# R46 1 2 49.9_0402_1%
Y H_PROCHOT# R47
A 1 1 2 68_0402_5%
G

H_CPURST# R48 1 @ 2 68_0402_5% Leakage Issue

1

U1 XDP_DBRESET# 1 @ 2 R62 +3VS

3

R44 R45 NC7SZ08P5X_NL_SC70-5 1K_0402_5%

@ H_COMP0 R49 1 2 49.9_0402_1% XDP_TDO 1 2 R63 +1.1VS_VTT
1.1K_0402_1% 1.5K_0402_1% H_COMP1 R50 1 2 49.9_0402_1% 51_0402_5%
Note: When implement S3 power H_COMP2 R51 1 2 20_0402_1%
2

H_COMP3 R55 1 2 20_0402_1% 10/22 Change R62 from mount to @

PM_DRAM_PW RGD_R reduction not to pop,R53,R44 pop 10/30 Change R62 from @ to mount (Follow NCQD0)
U1,R45,R54 SM_RCOMP_0 R58
11/25 Change R62 from mount to @ (Follow NIWE2)
1 2 100_0402_1%
1

11/23 Change R44,R53 from mount to @ SM_RCOMP_1 R60 1 2 24.9_0402_1%

R53 R54 SM_RCOMP_2 R61 1 2 130_0402_1%
@ Change U1,R45,R54 from @ to mount
3K_0402_1% 750_0402_1%
2

11/16 Reserve C530,C531,C532 for avoiding switching noise

11/23 Change C530,C531,C532 from @ to mount

VCCP_POK C530 1 2 100P_0402_50V8J

+5VALW
PM_DRAM_PW RGD_R C531 1 2 100P_0402_50V8J
1

H_CPUPW RGD C532 1 2 100P_0402_50V8J

R574
A
10K_0402_5% A
2

S3_0.75V_EN
S3_0.75V_EN <44>
1

D
VCCP_POK 2
Security Classification Compal Secret Data Compal Electronics, Inc.
G
Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title
Q37 12/04 Change Q37 from SB000008J00 to
S
PROCESSOR (2/6) CLK,JTAG
3

SSM3K7002FU_SC70-3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SB000009610 (Layout Spacing) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics
Date: Tuesday, March 09, 2010 Sheet 5 of 48
5 4 3 2 1
 5 4 3 2 1

JCPU1D
<11> DDR_B_D[0..63]
<11> DDR_B_DM[0..7]
JCPU1C
<10> DDR_A_D[0..63] <11> DDR_B_DQS#[0..7]
<10> DDR_A_DM[0..7] <11> DDR_B_DQS[0..7]
<10> DDR_A_DQS#[0..7] <11> DDR_B_MA[0..15]
<10> DDR_A_DQS[0..7]
<10> DDR_A_MA[0..15] SB_CK[0] W8 DDR_B_CLK0 <11>
SB_CK#[0] W9 DDR_B_CLK0# <11>
AA6 DDR_B_D0 B5 M3
SA_CK[0] DDR_A_CLK0 <10> SB_DQ[0] SB_CKE[0] DDR_B_CKE0 <11>
AA7 DDR_B_D1 A5
SA_CK#[0] DDR_A_CLK0# <10> SB_DQ[1]
P7 DDR_B_D2 C3
SA_CKE[0] DDR_A_CKE0 <10> SB_DQ[2]
DDR_A_D0 A10 DDR_B_D3 B3 V7
SA_DQ[0] SB_DQ[3] SB_CK[1] DDR_B_CLK1 <11>
DDR_A_D1 C10 DDR_B_D4 E4 V6
SA_DQ[1] SB_DQ[4] SB_CK#[1] DDR_B_CLK1# <11>
D DDR_A_D2 C7 DDR_B_D5 A6 M2 D
SA_DQ[2] SB_DQ[5] SB_CKE[1] DDR_B_CKE1 <11>
DDR_A_D3 A7 Y6 DDR_B_D6 A4
SA_DQ[3] SA_CK[1] DDR_A_CLK1 <10> SB_DQ[6]
DDR_A_D4 B10 Y5 DDR_B_D7 C4
SA_DQ[4] SA_CK#[1] DDR_A_CLK1# <10> SB_DQ[7]
DDR_A_D5 D10 P6 DDR_B_D8 D1
SA_DQ[5] SA_CKE[1] DDR_A_CKE1 <10> SB_DQ[8]
DDR_A_D6 E10 DDR_B_D9 D2
DDR_A_D7 SA_DQ[6] DDR_B_D10 SB_DQ[9]
A8 SA_DQ[7] F2 SB_DQ[10] SB_CS#[0] AB8 DDR_B_CS0# <11>
DDR_A_D8 D8 DDR_B_D11 F1 AD6
SA_DQ[8] SB_DQ[11] SB_CS#[1] DDR_B_CS1# <11>
DDR_A_D9 F10 AE2 DDR_B_D12 C2
SA_DQ[9] SA_CS#[0] DDR_A_CS0# <10> SB_DQ[12]
DDR_A_D10 E6 AE8 DDR_B_D13 F5
SA_DQ[10] SA_CS#[1] DDR_A_CS1# <10> SB_DQ[13]
DDR_A_D11 F7 DDR_B_D14 F3
DDR_A_D12 SA_DQ[11] DDR_B_D15 SB_DQ[14]
E9 SA_DQ[12] G4 SB_DQ[15] SB_ODT[0] AC7 DDR_B_ODT0 <11>
DDR_A_D13 B7 DDR_B_D16 H6 AD1
SA_DQ[13] SB_DQ[16] SB_ODT[1] DDR_B_ODT1 <11>
DDR_A_D14 E7 AD8 DDR_B_D17 G2
SA_DQ[14] SA_ODT[0] DDR_A_ODT0 <10> SB_DQ[17]
DDR_A_D15 C6 AF9 DDR_B_D18 J6
SA_DQ[15] SA_ODT[1] DDR_A_ODT1 <10> SB_DQ[18]
DDR_A_D16 H10 DDR_B_D19 J3
DDR_A_D17 SA_DQ[16] DDR_B_D20 SB_DQ[19]
G8 SA_DQ[17] G1 SB_DQ[20]
DDR_A_D18 K7 DDR_B_D21 G5 D4 DDR_B_DM0
DDR_A_D19 SA_DQ[18] DDR_B_D22 SB_DQ[21] SB_DM[0] DDR_B_DM1
J8 SA_DQ[19] J2 SB_DQ[22] SB_DM[1] E1
DDR_A_D20 G7 DDR_B_D23 J1 H3 DDR_B_DM2
DDR_A_D21 SA_DQ[20] DDR_B_D24 SB_DQ[23] SB_DM[2] DDR_B_DM3
G10 SA_DQ[21] J5 SB_DQ[24] SB_DM[3] K1
DDR_A_D22 J7 B9 DDR_A_DM0 DDR_B_D25 K2 AH1 DDR_B_DM4
DDR_A_D23 SA_DQ[22] SA_DM[0] DDR_A_DM1 DDR_B_D26 SB_DQ[25] SB_DM[4] DDR_B_DM5
J10 SA_DQ[23] SA_DM[1] D7 L3 SB_DQ[26] SB_DM[5] AL2
DDR_A_D24 L7 H7 DDR_A_DM2 DDR_B_D27 M1 AR4 DDR_B_DM6
DDR_A_D25 SA_DQ[24] SA_DM[2] DDR_A_DM3 DDR_B_D28 SB_DQ[27] SB_DM[6] DDR_B_DM7
M6 SA_DQ[25] SA_DM[3] M7 K5 SB_DQ[28] SB_DM[7] AT8
DDR_A_D26 M8 AG6 DDR_A_DM4 DDR_B_D29 K4
DDR_A_D27 SA_DQ[26] SA_DM[4] DDR_A_DM5 DDR_B_D30 SB_DQ[29]
L9 SA_DQ[27] SA_DM[5] AM7 M4 SB_DQ[30]
DDR_A_D28 L6 AN10 DDR_A_DM6 DDR_B_D31 N5
DDR_A_D29 SA_DQ[28] SA_DM[6] DDR_A_DM7 DDR_B_D32 SB_DQ[31]
K8 SA_DQ[29] SA_DM[7] AN13 AF3 SB_DQ[32]
DDR_A_D30 N8 DDR_B_D33 AG1
C DDR_A_D31 SA_DQ[30] DDR_B_D34 SB_DQ[33] DDR_B_DQS#0 C
P9 SA_DQ[31] AJ3 SB_DQ[34] SB_DQS#[0] D5
DDR_A_D32 AH5 DDR_B_D35 AK1 F4 DDR_B_DQS#1
DDR_A_D33 SA_DQ[32] DDR_B_D36 SB_DQ[35] SB_DQS#[1] DDR_B_DQS#2
AF5 SA_DQ[33] AG4 SB_DQ[36] SB_DQS#[2] J4
DDR_A_D34 AK6 C9 DDR_A_DQS#0 DDR_B_D37 AG3 L4 DDR_B_DQS#3
SA_DQ[34] SA_DQS#[0] SB_DQ[37] SB_DQS#[3]
DDR SYSTEM MEMORY A

DDR_A_D35 AK7 F8 DDR_A_DQS#1 DDR_B_D38 AJ4 AH2 DDR_B_DQS#4

SA_DQ[35] SA_DQS#[1] SB_DQ[38] SB_DQS#[4]

DDR SYSTEM MEMORY - B

DDR_A_D36 AF6 J9 DDR_A_DQS#2 DDR_B_D39 AH4 AL4 DDR_B_DQS#5
DDR_A_D37 SA_DQ[36] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D40 SB_DQ[39] SB_DQS#[5] DDR_B_DQS#6
AG5 SA_DQ[37] SA_DQS#[3] N9 AK3 SB_DQ[40] SB_DQS#[6] AR5
DDR_A_D38 AJ7 AH7 DDR_A_DQS#4 DDR_B_D41 AK4 AR8 DDR_B_DQS#7
DDR_A_D39 SA_DQ[38] SA_DQS#[4] DDR_A_DQS#5 DDR_B_D42 SB_DQ[41] SB_DQS#[7]
AJ6 SA_DQ[39] SA_DQS#[5] AK9 AM6 SB_DQ[42]
DDR_A_D40 AJ10 AP11 DDR_A_DQS#6 DDR_B_D43 AN2
DDR_A_D41 SA_DQ[40] SA_DQS#[6] DDR_A_DQS#7 DDR_B_D44 SB_DQ[43]
AJ9 SA_DQ[41] SA_DQS#[7] AT13 AK5 SB_DQ[44]
DDR_A_D42 AL10 DDR_B_D45 AK2
DDR_A_D43 SA_DQ[42] DDR_B_D46 SB_DQ[45]
AK12 SA_DQ[43] AM4 SB_DQ[46]
DDR_A_D44 AK8 DDR_B_D47 AM3
DDR_A_D45 SA_DQ[44] DDR_B_D48 SB_DQ[47] DDR_B_DQS0
AL7 SA_DQ[45] AP3 SB_DQ[48] SB_DQS[0] C5
DDR_A_D46 AK11 C8 DDR_A_DQS0 DDR_B_D49 AN5 E3 DDR_B_DQS1
DDR_A_D47 SA_DQ[46] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[1] DDR_B_DQS2
AL8 SA_DQ[47] SA_DQS[1] F9 AT4 SB_DQ[50] SB_DQS[2] H4
DDR_A_D48 AN8 H9 DDR_A_DQS2 DDR_B_D51 AN6 M5 DDR_B_DQS3
DDR_A_D49 SA_DQ[48] SA_DQS[2] DDR_A_DQS3 DDR_B_D52 SB_DQ[51] SB_DQS[3] DDR_B_DQS4
AM10 SA_DQ[49] SA_DQS[3] M9 AN4 SB_DQ[52] SB_DQS[4] AG2
DDR_A_D50 AR11 AH8 DDR_A_DQS4 DDR_B_D53 AN3 AL5 DDR_B_DQS5
DDR_A_D51 SA_DQ[50] SA_DQS[4] DDR_A_DQS5 DDR_B_D54 SB_DQ[53] SB_DQS[5] DDR_B_DQS6
AL11 SA_DQ[51] SA_DQS[5] AK10 AT5 SB_DQ[54] SB_DQS[6] AP5
DDR_A_D52 AM9 AN11 DDR_A_DQS6 DDR_B_D55 AT6 AR7 DDR_B_DQS7
DDR_A_D53 SA_DQ[52] SA_DQS[6] DDR_A_DQS7 DDR_B_D56 SB_DQ[55] SB_DQS[7]
AN9 SA_DQ[53] SA_DQS[7] AR13 AN7 SB_DQ[56]
DDR_A_D54 AT11 DDR_B_D57 AP6
DDR_A_D55 SA_DQ[54] DDR_B_D58 SB_DQ[57]
AP12 SA_DQ[55] AP8 SB_DQ[58]
DDR_A_D56 AM12 DDR_B_D59 AT9
DDR_A_D57 SA_DQ[56] DDR_B_D60 SB_DQ[59]
AN12 SA_DQ[57] AT7 SB_DQ[60]
DDR_A_D58 AM13 Y3 DDR_A_MA0 DDR_B_D61 AP9
DDR_A_D59 SA_DQ[58] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61]
AT14 SA_DQ[59] SA_MA[1] W1 AR10 SB_DQ[62]
B DDR_A_D60 DDR_A_MA2 DDR_B_D63 DDR_B_MA0 B
AT12 SA_DQ[60] SA_MA[2] AA8 AT10 SB_DQ[63] SB_MA[0] U5
DDR_A_D61 AL13 AA3 DDR_A_MA3 V2 DDR_B_MA1
DDR_A_D62 SA_DQ[61] SA_MA[3] DDR_A_MA4 SB_MA[1] DDR_B_MA2
AR14 SA_DQ[62] SA_MA[4] V1 SB_MA[2] T5
DDR_A_D63 AP14 AA9 DDR_A_MA5 V3 DDR_B_MA3
SA_DQ[63] SA_MA[5] DDR_A_MA6 SB_MA[3] DDR_B_MA4
SA_MA[6] V8 SB_MA[4] R1
T1 DDR_A_MA7 DDR_B_BS0 AB1 T8 DDR_B_MA5
SA_MA[7] <11> DDR_B_BS0 SB_BS[0] SB_MA[5]
Y9 DDR_A_MA8 DDR_B_BS1 W5 R2 DDR_B_MA6
SA_MA[8] <11> DDR_B_BS1 SB_BS[1] SB_MA[6]
DDR_A_BS0 AC3 U6 DDR_A_MA9 DDR_B_BS2 R7 R6 DDR_B_MA7
<10> DDR_A_BS0 SA_BS[0] SA_MA[9] <11> DDR_B_BS2 SB_BS[2] SB_MA[7]
DDR_A_BS1 AB2 AD4 DDR_A_MA10 R4 DDR_B_MA8
<10> DDR_A_BS1 SA_BS[1] SA_MA[10] SB_MA[8]
DDR_A_BS2 U7 T2 DDR_A_MA11 R5 DDR_B_MA9
<10> DDR_A_BS2 SA_BS[2] SA_MA[11] SB_MA[9]
U3 DDR_A_MA12 DDR_B_CAS# AC5 AB5 DDR_B_MA10
SA_MA[12] <11> DDR_B_CAS# SB_CAS# SB_MA[10]
AG8 DDR_A_MA13 DDR_B_RAS# Y7 P3 DDR_B_MA11
SA_MA[13] <11> DDR_B_RAS# SB_RAS# SB_MA[11]
T3 DDR_A_MA14 DDR_B_W E# AC6 R3 DDR_B_MA12
SA_MA[14] <11> DDR_B_W E# SB_WE# SB_MA[12]
DDR_A_CAS# AE1 V9 DDR_A_MA15 AF7 DDR_B_MA13
<10> DDR_A_CAS# SA_CAS# SA_MA[15] SB_MA[13]
DDR_A_RAS# AB3 P5 DDR_B_MA14
<10> DDR_A_RAS# SA_RAS# SB_MA[14]
DDR_A_W E# AE9 N1 DDR_B_MA15
<10> DDR_A_W E# SA_WE# SB_MA[15]

IC,AUB_CFD_rPGA,R1P0
CONN@
IC,AUB_CFD_rPGA,R1P0
A
CONN@ A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (3/6) DDRIII
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics 1.0
Date: Tuesday, March 09, 2010 Sheet 6 of 48
5 4 3 2 1
 5 4 3 2 1

JCPU1F

WW15 MOW
+CPU_CORE
Peak 21A +1.1VS_VTT
48A Continuous 18A
10U_0805_6.3V6M
AG35 AH14 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC1 VTT0_1
AG34 VCC2 VTT0_2 AH12
AG33 AH11 +CPU_CORE
VCC3 VTT0_3
AG32 AH10 1 1 1 1 1 1 1
D VCC4 VTT0_4 C2 C3 C4 C5 C6 C7 C8 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M D
AG31 J14
VCC5 VTT0_5
AG30 J13
VCC6 VTT0_6
AG29 VCC7 VTT0_7 H14 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2
AG28 VCC8 VTT0_8 H12
AG27 G14 C9 C10 C11 C12 C13 C14 C15 C16 C17
VCC9 VTT0_9 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AG26 G13
VCC10 VTT0_10 10U_0805_6.3V6M 2 2 2 2 2 2 2 2 2
AF35 VCC11 VTT0_11 G12
AF34 VCC12 VTT0_12 G11
AF33 F14 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC13 VTT0_13
AF32 VCC14 VTT0_14 F13 (Place these capacitors between inductor and socket on Bottom)
AF31 F12
VCC15 VTT0_15 +1.1VS_VTT
AF30 F11
VCC16 VTT0_16 +CPU_CORE
AF29
VCC17 VTT0_17
E14 11/25 Change C18,C19,C20 from SGA00002380
AF28 E12 330U_D2_2.5VY_R9M
VCC18 VTT0_18 (6mohm) to SGA00002680 (9mohm) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AF27 VCC19 VTT0_19 D14 1 1 1
AF26 VCC20 VTT0_20 D13
+ + + 11/25 Change C19 from mount to @

1.1V RAIL POWER

AD35 D12 C18 C19 C20 1 1 1 1 1 1 1
VCC21 VTT0_21 @
AD34
VCC22 VTT0_22
D11 11/30 Change C20 from SGA00002680 (9mohm) to SGA00002U00 (6mohm)
AD33 C14 C21 C22 C23 C24 C25 C26 C27
VCC23 VTT0_23 2 2 2
AD32 VCC24 VTT0_24 C13 11/09 Change R64,R66 from mount to @ (PWR Recommend) 2 2 2 2 2 2 2
AD31 VCC25 VTT0_25 C12
AD30 C11 330U_D2_2.5VY_R9M 330U_D2E_2VM_R6M 11/09 Change R65,R67 from @ to mount (PWR Recommend)
VCC26 VTT0_26 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AD29 VCC27 VTT0_27 B14
AD28
VCC28 VTT0_28
B12 (Place these capacitors under CPU socket, top layer)
AD27 VCC29 VTT0_29 A14
AD26 VCC30 VTT0_30 A13 CSC (Current Sense Configuration)
AC35 VCC31 VTT0_31 A12
+1.1VS_VTT
AC34 VCC32 VTT0_32 A11 11/09 H_VID[6:0] => 0100100
AC33
VCC33 +1.1VS_VTT
AC32
VCC34 H_VID0 R64 @
AC31 VCC35 1 2 1K_0402_1%
AC30 AF10 22U_0805_6.3V6M R65 1 2 1K_0402_1%
C VCC36 VTT0_33 C
AC29 VCC37 VTT0_34 AE10
AC28 AC10 H_VID1 R66 1 @ 2 1K_0402_1% +CPU_CORE
VCC38 VTT0_35 1 1
CPU CORE SUPPLY

AC27 AB10 C28 C29 R67 1 2 1K_0402_1%

VCC39 VTT0_36 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AC26 VCC40 VTT0_37 Y10
AA35 W10 H_VID2 R68 1 2 1K_0402_1%
VCC41 VTT0_38 2 2 R69 @
AA34 VCC42 VTT0_39 U10 1 2 1K_0402_1% 1 1 1 1 1 1
AA33 T10 22U_0805_6.3V6M
VCC43 VTT0_40 H_VID3 R70 @
AA32 J12 1 2 1K_0402_1% C34 C30 C35 C31 C32 C33
VCC44 VTT0_41 R71
AA31 J11 1 2 1K_0402_1%
VCC45 VTT0_42 2 2 2 2 2 2
AA30 VCC46 VTT0_43 J16
AA29 J15 H_VID4 R72 1 @ 2 1K_0402_1%
VCC47 VTT0_44 R73
AA28 1 2 1K_0402_1% 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC48
AA27
VCC49 (Place these capacitors on CPU cavity, Bottom Layer)
AA26 H_VID5 R74 1 2 1K_0402_1%
VCC50 R75 @
Y35 VCC51 1 2 1K_0402_1%
Y34
VCC52 H_VID6 R76 @
Y33 1 2 1K_0402_1%
VCC53 R77 +CPU_CORE
Y32 VCC54 1 2 1K_0402_1%
Y31
VCC55 PROC_DPRSLPVR R78
Y30 VCC56 1 2 1K_0402_1% 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
Y29 R79 1 @ 2 1K_0402_1%
VCC57
Y28 1 1 1 1 1 1
VCC58 PSI# R80 @
Y27 1 2 1K_0402_1%
VCC59 R81
Y26 1 2 1K_0402_1% C36 C37 C38 C39 C40 C41
VCC60
V35 AN33 PSI# <47>
VCC61 PSI# 2 2 2 2 2 2
V34
POWER

VCC62
V33 VCC63
V32 AK35 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC64 VID[0] H_VID0 <47>
V31
VCC65 VID[1]
AK33 H_VID1 <47> 11/17 Reserve C534,C535 for avoiding switching noise (Place these capacitors on CPU cavity, Bottom Layer)
V30
VCC66 VID[2]
AK34 H_VID2 <47> 11/17 Change C534,C535 from @ to mount
V29 AL35 H_VID3 <47>
VCC67 VID[3]
CPU VIDS

V28 VCC68 VID[4] AL33 H_VID4 <47>

B VTT_SELECT C534 1 100P_0402_50V8J B
V27 VCC69 VID[5] AM33 H_VID5 <47> 2
V26 AM35 H_VID6 <47>
VCC70 VID[6] VTT_SENSE C535 1 100P_0402_50V8J
U35 AM34 PROC_DPRSLPVR <47> 2
VCC71 PROC_DPRSLPVR
U34
VCC72
U33 VCC73 Please place C534,C535 close to PU701
U32 VCC74
U31 G15 VTT_SELECT
VCC75 VTT_SELECT VTT_SELECT <45>
U30
VCC76
U29
VCC77 11/09 Change C42~C47 from SGA00002U00 to SGA00001Q80 (PWR Recommend)
U28
VCC78 VTT Rail
U27
VCC79 VTT_SELECT = Low, 1.1V 11/11 Correct C42~C47 footprint
U26
VCC80 VTT_SELECT = High, 1.05V
R35 VCC81 Auburndale +1.1VS_VTT=1.05V
R34
R33
VCC82 Clarksfield +1.1VS_VTT=1.1V +CPU_CORE
VCC83
R32
VCC84 ISENSE
AN35 IMVP_IMON <47> 4 x 330uF(6m ohm@100kHz) SGA00001Q80
R31
VCC85
R30 1 2 +CPU_CORE 1 1 1 1 1 1
VCC86 R82 100_0402_1%
R29
VCC87 C42 + C44 + C45 + C46 + C47 + C43 +
AJ34 VCCSENSE_CPU R83 2 0_0402_5% VCCSENSE
SENSE LINES

R28 1
VCC88 VCC_SENSE VCCSENSE <47>
R27 AJ35 VSSSENSE_CPU R84 1 2 0_0402_5% VSSSENSE @ @
VCC89 VSS_SENSE VSSSENSE <47> 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M
R26
VCC90 2 2 2 2 2 2
P35 VCC91 1 2
P34 B15 R85 100_0402_1%
VCC92 VTT_SENSE VTT_SENSE <45>
P33 A15 VSS_SENSE_VTT
VCC93 VSS_SENSE_VTT R86 @
P32 VCC94 1 2 0_0402_5% TOP side (under inductor)
P31
VCC95
P30
VCC96 11/25 Change R86 from mount to @ (Follow NIWE2)
P29
VCC97 +CPU-CORE C,uF ESR, mohm Stuffing Option
P28
VCC98 Note:CRB has the VTT_SENSE connected through a
P27 "no-stuff" 0- series resistor and VSS_SENSE_VTT
Decoupling
VCC99
A
P26 VCC100 floating.Connect VSS_SENSE_VTT to GND or can be left floating. SPCAP,Polymer 4X330uF 6m ohm/4 2X330uF A

16X22uF 3m ohm/12
MLCC 0805 X5R
16X10uF 3m ohm/16

IC,AUB_CFD_rPGA,R1P0
Security Classification Compal Secret Data Compal Electronics, Inc.
CONN@ Issued Date 2009/10/10 2010/10/10 Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (4/6) PWR,Bypass
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics1.0
Date: Tuesday, March 09, 2010 Sheet 7 of 48
5 4 3 2 1
 5 4 3 2 1

+GFX_CORE
JCPU1G
22U_0805_6.3V6M 10U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M AT21 10/22 Reserve R609,R610 for GFXVR_EN,GFXVR_DPRSLPVR_R
VAXG1
AT19 VAXG2 VAXG_SENSE AR22 VCC_AXG_SENSE <46>

SENSE
LINES
C48
1
C53
1
C54
1
C49
1
C55
1
C50
1
C56
1
C51
1 AT18 VAXG3 VSSAXG_SENSE AT22 VSS_AXG_SENSE <46> 11/02 Change R610 from @ to mount (Follow NIWE2)
AT16 VAXG4
D @ @ @ @ AR21 11/23 Change R610 from SD028470180(4.7kohm) to SD028470080(470ohm) D
VAXG5
AR19 VAXG6
2 2 2 2 2 2 2 2
AR18 (Follow Intel Recommend)
VAXG7
AR16 VAXG8 GFX_VID[0] AM22 GFXVR_VID_0 <46>
AP21 AP22 GFXVR_EN R610 1 2 470_0402_5%
VAXG9 GFX_VID[1] GFXVR_VID_1 <46>

GRAPHICS VIDs
22U_0805_6.3V6M 22U_0805_6.3V6M AP19 AN22 GFXVR_DPRSLPVR_R R609 1 @ 2 10K_0402_5%
VAXG10 GFX_VID[2] GFXVR_VID_2 <46>
22U_0805_6.3V6M 10U_0805_6.3V6M AP18 AP23
VAXG11 GFX_VID[3] GFXVR_VID_3 <46>
AP16 VAXG12 15A GFX_VID[4] AM23 GFXVR_VID_4 <46>
1 1 AN21 VAXG13 GFX_VID[5] AP24 GFXVR_VID_5 <46>

GRAPHICS
AN19 VAXG14 GFX_VID[6] AN24 GFXVR_VID_6 <46>
C52 + + C57 AN18
@ VAXG15
AN16 VAXG16
330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M AM21 AR25 GFXVR_EN
2 2 VAXG17 GFX_VR_EN GFXVR_EN <46>
AM19 AT25 GFXVR_DPRSLPVR_R R87 1 2 0_0402_5% PAD T16 @
VAXG18 GFX_DPRSLPVR
AM18 VAXG19 GFX_IMON AM24 GFXVR_IMON <46>
AM16 VAXG20
AL21 VAXG21
AL19 VAXG22
AL18 +1.5V_1
VAXG23
11/25 Change C52,C57 from SGA00002380 (6mohm) to SGA00002680 (9mohm) AL16 VAXG24 1U_0402_6.3V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M
AK21 VAXG25 VDDQ1 AJ1
AK19 VAXG26 VDDQ2 AF1 1
AK18 AE7

- 1.5V RAILS
VAXG27 VDDQ3 1 1 1 1 1 1 1
AK16 AE4 C58 C59 C60 C61 C62 C63 C64 + C65
VAXG28 VDDQ4 330U_D2_2.5VY_R9M
AJ21 VAXG29 VDDQ5 AC1
AJ19 VAXG30 VDDQ6 AB7
2 2 2 2 2 2 2 2
AJ18 VAXG31 VDDQ7 AB4
AJ16 VAXG32 3A VDDQ8 Y1
AH21 VAXG33 VDDQ9 W7 12/22 Change C65 from

POWER
C AH19 W4 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z C
VAXG34 VDDQ10 22U_0805_6.3V6M SGA20331E10 to
AH18 VAXG35 VDDQ11 U1
AH16 VAXG36 VDDQ12 T7 SGA00002680
VDDQ13 T4
VDDQ14 P1
+1.1VS_VTT N7
VDDQ15
VDDQ16 N4

DDR3
VDDQ17 L1
J24 VTT1_45 VDDQ18 H1

FDI
J23 VTT1_46
1 1 H25 VTT1_47
C66 C67 +1.1VS_VTT

22U_0805_6.3V6M 22U_0805_6.3V6M P10

2 2 VTT0_59
VTT0_60 N10
VTT0_61 L10 1
K10 C68
VTT0_62
+1.1VS_VTT 10U_0805_6.3V6M
2
+1.1VS_VTT

1.1V
VTT1_63 J22
K26 VTT1_48 VTT1_64 J20
J27 VTT1_49 VTT1_65 J18 1

PEG & DMI

1 1 J26 H21 C71
C69 C70 VTT1_50 VTT1_66
J25 VTT1_51 VTT1_67 H20
H27 H19 22U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M VTT1_52 VTT1_68 2
G28 VTT1_53
2 2
G27 VTT1_54
B B
G26 VTT1_55
F26 +1.8VS
VTT1_56 R88
E26 VTT1_57 VCCPLL1 L26

1.8V
E25 0.6A L27 0_0805_5%
VTT1_58 VCCPLL2 +1.8VS_VCCSFR 2.2U_0603_6.3V6K
VCCPLL3 M26 1 2

1 1 1 1 1
C72 C73 C74 C75 C76

1U_0402_6.3V4Z
2 2 2 2 2 22U_0805_6.3V6M

IC,AUB_CFD_rPGA,R1P0 1U_0402_6.3V4Z 4.7U_0603_6.3V6K

CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (5/6) PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics1.0
Date: Tuesday, March 09, 2010 Sheet 8 of 48
5 4 3 2 1
 5 4 3 2 1

JCPU1H JCPU1I

AT20 VSS1 VSS81 AE34 Screw cap. Please place C520~C529 close to H1,H10,H2,H20,H3,H4,H6,H7,H8,H9
AT17 VSS2 VSS82 AE33
AR31 VSS3 VSS83 AE32 K27 VSS161
AR28 VSS4 VSS84 AE31 K9 VSS162 11/17 Change the power of C520,C528 from +3VS to B+
AR26 VSS5 VSS85 AE30 K6 VSS163
AR24 VSS6 VSS86 AE29 K3 VSS164 12/15 Change C520(@),C528(@) from SE070104Z80 to SE042104K80
AR23 VSS7 VSS87 AE28 J32 VSS165
AR20 AE27 J30 +3VALW +3VS B+
VSS8 VSS88 VSS166
AR17 VSS9 VSS89 AE26 J21 VSS167
AR15 VSS10 VSS90 AE6 J19 VSS168
D AR12 VSS11 VSS91 AD10 H35 VSS169 1 D
AR9 AC8 H32 C522 1 1 1
VSS12 VSS92 VSS170 @ C524 C520 C528
AR6 VSS13 VSS93 AC4 H28 VSS171
AR3 AC2 H26 0.1U_0402_16V4Z @ @ @
VSS14 VSS94 VSS172 2 0.1U_0402_16V4Z 0.1U_0603_25V7K 0.1U_0603_25V7K
AP20 VSS15 VSS95 AB35 H24 VSS173 2 2 2
AP17 VSS16 VSS96 AB34 H22 VSS174
AP13 VSS17 VSS97 AB33 H18 VSS175
AP10 VSS18 VSS98 AB32 H15 VSS176
AP7 VSS19 VSS99 AB31 H13 VSS177
AP4 VSS20 VSS100 AB30 H11 VSS178 11/10 Add C520~C529(@) (ESD Recommend)
AP2 VSS21 VSS101 AB29 H8 VSS179
AN34 VSS22 VSS102 AB28 H5 VSS180 11/13 Change C522 power from +3VS to +3VALW
AN31 VSS23 VSS103 AB27 H2 VSS181
AN23 VSS24 VSS104 AB26 G34 VSS182 11/17 Delete C521(@),C523(@)
AN20 VSS25 VSS105 AB6 G31 VSS183
AN17 VSS26 VSS106 AA10 G20 VSS184
AM29 Y8 G9 +3VS
VSS27 VSS107 VSS185
AM27 VSS28 VSS108 Y4 G6 VSS186
AM25 VSS29 VSS109 Y2 G3 VSS187
AM20 VSS30 VSS110 W35 F30 VSS188
AM17 VSS31 VSS111 W34 F27 VSS189 1 1 1 1
AM14 W33 F25 C525 C526 C527 C529
VSS32 VSS112 VSS190 @ @ @ @
AM11 VSS33 VSS113 W32 F22 VSS191
AM8 W31 F19 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VSS34 VSS114 VSS192 2 2 2 2
AM5 VSS35 VSS115 W30 F16 VSS193
AM2 VSS36 VSS116 W29 E35 VSS194
AL34 W28 E32
AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W27
W26
E29
E24
VSS195
VSS196
VSS197
VSS
C AL20 W6 E21 C
VSS40 VSS120 VSS198
AL17 VSS41 VSS121 V10 E18 VSS199
AL12 VSS42 VSS122 U8 E13 VSS200
AL9 VSS43 VSS123 U4 E11 VSS201 11/17 Delete T2,T3,T4,T5
AL6 VSS44 VSS124 U2 E8 VSS202
AL3 VSS45 VSS125 T35 E5 VSS203
AK29 VSS46 VSS126 T34 E2 VSS204 VSS_NCTF1 AT35
AK27 VSS47 VSS127 T33 D33 VSS205 VSS_NCTF2 AT1 12/15 Add C536~C540 (EMI Recommend)
AK25 VSS48 VSS128 T32 D30 VSS206 VSS_NCTF3 AR34
AK20 VSS49 VSS129 T31 D26 VSS207 VSS_NCTF4 B34 12/15 Change C539,C540 from SE070104Z80 to SE042104K80
AK17 T30 D9 B2

NCTF
VSS50 VSS130 VSS208 VSS_NCTF5
AJ31 VSS51 VSS131 T29 D6 VSS209 VSS_NCTF6 B1
AJ23 T28 D3 A35 +3VS B+
VSS52 VSS132 VSS210 VSS_NCTF7
AJ20 VSS53 VSS133 T27 C34 VSS211
AJ17 VSS54 VSS134 T26 C32 VSS212
AJ14 VSS55 VSS135 T6 C29 VSS213
AJ11 VSS56 VSS136 R10 C28 VSS214
AJ8 VSS57 VSS137 P8 C24 VSS215 1 1 1 1 1
AJ5 P4 C22 C536 C537 C538 C539 C540
VSS58 VSS138 VSS216
AJ2 VSS59 VSS139 P2 C20 VSS217
AH35 N35 C19 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0603_25V7K 0.1U_0603_25V7K
VSS60 VSS140 VSS218 2 2 2 2 2
AH34 VSS61 VSS141 N34 C16 VSS219
AH33 VSS62 VSS142 N33 B31 VSS220
AH32 VSS63 VSS143 N32 B25 VSS221
AH31 VSS64 VSS144 N31 B21 VSS222
AH30 VSS65 VSS145 N30 B18 VSS223
AH29 VSS66 VSS146 N29 B17 VSS224
AH28 VSS67 VSS147 N28 B13 VSS225 +5VS
B
AH27 VSS68 VSS148 N27 B11 VSS226 12/15 Add C541~C543 (EMI Recommend) B
AH26 VSS69 VSS149 N26 B8 VSS227
AH20 VSS70 VSS150 N6 B6 VSS228
AH17 VSS71 VSS151 M10 B4 VSS229
AH13 VSS72 VSS152 L35 A29 VSS230
AH9 VSS73 VSS153 L32 A27 VSS231 1 1 1
AH6 L29 A23 C541 C542 C543
VSS74 VSS154 VSS232
AH3 VSS75 VSS155 L8 A9 VSS233
AG10 L5 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VSS76 VSS156 2 2 2
AF8 VSS77 VSS157 L2
AF4 VSS78 VSS158 K34
AF2 VSS79 VSS159 K33
AE35 VSS80 VSS160 K30

IC,AUB_CFD_rPGA,R1P0 IC,AUB_CFD_rPGA,R1P0
CONN@ CONN@
+3VS +R_CRT_VCC B+ B+ +5VS +USB_VCCA

1 1 1 1 1 1 1
C550 C544 C545 C546 C547 C548 C549

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0603_25V7K 0.1U_0603_25V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

2 2 2 2 2 2 2

A A

01/15 Add C544~C549 (EMI Recommend)

01/16 Add C550 (EMI Recommend)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (6/6) VSS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics
Date: Friday, February 26, 2010 Sheet 9 of 48
5 4 3 2 1
 5 4 3 2 1

M1 Circuit +1.5V +1.5V

<6> DDR_A_DQS#[0..7] JDIMM1
+1.5V VREF_DQA 1 2
<6> DDR_A_D[0..63] VREF_DQ VSS1 DDR_A_D4
3 4
DDR_A_D0 VSS2 DQ4 DDR_A_D5
<6> DDR_A_DM[0..7] 5 DQ0 DQ5 6

1
DDR_A_D1 7 8
R91 +V_DDR3_DIMM_REF DQ1 VSS3 DDR_A_DQS#0
<6> DDR_A_DQS[0..7] 9 10
1K_0402_1% DDR_A_DM0 VSS4 DQS#0 DDR_A_DQS0
11 DM0 DQS0 12
<6> DDR_A_MA[0..15] 13 VSS5 VSS6 14
DDR_A_D2 15 16 DDR_A_D6

2
+V_DDR3_DIMM_REF DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 18
DQ3 DQ7
19 VSS7 VSS8 20
1 DDR_A_D8 DDR_A_D12
21 DQ8 DQ12 22
R89 DDR_A_D9 23 24 DDR_A_D13
D DQ9 DQ13 D
25 26
1K_0402_1% DDR_A_DQS#1 VSS9 VSS10 DDR_A_DM1
27 28
DDR_A_DQS1 DQS#1 DM1 DIMM_DRAMRST#
29 30
2

DQS1 RESET# DIMM_DRAMRST# <11>

31 VSS11 VSS12 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
M1 Circuit 35 36
DQ11 DQ15
37 VSS13 VSS14 38
R90 1 2 0_0402_5% DDR_A_D16 39 40 DDR_A_D20
+V_DDR3_DIMM_REF DQ16 DQ20
DDR_A_D17 41 42 DDR_A_D21
DQ17 DQ21
43 VSS15 VSS16 44
2009/04/13 DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS#2 DM2
For Arrandale ,it should be use M1 Circuit 1 1 47 48
+1.5V C77 C78 DQS2 VSS17 DDR_A_D22
49 50
For Clarksfield ,it should be use M3 Circuit DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DG V1.52 0.1U_0402_16V4Z 2.2U_0603_6.3V4Z DDR_A_D19 53 54
DQ19 VSS19

1
2 2 55 56 DDR_A_D28
R92 1 @ DDR_A_D24 VSS20 DQ28 DDR_A_D29
2 0_0402_5% R93 57 DQ24 DQ29 58
11/10 Change C78 from DDR_A_D25 59 60
1K_0402_1% DQ25 VSS21 DDR_A_DQS#3
61 62
SE103225Z80 to DDR_A_DM3 VSS22 DQS#3 DDR_A_DQS3

D
63 64

2
DIMM_DRAMRST# DM3 DQS3
<5> SM_DRAMRST# 3 1 SE049225Z80 DDR_A_D26
65 VSS23 VSS24 66
DDR_A_D30
67 DQ26 DQ30 68

1
Q9 BSH111_SOT23-3 10/21 Change R93 from @ to mount DDR_A_D27 69 70 DDR_A_D31
R94 DQ27 DQ31

G
71 72
VSS25 VSS26

2
100K_0402_1%
11/05 Change R94 from @ to mount (Follow NIWE2)

2
RST_GATE DDR_A_CKE0 73 74 DDR_A_CKE1
<6> DDR_A_CKE0 CKE0 CKE1 DDR_A_CKE1 <6>
<18> RST_GATE 75 76
VDD1 VDD2 DDR_A_MA15
77 78
DDR_A_BS2 NC1 A15 DDR_A_MA14
1 <6> DDR_A_BS2 79 BA2 A14 80
C502 81 82
C DDR_A_MA12 VDD3 VDD4 DDR_A_MA11 C
83 A12/BC# A11 84
0.1U_0402_16V4Z DDR_A_MA9 85 86 DDR_A_MA7
2 A9 A7
87 88
DDR_A_MA8 VDD5 VDD6 DDR_A_MA6
89 A8 A6 90
DDR_A_MA5 91 92 DDR_A_MA4
A5 A4
93 VDD7 VDD8 94
10/22 Add C502 at RST_GATE DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 98
(Intel 425302_Calpella_S3PowerReduction_WhitePaper_Rev1.0) A1 A0
99 100
DDR_A_CLK0 VDD9 VDD10 DDR_A_CLK1
11/09 Change C502 from 0.047uF to 0.1uF <6> DDR_A_CLK0
DDR_A_CLK0#
101 CK0 CK1 102
DDR_A_CLK1# DDR_A_CLK1 <6>
<6> DDR_A_CLK0# 103 104 DDR_A_CLK1# <6>
CK0# CK1#
11/23 Change R92 from mount to @ DDR_A_MA10
105
VDD11 VDD12
106
DDR_A_BS1
107 108 DDR_A_BS1 <6>
Change Q9 from @ to mount DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
<6> DDR_A_BS0 109 110 DDR_A_RAS# <6>
BA0 RAS#
111 VDD13 VDD14 112
DDR_A_WE# 113 114 DDR_A_CS0#
<6> DDR_A_WE# WE# S0# DDR_A_CS0# <6>
<6> DDR_A_CAS# DDR_A_CAS# 115 116 DDR_A_ODT0
CAS# ODT0 DDR_A_ODT0 <6>
117 VDD15 VDD16 118
DDR_A_MA13 119 120 DDR_A_ODT1 +V_DDR3_DIMM_REF
DDR_A_CS1# A13 ODT1 DDR_A_ODT1 <6>
<6> DDR_A_CS1# 121 S1# NC2 122
123 124
VDD17 VDD18 DDR_VREF_CA_DIMMA
125 126 1 2
NCTEST VREF_CA R95 0_0402_5%
127 128
DDR_A_D32 VSS27 VSS28 DDR_A_D36
129 130
DDR_A_D33 DQ32 DQ36 DDR_A_D37
Layout Note: 131
DQ33 DQ37
132
133 134
Place near JDIMM1 DDR_A_DQS#4 VSS29 VSS30 DDR_A_DM4
135 DQS#4 DM4 136
DDR_A_DQS4 137 138 1 1
DQS4 VSS31 DDR_A_D38 C79 C80
139 140
DDR_A_D34 VSS32 DQ38 DDR_A_D39
Layout Note: Place these 4 Caps near Command 141
DQ34 DQ39
142
DDR_A_D35 143 144 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z
and Control signals of DIMMA 145
DQ35 VSS33
146 DDR_A_D44 2 2
B DDR_A_D40 VSS34 DQ44 DDR_A_D45 B
147 DQ40 DQ45 148
+1.5V DDR_A_D41 149 150
DQ41 VSS35 DDR_A_DQS#5
151 152
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5
153 154
DM5 DQS5
155 VSS37 VSS38 156
1 DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
1 1 1 1 1 1 1 1 1 1 159 160
C81 C82 C83 C84 C85 C86 C87 C88 C89 C90 + C91 DQ43 DQ47
161 162
@ DDR_A_D48 VSS39 VSS40 DDR_A_D52
163 164
220U_D2_4VM DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 166
2 2 2 2 2 2 2 2 2 2 2 DQ49 DQ53
167 168
DDR_A_DQS#6 VSS41 VSS42 DDR_A_DM6
169 170
DDR_A_DQS6 DQS#6 DM6
11/25 Change C91(@) from SGA20331E10 to SGA00000Y80 171 DQS6 VSS43 172
DDR_A_D54
173 VSS44 DQ54 174
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_A_D50 175 176 DDR_A_D55
DDR_A_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_A_D60
179 180
DDR_A_D56 VSS46 DQ60 DDR_A_D61
181 182
DDR_A_D57 DQ56 DQ61
183 184
DQ57 VSS47 DDR_A_DQS#7
185 186
DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7
187 188
DM7 DQS7
Layout Note: DDR_A_D58
189
VSS49 VSS50
190
DDR_A_D62
191 DQ58 DQ62 192
Place near JDIMM1.203 & JDIMM1.204 DDR_A_D59 193 194 DDR_A_D63
DQ59 DQ63
195 196
R96 VSS51 VSS52 PM_EXTTS#0_1
1 2 10K_0402_5% 197 SA0 EVENT# 198 PM_EXTTS#0_1 <5,11>
199 200 D_CK_SDATA
+3VS VDDSPD SDA D_CK_SCLK D_CK_SDATA <11,12>
201 202
+0.75VS SA1 SCL D_CK_SCLK <11,12>
1 1 203 204 +0.75VS
VTT1 VTT2

1
C92 C93
1U_0603_10V4Z 1U_0603_10V4Z 2.2U_0603_6.3V4Z R97 205 206
0.1U_0402_16V4Z G1 G2
A 2 2 10K_0402_5% FOX_AS0A626-U4SN-7F
CONN@
DDR3 SO-DIMM A A

Standard Type
2
2 2 2 2 1
C94 C95 C96 C97 C98

10U_0805_6.3V6M Copy NTUC0 H = 4.0mm

1 1 1 1 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/08/25 Title
1U_0603_10V4Z 1U_0603_10V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom NAU00 M/B LA-6101P Schematics 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 09, 2010 Sheet 10 of 48
5 4 3 2 1
 5 4 3 2 1

+1.5V
+1.5V
JDIMM2
<6> DDR_B_DQS#[0..7] VREF_DQB 1 VREF_DQ VSS1 2
3 4 DDR_B_D4
<6> DDR_B_D[0..63] DDR_B_D0 VSS2 DQ4 DDR_B_D5
5 6
DDR_B_D1 DQ0 DQ5
7 DQ1 VSS3 8
9 10 DDR_B_DQS#0
<6> DDR_B_DM[0..7] DDR_B_DM0 VSS4 DQS#0 DDR_B_DQS0
11 DM0 DQS0 12
13 14
<6> DDR_B_DQS[0..7] DDR_B_D2 VSS5 VSS6 DDR_B_D6
15 DQ2 DQ6 16
DDR_B_D3 17 18 DDR_B_D7
<6> DDR_B_MA[0..15] DQ3 DQ7
19 20
D DDR_B_D8 VSS7 VSS8 DDR_B_D12 D
21 22
DDR_B_D9 DQ8 DQ12 DDR_B_D13
23 24
DQ9 DQ13
25 VSS9 VSS10 26
DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS#1 DM1 DIMM_DRAMRST#
29 30 DIMM_DRAMRST# <10>
DQS1 RESET#
31 32
M1 Circuit DDR_B_D10 VSS11 VSS12 DDR_B_D14
33 DQ10 DQ14 34
DDR_B_D11 35 36 DDR_B_D15
DQ11 DQ15
37 38
R98 DDR_B_D16 VSS13 VSS14 DDR_B_D20
+V_DDR3_DIMM_REF_B 1 2 0_0402_5% 39 DQ16 DQ20 40
DDR_B_D17 41 42 DDR_B_D21
DQ17 DQ21
43 44
DDR_B_DQS#2 VSS15 VSS16 DDR_B_DM2
45 46
DDR_B_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
2009/04/13 49 50 DDR_B_D22
DDR_B_D18 VSS18 DQ22 DDR_B_D23
For Arrandale ,it should be use M1 Circuit 1 1 51 DQ18 DQ23 52
C99 C100 DDR_B_D19 53 54
For Clarksfield ,it should be use M3 Circuit DQ19 VSS19 DDR_B_D28
55 56
2.2U_0603_6.3V4Z DDR_B_D24 VSS20 DQ28 DDR_B_D29
DG V1.52 2 2
57
DQ24 DQ29
58
DDR_B_D25 59 60
DQ25 VSS21 DDR_B_DQS#3
61 VSS22 DQS#3 62
11/10 Change C99 from DDR_B_DM3 63 64 DDR_B_DQS3
0.1U_0402_16V4Z DM3 DQS3
65 VSS23 VSS24 66
SE103225Z80 to DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
SE049225Z80 69 DQ27 DQ31 70
71 VSS25 VSS26 72

<6> DDR_B_CKE0 DDR_B_CKE0 73 74 DDR_B_CKE1

+1.5V CKE0 CKE1 DDR_B_CKE1 <6>
75 VDD1 VDD2 76
77 78 DDR_B_MA15
C DDR_B_BS2 NC1 A15 DDR_B_MA14 C
<6> DDR_B_BS2 79 BA2 A14 80
1
81 VDD3 VDD4 82
R606 +V_DDR3_DIMM_REF_B DDR_B_MA12 83 84 DDR_B_MA11
1K_0402_1% DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
2

+V_DDR3_DIMM_REF_B DDR_B_MA5 A8 A6 DDR_B_MA4

91 A5 A4 92
93 94
VDD7 VDD8
1

DDR_B_MA3 95 96 DDR_B_MA2
R607 DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 100
1K_0402_1% DDR_B_CLK0 VDD9 VDD10 DDR_B_CLK1
<6> DDR_B_CLK0 101 102 DDR_B_CLK1 <6>
DDR_B_CLK0# CK0 CK1 DDR_B_CLK1#
<6> DDR_B_CLK0# 103 104
2

CK0# CK1# DDR_B_CLK1# <6>

105 106
DDR_B_MA10 VDD11 VDD12 DDR_B_BS1
107 A10/AP BA1 108 DDR_B_BS1 <6>
DDR_B_BS0 109 110 DDR_B_RAS#
<6> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <6>
111 112
DDR_B_WE# VDD13 VDD14 DDR_B_CS0#
<6> DDR_B_WE# 113 WE# S0# 114 DDR_B_CS0# <6>
Layout Note: DDR_B_CAS# 115 116 DDR_B_ODT0
<6> DDR_B_CAS# CAS# ODT0 DDR_B_ODT0 <6>
117 VDD15 VDD16 118
Place near JDIMM2 DDR_B_MA13 119 120 DDR_B_ODT1
DDR_B_ODT1 <6>
DDR_B_CS1# A13 ODT1 +V_DDR3_DIMM_REF_B
<6> DDR_B_CS1# 121 122
S1# NC2
Layout Note: Place these 4 Caps near Command 123
VDD17 VDD18
124
125 126 DDR_VREF_CA_DIMMB R99 1 2 0_0402_5%
and Control signals of DIMMA 127
NCTEST VREF_CA
128
DDR_B_D32 VSS27 VSS28 DDR_B_D36
129 130
+1.5V DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 DQ33 DQ37 132
133 134
10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_B_DQS#4 VSS29 VSS30 DDR_B_DM4
135 136
DDR_B_DQS4 DQS#4 DM4
137 138 1 1
DQS4 VSS31 DDR_B_D38 C101 C102
1 139 140
DDR_B_D34 VSS32 DQ38 DDR_B_D39
1 1 1 1 1 1 1 1 1 1 141 DQ34 DQ39 142
C105

B C103 C104 C106 C107 C108 C109 C110 C111 C112 + C113 DDR_B_D35 143 144 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z B
DQ35 VSS33 DDR_B_D44 2 2
145 146
220U_D2_4VM DDR_B_D40 VSS34 DQ44 DDR_B_D45
147 148
10U_0805_6.3V6M 2 2 2 2 2 2 2 2 2 2 2 DDR_B_D41 DQ40 DQ45
149 150
DQ41 VSS35 DDR_B_DQS#5
11/25 Change C113 from SGA20331E10 DDR_B_DM5
151 VSS36 DQS#5 152
DDR_B_DQS5
153 DM5 DQS5 154
to SGA00000Y80 155 156
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_B_D42 VSS37 VSS38 DDR_B_D46
157 158
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 160
DQ43 DQ47
161 162
DDR_B_D48 VSS39 VSS40 DDR_B_D52
163 164
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 166
DQ49 DQ53
167 VSS41 VSS42 168
Layout Note: DDR_B_DQS#6 169 170 DDR_B_DM6
DDR_B_DQS6 DQS#6 DM6
171 172
Place near JDIMM2.203 & JDIMM2.204 DQS6 VSS43 DDR_B_D54
173 174
DDR_B_D50 VSS44 DQ54 DDR_B_D55
175 176
DDR_B_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_B_D60
179 180
DDR_B_D56 VSS46 DQ60 DDR_B_D61
181 182
+0.75VS DDR_B_D57 DQ56 DQ61
183 184
DQ57 VSS47 DDR_B_DQS#7
185 186
1U_0603_10V4Z DDR_B_DM7 VSS48 DQS#7 DDR_B_DQS7
187 DM7 DQS7 188
189 190
DDR_B_D58 VSS49 VSS50 DDR_B_D62
191 192
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194
C114 2 C115 2 C116 2 C117 2 1 C118 195 196
R100 1 VSS51 VSS52 PM_EXTTS#0_1
2 10K_0402_5% 197 198 PM_EXTTS#0_1 <5,10>
SA0 EVENT# D_CK_SDATA
+3VS 199 200
1U_0603_10V4Z 10U_0805_6.3V6M VDDSPD SDA D_CK_SCLK D_CK_SDATA <10,12>
1 2 201 202
1 1 1 1 2 R101 10K_0402_5% SA1 SCL D_CK_SCLK <10,12>
203 204 +0.75VS
VTT1 VTT2
1 1
A C119 C120 A
205 206

1U_0603_10V4Z 1U_0603_10V4Z 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z

G1 G2
FOX_AS0A626-U4RN-7F
DDR3 SO-DIMM B
2 2 CONN@
Standard Type
Copy NTUC0
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/10 Deciphered Date 2010/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NAU00 M/B LA-6101P Schematics 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 09, 2010 Sheet 11 of 48
5 4 3 2 1
 A B C D E F G H

+CLK_VDD
Layout note: Layout note: Layout note:
Place C122 close to L2 Place C130 close to L1 Place C133 close to U2.1

1
Place C123 close to U2.15 Place C131 close to U2.5 R102
Place C134 close to U2.17
Layout note:
Place C124 close to U2.18 Place C132 close to U2.29 @ Place C135 close to U2.24
+CLK_VDD Place C507 close to R103 0_0402_5%
1
+CLK_VDDSRC +VDD_3V3_1V5 1

2
0.1U_0402_16V4Z
+1.1VS_VTT L2 1 2 0_0603_5% 0.1U_0402_16V4Z +3VS L1 1 2 0_0603_5% +1.5VS R103 1 2 0_0402_5%

1 1 1 1 1 1 1 1 1 1
11/06 Change +1.05VS to +1.1VS_VTT C122 C123 C124 C130 C131 C132 C507 C133 C134 C135

10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z

2 2 2 2 2 2 2 2 2 2

0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

11/03 Delete C121(@) 11/03 Delete C129(@) 11/03 Delete L3,C126,C125(@)
11/03 Change L2 from SM01000AX00 to 0ohm (Follow NIWE2) 11/03 Change L1 from SM01000AX00 to 0ohm (Follow NIWE2) 10/23 Delete C127, C128, C501
on +CLK_1.5VDD 10/23 Add C1000 on +VDD_3V3_1V5
Change C133, C134, C135 from +CLK_VDD to +VDD_3V3_1V5
11/03 Change C507 from @ to mount
Type R102 R103

Standard Mount @

Low Power @ Mount

2 2

10/23 Change U2 Pin1,17,24 +CLK_VDDSRC

Net Name to +VDD_3V3_1V5
+CLK_VDD
Clock Generator
+CLK_VDDSRC U2

11/03 Delete RP1,RP2,RP3,RP4 +VDD_3V3_1V5 1 32 D_CK_SCLK

VDD_USB_48 SCL D_CK_SDATA D_CK_SCLK <10,11>
2 VSS_48M SDA 31 D_CK_SDATA <10,11>
CLK_BUF_DREF_96M 3 30 REF_0/CPU_SEL R104 1 2 33_0402_5%
<14> CLK_BUF_DREF_96M DOT_96 REF_0/CPU_SEL CLK_BUF_ICH_14M <14>
CLK_BUF_DREF_96M# 4 29
<14> CLK_BUF_DREF_96M# DOT_96# VDD_REF
+CLK_VDD 5 28 CLK_XTAL_IN 1 11/04 Reserve C509(@) for
VDD_27 XTAL_IN CLK_XTAL_OUT C509
10/21 Change R542 from 0ohm to 33ohm (Vendor Recommend) 6 27MHZ XTAL_OUT 27
CLK_BUF_ICH_14M
7 27MHZ_SS VSS_REF 26
R542 1 2 33_0402_5% 48M 8 25 CK505_PW RGD 10P_0402_50V8J
<28> CLK_48M
C510 1 USB_48 CKPWRGD/PD# 2 (RF Recommend)
2 @ 15P_0402_50V8J

CLK_BUF_PCIE_SATA
9 VSS_27M VDD_CPU 24
CLK_BUF_CPU_BCLK
01/15 Add C509 (10pF)
<14> CLK_BUF_PCIE_SATA 10 SATA CPU_0 23 CLK_BUF_CPU_BCLK <14>
CLK_BUF_PCIE_SATA# 11 22 CLK_BUF_CPU_BCLK#
<14> CLK_BUF_PCIE_SATA# SATA# CPU_0# CLK_BUF_CPU_BCLK# <14>
12 VSS_SRC VSS_CPU 21
CLK_BUF_CPU_DMI 13 20
<14> CLK_BUF_CPU_DMI SRC_1 CPU_1
CLK_BUF_CPU_DMI# 14 19
<14> CLK_BUF_CPU_DMI# SRC_1# CPU_1#
15 VDD_SRC_IO VDD_CPU_IO 18
11/04 Reserve C510(@) for CLK_48M (RF Recommend) H_STP_CPU# 16 17
CPU_STOP# VDD_SRC
3 3
33 TGND +VDD_3V3_1V5
SLG8SP587VTR_QFN32_5X5
SA00003HR00
11/03 Change U2 from SA00003MF00 to SA00002XY00
10/23 Change R107 from mount to @ 11/23 Change U2 from SA00002XY00 to SA00003HR00
11/03 Change R107 from @ to mount
+3VS +3VS
+3VS R108
4.7K_0402_5% Realtek Have Internal Pull-Down
2

2
Q11 C136
G

1 2 +3VS
SSM3K7002FU_SC70-3 R105 22P_0402_50V8J 9/23 Change C495 to 22pF
R107 1 2 10K_0402_5% H_STP_CPU# 1 3 D_CK_SDATA 10K_0402_5% CLK_XTAL_IN 2 1
<14,32,37> PCH_SMBDATA R106
D

2
0_0402_5%

1
CK505_PW RGD 1 @ 2 Y1
VGATE <15,47>
IDT& Realtek Have Internal Pull-Down 9/10 Change symbol of 14.318MHZ_16PF_7A14300083 C137
+3VS 1
D 22P_0402_50V8J
Q31/Q32 to SC70-3

1
R110 2 CLK_XTAL_OUT 2 1
CLK_EN# <47>
R109 1 2 10K_0402_5% REF_0/CPU_SEL 4.7K_0402_5% Q10 G
2

SSM3K7002FU_SC70-3
G

1 2 +3VS S
3

9/10 Change symbol of

1 3 D_CK_SCLK
<14,32,37> PCH_SMBCLK Q29 to SC70-3
D

update PCB footprint

PIN 30 CPU_0 CPU_1 Q12
4
SSM3K7002FU_SC70-3 4

0 (Default) 133MHz 133MHz

1 100MHz 100MHz
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock Generator (CK505)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics
Date: Tuesday, March 09, 2010 Sheet 12 of 48
A B C D E F G H
 5 4 3 2 1

+RTCVCC 1 2 PCH_RTCRST#
R111 C138 R652 1 @ 2 0_0402_5%
20K_0402_1% RC Delay 18~25mS 18P_0402_50V8J
2 1 PCH_RTCX1 +3VS
close to RAM door
X1 12/17 Change U3 from SA00003N7B0 to SA00003N7A0

1
1 2 3 NC OSC 4 11/30 Change U3 from SA00003N720 to SA00003N7B0

5
J1 @ R112
10K_0603_5% 2 1 PCH : SA00003N7A0 PCH_SATALED#_R 2

P
C139 NC OSC 10M_0402_5% U3A B
Y 4 PCH_SATALED# <36>
1U_0603_10V6K 32.768KHZ_12.5PF_Q13MC14610002
REV1.0 1

2
A

G
1 2 C140 B13 D33 LPC_AD0
PCH_RTCX2 RTCX1 FWH0 / LAD0 LPC_AD1 LPC_AD0 <33> U34
D 2 1 D13 B33 D

3
RTCX2 FWH1 / LAD1 LPC_AD2 LPC_AD1 <33> NC7SZ08P5X_NL_SC70-5
FWH2 / LAD2 C32 LPC_AD2 <33>
18P_0402_50V8J A32 LPC_AD3
PCH_SRTCRST# PCH_RTCRST# FWH3 / LAD3 LPC_AD3 <33>
+RTCVCC 1 2 C14 RTCRST#
R115 C34 LPC_FRAME#
+RTCVCC FWH4 / LFRAME# LPC_FRAME# <33>
20K_0402_1% RC Delay 18~25mS PCH_SRTCRST# D17 01/21 Add U34,R652(@)
SRTCRST#
A34

RTC

LPC
R113 1 LDRQ0#
close to RAM door 2 1M_0402_5% SM_INTRUDER# A16 INTRUDER# LDRQ1# / GPIO23 F34
1 2
J2 @ R114 1 2 330K_0402_5% PCH_INTVRMEN A14 AB9 SERIRQ
10K_0603_5% INTVRMEN SERIRQ SERIRQ <33>
C141 10/5 Change R223 to 330K ohm
1U_0603_10V6K
1 2 INTVRMEN - Integrated SUS 1.1V VRM Enable HDA_BITCLK_PCH A30 HDA_BCLK SATA_DTX_C_PRX_N0
High - Enable Internal VRs SATA0RXN AK7 SATA_DTX_C_PRX_N0 <25>
HDA_SYNC_PCH D29 AK6 SATA_DTX_C_PRX_P0 SATA for HDD
HDA_SYNC SATA0RXP SATA_DTX_C_PRX_P0 <25>
AK11 SATA_PTX_DRX_N0
SATA0TXN SATA_PTX_DRX_N0 <25>
HDA for AUDIO 11/04 Reserve C508(@) for BITCLK (RF Recommend) PCH_SPKR P1 AK9 SATA_PTX_DRX_P0
<29> PCH_SPKR SPKR SATA0TXP SATA_PTX_DRX_P0 <25>
HDA_RST#_PCH C30
C508 1 HDA_RST#
2 @ 15P_0402_50V8J SATA1RXN AH6 SATA_DTX_C_PRX_N1
SATA_DTX_C_PRX_N1 <32>
AH5 SATA_DTX_C_PRX_P1 SATA for SSD
SATA1RXP SATA_DTX_C_PRX_P1 <32>
1 2 HDA_BITCLK_PCH G30 AH9 SATA_PTX_DRX_N1
<29> HDA_BITCLK_AUDIO <29> HDA_SDIN0 HDA_SDIN0 SATA1TXN SATA_PTX_DRX_N1 <32>
R116 33_0402_5% AH8 SATA_PTX_DRX_P1
SATA1TXP SATA_PTX_DRX_P1 <32>
1 2 HDA_SYNC_PCH F30
<29> HDA_SYNC_AUDIO HDA_SDIN1
R117 33_0402_5% AF11
HDA_RST#_PCH SATA2RXN 2/10 SATA2, SATA3 not support on HM55
<29> HDA_RST#_AUDIO 1 2 E32 AF9

IHDA
R118 33_0402_5% HDA_SDIN2 SATA2RXP
SATA2TXN AF7
1 2 HDA_SDOUT_PCH F32 AF6
<29> HDA_SDOUT_AUDIO HDA_SDIN3 SATA2TXP
C R119 33_0402_5% C
If GPIO33 pull down, ME will not working. SATA3RXN AH3
For factory update ME, pull down resistor pull HDA_SDOUT_PCH B29 AH1
HDA_SDO SATA3RXP
under door. <33> ME_EN# SATA3TXN AF3
SATA3TXP AF1
R604 1 @ 2 1K_0402_5% ME_EN# H32

SATA
HDA_DOCK_EN# / GPIO33 SATA_DTX_C_PRX_N4
11/10 Delete Q13,R120,R121 (Follow NIWE2) R603 1 @ SATA4RXN AD9 SATA_DTX_C_PRX_N4 <31>
+3VALW 2 10K_0402_5% PCH_GPIO13 J30 HDA_DOCK_RST# / GPIO13 SATA4RXP AD8 SATA_DTX_C_PRX_P4
SATA_DTX_C_PRX_P4 <31> SATA for eSATA
AD6 SATA_PTX_DRX_N4
SATA4TXN SATA_PTX_DRX_N4 <31>
GPIO33 can not pull down AD5 SATA_PTX_DRX_P4
SATA_PTX_DRX_P4 <31>
SATA4TXP
(manufacturing environments)
PCH_JTAG_TCK M3 AD3 SATA_DTX_C_PRX_N5
JTAG_TCK SATA5RXN SATA_DTX_C_PRX_N5 <32>
AD1 SATA_DTX_C_PRX_P5 SATA for SSD
SATA5RXP SATA_DTX_C_PRX_P5 <32>
PCH_JTAG_TMS K3 AB3 SATA_PTX_DRX_N5
JTAG_TMS SATA5TXN SATA_PTX_DRX_N5 <32>
AB1 SATA_PTX_DRX_P5
SATA5TXP SATA_PTX_DRX_P5 <32>
PCH_JTAG_TDI K1 JTAG_TDI +1.1VS_VTT

JTAG
PCH_JTAG_TDO J2 AF16
JTAG_TDO SATAICOMPO
PCH_JTAG_RST# SATA_COMP R122 1
11/06 Change +1.05VS to +1.1VS_VTT
J4 TRST# SATAICOMPI AF15 2 37.4_0402_1%

PCH_SPI_CLK_1 R123 1 2 0_0402_5% PCH_SPI_CLK BA2 +3VS

SPI_CLK
+3VS R126 10/5 Change R287 to 10K ohm PCH_SPI_CS0# R124 1 2 15_0402_5% PCH_SPI_CS0#_R AV3 R125 1 2 10K_0402_5%
10K_0402_5% SPI_CS0#
1 @ 2 PCH_SPKR AY3 T3 PCH_SATALED#_R
SPI_CS1# SATALED# +3VS
Have internal PD 9/3 Remove R738
B B

1 2 SERIRQ PCH_SPI_MOSI_1 R128 1 2 15_0402_5% PCH_SPI_MOSI AY1 Y9 PCH_GPIO21 R129 1 2 10K_0402_5%

R127 SPI_MOSI SATA0GP / GPIO21

SPI
10K_0402_5% PCH_SPI_MISO_1 R130 1 2 0_0402_5% PCH_SPI_MISO AV1 V1 PCH_GPIO19 R131 1 2 10K_0402_5%
SPI_MISO SATA1GP / GPIO19
10/5 Change R734 to 0 ohm

1
IBEXPEAK-M_FCBGA107
R132 R133
@ @
10K_0402_5% 10K_0402_5%
PCH JTAG PCH JTAG

2
Pre-Production Production +3VALW
PCH Pin RefDes 11/06 Change +1.05VS to +1.1VS_VTT
ES1 ES2 MP
*
R138 No Install 200ohm No Install R135 1 @ 2 200_0402_5% +3VS
PCH_JTAG_TMS R136 1 @ 2 100_0402_5% 11/09 Delete R148(@) (Follow NIWE2) 11/23 Change R129,R131 from @ to mount
PCH_JTAG_TDO R139 No Install 100ohm No Install
Change R132,R133 from mount to @
R138 1 @ 2 200_0402_5%
PCH_JTAG_TDO R139 1 @
(Follow NIWE2)
2 100_0402_5%
R135 200ohm 200ohm No Install +3VS
PCH_SPI_MOSI R149 1 @ 2 1K_0402_5% U4
PCH_JTAG_TMS R136 100ohm 100ohm No Install R143 1 @ 2 200_0402_5% enable iTPM: SPI_MOSI High PCH_SPI_CS0# 1 CS# VCC 8
PCH_JTAG_TDI R144 1 @ 2 100_0402_5% +3VS R140 1 2 3.3K_0402_5% SPI_W P1# 3 6 PCH_SPI_CLK_1
R141 1 WP# SCLK
2 3.3K_0402_5% SPI_HOLD1# 7 HOLD# SI 5 PCH_SPI_MOSI_1
4 2 PCH_SPI_MISO_1
R143 GND SO
200ohm 200ohm No Install R146 1 @ 2 20K_0402_5% PCH_JTAG_TCK R150 1 2 51_0402_5%
A
PCH_JTAG_RST# R147 1 @ 2 10K_0402_5% S IC FL 32M MX25L3205DM2I-12G SOP 8P A
PCH_JTAG_TDI R144 100ohm 100ohm No Install
11/05 Change R150 from 4.7kohm to 51ohm (Follow NIWE2) SPI ROM Footprint 150mil
11/05 Change R135,R136,R138,R139,R143,R144,R146,R147 from mount to @ (Follow NIWE2)
PCH_JTAG_TCK R150 51ohm 51ohm 51ohm 11/10 Delete R134(@),R137(@),R142(@),R145(@)
R146 20Kohm 20Kohm No Install Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title
PCH_JTAG_RST# R147 10Kohm 10Kohm No Install
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/9) SATA,HDA,SPI, LPC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics1.0
Date: Tuesday, March 09, 2010 Sheet 13 of 48
5 4 3 2 1
 5 4 3 2 1

U3B
+3VALW
PCIE_DTX_C_PRX_N1 BG30
REV1.0 B9 EC_LID_OUT#
<26> PCIE_DTX_C_PRX_N1 PERN1 SMBALERT# / GPIO11 EC_LID_OUT# <33>
PCIE_DTX_C_PRX_P1 BJ30 PCH_SML0CLK R622 1 2 2.2K_0402_5%
<26> PCIE_DTX_C_PRX_P1 PERP1
For PCIE LAN C142 2 1 .1U_0402_16V7K PCIE_PTX_DRX_N1 BF29 H14 PCH_SMBCLK
<26> PCIE_PTX_C_DRX_N1 PETN1 SMBCLK PCH_SMBCLK <12,32,37>
C143 2 1 .1U_0402_16V7K PCIE_PTX_DRX_P1 BH29 PCH_SML0DAT R623 1 2 2.2K_0402_5%
<26> PCIE_PTX_C_DRX_P1 PETP1
C8 PCH_SMBDATA
PCIE_DTX_C_PRX_N2 AW30 SMBDATA PCH_SMBDATA <12,32,37>
<32> PCIE_DTX_C_PRX_N2
PCIE_DTX_C_PRX_P2 BA30 PERN2 11/02 Add R621,R622 pull-up 2.2kohm to +3VALW (Follow NIWE2)
<32> PCIE_DTX_C_PRX_P2 PERP2
For Wireless LAN <32> PCIE_PTX_C_DRX_N2 C144 2 1 .1U_0402_16V7K PCIE_PTX_DRX_N2 BC30 J14 PCH_GPIO60
C145 2 .1U_0402_16V7K PCIE_PTX_DRX_P2 BD30 PETN2 SML0ALERT# / GPIO60
<32> PCIE_PTX_C_DRX_P2 1 PETP2
D C6 PCH_SML0CLK D
PCIE_DTX_C_PRX_N3 SML0CLK
AU30

SMBus
<37> PCIE_DTX_C_PRX_N3 PERN3
PCIE_DTX_C_PRX_P3 AT30 G8 PCH_SML0DAT
<37> PCIE_DTX_C_PRX_P3 PERP3 SML0DATA
For New Card C146 2 1 .1U_0402_16V7K PCIE_PTX_DRX_N3 AU32
<37> PCIE_PTX_C_DRX_N3 PETN3
C147 2 1 .1U_0402_16V7K PCIE_PTX_DRX_P3 AV32
<37> PCIE_PTX_C_DRX_P3 PETP3
M14 PCH_GPIO74
SML1ALERT# / GPIO74
BA32 PERN4
BB32 E10 PCH_SML1CLK R625 1 2 0_0402_5% EC_SMB_CK2
PERP4 SML1CLK / GPIO58 EC_SMB_CK2 <33>
BD32 PETN4
BE32 G12 PCH_SML1DAT R626 1 2 0_0402_5% EC_SMB_DA2
PETP4 SML1DATA / GPIO75 EC_SMB_DA2 <33>

PCI-E*
BF33 PERN5 11/05 Add R625,R626, delete Q14,Q15 (Follow NIWE2)
BH33 PERP5 CL_CLK1 T13

Controller
BG32 PETN5
BJ32 PETP5 CL_DATA1 T11

Link
BA34 PERN6 CL_RST1# T9
AW34 PERP6
BC34 PETN6 11/02 Change R597 to pull-up resister to +3VALW on PCH_GPIO47
BD34 PETP6
H1 PCH_GPIO47 R597 1 2 10K_0402_5% +3VALW
PEG_A_CLKRQ# / GPIO47
AT34 PERN7
2/10 PCIE7, PCIE8 not support on HM55 AU34 PERP7
AU36 PETN7 CLKOUT_PEG_A_N AD43
AV36 PETP7 CLKOUT_PEG_A_P AD45

BG34 PERN8 CLKOUT_DMI_N AN4 CLK_CPU_DMI# <5>

PEG
BJ34 PERP8 CLKOUT_DMI_P AN2 CLK_CPU_DMI <5>
BG36 PETN8
C BJ36 C
PETP8
CLKOUT_DP_N / CLKOUT_BCLK1_N AT1
CLKOUT_DP_P / CLKOUT_BCLK1_P AT3
R151 1 2 0_0402_5% CLK_PCIE_LAN#_R AK48 10/30 Delete Net : CLK_CPU_DP,CLK_CPU_DP#
<26> CLK_PCIE_LAN# CLKOUT_PCIE0N
For PCIE LAN R152 1 2 0_0402_5% CLK_PCIE_LAN_R AK47
<26> CLK_PCIE_LAN CLKOUT_PCIE0P

From CLK BUFFER

CLKIN_DMI_N AW24 CLK_BUF_CPU_DMI# <12>
11/05 Delete R153 LAN_CLKREQ# P9 BA24
<26> LAN_CLKREQ# PCIECLKRQ0# / GPIO73 CLKIN_DMI_P CLK_BUF_CPU_DMI <12>

R154 1 2 0_0402_5% CLK_PCIE_MINI1#_R AM43 AP3

<32> CLK_PCIE_MINI1# CLKOUT_PCIE1N CLKIN_BCLK_N CLK_BUF_CPU_BCLK# <12>
For Wireless LAN R155 1 2 0_0402_5% CLK_PCIE_MINI1_R AM45 AP1
<32> CLK_PCIE_MINI1 CLKOUT_PCIE1P CLKIN_BCLK_P CLK_BUF_CPU_BCLK <12>
MINI1_CLKREQ# U4
<32> MINI1_CLKREQ# PCIECLKRQ1# / GPIO18
CLKIN_DOT_96N F18 CLK_BUF_DREF_96M# <12>
CLKIN_DOT_96P E18 CLK_BUF_DREF_96M <12>
R156 1 2 0_0402_5% CLK_PCIE_EXP#_R AM47
<37> CLK_PCIE_EXP# CLKOUT_PCIE2N
For New Card R157 1 2 0_0402_5% CLK_PCIE_EXP_R AM48
<37> CLK_PCIE_EXP CLKOUT_PCIE2P
CLKIN_SATA_N / CKSSCD_N AH13 CLK_BUF_PCIE_SATA# <12>
EXP_CLKREQ# N4 AH12
<37> EXP_CLKREQ# PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P CLK_BUF_PCIE_SATA <12>

AH42 CLKOUT_PCIE3N REFCLK14IN P41 CLK_BUF_ICH_14M <12>

AH41 CLKOUT_PCIE3P
PCH_GPIO25 A8 J42
PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK CLK_PCI_FB <17>
C148
11/06 Change +1.05VS to +1.1VS_VTT 27P_0402_50V8J
AM51 AH51 XTAL25_IN 1 2
CLKOUT_PCIE4N XTAL25_IN XTAL25_OUT
AM53 CLKOUT_PCIE4P XTAL25_OUT AH53

2
B B
PCH_GPIO26 M9 AF38 XCLK_RCOMP R158 1 2 90.9_0402_1% +3VS R159 Y2
PCIECLKRQ4# / GPIO26 XCLK_RCOMP +1.1VS_VTT
1M_0402_5% 25MHZ_20PF_7A25000012
Project Port ID

1
AJ50 T45 PROJECT_ID2 R160 1 @ 2 10K_0402_5%

2
CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64 R161 1
AJ52 CLKOUT_PCIE5P 2 10K_0402_5% 1 2

PCH_GPIO44 H6 P43 PROJECT_ID1 R162 1 @ 2 10K_0402_5% C149

Clock Flex

PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65 R163 1 2 10K_0402_5% 27P_0402_50V8J

AK53 T42 PROJECT_ID0 R164 1 @ 2 10K_0402_5%

CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66 R165 1
AK51 CLKOUT_PEG_B_P 2 10K_0402_5%

PCH_GPIO56 P13 N50 PROJECT_ID3 R166 1 @ 2 10K_0402_5%

PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67 R167 1 2 10K_0402_5%
+3VS IBEXPEAK-M_FCBGA107
9/14 Add R374/R239/R375/R376(Project ID use)
9/14 Change power net from +3V
MINI1_CLKREQ# R168 1 2 10K_0402_5%
EXP_CLKREQ# R169 1
to +3VALW
2 10K_0402_5%
+3VALW

EC_LID_OUT# R170 1 2 10K_0402_5%

PCH_SMBCLK R171 1 2 2.2K_0402_5%
PCH_SMBDATA R172 1 2 2.2K_0402_5%

A
PCH_GPIO60 R173 1 2 10K_0402_5% A
9/14 Change to +3VALW(Follow CRB1.1) +3VALW
PCH_SML1CLK R174 1 2 2.2K_0402_5%
PCH_SML1DAT R175 1 2 2.2K_0402_5%

PCH_GPIO74 R176 1 2 10K_0402_5%

PCH_GPIO25 R177 1 2 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.
PCH_GPIO26 R178 1 2 10K_0402_5% 2009/10/10 2010/10/10 Title
Issued Date Deciphered Date
PCH_GPIO44 R179 10K_0402_5%
PCH_GPIO56 R180
1
1
2
2 10K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/9) PCIE, SMBUS, CLK
LAN_CLKREQ# R181 1 2 10K_0402_5% Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics1.0
Date: Tuesday, March 09, 2010 Sheet 14 of 48
5 4 3 2 1
 5 4 3 2 1

DMI_HTX_PRX_N[0..3]
<4> DMI_HTX_PRX_N[0..3]
DMI_HTX_PRX_P[0..3]
<4> DMI_HTX_PRX_P[0..3]
DMI_PTX_HRX_N[0..3]
<4> DMI_PTX_HRX_N[0..3]
DMI_PTX_HRX_P[0..3]
<4> DMI_PTX_HRX_P[0..3]

H_FDI_TXN[0..7]
<4> H_FDI_TXN[0..7]
D U3C D
H_FDI_TXP[0..7] H_FDI_TXN0
<4> H_FDI_TXP[0..7]
DMI_HTX_PRX_N0 BC24
REV1.0 FDI_RXN0 BA18
BH17 H_FDI_TXN1
DMI_HTX_PRX_N1 BJ22 DMI0RXN FDI_RXN1 H_FDI_TXN2
DMI1RXN FDI_RXN2 BD16
DMI_HTX_PRX_N2 AW20 BJ16 H_FDI_TXN3
DMI_HTX_PRX_N3 BJ20 DMI2RXN FDI_RXN3 H_FDI_TXN4
DMI3RXN FDI_RXN4 BA16
+3VS BE14 H_FDI_TXN5
DMI_HTX_PRX_P0 FDI_RXN5 H_FDI_TXN6
BD24 DMI0RXP FDI_RXN6 BA14
DMI_HTX_PRX_P1 BG22 BC12 H_FDI_TXN7
DMI_HTX_PRX_P2 DMI1RXP FDI_RXN7
BA20 DMI2RXP
1 2 PM_CLKRUN# DMI_HTX_PRX_P3 BG20 BB18 H_FDI_TXP0
R182 8.2K_0402_5% DMI3RXP FDI_RXP0 H_FDI_TXP1
FDI_RXP1 BF17
1 2 PCH_SYS_RESET# DMI_PTX_HRX_N0 BE22 BC16 H_FDI_TXP2
R183 10K_0402_5% DMI_PTX_HRX_N1 DMI0TXN FDI_RXP2 H_FDI_TXP3
BF21 DMI1TXN FDI_RXP3 BG16
DMI_PTX_HRX_N2 BD20 AW16 H_FDI_TXP4
DMI_PTX_HRX_N3 DMI2TXN FDI_RXP4 H_FDI_TXP5
10/30 Change R183 from mount to @ (Follow NCQD0) BE18 DMI3TXN FDI_RXP5 BD14
H_FDI_TXP6
11/25 Change R183 from @ to mount (Follow NIWE2) DMI_PTX_HRX_P0 FDI_RXP6 BB14
H_FDI_TXP7
BD22 DMI0TXP FDI_RXP7 BD12
9/14 Change power net from +3V DMI_PTX_HRX_P1 BH21
+3VALW DMI_PTX_HRX_P2 DMI1TXP
to +3VALW BC20 DMI2TXP
DMI_PTX_HRX_P3 BD18 BJ14
+1.1VS_VTT DMI3TXP FDI_INT H_FDI_INT <4>
11/06 Change +1.05VS to +1.1VS_VTT

DMI
FDI
1 2 SUS_PW R_ACK_R BF13
FDI_FSYNC0 H_FDI_FSYNC0 <4>
R184 10K_0402_5% R185 BH25
PCH_GPIO72 49.9_0402_1% DMI_ZCOMP
1 2 FDI_FSYNC1 BH13 H_FDI_FSYNC1 <4>
R186 8.2K_0402_5% 1 2 DMI_COMP BF25
RI# DMI_IRCOMP
1 2 FDI_LSYNC0 BJ12 H_FDI_LSYNC0 <4>
R187 10K_0402_5%
1 2 PCH_PCIE_W AKE# 10/22 Change R188 from 1kohm to 10kohm (Follow checklist) BG14
FDI_LSYNC1 H_FDI_LSYNC1 <4>
C R188 10K_0402_5% C
1 @ 2 PM_SLP_LAN# 10/22 Reserve R612(@) between PCH_SYS_RESET# and XDP_DBRESET#
R189 10K_0402_5%
Chanfe R183 from @ to mount
10/30 Change R612 from @ to mount (Follow NCQD0)

R612 2 1 0_0402_5% PCH_SYS_RESET# T6 J12 PCH_PCIE_W AKE#

<5> XDP_DBRESET# SYS_RESET# WAKE# PCH_PCIE_W AKE# <26,32,37>

SYS_PW ROK R190 2 1 0_0402_5% SYS_PW ROK_R M6 Y1 PM_CLKRUN#

VGATE R191 2 @ SYS_PWROK CLKRUN# / GPIO32 PM_CLKRUN# <33>
1 0_0402_5%

System Power Management

SYS_PW ROK B17 PWROK

2 1 ME_PW ROK K5 MEPWROK SUS_STAT# / GPIO61 P8 PCH_GPIO61 @ PAD T6

R192 0_0402_5%

LAN_RST# A10 F3 PCH_GPIO62 @ PAD

LAN_RST# SUSCLK / GPIO62 T7

<5> PM_DRAM_PW RGD D9 DRAMPWROK SLP_S5# / GPIO63 E4 PM_SLP_S5# <33>

PCH_RSMRST# C16 H7
RSMRST# SLP_S4# PM_SLP_S4# <33>
11/05 Add R627(@) (Follow NIWE2)
R627 1 @ 2 0_0402_5% SUS_PW R_ACK_RM1 P12
B <33> SUS_PW R_ACK SUS_PWR_DN_ACK / GPIO30 SLP_S3# PM_SLP_S3# <33> B

11/03 Change R193 from 100kohm to 10kohm (Follow Intel and PBTN_OUT#
NIWE2) PM_SLP_M# @
<33> PBTN_OUT# P5 PWRBTN# SLP_M# K8 PAD T8
R194 2 @ 1 0_0402_5%
+3VALW R193 1 2 10K_0402_5% Q16
R624 1 2 0_0402_5% PCH_ACIN P7 N2 PM_SLP_DSW # @ PAD MMBT3906_SOT23-3
<33> AC_PRESENT ACPRESENT / GPIO31 TP23 T9
PCH_RSMRST# 1 3

C
EC_RSMRST# <33>

E
11/03 Delete D1, add R624 PCH_GPIO72 A6 BJ10
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <5>

B
2
11/05 Delete the off page : EC_SWI# from PCH to EC, R195 1 2 +3VALW
RI# F14 F6 PM_SLP_LAN# 10K_0402_5% R196 4.7K_0402_5%
change net from EC_SWI# to RI# (Follow NIWE2) RI# SLP_LAN# / GPIO29
11/09 Add R629(@) D2A 9/14 Change power net from +3V

2
IBEXPEAK-M_FCBGA107 1 to +3VALW
6
R629 1 @ 2 0_0402_5% 2
+3VS BAV99DW -7-F_SOT363~N

D2B
5

U5 4 11/05 Change D3B to D2B

2 EC_PW ROK 3
P

B EC_PW ROK <33>

SYS_PW ROK 4 5
Y

1
1 VGATE
A VGATE <12,47>
G

BAV99DW -7-F_SOT363~N R197

NC7SZ08P5X_NL_SC70-5 2.2K_0402_5%
3

9/14 Change PN of D14B from SC6V99DW000 to SC6V99DW010

2
A A

SYS_PW ROK 1 2
R198 10K_0402_5%

EC_PW ROK 1 2
R199 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title
LAN_RST# 1
R200
2
10K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/9) DMI, FDI, PM
No used Integrated LAN, Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
connecting LAN_RST# to GND DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics1.0
Date: Tuesday, March 09, 2010 Sheet 15 of 48
5 4 3 2 1
 5 4 3 2 1

U3D
ENBKL 0_0402_5% 2 1 R213 IGPU_BKLT_EN T48 BJ46
<33> ENBKL L_BKLTEN SDVO_TVCLKINN
<22> PCH_ENVDD T47 L_VDD_EN SDVO_TVCLKINP BG46

D <22> DPST_PW M Y48 L_BKLTCTL SDVO_STALLN BJ48 D

SDVO_STALLP BG48
PCH_LCD_CLK AB48
<22> PCH_LCD_CLK PCH_LCD_DATA L_DDC_CLK
<22> PCH_LCD_DATA Y45 L_DDC_DATA SDVO_INTN BF45
SDVO_INTP BH45
LCTLA_CLK AB46
LCTLB_DATA L_CTRL_CLK
V48 L_CTRL_DATA
R202 1 2 100K_0402_5% IGPU_BKLT_EN
R201 1 2 LVDS_IBG AP39 T51
2.37K_0402_1% LVD_IBG SDVO_CTRLCLK SDVO_SCLK <24>
AP41 LVD_VBG SDVO_CTRLDATA T53 SDVO_SDATA <24>
10/5 Change R163 to 2.37K ohm(Follow CRB & DG2.0)
AT43 LVD_VREFH
AT42 BG44 R204 1 2 100K_0402_5%
LVD_VREFL DDPB_AUXN
DDPB_AUXP BJ44
11/09 Delete R203 AU38 PCH_DPB_HPD
DDPB_HPD PCH_DPB_HPD <24>

LVDS
PCH_TXCLK- AV53
<22> PCH_TXCLK- LVDSA_CLK#
PCH_TXCLK+ AV51 BD42 PCH_DPB_N0 C150 2 1 .1U_0402_16V7K
+3VS <22> PCH_TXCLK+ LVDSA_CLK DDPB_0N PCH_TMDS_D2# <24>
BC42 PCH_DPB_P0 C151 2 1 .1U_0402_16V7K HDMI D2
DDPB_0P PCH_TMDS_D2 <24>
PCH_TXOUT0- BB47 BJ42 PCH_DPB_N1 C152 2 1 .1U_0402_16V7K
<22> PCH_TXOUT0- LVDSA_DATA#0 DDPB_1N PCH_TMDS_D1# <24>
PCH_TXOUT1- BA52 BG42 PCH_DPB_P1 C153 2 1 .1U_0402_16V7K HDMI D1

Digital Display Interface

<22> PCH_TXOUT1- LVDSA_DATA#1 DDPB_1P PCH_TMDS_D1 <24>
PCH_TXOUT2- AY48 BB40 PCH_DPB_N2 C154 2 1 .1U_0402_16V7K
<22> PCH_TXOUT2- LVDSA_DATA#2 DDPB_2N PCH_TMDS_D0# <24>
AV47 BA40 PCH_DPB_P2 C155 2 1 .1U_0402_16V7K HDMI D0
LVDSA_DATA#3 DDPB_2P PCH_TMDS_D0 <24>
AW38 PCH_DPB_N3 C156 2 1 .1U_0402_16V7K
DDPB_3N PCH_TMDS_CK# <24>
PCH_TXOUT0+ BB48 BA38 PCH_DPB_P3 C157 2 1 .1U_0402_16V7K HDMI CLK
<22> PCH_TXOUT0+ LVDSA_DATA0 DDPB_3P PCH_TMDS_CK <24>
PCH_TXOUT1+ BA50
<22> PCH_TXOUT1+ LVDSA_DATA1
R205 1 2 10K_0402_5% LCTLA_CLK PCH_TXOUT2+ AY49
<22> PCH_TXOUT2+ LVDSA_DATA2
AV48 LVDSA_DATA3 DDPC_CTRLCLK Y49
R206 1 2 10K_0402_5% LCTLB_DATA AB49
DDPC_CTRLDATA
C R207 1 2 2.2K_0402_5% PCH_CRT_CLK AP48 C
LVDSB_CLK#
AP47 LVDSB_CLK DDPC_AUXN BE44
R208 1 2 2.2K_0402_5% PCH_CRT_DATA BD44
DDPC_AUXP
AY53 LVDSB_DATA#0 DDPC_HPD AV40
AT49 LVDSB_DATA#1
AU52 LVDSB_DATA#2 DDPC_0N BE40
AT53 LVDSB_DATA#3 DDPC_0P BD40
DDPC_1N BF41
AY51 LVDSB_DATA0 DDPC_1P BH41
AT48 LVDSB_DATA1 DDPC_2N BD38
AU50 LVDSB_DATA2 DDPC_2P BC38
AT51 LVDSB_DATA3 DDPC_3N BB36
DDPC_3P BA36

R209 1 2 150_0402_1% PCH_CRT_B PCH_CRT_B AA52 U50

<23> PCH_CRT_B CRT_BLUE DDPD_CTRLCLK
PCH_CRT_G AB53 U52
<23> PCH_CRT_G CRT_GREEN DDPD_CTRLDATA
R210 1 2 150_0402_1% PCH_CRT_G PCH_CRT_R AD53
<23> PCH_CRT_R CRT_RED
R211 1 2 150_0402_1% PCH_CRT_R BC46
PCH_CRT_CLK DDPD_AUXN
<23> PCH_CRT_CLK V51 CRT_DDC_CLK DDPD_AUXP BD46
PCH_CRT_DATA V53 AT38
<23> PCH_CRT_DATA CRT_DDC_DATA DDPD_HPD

DDPD_0N BJ40
1 1 1 <23> PCH_CRT_HSYNC Y53 CRT_HSYNC DDPD_0P BG40
C229 C230 C231 Y51 BJ38
<23> PCH_CRT_VSYNC CRT_VSYNC DDPD_1N
DDPD_1P BG38

CRT
12P_0402_50V8J BF37
2 2 2 12P_0402_50V8J CRT_IREF AD48 DDPD_2N
DAC_IREF DDPD_2P BH37
B B
AB51 CRT_IRTN DDPD_3N BE36

12P_0402_50V8J
REV1.0 DDPD_3P BD36

IBEXPEAK-M_FCBGA107
1

10/29 Move C229,C230,C231 close to U3 (EMI Recommend) R212

1K_0402_0.5%

2/3 Change to 1K_0402_0.5% from Intel

2

Suggestion. (EDS 1.0 is incorrect)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/9) LVDS, CRT, DPI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics 1.0
Date: Tuesday, March 09, 2010 Sheet 16 of 48
5 4 3 2 1
 5 4 3 2 1

U3E +VCCQ_NAND
+3VS 9/4 NC
H40
N34
AD0 REV1.0 NV_CE#0 AY9
BD1
AD1 NV_CE#1 NV_ALE R219 1 @
C44 AD2 NV_CE#2 AP15 2 1K_0402_5%
R218 1 2 8.2K_0402_5% PCI_PIRQA# A38 BD8 NV_CLE R221 1 @ 2 1K_0402_5%
R214 8.2K_0402_5% PCI_PIRQG# AD3 NV_CE#3
1 2 C36 AD4
R215 1 2 8.2K_0402_5% PCI_PIRQC# J34 AV9
R220 8.2K_0402_5% PCI_SERR# AD5 NV_DQS0 R628 1
1 2 A40 AD6 NV_DQS1 BG8 2 0_0402_5% 11/09 Add R628(@)
D45 AD7
E36 AD8 NV_DQ0 / NV_IO0 AP7
+3VS 12/04 Change R628 from @ to
H48 AD9 NV_DQ1 / NV_IO1 AP6
E40 AT6 mount
AD10 NV_DQ2 / NV_IO2
D C40 AD11 NV_DQ3 / NV_IO3 AT9 D

5
R222 1 2 8.2K_0402_5% PCI_PLOCK# M48 BB1 U6 @
R223 8.2K_0402_5% PCI_PERR# AD12 NV_DQ4 / NV_IO4 PLT_RST#
1 2 M45 AV6 2 B

P
R216 8.2K_0402_5% PCI_PIRQE# AD13 NV_DQ5 / NV_IO5
1 2 F53 AD14 NV_DQ6 / NV_IO6 BB3 Y 4 PLT_RST_BUF# <26,32,37>
R224 1 2 8.2K_0402_5% PCI_STOP# M40 BA4 1
AD15 NV_DQ7 / NV_IO7 A

G
NVRAM
M43 AD16 NV_DQ8 / NV_IO8 BE4

1
J36 BB6 NC7SZ08P5X_NL_SC70-5

3
AD17 NV_DQ9 / NV_IO9 R225
K48 AD18 NV_DQ10 / NV_IO10 BD6
F40 BB7 100K_0402_5%
AD19 NV_DQ11 / NV_IO11
C42 AD20 NV_DQ12 / NV_IO12 BC8
R217 1 2 8.2K_0402_5% PCI_REQ0# K46 BJ8 12/04 Change U6 from mount to @

2
R226 8.2K_0402_5% PCI_PIRQB# AD21 NV_DQ13 / NV_IO13
1 2 M51 AD22 NV_DQ14 / NV_IO14 BJ6
R227 1 2 8.2K_0402_5% PCI_PIRQF# J52 BG6
R228 8.2K_0402_5% PCI_REQ3# AD23 NV_DQ15 / NV_IO15
1 2 K51 AD24
L34 BD3 NV_ALE
AD25 NV_ALE NV_CLE
F42 AD26 NV_CLE AY6
J40 AD27
G46 AD28
R229 1 2 8.2K_0402_5% PCI_IRDY# F44 AU2 9/4 NC
R230 8.2K_0402_5% PCI_PIRQD# AD29 NV_RCOMP
1 2 M47 AD30

PCI
R231 1 2 8.2K_0402_5% PCI_REQ2# H36 AV7
R232 8.2K_0402_5% PCI_DEVSEL# AD31 NV_RB#
1 2
J50 C/BE0# NV_WR#0_RE# AY8
G42 C/BE1# NV_WR#1_RE# AY5
H47 C/BE2#
G34 C/BE3# NV_WE#_CK0 AV11
R233 1 2 8.2K_0402_5% PCI_FRAME# BF5
R234 8.2K_0402_5% PCI_REQ1# PCI_PIRQA# NV_WE#_CK1
1 2 G38 PIRQA#
R235 1 2 8.2K_0402_5% PCI_PIRQH# PCI_PIRQB# H51
C R236 8.2K_0402_5% PCI_TRDY# PCI_PIRQC# PIRQB# USB20_N0 C
1 2 B37 PIRQC# USBP0N H18 USB20_N0 <31>
PCI_PIRQD# A44 J18 USB20_P0 USB Conn.(HS) JUSB1
PIRQD# USBP0P USB20_N1 USB20_P0 <31>
USBP1N A18 USB20_N1 <31>
PCI_REQ0# F51 C18 USB20_P1 eSATA USB Conn.
PCI_REQ1# REQ0# USBP1P USB20_N2 USB20_P1 <31>
A46 REQ1# / GPIO50 USBP2N N20 USB20_N2 <22>
PCI_REQ2# B45 P20 USB20_P2 CMOS Camera (LVDS)
PCI_REQ3# REQ2# / GPIO52 USBP2P USB20_N3 USB20_P2 <22>
M53 REQ3# / GPIO54 USBP3N J20 USB20_N3 <31>
USBP3P L20 USB20_P3
USB20_P3 <31> USB Conn.(HS) JUSB2 EHCI 1
PCI_GNT0# F48 F20
PCI_GNT1# GNT0# USBP4N
K45 GNT1# / GPIO51 USBP4P G20 Danbury Technology Enabled
@ PCI_GNT2# F36 A20 USB20_N5
T14 PAD GNT2# / GPIO53 USBP5N USB20_N5 <28>
PCI_GNT3# H53 C20 USB20_P5 CardReader
GNT3# / GPIO55 USBP5P USB20_P5 <28>
USBP6N M22 High = Enabled
PCI_PIRQE# B41 N22 NV_ALE
PCI_PIRQF# PIRQE# / GPIO2 USBP6P
K53 PIRQF# / GPIO3 USBP7N B21 Note: USB6,USB7 not support on HM55 Low = Disabled
PCI_PIRQG# A36 D21
PCI_PIRQH# PIRQG# / GPIO4 USBP7P USB20_N8
A48 PIRQH# / GPIO5 USBP8N H22 USB20_N8 <32>
J22 USB20_P8 Mini Card(WLAN)
USBP8P USB20_P8 <32>

USB
K6 E22 USB20_N9
PCIRST# USBP9N USB20_P9 USB20_N9 <36>
USBP9P F22 USB20_P9 <36> Fingerprint DMI Termination Voltage
PCI_SERR# E44 A22 USB20_N10
PCI_PERR# SERR# USBP10N USB20_P10 USB20_N10 <37>
E50 PERR# USBP10P C22
USB20_N11 USB20_P10 <37> New Card
USBP11N G24 USB20_N11 <35>
Set to Vss when LOW
USBP11P H24 USB20_P11
USB20_P11 <35> Bluetooth EHCI 2 NV_CLE
PCI_IRDY# A42 L24 Set to Vcc when HIGH
IRDY# USBP12N
H44 PAR USBP12P M24
PCI_DEVSEL# F46 A24 USB20_N13
PCI_FRAME# DEVSEL# USBP13N USB20_P13 USB20_N13 <32>
C46 FRAME# USBP13P C24 USB20_P13 <32> Mini Card(3G)
B PCI_PLOCK# B
D49 PLOCK#
B25 USB_BIAS 1 2
PCI_STOP# USBRBIAS# R237
D41 STOP#
PCI_TRDY# C48 D25 22.6_0402_1% 11/09 Delete R238,R601
TRDY# USBRBIAS
PCI_PME# M7
<33> PCI_PME# PME#
OC0# / GPIO59 N16 USB_OC#0 <31>
(For USB Port0)
<5,33> PLT_RST#
PLT_RST# D5 J16 USB_OC#1 <31>
(For eSATA USB Port1)
PLTRST# OC1# / GPIO40
OC2# / GPIO41 F16 USB_OC#2_R (For USB Port3) OC[0..3] use for EHCI 1
N52 L16 USB_OC#3_R OC[4..7] use for EHCI 2
CLKOUT_PCI0 OC3# / GPIO42 USB_OC#4_R
P53 CLKOUT_PCI1 OC4# / GPIO43 E14
P46 G16 USB_OC#5_R
R242 CLKOUT_PCI2 OC5# / GPIO9
<33> CLK_PCI_LPC 1 2 22_0402_5% CLK_PCI_LPC_R P51 CLKOUT_PCI3 OC6# / GPIO10 F12 USB_OC#6_R
R243 1 2 22_0402_5% CLK_PCI_FB_R P48 T15 USB_OC#7_R
<14> CLK_PCI_FB CLKOUT_PCI4 OC7# / GPIO14
9/14 Change power net from +3V
2008/1/6 2009MOW01 change to 22 ohm IBEXPEAK-M_FCBGA107
to +3VALW

+3VALW
USB_OC#2_R R598 2 1 10K_0402_5%
Boot BIOS Strap USB_OC#3_R R599 2 1 10K_0402_5%
PCI_GNT0# R245 1 @ 2 1K_0402_5% USB_OC#4_R R600 2 1 10K_0402_5%
PCI_GNT#0 PCI_GNT#1 Boot BIOS Location Have internal PU USB_OC#5_R R244 2 1 10K_0402_5%
PCI_GNT1# R248 1 @ 2 1K_0402_5% USB_OC#6_R R247 2 1 10K_0402_5%
0 0 LPC Have internal PU USB_OC#7_R R249 2 1 10K_0402_5%

0 1 Reserved (NAND)
A
PCI_GNT3# R250 1 @ 2 1K_0402_5% A
1 0 PCI Have internal PU

* 1 1 SPI

A16 swap override Strap/Top-Block Security Classification Compal Secret Data Compal Electronics, Inc.
Swap Override jumper Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title

PCI_GNT#3 Low = A16 swap THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/9) PCI, USB, VRAM
High = Default Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics1.0
Date: Tuesday, March 09, 2010 Sheet 17 of 48
5 4 3 2 1
 5 4 3 2 1

+3VS
U3F

R277 2 1 10K_0402_5% PCH_GPIO0 PCH_GPIO0 Y3 AH45

R251 10K_0402_5% PCH_GPIO1 BMBUSY# / GPIO0 CLKOUT_PCIE6N
1 2 CLKOUT_PCIE6P AH46
R252 1 2 10K_0402_5% PCH_GPIO6 PCH_GPIO1 C38
R253 10K_0402_5% PCH_GPIO16 TACH1 / GPIO1
1 2
PCH_GPIO6 D37
R254 10K_0402_5% PCH_GPIO22 TACH2 / GPIO6
D 1 2 CLKOUT_PCIE7N AF48 D

MISC
R263 1 2 10K_0402_5% PCH_GPIO38 EC_SCI# J32 AF47 +3VS
<33> EC_SCI# TACH3 / GPIO7 CLKOUT_PCIE7P
R255 1 2 10K_0402_5% PCH_GPIO39
R264 1 2 10K_0402_5% PCH_GPIO36 EC_SMI# F10
<33> EC_SMI# GPIO8
R256 1 2 10K_0402_5% PCH_GPIO37 (GPIO8 Should not be Pull-Low) EC_GA20 R265 1 2 10K_0402_5%
R257 1 2 10K_0402_5% PCH_GPIO48 CP_PE# K9 U2 EC_GA20
<37> CP_PE# LAN_PHY_PWR_CTRL / GPIO12 A20GATE EC_GA20 <33>
R258 1 2 10K_0402_5% PCH_TEMP_ALERT# EC_KBRST# R259 1 2 10K_0402_5%
PCH_GPIO15 T7
R260 1 GPIO15
2 10K_0402_5% PCH_GPIO34
R261 1 @ 2 10K_0402_5% EC_SCI# PCH_GPIO16 AA2 AM3
SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLK_CPU_BCLK# <5>
+3VALW @ PCH_GPIO17 F38 AM1
T19 PAD TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLK_CPU_BCLK <5>
11/25 Change R261,R266 from mount to @ (Follow NIWE2) PCH_GPIO22 Y7 SCLOCK / GPIO22 PECI BG10 H_PECI <5>

GPIO
R262 1 2 10K_0402_5% PCH_GPIO57
(Rev:1.0 GPIO24 Only) H10 T1 EC_KBRST#
GPIO24 RCIN# EC_KBRST# <33>
R266 1 @ 2 10K_0402_5% EC_SMI#
@ PCH_GPIO27 AB12 BE10
T13 PAD GPIO27 PROCPWRGD H_CPUPW RGD <5>

CPU
R267 1 2 1K_0402_5% PCH_GPIO15
PCH_GPIO28 V13 BD10 THRMTRIP_PCH# 2 1 H_THERMTRIP#
GPIO28 THRMTRIP# R268 56_0402_5% H_THERMTRIP# <5>
PCH_GPIO34 M11 2 1 +1.1VS_VTT
STP_PCI# / GPIO34 R269 56_0402_5%
R270 1 2 10K_0402_5% PCH_GPIO28 PCH_GPIO35 V6
R271 10K_0402_5% CP_PE# SATACLKREQ# / GPIO35
1 2
R272 1 2 10K_0402_5% RST_GATE PCH_GPIO36 AB7 BA22
R273 10K_0402_5% PCH_GPIO45 SATA2GP / GPIO36 TP1
1 2 WW46 Platform/Design Updates
PCH_GPIO37 AB13 AW22
9/14 Change power net from +3V
SATA3GP / GPIO37 TP2 2008/11/17 54.9 1% ->56 5%
C PCH_GPIO38 V3 BB22 C
to +3VALW SLOAD / GPIO38 TP3
PCH_GPIO39 P3 AY45
SDATAOUT0 / GPIO39 TP4
PCH_GPIO45 H3 AY46
PCIECLKRQ6# / GPIO45 TP5
11/09 Delete R274(@),R276(@) RST_GATE F1 AV43
<10> RST_GATE PCIECLKRQ7# / GPIO46 TP6
PCH_GPIO48 AB6 AV45
SDATAOUT1 / GPIO48 TP7
R275 1 2 10K_0402_5% PCH_GPIO35 PCH_TEMP_ALERT# AA4 AF13
<33> PCH_TEMP_ALERT# SATA5GP / GPIO49 TP8
Schematics check list 2.0 PCH_GPIO57 F8 M18
GPIO57 TP9

TP10 N18

A4 VSS_NCTF_1 TP11 AJ24

A49

NCTF
VSS_NCTF_2

RSVD
A5 VSS_NCTF_3 TP12 AK41
A50 VSS_NCTF_4
A52 VSS_NCTF_5 TP13 AK42
A53 VSS_NCTF_6
B2 VSS_NCTF_7 TP14 M32
B4 VSS_NCTF_8
B52 VSS_NCTF_9 TP15 N32
B53 VSS_NCTF_10
BE1 VSS_NCTF_11 TP16 M30
BE53 VSS_NCTF_12
BF1 VSS_NCTF_13 TP17 N30
B B
BF53 VSS_NCTF_14
BH1 VSS_NCTF_15 TP18 H12
BH2 VSS_NCTF_16
BH52 VSS_NCTF_17 TP19 AA23
BH53 VSS_NCTF_18
BJ1 VSS_NCTF_19 NC_1 AB45
BJ2 VSS_NCTF_20
BJ4 VSS_NCTF_21 NC_2 AB38
BJ49 VSS_NCTF_22
BJ5 VSS_NCTF_23 NC_3 AB42
BJ50 VSS_NCTF_24
BJ52 VSS_NCTF_25 NC_4 AB41
BJ53 VSS_NCTF_26
D1 VSS_NCTF_27 NC_5 T39
D2 VSS_NCTF_28
D53 VSS_NCTF_29
E1 VSS_NCTF_30 INIT3_3V# P6
E53 VSS_NCTF_31
REV1.0 TP24 C10 TP24_SST @ PAD T10
IBEXPEAK-M_FCBGA107

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/9) GPIO, CPU, MISC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics 1.0
Date: Tuesday, March 09, 2010 Sheet 18 of 48
5 4 3 2 1
 5 4 3 2 1

CRB 0.9 is 180 ohm @ 100MHz

DG0.8 is 600 ohm FB (Page 290)

+1.1VS_VTT +3VS
11/06 Change +1.05VS to +1.1VS_VTT POWER
U3G 60mA R649
10U_0805_10V4Z 1U_0402_6.3V4Z AB24 AE50 +VCCADAC 1 2
VCCCORE[1] VCCADAC[1]
1 1 AB26 VCCCORE[2] 1 1 1 1
D Intel suggest follow CRB 8/21 AB28 69mA AE52 C160 C161 C162 C551 1_0603_5% D
C158 C159 VCCCORE[3] VCCADAC[2] @
AD26 VCCCORE[4]1524mA

CRT
AD28 AF53 0.01U_0402_16V7K 0.1U_0402_16V4Z 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 VCCCORE[5] VSSA_DAC[1] 2 2 2 2
AF26 VCCCORE[6]

VCC CORE
AF28 VCCCORE[7] VSSA_DAC[2] AF51
Near AB24 Near AB24 AF30 VCCCORE[8] Near AE50 +3VS 01/18 Change L4 (SM010005500) to R649 (SD013100B80)
Top Side AF31 VCCCORE[9] 11/09 Delete R278(@) 01/18 Change C162 from 10uF to 22uF
AH26 VCCCORE[10] +VCCA_LVDS R279 1
01/19 Add C551(@)
AH28 VCCCORE[11] 2 0_0603_5%
AH30 VCCCORE[12] 300mA
AH31 VCCCORE[13] VCCALVDS AH38 11/09 Change R279 from 0_0805 to 0_0603
All Ibex Peak-M Power rails with netnames +1.1VS and AJ30 VCCCORE[14]
AJ31 AH39
+1.1V rails are actually +1.05VS and +1.05V rails VCCCORE[15] VSSA_LVDS

+1.1VS_VTT 59mA +1.8VS

VCCTX_LVDS[1] AP43
VCCTX_LVDS[2] AP45
AT46 Near AP43 L5

LVDS
VCCTX_LVDS[3] +VCCTX_LVDS C165
AK24 VCCIO[24] VCCTX_LVDS[4] AT45 2 1
C163 1 1 1 0.1UH_MLF1608DR10KT_10%_1608
42mA 0.01U_0402_16V7K 22U_0805_6.3V6M 0.1uH inductor, 200mA
11/09 Delete L6(@),C166(@) BJ24 C164
VCCAPLLEXP 0.01U_0402_16V7K
VCC3_3[2] AB34
2 2 2
AN20 VCCIO[25] VCC3_3[3] AB35
AN22

HVCMOS
VCCIO[26]
AN23 VCCIO[27] VCC3_3[4] AD35 +3VS
AN24 VCCIO[28]
AN26 VCCIO[29] 1 Near AB34
C AN28 C
VCCIO[30] C167
BJ26 VCCIO[31]
BJ28 0.1U_0402_16V4Z Change R280,R281,R282 from 0805 to 0603 (Layout Request)
VCCIO[32] 2
AT26 VCCIO[33]
AT28 VCCIO[34] 11/06 Change +1.05VS to +1.1VS_VTT
AU26 VCCIO[35]
+1.1VS_VTT +VCCVRM
11/06 Change +1.05VS to +1.1VS_VTT AU28 VCCIO[36] 11/09 Delete R280(@),R281(@)
AV26 VCCIO[37] 35mA R282 1
Near AN20 AV28 VCCIO[38] VCCVRM[2] AT24 2 0_0402_5% +1.8VS 11/09 Change R282 from 0_0603 to 0_0402
10U_0805_10V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z AW26 3208mA
VCCIO[39]
1 1 1 1 1 AW28 VCCIO[40] 61mA +1.1VS_VTT

DMI
BA26 VCCIO[41] VCCDMI[1] AT16
C168 C169 C170 C171 C172 BA28 VCCIO[42] +VCC_DMI R283 1
BB26 VCCIO[43] VCCDMI[2] AU16 2 0_0402_5%
2 2 2 2 2
BB28 VCCIO[44] 1 11/09 Change R283 from 0_0805 to 0_0402
BC26 VCCIO[45]

PCI E*
Top Side 1U_0402_6.3V4Z 1U_0402_6.3V4Z BC28 C173 11/06 Delete R284(@)
VCCIO[46] 1U_0402_6.3V4Z
BD26 VCCIO[47] 2
BD28 VCCIO[48] 156mA
BE26 VCCIO[49] VCCPNAND[1] AM16 Near AT16
BE28 VCCIO[50] VCCPNAND[2] AK16
BG26 VCCIO[51] VCCPNAND[3] AK20
BG28 VCCIO[52] VCCPNAND[4] AK19
Near AN35 BH27 VCCIO[53] VCCPNAND[5] AK15
+VCCQ_NAND +1.8VS
VCCPNAND[6] AK13
+3VS AN30 AM12
Follow Intel suggestion 8/21 VCCIO[54] VCCPNAND[7]

NAND / SPI
AN31 VCCIO[55] VCCPNAND[8] AM13
AM15 R285 1 2 0_0402_5% 11/09 Change R285 from 0_0805 to 0_0402
0.1U_0402_16V4Z VCCPNAND[9]
B
1 B
C175 2 1 AN35 VCC3_3[1] C174
0.1U_0402_16V4Z
2
+VCCVRM AT22 VCCVRM[1]
85mA Near AK13
11/09 Delete L7(@),C176(@) BJ18 VCCFDIPLL 6mA VCCME3_3[1] AM8
+3VS
VCCME3_3[2] AM9
FDI

+1.1VS_VTT AM23 VCCIO[1] VCCME3_3[3] AP11

VCCME3_3[4] AP9
1
REV1.0 C177
IBEXPEAK-M_FCBGA107 0.1U_0402_16V4Z
2
11/06 Change +1.05VS to +1.1VS_VTT Near AM8

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/9) PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics1.0
Date: Friday, February 26, 2010 Sheet 19 of 48
5 4 3 2 1
 5 4 3 2 1

U3J POWER
AP51
REV1.0 V24
11/06 Change +1.05VS to +1.1VS_VTT
VCCACLK[1] VCCIO[5] +1.1VS_VTT
11/09 Delete L8(@),C178(@),C179(@) 52mA VCCIO[6] V26 1
+1.1VS_VTT +VCCADPLLA
AP53 VCCACLK[2] VCCIO[7] Y24
Y26 C189
VCCIO[8] 1U_0402_6.3V4Z
11/09 Delete R286(@),C190(@) 344mA 2
AF23 VCCLAN[1] VCCSUS3_3[1] V28
+3VALW
Near BB51
U28 Near V24 L9 1 2
VCCSUS3_3[2] 10UH_LB2012T100MR_20%
AF24 VCCLAN[2] VCCSUS3_3[3] U26
U24 0.1U_0402_16V4Z 10uH inductor, 120mA
1 1
VCCSUS3_3[4]

1
P28 1 1 R288
VCCSUS3_3[5]

1
D R287 +PCH_VCCD6W Y20 P26 + C191 0_0402_5% D
0_0402_5% DCPSUSBYP VCCSUS3_3[6] C180 C181 C182 1U_0402_6.3V4Z @
1 VCCSUS3_3[7] N28
0.1U_0402_16V4Z 220U_B2_2.5VM_R35 2
C183
1998mA VCCSUS3_3[8] N26
2 2 2
AD38 M28

2
0.1U_0402_16V4Z VCCME[1] VCCSUS3_3[9]
M26 Near A26 Near U23

2
2 VCCSUS3_3[10] +VCCADPLLB
AD39 L28

USB
VCCME[2] VCCSUS3_3[11]
11/06 Change +1.05VS to +1.1VS_VTT VCCSUS3_3[12] L26
Near Y20 AD41 VCCME[3] VCCSUS3_3[13] J28 9/14 Change power net from +3V
J26 L10 1 2
+1.1VS_VTT Follow Intel suggestion VCCSUS3_3[14] to +3VALW 10UH_LB2012T100MR_20%
AF43 VCCME[4] VCCSUS3_3[15] H28
VCCSUS3_3[16] H26 10uH inductor, 120mA 1 1
22U_0805_6.3V6M AF41 163mA G28
VCCME[5] VCCSUS3_3[17] + C185
1 1 1 1 1 VCCSUS3_3[18] G26
AF42 F28 9/14 Change power net from +3V C184 1U_0402_6.3V4Z
C192 C186 C193 C187 C188 VCCME[6] VCCSUS3_3[19] 220U_B2_2.5VM_R35 2
VCCSUS3_3[20] F26 to +3VALW
22U_0805_6.3V6M +3VALW 2
2 2 2 2 2
V39 VCCME[7] VCCSUS3_3[21] E28 Near BD51
1U_0402_6.3V4Z E26

Clock and Miscellaneous

VCCSUS3_3[22]
V41 VCCME[8] VCCSUS3_3[23] C28

2
22U_0805_6.3V6M Near AD38 1U_0402_6.3V4Z Near V39 C26
VCCSUS3_3[24] D4
V42 VCCME[9] VCCSUS3_3[25] B27
A28 RB751V-40_SOD323-2 12/27 Change D4,D5 from SC1H751H010 to SCS00000Z00
VCCSUS3_3[26]
Y39 VCCME[10] VCCSUS3_3[27] A26
All Ibex Peak-M Power rails with netnames +1.1VS and +1.1VS_VTT 9/14 Follow

1
Y41 U23 +3VS
+1.1V rails are actually +1.05VS and +1.05V rails VCCME[11] VCCSUS3_3[28] CRB1.1 Change +5VALW
Y42 V23 to 10 ohm
VCCME[12] VCCIO[56]

2
R289
Near V9 C194 >1mA F24 +VCC5REFSUS 1 2 10_0402_5% D5 9/14 Follow
0.1U_0402_16V4Z V5REF_SUS RB751V-40_SOD323-2
9/14 Follow CRB1.1 Change
C 1 2 +VCCRTCEXT V9 2 1 C195 C
DCPRTC 0.1U_0402_16V4Z
CRB1.1 Change to 10 ohm

1
>1mA Near F24 to 0.1uF R290
K49 +VCC5REF 1 2 10_0402_5% +5VS
V5REF Change to 1U for power
+VCCVRM AU24 VCCVRM[3]

PCI/GPIO/LPC
357mA sequence issue on ICH9 2 1 C196
72mA J38 1U_0402_6.3V6K
VCC3_3[8]
+VCCADPLLA BB51 VCCADPLLA[1] Near K49
BB53 VCCADPLLA[2] VCC3_3[9] L38
+3VS
73mA VCC3_3[10] M36
11/06 Change +1.05VS to +1.1VS_VTT +1.1VS_VTT +VCCADPLLB BD51 VCCADPLLB[1]
BD53 VCCADPLLB[2] VCC3_3[11] N36
Near AF32 Near AH23 1
AH23 P36 C197
VCCIO[21] VCC3_3[12]
AJ35 VCCIO[22]
1 1 1 AH35 U35 0.1U_0402_16V4Z
VCCIO[23] VCC3_3[13] 2 +3VS
C198 C199 C200 AF34 Near J38
1U_0402_6.3V4Z 1U_0402_6.3V4Z VCCIO[2]
2 2 2 VCC3_3[14] AD13 Near AD13
AH34 VCCIO[3]
Near AH35 1 2 C201
1U_0402_6.3V4Z AF32 32mA 0.1U_0402_16V4Z
VCCIO[4]
VCCSATAPLL[1] AK3
1 2 +VCCSST V12 AK1 11/09 Delete L11(@),C203(@),C204(@)
C202 DCPSST VCCSATAPLL[2]
Near V12
0.1U_0402_16V4Z
+1.1VS_VTT
1 2 +VCCSUS Y22
B C205 DCPSUS B
+3VALW
Near Y22 VCCIO[9] AH22
9/14 Change power net from +3V 0.1U_0402_16V4Z 11/06 Change +1.05VS to +1.1VS_VTT
to +3VALW
P18 VCCSUS3_3[29] VCCVRM[4] AT20 +VCCVRM
1
U19 11/06 Change +1.05VS to +1.1VS_VTT
SATA
C206 VCCSUS3_3[30] +1.1VS_VTT
PCI/GPIO/LPC

VCCIO[10] AH19
0.1U_0402_16V4Z U20
2 VCCSUS3_3[31]
VCCIO[11] AD20
Near P18 U22 VCCSUS3_3[32]
VCCIO[12] AF22 1
+3VS
AD19 C207
VCCIO[13] 1U_0402_6.3V4Z
V15 VCC3_3[5] VCCIO[14] AF20
2
1 VCCIO[15] AF19
V16 VCC3_3[6] VCCIO[16] AH20 Near AB19
C208
0.1U_0402_16V4Z
11/06 Change +1.05VS to +1.1VS_VTT
Y16 VCC3_3[7] VCCIO[17] AB19
2
+1.1VS_VTT VCCIO[18] AB20 11/09 Change +1.1VS_VTT
Near V15 VCCIO[19] AB22
> 1mA AD22 R292,R293,R294,R295 from
VCCIO[20]
AT18 V_CPU_IO[1] 0_0603 to 0_0402 0_0402_5%
1 1 1 AA34 PCH_VCCME13 R292 1 2
CPU

C210 C211 C212 VCCME[13] PCH_VCCME14 R293 1

VCCME[14] Y34 2 0_0402_5%
AU18 Y35 PCH_VCCME15 R294 1 2 0_0402_5%
4.7U_0603_6.3V6K 0.1U_0402_16V4Z V_CPU_IO[2] VCCME[15] PCH_VCCME16 R295 1
VCCME[16] AA35 2 0_0402_5%
2 2 2
0.1U_0402_16V4Z Near AT18 2mA 6mA
RTC

A A12 L30 +VCCSUSHDA R593 1 2 0_0402_5% +3VALW A

VCCRTC VCCSUSHDA
HDA

R594 1 @ 2 0_0402_5% +1.5V 11/09 Change R593,R594 from 0_0603 to 0_0402

IBEXPEAK-M_FCBGA107 C213 1 2 1U_0402_6.3V4Z Near L30
+RTCVCC
1 1 1
C215 C216
C214 Security Classification Compal Secret Data Compal Electronics, Inc.
0.1U_0402_16V4Z 2009/10/10 2010/10/10 Title
2 2 2 Issued Date Deciphered Date
1U_0402_6.3V4Z
Near A12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (8/9) PWR
0.1U_0402_16V4Z Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics 1.0
Date: Friday, February 26, 2010 Sheet 20 of 48
5 4 3 2 1
 5 4 3 2 1

U3I U3H
AY7 VSS[159] VSS[259] H49 AB16 VSS[0]
B11 VSS[160] VSS[260] H5
B15 VSS[161] VSS[261] J24 AA19 VSS[1] VSS[80] AK30
B19 VSS[162] VSS[262] K11 AA20 VSS[2] VSS[81] AK31
B23 VSS[163] VSS[263] K43 AA22 VSS[3] VSS[82] AK32
B31 VSS[164] VSS[264] K47 AM19 VSS[4] VSS[83] AK34
B35 VSS[165] VSS[265] K7 AA24 VSS[5] VSS[84] AK35
B39 VSS[166] VSS[266] L14 AA26 VSS[6] VSS[85] AK38
B43 VSS[167] VSS[267] L18 AA28 VSS[7] VSS[86] AK43
B47 VSS[168] VSS[268] L2 AA30 VSS[8] VSS[87] AK46
B7 VSS[169] VSS[269] L22 AA31 VSS[9] VSS[88] AK49
D BG12 VSS[170] VSS[270] L32 AA32 VSS[10] VSS[89] AK5 D
BB12 VSS[171] VSS[271] L36 AB11 VSS[11] VSS[90] AK8
BB16 VSS[172] VSS[272] L40 AB15 VSS[12] VSS[91] AL2
BB20 VSS[173] VSS[273] L52 AB23 VSS[13] VSS[92] AL52
BB24 VSS[174] VSS[274] M12 AB30 VSS[14] VSS[93] AM11
BB30 VSS[175] VSS[275] M16 AB31 VSS[15] VSS[94] BB44
BB34 VSS[176] VSS[276] M20 AB32 VSS[16] VSS[95] AD24
BB38 VSS[177] VSS[277] N38 AB39 VSS[17] VSS[96] AM20
BB42 VSS[178] VSS[278] M34 AB43 VSS[18] VSS[97] AM22
BB49 VSS[179] VSS[279] M38 AB47 VSS[19] VSS[98] AM24
BB5 VSS[180] VSS[280] M42 AB5 VSS[20] VSS[99] AM26
BC10 VSS[181] VSS[281] M46 AB8 VSS[21] VSS[100] AM28
BC14 VSS[182] VSS[282] M49 AC2 VSS[22] VSS[101] BA42
BC18 VSS[183] VSS[283] M5 AC52 VSS[23] VSS[102] AM30
BC2 VSS[184] VSS[284] M8 AD11 VSS[24] VSS[103] AM31
BC22 VSS[185] VSS[285] N24 AD12 VSS[25] VSS[104] AM32
BC32 VSS[186] VSS[286] P11 AD16 VSS[26] VSS[105] AM34
BC36 VSS[187] VSS[287] AD15 AD23 VSS[27] VSS[106] AM35
BC40 VSS[188] VSS[288] P22 AD30 VSS[28] VSS[107] AM38
BC44 VSS[189] VSS[289] P30 AD31 VSS[29] VSS[108] AM39
BC52 VSS[190] VSS[290] P32 AD32 VSS[30] VSS[109] AM42
BH9 VSS[191] VSS[291] P34 AD34 VSS[31] VSS[110] AU20
BD48 VSS[192] VSS[292] P42 AU22 VSS[32] VSS[111] AM46
BD49 VSS[193] VSS[293] P45 AD42 VSS[33] VSS[112] AV22
BD5 VSS[194] VSS[294] P47 AD46 VSS[34] VSS[113] AM49
BE12 VSS[195] VSS[295] R2 AD49 VSS[35] VSS[114] AM7
BE16 VSS[196] VSS[296] R52 AD7 VSS[36] VSS[115] AA50
BE20 VSS[197] VSS[297] T12 AE2 VSS[37] VSS[116] BB10
BE24 VSS[198] VSS[298] T41 AE4 VSS[38] VSS[117] AN32
C BE30 T46 AF12 AN50 C
VSS[199] VSS[299] VSS[39] VSS[118]
BE34 VSS[200] VSS[300] T49 Y13 VSS[40] VSS[119] AN52
BE38 VSS[201] VSS[301] T5 AH49 VSS[41] VSS[120] AP12
BE42 VSS[202] VSS[302] T8 AU4 VSS[42] VSS[121] AP42
BE46 VSS[203] VSS[303] U30 AF35 VSS[43] VSS[122] AP46
BE48 VSS[204] VSS[304] U31 AP13 VSS[44] VSS[123] AP49
BE50 VSS[205] VSS[305] U32 AN34 VSS[45] VSS[124] AP5
BE6 VSS[206] VSS[306] U34 AF45 VSS[46] VSS[125] AP8
BE8 VSS[207] VSS[307] P38 AF46 VSS[47] VSS[126] AR2
BF3 VSS[208] VSS[308] V11 AF49 VSS[48] VSS[127] AR52
BF49 VSS[209] VSS[309] P16 AF5 VSS[49] VSS[128] AT11
BF51 VSS[210] VSS[310] V19 AF8 VSS[50] VSS[129] BA12
BG18 VSS[211] VSS[311] V20 AG2 VSS[51] VSS[130] AH48
BG24 VSS[212] VSS[312] V22 AG52 VSS[52] VSS[131] AT32
BG4 VSS[213] VSS[313] V30 AH11 VSS[53] VSS[132] AT36
BG50 VSS[214] VSS[314] V31 AH15 VSS[54] VSS[133] AT41
BH11 VSS[215] VSS[315] V32 AH16 VSS[55] VSS[134] AT47
BH15 VSS[216] VSS[316] V34 AH24 VSS[56] VSS[135] AT7
BH19 VSS[217] VSS[317] V35 AH32 VSS[57] VSS[136] AV12
BH23 VSS[218] VSS[318] V38 AV18 VSS[58] VSS[137] AV16
BH31 VSS[219] VSS[319] V43 AH43 VSS[59] VSS[138] AV20
BH35 VSS[220] VSS[320] V45 AH47 VSS[60] VSS[139] AV24
BH39 VSS[221] VSS[321] V46 AH7 VSS[61] VSS[140] AV30
BH43 VSS[222] VSS[322] V47 AJ19 VSS[62] VSS[141] AV34
BH47 VSS[223] VSS[323] V49 AJ2 VSS[63] VSS[142] AV38
BH7 VSS[224] VSS[324] V5 AJ20 VSS[64] VSS[143] AV42
C12 VSS[225] VSS[325] V7 AJ22 VSS[65] VSS[144] AV46
C50 VSS[226] VSS[326] V8 AJ23 VSS[66] VSS[145] AV49
D51 VSS[227] VSS[327] W2 AJ26 VSS[67] VSS[146] AV5
B B
E12 VSS[228] VSS[328] W52 AJ28 VSS[68] VSS[147] AV8
E16 VSS[229] VSS[329] Y11 AJ32 VSS[69] VSS[148] AW14
E20 VSS[230] VSS[330] Y12 AJ34 VSS[70] VSS[149] AW18
E24 VSS[231] VSS[331] Y15 AT5 VSS[71] VSS[150] AW2
E30 VSS[232] VSS[332] Y19 AJ4 VSS[72] VSS[151] BF9
E34 VSS[233] VSS[333] Y23 AK12 VSS[73] VSS[152] AW32
E38 VSS[234] VSS[334] Y28 AM41 VSS[74] VSS[153] AW36
E42 VSS[235] VSS[335] Y30 AN19 VSS[75] VSS[154] AW40
E46 VSS[236] VSS[336] Y31 AK26 VSS[76] VSS[155] AW52
E48 VSS[237] VSS[337] Y32 AK22 VSS[77] VSS[156] AY11
E6 VSS[238] VSS[338] Y38 AK23 VSS[78] VSS[157] AY43
E8
F49
VSS[239] VSS[339] Y43
Y46
AK28 VSS[79] REV1.0 VSS[158] AY47
VSS[240] VSS[340] IBEXPEAK-M_FCBGA107
F5 VSS[241] VSS[341] P49
G10 VSS[242] VSS[342] Y5
G14 VSS[243] VSS[343] Y6 9/14 Change PN of U60 from SA00002KV0L to SA00003NI20
G18 VSS[244] VSS[344] Y8
G2 VSS[245] VSS[345] P24
G22 VSS[246] VSS[346] T43
G32 VSS[247] VSS[347] AD51
G36 VSS[248] VSS[348] AT8
G40 VSS[249] VSS[349] AD47
G44 VSS[250] VSS[350] Y47
G52 VSS[251] VSS[351] AT12
AF39 VSS[252] VSS[352] AM6
H16 VSS[253] VSS[353] AT13
H20 VSS[254] VSS[354] AM5
H30 VSS[255] VSS[355] AK45
A H34 VSS[256] VSS[356] AK39 A
H38 VSS[257] VSS[366] AV14
H42 VSS[258]

REV1.0
IBEXPEAK-M_FCBGA107 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title
9/14 Change PN of U60 from SA00002KV0L to SA00003NI20 PCH (9/9) VSS & PCH XDP Port
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics 1.0
Date: Friday, February 26, 2010 Sheet 21 of 48
5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT

+LCDVDD
+3VALW +3VS 11/10 Change U7 from @ to mount
9/14 Change power net from +3V
to +3VALW W=60mils 12/31 Change U7,R302 from mount to @

1
R296 Change R298,R300 from @ to mount

1
+3VS
1
300_0603_5% R297 C217
100K_0402_5% U7

6 2

1
4.7U_0603_6.3V6K NC7SZ14P5X_NL_SC70-5
2 @

NC
2
Q1A 2 4 DPST_PWM_1 1 2 INVTPWM
<16> DPST_PWM A Y

3
S
R299 R298 0_0402_5%

G
D
G D
2 LVDS_OE# 2 1 2 Q18 01/07 Change Q18 from
AO3413_SOT23-3

3
2N7002DW-T/R7_SOT363-6
1 100K_0402_5% 1 D SB923010020 to SB934130000

1
3
C218 +LCDVDD
W=60mils
1 2
0.1U_0402_16V4Z 12/05 Change Q18 from R300 0_0402_5%
5 2
<16> PCH_ENVDD SB934130000 to SB923010020
Q1B 1 1
1

C219 C220 INVT_PWM 1 @ 2 INVTPWM

4
<33> INVT_PWM
2N7002DW-T/R7_SOT363-6 @ R302 0_0402_5%
R301 4.7U_0603_6.3V6K 0.1U_0402_16V4Z

1
100K_0402_5% 2 2
01/15 Change Q1 from 11/09 Change U7,R298 from mount to @ R303
2

SB00000AR00 to SB00000D900 Change R302 from @ to mount 10K_0402_5%

03/05 Change Q1,Q2 from SB00000D900 to SB00000DH00 (MFG Recommend) @

2
PCH_ENVDD C533 1 100P_0402_50V8J
11/09 Change C218 from 0.047uf to 0.1uF
2
Change R299 from 1kohm to 100kohm
Change C219 from mount to @
11/16 Reserve C533 for avoiding switching noise (Follow KHLBX)
11/23 Change C533 from @ to mount

11/09 Delete R304(@) 11/10 Delete R305

+INVPWR_B+ B+
W=60mils +LCDVDD
BKOFF# W=60mils
<33> BKOFF#
L12 2 1
C R306 1 C
2 10K_0402_5% FBMA-L11-201209-221LMA30T_0805 1 1
1 1 C222 C223
9/1 Del D5/R22(BKOFF# not need to pull high) C221 C224
680P_0402_50V7K 68P_0402_50V8J 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2
2 2
+3VS
ESD PROTECT
CLOSE TO JLVDS1
R307 1 2 2.2K_0402_5% PCH_LCD_CLK

R308 1 2 2.2K_0402_5% PCH_LCD_DATA

L13 +3VS
USB20_N2 1 2 USB20_CMOS_N2
1 2 INVTPWM 1 2
1 C225 220P_0402_50V7K
USB20_P2 4 3 USB20_CMOS_P2 C226 BKOFF# 1 2
4 3 C227 220P_0402_50V7K
WCM2012F2S-900T04_0805 0.1U_0402_16V4Z
@ 2

9/14 Add By Vivian(EMI suggest)

LCD/PANEL BD. Conn.
D6 <EMI> +5VALW Copy NAV50 Conn.
USB20_CMOS_N2 6 3
B CH3 CH2 KB_LIGHT# JLVDS1 B

W=60mils +LCDVDD 1
2
3

+3VS 5
Vp Vn
2 W=40mils +3VS 3
D7
@ PCH_LCD_CLK 4
<16> PCH_LCD_CLK 5
PESD5V0U2BT 3P C/C SOT23 ESD PCH_LCD_DATA
USB20_CMOS_P2 <16> PCH_LCD_DATA PCH_TXOUT0- 6
4 1 <16> PCH_TXOUT0-
CH4 CH1 PCH_TXOUT0+ 7
1

<16> PCH_TXOUT0+ 8
CM1293-04SO_SOT23-6
@ PCH_TXOUT1- 9
11/09 Change D7 from mount to @ <16> PCH_TXOUT1- PCH_TXOUT1+ 10
<16> PCH_TXOUT1+ 11
PCH_TXOUT2- 12
<16> PCH_TXOUT2- PCH_TXOUT2+ 13
<16> PCH_TXOUT2+ 14
PCH_TXCLK- 15
<16> PCH_TXCLK- PCH_TXCLK+ 16
<16> PCH_TXCLK+ +5V_CAM_LV 17
W=20mils +5VS R310 2 1 0_0603_5%
R311 0_0402_5% USB20_CMOS_N2 18
<17> USB20_N2 1 2
R312 0_0402_5% USB20_CMOS_P2 19
<17> USB20_P2 1 2
R309 300_0402_5% +5VALW_LV 20
W=20mils +5VALW 1 2 21
<33> KB_LIGHT# INVTPWM 22
BKOFF# 23
24
25
26
27
28
+INVPWR_B+ 29
W=60mils 30
A ACES_88341-3000B001 A
CONN@

11/09 Change JLVDS1 and pin definition

12/04 Change JLVDS1 and pin definition
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics1.0
Date: Tuesday, March 09, 2010 Sheet 22 of 48
5 4 3 2 1
 A B C D E

10/29 Delete L14,L15,L16 (For layout spacing)

CRT Connector +5VS

W=40mils
+R_CRT_VCC +CRT_VCC

D11 F1 W=40mils
2 1 1 2

RB491D_SC59-3 1.1A_6V_SMD1812P110TF
1
C228
1 0.1U_0402_16V4Z 1
PCH_CRT_R 2
<16> PCH_CRT_R PCH_CRT_G
<16> PCH_CRT_G PCH_CRT_B
<16> PCH_CRT_B 10/29 Delete D8,D9,D10 (For layout spacing) Copy KAV60
PCH_CRT_R L18 1 2 FCM2012CF-800T06_2P CRT_R_2 JCRT1
6
11
PCH_CRT_G L19 1 2 FCM2012CF-800T06_2P CRT_G_2 1
7
12
PCH_CRT_B L22 1 2 FCM2012CF-800T06_2P CRT_B_2 2
8 G 16
13 17
1

G
1 1 1 1 1 1 3
R313 R314 R315 C232 C233 C234 9
C235 C236 C237 14
150_0402_1% 150_0402_1% 15P_0402_50V8J 15P_0402_50V8J 15P_0402_50V8J 4
2 2 2 2 2 2
10
2

22P_0402_50V8J 22P_0402_50V8J 15
1 5
150_0402_1% 22P_0402_50V8J Change to 12pf for DIS C238
SUYIN_070546FR015S290ZR
100P_0402_50V8J CONN@
2

1 2 CRT_HSYNC_2
+CRT_VCC L23 BLM18AG121SN1D_2P DSUB_12

C239 1 2 0.1U_0402_16V4Z R317 2 1 10K_0402_5% 1 2 CRT_VSYNC_2 1

L24 BLM18AG121SN1D_2P 1 1
2 2
5

U8 C240 C241 DSUB_15 0909 Change JCRT1 symbol from KAVAA

10P_0402_50V8J 10P_0402_50V8J C242 2
OE#
P

PCH_CRT_HSYNC 2 CRT_HSYNC_R R540 1 CRT_HSYNC_1 2 2

<16> PCH_CRT_HSYNC A Y 4 2 39_0402_5% 68P_0402_50V8J 1
G

TC7SET125FUF SC70 5P BUFFER 11/11 Correct L23,L24 footprint C243

68P_0402_50V8J
3

2
+CRT_VCC

C244 1 2 0.1U_0402_16V4Z 11/10 Add C518,C519 (EMI Recommend)

5

U9
+3VS
OE#
P

PCH_CRT_VSYNC 2 4 CRT_VSYNC_R R541 1 2 39_0402_5% CRT_VSYNC_1

<16> PCH_CRT_VSYNC A Y
G

TC7SET125FUF SC70 5P BUFFER

3

1 1
C518 C519
11/03 Change U8,U9 from SA411250130 to SA00000RZ00
680P_0402_50V7K 680P_0402_50V7K
2 2
+CRT_VCC

PCH DDC PU 2.2K

on Page 17
+3VS

1
R538 R539
3 2.2K_0402_5% 2.2K_0402_5% 3

2
2
Q2A

PCH_CRT_DATA 1 6 DSUB_12
<16> PCH_CRT_DATA
2N7002DW-T/R7_SOT363-6

5
Q2B

PCH_CRT_CLK 4 3 DSUB_15
<16> PCH_CRT_CLK
2N7002DW-T/R7_SOT363-6

01/15 Change Q2 from

SB00000AR00 to SB00000D900
03/05 Change Q1,Q2 from SB00000D900 to SB00000DH00 (MFG Recommend)
9/10 Change from 2N7002E-T1-E3_SOT23-3
to 2N7002DW-T/R7_SOT363-6
Michael

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics 1.0
Date: Tuesday, March 09, 2010 Sheet 23 of 48
A B C D E
 5 4 3 2 1

+3VS 10/22 Change R335(1442@) from 3.3kohm to 3.4kohm (Vendor Recommend)

+3VS

Copy NTUC0

1
R335 R335

1
R318
@
4.7K_0402_5% R319 U10 10/23 Change R327 from 7318C@ from @
0_0402_5%

2
Change R332 from @ to 7318C@

2
HDMI_OE# +3VS 3.4K_0402_1% 1.2K_0402_1%
25 OE# (Vendor Recommend) 1442@ 7318C@

1
D +3VS
VCC 2
HDMI_DETECT 2 R322 1 0_0402_5% 2 @ HDMICLK_R 28 11 1 1 1 1
G R323 SCL_SINK VCC
15
VCC

1
D S Q19 0_0402_5% HDMIDAT_R C245 C246 C247 C248 D
29 21

3
SDA_SINK VCC

1
SSM3K7002FU_SC70-3 26 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z

2
R325 R326 VCC 2 2 2 2
VCC 33
7318C@ 4.7K_0402_5% HDMI_DETECT 30 40
33K_0402_5% HPD_SINK VCC
46

2
VCC R327 1 @
32 2 4.7K_0402_5% +3VS
2 DDC_EN R328 1 8101@ 2 4.7K_0402_5% 10/23 Delete R324(7318C@),R329(7318C@) for Calpella

1
+3VS +3VS
@ R331 1 7318C@ 2 4.7K_0402_5% 34 4 R332 1 1442@ 2 4.7K_0402_5% 12/22 Change R332 from 7318C@ to 1442@
R330 R333 1 7318C@ 2 4.7K_0402_5% CFG0 PC1 R334 1 @
35 CFG1 PC0 3 2 4.7K_0402_5%
0_0402_5% internal pull down

1
2
6 R335 1 8101@ 2 430_0402_1%
REXT

2
R336 R337
R338 @ 7 PCH_DPB_HPD 2.2K_0402_5% 2.2K_0402_5%
HPD# PCH_DPB_HPD <16>
1442@ R339

2
4.7K_0402_5% 4.7K_0402_5% 8 SDVO_SDATA
SDA SDVO_SDATA <16>

1
9 SDVO_SCLK
SCL SDVO_SCLK <16>

10 R340 1 @ 2 4.7K_0402_5% +3VS

RT_EN#
12/22 Change R338 from @ to 1442@

1
48 13 HDMI_TX0+ R341
<16> PCH_TMDS_D0 IN_D4+ OUT_D4+ HDMI_TX0- HDMI_TX2+ HDMI_TX2+_CONN
47 14 @ R342 1 1442@ 2 0_0402_5%
<16> PCH_TMDS_D0# IN_D4- OUT_D4- HDMI_TX2- HDMI_TX2-_CONN
4.7K_0402_5% R343 1 1442@ 2 0_0402_5%
45 16 HDMI_TX2+ HDMI_TX1+ R344 1 1442@ 2 0_0402_5% HDMI_TX1+_CONN

2
<16> PCH_TMDS_D2 IN_D3+ OUT_D3+ HDMI_TX2- HDMI_TX1- HDMI_TX1-_CONN
44 17 R345 1 1442@ 2 0_0402_5%
<16> PCH_TMDS_D2# IN_D3- OUT_D3- HDMI_TX0+ HDMI_TX0+_CONN
R346 1 1442@ 2 0_0402_5%
42 19 HDMI_TX1+ HDMI_TX0- R347 1 1442@ 2 0_0402_5% HDMI_TX0-_CONN
<16> PCH_TMDS_D1 IN_D2+ OUT_D2+ HDMI_TX1- HDMI_CLK+ HDMI_CLK+_CONN
41 20 R348 1 1442@ 2 0_0402_5%
C <16> PCH_TMDS_D1# IN_D2- OUT_D2- HDMI_CLK- HDMI_CLK-_CONN C
R349 1 1442@ 2 0_0402_5%
39 22 HDMI_CLK+
<16> PCH_TMDS_CK IN_D1+ OUT_D1+ HDMI_CLK-
38 23
<16> PCH_TMDS_CK# IN_D1- OUT_D1- 06/25 Mirror L8,L9,L10,L11
HDMI_TX2+ 1 WCM-2012-900T_4P HDMI_TX2+_CONN
1 2 2

1
GND 1
5
R651 GND HDMI_TX2- HDMI_TX2-_CONN
12 4 3
2.2K_0402_5% GND 4L25 8101@ 3
GND 18
24

2
GND
27
GND HDMI_TX1+ HDMI_TX1+_CONN
31 1 WCM-2012-900T_4P 2
GND 1 2
36
GND
01/20 Add R651 (Asmedia Recommend) GND 37
HDMI_TX1- HDMI_TX1-_CONN
43 4 3
GND 4L26 8101@ 3
49
PAD
PS8101QFN48G QFN 48P
8101@ HDMI_TX0+ 1 WCM-2012-900T_4P HDMI_TX0+_CONN
1 2 2

HDMI_TX0- 4 3 HDMI_TX0-_CONN
4L27 8101@ 3
11/09 Delete R350(@)
U10 U10
+5VS
HDMI_CLK+ 1 WCM-2012-900T_4P HDMI_CLK+_CONN
1 2 2

HDMI_CLK- 4 3 HDMI_CLK-_CONN
4L28 8101@ 3

2
ASM1442_QFN48_7X7 CH7318C
1442@ 7318C@
B D12 L25 L26 L27 L28 B

11/17 Change net name from +5VS to +5VS_HDMI RB491D_SC59-3

1
+5VS_HDMI_D 11/17 Add F2 (Safety Recommend)
+5VS_HDMI

1.1A_6VDC_FUSE 1 F2
1
WCM-2012-900T_4P WCM-2012-900T_4P WCM-2012-900T_4P WCM-2012-900T_4P
C249 7318C@ 7318C@ 7318C@ 7318C@
0.1U_0402_16V4Z
2
Copy KHLB0
2
2

R351 R352
JHDMI1
HDMI_DETECT 19
2.2K_0402_5% 2.2K_0402_5% +5VS_HDMI HP_DET +5VS
18
1

+5V
17
HDMIDAT_R DDC/CEC_GND
16
SDA

2
HDMICLK_R 15
SCL
14
Reserved
13
HDMI_CLK-_CONN CEC
12
CK- GND
20 11/09 Delete R353
11 21
HDMI_CLK+_CONN CK_shield GND @
10 22

1
HDMI_TX0-_CONN CK+ GND HDMI_DETECT D13
9 23
D0- GND BAT54S-7-F_SOT23-3
8
HDMI_TX0+_CONN D0_shield
7 D0+
HDMI_TX1-_CONN 6
D1-
5
HDMI_TX1+_CONN D1_shield
4
HDMI_TX2-_CONN D1+
3
D2-
2
HDMI_TX2+_CONN D2_shield
1 D2+
A A
TYCO_1775040-6
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/03/20 Title
HDMI Level Shifter & Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics
Date: Tuesday, March 09, 2010 Sheet 24 of 48
5 4 3 2 1
 A B C D E F G H

SATA HDD Conn.

HDD
Copy NIM00
JHDD1

1
SATA_PTX_DRX_P0 C250 1 SATA_PTX_C_DRX_P0 GND
<13> SATA_PTX_DRX_P0 2 0.01U_0402_16V7K 2 A+
SATA_PTX_DRX_N0 C251 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 3
<13> SATA_PTX_DRX_N0 A-
4
1 SATA_DTX_C_PRX_N0 C252 1 SATA_DTX_PRX_N0 GND 1
2 0.01U_0402_16V7K 5
<13> SATA_DTX_C_PRX_N0 SATA_DTX_C_PRX_P0 C253 1 SATA_DTX_PRX_P0 B-
2 0.01U_0402_16V7K 6
<13> SATA_DTX_C_PRX_P0 B+
7 GND

+3VS 8
V33
9 V33
10 V33
11
GND
12 GND
13
R354 1 +5VS_HDD GND
+5VS 2 0_0805_5% 14
V5
15
+5VS_HDD V5
16 V5
17 GND
18 DAS/DSS
19 GND
0.1U_0402_16V4Z 10U_0805_10V4Z 20 23
V12 GND
21 24
V12 GND
1 1 1 1 22 V12
C254 C255 C256 C257
SUYIN_127043FR022G196ZR
2 2 2 2 CONN@

1000P_0402_50V7K 1U_0402_6.3V4Z
11/11 Add GND net on JHDD1.23 and JHDD1.24

2 2

11/11 Correct Q20 footprint

+3VS
01/07 Change Q20 from
Copy KIUE0 +3VS_GEN
SB923010020 to SB934130000
Q20 GSENSOR@
AO3413_SOT23-3
R355
1 2 +3VS_ITES_R 1 3

S
G-Sensor C258
1 1 1
C260
47_0402_5%
GSENSOR@
C261

G
2
GSENSOR@ GSENSOR@ 1 2 1
0.1U_0402_16V4Z 10U_0805_6.3V6M C262

1
2 2 2 0.1U_0402_16V4Z GSENSOR@
GSENSOR@ R356 1U_0603_10V4Z
GSENSOR@ 2
100K_0402_5%
C259 2
GSENSOR@
1U_0603_10V4Z
<33> EC_GENPD
1

3 R357 3
@
10K_0402_5%
U13
2

GSENSOR@
2 12 X R358 1 2 0_0402_5% VOUTX
<33> G_SELFTEST ST Xout VOUTX <33>
10 Y R359 1 2 0_0402_5% VOUTY
Yout GSENSOR@ VOUTY <33>
1

14
R360 Vs
15
GSENSOR@ Vs
1
100K_0402_5% NC
4
NC Z R361 1 @ VOUTZ
8 2 0_0402_5%
2

NC VOUTZ <33>
3 COM NC 9
5 11
COM NC
6 13
COM NC
7 16
COM NC

S IC LIS244ALTR LGA 16P G-SENSOR 1 1 1

GSENSOR@ C263 C265
@ GSENSOR@
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2

C264
GSENSOR@
0.1U_0402_16V4Z

4 4

12/17 Change C258,C259,C260,R355,Q20,C261,R356,C262,R360,R358,R359,C264,C265,U13 from mount to GSENSOR@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title
HDD Conn/G-Sensor
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics
Date: Tuesday, March 09, 2010 Sheet 25 of 48
A B C D E F G H
 5 4 3 2 1

+1.7_VDDCT
+1.7_LX
LAN Power Circuit & Refer NTUC0
+1.7_VDDCT 1 2 +1.7_LX

1000P_0402_50V7K
10U_0805_10V4Z

0.1U_0402_16V4Z
L33 4.7UH_SIA4012-4R7M_20%
+3V_LAN
1 1 1 Layout note : C266,C267,C268&L33 Close to Pin40

C266

C267

C268
R362 1
60mil
+3VALW @ 2 0_0603_5% Note:
1000P_0402_50V7K
1U_0402_6.3V4Z
1 1 1 1 1
2 2 2 Place Close to LAN chip
D C271 C272 C493 D
C270
L33 DCR< 0.15 ohm
C269 10U_0805_10V4Z Rate current of L33 > 1A
2 2 2 2 2

D
3 1 10U_0805_10V4Z 0.1U_0402_16V4Z

Q21

G
Place Close to Pin 1
2
01/07 Change Q21 from AO3413_SOT23-3

SB923010020 to SB934130000 Refer CRB

R363 1 2 10K_0402_5%
EN_WOL# <33>
2
C273

0.1U_0402_16V4Z
1
10/22 Remove R364

01/15 Change R362 from mount to @

Change Q21,R363,C273 from @ to mount
10/100_LINK_LED 2
R365 1
LED2_CKR# 1 2 1000_LINK_LED 3 LAN_LINK# <27>
0_0402_5%
D14
CHP202UPT_SOT323-3

C C

R366 no overclocking
5.1K_0402_5% PD 5.1K
1 2 +3V_LAN
U14

C274 1 2 .1U_0402_16V7K PCIE_DTX_PRX_N1 29 38 LAN_ACTIVITY# R371 2 @ 1 4.7K_0402_5% LAN_CLKREQ#

<14> PCIE_DTX_C_PRX_N1 TX_N LED_0 10/100_LINK_LED LAN_ACTIVITY# <27>
C275 1 2 .1U_0402_16V7K PCIE_DTX_PRX_P1 30
Atheros LED_1
39
23 LED2_CKR#
<14> PCIE_DTX_C_PRX_P1 TX_P 8151-AL1A LED_2
36 RX_N
<14> PCIE_PTX_C_DRX_N1 MIDI0-
12 MIDI0- <27>
TRXN0 MIDI0+
<14> PCIE_PTX_C_DRX_P1 35 11 MIDI0+ <27>
RX_P TRXP0 MIDI1-
TRXN1 15 MIDI1- <27>
R369 2 1 0_0402_5% CLK_PCIE_LAN#_C 32 14 MIDI1+ MIDI1+ <27>
<14> CLK_PCIE_LAN# R370 2 CLK_PCIE_LAN_C REFCLK_N TRXP1 MIDI2-
1 0_0402_5% 33 REFCLK_P TRXN2 18 MIDI2- <27>
<14> CLK_PCIE_LAN MIDI2+
17 MIDI2+ <27>
PLT_RST_BUF# TRXP2 MIDI3-
<17,32,37> PLT_RST_BUF#
2
PERST# TRXN3
21
MIDI3+
MIDI3- <27> 10/22 Change R376 from mount to @
20 MIDI3+ <27>
R543 1 PCH_PCIE_WAKE#_R TRXP3
2 0_0402_5% 3 11/02 Change R373 from mount to @
<15,32,37> PCH_PCIE_WAKE# WAKE# R372
<33> PCH_PCIE_WAKE#_R LAN_RBIAS
25 10 1 2 2.37K_0402_1% 11/02 Delete Q3(@),R375(@),R377(@)
SMCLK RBIAS
10/22 Change off-page 26 SMDATA
direction of LAN_TEST_RST +3V_LAN
11/09 Delete R373(@),R376(@)
+3V_LAN R374 2 @ 1 4.7K_0402_5% 28 1 +3V_LAN
TEST_RST VDD33 +1.7_LX
PCH_PCIE_WAKE# and 27
TESTMODE
PCH_PCIE_WAKE#_R 11/02 Change R374 from mount to @ +1.7_LX +1.7_VDDCT
LX 40
B LAN_XTALO B
7 XTLO
LAN_XTALI 8
XTLI +1.7_VDDCT
5
VDDCT
1
LAN_CLKREQ# 4
<14> LAN_CLKREQ# CLKREQ# +1.1_DVDDL C278 1
DVDDL 24 2 0.1U_0402_16V4Z C279
37 0.1U_0402_16V4Z
DVDDL_REG C280 1 2
13 2 1U_0402_6.3V4Z
AVDDL C281 1
19 2 0.1U_0402_16V4Z
AVDDL
31
AVDDL AVDDH
16 Near Pin37
+1.1_AVDDL
34
6
AVDDL AVDDH
22
9 +2.7_AVDDH
Place Close to LAN chip
AVDDL_REG AVDDH_REG
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1 1 49.9_0402_1%
41 MIDI0+ R378 1 2 1 2 C292 1000P_0402_50V7K
GND 49.9_0402_1%
C282

C283

C284

C285

C286

C287

C288

C289

C290

C291
AR8151-AL1A_QFN40_5X5 MIDI0- R379 1 2 1 2 C293 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2 49.9_0402_1%
MIDI1+ R380 1 2 1 2 C294 1000P_0402_50V7K
49.9_0402_1%
MIDI1- R381 1 2 1 2 C295 0.1U_0402_16V4Z
Layout note : C286&C287 Close to Pin6 Layout note : C288&C289 Close to Pin9 49.9_0402_1%
MIDI2+ R382 1 2 1 2 C296 1000P_0402_50V7K
C282 Close to Pin13 C290 Close to Pin16 49.9_0402_1%
MIDI2- R383 1 2 1 2 C297 0.1U_0402_16V4Z
C283 Close to Pin19 C291 Close to Pin22 49.9_0402_1%
C284 Close to Pin31 MIDI3+ R384 1 2 1 2 C298 1000P_0402_50V7K
49.9_0402_1%
C285 Close to Pin34 MIDI3- R385 1 2 1 2 C299 0.1U_0402_16V4Z

LAN_XTALI
A A
LAN_XTALO
Y3
1 2
27P_0402_50V8J

25MHZ_20PF_7A25000012
27P_0402_50V8J

1 1
C276

C277

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date Deciphered Date 2010/10/10 Title
2 2 2009/10/10
LAN AR8151
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics
Date: Tuesday, March 09, 2010 Sheet 26 of 48
5 4 3 2 1
 5 4 3 2 1

Copy NIMUA
+1.7_VDDCT R386
0_0603_5%
1 2 +1.7_VDDCT_R

C300
TAIMAG: SP050004M00
Layout note : C300 Close to R386 BOTHHAND: NA
1U_0402_6.3V4Z
2 1 T11
10/28 Swap transformer signal Close to R7 10/28 Swap transformer signal
1 24 MCT3
MIDI3- TCT1 MCT1 RJ45_MIDI3-
2 23
<26> MIDI3- MIDI3+ TD1+ MX1+ RJ45_MIDI3+
<26> MIDI3+ 3 22
TD1- MX1-
D D
4 21 MCT2
MIDI2- TCT2 MCT2 RJ45_MIDI2-
5 20
<26> MIDI2- MIDI2+ TD2+ MX2+ RJ45_MIDI2+
6 19
<26> MIDI2+ TD2- MX2-
7 18 MCT1
MIDI1- TCT3 MCT3 RJ45_MIDI1-
8 17
<26> MIDI1- MIDI1+ TD3+ MX3+ RJ45_MIDI1+
9 16
<26> MIDI1+ TD3- MX3- C309

MIDI0-
10
11
TCT4 MCT4
15
14
MCT0
RJ45_MIDI0-
2 1
Copy NAV50
<26> MIDI0- MIDI0+ TD4+ MX4+ RJ45_MIDI0+ 470P_0402_50V7K JLAN1
12 13
<26> MIDI0+ TD4- MX4- R391 1 2 510_0402_5% 11
Yellow LED+

1 75_0402_1%

1 75_0402_1%

1 75_0402_1%

1 75_0402_1%
<26> LAN_ACTIVITY#
12
350UH_IH-037-2 Yellow LED-
15
RJ45_MIDI3- SHLD1
8
1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
PR4-
13
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
RJ45_MIDI3+ DETECT PIN1
7
PR4+
1 1 1 1 1 1 1 1 RJ45_MIDI1- 6
PR2- LANGND
RJ45_MIDI2-
C301

C302

C303

C304

C305

C306

C307

C308
5
PR3-

2
2 2 2 2 2 2 2 2 RJ45_MIDI2+ 4
PR3+

R387

R388

R389

R390
RJ45_MIDI1+ 3
PR2+
near Pin1 near Pin4 near Pin7 near Pin10
RJ45_MIDI0- 2
RJ45_GND PR1-
Place close to TCT pin
40mil RJ45_MIDI0+ 1
PR1+
14
R392 1 SHLD1
+3V_LAN 2 510_0402_5% 9
Green LED+
10
Green LED-
SANTA_130452-3

C C311 C
1000P_1206_2KV7K 40mil
RJ45_GND 1 2 LANGND

470P_0402_50V7K

470P_0402_50V7K
10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
R394
2 1 LAN_LINK# <26>
1 1 2 1 1 2

C496

C497

C494

C312

C495

C498
0_0402_5%

1 2 2 1 2 2 1
C310

470P_0402_50V7K
2

Follow CRB

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN Magnetic & RJ45
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics
Date: Tuesday, March 09, 2010 Sheet 27 of 48
5 4 3 2 1
 5 4 3 2 1

CR_REFE must far away from

48MHz clock trace.
Place CR1,RR2 close to U15 Pin1
11/04 Change CR1 from SE071101J1M to SE071101J80
11/09 Delete RR1(@) CR1 1 2 100P_0402_50V8J
Pin1 and pin6 of U15 trace width = 20mil U15
RR2 2 1 6.19K_0402_1% CR_REFE 1 11/09 Delete RR4
RR3 1 REFE
+3VS 2 0_0603_5% GPIO0 17
D
<17> USB20_N5 2 DM D
40mil 40mil 3 24 CLK_48M
<17> USB20_P5 DP CLK_IN CLK_48M <12>
+3VS_CR 4 23 XD_D7
+VCC_3IN1 3V3_IN XD_D7
+VCC_3IN1 5 CARD_3V3
+V18_CR 6 22 XD_D6_MS_BS
V18 SP14 XD_D5_SD_D2_MS_D5
40mil +V18_CR : 20mil XD_CD# SP13 21
XD_D4_SD_D3_MS_D1
1 1 1 2 7 XD_CD# SP12 20
CR2 CR3 CR4 CR5 19 XD_D3_SD_D4_MS_D4
XD_RDY_SD_W P_MS_CLK_R RR5 1 XD_RDY_SD_W P_MS_CLK SP11 XD_D2_SD_CMD
2 8 SP1 SP10 18
0.1U_0402_16V4Z 10U_0805_10V6K 0_0402_5% XD_RE#_MS_INS# 9 16 XD_D1_SD_D5_MS_D0 RR6
2 2 2 1 XD_CE#_SD_D1 SP2 SP9 XD_D0_SD_CLK_MS_D2 XD_D0_SD_CLK_MS_D2_R
10 SP3 SP8 15 1 2

EPAD
0.1U_0402_16V4Z 1U_0402_6.3V6K XD_CLE_SD_D0_MS_D7 11 14 XD_W P_SD_D6_MS_D6
XD_ALE_SD_D7_MS_D3 SP4 SP7 XD_W E#_SD_CD# 0_0402_5%
Place CR2,CR3 close to U15 Pin4 12 SP5 SP6 13
Place CR4,CR5 close to U15 Pin5,6 RTS5138-GR_QFN24_4X4

25
Ground pad must have 4 via
Close to U15 pin24
no more than 2 via on all signal trace CLK_48M

Pin8 and Pin15 Keep trace routing lengths as short as possible,

Avoid via and layer changes

1
RR7

C 22_0402_5% C

2
1
CR6

10P_0402_50V8J
2

20mil 20mil 12/22 Mount RR7,CR6

+VCC_3IN1 +VCC_3IN1

7 in 1 Card Reader
Copy NCQF0
JCR1
22 XD-VCC SD4-VDD 11
MS9-VCC 18
XD_D0_SD_CLK_MS_D2 30
XD_D1_SD_D5_MS_D0 29
XD10-D0
9 XD_D0_SD_CLK_MS_D2 Close to JCR1
XD_D2_SD_CMD XD11-D1 SD5-CLK XD_CLE_SD_D0_MS_D7
28 XD12-D2 SD7-DAT0 4
XD_D3_SD_D4_MS_D4 27 3 XD_CE#_SD_D1 1 1
XD_D4_SD_D3_MS_D1 XD13-D3 SD8-DAT1 XD_D5_SD_D2_MS_D5 CR8 CR7
26 XD14-D4 SD9-DAT2 21
XD_D5_SD_D2_MS_D5 25 19 XD_D4_SD_D3_MS_D1
XD_D6_MS_BS 24
XD15-D5 SD1-DAT3
16 XD_D2_SD_CMD 0.1U_0402_16V4Z 0.1U_0402_16V4Z EMI reserved Close to JCR1
B XD_D7 XD16-D6 SD2-CMD XD_W E#_SD_CD# 2 2 B
23 XD17-D7 SD-CD 1
2 XD_RDY_SD_W P_MS_CLK
XD_W E#_SD_CD# SD-WP XD_D0_SD_CLK_MS_D2_R
33 XD07-WE
XD_W P_SD_D6_MS_D6 32 6
XD_ALE_SD_D7_MS_D3 XD08-WP SD6-VSS XD_RDY_SD_W P_MS_CLK_R
34 XD06-ALE SD3-VSS 13
XD_CD# 39 XD01-CD

1
XD_RDY_SD_W P_MS_CLK 38
XD_RE#_MS_INS# XD02-R/B RR8 RR9
37 XD03-RE
XD_CE#_SD_D1 36 17 XD_RDY_SD_W P_MS_CLK @ @
XD_CLE_SD_D0_MS_D7 XD04-CE MS8-SCLK XD_D1_SD_D5_MS_D0 10_0402_5% 10_0402_5%
35 XD05-CLE MS4-DATA0 10
8 XD_D4_SD_D3_MS_D1

2
MS3-DATA1 XD_D0_SD_CLK_MS_D2
31 XD GND MS5-DATA2 12
40 15 XD_ALE_SD_D7_MS_D3 1 1
XD GND MS7-DATA3 XD_RE#_MS_INS# CR9 CR10
MS6-INS 14
7 XD_D6_MS_BS @ @
MS2-BS 10P_0402_50V8J 10P_0402_50V8J
MS1-VSS 5
2 2
41 SD CD/WP GND MS10-VSS 20
42 SD CD/WP GND
T-SOL_144-1300302600_NR
CONN@
1

1
RR10 CR11
@
100K_0402_5% 0.1U_0402_16V4Z
2
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Card Reader/7-IN-1 Socket
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics
Date: Tuesday, March 09, 2010 Sheet 28 of 48
5 4 3 2 1
 5 4 3 2 1

10/29 Follow NTUC0 J3

2 1
2 1
C332
JUMP_43X39
R414 1 2 47K_0402_5% 1 2 MONO_IN
<33> BEEP# +5VAMP
U16
R415 1 0.1U_0402_16V4Z PLO @
(output = 300 mA)
2 47K_0402_5% +5VS L34 1 2 0.1U_0402_16V4Z 1 IN
<13> PCH_SPKR FBMA-L11-201209-221LMA30T_0805 5 4.75V
OUT +VDDA

1
1 1
C329
1
C330
2 GND PLO C331
R416 C328 3 4 1 2 @
D 10K_0402_5% 0.1U_0402_16V4Z SHDN BYP D
0.1U_0402_16V4Z
2 2 2 G9191-475T1U_SOT23-5

2
2.2U_0603_6.3V6K
'9718LW

10/29 Delete C333,C334,D15,Q22,R411,R412,R413

Change R414,R415 from 560ohm to 47kohm
Change C332,C328 from 1uF to 0.1uF

+5VS
W=40mil
1 1
C335 C336
10U_0805_10V4Z 0.1U_0402_16V4Z
+1.5VS_3VS_HDIO 2 2

+3VS L35 1 2 10U_0805_10V4Z

0_0603_5% 1 1
+5VS
+1.5VS L50 1 @ 2 C337 C338 W=40mil
0_0603_5%
2 2
change to +3vs 1 1
0.1U_0402_16V4Z
C339 C340
11/09 Change L35,L36,L50 from SM010015410 to SD013000080 10U_0805_10V4Z 0.1U_0402_16V4Z
C 2 2 C

+3VS +3VS_HD +VDDA

20mil
1 2 10U_0805_10V4Z +HD_AVDD
L36 0_0603_5% 1 1 1
40mil
L37
100P_0402_50V8J 0.1U_0402_16V4Z 2 1
C341 C342 C343 1 1 1 1 FBMA-L11-160808-800LMT_0603
@ C344 C345 C346 C347
2 2 2
100P_0402_50V8J 0.1U_0402_16V4Z @
11/11 Correct L37 footprint HDA_BITCLK_AUDIO_R 1 2 1 2
2 2 2 2 R418 @

39

46

25

38
1

9
0.1U_0402_16V4Z 10U_0805_10V4Z 22_0402_5% C348 @
U17 10P_0402_50V8J

DVDD_IO

PVDD1

PVDD2

AVDD1

AVDD2
DVDD
23 40 SPKL+
LINE1_L SPK_OUT_L+ SPKL- SPKL+ <30>
24 LINE1_R SPK_OUT_L- 41
SPKL- <30>
11/10 Change R465,R466 from SE053475Z80 to SE107475M80 (Realtek Recommend) 14 45 SPKR+
LINE2_L SPK_OUT_R+ SPKR- SPKR+ <30>
15 44
LINE2_R SPK_OUT_R- SPKR- <30>
C465 1 2 4.7U_0603_6.3V6K MIC1_L 21 32 HP_LEFT +MIC1_VREFO_R +MIC1_VREFO_L
<30> MIC1_L_R C466 1 MIC1_R MIC1_L HP_OUT_L HP_RIGHT HP_LEFT <30>
2 4.7U_0603_6.3V6K 22 33
<30> MIC1_R_R MIC1_R HP_OUT_R HP_RIGHT <30>
16 C349 C350
MIC2_L @ @
17
MIC2_R 0.1U_0402_16V4Z 0.1U_0402_16V4Z
02/26 Change R422 from SD028000080 to SM01000CY00 SYNC
10
HDA_SYNC_AUDIO <13>
01/07 Change C351.2 from R422.2 to R422.1 R420 1 2 0_0402_5% DMIC_DATA 2 6 HDA_BITCLK_AUDIO_R R421 1 2 0_0402_5%
B <30> DMIC_DATA_R GPIO0/DMIC_DATA BCLK HDA_BITCLK_AUDIO <13> B
1 2 DMIC_CLK 3 DGGLWIRU(0,
<30> DMIC_CLK_R R422 FBMA-10-100505-301T 0402 GPIO1/DMIC_CLK HDA_SDOUT_AUDIO_R R423 1
1 2 5 2 0_0402_5%
C351 @ 10P_0402_50V8J SDATA_OUT HDA_SDOUT_AUDIO <13>
R424 1 2 0_0402_5% 4 8 HDA_SDIN0_R R425 1 2 33_0402_5%
<33> EC_MUTE# PD# SDATA_IN HDA_SDIN0 <13>
01/07 Add R648(@) to +HD_AVDD (Realtek Recommend) +HD_AVDD R648 1 @ 2 10K_0402_5%
HDA_RST#_AUDIO 11 47 EAPD R426 1 2 0_0402_5%
<13> HDA_RST#_AUDIO RESET# EAPD
DGGLW C499 1 2 @ 0.01U_0402_16V7K EC_EAPD <33>
48
SENSE_A MONO_IN SPDIFO
<30> HP_PLUG# 2 1 12
R427 39.2K_0402_1% PCBEEP
1 2 20
C352 @ 100P_0402_50V8J MONO_OUT
<30> MIC_PLUG# 1
R428
2
20K_0402_1% SENSE_A
11/05 Add net name : CODEC_LDO_CAP,+CODEC_VREF,+CODEC_JDREF,CODEC_CPVEE
10/30 Change C352 GND from AGND to GND 13 SENSE A
MIC2_VREFO
29 DGND To AGND Bypass
18
SENSE B
30
10mil
MIC1_VREFO_R CODEC_LDO_CAP +MIC1_VREFO_R
1 2 36 28 C492 1 210U_0805_10V4Z
Sense Pin Impedance Codec Signals C353 2.2U_0402_6.3V6M CBP LDO_CAP 10mil
+CODEC_VREF
35
CBN VREF
27 10mil
39.2K PORT-A (PIN 32, 33) +CODEC_JDREF
1 1
R431 1 2 0_0402_5%
+MIC1_VREFO_L 31
MIC1_VREFO_L JDREF
19 10mil C354 C355
10mil

1
20K PORT-B (PIN 21, 22) CODEC_CPVEE @ 10U_0805_10V4Z 0.1U_0402_16V4Z R433 1 2 0_0402_5%
43
PVSS2 CPVEE
34 10mil 2 2
SENSE A 42
PVSS1 2
49 26 C356 R432 R434 1 2 0_0402_5%
10K PORT-C (PIN 23, 24)
change pin31 and pin28 7
DVSS2 AVSS1
37 2.2U_0402_6.3V6M 20K_0402_1%
DVSS1 AVSS2 R605 1 2 0_0402_5%

2
ALC259-VB5-GR_QFN48_7X7 1
5.1K PORT-D (PIN 48) DGND AGND
A
10/21 Change U17 to SA00003QR00 Symbol DGND AGND A
39.2K PORT-E (PIN 14, 15)
03/04 Change U17 from SA00003QR00 to SA00003QR10
11/02 Change R429,R430,R431,R433,R434,R605 from 0_0603 to 0_0402 (Layout Spacing)
20K PORT-F (PIN 16, 17)
SENSE B 11/17 Delete R429,R430
10K PORT-G (PIN 20) Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title
5.1K PORT-H (PIN 47) HDA Codec ALC259Q-GR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NXXXX M/B LA-6101P Schematics
Date: Tuesday, March 09, 2010 Sheet 29 of 48

5 4 3 2 1
 5 4 3 2 1

11/11 Change R435~R438 from SM010012010 to SD013000080

11/10 Add C512~C517(@) for EMI (Follow Realtek CRB)
Please place R435~R438,C512~C517 close to U17 Int. Speaker Conn. Copy KTV00
JSPK1
SPK_R- 1
20mil SPKL+ R435 1 2 0_0603_5% SPK_L+ SPK_R+ 2
1
2
Right
<29> SPKL+ SPK_L- 3 5
1 SPK_L+ 4
3
4
G1
G2
6 Left
C513

2
@ ACES_88266-04001
1U_0402_6.3V4Z 1
2 C512
@
D 1U_0402_6.3V4Z D33 D34 D
1 2
C514 PJDLC05C_SOT23-3 PJDLC05C_SOT23-3
@ @ @
1U_0402_6.3V4Z
2

1
SPKL- R436 1 2 0_0603_5% SPK_L-
<29> SPKL-
20mil

11/18 Change the pin definition of JSPK1 (Audio Recommend)

11/18 Swap D33
20mil SPKR- R437 1 2 0_0603_5% SPK_R-
<29> SPKR-
1
C516
@
1U_0402_6.3V4Z 1
2 C515
@
1 1U_0402_6.3V4Z
C517 2
@
1U_0402_6.3V4Z
2
SPKR+ R438 1 2 0_0603_5% SPK_R+
<29> SPKR+
20mil

C C
Headphone Out
2 2
C357 C358

330P_0402_50V7K
1 1
330P_0402_50V7K Copy NIUR1
10/29 Change R441,R442 from 56ohm to 75ohm (Follow Realtek CRB) JEHP1

HP_LEFT HPOUT_L_1 L38 1

PLO 1
1 2 2 FBMA-L11-160808-700LMT_2P HPOUT_L_2 2
<29> HP_LEFT R441 75_0402_1%

HP_RIGHT 1 2 HPOUT_R_1 L39 1 2 FBMA-L11-160808-700LMT_2P HPOUT_R_2 3

<29> HP_RIGHT R442 75_0402_1%
4

2
<29> HP_PLUG#
11/11 Correct L38,L39,L40,L41 footprint 5
6
+3VS
Copy KTV00
7DNHRII' D35 SUYIN_010030FR006G109ZL
JMIC1 PJDLC05C_SOT23-3 CONN@
1
8mil 2
1
2
@
<29> DMIC_CLK_R 3 5

1
<29> DMIC_DATA_R 3 G1
4 6
4 G2
1

ACES_88266-04001
R619 CONN@
@
1 01/07 Change GND to GNDA
2

C361 0_0402_5%
D17 @
2

PJDLC05C_SOT23-3 22P_0402_50V8J
B 2 B
1
For ESD 12/22 C362
@ 10/29 Short D18,D19 (Follow Realtek CRB)
@ 22P_0402_50V8J
2 10/29 Change R443,R444 location
1

+MIC1_VREFO_L +MIC1_VREFO_R

PLO PLO
316&$
MIC JACK

1
R443 R444

4.7K_0402_5% 4.7K_0402_5% Copy NIUR1

2

2
JEMIC1
1
<29> MIC1_L_R 1 2 MIC1_L_R_1 L41 1 2 FBMA-L11-160808-700LMT_2P MIC1_L_R_2 2
R445 1K_0603_1%

<29> MIC1_R_R 1 2 MIC1_R_R_1 L40 1 2 FBMA-L11-160808-700LMT_2P MIC1_R_R_2 3

R446 1K_0603_1%
4
<29> MIC_PLUG#
1 1
5

2
C363 C364 6
220P_0402_50V8J 220P_0402_50V8J D20
2 2 PJSOT05C_SOT23-3 SUYIN_010030FR006G109ZL
@ CONN@

1
A A

11/11 Correct D20 footprint

01/07 Change GND to GNDA
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio Jack/MIC Conn/SPK Conn
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NXXXX M/B LA-6101P Schematics
Date: Tuesday, March 09, 2010 Sheet 30 of 48
5 4 3 2 1
 A B C D E

10/22 Add R614, change R590,R589 from 0ohm to 4.7kohm (Vendor Recommend) 9/14 Change power net from +3V to

eSATA 12/22 Change U32,C490,C491,C503~C506,R589,R590,R614 from mount to @ +3VS

+5VALW
+3VALW
+3VALW

1
+USB_VCCD
R614 1 @ 2 4.7K_0402_5% 0.01U_0402_16V7K U18
Copy NITU1 1 8 R447
GND VOUT
1 2 2 VIN VOUT 7

2
C490 C491 3 6 100K_0402_5%

2
@ @ R590 R589 USB_ON# VIN VOUT
1 4 EN FLG 5 1 2 USB_OC#0 <17>
U32 0.1U_0402_16V4Z @ @ C367 R449 1
2 1 4.7K_0402_5% 4.7K_0402_5% RT9715BGS_SO8 10K_0402_5% C368
10/23 Add C503~C506 7 EN VCC 6
4.7U_0603_6.3V6K
10

1
C503 1 VCC 2
1 2 @ 0.01U_0402_25V7K SATA_PTX_DRX_P4_CR 1 RX_0P VCC 16 0.1U_0402_16V4Z 1
<13> SATA_PTX_DRX_P4 C504 1 2
2 @ 0.01U_0402_25V7K SATA_PTX_DRX_N4_CR 2 RX_0N VCC 20 9/14 Change symbol of U59 by Vivian
<13> SATA_PTX_DRX_N4
C505 1 2 @ 0.01U_0402_25V7K SATA_DTX_C_PRX_P4_CR 5 9 11/25 Change L42 from @ to mount
<13> SATA_DTX_C_PRX_P4 C506 1 TX_1P D0
2 @ 0.01U_0402_25V7K SATA_DTX_C_PRX_N4_CR 4 TX_1N D1 8
<13> SATA_DTX_C_PRX_N4 Change R451,R448 from mount to @

2
3 15 SATA_PTX_DRX_P4_R 12/27 Change C365 from SGA00002N80 to SGA00001E00
GND TX_0P SATA_PTX_DRX_N4_R R591 R592
(EMI Recommend)
13 GND TX_0N 14
@ @ +USB_VCCD
17 GND SATA_DTX_C_PRX_N4_R 0_0402_5% 0_0402_5%
12/22 Change L42 from mount to @
18 GND RX_1N 12
19 11 SATA_DTX_C_PRX_P4_R Change R451,R448 from @ to mount 150U_B2_6.3VM_R45M

1
GND RX_1P
21 PAD (EMI Recommend)
1 1
SN75LVCP412RTJR_QFN20_4X4 R448 1 2 0_0402_5% C366
@ C365 +
L42 @
USB20_N1 2
1 1 2 2
<17> USB20_N1 2 470P_0402_50V7K
SATA_PTX_DRX_P4 R585 2 1 0_0402_5% SATA_PTX_DRX_P4_RR R615 2 1 0_0402_5% SATA_PTX_DRX_P4_R Copy NCQF0
USB20_P1 4 3
SATA_PTX_DRX_N4 R586 2 <17> USB20_P1 4 3
1 0_0402_5% SATA_PTX_DRX_N4_RR R616 2 1 0_0402_5% SATA_PTX_DRX_N4_R JSATA1
W CM2012F2S-900T04_0805 1 USB
SATA_DTX_C_PRX_N4 R587 2 VBUS
1 0_0402_5% SATA_DTX_C_PRX_N4_RR R617 2 1 0_0402_5% SATA_DTX_C_PRX_N4_R USB20_N1_1 2 D-
1 2 USB20_P1_1 3
SATA_DTX_C_PRX_P4 R588 2 D+
1 0_0402_5% SATA_DTX_C_PRX_P4_RR R618 2 1 0_0402_5% SATA_DTX_C_PRX_P4_R R451 0_0402_5% 4 GND
On opposite side of U32 10/23 Add R615~618 SATA_PTX_DRX_P4_R C369 2
5 GND
12/22 Change R585~R588,R615~R618 from @ to mount 1 0.01U_0402_25V7K SATA_PTX_C_DRX_P4 6 A+
SATA_PTX_DRX_N4_R C370 2 1 0.01U_0402_25V7K SATA_PTX_C_DRX_N4 7 ESATA
2 A- 2
8
SN75LVCP412 SATA_DTX_C_PRX_N4_R C371 2 1 0.01U_0402_25V7K SATA_DTX_PRX_N4 9
GND
TI:D0 D1 SATA_DTX_C_PRX_P4_R C372 2 1 0.01U_0402_25V7K SATA_DTX_PRX_P4 10
B-
B+
11/09 Change D22 from mount to @ 11 GND
EN BA BB CHANNEL 0 CHANNEL 1 11/05 Delete USB20_N1_1,USB20_P1_1 on D21 (ESD Recommend) 12 GND
13 GND
0 X X Low-power Low-power 10/5 Change Bom structure to mount(D13) 14 GND
D21 @ <ESD> 15
USB20_N0_1 GND
6 CH3 CH2 3
TYCO_1759576-1
1 0 0 0dB 0dB (Default) CONN@

5 2
1 1 0 2.5dB pre-emphasis 0dB +USB_VCCD Vp Vn

1 0 1 0dB 2.5dB pre-emphasis USB20_P0_1 4 1

CH4 CH1
CM1293-04SO_SOT23-6
1 1 1 2.5dB pre-emphasis 2.5dB pre-emphasis

USB Port +USB_VCCD

Copy NAV50
+USB_VCCD 1 2
R452 0_0402_5%
L43 @ JUSB1
3 USB20_N0 3
1 1 1 1 2 2 1 VCC
9/14 Change power net from +3V to C373 C374 <17> USB20_N0 USB20_N0_1 2
+ USB20_P0_1 D-
+3VALW 3 D+
150U_B2_6.3VM_R45M USB20_P0 4 3 4
+3VALW 2 <17> USB20_P0 4 3 GND
2 470P_0402_50V7K W CM2012F2S-900T04_0805 5 GND1
R453 1 2 0_0402_5% 6
+5VALW GND2
1

+USB_VCCA 7
U19 GND3
R455
11/06 Swap L43 8 GND4
1 GND VOUT 8
100K_0402_5%
12/27 Change C373,C375 from SGA00002N80 to SGA00001E00 SUYIN_020133GB004M25MZL
2 VIN VOUT 7 11/25 Change L43 from @ to mount 12/22 Change L43 from mount to @ CONN@
3 6
2

USB_ON# VIN VOUT Change R452,R453 from mount to @ Change R452,R453 from @t to mount
1 4 EN FLG 5 1 2 USB_OC#1 <17>
C377 R456
RT9715BGS_SO8 10K_0402_5%
(EMI Recommend) (EMI Recommend)
4.7U_0603_6.3V6K +USB_VCCA
2 1
C378 R454 1 2 0_0402_5% Copy NAV50
9/14 Change symbol of U64 by Vivian +USB_VCCA
0.1U_0402_16V4Z L44 @ JUSB2
2 USB20_N3 1 1 2 2 1 VCC
<33> USB_ON# <17> USB20_N3 USB20_N3_1 2
1 1 D-
10/6 Change Bom structure to mount(D26) C375 C376 USB20_P3_1 3
+ USB20_P3 D+
11/09 Change D22 from mount to @ 150U_B2_6.3VM_R45M <17> USB20_P3
4 4 3 3 4 GND
2 W CM2012F2S-900T04_0805 5 GND1
D22 @ <ESD> 2 470P_0402_50V7K 1 2 6 GND2
6 3 USB20_N3_1 R457 0_0402_5% 7
CH3 CH2 GND3
11/12 Swap USB20_N3,USB20_P3,USB20_P3_1 and USB20_N3_1 on L44 8 GND4
4 4
11/25 Change L44 from @ to mount 12/22 Change L44 from mount to @ SUYIN_020133GB004M25MZL
+USB_VCCA 5 2 CONN@
Vp Vn Change R454,R457 from mount to @ Change R454,R457 from @ to mount
(EMI Recommend) (EMI Recommend)
USB20_P3_1 4 CH4 CH1 1 Security Classification Compal Secret Data Compal Electronics, Inc.
CM1293-04SO_SOT23-6 2009/10/10 2010/10/10 Title
Issued Date Deciphered Date
11/11 Swap USB20_P3_1 and USB20_N3_1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB / BT / eSATA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics 1.0
Date: Tuesday, March 09, 2010 Sheet 31 of 48
A B C D E
 5 4 3 2 1

WLAN Copy NTUC0

11/14 Add +1.5VS
+1.5VS
+3VS_W LAN R458 1
R459 1 @
2 0_0603_5%
2 0_0603_5%
+3VS
+3VALW

R460 0_0402_5% JW LAN1

PCH_PCIE_W AKE# 1 @ 2 1 2 +3VS_W LAN
<15,26,37> PCH_PCIE_W AKE# 1 2
10/22 Add Net : BT_ACTIVE and R613, Delete T13 R631 1 @ 2 0_0402_5% BT_ACTIVE_R_1 3 4
R613 1 @ 3 4
<35> BT_ACTIVE 2 0_0402_5% BT_ACTIVE_R 5 5 6 6
11/10 Add R631(@) MINI1_CLKREQ# 7 8 10/22 Reserve pull-up resister R611(@) for WLAN_LED#
<14> MINI1_CLKREQ# 7 8
9 9 10 10
D CLK_PCIE_MINI1# 11 12 01/21 Change R611 from @ to mount D
<14> CLK_PCIE_MINI1# CLK_PCIE_MINI1 11 12
<14> CLK_PCIE_MINI1 13 13 14 14
15 16 Change R461 from mount to @
15 16
17 17 18 18
19 20 W L_OFF# +5VS +3VS
19 20 W L_OFF# <33>
21 22 PLT_RST_BUF# PLT_RST_BUF# <17,26,37>
PCIE_DTX_C_PRX_N2 21 22 R632 1 0_0402_5%
<14> PCIE_DTX_C_PRX_N2 23 23 24 24 2 +3VS_W LAN
PCIE_DTX_C_PRX_P2 R633 1 @ 0_0402_5%
<14> PCIE_DTX_C_PRX_P2 25 25 26 26 2 +3VALW (9~16mA)

1
27 27 28 28
PCH_SMBCLK
11/10 Add R632,R633(@) R461 R611
29 29 30 30 PCH_SMBCLK <12,14,37>
PCIE_PTX_C_DRX_N2 31 32 PCH_SMBDATA PCH_SMBDATA <12,14,37> @
<14> PCIE_PTX_C_DRX_N2 31 32
PCIE_PTX_C_DRX_P2 33 34 11/17 Add GND on JWLAN1.40 10K_0402_5% 10K_0402_5%
<14> PCIE_PTX_C_DRX_P2 33 34
35 36 USB20_N8 USB20_N8 <17>

2
35 36 USB20_P8
37 37 38 38 USB20_P8 <17>
39 40 W LAN_LED#
+3VS_W LAN 39 40
41 42 W W AN_LED#_RR R646 1 @ 2 0_0402_5%
41 42 W LAN_LED#_RR R647 1
43 43 44 44 2 0_0402_5% W LAN_LED# <35>
45 45 46 46

EC_TX_P80_DATA
47 47 48 48 12/16 Add R646(@),R647
<33> EC_TX_P80_DATA 49 49 50 50
EC_RX_P80_CLK 51 52 +3VS_W LAN
<33> EC_RX_P80_CLK 51 52
53 54 0.1U_0402_16V4Z
GND1 GND2
1 1

1
R634 FOX_AS0B226-S40N-7F C379 C380 C381

100K_0402_5% 2 2
4.7U_0805_10V4Z 0.1U_0402_16V4Z

2
C C

10/5 Add C13/C15/C16 by Vivian

11/10 Change net : EC_TX_P80_DATA from JWLAN1.17 to JWLAN1.49
Add R634

WWAN
+3VS_W W AN R462 1 2 0_0603_5% +3VS

12/15 Reserve R642(@) Copy NTUC0

Copy NTUC0 +3VS_W W AN
12/16 Add R643(@) JW W AN1
<15,26,37> PCH_PCIE_W AKE#
R643 1 @ 2 0_0402_5% PCH_PCIE_W AKE#_3G 1
3
1 2 2
4
+1.5VS SIM Card Conn.
3 4
11/17 Swap SATA port5 signals R642 1 @
5 5 6 6
+3VS 2 10K_0402_5% 7 7 8 8 +UIM_PW R JSIM1
B UIM_DATA +UIM_PW R B
9 9 10 10 4 GND VCC 1
C489 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P5 11 12 UIM_CLK UIM_VPP 5 2 UIM_RST
<13> SATA_PTX_DRX_P5 11 12 VPP RST
C488 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N5 13 14 UIM_RST 12/15 Add PLT_RST_BUF# on JWWAN.22 UIM_DATA 6 3 UIM_CLK
<13> SATA_PTX_DRX_N5 13 14 I/O CLK
15 16 UIM_VPP 12/16 Add R644(@),R645(@) 7
C487 1 15 16 DET
2 0.01U_0402_16V7K SATA_DTX_PRX_N5 17 17 18 18
<13> SATA_DTX_C_PRX_N5 C486 1 2 0.01U_0402_16V7K SATA_DTX_PRX_P5 19 20 R463 1 2 0_0402_5%
19 20 W W AN_OFF# <33> 1

1
<13> SATA_DTX_C_PRX_P5 21 22 PLT_RST_BUF# C383
21 22 PLT_RST_BUF# <17,26,37>
C382 1 2 0.01U_0402_16V7K SATA_DTX_PRX_P1 23 24 R464 1 2 0_0402_5% +3VS_W W AN @ 8
<13> SATA_DTX_C_PRX_P1 C384 1 23 24 GND
2 0.01U_0402_16V7K SATA_DTX_PRX_N1 25 25 26 26 R465 1 @ 2 0_0402_5% +3VALW R466
GND 9 1U_0603_10V4Z
<13> SATA_DTX_C_PRX_N1 10K_0402_5% 2
27 27 28 28
29 30 R644 1 @ 2 0_0402_5% PCH_SMBCLK <12,14,37>

2
C385 1 29 30
<13> SATA_PTX_DRX_N1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N1 31 31 32 32 R645 1 @ 2 0_0402_5% PCH_SMBDATA <12,14,37>
C386 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P1 33 34
<13> SATA_PTX_DRX_P1 33 34
35 36 USB20_N13 USB20_N13 <17> +UIM_PW R
35 36 USB20_P13 TAITW _PMPAT6-06GLBS7N14N0 CONN@
37 37 38 38 USB20_P13 <17>
+3VS_W W AN 39 39 40 40
41 42 W W AN_LED# Reserve for SIM card does not meet rise time
41 42 W W AN_LED# <35>
43 44
43 44 R467 1 @ 2 100K_0402_5%
and pull-up is needed.
11/17 Change SSD_DET# from JWWAN1.47 to JWWAN1.51 45 45 46 46
R468 1
+5VS
47 47 48 48 2 100K_0402_5% +3VS
49 49 50 50
+3VS_W W AN
<33> SSD_DET#
51 51 52 52 10/28 Change Net from USB20_N9,USB20_P9 to USB20_N13,USB20_P13
53 54 01/22 Change R468 from @ to mount 0.1U_0402_16V4Z
GND1 GND2
1 1
Change R467 from mount to @
FOX_AS0B226-S40N-7F C552 C553 C554

R469 1 @ 2 2
A +3VALW 2 100K_0402_5% A
4.7U_0805_10V4Z 0.1U_0402_16V4Z
+3VS R545 1 @ 2 100K_0402_5%

01/19 Add C552,C553,C554 for +3VS_WWAN

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title
WLAN/WWAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics
Date: Tuesday, March 09, 2010 Sheet 32 of 48
5 4 3 2 1
 +3VALW
+EC_AVCC
12/05 Change L48,L49 from SM010016810 to SM010005500
1 1 1 1 1 1

0.1U_0402_16V4Z
C467

0.1U_0402_16V4Z
C468

0.1U_0402_16V4Z
C469

0.1U_0402_16V4Z
C470

1000P_0402_50V7K
C474

1000P_0402_50V7K
C471
L48 1 2
+3VALW +EC_AVCC
BLM18AG601SN1D_2P
2 1
C472 2 2 2 2 2 2
0.1U_0402_16V4Z C473

111
125
1000P_0402_50V7K

22
33
96

67
9
L49 1 2 1 ECAGND 2 U30
BLM18AG601SN1D_2P

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
R546 1 2 0_0402_5%
D31 EC_GA20 KILL_SW#
1 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F 21
2 1 <18> EC_GA20 KB_RST#_EC 2 23 BEEP# KILL_SW# <35>
<18> EC_KBRST# SERIRQ KBRST#/GPIO01 BEEP#/PWM2/GPIO10 FAN_PWM BEEP# <29>
3 26
@ <13> SERIRQ LPC_FRAME# SERIRQ# FANPWM1/GPIO12 ACOFF FAN_PWM <37> BRD_IN R547 1 @
4 27 2 0_0402_5%
CH751H-40PT_SOD323-2 <13> LPC_FRAME# LPC_AD3 LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF <40,42> VOUTZ <25>
5
LAD3
11/10 Change R546 from @ to mount <13> LPC_AD3
<13> LPC_AD2
LPC_AD2
LPC_AD1
7 LAD2 PWM Output
BATT_TEMPA
8 LAD1 BATT_TEMP/AD0/GPIO38 63
Change D31 from mount to @ <13> LPC_AD1 LPC_AD0 BATT_OVP BATT_TEMPA <41> +3VALW
LAD0 LPC & MISC
10 64 PAD T15 @
<13> LPC_AD0 BATT_OVP/AD1/GPIO39 ADP_I
2 1 2 1 65
@ C475 22P_0402_50V8J @ 10_0402_5% ADP_I/AD2/GPIO3A VOUTX ADP_I <42> USB_ON# R548 1 @
12 PCICLK AD Input AD3/GPIO3B 66 2 10K_0402_5%
R549 <17> CLK_PCI_LPC 13 75 VOUTY VOUTX <25>
<5,17> PLT_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42 BRD_IN VOUTY <25>
+3VALW 1 2
EC_SCI#
37
ECRST# SELIO2#/AD5/GPIO43
76 12/07 Change R548(@) connection from GND to +3VALW +5VS
R550 47K_0402_5% 20
R635 <18> EC_SCI# PM_CLKRUN#_R SCI#/GPIO0E
2
<15> PM_CLKRUN#
1
@ 0_0402_5%
2 38 CLKRUN#/GPIO1D 11/02 Delete net : KB_L#DA TP_CLK R553 1
68 2 4.7K_0402_5%
C476 DAC_BRIG/DA0/GPIO3C BATT_SEL_EC
70
0.1U_0402_16V4Z EN_DFAN1/DA1/GPIO3D IREF BATT_SEL_EC <42> TP_DATA R554 1
11/10 Add R635(@) DA Output IREF/DA2/GPIO3E 71 2 4.7K_0402_5%
1 KSI0 CHGVADJ IREF <42> +3VALW
55 KSI0/GPIO30 DA3/GPIO3F 72
KSI1 56 CHGVADJ <42> BATT_OVP 1 2
KSI2 KSI1/GPIO31 R555 1 @
57 KSI2/GPIO32 2 10K_0402_5% C477 100P_0402_50V8J
KSI3 58 83 EC_MUTE# BATT_TEMPA 1 2
KSI4 KSI3/GPIO33 PSCLK1/GPIO4A USB_ON# EC_MUTE# <29> C478 100P_0402_50V8J
59 84
KSI5 KSI4/GPIO34 PSDAT1/GPIO4B G_SELFTEST USB_ON# <31> ACIN
60 KSI5/GPIO35 PSCLK2/GPIO4C 85 1 2
KSI6 61 PS2 Interface 86 T/P_LOCK_LED# G_SELFTEST <25> C479 100P_0402_50V8J
KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK T/P_LOCK_LED# <35>
62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 KB926D3 : Pull-up
KSO0 39 88 TP_DATA TP_CLK <35> +3VALW
KSO1 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <35> KB926E0 : Pull-down
40
KSO[0..15] KSO2 KSO1/GPIO21 R608 1 @
41 KSO2/GPIO22 KB926 SPI STRAP PIN 2 10K_0402_5% 10/21 Reserve R608(@) for EC strap pin
<36> KSO[0..15] KSO3 42 97 R556 1 2 4.7K_0402_5%
KSI[0..7] KSO4 KSO3/GPIO23 SDICS#/GPXOA00 EN_WOL#
<36> KSI[0..7] KSO5
43 KSO4/GPIO24 SDICLK/GPXOA01 98
ME_EN# EN_WOL# <26>
11/10 Change R556 from @ to mount
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW# ME_EN# <13>
KSO7
45
KSO6/GPIO26 Matrix SDIDI/GPXID0
109
LID_SW# <35>
11/10 Change ME_EN to ME_EN#
46
KSO7/GPIO27 SPI Device Interface
KSO8 47
KSO9 KSO8/GPIO28 EC_SI_SPI_SO
48 KSO9/GPIO29 SPIDI/RD# 119
KSO10 EC_SO_SPI_SI EC_SI_SPI_SO <36>
For ENE issue KSO11
49
50
KSO10/GPIO2A
KSO11/GPIO2B SPI Flash ROM
SPIDO/WR#
SPICLK/GPIO58
120
126 EC_SPICLK EC_SO_SPI_SI <36>
1 2 KSO1 KSO12 51 128 EC_SPICS#/FSEL# EC_SPICLK <36>
+3VALW KSO13 KSO12/GPIO2C SPICS# EC_SPICS#/FSEL# <36>
R557 47K_0402_5% 52
KSO2 KSO14 KSO13/GPIO2D
1 2 53 KSO14/GPIO2E
R558 47K_0402_5% KSO15 54 73 SSD_DET#
KSO15/GPIO2F CIR_RX/GPIO40 EC_GENPD SSD_DET# <32>
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74
FSTCHG EC_GENPD <25>
11/02 Change net from KB_LIGHT# to KB_LIGHT#_R
82 89
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 CHARGE_LED0# FSTCHG <42>
CHARGE_LED0# <35> 11/05 Change net from KB_LIGHT#_R to KB_LED# (EC Recommend)
90
BATT_CHGI_LED#/GPIO52 CAPS_LED#
CAPS_LED#/GPIO53 91
EC_SMB_CK1 77 GPIO 92 CHARGE_LED1# CAPS_LED# <36>
<41> EC_SMB_CK1 EC_SMB_DA1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 KB_LED# CHARGE_LED1#2 <35>
78 93 1
<41> EC_SMB_DA1 EC_SMB_CK2 SDA1/GPIO45 SUSP_LED#/GPIO55 SYSON R551 0_0402_5% KB_LIGHT# <22>
<14> EC_SMB_CK2
79
SCL2/GPIO46 SM Bus SYSON/GPIO56
95
SYSON <37,38,44>
EC_SMB_DA2 80 121 VR_ON
<14> EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 ACIN VR_ON <47>
AC_IN/GPIO59 127
ACIN <38,40>
11/02 Delete R552
PM_SLP_S3# 6 100 EC_RSMRST#
<15> PM_SLP_S3# PM_SLP_S5# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_LID_OUT# EC_RSMRST# <15>
14 101
<15> PM_SLP_S5# EC_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_ON EC_LID_OUT# <14>
15 EC_SMI#/GPIO08 EC_ON/GPXO05 102
<18> EC_SMI# PCH_TEMP_ALERT# 16 103 H_PROCHOT#_EC EC_ON <34> R636 1 2 0_0402_5%
<18> PCH_TEMP_ALERT# NOVO# LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_PWROK H_PROCHOT# <5,47>
17 104
<36> NOVO# USER_BTN# SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF# EC_PWROK <15>
18
PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08
105 11/05 Delete net : EC_SWI# on U30.103 (Follow NIWE2)
+3VALW <36> USER_BTN# SUS_PWR_ACK 19 GPIO 106 WL_OFF# BKOFF# <22>
11/12 Add R636, net : H_PROCHOT#
<15> SUS_PWR_ACK INVT_PWM EC_PME#/GPIO0D WL_OFF#/GPXO09 MUTE_BTN# WL_OFF# <32>
25 107
<22> INVT_PWM FAN_SPEED1 EC_THERM#/GPIO11 GPXO10 BT_ON# MUTE_BTN# <36>
28
FAN_SPEED1/FANFB1/GPIO14 GPXO11
108 11/03 Delete U29
2

<37> FAN_SPEED1 WWAN_OFF# 29 BT_ON# <35>

R560 <32> WWAN_OFF# EC_TX_P80_DATA FANFB2/GPIO15
30
<32> EC_TX_P80_DATA EC_RX_P80_CLK EC_TX/GPIO16 PM_SLP_S4#
10/22 Change R561 from mount to @ 10K_0402_5% <32> EC_RX_P80_CLK ON/OFF#
31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110
ENBKL PM_SLP_S4# <15>
32 112
Change R562 from @ to mount <34> ON/OFF# PWR_LED# ON_OFF/GPIO18 ENBKL/GPXID2 EC_EAPD ENBKL <16>
34 114
1

<35,36> PWR_LED# NUM_LED# PWR_LED#/GPIO19 GPXID3 AC_PRESENT EC_EAPD <29>

11/10 Change R562 from mount to @ <36> NUM_LED#
36 NUMLED#/GPIO1A GPI GPXID4 115
AC_PRESENT <15>
116 SUSP# 11/03 Add AC_PRESENT on U30.115
GPXID5 PBTN_OUT# SUSP# <37,38,42,45>
117
R561 1 @ GPXID6 EC_PME# PBTN_OUT# <15>
2 0_0402_5% 118
<26> PCH_PCIE_WAKE#_R XCLKI GPXID7
122
XCLKO XCLK1
123 XCLK0 V18R 124
R562 1 @ 2 0_0402_5% EC_PME# 1 C480
AGND

<17> PCI_PME# 4.7U_0603_6.3V6M 11/10 Delete C481(@)

GND
GND
GND
GND
GND

KB926QFA1_LQFP128 2
11
24
35
94
113

69

E0 Version
ECAGND

11/05 Change the power of R566,R567 +3VALW SA00001J5A0

from +5VALW to +3VALW (Follow NIWE2) 10/21 Change U30 from SA00001J580 to SA00001J5A0
1 2 MUTE_BTN#
+3VALW R564 100K_0402_1%

1 2 EC_SMB_CK1 1 2 USER_BTN#
R566 4.7K_0402_5% R565 100K_0402_1%

EC_SMB_DA1
11/05 Delete D32(@), move to close to JBATT1 (ESD Recommend)
1 2
R567 4.7K_0402_5%

11/03 Change R568,R569 from 2.7kohm to 2.2kohm

11/05 Change R568,R569 from mount to @ (Follow NIWE2)
11/10 Delete R568(@),R569(@),C483(@),C484(@)
11/02 Delete U31,Q36,R570
2 1
C482 15P_0402_50V8J
XCLKO
1

3 4 @
NC OSC R571
2 1 20M_0603_5%
NC OSC
2

X2 XCLKI
32.768KHZ_12.5PF_Q13MC14610002
Security Classification Compal Secret Data Compal Electronics, Inc.
2 1 Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title
C485 15P_0402_50V8J
EC ENE-KB926
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
01/11 Change X2 from SJ100003M00 to SJ132P7KW10 (Cost down) Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics
Date: Tuesday, March 09, 2010 Sheet 33 of 48
 A B C D E

Power Button

1 1

+3VALW

2
R489
ON/OFF switch
100K_0402_5%
<36> ON/OFFBTN#

1
D24
2
1 ON/OFF# <33>
3 51_ON#
51_ON# <36,40>
DAN202UT106_SC70-3

12/04 Delete SW1

1
D
EC_ON 2
<33> EC_ON G Q24

2
S SSM3K7002FU_SC70-3

3
R490
9/10 Change symbol of
10K_0402_5% Q48 to SC70-3

1
2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power OK/PBN/TP Lock/LED
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics 1.0
Date: Tuesday, March 09, 2010 Sheet 34 of 48
A B C D E
 5 4 3 2 1

Lid Switch BT 12/17 Change R491,C405,R494,C406,Q25,C410,Q26,R496 from mount to BT@

R491 2 BT@
12/05 Change Q25 from +5VS
+3VALW 1 0_0603_5%
20mil SB934130000 to SB923010020
+3VS R492 2 @ 1 0_0603_5% 12/09 Add +3V_BT net name

1
+3V_BT 20mil R493 Copy NIWE2 Conn.
(Hall Effect Switch) C405
1
C406 10K_0402_5% +BT_VCC
BT@ BT@

2
D +3VALW 0.1U_0402_16V4Z 1U_0603_10V4Z JBT1 D

3
2
S
BT_LED# 1
G
BT_ACTIVE 1
1 BT@ 2 2 Q25 <32> BT_ACTIVE 2 2
<33> BT_ON# R494 BT@ USB20_P11 3
<17> USB20_P11 3

1
10K_0402_5% AO3413_SOT23-3 D USB20_N11
D
<17> USB20_N11 4

1
Q26 BTON_LED 4
2 5 7
5 G1

1
2 01/07 Change Q25 from BT@ G 6 8
6 G2

2
R495 +BT_VCC SSM3K7002FU_SC70-3 S

3
SB923010020 to SB934130000

1
C407 47K_0402_5% ACES_87213-0600G

VDD
0.1U_0402_16V4Z 1 20mil R496 CONN@
1 C409 C410 BT@

2
3 LID_SW# @ BT@ 10K_0402_5%
OUTPUT LID_SW# <33>
4.7U_0603_6.3V6K 0.1U_0402_16V4Z

2
2
GND

1 9/1 Del D19 and change net name to LID_SW#

U22 C411 11/10 Delete C408
1

A3212ELHLT-T_SOT23W-3 10P_0402_50V8J
2 11/10 Change C409 from mount to @

KILL Switch +3VALW 11/11 Correct D25 footprint

Copy JHXXX
3

2
D25
DAN217T146_SC59-3
+3VALW
RTC
2
C <EMI> C
@ R498
1

100K_0402_5%

11/10 Delete D26,C412,R497, Add R630,C511 (Follow NIWE2)

1
KILL_SW#
KILL_SW# <33>

+RTCVCC +RTCBATT
1
2
3

4
5

SW2 11/11 Correct SW2 footprint R630 1 2 100_0603_1%

1
2
3

G1
G2

1BS003-1210L_3P
2
C511

0.1U_0402_16V4Z
1
01/20 Add R650(@)

LED 01/21 Change R650 from @ to mount

Change R596 from mount to @
+3VS +5VS

1
+3VS R650 R596 WLAN_WWAN_LED#
@
11/11 Correct U33 footprint 10K_0402_5% 10K_0402_5%
2

1
D
2
5

B G B
WLAN_LED# 1 D
2 S
P

3
<32> WLAN_LED# B
4 2 Q39
WWAN_LED# Y G SSM3K7002FU_SC70-3
<32> WWAN_LED# 1
A
G

S
3

U33 Q38
3

NC7SZ08P5X_NL_SC70-5 SSM3K7002FU_SC70-3

TP_CLK

Touch Pad TP_DATA

2
D36
PJSOT05C_SOT23-3
Blue @

R595 1 2 820_0402_5% 2 1 LED5 BT_LED#

+5VS

1
HT-191NB_BLUE_0603

+5VS +5VS
Blue
JTP1
+5VS R499 1 2 820_0402_5% 2 1 LED1 WLAN_WWAN_LED# 1 4 11/11 Correct D36 footprint
HT-191NB_BLUE_0603 C413 TP_CLK 4
3 3
<33> TP_CLK TP_DATA 2 6
0.1U_0402_16V4Z <33> TP_DATA 26
Blue 2
1
15
5

R500 1 2 820_0402_5% 2 1 LED2 PWR_LED# ACES_85201-0405

+5VALW PWR_LED# <33,36>
HT-191NB_BLUE_0603 CONN@

11/09 Change JTP1 pin definition (Follow rubber dome pin defintion)
A A
Amber R503 2 T/P_LOCK_LED#
+5VS 1 2 1 LED4 T/P_LOCK_LED# <33>
+5VALW R501 1 2 300_0402_5% 2 1 LED6 CHARGE_LED1# 4.3k_0402_5% HT-191NB_BLUE_0603
CHARGE_LED1# <33>
HT-191UD_Amber_0603
Blue 01/26 Change R503 from 820ohm to 4.3kohm
R502 1 2 300_0402_5% 2 1 LED3 CHARGE_LED0#
+5VALW CHARGE_LED0# <33>
HT-191NB_BLUE_0603
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title
10/30 Add LED6, change LED3 11/11 Correct LED6 footprint LID/RTC/BT/TP/KILL SW/LED
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NAU00 M/B LA-6101P Schematics 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 09, 2010 Sheet 35 of 48
5 4 3 2 1
 INT_KBD Conn.
Copy KIUE0
JKB1 KSO15 C414 1 2 @ 100P_0402_50V8J KSO7 C415 1 2 @ 100P_0402_50V8J
KSO0 1
KSO1 1 KSO14 C416 1 KSO6
2 2 2 @ 100P_0402_50V8J C417 1 2 @ 100P_0402_50V8J
KSO2 3
KSO3 3 KSO13 C418 1 KSO5
4 2 @ 100P_0402_50V8J C419 1 2 @ 100P_0402_50V8J
KSO4 4
5
KSI[0..7] KSO5 5 KSO12 C420 1 KSO4
KSI[0..7] <33> 6 6 2 @ 100P_0402_50V8J C421 1 2 @ 100P_0402_50V8J
KSO6 7
KSO7 7
8
KSO8 8 KSI0 C422 1 KSO3
9 2 @ 100P_0402_50V8J C423 1 2 @ 100P_0402_50V8J
KSO[0..15] KSO9 9
KSO[0..15] <33> 10 10
KSO10 11 KSO11 C424 1 2 @ 100P_0402_50V8J KSI4 C425 1 2 @ 100P_0402_50V8J
KSO11 11
12
KSO12 12 KSO10 C426 1 KSO2
13 13 2 @ 100P_0402_50V8J C427 1 2 @ 100P_0402_50V8J
KSO13 14
KSO14 14 KSI1 C428 1 KSO1
15 2 @ 100P_0402_50V8J C429 1 2 @ 100P_0402_50V8J
KSO15 15
16
KSI7 16
17 17
KSI6 18 KSI2 C430 1 2 @ 100P_0402_50V8J KSO0 C431 1 2 @ 100P_0402_50V8J
KSI5 18
19 19
KSI4 20 KSO9 C432 1 2 @ 100P_0402_50V8J KSI5 C433 1 2 @ 100P_0402_50V8J
KSI3 20
21
KSI2 21 KSI3 C434 1 KSI6
22 2 @ 100P_0402_50V8J C435 1 2 @ 100P_0402_50V8J
KSI1 22
23 23
KSI0 24 KSO8 C436 1 2 @ 100P_0402_50V8J KSI7 C437 1 2 @ 100P_0402_50V8J
24
25 G1
26 G2
ACES_85202-24051
CONN@

03/02 Add C555 (10uF) for FP power

+5VS
12/17 Change D27,R504,R505 from mount to FP@
10/28 Change Net from USB20_N10,USB20_P10,USB20_R_P10,USB20_R_N10
FingerPrint/B Conn. to USB20_N9,USB20_P9,USB20_R_P9,USB20_R_N9
11/11 Correct L47 footprint
C555

10U_0805_10V4Z
1

EC SPI ROM
L47 @ 2
D27 4 3
4 3
6 3 USB20_R_P9
CH3 CH2
1 2
1 2 +5VS Copy IFT00
WCM2012F2S-900T04_0805
+3VS 5 2 JFP1
Vp Vn
USB20_P9 USB20_R_P9
1
15
5 11/10 Delete R506
R504 1 FP@ 2 0_0402_5% 2 6
<17> USB20_P9 USB20_N9 R505 1 FP@ USB20_R_N9 26
2 0_0402_5% 3 0.1U_0402_16V4Z 2 1 C438 +3VALW
USB20_R_N9 <17> USB20_N9 3
4 1 4
CH4 CH1 4
CM1293A-04SO SOT23-6 ACES_85201-0405 11/25 Change U23 from SA00002C100 to SA00003GK00
<EMI> @ CONN@
12/22 Change D27 from FP@ to @
U23 20mils
<33> EC_SPICS#/FSEL# EC_SPICS#/FSEL# 1 8
R507 1 SPI_WP# CE# VDD EC_SPICLK_R R508 2 0_0402_5% EC_SPICLK
2 4.7K_0402_5% 3 WP# SCK 6 1
R509 1 2 4.7K_0402_5% SPI_HOLD# 7 5 EC_SO_SPI_SI_R 1 R510 2 0_0402_5% EC_SO_SPI_SI EC_SPICLK <33>
+3VALW HOLD# SI EC_SO_SPI_SI <33>
4 2 EC_SI_SPI_SO_R 1 R511 2 0_0402_5% EC_SI_SPI_SO
VSS SO EC_SI_SPI_SO <33>

Function/B Conn. Copy IFT00 150mils

MX25L2005CMI-12G_SOP8
SA00003GK00
256kB
JFUN1
MUTE_BTN# 1 5
<33> MUTE_BTN# USER_BTN# 15 @
2
<33> USER_BTN# 26 6 EC_SPICLK_R R512 2 @ C439
3 1
3 0_0402_5%
4 4 33P_0402_50V8K
ACES_85201-0405
CONN@ 11/04 Change Net from EC_SPICLK to EC_SPICLK_R on R512.2
Layout Note : Please place R508,R510,R512,C439 close to U30

Power/B Conn. +3VALW

2

Copy KSW01 R544

100K_0402_5%
JPWR1
1 +5VALW D30
1

1 NOVO#
2 +5VS 2
2 ON/OFFBTN# <33> NOVO# NOVO_BTN#
3 3 1
4 NOVO_BTN# ON/OFFBTN# <34> 51_ON# 3
4 PWR_LED# <34,40> 51_ON#
5 5 PWR_LED# <33,35>
6 CAPS_LED#
6 NUM_LED# CAPS_LED# <33> DAN202UT106_SC70-3
7 7 NUM_LED# <33>
8 PCH_SATALED#
8 PCH_SATALED# <13>
9
9
10 10
Security Classification Compal Secret Data Compal Electronics, Inc.
GND
11 Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title
12
GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS/KBD/Fun_B/PWR_B/FP_B
ACES_85201-1005N AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
CONN@ B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics1.0
Date: Tuesday, March 09, 2010 Sheet 36 of 48
 New Card Socket
New Card Power Switch +3VS_CARD1 Copy KIUE0
JEXP1
10/28 Change Net from USB20_N4,USB20_P4 to USB20_N10,USB20_P10
1 1 1
C440 C441 GND
2 USB_D-
@ <17> USB20_N10
+1.5VS
11/17 Add R637,R638 <17> USB20_P10 CP_PE#
3 USB_D+
0.1U_0402_16V4Z 4.7U_0805_10V4Z 4
C442 U24 2 2 CPUSB#
5
+1.5VS_CARD1_R RSV
2 1 0.1U_0402_16V4Z 12 11 R637 1 2 0_0603_5% +1.5VS_CARD1 6
1.5Vin 1.5Vout RSV
14 1.5Vin 1.5Vout 13 <12,14,32> PCH_SMBCLK 7 SMB_CLK
+3VS 8
+1.5VS_CARD1 <12,14,32> PCH_SMBDATA SMB_DATA
C443 +1.5VS_CARD1 9
+3VS_CARD1_R +1.5V
2 1 0.1U_0402_16V4Z 2 3 R638 1 2 0_0603_5% +3VS_CARD1 10
3.3Vin 3.3Vout +1.5V
4 3.3Vin 3.3Vout 5 <15,26,32> PCH_PCIE_WAKE# 11 WAKE#
2 1 0.1U_0402_16V4Z 1 1 +3VALW_CARD1 12 +3.3VAUX
C444 17 15 C445 C446 PERST1# 13
+3VALW AUX_IN AUX_OUT +3VALW_CARD1 PERST#
@ +3VS_CARD1 14
PLT_RST_BUF# 0.1U_0402_16V4Z 4.7U_0805_10V4Z +3.3V
<17,26,32> PLT_RST_BUF# 6 SYSRST# OC# 19 15 +3.3V
2 2 EXP_CLKREQ# 16
SYSON PERST1# <14> EXP_CLKREQ# CP_PE# CLKREQ#
<33,38,44> SYSON 20 8 <18> CP_PE# 17
SHDN# PERST# CPPE#
<14> CLK_PCIE_EXP# 18 REFCLK-
SUSP# 1 16 19
<33,38,42,45> SUSP# STBY# NC <14> CLK_PCIE_EXP REFCLK+
20 GND
+3VALW R513 2 @ 1 100K_0402_5% CP_PE# 10 CPPE# GND 7 <14> PCIE_DTX_C_PRX_N3 21 PERn0
(Internal Pull High to AUXIN) <14> PCIE_DTX_C_PRX_P3 22
PERp0
(Internal Pull High to AUXIN) 9 +3VALW_CARD1 23
CPUSB# GND
<14> PCIE_PTX_C_DRX_N3 24 PETn0
11/09 Delete R602(@) 18 RCLKEN <14> PCIE_PTX_C_DRX_P3 25 PETp0
26 GND
Change net from CP_USB# to CP_PE# G577NSR91U TQFN 1 1
(Follow NIWE2) C447 C448 27 30
@ GND GND
28 GND GND 29
0.1U_0402_16V4Z 4.7U_0805_10V4Z
2 2 SANTA_130801-5_RT
CONN@

11/10 Delete D28,D29,C449,C450

12/10 Change H17 from H_3P6X5P6 to H_3P6X4P6
FAN1 Conn 11/14 Add H26 H_2P8
11/11 Change H12~H15 to H_3P3

H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H25

H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8

@ @ @ @ @ @ @ @ @ @ @ @

1
+3VS
H12 H13 H14 H15 H16
H_3P3 H_3P3 H_3P3 H_3P3 H_3P6
1

R514
10K_0402_5% @ @ @ @ @ H26

1
40mil H_2P8
1 2 +VCC_FAN1 JFAN1
+5VS
2

R515 0_0603_5% +VCC_FAN1 1

1 H17 H18 H19 H20 @
2

1
<33> FAN_SPEED1 FAN_PWM 2 H_3P6X4P6 H_3P6X5P6 H_4P1X3P1 H_6P0
3
<33> FAN_PWM 3
4
4
5
G5 @ @ @ @
6

1
G6
ACES_85205-04001
CONN@
H21 H22 H23 H24
H_3P8 H_3P8 H_3P8 H_3P8
9/1 Del U3/C11/C12/R8 Copy NIWE2
11/10 Delete C451 10/23 Change JFAN1 to NIWE2 FAN connector @ @ @ @
1

1
@ @ @ @

1
FD1 FD2 FD3 FD4
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN & Screw Hole
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics
Date: Tuesday, March 09, 2010 Sheet 37 of 48
 A B C D E

+5VALW TO +5VS
For EMI Require 1/21
+5VALW +5VS Put near Right side of DIMM
11/10 Change
U25
R517 from 8 1 0.1U_0402_16V4Z
D S
200kohm to 7 D S 2 1

2
6 D S 3 1
20kohm (Follow 5 D G 4 C452 R516 C453
@
NIWE2) SI4800BDY-T1-E3_SO8 470_0603_5% 2
1U_0603_10V4Z 2
12/17 Change R517 SB548000310

1
5VS_GATE_1
1 from 20kohm to 1

10kohm

1
D

B+ 2 R517 1 5VS_GATE 1 R641 2 2 SUSP

10K_0402_5% 10K_0402_5% G
1 S Q40 @

3
C454 SSM3K7002FU_SC70-3
1

D 0.1U_0603_25V7K
SUSP 2 12/04 Add R639, Change R520 from mount to @
2
G 12/04 Change Q5,Q6,Q7,Q8 from SB00000AR00 to SB000009610 01/21 Change R520 from @ to mount
Q5 S
3

SSM3K7002FU_SC70-3 Add Q40,Q41,Q42,Q43(SB000009610) Change R639 from mount to @

12/07 Add R641 (10kohm) 12/04 Change Q40,Q41,Q42,Q43,R516,R521,R527,R518 from mount to @
01/21 Change R520 from 100kohm to 10kohm
+5VALW RTCVREF +5VALW
+3VALW TO +3VS

2
+3VALW +3VS
R518 R639 R520
U26 @ @
8 1 100K_0402_5% 100K_0402_5% 10K_0402_5%
D S
11/10 Change 7 2

1
D S

2
6 3 1 SUSP
R522 from D S C455 R521 SYSON# <44> SUSP
5 D G 4
200kohm to @
SI4800BDY-T1-E3_SO8 470_0603_5%
47kohm (Follow SB548000310 1U_0603_10V4Z 2
1

1
D D
2 NIWE2) SYSON 2 2 2
<33,37,44> SYSON G <33,37,42,45> SUSP# G
1

1
D
S Q6 @ S Q41

3
1
2 R522 1 3VS_GATE 2 SUSP R523 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3
B+
47K_0402_5% G 10K_0402_5% R525
1 S Q42 @ 10K_0402_5%
3

C456 SSM3K7002FU_SC70-3

2
1

D 0.1U_0603_25V7K
SUSP 2
2
G
11/09 Change R523 from 100kohm to 10kohm
Q7 S
3

SSM3K7002FU_SC70-3
+1.5V +1.5V_1

+1.5V to +1.5VS 12/18 Change U27 from SB000007O00 to SB548000310

C457 1 2 0.1U_0402_16V4Z
+1.5V +1.5VS Optional, if +1.5VS can combine with +1.5V_1 C458 1
For Calpella CPU S3 DRAM Power
2 0.1U_0402_16V4Z

U27 C459 1 2 0.1U_0402_16V4Z (1.5V_CPU VDDQ)

8 1
D S C460 1
7 2 1 2 0.1U_0402_16V4Z
D S
2

6 3 C461
D S R527
11/10 Change R528 5 D G 4
@
from SI4800BDY-T1-E3_SO8 2
1U_0603_10V4Z 470_0603_5% 11/17 Delete R526(@) J4
510kohm to 100kohm SB548000310 1 2
1

1 2
(Follow NIWE2) JUMP_43X118@
3 3
J5
1

D
1 2
1.5VS_GATE 1 2
B+ 2 R528 1 2 SUSP 12/18 Change U28 from SB000007O00 to SB548000310
100K_0402_5% G JUMP_43X118@
510K_0402_5%

1 S Q43 @
3
1

C462 SSM3K7002FU_SC70-3 11/10 Change R531 U28 250mil(6A)

8 1
R529 0.1U_0603_25V7K from 100kohm to D S
7 2
D S
1

2
D @ 2
20kohm (Follow 6 3 1
SUSP D S C463 R530
2 5 4
2

NIWE2) D G

1.5V_1_GATE_1
G
Q8 S SI4800BDY-T1-E3_SO8 0.1U_0402_16V4Z 220_0603_5%
3

SSM3K7002FU_SC70-3 2
11/25 Change R531 from SB548000310 11/23 Change R530 from SD013470080(470ohm) to SD013220080(220ohm)

1
20kohm to 100kohm
1

1
ACIN D
2
<33,40> ACIN G @ 9/10 Change symbol of 1 R531 2 1.5V_1_GATE 2 R640 1 2 SUSP
B+
S SSM3K7002FU_SC70-3 33K_0402_5% 47K_0402_5% G
Q39 to SC70-3
3

Q28 1 S Q29

3
1
D C464 SSM3K7002FU_SC70-3
SUSP 2
G 0.1U_0603_25V7K
Q30 S 2

3
+0.75VS +1.1VS_VTT +1.8VS +1.5V SSM3K7002FU_SC70-3

12/04 Add R640

2

R532 R534 R535 R536

12/05 Change R640 from 10kohm to 20kohm
12/15 Change R640 from 20kohm to 47kohm
@ @ 470_0603_5% 12/15 Change R531 from 100kohm to 33kohm
22_0603_5% 470_0603_5% 470_0603_5% @
11/23 Change C457,C458,C459,C460,U28,R531,C464,Q30,C463,R530,Q29 from @ to mount (For Intel S3 Power Reduction.)
1

4 4
1

D D D D
2 SUSP 2 SUSP 2 SUSP 2 SYSON#
G G G G
SSM3K7002FU_SC70-3 S S Q33 @ S Q34 @ S SSM3K7002FU_SC70-3
3

Q31 SSM3K7002FU_SC70-3 SSM3K7002FU_SC70-3 Q35

11/06 Delete R533,Q32 @
9/10 Change symbol of
Security Classification Compal Secret Data Compal Electronics, Inc.
11/25 Change R534,R535,Q33,Q34 from mount to @ Q37/Q38 to SC70-3 Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title
11/23 Change R532 from SD013470080(470ohm) to SD000001R80(22ohm) DC Interface
(Follow Intel Recommend) 9/10 Change symbol of Q44/Q64/Q66 to SC70-3 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics
Date: Tuesday, March 09, 2010 Sheet 38 of 48
A B C D E
 A B C D E

COMPAL CONFIDENTIAL
MODEL NAME: KBLA0 Power Sequence Block Diagram
PCB NAME: LA4811P
1 REVISION: 1

DATE: 2008/12/04
SBPWR_EN 2
U28,+3V

V
AC A1
MODE VIN Q5,+5V
V V
A2 A3 B5

VV
A5 2

V
PU5 PU4

V
B+ +3V
+3VALW B7 2 3
BATT V +5V
BATT
MODE
B1
B2
B+ B4 V 12

V
V 4 SYS_PWROK
EC
13
PQ1 EC_RSMRST# PCH_RSMRST# PM_DRAM_PWRGD

V
V V PCH
B3 A5 B7 5 14 (UMA)
PBTN_OUT# H_CPUPWRGD
CPU

V V
V
2 2
51ON# EC_ON 8c
PLT_RST# 15
GFXVR_EN
SLP_S3#
A4 B6 SLP_S4# 6
V V
SLP_S5# PU12

V
V

ON/OFF VV MAX17028
H_VTTPWRGD 8b Power Up
SYSON 7 SYSON#

V
+1.5V
PU6 V V
11a 11b
SUSP#,SUSP 8 8a VS_ON PU13

V
U20 +1.1VS_VTT VGATE EC_PWROK

V
U39 VS_ON PU7

V
3 +5VS +1.05VS 3

(DIS)
V
U19
VGA_ON MXM
+3VS

V
V

U26
+1.5VS

PU8 (DIS) (UMA)

V

+0.75V 8c 8c
VGA_PWRGD GFX_CORE_PWRGD

9 10 CLK_ENABLE# U36
VR_ON
V
PU11 CK505
V

+CPU_CORE
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/10/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Sequence Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics1.0
Date: Friday, February 26, 2010 Sheet 39 of 48
A B C D E
 A B C D

ACIN BATT ONLY

Precharge detector Precharge detector
VIN
Min. typ. Max. Min. typ. Max.
@ SINGA_2DW -0268-B16 PF101 PL101 L-->H 14.991V 15.381V 15.782V L-->H 7.196V 7.349V 7.505V
JDCIN1 7A_24VDC_429007.W RML SMB3025500YA_2P
APDIN 2 APDIN1
H-->L 13.860V 14.247V 14.621V H-->L 6.138V 6.214V 6.056V
4 4 1 1 2
3 3
2 2
1 1

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
@ 0.1U_0603_25V7K

@ 0.1U_0603_25V7K
1 1

PR102

1
1K_1206_5%
1 2 PQ102

PC104
TP0610K-T1-E3_SOT23-3

2
PC101

PC102

PC103

PC105

PC106
PR103
1K_1206_5%
VIN 2 1 1 2 3 1

PD102 PR104
LL4148_LL34-2 1K_1206_5%
1 2

100K_0402_1%
1

1
100K_0402_1%
PR105

PR106

2
Vin Detector

2
Min. typ. Max.
L-->H 17.430V 17.901V 18.384V

100K_0402_1%
H-->L 16.976V 17.262V 17.728V

PR107
1
PR101
1M_0402_1%

1 2
1 2
VINDE-2 VIN 2
VS <33,42> ACOFF
PQ103
VIN
2
DTC115EUA_SC70-3 2

0.01U_0402_25V7K
B+

10K_0805_5%
2

3
1
PQ104
1

PC107

PR109
PR108 PR110 DTC115EUA_SC70-3
84.5K_0402_1% 10K_0402_1%
2

3
1 2

2
PR111 ACIN <33,38>
2

22K_0402_1%
VINDE-1 1 2 3
P

+ PACIN PR113
0.068U_0603_16V7K

O 1
VINDE-3 2 -
PACIN <42> VL 2.2M_0402_5%
G
1

20K_0402_1%

10K_0402_5%
PU102A
0.1U_0402_16V7K

2 1
1

1
LM393DG_SO8
4
PC108

PR112

PC109

PR114
PD101
2

499K_0402_1%
LLZ4V3B_LL34-2
2

1
PR115 VS
2

PR116
10K_0402_5%

0.01U_0402_25V7K
100K_0402_1%
2 1 RTCVREF 3.3V

1
PR117

PC110

2
2
PD103

8
RB715F_SOT323-3
2 5

P
<41,43> MAINPW ON +
VIN 1 7 O

205K_0402_1%

499K_0402_1%

0.01U_0402_25V7K
<42> ACON 3 6

G
-

1
PU102B

1
PR118

PR119

PC112
LM393DG_SO8

1000P_0402_50V7K
4
2

1
3 3

PC111
PD104

0.1U_0603_25V7K

2
LL4148_LL34-2

PRG++ 2

2
1

PC113
PD105
1

LL4148_LL34-2 51ON-1

2
BATT+ 2 1
1

PR120 PR121 PR122 PR123

1
PQ101 68_1206_5% 68_1206_5% 10K_0402_5% D 47K_0402_5%
TP0610K-T1-E3_SOT23-3 2 1 2 2 1 PACIN
PR124 RTCVREF G
2

1
200_0603_5% S

3
CHGRTCP 1 2 51ON-2 3 1 PQ105
VS SSM3K7002FU_SC70-3
0.22U_0603_25V7K
1

2 +5VALW
2

1
PC114

PR125 PC115
100K_0402_1% 0.1U_0603_25V7K
1

PR126 PQ106
2

3
22K_0402_1% DTC115EUA_SC70-3
1 2 51ON-3
<34,36> 51_ON#
- JRTC1 + PR128
560_0603_5%
2 1 1 2 +RTCBATT

RTCVREF PD106
1

@ MAXEL_ML1220T10 1 2
PU101 PR127 +CHGRTC
+CHGRTC 200_0603_5% RB751V-40_SOD323-2
4
PR129 APL5156-33DI-TRL_SOT89-3 4

560_0603_5% 3.3V
RTC Battery
2

RTCVREF-1
1 2 3 2CHGRTCIN
VOUT VIN
1

GND PC117
PC116 1U_0805_25V6K
10U_0603_6.3V6M 1
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2009/10/10 Deciphered Date 2010/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN & DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 09, 2010 Sheet 40 of 48
A B C D
 A B C D

1 1

PH1 under CPU botten side :

CPU thermal protection at 95 degree C
Recovery at 56 degree C

VMB2 VMB VL
PF201 PL201
JBATT1 12A_65V_451012MRL SMB3025500YA_2P
1 1 2 1 2 VL
1 BATT+
2 2
3 EC_SMCA
3

1
2
4 EC_SMDA 2

2
5 PC203 PR203 PR204
5

1
6 0.1U_0603_25V7K 10K_0402_1% 20K_0402_1% PR205

2
6
1

7 PC201 PC202 @ 100K_0402_1%

7
3

0.01U_0402_25V7K
100_0402_1%

100_0402_1%

8 1000P_0402_50V7K

2
GND PD202 PU201
9

1
GND @ 1 VCC TMSNS1 8
PR201

PR202

@ SUYIN_200082MR007G100ZR
2

2
2 GND RHYST1 7
PR206
1

3 6 8.87K_0402_1%
PESD5V0U2BT 3P C/C SOT23 ESD OT1 TMSNS2

@ 47K_0402_1%
4 5

1
OT2 RHYST2

1
PR207
G718TM1U_SOT23-8
PH201
EC_SMB_CK1 <33> 100K_0402_1%_TSM0B104F4251RZ

2
EC_SMB_DA1 <33> MAINPW ON <40,43>

1
1 2 +3VALW PH202
PR208 @ 100K_0402_1%_TSM0B104F4251RZ
6.49K_0402_1%

2
1
PR209
2 BATT_TEMPA <33> A/D
10K_0402_5%
3

3 3

PD201
@ PJSOT24C_SOT23-3
1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 09, 2010 Sheet 41 of 48
A B C D
 5 4 3 2 1

P3
B+
P2
PQ301 PQ302
FDS6675BZ_SO8 FDS6675BZ_SO8
PR302
VIN 8
7
1
2
1
2
8
7 0.02_1206_1% CHG_B+
6 3 3 6 PJ301
PQ303
5 5 1 4 2 2 1 1
FDS6675BZ_SO8

470P_0603_50V8J
2 3 @ JUMP_43X118 1 8

1
47K_0402_5%
2 7
1

@ PC302

PC306
D 3 6 D

2200P_0402_50V7K
PR301

2200P_0402_50V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
5

2
200K_0402_1%
DTA144EUA_SC70-3

0.1U_0603_25V7K

PC324

4
1

PC304

PC305

PC303
CSIN
2

PC301

PR303
PQ304 CSIP

1
@ PR304
47K_0402_1%

2
2 1 2

2
VIN
1

2
RB751V-40_SOD323-2 PR305 3 ACOFF
1

PD301 10K_0402_1% 1
1 2 6251_VDD 2
2 PR307

2.2U_0603_6.3V6K

1 1
PC307
PQ305 PR306 PD302 200K_0402_1%

1
10K_0402_1% RB715F_SOT323-3 1 2 VIN
DTC115EUA_SC70-3 <33> FSTCHG FSTCHG 2 1 PU301 PC309
0.1U_0603_25V7K
3

2
1 2 1 24 6251_DCIN2 1 PQ306
VDD DCIN

100K_0402_1%
PC308 DTC115EUA_SC70-3 2
PQ307 0.1U_0402_16V7K
1

D SSM3K7002FU_SC70-3

PR308
150K_0402_1% 2 23
ACSET ACPRN
PR309

2 PR310

SIS412DN-T1-GE3 _PAK1212-8
G 20_0402_5%

0.1U_0603_25V7K
2

3
5

1
6251_EN CSON D
S 3 22 1 2
3

EN CSON

1
PC311
PC310 2 PACIN
2

0.047U_0402_16V7K G

PQ308
CELLS 4 21 1 2 CSOP S

3
CELLS CSOP PR311 PQ309
C PC312 6800P_0402_25V7K 20_0402_5% SSM3K7002FU_SC70-3 C
4
PR313 PQ310 1 2 5 20 2 1
ICOMP CSIN
1

2
3K_0402_1% D SSM3K7002FU_SC70-3 PR312
<40> PACIN PACIN 1 2 2 PC313 PR314 6.81K_0402_1% PC314 20_0402_5%
G 1 2 1 2 6 19 0.1U_0402_16V7K
1 2 PL301 PR317

3
2
1
VCOMP CSIP PR315 10UH_1164AY-100M=P3_4.7A_20% 0.02_1206_1%
S
3

0.01U_0402_25V7K 1 2 2.2_0402_5% BATT+

PC315 1 2 7 18 LX_CHG 1 2 CHG
1 4
@ 100P_0402_50V8J PR316 ICM PHASE
<40> ACON

5
100_0402_1% 2 3

SI7716ADN-T1-GE3 _PAK1212-8
<33> ADP_I

1
6251_VREF DH_CHG

4.7_1206_5%
8 VREF UGATE 17
1

PR318
PQ311 PR319 1 2 PR320 PC317
DTC115EUA_SC70-3 154K_0402_1% PC316 2.2_0402_5% 0.1U_0603_25V7K

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
PQ312
<33> IREF 2 1 0.1U_0402_16V7K 9 16 BST_CHG 1 2 BST_CHGA 2 1
CHLIM BOOT

1
PR321 4

1
PC318

PC319

PC320
ACOFF 21K_0402_1% PD303
0.01U_0402_25V7K

<33,40> ACOFF 2
6251_VREF 1 2 10 15 6251_VDDP RB751V-40_SOD323-2
ACLIM VDDP
1

2
1
PC321

PR322 26251_VDD

680P_0603_50V7K
1

3
2
1
1

PC322
100K_0402_1% 11 14 DL_CHG
3

2
VADJ LGATE

1
PR324 PR323
2

2.26K_0402_1% 4.7_0402_5%
2

12 13 PC323

2
GND PGND 4.7U_0805_6.3V6K
2

ISL6251AHAZ-T_QSOP24
CHGVADJ=(Vcell-4)/0.10627 PR325
Connect to EC A/D Pin. 15.4K_0402_1%
Vcell CHGVADJ <33> CHGVADJ 1 2

B
4V 0V B
1

4.2V 1.882V UMA CP mode (55W) 6251_VDD 6251_VDD

PR326
4.35V 3.2935V Vaclim=2.39*((2.26K//152K)/(2.26K//152K+21K//152K))=0.25739V 31.6K_0402_1%
Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05)

2
2

where Vaclim=0.25739V, Iinput=2.7692A PR327 PR328

CC=0.25A~3A 100K_0402_1% @ 100K_0402_1%

IREF=1.016*Icharge UMA CP mode (30W)

1
CELLS
IREF=0.254V~3.048V Vaclim=2.39*((31.6K//152K)/(31.6K//152K+31.6K//152K))=1.195V

3
Iinput=(1/0.05)((0.05*Vaclim)/2.39+0.05)
VCHLIM need over 95mV
where Vaclim=1.195V, Iinput=1.5A @ PR330
0_0402_5% 2 5 2 1
PR331 BATT_SEL_EC <33>

2
@ 0_0402_5%

4
PQ314 TP0610K-T1-E3_SOT23-3 PR333
10_0603_5%
3 1 1 2 6251_DCIN PQ313A PQ313B
P3 @ 2N7002KDW -2N_SOT363-6 @ 2N7002KDW -2N_SOT363-6
1
100K_0402_1%
PR335

PR337
2

2 1

A 100K_0402_1% A
1

PQ315
DTC115EUA_SC70-3 2 FSTCHG
2 1
3 SUSP# Security Classification Compal Secret Data Compal Electronics, Inc.
SUSP# <33,37,38,45> 2009/10/10 2008/6/22 Title
Issued Date Deciphered Date
PD304 CHARGER
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RB715F_SOT323-3 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 09, 2010 Sheet 42 of 48

5 4 3 2 1
 5 4 3 2 1

ISL6237_B+
ISL6237_B+
B+
PJ401 PR401
@ JUMP_43X118 0_0402_5%
2 2 1 1 1 2

330P_0402_50V7K

10U_1206_25V6M

2200P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K
10U_1206_25V6M

2200P_0402_50V7K
0.1U_0402_25V6

0.1U_0402_25V6
D D

1
PC401

PC402

PC403

PC404

PC423

PC406

PC407

PC424
5

PC405
1U_0603_10V6K
VL

2
2
@ @

PC409
PC408
PQ401 0.1U_0603_25V7K 4

4.7U_0805_6.3V6K
3/5V_VCC
1

1
3/5V_VIN
4 SIS412DN-T1-GE3_PAK1212-8

PC410
PQ402 +5VALWP

2
SIS412DN-T1-GE3_PAK1212-8

3
2
1
PL402

1
2
3
PL401 4.7UH_PCMC063T-4R7MN_5.5A_20%

7
4.7UH_PCMC063T-4R7MN_5.5A_20% PU401 PC411 2 1
1 2 1U_0603_10V6K

VIN

VCC

LDO
+3VALWP 33 19 1 2
TP PVCC

1
1

5
UG3 26 15 HG5
PR402 UGATE2 UGATE1 PR405
0_0402_5%

4.7_1206_5% BST3A-1 2 1 BST3A 24 17 BST5A2 1BST5A-1 4.7_1206_5% 1

BOOT2 BOOT1
2

PR403 PR406

15V_SNB
1

2
2

2
+
PR404

2.2_0603_5% 2.2_0603_5% PC415

@ 61.9K_0402_1%
4

13V_SNB
2
PC412 + 4 PC413 150U_B2_6.3VM_R45M

2
150U_B2_6.3VM_R45M 0.1U_0603_25V7K

1
2

PR407
SW 3 25 16 SW 5 PC416
1

2 PC417 PHASE2 PHASE1 PC414 680P_0603_50V7K

3
2
1
680P_0603_50V7K 0.1U_0603_25V7K

1
2
3

2
LG3 23 18 LG5

1
PQ403 LGATE2 LGATE1
10K_0402_1%

SI7716ADN-T1-GE3_PAK1212-8
2

PGND 22

2
C C
PR408

FB3 30 PQ404
OUT2

PR409
0_0402_5%
SI7716ADN-T1-GE3_PAK1212-8
OUT1 10
VL 32
1

@ FB2

1
11 FB5
2VREF_ISL6237 FB1

1 2 1 REF
PC418
0.22U_0603_25V7K 9
BYP
8 NC
PD401 29 5V_SKIP 2 1
SKIP PR410
VL
1 2
@ 0_0402_5%
RB751V-40_SOD323-2 1 2
20 28 PR411
PR412 SECFB POK2 0_0402_5%
VS PD402 100K_0402_1% 2 1 2VREF_ISL6237
1 2 EN_LDO-1 1 2 EN_LDO 4 13 PR413
EN_LDO POK1 @ 0_0402_5%
2
200K_0402_1%

LLZ5V1B_LL34-2
2
PR414

PC419 3/5V_EN1 14 12 ILM1 2 1

0.22U_0603_25V7K EN1 ILIM1 PR415
301K_0402_1%
1

3/5V_EN2 27 31 ILIM2 2 1

GND
TON
1

EN2 ILIM2

NC
PR416

2
RT8206BGQW _QFN32_5X5 301K_0402_1%

21
B VL B
806K_0603_1%

PD403

13/5V_NC
2

1 2 PR417

13/5V_TON
PR418

0_0402_5%
1

RB751V-40_SOD323-2 PR420

1U_0603_10V6K
PC420
@ 47K_0402_1%
2VREF_ISL6237

PR419
1

<40,41> MAINPW ON 2 1 1 2

0_0402_5% 2 PR421
0.047U_0402_16V7K

0.047U_0402_16V7K

0_0402_5% PJ402
1

+3VALWP 2 1 +3VALW
2 2 1
PC421

PC422

@ JUMP_43X118
2

2VREF_ISL6237

@ PJ403
+5VALWP 2 2 1 1 +5VALW
@ JUMP_43X118

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2009/10/10 2010/01/06 Title
Issued Date Deciphered Date 3VALW/5VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 09, 2010 Sheet 43 of 48
5 4 3 2 1
 5 4 3 2 1

PJ501
1.5V_IN 2 1 B+
2 1
@ JUMP_43X79

5
6
7
8

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K

2200P_0402_50V7K
0.1U_0402_25V6
1

1
SI4686DY-T1-E3_SO8

PC502

PC503

PC504

PC505

PC511
PR502

2
240K_0402_1% 4
1.5V_TON 1 2
D D

PQ501
PR501 @
0_0402_5%
<33,37,38> SYSON 1 2 1.5V_EN BST_1.5V 1 2BST_1.5V-1
1 2

3
2
1
PR503 PC506
2.2_0603_5% 0.1U_0603_25V7K

1
PL501

15

14
1
PC501 PU501 1UH_PCMB103E-1R0MS_20A_20%
@0.1U_0402_16V7K 1 2

EN/DEM

NC

BOOT
+1.5VP

220U_B2_2.5VM_R15M
1
2 13 UG_1.5V
TON UGATE
PR505 3 12 1.5V_TRIP PR504
VOUT PHASE

5
6
7
8
100_0603_1% 4.7_1206_5%

10U_0603_6.3V6M
1
+5VALW 1 2 1.5V_V5FILT 4 11 SW
1 _1.5V 2 +5VALW

1.5V_SNB 2
VDD CS

1
+

PC507
PR506

SI4634DY-T1-E3_SO8
1.5V_FB 5 10 10K_0402_1%
FB VDDP

PC508
2
1
LG_1.5V 2
6 PGOOD LGATE 9 4

PGND

PQ502
PC509

GND
4.7U_0603_6.3V6K PC510

1
@ 47P_0402_50V8J PC513
1 2 RT8209BGQW _W QFN14_3P5X3P5 PC512 680P_0603_50V7K

3
2
1
4.7U_0805_6.3V6K

2
PR508
31.6K_0402_1%
1 2

1
C PR509 C
30.1K_0402_1%

2
PJ504
+1.5VP 2 2 1 1 +1.5V
@ JUMP_43X118

PJ506
+0.75VSP 2 2 1 1 +0.75VS
@ JUMP_43X79

PJ603
+1.8VSP 1 1 2 2 +1.8VS
@ JUMP_43X39
+1.5V
1

B PJ503 B
1

@ JUMP_43X79
+3VS
2

PU503
2

0.75V_IN 1 6 +3VALW
VIN VCNTL

1
2 GND NC 5
1

PC525 PJ604

1
1

4.7U_0805_6.3V6K 3 7 PC526 @ JUMP_43X39

PR519 VREF NC 1U_0402_6.3V6K
2

2
1K_0402_1% 4 8 PU602
@ PR520 VOUT NC LDO_1.8V_IN 1 6 +5VS

2
0_0402_5% VIN VCNTL
9
2

TP
<5> S3_0.75V_EN 1 2 2 GND NC 5

1
0.75V_REF G2992F1U_SO8 PC618

1
4.7U_0805_6.3V6K 3 7 PC619
VREF NC
1

PR521 PR619 1U_0402_6.3V6K

+0.75VSP

2
1

150K_0402_1% D PR522 1K_0402_1% 4 VOUT NC 8

<38> SUSP 1 20.75V_EN 2 1K_0402_1% PC527
1

G 0.1U_0402_16V7K 9
2

2
TP
S PQ505 PC529
3

SSM3K7002FU_SC70-3 10U_0603_6.3V6M LDO_1.8V_REF G2992F1U_SO8

2

2 1

1
PR620 +1.8VSP
1

1
PD501 100K_0402_1% D PR621
1SS355_SOD323-2 PC528 <38> SUSP 1 2LDO_1.8V_EN
2 1.24K_0402_1% PC620

1
0.1U_0402_16V7K G 0.1U_0402_16V7K
2

2
1

S PC621
3

2
PC622 PQ604 10U_0603_6.3V6M

2
0.1U_0402_16V7K SSM3K7002FU_SC70-3
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5V/0.75V/1.8V
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 09, 2010 Sheet 44 of 48
5 4 3 2 1
 5 4 3 2 1

PJ701
2 1 VTT_B+
B+ 2 1
@ JUMP_43X118
+5VS
D D

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_50V7K

2200P_0402_50V7K
SW _VTT

0.1U_0402_25V6
1

1K_0402_5%
PC701

PC702
UG_VTT PR702

PC703

PC704

PC708

PR701
2.2_0603_5%
2

2
VTT_BOOT1 2 VTT_BOOT-1 1 2
PR703

2
0_0402_5% PC705
@ +5VALW 0.1U_0603_25V7K

1.1VS_PGOOD
<5> VCCP_POK 1 2

5
PR704
0_0603_5%

PR705

16

15
8

1
PU701 4.7_0603_5% PQ701

2
1 2 VTT_VCC 4 AON6410

GND

PGOOD

PHASE

UG

BOOT
3 14 VTT_PVCC
1 2
VIN PVCC

3
2
1
PC706
2.2U_0603_6.3V6K
VTT_VCC 4 13 LG_VTT PL701
VCC LG 0.36UH_PCMC104T-R36MN1R17_30A_20%
1 2 +1.1V_VCCPP

AON6704
ISL6268CAZ-T_SSOP16

1
AON6704
PC707 12
PGND

PQ702

PQ703
2.2U_0603_6.3V6K

2
PR706 PR707

330U_D2E_2VM_R6M
1
0_0402_5% 4.7_1206_5%
C VTT_EN-1 VTT_ISEN 1 + C
<33,37,38,42> SUSP# 1 2 5 11 2

1 2
EN ISEN VTT_SNB
4 4

COMP

PC709
FSET
PR709
1

VO
2.21K_0402_1% PC711

FB
PC710 680P_0603_50V7K

2
@ 0.1U_0402_16V7K
2

10

3
2
1

3
2
1
Rds=2.3~3.2mȍ

1 VTT_FSET
VTT_FB
VTT_COMP

22.1K_0402_1%
1

42.2K_0402_1%

2
PR710
VTT_COMP-1

1
PR712

PR711
PC712 10_0402_5%
2

0.01U_0402_25V7K
22P_0402_50V8J

2
1

6800P_0402_25V7K

1
PC713

1
PC714

PR715
0_0402_5%
<7> VTT_SELECT 1 2 1 2 VTT_FB-1 2 1 VTT_SENSE <7>
PR713 PR714
35.7K_0402_1% VFB=0.6V 1.62K_0402_1%
1

B H_VTTVID1= Low, 1.1V PR716 B

1.96K_0402_1%
H_VTTVID1= High, 1.05V
2

PJ702
+1.1V_VCCPP 2 2 1 1 +1.1VS_VTT
@ JUMP_43X118

PJ703
2 2 1 1

@ JUMP_43X118

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.1VS_VTT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 09, 2010 Sheet 45 of 48
5 4 3 2 1
 5 4 3 2 1

change name

<8>

<8>

<8>

<8>

<8>

<8>

<8>
D D

GFXVR_VID_0

GFXVR_VID_1

GFXVR_VID_2

GFXVR_VID_3

GFXVR_VID_4

GFXVR_VID_5

GFXVR_VID_6
<8>
GFXVR_EN
+3VS

1
PR801

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
10K_0402_1% +5VS

+GFX_B+ PL801

2
FBMA-L11-201209-121LMA50T_0805

2
PR802

0_0402_5%
0_0402_5%

PR814

PR803

PR804

PR805

PR806

PR807

PR808

PR809

PR810
1 2 B+
2 1GFX_PWRGD PR811

10U_1206_25V6M
0.1U_0402_25V6
GFXVR_PWRGD

2200P_0402_50V7K

2200P_0402_50V7K
10_0603_1%

10U_1206_25V6M
@

1
+1.1VS_VTT

PC817

PC818

@ PC819

PC802

PC803
GFX_EN

31 GFX_VID0

30 GFX_VID1

29 GFX_VID2

28 GFX_VID3

27 GFX_VID4

26 GFX_VID5

25 GFX_VID6

2
1

1
PR812

5
6
7
8
GFX_VCC
@ 300K_0402_1% PC804
1U_0603_16V6K

32

SI4686DY-T1-E3_SO8
<8> GFXVR_IMON GFX_IMON
2

VID0

VID1

VID2

VID3

VID4

VID5

VID6
EN
0.056U_0402_16V7K

PQ801
24 PR815 PC805 4
1

PR813 VCC 2.2_0603_5% 0.22U_0603_25V7K

PC801

1
6.98K_0402_1% PWRGD
23 GFX_BOOST 1 2GFX_BOOST-1
1 2
1

GFX_IMON BST 0.36UH_PCMC104T-R36MN1R17_30A_20%

2
2

PC806 IMON GFX_DRVH

22 PL802
2

3
2
1
1000P_0402_50V7K DRVH
3
2

CLKEN# GFX_SW
21 1 4
C 4
SW +GFX_COREP C

1
FBRTN ADP3211AMNR2G_QFN32_5X5 20 +5VS 2 3
PVCC

5
1 2 GFX_FB 5 1
FB

330U_D2_2.5VY_R9M
PU801 19 GFX_DRVL 2 1 PR816

1
PC807 PC809 GFX_COMP DRVL 4.7_1206_5% +

PC811
6

TPCA8028_PSO8
220P_0402_50V7K 47P_0402_50V8J COMP PC808
18 LL=7m ohm

2
GFX_VCC 7 PGND 2.2U_0603_10V6K
2GFX_COMP-1 2 GPU 2 OCP=26A

PQ802
1 2 1 1 2 17 4

1
GFX_ILIM 8 AGND
VID:~1.25V

CSCOMP
PR817 PC810 PR818 ILIM PC812
33

CSREF
AGND Io(max)=22A

RAMP

LLINE

CSFB
1K_0402_1% 470P_0402_50V8J 20K_0402_1% 680P_0603_50V7K

IREF

RPM

2
RT

3
2
1
9

10

11

12

13

14

15

16
2

PR819
10.7K_0402_1%
GFX_IREF

GFX_CSCOMP

GFX_CSCOMP
GFX_RAMP

GFX_CSFB
GFX_RT
2 GFX_RPM
GFX_CSCOMP 1

PH801

1 2
80.6K_0402_1%

237K_0402_1%

340K_0402_1%
2

2
220K_0402_5%_ERTJ0EV224J~D
PR820

Avoid high dV/dt

PR821

PR822
Place RTH1 close to inductor
PR826
71.5K_0402_1% on the same layer
1 2 1

422K_0402_1%
1

1
2

PR825

1
PR823 PR824

1
0_0402_5% 0_0402_5% PC814
560P_0402_50V7K PR827
2

PC813 165K_0402_1%
1

2
1000P_0402_50V7K

2
PR829 2 1
1K_0402_1%
2

+GFX_B+ 2 1 GFX_RAMP-1 PR828

2

PR831 34K_0603_1%
B B
PR830 100_0402_1%
100_0402_1%
1
<8>

<8>

Connect to input caps

VSS_AXG_SENSE

VCC_AXG_SENSE
1

PC815 PC816
1000P_0402_50V7K 1000P_0402_50V7K
2

+GFX_COREP

Shortest the
net trace

PJ801
+GFX_COREP 2 1 +GFX_CORE
2 1
@ JUMP_43X118

PJ802
2 1
2 1
@ JUMP_43X118

(15A,600mils ,Via NO.= 30)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2010/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GFX_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 09, 2010 Sheet 46 of 48
5 4 3 2 1
 8 7 6 5 4 3 2 1

<7> PROC_DPRSLPVR

<7> PSI#

<7> H_VID6
H H
<7> H_VID5

<7> H_VID4

<7> H_VID3
+5VS
<7> H_VID2

<7> H_VID1

1
<7> H_VID0
PR902
10_0603_5% +CPU_B+ PL901
FBMA-L18-453215-900LMA90T_1812

2
<33> VR_ON 2 1
B+

2200P_0402_50V7K

2200P_0402_50V7K
0.1U_0603_25V7K
1
G G

499_0402_1%

10U_1206_25VAK

10U_1206_25VAK
1

1
PC902 +

PC903

PC907
0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

68U_25V_M_R0.36
1

1
1U_0603_16V6K

PC904

PC926

PC905

PC906
+3VS

2
5
2
+3VS
@

2
1

PR903

PR904

PR905

PR906

PR907

PR908

PR909

PR910

PR911
PR901 PQ902

3K_0402_5%
1.91K_0402_1% 3212_DRVH1 4 TPCA8030-H_SOP-ADV8-5

PR912
DCR=1.1mȍ ±7%

1
PU901

0_0402_5%
2

PR914 PL902

PR913
Layout note:

48

47

46

45

44

43

42

41

40

39

38

37
+CPU_CORE
0_0402_5% 0.36UH_PCMC104T-R36MN1R17_30A_20%
2

3
2
1
2 1 3212_CLK_EN# Boost Parts close 3212_SW1 1 4

VID0

VID1

VID2

VID3

VID4

VID5

VID6

PH0

PH1
PSI

VCC
DPRSLP
<12> CLK_EN#

5
PR915

2
+1.1VS_VTT

TPCA8028-H_SOP-ADVANCE8-5
PQ903
0_0402_5% PR917 PC908 2 3

TPCA8028-H_SOP-ADVANCE8-5
<12,15> VGATE 2 1 2.2_0603_5% 0.1U_0603_25V7K

1
PQ904
1 36 2 1 2 1
1

1
F EN BST1 PR918 F
3212_DRVL1 4 4.7_1206_5% PR919
@ PR916 2 35 3212_DRVH1 10_0402_5%
0_0402_5% PWRGD DRVH1 3212_DRVL1 4

1 2
2 2

2
<7> IMVP_IMON IMVP_IMON 3 34 3212_SW1

3
2
1
IMON SW1 PC909
@
1

470P_0603_50V8J

3
2
1

3212_CS_PH1
PR920 PC901 3212_CLK_EN# 4 33 1 PR921 2 3212_CS_PH1
4.99K_0402_1% CLKEN SWFB1
0.082U_0402_16V7K
2

CSREF
100_0402_1%
1

2 1 3212_FBRTN 5 32 +5VS
FBRTN PVCC
PC910 PC912 150P_0402_50V8J 12P_0402_50V8J

1
1000P_0402_50V7K 3212_FB PC913 3212_DRVL1 +CPU_B+
1 2 6
FB DRVL1
31 Close IC
$'3015*B4)1B;
PC911
1

PC914 4.7U_0603_6.3V6M

2
PR922 150P_0402_50V8J PR923 7 30
1.65K_0402_1% 39.2K_0402_1% COMP PGND
2

E E
1 2 1 2 1 2

10U_1206_25VAK

10U_1206_25VAK
2200P_0402_50V7K
0.1U_0603_25V7K
TPCA8030-H_SOP-ADV8-5
2 1 8 29 3212_DRVL2
5.11K_0402_1% TRDET DRVL2

1
PR924
PR925

PC916

PC917

PC918

PC915
+5VS 9 28 1 2 3212_CS_PH2

2
VARFR SWFB2 100_0402_1%

PQ906
3212_VRTT 10 27 3212_SW2 3212_DRVH2 4
VRTT SW2
DCR=1.1mȍ ±7%
2

+3VS
PR926 PR927 TTSENSE 11 26 3212_DRVH2 PL903
0_0402_5% 0_0402_5% TTSNS DRVH2 PC919 0.36UH_PCMC104T-R36MN1R17_30A_20%
PR929

3
2
1
0.1U_0603_25V7K 3212_SW2 1 4
1

12 25 2 1 2 1
1

@ PR928 GND BST2

2 3
CSCOMP

TPCA8028-H_SOP-ADVANCE8-5
PR930 499_0402_1%
CSSUM

SWFB3
CSREF

PWM3

1
2.2_0603_5%
RAMP

LLINE

TPCA8028-H_SOP-ADVANCE8-5
0_0402_5% 49
IREF

RPM

OD3
AGND ILIM
@ PR931
RT

<5,33> H_PROCHOT#
2

1
4.7_1206_5%
D 2 1 Layout note: D

PQ907

PQ908
13

14

15

16

17

18

19

20

21

22

23

24
Boost Parts close 3212_DRVL2 4 3212_DRVL2 4 PR932

1 2
2N7002W-T/R7_SOT323-3

@ 10_0402_5%
1

D
PQ909

162K_0402_1%

2
1

2 3212_VRTT PC920
3212_CSCOMP

3212_CSCOMP

470P_0603_50V8J

3212_CS_PH2
PR933
PR935

3
2
1

3
2
1

2
S 80.6K_0402_1% @
3

Avoid high dV/dt

CSREF
+5VS
2

1
1

PR934 PR936 PR938

2

PR937 69.8K_0402_1% 649K_0402_1% 1.91K_0402_1%

7.32K_0402_1% Connect to input caps
2
2

TTSENSE +CPU_B+ 2 PR939 1 Layout note:

C C
1200P_0402_50V7K
1

@ 1K_0402_1% Close to PHASE 1

71.5K_0402_1%
390P_0402_50V7K

2
PC921
inductor on the same layer
1

PH902
PR941

0.01U_0402_50V7K
2

@PR940 PC922
PC923

PC924

0_0402_5% 1000P_0402_50V7K 220K_0402_5%_ERTJ0EV224J~D

2

PR942
2

165K_0402_1%
2

CSREF 1 2

Layout note:
1

PC925
1

Close Phase 1 MOS 1U_0603_16V6K PR943 127K_0603_1%

@ PH901 2 1 3212_CS_PH1
2

100K +-1% NCP15WF104F03RC 0402

2 1 3212_CS_PH2
2

PR944 127K_0603_1%
B B

Shortest the 0603 package

VCCSENSE VCCSENSE <7>
net trace at least

VSSSENSE VSSSENSE <7>

OCP : 60A
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/10 Deciphered Date 2010/01/06 Title
Layout note: CPU_CORE
Close CPU pin THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 09, 2010 Sheet 47 of 48
8 7 6 5 4 3 2 1
 5 4 3 2 1

9HUVLRQFKDQJHOLVW3,5/LVW 3DJHRI

IRU3:5
,WHP 5HDVRQIRUFKDQJH 3* 0RGLI\/LVW 'DWH 3KDVH

D
 )RU(6' 3 $GG3'  (97
D

 )RU+:UHTXHVWUHPRYH9
V-803 3 5HPRYH9
V-803  (97

 %HFDXVHOLPLWHGKLJKLVQRWHQRXJK 3 &KDQJH3&IURPX)WRX)  (97

 $GG3535IRU*);B&25(VHQFH 3 $GG3535IRU*);B&25(VHQFH  (97

 &KDQJH%DWWHU\FRQQHQWIRRWSULQW 3 &KDQJH%DWWHU\FRQQHQWIRRWSULQW  (97

 &KDQJH35IURPRKPWR.RKP 3 +:UHTXHVW  (97

$GG3&RQ%20

 $GG3' 3 +:UHTXHVW  '97

 5HVHUYH&DSRQ%IRU5) 5)UHTXHVW  397

 &KDQJH35IURP.RKPWR.RKP
3 7KHUPDOWHDPUHTXHVWWRFKDQJH273WHPSFKDQJHIURPGHJUHHWRGHJUHH  397
&KDQJH35IURP.RKPWR.RKP
C C



B B













 20081022
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/10 Deciphered Date 2009/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NAU00 M/B LA-6101P Schematics
Date: Tuesday, March 09, 2010 Sheet 48 of 48
5 4 3 2 1