Unit 1 Control Design Cae cannEnnnI Ee ee 3.1 Introduction We know that the control unit is responsible for generating control signals which are provided to execution unit /data processing unit to carry out different operations. The signals are generated by a separate control unit which is designed to issue control signals (called internal control signals). The design of control unit will be studied in this Unit. In first two units we have considered design aspects of data processor unit. The data processor unit performs the various operations which are specified by instructions from ‘instruction set. These operations are performed in a predefined sequence. The execution of these instructions in'a sequence requires the control signals which act like activating signals and so, these signals are provided by control unit in sequential manner to various sub units of data processor unit. The control unit is used to fetch instructions from memory and decode them to find which control signals are to be issued, in what sequence they are issued to data processor unit. Thus the main function of control unit is :- (1) to fetch and decode instructions from memory. (2) to issue the control signals accordingly. The above two functions are based on the following concepts, () Instruction sequencing. (ii) Instruction decoding.3.2 Unit IIT Instruction sequencing is the manner in which various instructions in program are selected for inte sequence of instruction various control instruction sequencing is the way in which the processor transfers its contro] from one instruction to other instruction for step by step execution. These instruction are decoded or interpreted to know what is the operation pretation and execution. Depending on this signals are issued in sequence. Thus specified by these instructions and hence what control signals are required to be generated by control unit. 3.1.1 Instruction Sequencing [N.U.Summer 02/Winter 02] Instructions are stored in memory locations in the form of opcodes. Each of these locations have the address. These instructions must be executed in a specific sequence so that desired result or purpose for which any program is written must be solved. Thus, processor must process the instructions in sequence. The control unit which fetches the instructions one by orie must know the address of location where next instruction in programes stored. The easiest way to implement this logic is that every instruction must specify the next instruction address. So, when an instruction is fetched from memory by control unit it should contain the address of location where next instruction is present so that when the Current instruction is decoded the next address is known to control unit. This method was implemented in earlier generation computers. The obvious disadvantage of this method is that the length of instruction increases and it requires more number of bits to be stored in memory which Taises the cost of hardware, This is because the instructions now contain opcode field (operation specified )and address field (to fetch next instruction in sequence). Im advanced machines a special Purpose counter called program counter $ used which ot . Stores the memory location address where the instruction opco4® is present,Control Design 3.3 This PC (program counter) is auto incremented by one every time the Ut ; struction opcode is fetched. Thus, it automatically points to next instruction inst opcode. In case of program control transfer (for example CALL and JUMP instruc- break the new jump tions) where the sequence of execution is required to address where the next instruction. is present is loaded into PC an ing instructions from this address one by one. The id now processor starts fetchi program counter which is also called instruction address register. (N.U.Summer 99,02/Winter 00, 01] 3.1.1.1 Microprogram Sequencer the control The basic components of a microprogramme control unit are memory and the circuits that select the next address. The address selection partis called a microprogram sequencer. A microprogram sequencer can be constructed with digital functions to suit a particular application. The purpose of a microprogram sequencer is to present an address to the control memory and the circuits that select the next address. The address selection part is called a microprogram sequencer. A microprogram sequencer can be constructed with digital functions to suit a particular application. The purpose of a microprogram sequencer is to present an address to the control memory so that a microinstruction may be read and executed. The next-address logic of the sequencer determines the specific address source to be loaded into the control address register. The choice of the address source is guided by the next-address information bits that the sequencer receives from the present microinstruction. 3.1.1.2 Block diagram of microprogram sequencer The block diagram of the microprogram sequencer is shown in fig.3.1. The contro} in the d ion betwe | memory is included in the iagram to show the interaction een the sequencer and the memory attached t re two multiplexer qt d to it. There are multip! i Ts in the circuit. first multiplexer select: ress from one of four sources |. The fir: cts an addi ur34 Unit IID and routes it into a control address register CAR, The second multiplexer tests the value of a selected status bit and the result of the test is applied to an input logic circuit. The output form CAR provides the address for the contro} memory. The content of CAR is incremented and applied to one of the multiplexer inputs and to the subroutine register SBR. The other three inputs to multiplexer number 1 come from the address field of the present microin- struction, from the output of SBR, and from an external source that maps the instruction. Although, the diagram shows a single subroutine register, typical sequencer will have a register stack about four to eight levels deep. In this way, a number of subroutines can be active at the same time. A push and pop operation, in conjunction with a stack pointer, stores and retrieves the return address during the call and return microinstructions. The CD (condition) field of the microinstruction. selects one of the status bits in the second multiplexer. If the bit selected is equal to 1, the T (test) variable is equal to 1 ; otherwise, it is equal to 0. The T value together with the two bits from the BR (branch) field go to an input logic circuit. The input logic in a particular sequencer will determine the type of operations that are available in the unit. Typical sequencer operations are ; increment, branch of jump, call and return from subroutine, load an external address, push or pop the stack, and other address sequencing operations. With three inputs, the sequencer can Provide upto either address sequencing operations. Some commercial se- quencers have three or four inputs in addition to the T input and thus provide a wider range of operations, The input logic circuit in fig.3.1 has three inputs, I, 1) and ‘T, and three outputs, So, Si and L. Variables Sy and S,-select one of the source ad- dresses for CAR. Variable L enables the load input in SBR. ‘The binary valuesControl Design 3.5 of the two selection variables determine the path in the multiplexer. For example, with Sy So = 10, multiplexer input number 2 is selected and estab- transfer path from SBR to CAR. Note that each of the four inputs as lishes a well as the output of MUX 1 contains a 7-bit address. ‘The truth table for the input logic circuit is shown in Table 3.1. Inputs I, and Ip are identical to the bit values in the BR field. The bit values for $1 and So are determined from the stated function and-the path in the multiplexer that establishes the required transfer. The subroutine register is loaded with the incremented value of CAR during a call microinstruction (BR =01) provided that the status bit condition is satisfied (T = 1). The truth table can be used to obtain the simplified Boolean functions of the input logic circuit : Spey So = hIo+ IT L=hlbT Table 3.1 Input Log Truth Table for Microprogram Sequen cer BR Input M (UX 1 Field lh T Si: Sq ee 00 000 0 0 0 00 001 ool 0 ol 010 0 Oo 0 01 old 0 ou 1 10 10 x 1 oo ) 0 Li} ix D oi t The circuit 01 it can be cons; i a nstructed with three AND gates, an OR nates, Bate, and any,Unit Il Extemal [Incrementer] - Control memory Microops CD BR. a Fig.3.1: Microprogram sequencer for a control memory. 3.1.2 Stack Memory for Program Control Transfer When subroutines are to be executed in case of interrupts, the control of program is to be transfered to some other address. This is became the subroutine opcodes are stored at an address different from address of main program. Also, in case of conditional or unconditional branch statements, the normal sequence of execution of a program breaks and control is transferred to new address where the next instruction is present. In such cases (specially for execution of subroutines if nested loops are there) the control again jumps to main program after the subroutine is executed (by RETURN instructions). Thus, the address of main program, to which the Control is transferred must be known to processor i.e. it should be restored in PC.3.7 Control D TACK memo: pecial type of memory is used called mory ice. For this procedure a 5] mory but it functions like serial access me! which is a part of main me it operates on First In Last Out bi CALL or JUMP instruction is to be €: in stack by PUSH instructions. Then the subro} instruction is executed the return addresses are fetch isis. The locations are accessed serially. When xecuted the return addresses are stored utine is executed and when RET ed from stack by POP instructions. Thus STACK memories provide a very efficient tool for transferring pro- gram control from main program to subroutine 3.1.3 Design of Stack [N.U.Winter 04] We consider the design of stack memory of n words (i.e. » number of locations ). Each location can store a k-bit word. The k number of shift registers with left and right shift property are used and they are arranged as shown in figure 3.2. Each register is n-bits register. The leftmost end i.e. MSB of all the shift registers is defined as the stack top ie. Ist location in stack memory, and the:LSB ic. rightmost end is defined as last location in stack memory. The: first word which is pushed in stack by PUSH instruction is loaded in MSBs of all the registers. Now, the PUSH control (right shift ) i8'activated. So, the count of mod n Counter increases by one and the word is pushed to next location. Thus the Stack top becomes vacant to store next word. Similarly, when POP instruction is executed, the left shift/POP control is a word stored in MSBe of all shift registers is brought on’to data » the mod n counter is decremented by one. ae “ditional circuit to detect underflow and overflow, Underflow ek oa there is an attempt to pop a word from emply stack and overflow D there is an attempt to push a word in stack which is fully loaded. ‘hen the : Counter is storing count of 1, and if push line is activated overtow38 Unit IIT is detected and when the counter is storing zero and there is POP activateq then it indicates underflow. Sometimes, to control the stack operation the additional register-counter jg provided called the stack pointer, it contains the address of top most location of the stack. a Input data | —>—] —_— lines fee ree su Output’ * daz J <—_ lines 1 SR2 —& Teg SRk , a! y Up Push ight Shift) Signal Control Line. | "| tee PoP (Left Shift) Céunter Control Line Down Signal ae | Overflow Combinational [+ Indication bogie |» Undertlow Indication Fig. 3.2 : Implementation of StackControl Design = 239 _ 3.2 Hardwired Control [N.U.Summer 99,01/Winter 02] We have already studied concept of microprogramming. A particular opera- tion specified by the instruction opcode is divided into a number of micro instructions which are executed in predefined sequence and this execution results in execution of that operation. All these micro instructions are stored in memory called control memory. They are fetched one by one by control unit. Each of these micro instructions specify the control signals which must be activated so, that particular microinstruction can be executed. Number of such executions in sequence constitute one operation. Thus a control unit is designed to fetch, decode and execute the microinstruc- tions from control memory and is called a microprogrammed control unit. A microprogram is a sequence of microinstructions stored in control mem- ory. The control unit which is implemented to execute these microprograms is called micro programmed control unit. Design of such microprogrammed control unit is studied in this to in this topic. There are three different methods of hardwired design of control units, 1) State table method. 2) Delay element method. 3) Sequence counter method. 3.2.2 State Table Method In this method the behavioral description of control unit is written in the form of a state table. Constructing state table for control unit is first step. The behavior/function of control unit corresponding to data processor unit is written in the form of a flowchart or algorithm{ Each executable step in the ‘Towchart is called a state or intemal state represented bys, The control signals al y the con eT i Te generated by the control unit is,a sequence and these are called intemal3.10 Unit II control signals. There are certain control or activating signals which are provided externally called external control signals. The format of a state table is as under : Table 3.2 2 Inputs (1k ---~) States yh b 5 Si Su Zu S12 Z12 Sz S21 Z21 S22 Z22 Description : 1) The first column represents the states of the machine. These states are decided depending on the algorithm or the flowchart which is written for the function of data processor unit. These states are written in the first column, ~ 4 2)- The first row corresponds to the inputs. The total number of inputs are encoded by assigning binary itso them and itiey are written in the first row in the form of encoded binary number. These inputs are nothing but the control signals which are provided externally to the e control v uni 3) Thus, every row corresponds to internal state of machine and every column corresponds to externally provided control signals i.e. the inputs to the machine. The entry in the table- corresponding to any row i.e. State Sj and any golumn i.e. input Ij is written as 8,2Control Design 311 — j ; is the state of the control unit when it is provided the given inputs Tj and when it was in the state Sj previously i.e. when data processor unit is in state §; and provided the control inputs Ij_ we get next state denoted by Sj. Zj : It denotes the output of the control unit in the form of control signals which are generated. Thus when data processor unit is in state Sj and is provided with input control signals Ij, we get the output control signals from it denoted by Zij. Thus, a hardwired control unit can be implemented from the above state table knowing the next state and output of control unit, depending on previous state and inputs control signals to it. : Disadvantages of State Table Method : 1) Ifthe number of inputs i.e. control signals and / or the states of the data processor unit are more then the state table becomes tedious to construct and the computation of next state from previous state becomes difficult. 2) If there are loops etc. which are to be executed in the algorithm or flowchart then there is no special provision for this kind of behaviour in this method. 3) The design of control unit implemented using this method is difficult to debug. 3.2.2 Delay-Element Method {N.U.Summer 04] The control unit generates control signals in a predefined meaningful se- uence in such a way that when they are provided to the data processor unit the required instruction should be executed as a result of execution of number of microoperations one after another. Thus, all these control signals generated by control unit, going to data Processor unit are required one after another with some time lapse in between. The control signals are the clock pulses of fixed duration and amplitude.3.12 Unit IIT Now, consider the control signals C1 ; C2 ,C3 —— are generated sequen- tially at time ty , t2, t3 etc. ie. At time t1 + C1 is generated (first control signal at start). At time t2 1 C2 is generated (next control signal after time lag this time lag ist2-ti). , At time t3 : C3 is activated which is required next to C2 after a time lag of (t3 — tz) and so on. isa ats: tare a] i ot a ty c2 FL controt signals to Q the data processor unit: C3 (tg - ty) delay <> 4 (tg - ty) delay Fig.3.3 The delay between any two successive control signals must be synchronised ie. uniform, (; So, D-flipflop (delay flip flop ) are used to produce the delay. The D Flipflop Presents the output after a fixed delay time when input is provided to it. This delay time is equal to one clock pulse which is used to activate the D flipflop. Thus, all the delays between successive control signals are generated by D flipflops and all the D flipflops are activated by same clock signal so that the delays are synchronised.Control Design 3.13 ‘ontro| Signal Ci DFlip Flop | Control Signal Ci +1 ! Fig.3.4 In this method, there are as many D flipflops as the number of delays and only one D Flipflop is working at any point of time while others are deacti- time tj a delay of (tj + 1 - tj) time tj +] vated. The advantage of this method is that the control unit can be constructed directly from the flowchart of function of data processor unit. If the flowchart of unit is known then we convert that flow chart in time delay elements directly Bs 4 following some rules of conversion. The reason is that every box in flowchart Tepresents a function or a.microoperation and the corresponding control 4 signals which are needed to carry out this microoperation. We can introduce i delay elements between two successive blocks and construct control circuit from this delay element diagram. Rules of converting system flowchart into delay element diagram. 4 1) Any two successive microoperations require delay element in between. Some times the required microoperation is performed when a number of control signals are activated from delay element simultaneously. Thus, the signals can be ORed together using OR gate. 7 The input and output of delay element gives the two successive signals, directly which can be ORed together so that required control signal is Senerated, States in diagram below represent the microoperations.3.14 Unit IIT € Element Control i: Signal C Signal i+ 1 Fig. 3.5 2) The OR gate need not be shown in delay element diagram. It can be teplaced as follows. Signal i i Control wy pe — Signal C ; Signali+1 i+] Fig. 3.6 3 Thus lines merging together to form a single line indicates use of OR gate. 3) If there is a decision box in system flowchart ice. if there is transfer of control in program depending on some.condition to be satisfied then it can be shown using AND gate. ‘Two AND gates are used one of the AND gate is provided input or enabled if condition is satisfied and other AND gate is enabled if condition is not satisfied. Thus depending on which AND gate is active the flow of control is decided. x#lie. X=0 NO NO Fig. 3.7Control Design BIS Instead of AND gate one bit multiplexer can also be used which selects one out of the two inputs depending on control variable x = 0 or 1 as under . en shew Ifx = 0, I} is selected i 1 x~ IIgs selected Fig. 3.8 Thus using above rules of transformation we can construct directly the control unit from delay element diagram: Example From given flowchart of a unit construct the control unit using delay element method. State T (Generate C1) State 2 (Generate Cz) State 3 (Generate C3) Fig. 3.93.16 Unit IIT s BNO States are representing microoperations and C1 ; Cz etc’ denote the contro} points /signals which are to be activated by the control unit at different times, Construction of Delay Element Diagram : ‘The delay elements in above diagram are the D Flipflops. Thus, control unit is constructed by using a number of delay flipflop and taking outputs and inputs from them which constitute different control signals. (Begin) [—> C; (State S, is carried out) Delay Element D: [-—> Cp (State S2 is carried out after [Delay Element] - 3¢!ay by Di) D. x=1 x=0 ND) .NDy C3 (State $3 is carried out after a delay by Do andifx = 1 is satisfied) (Merging of lines at point A by OR gate) to next state Fig. 3.10 Disadvantages ; . System pulse in duration and magnitude. 2) Number of delay elements used are equal to number of DFFs which are Tequired to build up control circuit. The contro} unit becomes bulky due ‘S bul lui to this. Also, any one DFF is working at any time while all others are deactivated.Control Design 3.17 TTT 3) Ifthere are many delay elements and they are having propagation delays then the resultant propagation delay when signal travels through all delay elements become considerable and the control signals are not synchro- nised 4) Implementation is expensive and complicated. 3.2.3 Sequence Counter Method . [N.U.Summer 04] In this method a mod - k counter is used and its output is connected to a decoder. When the counter starts counting the states successively after a delay between two states ( which depends on system clock) the output of the counter presents these different counts. The decoder gets these counts one by one as the inputs. It decodes these counts and depending on input activates one of the output lines. When a particular output line is activated we get a clock pulse of fixed duration and amplitude on that line. This signal is called phase signal. Thus as the count of counter progresses we get one out of many otitputs of _ decoder activated with a clock or phase signal generated on it . This phase signals are represented by $i - / Generally, there are externally provided control signals like Begin, clock, end or reset using combination of logic devices we can control the counting process of the counter i.e. we can reset the counter or we can stop its function or we can enable it to count the sequence. Generally, the function of external control signals can be specified as under, 1) Begin : Clock pulse on this line enables the counter and its starts counting the states in sequence thus generating phase signals. . J 2) End : Clock pulse on this line resets the counter. It is activated when given task is over. 3) ‘Clock : When this is activated, only then counter starts counting states 4) Reset : This is external rest signal provided which can stop function, of control unit asynchronously at any time.318 Unit IIT Advantages = i 1) If there are loops or repeated steps in system flowchart we require less hardware to implement then in this method. BEGIN Count Enable )}— ‘Sequence counter END —F yp} Reset Line | Mod CLOCK Reset Decoder_| . ok decoder Enable Phase signals generated Fig3.11 The output of decoder is as under, oP line 1 or fs lveubine dots rad neiins line 2 oP 8. Fig.3.12 ‘Thus the phase signals are synchronised with system clock in duration and magnitude and they are generated by decoder depending on the input given to pers k it (which is decode by k : 2* decoder). The output of the counter (k lines) which is provided as decoder Inputreflects the state hold by counter which is counting clock pulses at input. The phase signals, f decoder ar te the contro! ; Phase signals/output of decoder are provided to generate the control signals directly i ich are r in gt irectly or indirectly which are then given to data processor unit. I the next secti i ton implementation of control unit for multiplier is considered.Control Design 3.19 ss 3.3 Design of Control Unit For Multiplier (N.U.Winter 00] We have studied the multiplier circuit for binary numbers represented in 2’s compliment form. The algorithm for this circuit is as under, DECLARE REGISTER A(0:7), M(0:7), Q(0:7) COUNT (0:2) F DECLARE BUS INBUS (0:7) OUTBUS (0:7) BEGING : A 0,COUNT<0,F <0; INPUT : M¢€ INBUS; Q < INBUS; ' ADD 2A (0:7) < A(0:7) + M(0:7) XQ (7); F <— M(0) AQ(7) VF; a RIGHTSHIFT : A(0) < F, A(1:7)Q <—A.Q.(0:6;) IF COUNT = 6 THEN GO TO CORRECTION; COUNT < COUNT +1, GOTO ADD; CORRECTION : A (0:7) < A(0:7) - M(0:7) XQ (7), Q(7) <— 0; OUTPUT : OUTBUS < A; OUTBUS < Q; END: The above algorithm multiplies two 8-bit numbers in two's compliment form. The logic is already explained in previous chapter. From the algorithm we can list out the possible control points for the circuit as under. Co For loading the value of Flip flop F which contains sign bit of the product to MSB bit of A. Control signal called ‘shift’ input provided to the register pair A.Q. to q shift it to right side by one bit . . ster A i.e. for loading For transferring the output of parallel adder to regi the partial product. C3 For loading the parallel adder left input from register A- & naan demas cit PETES3:20 Unit II C4 For loading parallel adder right input from register M. Cs For loading 0 to Qc7 bit of register Qa C6 For transferring part of result stored in register A on to OUTBUS. Cy For transferring part of result stored in register Qon to OUTBUS. Cg For transferring input (8 bit binary) in 2’s compliment form from INBUS to register Q i.e. the number x is loaded in Q from INBUS. Co For transferring binary number Y from INBUS into register M. Cyo This control signal is used for following operations simultaneously. It is a input to register called ‘clear input’ which loads 0, (1) Clear A (2) Clear COUNT (3) Clear Flipflop F. C31 Control signal used to increment the count register COUNT by one. All the control signals which are listed above are implemented physically in the block diagram of multiplier as under, according to their functions. Every control signal provided to different points from the list is responsible for initiating certain action or performing particular operation. There are some operations which take place simultaneously i.e. in the same clock cycle and hence are provided the same control signal for example C19. The external control signals are signals provided externally to the circuit BEGIN signal is a clock pulse when given, is required to initiate the complete circuit to perform multiplication. The comparator is used in control unit alongwith COUNT register to count cee ane of add-shift operations. The COUNT is incremented d € loop is executed. The content of COUNT register 35 ae Nn : uD ao is equal to 6. When contents of ‘0 6 i.e. 110, both the numbers are compared byco ich gi comparator which gives output equal to 1. This output is provided as control signal to change the flow of control and called as COUNT 6.Control Design 3.21 M(0) C3 Is 1 | | Left /P Right /P | i I i { Parailel eG ‘Adder le--f-- = Output“ Input and (->¥ output | LOUTBUS data bus INBUS ] Extemaly BEGIN __ ircouNT~6 | ovided provided J END sey Intel signals | CLOCK __ ae *conttol 107 signals Fig. 3.13 3.3.1 Flowchart For Multiplication The algorithm explaining the logic of multiplications of 2’s compliment numbers is given above. To start with design of control unit for this multiplier, which is used to generate the control signals, the first step is to draw a flowchart. In this flowchart every operation or step in the algorithm which takes place in one clock cycle is included in one rectangular box.3.22 Unit IIT Thus all the operation specified in one block are those which are being performed simultaneously. Each such rectangular box is called a state and given the state numbers S; S2 etc. Now, the control signals are required to carry out each of these states. These "control signals are written with the state. e.g. state So is begin, it requires no control signal (Begin itself is a control signal provided externally). Next operation in algorithm is A <- 0, COUNT <0, F< 0,M < Inbus, All these operations are separated by (,) comma and represent simultaneous as parallel operations, : So, all these are given state S1 and included in a box. For these operations we require control signals Cy anid Cio where Co is used to load M and Ciois clearing A, COUNT, F. So, Co, Cio are written at box called state S). In algorithm there are certain conditions which when satisfied change the Program control, for example if COUNT Tegister becomes equal to 6, then goto output state 9 correction state. : Similarly if Qc bit is 1 change the sequence. Such decision making state- ments are included in diamond. for and they are not given the state. Because they are not the operation being performed but they are the test conditions and change the sequence of execution depending on decision YES or NO. Thus the flowchart contains the States i.e. oj Control Signals : Which are Tequired to Test Conditions ; perations which are performed. Perform above operations. Which are not the states but control the sequence of execution. : All the simultaneously or parallel operations are included in one box and given same state number but they ma 'y Tequire different control signals to initiate them. control is transferred.Control Design 3.23 ‘Thus we draw the flowchart for above system (multiplier). This flowchart is used as a first step in designing hardwired control unit. ABM Ane 0 JOUTBUS =X Qa) circuit to be 0 COUNT 6 designed m ®) foe Cy tf at Fig. 3.15Control Design 3.29 ae a a ee 6) Thus to summaries we design a combinational circuit N with input as external inputs and present state status of J K. flipflops output is the control signals END, Co, C; etc. Also, the next state which is entered after the present state is given on output side. These are values of J & K input of flipflops. Step 6: For construction the above circuit, the state transition table is required. This table represents output of block N depending on the external input and present state variables Qi Q2 Q3. Thus there are two parts Input and Output. Input consist of BEGIN , Qc7) , COUNT 6, Qi, Q2, Q3 and output consist of END, Co, C1, ——Ci1, Ji Ki, Jp Ka, J3 K3 ete. To fill up the entries, first the input combinations and the present states are written. Then depending on the previous state the corresponding control signal entries are made and next state is decided on this basis, the J, K output columns , are filled up. For this the state transition or excitation table for J K flip flop is used. The format of transition table is given as under. Inputs Outputs ] BEGIN | Qc7)| Count 6 | Qi | Qz | Q3 END NiKi} J2 Ka |J3 Ks} CoC - Cio Cur ——__L 3.3.3 Delay Element Method [{N.U.Summer 99/Winter 01] We have already studied the rules for transforming the system flowchart into the delay element diagram. Based on these rules we can draw the flowchart for delay element method and implement the hardware circuit directly from this flowchart. The hardware circuit consist of D flipflops which are used to produce delays. The output of the designed circuits are the control signals.3.30 Unit IIT These control signals are directly taken out from input and output of delay elements i.e. D flip flops. Apart from these, the logic gates are used in the diagram. END C9 Cy Co, CAC ACS) CoCr Cy Fig.3.16 : All NAND one-hot design for the multiplier control unit 3.3.4 Sequence Counter Method [N.U.Summer 00,02] In this design method a counter is used Specially for executing loops in the algorithm. If there is a particular action or sequence of actions to take placeControl Design 3.31 repeatedly in the algorithm then accordingly the counter is chosen whose mod is equal to the number of times loop is executed, In algorithm of multiplier the add and shift operation takes place seven number of times is in the algorithm apart from the add shift loop which is executed seven times there are some operations which are not the part of this loop. Thus the complete of multipli- cation algorithm is divided into three main parts, one of which consist of the add- shift loop. ‘These parts are as under ( refer flowchart) , Cycle 1 : It consists of states So , S1 , S i.e. resetting the control unit and loading the inputs into registers M and Q. Since there are three states, state So does not require any control signals i.e. only two states $1 & S2 are there which need control signals. Thus these two states need two clock cycles at the beginning. Cycle 2 to 8 : This consists of forming the product which includes the add and shift operations. Since this loop is executed seven number of times it requires seven cycles for execution. Thus cycle 2 to 8 are allotted to this part of flowchart it includes repeated execution of states S3 , Sa, Ss. Cycle 9 : At the end of algorithm state So is correction step which is executed and the results are transferred on the output bus from register A & Q i.e. state Se. S7 and Sg. These operations are included in one cycle i.e. cycle 9. ~ Thus we require 3 different steps of execution. In first step, cycle one is executed. In Second step cycle 2 to 8 are executed (loop executed seven number of times). In Third step cycle 9 is executed. So, for one multiplication process we require nine cycles in sequence given above. Multiplier Design : We have divided the algorithm in three steps, hence three flipflops (S-R FF) are used to identify these 3 steps such that first flipflop is set when first is carried out. First is reset and second FF is set when step 2 is carried out. First and second are reset and third FF is set when step 3 is carried out. Step 1 consists of cycle 1, Step 2 consists of cycle 2 to 8.3.32 2 3) 4) Unit IT Step 3 consists of cycle 9. A modulo - 3 counter is selected for generating the phase signals which are clubbed together logically such that the actual clock signals or control signals are generated and provided to the data processing unit. The three phase signals $1 $2 and $3 are generated by the sequence counter which are used to activate the AND gates. The AND gates are required to generate the control signal outputs depending on the status in algorithm. Generally number of AND gates are equal to the number of states or total number of operations which are to be performed by multiplier. Since there are two states in the first State hence , we require 2 AND gates; one for each state S1 and S2 ), When AND gate (1) shown in following figure is activated it must generate control signals Cp. and Cio as these are required to carry out operation of clear and load specified by state Si. When AND gate (2)is activated it must generate control signal Cg so that the operation of loading Q is performed. The OR gates are used on the output side with AND gates. The control ._ Signals generated may be required for more than one operations or states, 5) 6) such control signals are of obtained at the output of the OR gates and Inputs to the OR gates are given from. corresponding states or ‘operations. The AND gates get there inputs from Sequence counter i.e. the phase signals, the three flipflops and external control si ignals that are provided to the control unit. In one cycle phase signal $1 is active and it enables AND gate (1) thus generating control signals Co & Cig to perform state S; . The other input to this same gate is from FF1 which is activated by the begin signal BEGIN when next Phase signal $2 is generated and AND gate 2 is enabled. Both these AND Bates have second input from Q output of FFI which is set fill BEGIN is active,Control Design 3.33 7) When operation in state S2 is over, it resets the FF1_ and sets FF2. Now next sets of AND gates are enabled duc to Q from FF2 and phase signals $1, 2, $3, becoming active respectively. This process continues . 8) There are three external inputs BEGIN, Qc7) and COUNT 6. 3.4 CPU Control Unit 3.4.1 Hardwired Design (N.U.Summer 04] We have discussed CPU in its most'simplest form in the earlier sections. This CPU is considered to execute only several instructions which are general form of instructions in any instruction set. Thus this CPU resembles, RISC proc- essor. These instructions are all one-address-field instructions. Eight instruc- tions are included in the set. Table : 3.5 Instructions Operati ] peration Performed 1 LOAD x |Load contents of memory location to x accumulator | ACE M(®) 2 | STORE x |Store contents in accumulator AC to memory location | of address x M (x) — AC 3 | ADDx |Add contents of memory location x to accumulator and | store result in accumulator AC <— AC +M (x) , 4 | AND x Logically AND contents. of memory location x to accumulator and store the result in accumulator’ __| JAC — ACM M(x) (A > represents AND ing ) 5 | JUMP x |Jump to memory location of address x unconditional] jump PC « x 6 | JUMPZ x |If accumulator is zero jump to addre: i 8 conditional jump PC & x ifAC = Compliment every bit of aceummilator AC — AC Right shift the contents of r by one bit. |3.34 Unit IT Alll the above instructions are such that they can be operated by the general purpose register level organisation of CPUc. Also, the accumulator is consid- ered as one of the source and destination by default. Now, the algorithm is written for executing each instruction physically using hardware. The execu- tion of all these instruction is divided into two cycles, (1) Fetch Cycle : In this the opcode stored in memory is fetched by CPU. Fetch cycle is common to all of these instructions. (2) Execution Cycle : In this each of the specified instruction is executed or the operation specified by it is carried out. The execution cycle is different for different instructions. Each instruction divided into smaller operations called microoperations or microinstructions such that these microoperations should get executed in one single clock cycle. Thus execution of one single instruction is carried out by executing a number of microinstructions in meaning full sequence. So, a flowchart is written for executing each instruction whose execution cycle consists of these micro instructions written in consecutive boxes. The cight instruction in the set have the fetch cycle common i.e. this operation is "performed by CPU in a similar way for all instructions. So, in the flowchart all these instructions are shown combinedly with different flowchart to repre- sent the execution cycle. These microoperation ie. each step in the flowchart is used to describe the control signals which must be generated by control tinit to carry out these micro operations. Here, the control points and control signals for execution of microinstruc- tions are listed out. These control points are implemented in the block diagram (at register level) of general purpose CPU. In the above flowchart the fetch and execute cycles are shown clearly the fetch cycle consist of transferring the address present in PC, which in the address where opcode is stored into Address Register AR. The opcode isControl Design 3.35 fetched from this address and it is decoded by instruction decoder. The opcode is interpreted and executed in execute cycle. Execute cycle is different for different instructions in the flowchart the instructions shown in execute cycle are of general form and rest of the instruction can be shown on the same lines. AC in flowchart means the accumulator, x is the address of the memory location, M (x) means the data stored in the location of address x. 3.4.2 Flow - Chart No YES PC AK Fetch x Cycle Fetch OPCODE x PCH PCI I Decode OPCODE LOAD Instruction ‘ADD R SHIFT ¥. —*— ARE X AR & X ¥ Read x Read x ¥ ACEAC + m(x) SHIFT AC ¢§—— 4s Fig 3.1736 Unit I 3.4.3 List of Control Signals In the flowchart the micro instructions which are written ina box get executed in one clock cycle in most cases. Thus we need one control signal i.c. one clock ; cycle to execute each of these control signals. So, the following list of contro} points are listed depending on the flowchart. Table : 3.6 Control Operation Performed Points 1 Co__ |For addition instruction. Addition of memory content to accumulator. 2 Cy |For logical AND instruction. Memory contents are AND ed to accumulator. 3 C2__ |For logical NOT instruction. Complimenting contents of accumulator. 4 C3 [Read instruction. This control signal is required to read the contents of| memory location “4 5 C4 | Write Instruction. This control signal is required to write data at a memory location. 6 Cs | This control signal is required to transfer data (address) to the program counter. 7 Ce | This control signal is required to increment the program counter by one every time opcode is fetched. C7_| This is required to right shift contents of accumulator. All these control signals are required to execute the instructions listed out using general purpose CPU. These control signals can be implemented in a control unit which can designed using any one out of the three hardwired design methods discussed earlier. JE Microprogrammed Control —_[N.U. Summer 02,05/Winter 99] In the previous sections we have studied design of control unit using three methods of hardwired control i.e, State table method, delay element method and sequence counter method, In this section we study microprogrammed control design. In this method the L control unit is considered as a small unit which can store the microin:Control Design 3.37 written in a meaningful sequence and then execute them in sequence. The execution of these consecutive microinstructions is carried out by control signals. So, when a particular microinstruction is decoded and executed it results in one or more control signals, which are activated or generated. These control signals which are thus generated in control unit are then provided to the data processor unit, so that the micro-operation specified by that microin- struction is performed physically. These microinstructions written in a defi- nite sequence constitute the microprogram. This microprogram when executed results in execution of a single instruction in the data processor unit. For this the instruction is divided into a number of small subinstructions or operations which when executed in sequence constitute the instructions. Generally these micro instructions or the microoperation are such that they need only one cycle for their execution i.e. single cycle execution. Thus for one instruction a microprogram is written which consists of a number of microinstructions. For each of these microinstructions, control signals are required and they are generated by the control unit. These control signals are very large in number selecting these control signals for a particular micro instruction is a very complicated process. Thus if using the hardwired control, this control unit is implemented, the design becomes very difficult and complicated. If the instruction set of the processor is now required to be modified or if there is any problem in the execution of current instructions then it becomes difficult to change the hardwired design of the control unit. So, to overcome the difficulty of hardwired design, the method of microprogramming is used to design the control unit. In this method of design the process of selection and activating the control signal in sequence is carried out by waitting the microinstructions ina sequence No form the microprogram. These microinstructions directly or indirectly (specify the control signals. The microingtructions are Stored in RAM or ROM3.38 Unit IIT type of memory in control unit. This section of control unit is called control memory or CM. Now, the microinstructions which are stored in CM are fetched by the control unit one by one ina sequence just like the processor (CPU) fetches instructions, These mieroinstructions are decoded to specify the contiol signals {hat are required to be activatedand the a address where the next microinstruction i in the sequence is stored. Then the control unit activates these control signals and they are provided to’the data processor unit for further actior’. The microin- struction, opcodes are stored ii inf the control memory CM. If there is any microinstruction which is modified or there is error in execution of microin- struction, ‘the microprogram which js in CM can be easily changed or modified. Thus this method of design is very flexible and easy to implement. Though it requires some extra’ cost of implementation as compared to the hardwired control unit design. It is more flexible and easy to implement. Q.1) Write a brief note on microprogramming. What are the various Ways to increase speed in microprogramming ?_[N.U.Summer 04,05] Ans : Two general techniques for interpreting instructions have been identi- fied :- hardwired control and microprogrammed control. Hardwired control units employ fixed special-purpose logic circuits to generate control signals. mploy fh P' Irpo Lits to generate control sig In a microprogrammed control unit, control signals are stored in the form of microinstructions in a special addressable memory éalled the control memory. Microprogramming has two major advantage : 1. It provides a systematic method for control unit design.-—~ 2. Since instructions are interpreted by microprograms, an instruction set can easily be changed by changing the microprograms. “Thus the behaviour of a microprogrammed control unit can be altered by software rather than by hardware changes. On the other hand, micropro- rammed control units are generally somewhat larger and slower than the g : . : . corresponding hardwired units.Control Design 3.39 It can be made footer by using (i) Parallel processing (ii) Footer memory devices. 3.5.1 Difference between Hardwire and Microprogramming [N.U.Summer 00,05/Winter 01,04] Microprogramming is a technique for implementing the control function of a processor in a systematic and flexible manner. Microprogramming may be considered as an alternative to hardwired con- trol. A hardwired control unit for a processor is typically a sequential circuit with the general structure shown in Fig.3.18. A microprogrammed processor control circuit has the structure shown in Fig.3.19. Each instruction of the processor being controlled causes a sequence of microinstructions, called a microprogram, to be fetched from a special ROM or RAM, called a control memory. , The microinstructions specify the sequence of microoperations or register transfer operations needed to interpret and execute the main instruc- tion. Each instruction fetch from main memory thus initiates a sequence of microinstruction fetches from control memory. Microprogramming provides a simpler and more systematic way of design- ing control circuits and greatly increases the flexibility of a computer. The instruction set of a miroprogrammed machine tan be changed merely by replacing the contents of the control memory. This makes it possible for a microprogrammed computer to execute directly programs written in the machine language at a different computer, a process called emulation. Mi- croprogrammed control units tend to be more costly and slower than hardware units, but these drawbacks are generally outweighed by the greater flexibility provided by microprogramming. Because of the close interaction of software and hardware in microprogrammed systems, microprograms are sometimes referred to as firmware.3.40 Unit HT Clock . Sequential Control : logic signals Status circuit fe signals processor from processor’ Instruction Tegister Fig.3.18 : A hardwired control unit. ‘Address Clock generation cireuit Status signals from Processor Control 7 i: oe Fare register Processor Fig.3.19: A microprogrammed control unit. 3.5.2 Emulation (N.U.Summer 03,05] When 2 computer center mothballs its old computer and gets a new one, the problem of portability becomes acute. Some of the users may have foreseen this transition and written all their Programs with portability in mind. They will have few problems. Other users will have programmed only in problem- oriented languages, without thought of portability. These users will have some problems, but as long as their languages are available on the new machine, they will generally manage somehow For the programs written in the machine language of the old machine or for compilers that translate special-purpose languages to the old machine lan- guage, the new machine spells disaster ‘These progams can be moved to theControl Design 3.41 new machine provided that the old machine language is available as one of the new machine’s levels. The most convenient way to accomplish this transition is to provide the new microprogramming level with an interpreter for execut- ing programs in the old machine language. If this strategy is adopted, the new machine will have (at least) two micro- programs : one for its own conventional machine level and one for the old machines. The interpreter for the old machine is usually called an emulator, to distinguish it from the native conventional machine level interpreter. Typical examples are the DEC VAX emulating the PDI-11 and the IBM 370 emulating the 1401. The most difficult part of an emulator’s job is emulation of the old /O instructions and devices. I/O instructions are normally carried out in parallel with CPU instructions and, unlike CPU instructions, I/O is strongly timing dependent. If the program being run in emulation mode makes assumptions about relative speeds, énsuring that it works properly on the new computer can be difficult. To illustrate the kind of problems that can arise, consider a program that sequentially read records from disk file into a buffer the same size as one record and processed them. To gain speed and save space, the program initiated reading the next record into the buffer before ‘it had finished processing the old record, knowing that the new data would not actually begin overwritting the old data for X milliseconds, due to the seek time of the old disk If then used these X milliseconds of finish up its processing just in time. If the new disk seeks relatively faster (compared to the speed of the emulated CPU) than the old one, the old data may be erased before they have been processed. Mallach (1975) gives an excellent introduction to emulation techniques, particularly emphasizing I/O emulation.3.42 Unit IL Be Wilke's Design [N.U.Summer 00,05/Winter 00} ‘The microinstruction is divided into two main parts. (1) Control fields (2) Address field The control field specifies the the control signals which must be activated by instructions directly or indirectly. The address field indicates the that micro address of the next microinstruction in the sequence. These microinstructions are stored in CM. Wilke’s design was proposed to implement the micropro- grammed control unit. It is the most simplest and straight forward way to implement control unit. Address provided externall Control memory Decoder aya) ay Address field ‘Control Signals in External control field Condition Fig:3.20 In this design eac ” en each bit in the control field of a microinstruction specifies one control signal directly. ‘ = 8} ectly. Thus if any bit in the control field of microinstruction is set or ‘1, then ynal ci : Control signal corresponding to that bit is activated and if'any bit is zero or reset then that ¢ ¢t then that control signal is disabled, Thus when a microin- struction is fetched then dey s fetched then depending on the number of bits which are set or 1 i the control field, corresponding control signals are generated or activated:Control Design 3.43 Thus, the total number of control signals required from the control unit 1 decide the number of bits in control field and in case of wilke’s design the number of bits in control field is same as the total number of control signals required. The Wilke’s Design is shown in the figure 3.20. 3.6.1 Control Memory (N.U.Summer 05] As shown in the figure the control memory section is organised as ROM - PLA structure that we have studied earlier. In the figure, the dots shown at intersection of grids shown the selected vertical columns. It consists of control field and address field. In the control field the number of vertical conductors or_columns is eqi | number of control signals. When a particular control signal is required to be activated that column is selected. The rows correspond to memory locations store the microinstructions. Thus in the figure there are eight rows, hence the control unit has a capacity to store eight microinstructions in a given sequence. The decoder selects the address i.e. row in which that microinstruction is stored. This microinstruction is stored in the form of control signals. So, when microinstruction is selected, those control signals which are required for its execution are activated and they are provided by the control unit. e.g. : when first microinstruction is selected, control signals Co & Cj are activated and so on. The address field forms a part of control memory section. The address field is used to store the address of locations of memory where the next microin- struction in the sequence is stored. Since there are eight locations shown in above unit, the address is of 3 bits, hence columns ag aj a2 are the address bits. When first microinstruction is selected i.e. first row is activated by the decoder, the control field consists of Co Ci and the address field will activate corre- sponding columns out of ao a! a2 such that it presents the next address where next microinstruction in the microprogram is stored.3.44 Unit HI 3.6.2 CMAR ~-This is the control memory address register which holds the address of the microinstruction temporarily, The address in the address field of CM is loaded in CMAR or sometimes the address selection is done externally irrespective of the address of stored in address field. This address is then given to the decoder which decodes the 3 bit address to select one out of eight rows which store the microinstructions. The microinstructions are’ written in a sequence and if there is a jump in the microprogram whether conditional or unconditional, the next address where the nextmicroinstructions is stored must be provided to CMAR. The switching clement S is provided for this. The external condition is set active if the jump is conditional jump. When this is done the switching element $ selects the jump address and this address is then loaded in CMAR to jump to that location, Im case of unconditional jump it can be implement using hardware in the address field of CM or it can be provided extemally to the CMAR. Generally, the external address lines provided to CMAR are loaded with Starting address of the first microinstruction, Thus, the wilke’s design of control unit with CM and suitable address decoding logic provides a very simple and straightforward way to micropro- gramming. But the main problem associated with this design is that the number of bits in the control field of control memory is equal to the total number of Control signals those are required for the Processing or execution of instruc ‘fons. This number is very large and hence the control field in CM has to be very large. Thus the implementation of control memory becomes costly. In the method microprogramme controls the size of control field in CM is the main area of concern to the designers as it decides the cost of the whole design- 3.6.3 Control Field Size The size of control field in CM directly depends on the total number of control signals that are required by the Processor, in case of Wilke’s Design.Control Design 3.45 But in other microprogrammed control units, as the concept of control memory is there, the control field size directly or indirectly depends on the total number of control signals that are tequired. Thus the size of control field must be optimized (it should be kept as small as Possible). So that the cost of design of the control unit should be less. The size of microinstructions which directly or indirectly store the control signals (and which is stored in the control field of CM) depends on the following factors, (1) Parallelism in microinstructions, (2) Length of control field of microinstruction. (3) Length of address field of microinstruction. 3.7 Parallelism in Microinstruction’ Many a/times there are a number of similar microoperations they can be carried out by writting only one microinstructions for it. Such microoperations are called parallel microinstructions. The number of such operations can be upto several hundreds. It may be the case that several number of individual micro instructions are written’ to carry out these parallel microoperations. Sometimes a single micro operation is specified by a number of microinstruc- tions. ‘In the processor a number of simultaneous operations are taking place. Thus at same instance of time a number of microoperations are getting executed If all such microoperations are specified by different opcodes them it is needed that for getting executed such parallel microoperations (at same time) differ- ent micro instruction are to be decoded and executed. df it becomes possible 'Q write only one opcode for all these microoperations which can take place Simultaneously in the data processor unit, then a lot of space in CM can be saved as these opcodes of microinstructions are stored in the control memory ‘ocations,3.46 Unit il eee But, if'a large number of such micro operations are specified by single opcode then it is needed that, this opcode be decoded in such a way that all the corresponding parallel microinstructions should get executed, Thus this op- code should be decoded to preferer ‘ea number of different operations and the decoding circuit becomes very complicated to design, ‘To avoid this problem total parallel microinstructions are divided into some 1 fields. Now ch of ruction opcode in these fields contain microaperations specified by, microi such a way th the other field. The control field of the microinstruction is now divided inton subfields and each of these fields cor ican be executed simultancously with any microoperation of na opcode, This opcode represents all the microoperations/micro instructions included in that § Thus by this mechanism designer tries to save the cost of control memory implementation because by specifying some of the total parallel microinstruc- tions by single opcode which is included in one of the subfields of the control field. The total space occupied by opcodes in CM is reduced, In this if there is one bit reserved for every control signal, then the width of location of CM may be increased. At the cost of the extra hardware which is required to decode the parallel microinstructions opcode, we achieve reduced size of control memory. Length of Control Memory Location : The microinstruction is divided into two fields as under, (1) Control field : Which stores the microinstruction opcode (2) Address field : Which stores the address of the next microinstruction in a microprogram : ro While designing the control unit using the method of microprogrammed * control, the cost of design is greatly affected by the control memory sectionControl Design 3.47 in control unit. The control memory is RAM or ROM type of memory which is used to store the microinstructions in the format shown above. Now. depending upon the number of bits required to represent the control field as Ee Phesent the contro! held as well as address field, the width of the control memory location varies. More number of bits in control field i.e. the number of bits in opcode of microin- struction which is stored in control field increase the width of the CM location. These microinstructions are written in the form of opcodes to specify the number of control signals which must be activated and provided to the data processor unit by the control unit, when that microinstruction is decoded and executed, so that the particular microoperation should get operated in the data processor unit. * Thus the control field directly on indirectly specifies the control signals. In wilke’s design we have seen that the control field of the CM contains as many columns as there are control signals in the unit i.e. the number of bits in the control field is equal to total number of control points in the circuit, as there is one to one correspondence. Thus; if there are a very large number of control signals in the unit to be designed, then the control memory section becomes very costly design and it is not practically feasible. To avoid this problem the total number of control signals which are required are encoded i.e. they are represented by less number of bits in the opcode. This requires reduced length of the control memory locations. We consider the following example to illustrate this point. Consider, that there is a register R which is to be loaded by some data from three different sources. Now, these sources are as under , Source - 1S Source -2 Sz Source - 3 $3 Register R-— destination3.48 ~ Unit dit For loading these various sources into the destination R we require control signals as under, Cy loads S} data into R Cz loads S2 data into R C3 loads $3 data into R Fig. 3.21 Now, the microinstruction is written so that these various microoperations can be performed. There are three control signals Cy , C2 and C3. If we decide to reserve one bit in control field for one control signal as in wilke’s design we should have 3 bits in the control field. Control field Now, the opcodes are designed for the three microoperation written above. Table :3.7 Opeode ~ | Micro Operation GO G oO 0.0 No operation Oo 0 1 Load S; into R 0 1 0 Load S2 into R , 1 0 0 |_Load $3 into RControl Design 3.49 Thus in the 3-bit opcode of the control field only above entries are valid and they represent the control signal that is activated corresponding, to the bit position which is set. Ifany other bit combination gets loaded then there will be unpredictable operation. Now, we consider the method of encoding , the control field of the microinstruction, In this there are total four microoperations which are to be carried out by the system. These four microinstructions are written using two bits which specify the opcode as under, Table : 3.8 Microoperation | Control signals activated 0 No operation No control signal 1 Load S) into R Activate Cj 1 0 Load S2 into R Activate C2 Load $3 into R Activate C3 Thus, there are only two bits Bz and B) which form the opcode and still they specify all the four microoperations which are specified by the earlier opcode of microinstruction. Thus the control field now needs to have only two bits, while in the previous case the requirement was of three bits. Also, there is no combination of bits which remains unspecified for 2 bit opcode. ‘The extra logic has to be designed in this case as the opcode is in the encoded form and as the microinstruction opcode does not specify the control signals to activated directly, a decoder is needed. This decoder decodes the 2 bit opcode and specifies which are the control signals that are to be activated , as under :3.50 Unit IIL B B, 1 anaes 2:4 decoder TTT 1 Cz ©g_ Noopperation Control field (opcode) Fig. 3.22 This example considers a very simple unlit. But in case of practical circuit of Processor which is highly complicated, the reduction in the number of bits in the control field due to encoding is highly appreciable. Hence, at the cast of decoder logic which is required in this case, the encoding is preferred. This teduces the width of the control field hence that of the control memory location thus reducing the cost of design. There are certain ways, the control field can be encoded as under, (1) Unencoded Control Field. n-1 LTTTUCTETCr yoe tT TT Trt4 Co Cy 20 sane - eee Cn-1 Fig. 3.23 In this type each bit in the control field is Tepresenting one control signal. Thus, total number of control signals derived from the control unit is equal to number of bits in control field. The control signals are derived directly fromControl Design 3.51 the control memory location and provided to the data Processor unit depending on the bit which is set, that control signal is active and if a bit is reset, that control signal is disabled. In this type the decoder logic is not required, but the number of bits in control field increases the cost. (2) Partly encoded control field Control field 1 Control field 2 Control field 3 Decoder Decoder for CF} for CF3 y ¥ v ¥ ¥ c Fig. 3.24 Total control signals which are derived from control unit. In the above method the total control field consists of a subfields e.g. CF7 , CF etc. These subfields are used to store the opcodes of the microinstruction in encoded form. Thus the control field 1 is used to represent some out of the total control signals. These control signals are then encoded and written in the form of opcodes in CF}. In this case the separate decoders are required for every control field CF1, CF2 etc. depending on the total number of bits in each field which is encoded. The output of decoder is the control signal directly, which are then provided to data processor unit. (3) Fully encoded control field In this type the complete control field is encoded i.e. it contains the opcode which can specifies all the microinstructions that can be written. In other words it encodes the total number of control signals that are derived from the control field. A single decoder is required to decode the opcode and all the control3.52 Unit HT signals are derived from the output of the decoder only. Thus, the hardware required is of less cost but the problem related to this method is that the parallel microinstructions can not be stored and it increases the length of CM. Control field Fig.3.25 Length of CM : If a number of microinstructions are there, CM space occupied is more. Thus effectively reducing the number microinstructions written for a microprogram reduces the length of CM. This can be achieved by writting parallel microinstructions in subfields as discussed above. 3.7.1 Instruction level and microinstruction level execution [N.U.Summer 03] Probably the key trade-off is how much encoding should be microinstruc- tions contain. If one were to build the Mic-1 ona single VLSI chip, one could ignore the abstractions such as registers, ALU, and so on, and just look at all the gates. To make the machine run, certain signals are needed, such as the 16 OE signals to gate the registers onto the A bus and the signals that control the ALU function. When we look inside the ALU, we see that the internal circuitry is actually riven by four lines, not two, because in the lower left-hand corner we find a 2-to-4 decoder circuit. In short, for each machine some of n control signals applied at the appropriate places can make the machine run, without any decoding.Control Design 3.53 en This point of view leads to a different microinstruction format : just make it n bits wide, one bit per control signal. Microinstructions designed according to this principle are allied horizontal and present one extreme of a spectrum of possibilities. At the other end of the spectrum are microinstructions with a small number of highly encoded fields. . These are said:to be vertical. The names come from how an artist might sketch their. respective control stores ; horizontal designs have a relatively small number of wide microinstructions ; vertical ones have many narrow microinstructions. Between these two extremes lie many mixed designs. Our microinstructions, for example, have a number of bits, suchas MAR, MBR, RD, WR and AMUX, that directly control hardware functions. On the other hand, the A, B, C and ALU fields require some decoding logic before they can be applied to the individual gates. An extreme vertical microinstruction might just have an opcode, which is merely a generalization of our ALU field, and some operands, such as our A, B, and C fields. In such an organization, opcodes would be needed for reading and writing main memory! making microjumps, and so on, because the fields that control these functions in our machine would no longer be present.