6.1 Introduction : Till chapter-5, we have covered basic concepts of microprocessor 8085; architecture and tardware interfacing to microprocessor S085. Now to co-operate with your practicals, it is ESSENTIAL 10 start with instruction set of microprocessor. An instruction is a command issied in the form of a bit pattem to perform a given task ona specified data. Each instruction basically consists of two The first part is called as OPCODE and the second is called as operand, The OPCODE part of an instruction specifies the operation to be performed. The operands either provides the data or specifies data. The operand can be specified in a number of ways. It includes : @ 8 BIWI6 bit internal general purpose register. (9 A memory location. (i) 8 bit port address/16 bit memory address. (js) Implicit operand : The operand is not specified, instead it is assumed in register. In 8085, we have varieties of instructions, therefore all instructions will not be of same byte size. The instructions vary from 1 to 3 bytes in length. For each and every instructions NUMBER of bytes will be specified. Actually, instruction set of 8085 is very big. So to study all the instructions and then use it will make the thing bit complicated. Therefore, we will study few, then use it. Study of new instroctions and immediately use it, this approach is used in this chapter. When we use it, there will be “flow of” instructions; one by one, This is nothing but referred as “program”, To represent “FLOW” of program, we use graphical presentation, normally refered as “FLOWCHART”. 6.2 Flowchart : The flowchart is a pictorial representation of various actions and computations that are taken to perform any task A flowchart is similar to a block diagram, representing the structure of the program. Flowcharts break large, complex programs into smaller logical units and make8085_Instruction sep ed for 2 thing I chat iS US sins roe the. prognam Tsic 10 others, Wig n be converted directly iggy s 5 Generally, MeetsieF to make changes and corrections. Gener » rmmanicate Ne hl claify the thinking process. (2) To comm Tan the Program stnicture clearly defined in. blocks. a SSUOF instructions, using any’ progemming langvae: sown in Fig. 6.1 Symibots commonly used in floweharting are 2 S eof Now ———+ Arrow ~ Incicates the direct! LT Paatetogram = 10 wit Rectangle - Indicates proc! ress operation Indicates predafined processes i.e. Subroutines | Double sided rectangle ~ Diamond unit - Decision unit Oval ~ Start and stop unit Fig. 6.1 : Flowchart symbols 8.3 Classification of Instruction Set Instruction ate generally classified into the functional categories as follows : 1. Data transfer group 2. Arithmetic group 3. Logical group 4. Branching group 5. Stack and machine control group 6. 1 Data Transfer Group : This group of instructions copies data from source to destination without modifying the Teale iy Ue Source. The various types of data transfer are possible between direct data, Tegisters and memory locations as follows la Data transfer Example 1. Between registers Register B -> Register D. 2. Specific data byte to register or a Data byte > Register B. memory location, Between memory location and register. Between an VO device and the accumulator 5._Between a register pair and the stack, 6.3.2 Arithmetic Group : This group of instucto ithme i : increment and decrement 1 PCM arithmetic operations. such as addition, subtraction, Memory location —> Register A. Input device -> Register A. Register_pair data — Stack locations.ssor_Techniques 6a eens Avy 8 bit diet data, conten of @)gdedisubtracted to/from accumulator accumlator The contents of register, memory location or 16 incremented or decremented by 1. The operation is from where it has taken data, Ex, Increment B rezister contents B reg. + 1 -> B reg 8085 Instruction Set Tegisters or the contents of memory location can be and the result of additionsubtraction is stored in the bit contents of register pair can be performed on data and result is stored 63.3 Logical Group : ‘This group of instructions perform logical operations such as AND, OR, EXOR, Rotate Complement cte (@) Any 8 bit direct data, contents of register or a memory location can be logically ANDed, ORed, EXORed with accumulator contents and result is stored in accumulator. Each bit in the accumulator can be shifted right or IeN by one postion at a time or al ‘he contents can be complemented ie, zera's replaced by 1's and I's by zemo's 4 Branching Group : ‘This group of instructions changes the path of program execution or sequence of program execution. The branching operations are of 2 types 1. Conditional and 2. Unconditional Jn condiionai branching, the micfoprocessor checks the condition of flags. If condition is satisfied then program control is transferred to branch address. If condition is not satisfied then it will ignore the instruction and will execute the next instruction after that In unconditional branching, no flags are checked and program control is transferred at the specified address directly. 2) Jump : The program control is transferred to specified address b) Call, Ret and Restart : The program control is transferred but the address of next instruction is stored on stack. These are generally used to call a subroutine or to return from subroutine, 6.3.5 Stack and Machine Control Group : ‘This group of instructions performs stack and machine control functions such as PUSH, POP, Halt, Enable/Disable interrupt, No operation. 64 Notation used in Instructions and Opcode : Notations used in instructions are ‘Notations Meanin M ‘Memory location pointed by HL register pair r S-bit register R, 16-bit register pair R Source register Ry Destination register addr | 16-bit address x S-bit data8085_ Instruction Ser Microprocessor Techniques oa Notations used in object code or OPCODE are : - = : | Notations | a 2 —_— 4 | ddd | Destination registers | | sss Source registers, ddd = sss= IID A 000 = B oor = C | 010 = D register | oll E register | 100 = H register 101 = L register nnn Restart number 000 to 111 i yy An 8 bit binary data yyy | A 16 bit binary data unit x Register pair 0 = BC 4 1 = DE Xx Register pair 00 = BC Ol = DE 10 = HL 11 = SP (if PUSH/POP) PSW PPQQ | A 16 bit_memory address Common format is used as follows : Description + It is used to cxplain the functions performed by an instruction, Operation + It is used to specify the exact operation performed by an instruction, Encoding + It is used go give the OPCODE format of the instruction and variations with OPCODES. No. of bytes: It is used to specify the number of bytes required to store the instruction in memory, : Addressing mode : It is used to specify the addressing mode in which it is operating, (This mode 1 will explain you, once we finish with instruction set), Flags + It is used to specify the status of various flags available. Example + It is used to give idea about changes in registers or memory locations because of an instruction. Now we will start, study groupwise 6.5 Data Transfer Group : ‘The data transfer group of instructions include following instructions : 1. MOV Ry R, 2. MOV R,Mand MOVM,R 3. MVIR, data 4. MVM, data 5. LXI Ry, 16 bit data 6. LDA address 7. STA address 8. LHLD address 9. SHLD address 10. LDAX R, M. STAX R, 12. XCHG 13. IN 8 bit address 14. OUT 8 bit address,yr cessor Techniques 65 a (ee Or, ww 65! MOV Ry Ry: ccigtin —¢ MOV is an abbredaion of MOVE. pe This instruction copies data from KR, source register to Ry destination register. The examples of R, and Ry are all general purpose rests such as A, B,C, D, E, H and L, The contents of source register ve pel altered. operation 2 Ro Ry Encoding : Loldddsss For MOV B, A — ddd = 000, sss = 111 foroooiit|> 47H No. of bytes : 1 byte ‘Addressing mode ; Register addressing, Flags + No flags are modified Example + MOV A, B: The contents of B reg are copied to A reg, Suppose A = 20, B = 10 and instruction MOV A, B is executed. Contents before execution of instruction Contents after execution of instruction Lue Ss AC PCY if F 5 a é 8 c c D iE E H L L Examples of instructions are : Mov B. | B | C D E H L_[ A movc. | B | C D E H L A Mov p, | B | C D E H L A_| Move, | B | C D E H Di A Mov H, | _B c D E H L A Mov, | B_| C D E H Li A mov aA, | B [| C D E H L A 65.2 MOV R, M or MOV M, R: Mov R, M Description ‘This instruction copies data from memory M to register R. ‘The term M specifies the HL memory pointer, The coments of HL register pair are used as address and the contents of that memory location are transferred 10 specified R i.e, register. Examples of R are all general purpose registers, such as A, B, C, D, E, H and L.> Mlctupnncesson techniyins Operstion 5M ota hy ol Vacating , an a Vor example, POV CIA da oraostin | =» ABB No. of Nytew OT byte Adievsing made + fwduect wbdvesing Aaa 1 No flags se: modiied ichinn, We TMMONY 6 Nole <1. Whenever If tam comes any mesiuchion, At i address will be quien by HL pait ; 2 Brackets arent HL species Mit ie conten {he brackets wil be used to spe Fxampte : MOV 13, “4 B rp = W a men IN cote HL, pat are OHO, WE om 2) Ht adios COO WON is stored and instruction 140" a 1. Contents bators srecuton of instruction LY Ye snes Dats I insttuction Moy BLM, the data is transferred from memory to B register. The HL fre wed as address ie. IL = COWO H. The contents of memory location ruisferred to B reyister, xo BE register contents will change from 20 H to 10 H, Examples of instructions arg : MOV 8 | Moy cin MOV D,M ;MOVE,M; i CM Movi aa AM MOV MR Description + This instruction copies data from R register to memory Mt. ‘eeistér pair are used as memory address. dnd the contents of specified register are transferred to that memory location Operation * RM or Ro(HL) Encoding : [otirosss For MOV M, C = sss = 001 = C reg 9llio001] 5 ay No. of bytes 1 byte Addressing mode : Indirect addressing. Flags No flags are modified,microprocessor Techniques 2085 Instruction Set yaample » MOV MCC Suppose the contents of HL pair are C 200, C reg = 20 H, at address 200 1011 is stored snd instruction MOV M, C is executed. Contents botore oxacution of Instruction Contents after execution of instruction 7, ACP CY i Ou Autre! Oat | i TOA, 8 20 |c cer B _.|& + 6200/7107 D nf ce, Con} cao a 20] In instruction MOV M, C the data is transferred from C register to memory. The HL register pair coments are used as address ie, HL = C200 H, The contents of register C are transferred (0 memory location C200, so memory location C200 contents will change from 10 H o 2011 f ples of instructions are ; MOV MB .;MOVM,C; = MOV M,D ,MOVM,E; MOV M,H = ;MOVM,L; = MOV MA 6.5.3 MVI R, Data : Description + Move immediate data to specified register. ‘The 8 bit data is specified with the instruction, This instruction moves the immediate 8 bit data to register, It is two byte instruction, so first byte of instruction will be OPCODE and second byte will be 8 bit data The examples of R are all general purpose registers such as A, B, C, D, E, H and L. Operation + Data > R Encoding feos oeedeeerdeerieeero [data Gy) |] For MVI C, 05 H => ddd | hOe e0) Oke Oe ele On|) ObH Final OPCODES are => OE H, 05 H No. of bytes 2 bytes Addressing mode : Immediate addressing. Flags + No flags are modified. Example : MVIC, 05 H. The data 05 will be loaded in register C. Contents before execution of instruction Contents after execution of instruction8085 Instruction ae 68 Microprocessor Techniques vic, XH; MVID,XH; MVIE,xXy MVLA.X Hj MVIB,XH; MVC MVLH,.XH | MVIL, XH; 8.5.4 MVIM, Data : moves it jate data to memory. Description 2 This instruction oe memory pointer, The — a HL ae the immediate : transferred to that memory location. Operation + Data > M or Data > (HL) (data) Encoding > Lo or to 11 0 [ay Gata) No. of bytes: 2 bytes Addressing mode : Immediate indirect addressing, =~ + No flags are modified. Example 1 MV H, 0H 20 data is transferred to H reg, “MVE Loon, 00 data is transferred to L reg. MVI M, 10H, + 10 data is transferred to memory. When MVI M instruction is executed, the data 10 H will be stored in memory location addressed by HL pair ie 2000 Contents before execution of instruction Contents after execution of ison Register Memory Register femory SZ ACP cy SZ ACP CY A F Address} Data A F Address} Data e ctr B lc tre F| e E 2000] D E2000] YW 200 H 200 65.5 LXxI Ry Data 16 Bit : Description + Load register pair with 16 bit data. ‘This instruction loads 16 bit data. specified with instruction o the Rp ‘eister pair. In instruction only high order register is specified for register Pair ic. if HL pair is 1o be loaded only H register il be specified in the instruction The examples of R, are BC pair, DE pair, HL pair and Stack pointer SP, Operation +16 bit data > R, Encoding :[o 0 0 0 © 1 JorcopE , DB DD, DD = ' D, Ds Ds D, D; D, Dy Dy Immediate data Dy~D, ee es OE Pis Dig Diy Diy Dy, Pio Dy Dy Immediate data Dy - D R, ~ Register pair, OPCODES of LXI R, instruction,Microprocessor Techniques 69 8085 Instruction Set BD H sp ba Co [arf ar [ar No. of bytes 3 bytes Addressing mode : Immediate addressing Flags + No flags are modified Example + @ LXIH, 2000 H : Load HL Pair with data 2000 H. 20 will be loaded in H reg and 00 H in L reg, Contents before execution of instruction Contents atter execution of instruction SZ ac Pp cy SZ AC PCY A F A [BAG 8 8 c o D E H HY yo. i) LXI SP, C600 : Load stack pointer with data C600 H. Contents before execution of instruction Contents after execution of instruction CP oy ene A F A BG \r 1 is a 3 byte instruction, So it is stored in memory in following fommat first byte OPCODE of instruction, second byte low order 8 bits of data and third byte high order 8 bits of data This instruction can be used instead of 2 move instructions, fo register pair. For example, MVI B, 8 bit data; MVI C, § bit data, 2 to load register pair instead you can use LXI B, 16 bit data, Examples of instruction are : LXI B, 16 bit data, LXI-D, 16 bit data; LXIH,16 bit data; LXI SP, 16 bit data 6.5.6 LDA Address : loading 2 registers of a Move instructions are used Description + Load accumulator direct from memory. This instruction copies the contents of the memory location to the accumulator. The address of memory location is specified along with the instruction. It is a 3 byte instruction. So it is stored in memory similar to LXI R,, data instruction, ie. OPCODE as first byte, lower order address as second byte and higher order address as third byte. Operation : (Address) > A Encoding : [0 0 3A OPCODE Ay Ag As Ag As Ax Ar Ap | Direct address Ay— Ayg085 Instruction Set 4 Microprocessor Techniques Direct address Ag ~ No. of bytes 1 3 bytes Addressing mode : Direct addressing. Flags : Ne flags are modified. e Example : LDA C100 HL : Load accumulator with the contents of memory location C100. 1 . Cs Contents atter execution of instruction Contents beara ot ee Register Memory SZ ACP CY SZ ACP CY | F Address Data A iE F Address} Data A Z 2 lc COFF 8 lc COFF| 2 S D = cr09) D le cro H L C101) H i ory 6.5.7 STA Address : zy Description 2 Store accumutator direct to memory. This instruction copies the contents of the accumulator to the memory location. The address of the memory location is specified along with the instruction. It is a 3 byte instruction. So it’s storing format is OPCODE as first byte, lower order address as second byte and high order address as third byte. Cperation 2 A ~> (Address) Encoding : [00110010 |32: OPCODE Direct address A - Ay Direct address Ag ~ Ays of bytes: 3 bytes Addressing mode : Direct addressing Flags : No flags are modified Example : STA C200 H : Store accumulator contents at memory location C200 H. Contents before execution of instruction Contents after execution of instruction Register Memory Register Memory SZ ACP oY SZ ACP CY ZG |r Aecrss| oat re F Address} Data lc corF| 8 az cori E c2oofn ton D Cae iL C201] H IL C201] 6.5.8 LHLD Address : Description : Load HL pair direct from memory.Microprocessor Techniques 6-11 8085 Instruction Set This instruction copies the content of the memory locations to H and L registers. The address of memory location is specified along with the instruction. The contents of memory location whose address is specified with the instruction are transferred to L register and (address + 1) contents to H register, This instruction is used to load H and L registers from memory. It is a 3 byte instruction, So its storing format is OPCODE as a first byte, Lower order address as second byte and high order address as third byte, Operation (Address) > L reg, (Address + 1) > H reg, Encoding 0 o 1 0 1 0 1 0 | 24 OPCODE —————P | 0 1 0} 24 Ar Ac As Ag Ay Ay Ay Ap | Dinect address Ay Ay Ais Ais Ars Az Air Ato Ay Ag | Direct address Ag— Ajs iI ie i a | No. of bytes a byes ‘Addressing mode : Direct addressing. Flags : No flags are modified. Example LHLD C200 : Load HL pair from memory locations C200 and C201. Suppose H = 05 H, L = 04 H, at memory locations C200 and C201 the data 20, 30 is stored respectively and instruction LHLD C200 is executed. Contents before execution of peruete ‘Contents after execution of instruction Register fernor Sz ACP CY i weescecy i F Address} Data A F Address) Data 8 lc COFF al JC corr D E C200} 207 Do Ee C206 Hf 05: = fos C20" H tT C201] 6.5.9 SHLD Address : Description Operation Encoding Store HL pair direct in memory. This instruction copies the contents of registers H and L to the memory locations. The address of memory location is specified along with the instruction. The contents of L register are stored at the memory location whose address is specified and the contents of register H to the (address + 1) location. This instruction is used to store Hand L registers direct to memory. The storing format is OPCODE as a first byte, lower order address as second byte and high order address as third byte. L reg — (Address) H reg + (Address + 1) o 0 a. 4 22 OPCODE Ay As As Ag Ay Ay Ar Ap | Direct address Ay Ay8085 _Instruction gq »_Instuction Seq 12 - rocessor Techniques _ 6 ~~ Ay | Ditwot auldress Ay ~ Ay, A Aw As ¥ bytes Dirvet anldressinys No Mays are modified SHLD C300; Store UL pe No, af bytes Adil Flags . ssing mode emory locations C300 and C301 air (9 MEN ry locations C300 and C301 the Example By Suppose H = 05 41, Lm 4 1 at me i ai 20 ‘and Ni ig stored respectively and instruction SHLD C300 ig executed. 7 struction Contents botore execution of instruction Contents onus geailen otinatucton Register Memory o7 ACP CY $Z ACP CY Address} Data A A f Addross| Data A F A : -—] Ic 8 ic GOFF 8 ee 20 D ° ae 620 all 6.5.10 LDAX R, = Deseription + Load accumulator indirect by using a memory pointer. ry location to the niction copies the contents of the memo ' location is given by the R, register The examples of R, are B This it accumulator. The address of memory pair specified along with the instruction (ie, BC pair) and D (ic. DE pair) only. Operation : (Ry Joa Encoding : LDAXB 10 |2A oPcopE LDAX D 0 |1A_ OPCODE No. of bytes) 1 byte Addressing mode : Register indirect addressing. Flags : No flags are modified Example + LDAX B : Load accumulator with the contents of memory location whose address is given by BC register pair. Suppose A = 00, B = 20, C = 02, at memory location 2002 : 50 is stored and instruction LDAX B is executed Contents before execution of instruction Contents after execution of instruction Register Memory Register Memory SZ ACP CY SZ ACP CY A F Address| Data A a B 2004 Bl D 2002] D H H L 2003}yr Mictot 8085 Instruction Set processor Techniques 613 Examples of instruction are LDAX B ; LDAX D. 65.11 STAX R, Description Operation Encoding No. of bytes Addressing mode Flags : Example Store accumulator indirect by using a memory pointer. ' to memory location. This instruction copies the contents of accumulator to memory The address of memory location is given by the R,, register pair specified along with the instruction. The examples of R, are B (ie. BC pair) and D (ie. DE pair) only. A>(R,) STAX B 0.0 0 0 0 0 1 0402 OPCODE STAX D 0.0 0 1 0 0 1 0 | 12 0PCODE 1 byte Register indirect addressing) No flags are modified STAX D : Store accumulator to the memory location, whose address is given by DE register pair. Suppose A = 20, D = 25, E = 05, at memory location 2505 : 10 is stored and instruction STAX D is executed. Contents after execution of instruction 2505| Contents before execution of instruction Register Memory Register Memory SZ ACP CY SZ ACP CY 7 Zr Adsress| Data A f Address| Data lc 2504] B ie 2504) of. E2508) H L Zoe> 2506} 2506 6.5.12 XCHG : Description Operation Encoding No. of bytes Addressing mode : Flags Example Examples of instruction are STAX B; STAX D. Exchange the contents of HL with DE pair ‘This instruction exchanges contents of H reg. with D reg, and L reg. with E reg. HeD, Lok [71 0 1 011 Jes opcone 1 byte Register addressing. No flags are modified. XCHG Suppose H = 20 H, L = 30 H, D = 40 H, E = 50 Hi and instruction XCHG is executed.9085 instruction Set ea “Gonton iter execution of instruction ononts ator exOESTT qlee Contents betore execution af instruction Rogister Microprocessor_Techni Poy rom» Note : IN and OUT instructions, We you to understand, Group 6.6 Program Examples for Data transfer ruftor;and, cata 20, Hints B reg a 05 H into accu! Ex. 1: Wete 2 program to load dat Soln, > . ee eee refer Fig. 6.2) TORraM The above problem wat to initilise the Description > yisters A and B ‘with data, The data is Coan) ddiweelly available, SO jnstruction which can be SP (ued is MVE R, data Toaddatain accumulator] Program Instruction Operation MVI A, 05 H 05 > A Toad data in rea Ct 8 ee Cénd ) HLT Stop Fig. 6.2 in a program memory, then the same is Suppose you want 10 see how it looks like ry location for example, depicted as follows. Assume 0000 Hi as starting memo 0000 H|_3E al a ae MVE A, 05 H_ (2 bytes instruction) 2H 5H MVIB, 06 H_ (2 bytes instruction) 4H ] ~ HLT (1 byte instruction) Note : HLT means HALT. It is again instruction of 8085. Refer sec. 6.10.6, for more detail Ex. 2: Wiite a program, to store the data type AB H into memory location, D0000 H. Soln. : Program - I © Tnstruetion Comment it ‘MVI A, ABH | Reg A= ABH aMicroprocessor Techniques 6-15 8085 Instruction Get STA DOO H + Store ACC contents at address DOW EL HLT 3 Stop 000 i y MV A, AB H (2 bytes instruction) ftoadimmediate data] «= 1 HL AB in eccumulator 2H{ 32 | OPCODE of STA t hear STA D000 H Transler accumulator] 3 H |, 00 _| > Lower address byte @ bytes instruction) data to memory 4H] Do | _, Upper address byte location 5 H/ 76 |] HLT (1 byte instruction) Flowchart 1 Note :Observe 3 bytes of STA D000 H instruction. Lower address byte is stored first and then upper address byte. This is INTEL STANDARD OF DATA STORAGE. OR Program - II \ Instruction Comment \ LX H, D000 HHL pointing to D000 H location (HL used as pointer) MVI M, ABH ; Store data, at memory location pointed by pointer HL HLT ; Stop 0000 H [21 |-> OPCODE of LXI H LXI H, D000 H 1H [00 | Lower order data ee a 2H | DO} > Upper order data nitiaise pointer — —_ 3H | 36 | OPCODE for MVI M, ] MVIM, ABH a ae ae data | @ bytes instruction) (Pointer) «Immediate >; J data SoH | 76/5. HET, > (1 byte instruction) Flowchart 2 Program - 1 Instruction Comment Initialise pointer] LXI —_B, D000 H ; Read BC as a pointer r MVI A, ABH ; Read data in ACC. [Load immediate| STAX B 5 Store accumulator eae ; data to memory ¥ 5 location pointed (Pointer) D000 H and D001 H, Ex 3: Wie a program to exchang Soln. : Comment Load data from one memory location Store it in B reg. Load data from second memory location Store data of second 2 Inemory location to first 2 memory location. * Recall data of first location oad data of first memory location “Store tin temporary register store [Load data of second memory location) ‘Siore it in first memory location mov Ay * Store it in second Recall data trom temporary register sta 2001 H * Socata memory t ‘Store iin second memory location HLT, i= Gen) Flowchart 4 Program - I Instruction Comment LHLD D000 H + Load HL with data at D000 H and DOO] H MOV A,H ! second byte in ACC MOV =H, L * first byte in H MOV L,A ‘second byte in L SHLD D000 H ; Store HL HLT 5 Stop ee 11 | Exchange contents Hk | use accumulator as mediator Store L and H D000 H/ D001 H respectively Flowchart 5HONG Inatiiesion Gat Mictoprocessor Techniques om Program <1 Jnstrvetion Comment UXt 1, boon SUL potting to Boow LXT oD, Door IT (DIE pointing to DOO A MOV 0M VD > UNL) (titer byte) LDAX D Late second byte In ACC XCHG 1 Exchange DIC aid HL, pale content MOV MB | Stowe fist byte in second location s D 1 Store eccond byte tn fitst lucition ML | Stop Using three examples and total 7 progims, we tue used approximately sll the instruction in data transfer group. 6.7 _ Arithmetic Opor: ‘The arithmetic group of instructions include following, insttuctons : 1, ADDR 2, ADD M 3. ADC 4, ADEM 5, ADI data 6. ACI data 7. DAD Ky, 4 SUB 9. SUB M 10, SBB RR i, SBE M 12, SUL data 13, SBI data M4. DAA 15. INR R 16, INK IM 17, DCRR 18. DCR M 19, INX R, 2, DCK Ky 6.7.1 ADD R: Description + Add register K contents to accumulator, ‘This instruction adds the contents of register Rand accumulstor and Stores the result in accumulator, ‘The examples of Rare all general Purpose registers such as A, B, C, D, E, Ht and L, In addition to the result in accumulator all the flags are modified to reflect the result of operation, Operation t AtR>A Encoding : Llovoosss] OPCODES of ADD R instructions BC p fit A App [80 | 81 | 82 | 83 | #4 [5 [ 97 No. of bytes 1 byte Addressing mode : Register addressing, Flags : All flags are modified to reflect the result of addition, Example : ADDB: A+B>A, Suppose A = 47 H, B = 51 H and instruction ADD B is executed, A 0100 O111 = 47 +B 0101 oo0o1 51 A 1001 moc =cS 8085 instru Microprocessor Techniques 6.18 ton i er system an ‘The addition is performed in hexadecimal number sy the fps status will be as follows I t0 zero, Zero flag is reset as result is not equal in an Party flag is reset as result contains odd numbers op (iii) Sign Sign flag is set as D, bit of result is 1 iy om 2 Camy flag is reset as there is no carry from D, bit of result to next stage ie. result is 8 bits only. () Ausiliny cany : The AC flag is reset as there is no carry from D, bit to Dy Vit of result Contents betore execution of instruction Contents after execution of instruction SZ AC PCY a eg a al T Z 7 A 1 of oYo ole 6 51 c Bee c D E D E H L H L Examples of instruction are ADD B, ADD C, ADD D, ADD E, ADD H, ADD L, ADD A. 67.2 ADD M: Description Add memory location contents to accumulator. ‘This instruction uses HL pair as memory pointer. The contents of memory location addressed by HL pair are added with accumulator and the result 's stowed in accumulator. All the fags are also modified to reflect the result of operation. Operation t A+M >A or A+(HL) 3A Encoding 2 [ooo 0110 | 8 OPCODE No. of bytes Addressing mode Flags Example Contents before execution of instruction 1 byte Register indirect addressing, All flags are modified to reflect the result of addition, ADD M: A+(HL)->A Contents after execution of instruction Reiser i Memory Register Memory a{Zane F Address} Data A F Address] Data B ic Coo9} B D E C004) BD WEA) § colaZ] 4 Suppose A = 10, H = C0, L = 02, at memory locati is stored and ADD M instruction ee is executed, A+(HL)>A : 104+20-530Microptocessor_ Techniques 8085 Instn 67.3 ADC R: Description 3 Addl register Rand curry flag contents to accumulator. ‘This instruction adds the contents of Reyister R, Cany flag CY and nulator and stores the result in accumulator, The examples of Rare I purpose registers such as A, B,C, D, E, Hand L. In addition (in accumulator all the fags are also modified to reflect the Fesull of operation, Operation b AFRECYSA. Encoding, : [roooisss | OPCODES of ADD R instructions No. of bytes Addressing mode : Flags Ep igs are modified to reflect the result of addition. Example + ADC B: A+B+CY3A Suppose B = 20, A = 3F, CY = Set and ADC B instruction is executed A =.0011 1111 B = 0010 0000 cy 1 A 0110 0000 So CY = Reset, Z = Reset, P = Set, AC = Set, S = Reset The previous carry flag will be reset because addition has not given a camry. Contents before execution of instruction Contents after execution of instruction SZ AC P cy SZ ACP cy a xx Axx |e A oA AsYole By je BE c D E D E H L H TL L Examples of instruction are : ADC B, ADC C, ADC D, ADC E, ADC H, ADC L, ADC A. 67.4 ADC M: Description + Add memory location and carry flag contents to accumulator, ‘This instruction uses HL pair as memory Pointer. The contents of memory location addressed by HL pair and cary flag are added with accumulator and the result is stored in accumulator. All flags are also modified to Teflect the result of operation,8085 Inst 6-20 Teton, ahenpacne Tete —— wecvtae : ge o7co0e | Operation Encoding No. of bytes : L byte 1 re MUSE oat te Addressing mode +! e AMD flags are y yA 4(HL)FEY 7" oy cy = Set, at memory location sult of addition. Flags Example ADC M: A a ; ; so Ae 10H CM instruction 1s executed, oot: 0 data is stored anid ae ef oo! 4 910 000° Y aT a al folk us will be as follows CY = R Result in A= 31 and flag stat = Reset cay generated, AC = Reset a8 110 calty from D, to D, bit, 7~S™ as result ig not 2270, P= Reset as in result odd number of pt present, § = Reset as Dy BHC 0. a Contents before execution of instruction Contents after execution of instruction Register Memory Register ths sz Ac PCY ry a fp Address| Data 7 ic C000) ° iE C001 H 6.7.5 ADI Data : Descripti : as eription. aad immediate data to accumulator. is instmction ad ‘ , SI ae eT eee ame also modified to aa ea rae is stored in accumulator. All the this. instruction will result of operation, The storing fom’ (Gata ‘wil be fist byte OPCODE and second bee, Operation + Abdeo>A byte ope Encoding —_ a im Se ya) Nath brig) 19 * Ds D, dD, Dz : ' 2 bytes | Immediate data Dy-D, Addressing mode : Immediate Flags Exam, + All flags are modi ple : ADI B7 aa to reflect the result of additi accumulator, id B7 Ho data to a em rand store result in Suppose A = = 59 H and i instruction ADI B7 is execu ted, meMicroprocessor Techniques 621 8085 Instruction Set A = 0161 1001 Data Oi 1p i 1 0001 0000 The result in A = 10 and flag status will be as follows : CY = Set as cany is generated from D, bit to next stage, Z = Reset as result is not ver, AC = Set as cany is generated from D, bit to Dy bit, P = Reset as in result odd number of I's are present, $ = Reset as D, bit = 0. Contents before execution of instruction Contents alter execution of instruction “SZ AGP cy SZ AG _P oy 1x} KZ) x| F | F A AX A 66702070 8 c 8 e D E ° E H L H L 6.7.6 ACI Data : Description Operation Encoding No. of bytes 1% mode Add immediate data and carry flag to accumulator. ‘This instruction adds the immediate data, cany flag and accumulator and stores the result in accumulator Al flags are also modified to reflect the result of operation. The storing format is first byte OPCODE and second byte operand (data). A+data+CY >A [1100 1110] CE OPcopE Dy De Ds Dy Dy Dz Dy Dy | Immediate data Dy-D, 2 bytes Immediate addressing, All flags are modified to reflect the result of addition. ACI 20 H : Add 20 H data and carry flag to accumulator and result is placed in accumulator. Suppose A = C0, CY = Reset and instruction ACI 20 is executed Contents before execution of instruction Contents after execution of instruction SZ ACP cy Zac Pp = xk AxAxGo]e Tuva Zoo > - mo = om Oo 67.7 DAD Rb : Description Add the specified register pair to HL pair. This instruction adds the contents of specified register pair to HL pair and stores the resull in HL pair. The examples of R, are SP, BC, DE and HL. Only cary flag is modified to reflect the result of operation.{ 6-22 8085 Instruction Set Microprocessor Techniques | Operation :R,+HL HL Encoding : fooR R100 OPCODES of DAD R, instructions, i B_D_H_ SP pap [09 [19 | 29] 39] No. of bytes: 1 byte result of operation. Examples : () DADB: BC + HL > HL. (ii) DAD SP: SP + HL > HL DAD B = 0, L = 45, flag register = 10x 10x) Suppose B = 20, C = 35, H Sore on DAD B is executed. The result of instruction will be, 2035 BC 04 5ees AOTA HL reset and HL will contain AO7A H as a result Cary flag will be Contents before execution of instruction Contents after execution of instruction SZ ACP Ss A of 1 Bo¥ tr - om oO 10 0! > Examples of instruction are : DAD B, DAD D, DAD H, DAD sp. Ex. 4: White program to load Data 05 H into accumulator and then transfer the same dat to B reg and H reg. Soln. : Program : (For flowchart refer Fig. 6.3) Load data in accumulator Lhe Comments MM. A,05H — ; Initialise A reg = 05 H MOV HLA | Trnsferconens of & We Hee HLT ; Stop the execution. "4 Transfer data from accumulator to H reg.Microprocessor Techniques 8085 Instruction Set Ex, 5: White a program to toad register B with 50 H and register L with 20 H and add the two Place the final result in D reg soln. Description: Fo Toad data in two registers the instructions used will be MVIR, da For nest step to add 2 data byles, we have to take one dala. in accumulator, because add instuction adds (A+R) and stores result in A feb. To store the result in D reg. we can use MOV instruction to transfer Tesull of addition from A reg. 10 D reg, Program : (For flowclunt refer Fig. 6.4) Instruction Operation MVI. B, 50 HI Load data 50 in B reg. Load data in B reg) MVI L, 20H: Load data 20 in L reg. ¥ MOV A, L : Take data from L reg to A. Load data, in L reg. ADD B Add A+B, result in A ¥ MOV D, A : Transfer result from A to D reg. ‘had he 2 data byte HLT + Stop ¥ Transler the reaull to D veg F Ex, 6: Write @ program to perform 16 bit addition on following data 1234 H and 4321 H Store the answer in H and L regs. Soln. : Program : (For flowchart refer Fig. 6.5) Instruction Operation MVI B, 12H : 12> Breg. Load 16 bit data, in BC and MVI C,34H 134 Creg. a . data, in DE register pair MVD, 43H ©4135 ree, ‘Add the LSB data using lower MVI E2H + 21> EB reg. tegisters C and E, A€-C+E MOV AE : EA rg. x ADD C PAHCA : 8. Store th 1B lore the LSB result MOV LA es ‘Add the MSB data using higher MOV A,D :D->A reg, fegisters B and D, A€B +D ADC B :CY+A4+B> A mg Store the MSB result Mov HA pn ott we: HLT Fig 65 Description + To add 2 data bytes 1234 and 4321, first load those data bytes in general Purpose registers. Then take 1 LSB data in accumulator and add the 2 LSB data bytes. Store the result of addition. Take next data byte, add the8085 | Microprocessor Techniques 624 nstucton 4 2 MSB data bytes and cany if generated from LSB addition. si, result of addition ' 1. The parallel program can be prepared by using LX1 B, 1254 insead of MNT B. 12 MVI_C, 34 and LX1 D, 4321 instead of MVI D, 43, MVI E, 21. Use of LT in reduces the size of the program so whenever a reg. pair is to be loaded it is used The same 16 bit addition can be performed directly by using DAD R, instruction by, requires 1 data in HL pair. LXIH, 1234 H 1234 > HL reg. pair LX] B, 4321 H : 4321 > BC reg. pair DAD B : HL+BC—HL reg. pair HLT : Stop 6.7.8 SUBR: Description + Subtract register from accumulator. This instruction subtracts the contents of the register from the contents the accumulator and the result is placed in accumulator. The contents R register are not altered. All flags are modified to reflect the rest Examples of R are A, B, C, D, E, H and L. The subtraction is performed by using 2's complement method 2 complement is done by microprocessor ‘itself programmer only specifi ‘two data bytes. Operation = A-ROA Encoding : L1oo10sss OPCODES of SUB R instructions, BoC DEHUL A sus [ 90 | 91 | 92 | 93 [94 [95 [97] No. of bytes: ‘1 byte Addressing mode : Register addressing, “ Flags + All flags are modified to reflect the result of subtraction, If CY = g result is negative and is in 2's complement form. If CY = Reset, result positive and is in-normal form. Example ' SUBB:A-B>A 1. Suppose the contents of A SUB B is executed. 4" 37 H and B = 40 H and instruct B= 0100 0000 2’s complement of reg. B 1100 0000 0 A= OfOT1 10" ty 2’s complement of reg. B 1100 0000Microprocessor Techniques 6-25 8085 Instruction Set ‘The flags status will be as follows : 2 = Reset; P = Reset; AC = Reset; $ = Set and CY = Sct. Contents before execution of instruction Contents after execution of instruction Bat AE Pp cy 82 AG picy A 7k xBxBAxBx]r A FF | ooo 1]F Bis 0 © Bie oe c o E D E H L H L 2. Suppose the contents of A = 40 H and B = 37 H and instruction SUB B is executed. B+ 0011 oii 2’s complement of reg. = B= 1100 1001 A = 0100 0000 2’s complement of reg. _B 1100 1001 1 + 0000 1001 Carry is generated, the microprocessor complements the carry so CY = Reset and CY reset represents that the result is positive and is in normal form, The status of flags will be as follows : Z = Reset; P = Set, AC = Reset, S = Reset and CY = Reset. Contents before execution of instruction Contents after execution of instruction 22 oe oe sZ ac _picy ale x Ax Gx|r ooo Yolr al c s D E E H . L L Examples of instruction are : SUB-B, SUB C, SUB D, SUB E, SUB H, SUB L, SUB A. 6.7.9 SUB M: Description : Subtract memory location contents from accumulator. This instruction subtracts memory location contents (whose address is given by HL) from accumulator and result is placed in accumulator. The subtraction is performed in the same way as SUB R instruction. All flags are modified to reflect the result of operation. Operation + A-(HL)>A Encoding : [1001 0110) 96 OPCODE No. of bytes : 1 byteques = soerocessr Addrewing mode : Indirect addressing - subtraction (same ay 1 All flags are modified to reflect the result of Su Pus : instrcton } I : SUBM A-(HL)>A oh Suppo 50H, H = C2, L = 00, at memory location C200. 9, Suppose A= 5 i is stored and instruction SUB M is execute Data oo10 0000 2's complement = Lio 01000 aan 0101 0000 2's complement © 1110; 0000 0000 1 oo1l Cary 1s generated, the microprocessor complements the camry y CY = Reset. CY reset represents that the result is positive and is iy normal form, The status of flags will be as follows : Z = Reset, P = Set, AC = reset, $ = Reset and CY = Reset Contents betore execution of instruction Contents after execution of instruction Register Memory Register Memory ‘SZ ACP CY deol Address] Data SZ ACP cr 9 AA a ak 5 co crre| 8 lc CHF a E — c200) 207) D E C200 4 Lesce, ce H IL C204 6.7.10 SBBR: + Subtract register and borrow flag from accumulator. This instruction subtracts register and the borrow flag from accumulator and result is placed in accumulator. All flags are modified to reflect the result of the subtraction. In subtraction instructions, carry flag is called 3s a borrow flag. Examples of R are all general purpose registers such as A,B,C, D, E, H and L. Operation + A-R~-Borow flag>a Encoding : Lidolisss OPCODES of SUB R instructions, BoC DEHULA Description SBB No. of bytes 1 byte All flags are modified to reflect the result of subtraction SBB BB: A-~B-CY3A Flags Addressing mode : Register addressing, Example :Microprocessor Techniques 627 8085 Instruction Set The subtraction is performed by using 2's complement method. First the borrow flag is added to register and then this number is subtracted from accumulator. Suppose A = 37 H; B = 3F and Cary ie. Borow flag is set and SBB instruction is executed. B= 0011 1111 Borrow 1 0100 0000 2's complement = 1100 0000 + A 0 Oni 1 0111 A Tait G1 No carry is generated, the microprocessor complements the cary so cary flag = set. Therefore Borrow flag is set, it represents that the result is negative, and the flags status will be as follows Borrow = Set, AC = Reset, Z = Reset, S = Set and P = Reset. Contents before execution of instruction, Contents atter execution of instruction 3:7 ACh Pp icy. SZ ac Pp cy Bx zroo> = om oO F c E L ZOOS Examples of instruction are : SBB B, SBB C, SBB D, SBB E, SBB H, SBB L, SBB A 6.7.11 SBBM: Description + Subtract memory and borrow flag from accumulator, This instruction subtracts memory location and the borrow flag from accumulator and result is placed in accumulator. The address of memory location is given by HL register pair. The operations are same as SBB R instruction. Operation : A-(HL)~Borow—>A or A~M~Borrow—> A. Encoding : [1001 1110] 9 (@PCODE) No. of bytes: 1 byte Addressing mode : Indirect addressing, Flags : All flags are modified to reflect the result of subtraction Example : SBB M : A-(HL)-Borrow >A Suppose A = 20 H, H = C2 H, L = 00 H, CY = Set, at memory location C200 : 4F H is stored and instruction SBB M is executed. Data = 4F +1 = 50628 2288 tassa, —Eeesrer Techniques eo Ooo g Data = 1011 ooog aparmits = 9910 vo, A + oy mt pe Fara T NTE follows > Sree ec Reset, § = Set and CY = sey 2 = Reset. P = Reset, AC Rents SR2r execu Of ncn Contents betore execution of msiructon Regst SZ A ee A 8 I 8 D qT = €200] DB “ESopm eros], o. H 6.7.12 SUI Data : Description 5 Subtract immediate data from ccurutator This instraction subtracts the date specified along : pedenmator and result is placed “im accumulacr he “subtction § Son ed bY using 2's complement. method operation is "same: SUB R instruction Operation Le aa, Encoding ethic. oo Ps Dz Dy Do | immediate data Dy~p, Ae of bytes 52 bytes Addressing mode: immedine addressing. Flags 2 Gul Mags are modified to reflect the Result of subtraction, Example * SUI 50: A~s05 a Suppose A = 29 and instruction SUI 50 is executed. Contents after execution of instruction S2 ACP cy =y; Contents betore execution of instruction SZ ACP cy A AGB |r oF oF ir a [yc ° D E E L Description ? Subtract immediate data and borrow Slag from accumulator. This instruction subtracts the data and borrow flag from accumulator an ion is same as SBB R. Stores result in accumulator. The Operation of instructiMicroprocessor Techniques 629 8085 Instruction Set Operation i ne Encoding ' —— Dg | Immediate data Dy - D, No. of bytes Addressing mode ; Flags Example 2 bytes Immediate addressing All flags are modi SBI 4F : A ified to reflect the result of subtraction oak = CY A, Suppose A = 20, cy = Set and instruction SUI 4F is executed Contents before execution of instruction Contents after execution of instruction SZ ACP cy SZ AC _P cy a x Zax nF |= 62620200 B c eS D E 5 H L i Ex. 7: Perform 16 bit subtraction. Subtrac o bit nu H (LSB / MsB) Flowchart Source program LHLD D000 H 3 Get first 16 bit number Get the lower byte of fist number xetiG > een 16 ee ¥ in DE Get the lower byte of second number LHLD D002 H $ Get second 16 bit number ¥ 3 in HL Subtract lower byte of second MOV AE 3 Get lower byte of the first number from lower byte of 3} Number first number SUB L 5 Subtract lower byte of the —¥ > second number Get the higher byte of first number MOV LA 5 Store the result in L register MOV A,D 3 Get higher byte of the first Get the higher byte of second number 3 number 7 r SBBo OH 3 Subtract higher byte of ae 7 3 second number with borrow Subtract higher byte of secon * . MOV H,A 3 Store result in H register number and borrow from the - Previous subtraction SHLD D004 H : Sion mult at D004 HF HLD ; Stop Store the result Operation : (D000 H) = 19H (D001 H) = 6AH Flowchart 6 (D002 H) = 15HOO 8085 Instruction Sep 620 Microprocessor Techniques 30. (oov = SCH ou Result = GAI9 H+ SCIS HT OO (Door n= OL (Dos Hy) = OF 6.7.14 DAA : : Ai just accumulator. ' om a binary value to jtg Description + Decimal adjust accu ar ae sep number. This is the contents of the accumulator 2 ac a cote only instruction that u of binary to BCD conversion. DAA instruction working The instruction checks the following conditions : ' oa rp 10 the value of the low onder 4 bits Dy~Dy in the a one 4 bits o} AC flag is set, the instruction adds 6 to the low order ie. If the value of the high order 4 bits D;-D, in the accu! nat flag to perform the operation ‘ its of accumulator. CY flag is set, the instruction adds 6 10 the high order 4 bits instruction which Note : The restriction on DAA is condiion of flags. If you ee ameeeico an affects the flags CY and AC and then if you try to ae = Gi eievous the result will be wrong as instruction will use AC and CY flag: ‘ instructions to take decisions, idition So DAA instruction is used with add instructions ADD, ADI to een a oF umber in BCD. The add instriction adds the two BCD numbers in hex DAA instruction converts this hexadecimal result to BCD formal. Operation +A meg. in binary > A reg, in BCD. Encoding : 27 OPCODE No. of bytes: 1 byte (Flags + All flags are modified to reflect the result of additions, Example #1 If you want to add two BCD numbers 12 and 39 and want result in BCD form. The following steps should be implemented : MVI A, 12 ADI 39 DAA Immediate data 39 is added to A (= 12) 9001 0010 2 + 0011 1001 39 ———_——+_1 001 39 O100 1011 4B The answer i 4B inahexadecimal form. Whe DAA instruction is executed it checks :truction Set Mictoptocessor Techniques 631 8085_ Inst . Ie () Is low order 4 bits Dy-D, greater thin 9 or is AC flag is oe any of the above condition is satisfied then 6 is added - Ae aie 4 bits. In this example, B > 9 and AC = Reset so 6 wil to low order 4 bits Is high order 4 bits D,-D, greater than 9 or is CY is set. If any of the above condition is satisfied then 6 is added to high order 4 bits. In this example, none of the condition is satisfied as 4 < 9 and CY = Reset so 6 is not added to high order 4 bits. 0100 10d) x oO110 a 0101 ooo01 Result in accumulator = 51 in BCD form, (b) Contents before execution of instruction DAA, Contents after execution of instruction DAA SZ ACP cy SZ AGP cy 0 oo Bor A ‘a 002020200 c 8 c E D E U H L If you want to add two BCD numbers 9 and 8 want result in BCD form. The following steps should be implemented : MVI A, 09 MVI B, 08 ADD B DAA A = 0000 1001 + B= 0000 1000 0001 0001 ‘The answer 11 is not correct as addition operation has been performed in hexadecimal number system. So we get A = 11 and flag reg. = 00 x1x1x0 Now, the DAA instruction is executed. As AC flag = set, 6 is added to lower order 4 bits. ooo1 oo001 + OT leo oo01 0111 = 17 in BCD form Ex. 8: Write a program to add two 4 digit BCD numbers, Assume data is already existing in BC and DE register pairs.ONE INStHEHION bg Microprocessor Techniques _ su : sen gen (0 Howe tee 60) cto CoA ‘Aad lower waistors Gand Mov A. c CN GD Sea noo Aa She MeL anon Mov La Hey pee eE |] Ane D wit BED. Senna] hoy mA ict ALT . SB BCD byte, C will contain Hi in LSB. CD byte, We stan rsp pil 4 digit BCD is 2 bytes in BCD. So B will contin MSI TSB BCD byte and D will contain MSB BCD byte, E wil using, DAA instouction, “They With addition of LSB bytes and adjust the result 10 ee ee ean to BCD formst ising DAA G MSB bytes with cary from previous stige and adjust the tes : DAA.We store the LSB result in L register and MSB result in H register. 67.15 INR.R: 2 Increr register contents by one. . Increment register contents by ied riser yt are Description : va This instruction increments the contents of the spc ter by 1 a result is stored in the same register. The cxamples of Rare all yeneral Purpose registers such as A, B, C, D, E, H and L, : Only cary flag is not modified, all other flags are modified, Operation : R+IoR Encoding : OODDDI0D OPCODES of INR R instructions, BC DEUHLQA ir [04 Toc] 14 [ic] 24 [2¢ [30 No. of bytes: 1 byte Addressing mode : Register addressing, Flags + Except cary flag, all other the result of operation, Example ? INRB:B+15B Suppose B = 2F, flag reg, = executed. Examples of instruction are ; INR B, INR C, INR D, INR E, INR H, INR L, INR A, ie, S, Z, P, AC flags are modified to reflect Nx0x0x1 and instruction INR B is5 wyuction Bet Microprocessor Tachniques ons #085 Instruction 6 Contents betore execution at instruc A 0 a 0 " 6.7.16 INR M ; Description 4 Increment memury contents by one. ‘This instruction increments the contents ML register pair by 1 and ae Only ci Operation PML 1 CHL) or Mt oom, Encoding + LOOLLOLOd | 44 opcope No. of bytes st byte Addressing mui Register indirect addressing, Except cary fap, all other Says ie, AC, S, Z, P are modified to reflect the resull of operation INR M : (HL) + 1 Hs CHL) Suppose = C2, L = 09, flag reg, = 00217071 at memory location C202 : 04 is stored, and instruction INR.M is executed, Contents betore execution of instruction Contents after execution of instruction Rogistor Mornony Rogistor Memory 92 ACP cy 87 scp cy A Hos Zoe F Addross] Data GOOG esters] Dara B c C204) Ic C205) d £ caval 76a) & cao| soy Hf ce. 02 |t — cz0a) 22. — cen 6.7.17 DCRR: Description 1 Decrement register contents by one. This instuction decrements the register contents by 1 and result is stored in same register. ‘The examples of Rar re all general purpose registers such as A, B,C, D, H, Mand L. Only cary flag is not modified, all other flags are modified. Operation > R-1OR Encoding, 7 101] OPCODES of DCR ft instructions, boepe per [os [op | 1s | ww] 25on _ 8085 Instruction Set Microprocessor Techniques No. of bh: +L byte fied 10 reflect the Ailiressing mode + Register addressing es ae oe uae te Flags + Except camy flag, all ot operation Example 2 DERD:D-t9B 1sox0x! snd insnclon Dex : Suppose B = 2F, flag re a ator execution of instruction nn Contents a Se eLstcton Contents beter executn of stucton ieee, sz A F : A ooo : c 8 = c al. Q g o a 4 i H =00x1xIx1 The result will be B = 2E and flag reg. ae DCR D, DCR E, Dee : Examples of instruction are : DCR B, DCR C, \ DCR L, DCR A. 67.48 DCR Mm: Description 2 Decrement memory location contents by one. This instruction decrements the contents of 0 ae addresseq by i it the same nemo, HI x by 1 and result is stored back a : 1 iscsiee “Only cany’ hag is not modified, all other flags are modified Operation * (HL)-1(HL) or M-1>™M. Encoding = [0011 010135 opcopEe No. of bytes: 1 byte Addressing mode : Indirect addressing, Flags + Except camy flag, all other flags are modified to reflect the Tesult of operation. Example : DOR M : (HL)-15(HL) fee i egies oe - 2F data is stored, flag reg. = 01%0%0.x1 and instruction DCR M is executed. Contents before execution of instruction Contenis after execution of instruction Register Memory Register Memory SZ ac p cy oo AF F Address] Data Sy 9 S zoa>Mictoprocessor Techniques 6.7.19 INX R, : Description Operation Encoding No. of bytes Addressing mode : Flags Example 6:35 8085 Instruction Set Increment register pair by one. This instruction increments the contents of register pair by one and result i S stored in the same register pair Examples of R, are BC, DE, HL and SP. Only higher order register is. 5 No flags are modified, R,+15R, oom goon] OPCODES of INX R, instructions, specified for register pair in instruction. BD H sp inx [03 [13 [23 [33 1 byte Register addressing, No flags are modified INX SP : SP+1— SP INX B -BC+1-BC Suppose B = 02; C = FF, SP = C200, flag reg = O1x1x1x0 and instructions INX B and INX SP are executed BC+1-—>BC; O2FF +1-+ 0300, So, B = 03 H and C = 00 H SP +1 SP ; C200 +1 C201, So SP = C201 Examples of instruction are : INX B, INX D, INX H, INX SP Contents before execution of instruction Contents after execution of instruction SZ ACP cy SZ ACP cy ols Ezl iow > rmo7 7 moO 6.7.20 DCX Rp : Description Operation Encoding Decrement register pair by one. This instruction decrements the contents of register pair by 1 and result is stored in same register pair. Examples of R, are SP, BC, DE and HL. In instruction only high order register is specified. No flags are modified, R,-1>R,. ooR,R10110 8085 Instructio 6-36 — —— foprocessor Techniques OPCODES of DAX Ry, intstnuctions, BD) Wh DCX (op | 15 [28 | 38 ] 1 byte No. of bytes Addressing mode : Register addressing. Flags No flags are modified. Example : DCX D : DE-1-> DE DCX H ; HL-1—- HL ae. | ion Set 7 ¥ = 00, reg. = Olx 1x 1x0 Sree box basi DX Ham eae DE-1-+ DE; 02FF-1—>02FE HL-1—HL; C200-1— CIFF one a. Contents ater execution of instruction 3 TE ABo oe Bieo|r . B c OF > ze ‘ whee : ‘ a sP Examples of instruction are : DCX B, DCX D, DCX H, DCX SP. 6.8 Branch Group : The microprocessor executes machine codes in a sequential manner, It goes on executing from one memory location to the next. Branch group of instructions insietet or tells the imicioprocessor to go to a different memory location, ‘The microprocessor continues executing machine codes from that new location. The address of the new memory location is cither fPecified in the instruction or supplied by the microprocessor or given by extra hardware The branch group instructions are classified in 3 categories (a) Jump instructions : 1. IMP address 2. Conditional jump instructions 3. PCHL (©) Call and return instructions : 1. CALL address 2. Conditional call instructions 3, RET 4. Conditional Ret instructions (© Restart instructions : 1. RST N 6.8.1 JMP Address : Description + Unconditional jump to the address specified along with the inst When this instruction is executed the instruction directs micr fruction, roprocessor about jump and it Provides the address where mucroprocessor has to transfer the control. The storing format is OPCODE, lower ord es” ler addressMicroprocessor Techniques Operation Encoding, Example 6.8.2 Conditional Description : | f | ‘Operation | Encoding tion Set oof 8085 Instruct and higher onde be executed in Address 5 pe " ‘ill address. Now the instructions from address onwards wi sequence, 3 bytes Tumediate addressing, No flags are modified, IMP C200 ¢ “struction is stored at address CO0S as follows COS OPCOD; C006 0 C007 CRusfers control of program ie win jump at rsccuting instructions from C200 onvarde | Jump Instructions The IMP address is an unconditional is checked it will have a jump when instruction is executed Ih Conditional jump instructions when the Condition is true or satisfied ie Si jee ode a the aeetach address. If condition is false or ettisfied it will just check and proceed further to execute the next instruction. after it. ‘d_by microprocessor, it address C200 and stants Jump instruction, in it no condition Different conditional jump's available are 1 JC Sump, if cany flag is set, 2. INC - Jump, if camy flag is reset 3. JZ ~ Jump, if 2er0 flag is set 4. INZ - Jump, if zero Slag is reset 3 IP ~ Sump, if positive ic, sign flag is reset § IM Jump, if minis or negative ie. sign flag is 4 g RE - Jump, if parity even ic. patty flag is oot 8. 3PO - Jump, if parity odd ic. parity flap is rose: Remember there is no jump on auxiliary cany flag If condition is tme, address > PC If false PC = PC +3 OPCODES: ‘ \ JC [110 110 10] pa mnc [110 100 10] v2 JZ [1100 1010] ¢Mictoprocessor_ Techniques No. of bytes Addressing mode : Flags Example 6.8.3 PCHL : Description Operation Encoding No. of bytes: Addressing mode : Flags : Example 6-38 8085 instruct n INZ [1100 0010] wy [itit ooto] Pm rs IM [L111 1010] FA we [1110 toto] EA O|1110 oo10] mB Ay Ag As Ay Ax Ap Ay Ag | Immediate address Ag- Ais Aig Ais Ai An Aro Ag 5 | Ammediate address Ag - 3 bytes Immediate addressing. No flags are modified, only flags are checked, 1. JZ C200 ; This instruction checks zero flag. If zero flag is set, condito true, So program control is transferred to address C200. If zer reset, condition is false. So program control is not transfered jpg it will execute the next instruction after JZ C200. 2. JNZ C200 This instruction checks zero flag. If zero flag is reset, condit true. So program control is transferred to address C200. If 20 is set, condition is false. So program control is not transy instead it will execute the next instruction after INZ C200, Load program counter with HL contents, The contents of H and L registers are traisferred to program ‘Counter, 1 H contents to high order 8 bits and L contents to low order 8 bie Program counter. This instruction is equivalent to a 1 byte unconditional jump insu A program sequence can be changed 10 any location by simply lak the H and L registers with address and by using this instruction PCHL, HL PC As PC is loaded with new value the next instruction executed vill from the new address. 11101001 |E9 OPCODE 1 byte Register addressing. No flags are modified. LXI H, C200 H PCHL The LXI H instruction initializes HL pair with C200 contents H =! and L = 00. When PCHL is executed HL contents are transfered to!eee Mictoptocesscr Tachnayung on £025 2f0 = and HC address 6.8.4 CALL Address: Description * CUB, 90 the next inetnetion will be exearted is from C20 + Unconditioned call subroutine, mari this Ineinetion is executed the program sequence is tansfered to Whe addtess specified in the instruction. Before transferring the sequence the program Couster conteras ate stored on 10 stack 1¢. Higher order bits and then Newer onder % bits. The call instruction is used 10 call a subrontine, “To tetumn track fom subsontine the Program counter contents ate tated an ig ack, Py (SP 1), 9 Address > PC, Operation 1,9 (SP=2) SP~2-5 sp Encading :ltoo 44 91! @ oPcopE Aq ha he he hy Ag Ay Ay | Subroutine Starting address Ay~ A, Ass Ata Ara Aya Ayy Agy Aa, Subroutine starting address Ag Ags No. of bytes Addressing mode Flags 3 bytes ininediste register indirect addressing No flags are modified, Example ALL C200 Suppose this instruction is stored at location. C006 OPCODE C007 06 C008 C2 C009 next instruction When this instruction is executed, program cotmter contests CD09 will be flored on to stack and the microprocessor starts executing instractions from C200 onwards, Note : More details on CALL, RET and Subroutine is covered in chapter 6. ] Contents before execution of instruction Contents after execution of instruction Registers Registers SZ AC P cy Memory SZ Ac P cr Memory: A F Adress] Data A e © coolgeoz] 8 o E coo7] a H| | L Co08) cops] sP Z : : Pc c7#o| - Ze) CHFEVXF) [SP cr 3XMicroprocessor Techniques 6-40 6.8.5 Conditional CALL Instructions : In conditional CALL instruction address is made, if condition is proceed for next instruction after it. Description Different conditional CALL instructions CC. Call, if camry flag is set CNC- Call, if cary flag is reset. . sign flag is reset. CM - Call, if minus ic. sign flag is set. CPE - Call, if parity even i. parity flag is set CP - Call, if positiv EPO - Call, if parity odd i. SIAM BENE NZ - Call, if 221 Remember there is no cal Operation If condition is true : PCy > (SP-1), PC, > (SP-2) sP-2 SP, Address -> PC If condition is false : PC-+3-> PC Encoding OPCODES : co [Wot 211010 cnc[1101 0100 cz [1100 1100 1100 0100 1111 0100 cm [1111 1100 cPpeE{1110 1100 cpojii10 0100 Bride hale Sale ation NZ cP No. of bytes 3 bytes when the col false then it will not D4 cH Fa 2085 Instruction Hen Sue ndition is true then a call a have a call and wi available are parity flag is reset. CZ ~ Call, if zero flag is set. ro flag is reset. II on auxiliary carry flag. DC cc FC EC 4 Subroutine starting address Ay Ay Ais Aig Ais Ala Aur Ato Ag Ag Subroutine starting address Ay-AyMicroprocessor Techniques Oat Sone _(nstueton Se Addressing mnie Magy Rvampte g 68.6 RET: Description : Operation : Encoding No. of bytes Addressing mode Flags Example Umediote repister tntinvet aldteesiyt No flags ave anoatitied ays aus onty checked ee C200 cat {1 cat’ Ha As set, the program vit flow advons C200 anv Mate CNM TE cacy ay Is rexel tnlehopracen will excite neXt instinetion attr CC C200, Retuen from subroutine, When this instine Whe this imietion is executed program sequence ix ttunsfotted from the Cvhere the ct calls program "he rctuan auddieas ie taken thon ack is nddregy eto as stored ts PC convents Lo. relanninlions) ne a twee in PC anal the program excention bel nt akiesy ‘The call return structure is as shown inf Main program UXI SP FFFF 67, Subroutine CALL subroutine Next instruction HUT Fig. 6.7 (SP+1) PCy ; (SP) PC, SP+2— sp 1100 1001)]c9 opcopE 1 byte Register indirect addressing No flags are modified, RET Suppose the CALL C200 instruction is written at C006 and is executed by microprocessor. The microprocessor will call the subroutine (see CALL instruction example). It will store the retum address at C7FE and C7FD, start executing instructions from C200 onwards. At C209 RET instruction is present. When RET instruction is executed by microprocessor, it will take return address from stack (C7FD and C7FE) and load in ‘program counter. So the next instruction executed will be from C009, |ia 808s struct, “on Microprocessor Techniques Contents ater execution of instruction Se Rogistors instruction Cxmtents Beene eneoutoyy of in SE AP CY Memory Memory pf Adsess) Data ‘Subroutine Eh e200 REY BP crt Soy) C7FE Sco C7FEFX 6.8.7 Conditional RET Instructions : Description + In conditional retum instructions when the condition is tue then only he RET is made at the address given by stack. If condition is false it wi Proceed further to execute the next instruction after it, Different conditional RET’s available are : 1, RC = Retum from subroutine, if camy flag is set, 2. RNC- Retum from subroutine, if cany flag is reset, 3. RZ - Retum from subroutine, if zero flag is set. 4 RNZ- Retum from subroutine, if zero flag is reset & RP - Retum trom subroutine, if positive te. if sign flag is reset, $ RM - Return from subroutine. if negative ic. if sign flag is set ¢ RPO- Retum from subroutine, it odd Parity ie. if parity flag is res 8 em RPE Return from subroutine, if even parity j Remember there is no retum on auxiliary cany flag. f parity flag is set Operation f If condition is true F (SP) > PC, (SP+1 ! > PCy, SP.+2- sp If condition is false : Encoding MCRL APC OPCODES 7 1100 1000 cs RNZ[1 100 0000 coictoprocessor Techniques | | a BAN | w Lit ono] "0 | eM [taay hoool 4 | wollte coe o| “0 | Ue | UK fo. of bytes + 1 byte ddressing mode : Register inditect addressing, ono Of the eight met contents of the to the address, Program to transfer fags + No flags are movlived, Migs ane only checked ; 188 RSTN: } lescription 2 Restart instructions, | These instructions sre equivalent to 1 | location ie. to These instructions cin te ct instruction is executed Restart instructions SUI o010 0018 The N ranges from 0 10 7 ane the difference between vecto Sold! 13 2812 ete 10: oh eg oToToToTofoTo[o] 4 KOK Instruction Set bylo CALI, instruction at restart mory locations om pays 0. The program, counter are saved on to lack sd program jumps software Internupte in excculion 10 one of the # locations and its locations are as follows + r locations is 8, 520i 720) Program counter after restart peration + PCy>(SP~1) PC, > ¢SP=2) sP-2-5 sp Restart address -> PC neoding : [LIAAAL 11] AAA=N;N=0-7RST number, OPCODES of RST N instructions, oO 123 4 5 6 7 rst [¢7| ce [7 | or| &7 | EF | F7| rr «of bytes: 1 byte , ldressing mode : Register indirect addressing, [otoTo}. oad 80 Flags LL 0010, the PC Example rent to CA\ ee nen uence is transferred to addres gus . 7 ‘This instruction is equi ate S O10 yy M ‘and program sequence ada my on Oa d very important instructions, that will introducy *. AL this. stage, we ha ln, concept”. .8.9 Concept of Looping : 6 Program “ is the ase, simctue which foes the CPU 10 repeat a = instructions. One can divide ‘LOOP" in fa ning values of ‘counters — ae i 1. Initialisation section: This aie vamistiee: re mm ae data manipulation occurs. This is the section a * the work. : 7 by 3. Loop control section : This updates counters and pointers for the next iteration, 4. Concluding section: Analyzes and stores the result. 2, Processing section Note : (1) Microprocessor executes section (1) and (4) ONCE. (2) Microprocessor executes section (2) and (3) many times. Execution time depends mainly on section (2) and (3). Following flowcharts 7 and 8 depicts two ways of arranging these four sections, [ _ a Talfaizaton Tail zation | section section = Processing Toop control Section section Loop contro} | section No. (5 Processing] | Concluding és section section Concluding section (End) Flowchart 7 (1) Processing section is alway Flowchart 8 s i once. YS executed | (1) Processi Sect at all Setion may not be executed @ More efficient, 2) Less efficientMicroprocessor Techniques 6-45 The loop structure can ‘must incre an address to next clement in the d; the data in the next memory location. Thus of any Iength with same sot of instruct examples. First example 1 will explain you 6.8.10 Examples : Ex.9: Write a program to ad: from C200. The result Soln. : Definition ; Inputs 10 data bytes from C200 to C209 Operation : Add the data bytes Output: Store result at C300 Solution plan : 1, Input stored at memory locations so access all locations using memory pointer. Memory pointer = Address 2. Initialise counter = Number of bytes to be added 3. Clear initial result = 00 4. Add (result and data) and store in result 5. Point to next data using memory pointer 6. Check if all data bytes added If no go to step 4 7. Store result 8085 Instruction Set Process entire blocks of data. To accomplish this, the progam Tegister (pointer), after cach itcration so that address register, poi lata block. The next iteration will then perform the same operations on , microprocessor is capable cnough to handle blocks ions. To understand looping concept let's take few in full detail, 4 ten data bytes. Data is stored in memory locations starting is 6 bits only. Store the result at C300 location, initialise counter and memory pointer] \ Initialise result = 00 \Take data using memory pointer | Resuit = resuit + daia Counter = counter—1 [Memory pointer = memory pointer + 4 is counter = 0 2 Yes 8 Stop. ‘Store result Program —: (For flowchart refer Fig. 6.8) ap : Fig. 6.8 Label Instruction Comments Operation LXI H, C200 H nitialise memory pointer + C200 HL MVI C, OAH 5 Initialise counter :0A>C MVI A, 00H 5 Initialise result register 1009 A LOOP: MOV B, M 3 Take data using memory pointer: (HL) +B ADD B Add old result + data 5 > New result PAtBOA INX H ; Memory pointer ; = Memory pointer + 1 :HL+1 HL DCR C 3 Counter = counter ~ 1 :C-15€ JNZ LOOP Check C = 00, if no go to loop STA C300 H 5 Store result at C300 H :A>(C300) HLT 5 StopMicroprocessor Techni 8085 Instruction Set Brample : : ca 88 Unital condition C300 : 00 201 06 202 : 203 - Sor. OT cos 8 206? 207 ol cos 50 canoe «= 10 Step wise program execution is as follows * TPass: 1, HL = C200 2 C=OA 3. A= 00 4. (HL) >B; 3. AtBOA, 6& HL+1>HL; ‘ 7 0-196 II Pass : (HL) +B; AtBoA; 6 HL+1—>HL; 7. C-13G MI Pass: 4. (HL) 3; 3. A+BSA 6 HL+1HL; 1 C-14G IV Pass ; 4 (HL) 3B; 5. A+BoA; 6 HL+15HL; 7 C-15G B= 05 00 +05 = 05 HL = C201 C= 09; Condition of zero flag not satisfied it will go tg step 4. B= 20 05420 = 25 HL = C202 C= 08; Condition not satisfied, go to step 4. B= 06 A= 06425 = 2B HL = C203 C= 07; Condition not Satisified, go to step 4, B= 21 A= 2B+21 = 4c HL = C204 C= 06; Condition Not satisified, go to step 4, eeMicroprocessor Techniques 647 8085 Instruction Set Vas: 4 (HL)3B; B= 07 S$. A+B3A; A= 4C+07=54 6 HL+1HL; HL = C205 7. C-1-C; C= 05; Condition not satisfied, go to step 4. ViPass: 4. (HL)+B; B= 08 S$. A+B3A; A= 54408 =5C 6 HL+15HL; HL = (206 7. C-1-4C; C= 04; Condition not satisified, go to step 4 Vil Pass: 4. (HL)>B; B= 02 3. A+B>A, A= SC+02 = SE 6 HL+1>HL; HL 7. C-1+C, C= 03; Condition not satisfied, go to step 4. VIII Pass: 4. (HL)+>B; B= 01 3. A#B3A; A= SE+01 = 5F 6 HL+1>HL; HL = C208 7. C-1>C, C= 02; Condition not satisified, go to step 4. IX Pass: 4. (HL)>B; B= 50 3. A#B3A; A= SF450= AF 6. HL+1—+HL; HL = C209 7. C-13C; C= 01; Codition not satisified, go to step 4, X Pass: 4. (HL)>B; B= 10 5. A#B3A; A= AF+10 = BF 6. HL+1+HL; HL = C20A 7. C-1-4C; C= 00; Condition is satisfied program control comes out of loop. A> (C300); Stop. Final result : [C300 = BF | and C200 to C209 data will remain as it is.6-48 Microprocessor Techniques 8085 Ing Cm in we a pep ema ee. ee ee Gee Ga Data is ren starting fom C300 onwal X may be 16 bits. Store the LSS resut at C3FE and MSB result at CSFF locations, bytes Soin. : The prognim is sume as previous program, with one change the result is 16 bits. Definition and solution plan remains same. Logic of 16 bit result : When 8 bits added with 8 bits, the result may be 9 bits. In this case 8 bits result is Stored in register and cany flag is set. In this example, 16 bit result is present so we keep result register common and go on counting the carries generated in addition. It is represented in flowchart, Program : (For flowchart refer Fig. 6.9) Label Instruction LXI_ oH, C200 H MVI C,0AH MVI A, 00 MVI_ D, 00 UP: MOV B,M ADD B JNC DOWN INR D DOWN: INX H DCR C INZ UP STA C3FE H MOV A,D STA C3FF H HLT Tnivalte courier endl inaripar oink sae Gest S00 eho ea asa Tay Take data using memery paar Operation + €200->H (Memory pointer) : 0A C (Counter) 100A Result reg) + 00D (Cany counter) : (HL) >B PAHBOA If camy = reset go to Down :D+I5D :HL+15HL :C-13C : If ze flag = A> (CFE) :DoA Teset go to UpMicroprocessor Techniques S49 8085 Instruction Sot Output Solution plan : 1. Load 2 data bytes in re Initialise B register, B = 99, Initialise result register pait HL Add number, to result To implement this Program : (For flowchart ref 2 . 4 Label Instruction MVI__D, number, MVI_C, number, MVI__B, 00 LXI__ H, 0900 UP: DAD B DcR D INZ UP HLT 6.8.11 Operating on Block of A] Block transfer : Source Destination ©2900) c400| CaFF| CaF @ C200] corr fet Fig, 6.10) * Result in register pair, ‘gisters D and C. = 0000, I, number, tims, se umber, as a counter, Operation Load number, and namborg| in Dand G| tegisters and make 8 rag, «= 00 number, > D Initialise result rogistor = 0000 number, > C Rosult= number, + result 0 >B 0000 > HL Number, = number, —1 HL+BCHL D-1>D IsC=0, if no go to Up Stop Data : Source Destination c2s0| c34F| (b) Fig. 6.11 <> os Cina) Fig, 6.10 Destination c1s0| 1 Source { 200] ' c2aF| 1 C2FF| t © transfe ic 3 cases we have to move block of data from one location to another. There are ae locks are not overlapping. Source and destination are totally different as shown in Fig. 6.11(a). 2 Two blocks are overlapping as shown in Fig, 6.11(b) from half part onwards, Two blocks are overlapping as shown in Fig. 6.11(c). Upto first half part. i reparing program for block transfer for first case, initilise 2 memory pointers, : Neale ie) Peat core dn using 2. We can start from higher address or lower address as we wish.Microprocessor Techniques ~> C250, The conteny, sfering dat re will NOL Bet the eon Cay 2 ase 2, if we start (ni it of CHF. De, 2. ie Sista te ie (© CHF. Decrement Poin implement this tense we MOT teh a In this case we have to * data and reach up to C200 0 icble ns For case 3, the oe vee ' = Pinte incremented, transfer data, and A & C200 data is. transfer 3 COFF and C24F. tored in locations at bytes of data st Cas 7 am to transfer 16 es to et? eer esas starting from C300 onwards. S ni Soln. : a ine Block of data, stored in memory y location, x sfer to another memory Out Targa onsen ia mene frm C300 to C30R, Solution plan : A 1. Iisa block transfer program so we require 2 memory pointers : (1) for Source blag, 2) for destination block, eink Be 2. Number of data bytes to be trsferred is 16 so counter = 16 M decimal. op hexadecimal a Simple block transfer, no overipping, Take data using pointer, and transfer day Pointer. > Pointcry = Pointer, +1, Pointer, = Pointer + 1 Repeat above steps 3 and 4 for 16 times. Program : (For flowchart refer Fig. 6.12) Label Instruction we Operati LXL OH, Q2s0H ©2505 Initialise memory pointer, and memory pointer, (Pointer ; i Initialise counter = number of data bytes eC C00» De (Pointer, ) IM GH nae” Store data Using memory omer, UP: MOV A.M : “ae 2 , : A Memory Pointer memory pointer, v7 StAX; D +A (DE) Memory pointer =memory, Pointers 4 INX oH HL+1 HL a D : DE+15D8 ne c :C-15¢ UP + Is counter = 0, if no go 0 HLT : Stoption Set Microprocessor Techniques 6-51 8085 Instruction oe ee data consisting of 256 bytes, stored in 7 memory starting at c ‘000 H. This block is to be shifted (relocated) in memory from COS0-H onwards. p, © not shift the block or part of the block anywhere else in the memory, Soln. : Definition ; Input + Block of data, stored in memory from C000 onwards. Operation Transfer to another memory location, Output * The transferred data in memory from COSO onwards, Solution plan : 1, It is a block transfer Program so we require 2 memory pointers : (1) for source (2) for destination, 2. Number of data bytes to be transferred is 256. So counter hexadecimal, = 256 in decimal = FF in Overlapping block transfer. Last part of source is overlapped with destination, so we start from last location of source, 4 Memory pointer, = memory pointer, ~ 1 Gan) ‘and memory pointer, = memory pointer, ~ 1 &o 5. Repeat the above steps for 256 times. Inialse memory pointer, and momary paTary Program : (For flowchan refer Fig. 6.13) ¥ Label Instruction Operation LXl H, COFRH =: COFF5HL Memory pointer, Take data using memon ointer,, an Soe cate aig a Memory pointer, = memory pointer, 1, MVI_ C, FF H + FF C counter Memory pointer=memory pointer, 1 UP :MOV A, M (HL) >A STAX D 2 A>(DE) Counter = counter—1 DCX H :HL-15 HL Dex D : DE-1>DE DCR C :C-15C INZ’ UP rISC=0, if no go to Up. HLT : Stop Fig. 6.13 . din memory from Ex. 14: Write a program to transfer a block of data. The data is store m C550 H to CSF H. The data is to be stored from C570 H to CSTE H in reverse order. (Data from : C550 -+ C57F and so on up to CSSF -> C570) Input : A block of data stored in memory from C550 H. Operation: Transfer to another location. Output + Transferred data in memory from CS7F onwards in reverse order.Microprocessor Techniques 682 8085 Instruction g et Solution plan : 2 3 5] Ex. It is a block transfer program so we require 2 memory pointers : (1) for source and (2) for destination. : Number of data bytes to be transferred is 16 so counter = 16 in decimal = OF in hexadecimal : Simple block transfer, no overlapping but data to be stored in reverse format. 4, Pointer, = Pointer, +1, Pointer, = Pointer, - 1 5, Repeat above steps 3 and 4 for 16 time, Program : (For flowchart refer Fig. 6.14) Initialise memory pointer, and memory pointers Tikaina sone Label Instruction Operation LXI H, C550 H C550-HL Take data using memory pointer, and LXI-B, CS7F H_: C57F4BC store data using memory pointer, MVI—D, OF :0F 3D Memory pointer, = memory pomter, +7 UP: MOV A,M (HL) >A Memory pointer, = memory pointer, —1 STAX B A> (BC) z INX H HL+1>h Counter = counter— 1 Dex 2B : BC-1 +R DCR D :D-1+D INZ UP. :IsD=0, if no g0 to Up HLT Stop Add operation on data block : 15: Write a program to add 2 arrays and generate a third array of results. Addition should be performed as follows : first elements of array, with array, Store resutt in array, and so on upto end The array consists of 10 bytes of data. Array,, starts from C100 onwards, anay, from C200 onwards and array, should start from C300 onwards. Soln. : Definition : Input : 2 arrays of 10 bytes each stored in memory. Operation : Addition of 2 data bytes. Output : Result should be stored as array in memory. Solution: plan : 1 2. Fa Data stored in memory so using Memory pointers access data, Number of data bytes to be added ‘is 10 use it as a counter, Memory pointers required so use HL, BC and DE. There will be shortage of register for counter so use memory location as a counter. Take data using memory pointers add and store in array using memory pointer.ion Set Microprocessor Techniques 6-53 8085. Instructi Program : (For flowch Label Instruction MVL A, oA HL hart refer Fig, 6.15) Comments + Initialize memory 5 location to use as 3 counter STA C0so H UXT H, C1OOH ; Initialize memory + pointer, LXL BL C200; Initialize memory 5 pointer, : LXID, C300 H; Initialize memory 3 pointer, uP LDAX B ake data | using ptr, in acc. | ADD M + Add data, + data, 5 > accumulator Initialise memory pointers 1, Bands | STAX D 3 Store result using | } memory pointer 3 Initialise counter | INX H 3 Memo: = | al Take data, and data, using | > memory pointer, +1 memory pointers 1 and 2 | INX B 3 Memory pointer, = | 5 memory pointer, +1 Fadia ana aay +d | INX D Memory pointer, = | (SSS perecar using memory pomnter3 3 Memory pointer, +1 r LDA C0SOH ; Take counter in Memory pointer's = memory pointers +7 | ‘Acres counter = counter = 1 | DCR A pA-ISA 4 | STA C050 H_— ; Store counter in counter = 0. | ; Memory 2 JNZ UP + Is counter = 0, Nes if no go to Up HLT 5 Stop Fig. 6.15 8.9 Logical Group : ihe logical group of instructions include following instructions : i OANA 2 ANA M 3. ANI data 4. ORAR i ORAM = 6.OORI datas 7) XRAR 8 OXRAM 1 XRI data’ 10. CMA 1. CMC 12. STC 3. CMPR 14. CMPM 15, CPI data 16. RLC 7. RRC 18, RAL 19. RAR Now, we study the above 19 instructions in detail 49.1 ANA R: nie Description : Logically AND register with accumulator. : : : = The f the specified register are logically ANDed with caneias of eerainlae and result is placed in accumulator. The operation