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IP Core Based Counter Design

This document describes an IP core based counter design. It defines an entity called IP_code with inputs for a clock, clear, load, and load value and an output for the counter value. The architecture instantiates a component called c_counter_binary_0 that maps the inputs and outputs of IP_code to perform the counter functionality.

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SAYAN CHATTERJEE
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32 views

IP Core Based Counter Design

This document describes an IP core based counter design. It defines an entity called IP_code with inputs for a clock, clear, load, and load value and an output for the counter value. The architecture instantiates a component called c_counter_binary_0 that maps the inputs and outputs of IP_code to perform the counter functionality.

Uploaded by

SAYAN CHATTERJEE
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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1.

IP core based Counter Design


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity IP_code is
Port ( clk,ce,sclr,load : in STD_LOGIC:='0';
L : in STD_LOGIC_vector(15 downto 0):="0000000000000000";
Q : out STD_LOGIC_vector(15 downto 0):="0000000000000000");
end IP_code;

architecture Behavioral of IP_code is

component c_counter_binary_0 IS
port (
clk: IN std_logic;
ce: IN std_logic;
sclr: in std_logic;
load: IN std_logic;
L: IN std_logic_VECTOR(15 downto 0);
Q: OUT std_logic_VECTOR(15 downto 0));
END component;

begin
UUT : c_counter_binary_0 port map(clk,ce,sclr,load,L,Q);

end Behavioral;

2. hhhh

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