CIRCUIT DIAGRAM:

MONOSTABLE MULTIVIBRATOR:

+Vcc = 5V

4 8

R = 10KΩ 3 Vout
7

555 5
6
C = 0.1µF C = 0.01µF

2 1

Trigger input

ASTABLE MULTIVIBRATOR:

+VCC = 5V

RA = 10KΩ 8
4
3 Vo
7
555
RB= 10KΩ 5
6 C = 0.01µF

2 1
C= 0.1µF
Expt.No:8
ASTABLE AND MONOSTABLE MULTIVIBRATOR
USING NE555 TIMER
AIM:
To design, construct and test the Astable Multivibrator and Monostable Multivibrator
using NE 555 timer
COMPONENTS REQUIRED:
S.NO APPARATUS NAME RANGE QUANTITY
1. Regulated power supply (0-30) Volts 1
2. Signal generator 1MHz 1
3. CRO 20MHz 1
4. Resistors 10kΩ 2
5. Timer IC NE555 1
6. Capacitors 0.1µF,0.01µF 1
7. Breadboard 1
8. Connecting wires As required

DESIGN:
Astable Multivibrator:
Let Vcc = 5V
Vc = ⅔ Vcc
T= 0.69 (RA+2RB) C
1 1.45
f  
T R A  2 RB C
Let RA = RB = R
T = 2.1RC
Assume R = 10KΩ and C = 0.1µF for T = 2.1ms
Also Ton = 0.69(RA+RB) C
Toff = 0.69RBC
MODEL GRAPH:
MONOSTABLE MULTIVIBRATOR
Output voltage

T (ms)
Output voltage across capacitor
Vcc
2/3
Vcc
1/3

Tlow Thigh

Ground 1 8 Vcc

Trigger 2 7 Discharge
555

Output 3 6 Threshold

Control
Reset 4 5 Voltage
Monostable Multivibrator:
T = 1.1RC
Assume R = 10KΩ and C = 0.1µF for T = 1.1ms
THEORY:
IC 555:
The astable and monostable circuit are commonly available in monolithic ICs, and
IC timers. The timer 555 is one example which has gained wide acceptance in terms of cost
and versatility. It was first introduced by Signetics Corporation as SE/NE 555. Some
important applications of this device are –monostable and astable multivibrators, dc-dc
converters, digital logic probes, waveform generators, analog frequency meters and
tachometers, temperature measurement and control, infrared transmitters, burglar and toxic
gas, alarms, voltage regulators, etc.
The IC 555 timer is a 8-pin IC that can be connected to external components for either
astable or monostable operation. The 555 timer will work with any supply voltage between
4.5V and 10V.In the internal structure of the 555 timer there are one flip flop and two op-
amps. The non-inverting input of upper op-amp is called as threshold voltage and inverting
input is called as control voltage.Multivibrators is group of regenerative circuits. They are
widely used in timing applications.Multivibrators are classified as
(1) Bistable multivibrators
(2) Monostable Multivibrators
(3) Astable Multivibrators
ASTABLE MULTIVIBRATORS:
Astable circuits are used to generate square waves. It is also known as free
running multivibrator.It has two quasistable states. Thus there is no oscillation between these
two states and no external signals to produce the change in state.
As there is no need of trigger input the second pin is connected to the sixth pin.
Comparing with monostable operation, the timing resistor is now split into two sections RA
and RB. Pin 7 is connected to the junction of R A and RB. When the power supply Vcc is
connected, the external timing capacitor C charges towards V cc with a time constant (RA+RB)
C. When the
ASTABLE MULTIVIBRATOR:

voltage Output voltage

o/p

T(ms)
Vcc
2/3
Vcc
1/3

Tlow Thigh

TABULATION:
MONOSTABLE MULTIVIBRATOR:
Parameter Amplitude(V) Time period(ms)
Output voltage

Capacitor voltage

ASTABLE MULTIVIBRATOR:
Parameter Amplitude(V) Time period(ms)
Output voltage

Capacitor voltage
threshold voltage exceeds ⅔Vcc, the upper op-amp has a high input and this sets the flip flop
allowing the capacitor discharging through RB. Therefore the discharge time constant is RBC.
When the capacitor drops below +Vcc/3, the lower amplifier has higher input and this resets
the flip flop. The capacitor C is thus periodically charged and discharged between (2/3) Vcc
and (1/3) Vcc. The total time period is given by
T = 0.69 (RA+2RB) C.
MONOSTABLE MULTIVIBRATORS:
The 555 timer configured for monostable operation is shown in the figure.
Monostable multivibrator often called a one shot multivibrator is a pulse generating circuit in
which the duration of this pulse is determined by the RC network connected externally to the
555 timer. In a stable or standby state, the output of the circuit is approximately zero or a
logic-low level. When external trigger pulse is applied output is forced to go high ( VCC).
The time for which output remains high is determined by the external RC network connected
to the timer.At the end of the timing interval, the output automatically reverts back to its
logic-low stable state. The output stays low until trigger pulse is again applied. Then the
cycle repeats. The monostable circuit has only one stable state (output low) hence the name
monostable. The time during which the output remains high is given by

PROCEDURE:
1. Get the required components and check the condition of them.
2. Connect the circuit as per the circuit diagram.
3. Switch on the power supply and look at the output with CRO.
4. Measure the width and time period of the output waveform.
5. Look at the voltage across the capacitor, an exponentially rising and falling wave between5V
and 10V is noted.
6. After completing the experiments, reduce the supply to zero potential and disconnect
the circuit diagram.
RESULT:
Thus the astable and monostable multivibrators was designed and tested using
NE555 timer.
DISCUSSION QUESTIONS:
1. What are the applications of 555 timers?
The applications of 555 timers include oscillator, pulse generator, burglar
alarm,
and traffic light control

2. Define duty cycle.

The duty cycle D of a circuit is defined as the ratio of ON time to the total
time period T= (tON +toff).

3. What is the function of 555 Timer?

The 555 timer is a highly stable device for generating accurate time delay or
oscillation. A single 555 timer can provide time delay ranging from microseconds
to hours
.
4. What are the modes of operation of a timer?
The modes of operation of timers are monostable and astable mode.

5. What are the applications of 555 timer in monostable mode?

The applications of 555 timer in Monostable mode are
(i) Missing Pulse Detector
(ii) Linear Ramp Generator
(iii) Frequency Divider
(iv) Pulse Width Modulation

6. What are the applications of 555 timer in Astable mode?

The applications of 555 timer in Astable mode are
(i) Pulse-Position Modulator
(ii) FSK Generator
(iii) Schmitt Trigger
4-to-1 line MUX (or) 4x1MUX

I0 0
I1 1
I2 4x 1 Y
2
I3 MUX
3

S0 S1

Truth Table

S0 S1 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

Logic Diagram
S0 S1

7411

S0 ' S1 '
I0

I1
Y

I2 Y= I0 S0 'S1 '+
I1 S0 'S1 +
I2 S0 S1'+
I3 I2 S0 S1
Expt. No .9

DESIGN AND IMPLEMENTATION OF 4:1 MULTIPLEXER AND 1:4

DEMULTIPLEXER

AIM:
To design and implement
(i) 4x1 Multiplexer
(ii) 1x4 Demultiplexer using logic gates.

COMPONENTS REQUIRED:

S.NO COMPONENT NAME RANGE QUANTITY

1. Digital trainer kit 1
2. IC7411, IC7432, IC7404 Each 1
3. Breadboard 1
4. Connecting wires

THEORY:
Multiplexer (or) Data selector (or) MUX
A digital multiplexer is a combinational circuit that selects binary information from
one of many input lines and directs it into a single output line. The selection of a particular
input line is controlled by a set of selection lines (S 0, S1 … Sn-1)
Block Diagram
I0
I1 . I inputs
2n x 1 Y
. Y output
. MUX
In-1 S Selection lines
.
.
.

S0, S1 Sn-1
Kinds:
2x1 MUX, 4x1 MUX, 16x1 MUX, 32x1 MUX and so on..
2x1 MUX
A logical symbol for 2 inputs (I0, I1) MUX consists of 1 selection line - S0 and one
output (Y).
4x1 MUX
A 4-to-1 line multiplexer consists of 4 inputs (I 0, I1, I2, I3) and 2 selection lines (S0, S1
) . The circuit operation is as follows. Consider S0, S1, as 10. The AND Gate associated with
input I2 has two of its inputs as 1 and the third input is connected to I2. For the other AND
gates at least one input is zero which makes the net output from the AND gate to be zero. The
OR gate value is now equal to the value of I2 ,
1-to-4 line DEMUX (or) 1x4 DEMUX
Logic Diagram
S0 S1
Y0
Din 1x4 Y1
DEMUX Y2 7411
Y3 S0 ' S1 '
Din Y0

S0 S1
Y1

Y2

Y3
Truth Table

S0 S1 Y3 Y2 Y1 Y0
0 0 0 0 0 Din
0 1 0 0 Din 0
1 0 0 Din 0 0
1 1 Din 0 0 0
Demultiplexer (or) Data distributor (or) DEMUX
A digital demultiplexer is a combinational circuit that accepts a single input and
distributes it into the specified number of output lines. The selection of a particular output
line is controlled by a set of selection lines (S0, S1 … Sn-1)
Block Diagram
Y0
Din 1x2 n Y1 D inputs
.
DEMUX . Y output
. . Yn-1 S Selection lines
.
.
S0, S1 Sn-1
Kinds:
1x2 DEMUX, 1x 4 DEMUX, 1x 16 DEMUX, 1x 32 DEMUX and so on..
1x2 DEMUX
A logical symbol for 1 input (Din ) MUX consists of 1 selection line - S0 and one
output (Y).
1x4 DEMUX
A 1-to-4line demultiplexer consists of 1 input(D0) ,4 outputs (Y0, Y1, Y2, Y3) and 2
selection lines (S0, S1 ) . The circuit operation is as follows. Consider S 0, S1, as 10. The AND
Gate associated with output Y2 has two of its inputs as 1 and the third input is connected to
Din. For the other AND gates at least one input is zero which makes the net output from the
AND gate to be zero. Thus the output gets distributed in the I 2. Hence, DEMUX is also called
as a Data distributor.

PROCEDURE:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to Vcc .
3. Apply the inputs to the respective input pins.
4. In 4x1 MUX the inputs are varied for checking the truth table.
5 In 1x4 DEMUX the selection line is varied to verify the truth table
RESULT:
Thus the combinational circuits
(i) 4x1 Mux (Multiplexer)
(ii) 1x4 Demux (Demulitplexer) were designed and implemented using the logic
gates.

DISCUSSION QUESTIONS:

1. Define multiplexer?
A multiplexer is a combinational circuit that selects one digital information
from several sources and transmits the selected information on a single output line.

2. What is demux?
Demultiplexer is a circuit that receives information on a single line and
transmits this information on one of 2n possible output lines. A demultiplexer is a
decoder with an enable input.

3. What is combinational circuit? Give an example.

A combinational circuit consists of logic gates whose outputs at any time
are determined from the present combination of inputs. Examples of
combinational circuits are adder, coder, magnitude comparator etc.

4. Where Multiplexers are used?

It is used in data selection, data routing, parallel to serial conversion, logic
function generation.

5. What is the other name for demultiplexer?

As the serial data is changed to parallel data, the input caused toappear aon
one of the n output lines, the demultiplexer is also called as distributor or a
serial to parallel converter.
Design

Pin Diagram of IC74180 (8-bit Parity Generator/Checker)

A 1 I 14 Vcc
B 2 C 13 H
EVEN 3 7 12 G
ODD 4 4 11 F
Even O/P 5 1 10 E
Odd O/P 6 8 9 D
Gnd 7 0 8 C

Truth table of IC 74180

Sum of 1s at Even Odd Even Odd

A through H input input output output
Even 1 0 1 0

Odd 1 0 0 1

Even 0 1 0 1

Odd 0 1 1 0

For example
Generator

A B C D E F G H Even Odd
0 0 0 0 0 0 0 0 1 0
0 1 1 1 0 0 0 0 0 1
Expt. No 10

DESIGN AND IMPLEMENTATION OF 8-BIT ODD/EVEN PARITY GENERATOR,

CHECKER USING IC74180
AIM
To implement
(i) Even Parity Generator/Checker
(ii) Odd Parity Generator/Checker using IC74180

COMPONENTS REQUIRED:

S.NO COMPONENT NAME RANGE QUANTITY

1. Digital trainer kit 1
2. IC74180 1
3. Breadboard 1
4. Connecting wires

THEORY:
A parity generator is a circuit that, given an n-1 bit data word, generates an extra
(parity) bit that is transmitted with the word. The value of this parity bit is determined by the
bits of the data word.

In an even parity scheme, the parity bit is a 1 if there is an odd number of 1's in the data
word. Thus when we examine all the bits transmitted (data word + parity), we see an even
number of ones (thus "even" parity).

At the receiving end of the transmission, a parity checker uses this extra information to detect
single-bit errors in the transmitted data word. It does so by regenerating the parity bit in the
same manner as the generator and comparing the two parity bits. Disagreement between these
bits means that one of the transmitted bits is incorrect, though the checker cannot determine
which bit is in error. Note that single-bit parity scheme is unable to detect an even number of
errors (e.g. 4 bits are wrong).

PROCEDURE:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to Vcc .
3. Connections are made as per the logic diagram.
4. Apply the inputs to the respective input pins.
5. Verify the output with the truth table.
RESULT

Thus the implementation of

1. Even Parity Generator/Checker
2. Odd Parity Generator/Checker using IC74180

DISCUSSION QUESTIONS:

1. What is meant by parity bit?

A parity bit is an extra bit included with a message to make the total
number of 1's either even or odd.

2. What is an parity generator?

The circuit that generates the parity bit in the transmitter is called parity
generator.

3. What is an parity checker?

The circuit that checks the parity an receiver is called parity checker.

4. What is an odd parity?

A binary digit that is added to ensure that the number of bits with value of
one in a given set of bits is always odd is an odd parity.

5. What is an even parity?

A binary digit that is added to ensure that the number of bits with value of
one in a given set of bits is always odd is an even parity.
Expt.No. 11
VOLTAGE TO FREQUENCY CHARACTERISTICS OF NE/SE 566 IC
AIM:

To test the voltage to frequency characteristics of NE/SE 566 VCO.

COMPONENTS REQUIRED:
S.No Components name Range quantity
1 NE/SE 566 1
2 Resistance 10 KΩ,1.5KΩ 1,1
3 Capacitance 10µF 1
1µF 1
0.001µF 1
4 Decade Resistance box 1
5. DC Power Supply (0-30)V 1
7. CRO 20MHZ 1
8. Bread board 1

Design:
2 V  Vc 
fo 
CT RT (V )
where
3
(v)  vc  (v)
4
CIRCUIT DIAGRAM:
+Vcc

1.5 KΩ RT

0.001µF

C
6 8
3
Vc 5
NE/
SE 566
10KΩ
4
7 1
111

CT

Pin Diagram:

Ground 1 8 +Vcc

NC 2 NE/SE 566 7 CT
Sq.wave VCO
3 6 RT
output
Triangular 4 5 Modulation
wave output Input
THEORY:

Voltage to frequency Characteristics of VCO:

There are applications such as frequency modulation, tone generators, and frequency
shift keying, where the frequency needs to be controlled by means of an input voltage called
control voltage. This function is achieved in the voltage controlled oscillator. A common type
of VCO available in IC form is signetics NE/SE 566.A timing capacitor CT is linearly
charged or discharged by a constant current source/sink. The amount of current can be
controlled by changing the voltage Vc applied at the modulating input (pin5) or by changing
the timing resistor RT external to the chip. The voltage at pin 6 is held at the same voltage as
pin 5. Thus, if the modulating voltage at pin 5 is increased, the voltage at pin 6 also increases,
resulting in less voltage across RT and there by decreasing the charging current. A small
capacitor of 0.001µF should be connected between pins 5 and 6 to eliminate possible
oscillations in the control current source. The frequency of oscillations is determined by an
external resistor RT ,capacitor CT, and the voltage applied to the control terminal 5.

PROCEDURE:

1. Make Connections as per the circuit diagram

2. For voltage to frequency characteristics the modulating input dc voltage is given to
corresponding pin and the waveforms are noted.
TABULATION:

Square wave form Triangular Wave

Amplitude Time Period Amplitude Time Period
RESULT:
Thus the Voltage to frequency characteristics using NE/SE566 was designed and tested.

DISCUSSION QUESTIONS:

1. List the basic building blocks of a PLL (Phase locked loop)

A phase locked loop consists of a phase detector/comparator, low pass filter, error
amplifier, voltage controlled oscillator.

2. Give the uses of low pass filter used in PLL and state its types.
The low pass filter may be active or passive type. The LPF not only removes the
high frequency components and noise, but also controls the dynamic characteristics of
the PLL such as capture range, lock range, bandwidth and transient response.

3. List the applications of PLL.

The PLLs are used as frequency multiplier, divider, AM detection, FM
demodulation and FSK demodulator

4. Write the expression for voltage to frequency conversion factor.

The voltage to frequency conversion factor kv is defined as
f
kv  o
vc
Where ∆vc is the modulation voltage required to produce the frequency shift ∆fo for a
VCO.

5. What is voltage controlled oscillator?

The voltage controlled oscillator generates an output frequency that is directly
proportional to input voltage. These are also called as voltage to frequency converters.
1. SISO (Serial in – Serial out)

Data DA QA DB QB DC QC DD QD Data
in out
FF A FF B FF C FF D

Q'A Q'B Q'C Q'D

MSB LSB

CLK

CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 0 1 0
4 0 1 0 1(MSB)
5 0 0 1 0
6 0 0 0 1
7 0 0 0 0(LSB)

2. SIPO (Serial in – Parallel out)

Data DA QA DB QB DC QC DD QD Data
in out
FF A FF B FF C FF D

Q'A Q'B Q'C Q'D

MSB LSB

CLK
QA QB QC QD

CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 0 1 0
4 0 1 0 1(MSB)
Expt. No .12

IMPLEMENTATION OF SISO, SIPO & PIPO SHIFT REGISTERS

USING D FLIP-FLOP

AIM:
To implement the basic kinds of shift registers using D flip-flop.

COMPONENTS REQUIRED:

S.NO COMPONENT NAME RANGE QUANTITY

1. Digital trainer kit 1
2. D fliflop 2
3. Breadboard 1
4. Connecting wires

THEORY:

Registers:
A group of binary cells (or) flip-flops used for storing the information.
Shift register: A register which is capable of shifting the information either to right/left is
known as shift register.

Types:
1. SISO (Serial in – Serial out)
2. SIPO (Serial in – Parallel out)
3. PISO (Parallel in – Serial out)
4. PIPO (Parallel in – Parallel out)
Assume a 4-bit shift register implemented using D FF. (Eg data: 0101)

Initially all the FF are under RESET condition. Loading the FF starts from LSB.
1. At the end of each clock pulse; a new data is stored inside the FF.
2. At the end of 4th clock pulse; data is loaded into the FF.
3. At the end of 5th clock pulse; data is shifted out.

Data is entered in a serial fashion. Once the data are stored, each bit appears on its respective
output line rather than on a bit-by-bit fashion.

Serial in- Serial out Shift Register:

This type of shift register accepts data serially; i.e one bit at a time on a single input
line.It produces the stored information on its single output also in serial form. Data may be
shifted left using left shift register or shifted right using shift right register.
 3.PIPO (Parallel in – Parallel out)

A B C D

DA QA DB QB DC QC DD QD

FF A FF B FF C FF D

Q'A Q'B Q'C Q'D

MSB LSB

CLK
QA QB QC QD

IC 7474 (D FF)
Serial-in-parallel out Shift register:
It consists of one serial input and outputs are taken from all the flip-flops parallely. In
this register, data is shifted in serially but shifted out in parallel. In order to shift the data out
in parallel, it is necessary to have all the data available at the outputs at the same time. Once
the data is stored, each bit appears on its respective output line and all the bits are available
simultaneously rather than on a bit by bit basis as with the serial outputs.

Parallel-in-Parallel out register:

In this type of register, data inputs can be shifted either in or out of the register in
parallel. Also in this register, there is no interconnection between successive flip flops since
no serial shifting is required. Therefore, the moment the parallel entry of the data is
accomplished, the respective bits will appear at the parallel outputs.

PROCEDURE:
1. Obtain the required flip-flop along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to Vcc.
3. Connections are made as per the logic diagram.
4. Apply the clock pulse in order to load the data into the flip-flop.
5. Verify the truth table.
RESULT:
Thus the different kinds of shift registers were implemented using D flip-flop.

DISCUSSION QUESTIONS:

1. If a serial –in serial –out shift register has N stages and if the clock frequency is f ,
What will be the time delay between input and output?

N
The time delay between input band output is TD =
f

2. What are registers?

A register is a group of binary cells. A register with n cells can store any
discrete quantity of information that contains n bits. The state of a register is an n-
tuple number of 1's and 0's, with each bit designating the state of one cell in the
register.

3. What is meant by register transfer?

A register transfer operation is a basic operation in digital systems. It consists
of transfer of binary information from one set of registers into another set of registers.
The transfer may be direct from one register to another, or may pass through data
processing circuits to perform an operation.

4. Define shift Registers

The binary information in a register can be moved from stage to stage within
the register or into or out of the register upon application of clock pulses. This type of
bit movement or shifting is essential for certain arithmetic and logic operations used
in microprocessors. This gives rise to a group of registers called shift registers.

5. What are the types of shift register?

1. Serial in serial out shift register?
2. Serial in parallel out shift register
3. Parallel in serial out shift register
4. Parallel in parallel out shift register
5. Bidirectional shift register shift register.