METAL-OXIDE-

SEMICONDUCTOR
FIELD-EFFECT
TRANSISTOR
(MOSFET)
Aloke Dutta/EE/IIT Kanpur 1
• Extremely popular device - has almost
pushed BJTs out of the market
• Three-Layer Device (Metal, Dielectric, and
Semiconductor)
• Four-Terminal Device [Drain (D), Source
(S), Gate (G), and Body/Substrate (B)]
• Current through two terminals (D and S)
can be controlled by the voltages applied at
G and B
 Voltage Controlled Device
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• Unipolar device
 Either electrons or holes participate in current
conduction
• Active device
 Capable of producing voltage/current/power
gain
• Two basic usage:
 Amplification (Analog Circuits)
 Switching (Digital Circuits)
• Two Types: NMOS and PMOS
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 NMOS Structure
G
tox
SiO2 Gate
W
S D

+ +
n n
Lact
LD LD
L

p-Si sub (N A)

Aloke Dutta/EE/IIT Kanpur 1

• Technology Parameters:
 Channel Length (L)
 Channel Width (W)
 Oxide Thickness (tox)
 Substrate Doping (NA)
• LD: Lateral overlap between G and S/D
• Actual channel length: Lact = L  2LD
• For now, we will assume LD = 0
 Lact = L
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Symbols and Current-Voltage
Conventions
D S
+ + + +
ID VSG
VSB
– –
G B VDS G B VSD
+ +
ID
VGS VBS
– – – –
S D
NMOS PMOS

Aloke Dutta/EE/IIT Kanpur 3

• Voltage Convention:
 NMOS: VGS (gate-source voltage), VDS (drain-
source voltage), VBS (body-source voltage)
 PMOS: VSG (source-gate voltage), VSD (source-
drain voltage), VSB (source-body voltage)
• Current Convention:
 NMOS: ID (drain current) flows into the drain
terminal and exits from the source terminal
 PMOS: ID flows into the source terminal and
exits from the drain terminal

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• Gate is DC isolated by the insulator
 Gate Current IG = 0
 Tremendous advantage!
• Same current ID flows through the device
• Extremely compact device
 Saves a lot of area
• Reversible device:
 D and S terminals are determined by their
bias states

Aloke Dutta/EE/IIT Kanpur 5

 Operation
inversion
layer
VG
Source (S) Drain (D)
gate
oxide
+ +
n n

depletion 0 L
region p-Si sub (N A)

Body (B) VDS = 0

Aloke Dutta/EE/IIT Kanpur 1

• The structure is similar to an n+pn+ BJT
• However, BJT action is not possible due to
large channel length (L)
• The way to make the device conduct is to
form a layer of electrons between S and D
 Known as Inversion Layer
• Then, if a bias is applied between S and D,
then inversion layer electrons will move
towards the higher potential due to drift
 A current would result
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• Consider VS = VD = VB = VG = 0
 Device is off and no current flows
• Note that the structure is similar to a
capacitor
• Now, as VG is made positive, initially it will
repel holes from surface towards bulk,
uncovering ionized acceptor atoms there
 Formation of a depletion layer
• There will be depletion layers around SB
and DB junctions as well
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• As VG is kept on increasing, the depletion
charge will keep on increasing
• At a certain value of VG (= VGS), a layer of
electrons will appear at the surface
• This particular value of VGS is known as
the threshold voltage VTN
• Still no current would flow, since VDS = 0
• SB and DB junctions must remain either at
zero bias or reverse bias all the time
 VSB and VDB  0
Aloke Dutta/EE/IIT Kanpur 4
 inversion
layer
VD
VG
Source (S)
ID
Drain (D)
gate
oxide
+ +
n n

depletion
0 L
region
p-Si sub (N A)

Body (B) VDS > 0

Aloke Dutta/EE/IIT Kanpur 1

• With VDS > 0, inversion layer electrons will
move towards the higher potential, i.e., D
 The drain current ID would flow from D to S
• Note:
 The depletion charge would increase as we
move towards the D (since the DB junction is
more reverse biased)
 The inversion charge would decrease as we move
towards the D
 For sufficiently high VDS, it may disappear
altogether

Aloke Dutta/EE/IIT Kanpur 2

 Body Effect
• The threshold voltage VTN is a function of
the SB voltage VSB
• As VSB, the SB junction depletion charge
would increase
 For the same VGS, inversion charge would
decrease (to maintain charge balance)
 Thus, to restore the original level of inversion,
VGS has to be increased
 Implies that VTN has increased
Aloke Dutta/EE/IIT Kanpur 3
• Expressed as:
VTN  VTN0    2F  VSB  2F 
VTN0  VTN VSB  0
= Zero back -bias threshold voltage

2qs N A
 = Body -effect coefficient
Cox
 ox
Cox  = Oxide capacitance per unit area
t ox
 NA 
F  VT ln   = Bulk potential (~ 0.3 - 0.45 V)
 ni 
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 Current-Voltage Relation
• For VGS > VTN and small VDS:


I D  k N VGT VDS  V 2
DS 2 
VGT = VGS  VTN = Gate overdrive

k N   W L  k N
 Device transconductance parameter

W/L = Aspect ratio

Aloke Dutta/EE/IIT Kanpur 1
 k N   n Cox
 Process transconductance parameter
n = Channel electron mobility
2
• For small VDS, the V DS term can be
neglected
 ID changes linearly with VDS
 Linear (or Non-Saturation) Region
• As VDS, the restraining effect of VDS
2

term
 Rate of increase of ID with VDS slows down

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• For inversion channel to exist at the D end,
VGD must be > VTN
 VDS must be < VGT
• When VDS = VGT, the channel is said to be
pinched-off at the D end, and ID does not
increase any more
• This value of VDS is known as the drain-to-
source saturation voltage VDS,sat
 VDS,sat = VGT

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• For VDS > VDS,sat, the mode of operation is
known as saturation
• Drain current in saturation:
kN 2
ID  VGT
2
 Obtained from the non-saturation ID
expression by substituting VDS = VGT
 Note that ID is independent of VDS
• Above equations are valid for VGT > 3VT
(~ 80 mV at room temperature)
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The Complete LEVEL 0 Model

I D  k N VGT VDS  VDS
2
2 
 linear region - VGT  3VT , VDS  VGT 
  k N 2  VGT
2

(saturation region - VGT  3VT , VDS  VGT )

0
(cutoff region - VGT  3VT , any VDS )

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ID
Non-
saturation Saturation

VGS3

VDS,sat = VGT VGS3 >

VGS2 >
VGS2 VGS1 >
(VTN + 3VT)
VGS1

0
VDS
VGS  (VTN + 3VT)

ID-VDS Characteristics

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Channel Length Modulation (CLM)
Inversion
Channel Pinch-Off
Point P
VDS > VDS,sat
Xd
S D
+ +
n n

Depletion
Region
p-Si sub
0 Leff L

Xd  length of the pinched-off region

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• For VDS = VDS,sat, pinch-off point P at D
end
• For VDS > VDS,sat, P moves towards source
• Effective channel length reduces from L to
Leff = L – Xd
 Xd = pinch-off region/drain region/saturation
region length
• Excess voltage (VDS – VDS,sat) drops across
Xd

Aloke Dutta/EE/IIT Kanpur 2

• Reduction of effective channel length
causes an increase in current
 Channel length modulation
• With VDS↑, Xd↑, Leff↓, and ID↑
 No real current saturation
• Thus, saturated drain current:
I D,sat   k N 2  W Leff  VGT
2

  k N 2  VGT
2
1  VDS 

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•  = Channel length modulation parameter
1 dX d

L dVDS
 Function of L and NA
 Higher L and NA => Lower λ
 Typical values of λ may range from close
to 0 to as high as 0.1-0.3 V–1
 Very similar to VA for BJTs

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• This gives LEVEL 1 model (also known as
Shichman-Hodges model) for MOSFETs:
I D  k N  VGT VDS  VDS
2
2  1  VDS 
(linear region - VGT  3VT , VDS  VGT )
  k N 2  VGT
2
1  VDS 
(saturation region - VGT  3VT , VDS  VGT )
=0
(cutoff region - VGT  3VT , any VDS )

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 ID VDS,sat = VGT
VGS3 > VGS2 > VGS1 > (V TN + 3VT)

VGS3
Actual

VGS2

VGS1
Ideal
0
VDS
VGS < (V TN + 3VT)

ID-VDS Characteristics in presence of CLM

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 DC Bias Point Calculation
VDD
• To find RD for BB 5V

 VTN0 = 1 V, k N = 40 A/V2,
ID
RD
V0
RG
W/L = 10 10 k
M
• Body terminal not shown VG
IG
2V
 Implies that it is connected
to the most negative potential available in the
circuit (ground in this case)
 VSB = 0  VTN = VTN0
• IG = 0  VGS = VG = 2 V
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• VGT = VGS  VTN = 1 V
• Assuming saturation mode of operation
and neglecting CLM:
I D   k N 2  VGT
2
 200 A
• For BB, VDS = VDD/2 = 2.5 V (2-element
output branch):
RD = (VDD  VDS)/ID = 12.5 k
• VDS > VGT  Assumption of saturation
mode of operation validated
• PD = VDS  ID = 0.5 mW
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 Small-Signal Model
• The electrical equivalent of the MOSFET at
the DC bias point
• Must be biased in saturation
 Resembles a constant current source
• DC analysis must precede, since need the
information regarding the Q-point (ID, VDS)
• This model for NMOS and PMOS is the
same (incremental model)
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 Validity of the
Small-Signal Model
• The instantaneous current VDD
(assuming VDS < 0.1): ID + id

kN
 VGT  vi 
2
Id  +
VB
2 vi
M

kN
 ID   2VGT vi  vi2  –
+
2 VGS
–
 vi 
 i d  k N VGT vi 1  
 2V GT 

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• Thus, for linear relationship between id and vi,
vi must be << VGT
• Note that VGT (minimum) = 3VT
• Hence, vi should be at least ten times less than
3VT
• Recall in BJT, for linear relationship between
ic and vi, vi has to be << VT
 Three times less than that for MOSFET
 MOSFETs are inherently more linear device
than BJTs (compare quadratic with exponential)
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Small-Signal Model Parameters
• Transconductance (gm):
I D
gm 
VGS VDS and VSB constant

 k N VGT 1  VDS   2k N I D 1  VDS 

 If VDS < 0.1:

g m  k N VGT  2k N I D

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 An important Figure of Merit is
transconductance to current ratio
 For MOSFETs: gm/ID = 2/VGT
 For BJTs: gm/IC = 1/VT
 Thus, BJTs produce more gm per unit current
 As we will see later, a high value of gm is
highly desirable, since it dictates the gain
 gm/ID can be changed by changing the bias
current and/or aspect ratio
 gm/IC is a function only of temperature

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• Body Transconductance (gmb):
I D
g mb   g m
VBS VGS and VDS constant


  Body factor (~ 0.1-0.3)
2 2F  VSB

 Note: As VSB, VTN  ID

 ID/VSB would have yielded negative gmb
 If both B and S are tied to fixed DC potentials
(including ground), gmb won’t matter!

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• Output Conductance (g0)/
Output Resistance (r0):
1 I D I D
g0  r  
VDS 1  VDS
0
VGS and VSB constant

 If VDS < 0.1:

g0 = 1/r0  ID
  has a very wide range ~ 0.01-0.5 V1
 When  → 0, g0 → 0, and r0 → 
 Device starts to behave like a constant current
source

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• Gate-Source and Gate-Drain Capacitance
(Cgs and Cgd):
 Each has two components: intrinsic (i) and
technological (t)
 Total intrinsic gate-body capacitance:
Cgbi  Cox WL
 Using Meyer’s model, intrinsic component:
 In linear region: Cgsi = Cgdi = Cgbi/2
 In saturation region: Cgsi = (2/3)Cgbi, Cgdi = 0
 Technology component arises due to gate-
source and gate-drain overlap (LD)
Aloke Dutta/EE/IIT Kanpur 1
 Technology components:
Cgst  Cgdt  Cgs0 W  Cgd0 W
Gate -Source /Drain Overlap Capacitance
per unit width: Cgs0  Cgd0  Cox L D

Thus, total capacitance in saturation:

Cgs   2 3 Cox WL  Cgs0 W
Cgd  Cgd0 W

 Cgs >> Cgd

Aloke Dutta/EE/IIT Kanpur 2
• Source-Body and Drain-Body Capacitance
(Csb and Cdb):
 Both reverse-biased n+p junctions
Csb0 Cdb0
Csb  and Cdb 
1  VSB V0  1  VDB V0 
m m

Csb0  Csb VSB  0

and Cdb0  Cdb VDB  0

VSB and VDB  0

• Drain/Source Series Resistance (RS and
RD):
 Due to neutral n+ source/drain regions
Aloke Dutta/EE/IIT Kanpur 3
 The Hybrid- Model
Cgd
G D' RD D

+
vgs Cgs gmvgs gmbvbs r0
–

S'
–
RS vbs Csb Cdb
+

Aloke Dutta/EE/IIT Kanpur 1

• Simplifications:
 RS and RD can be safely neglected
 For low to moderate frequencies, the
capacitive reactances of all the capacitances
will be extremely large  can be neglected
 If both B and S are connected to fixed DC
potentials, current source gmbvbs disappears
 Leads to the Low-Frequency T-Model, having
only two components: gmvgs and r0
 Simplest possible equivalent results if r0 is
also neglected (ideal current source!)
Aloke Dutta/EE/IIT Kanpur 2
G D

vgs gmvgs gmbvbs r0 G D

+ G D
–
vgs gmvgs r0 +
S –
vbs vgs gmvgs
–
+
–
B S S

Low-Frequency T-Model Low-Frequency T-Model

Without CLM
With Body Effect Without Body Effect

Aloke Dutta/EE/IIT Kanpur 3

 Frequency Specification
of MOSFETs
• Only Unity-Gain Frequency (fT)

ii Cgd

ii

+
vgs Cgs gmvgs
i0 i0
vgs
–

Aloke Dutta/EE/IIT Kanpur 4

• i0  gmvgs (neglecting reverse transmission
through Cgd)
• ii = j(Cgs + Cgd)
i 0  j  gm
 
ii  j j  Cgs  Cgd 
At f = f T , i 0 ii  1
gm
 fT 
2  Cgs  Cgd 
• Remarkable similarity with that for BJT

Aloke Dutta/EE/IIT Kanpur 5

• Maximum Operable Frequency (fmax):
 Maximum possible fT
 Noting that Cgs >> Cgd, neglecting Cgst, and
substituting the expressions for Cgsi and gm:
3 n VGT
f max  f T max 
4L2
 fmax  1/L2
 Thrust towards making L as small as possible
 fmax  VGT
 Making VGT large may be detrimental!

Aloke Dutta/EE/IIT Kanpur 6