5

Digital-to-Analog Converter
Arch itectu res

With the basic principles of DI A conversion explained in Chapter 4, we can

now study this function from an architectural perspective. This chapter de-
scribes D/A converter architectures based on resistor ladders and current-
steering arrays, with emphasis on stand-alone applications. While the capaci-
tor DACs introduced in Chapter 4 are frequently used in AID converters, they
have not been popular as stand-alone circuits, primarily because they require
a buffer to drive resistive loads and are also susceptible to nonlinear capacitive
loading (e.g., due to switch junction capacitance).

5.1 RESISTOR-LADDER DAC ARCHITECTURES

The simplicity of resistor-ladder DACs using MOS switches makes these ar-
chitectures attractive for many applications. However, for resolutions of 8
bits and above a simple ladder such as that described in Section 4.3.1 suffers
from several drawbacks: it requires a large number of resistors and switches
(2 m , where m is the resolution) and exhibits a long delay at the output. Conse-
quently, alternative ladder topologies have been devised to improve the speed
and resolution.
This section describes several resistor-ladder DAC architectures that
provide means of overcoming the above problems.
5.1.1 Ladder Architecture with Switched Subdivider
In high-resolution applications, the number of devices in a DAC can be
prohibitively large. It is therefore plausible to decompose the converter into

79
80 Digital-to-Analog Converter Architectures Chap. 5

a coarse section and a fine section so that the number of devices becomes
proportional to approximately 2m / 2 rather than 2m , where m is the overall
resolution. Such an architecture is shown in Figure 5.1(a). In this circuit, a
primary ladder divides the main reference voltage, generating 2 j equal voltage
segments. One of these segments is selected by the j most significant bits of
the input and subdivided by a factor of 2k using a secondary ladder such that
k + j = m. If k = j, the number of devices in this architecture is proportional
to 2m / 2 • It is also possible to utilize more than two ladders to further reduce
the number of devices at high resolutions.
Figure 5.1(b) depicts a simple implementation of this architecture using
MOS switches that are driven by l-of-n codes in both stages [1]. Depending
on the environment, these codes are generated from binary or thermometer
code inputs.
The architecture of Figure 5.1(b) suffers from several drawbacks due to
the switched subdivider. First, the finite on-resistance of the MOS switches
used in the first multiplexer introduces differential nonlinearity at the output.
Figure 5.2 illustrates this effect. Here, R u I and R u 2 represent the unit resistors
of the primary and secondary ladders, respectively, and Ron denotes the switch
on-resistance. Neglecting the current drawn by the secondary ladder, suppose
the input code is such that the subdivider is connected to nodes n - 1 and n
and the output voltage is equal to Vn [Figure 5.2(a)]. Now, if the digital input
increments by 1 LSB, the subdivider switches to nodes nand n + 1 and,
as shown in Figure 5.2(b), Vx is taken to the output. Ideally, the difference
between Vx and Vn must be equal to 1 LSB [= (Vn+1 - Vn)/2k ]. But, with the
finite on-resistance of the switches, a finite error results. It can be easily shown
that this error is approximately equal to (Vn+1 - Vn)Ron/(2Ron + 21< R u2). In
order to maintain this error much less than 1 LSB, Ron must be much less than
Ru 2 .
Another source of differential nonlinearity in this architecture is the
loading of the switched subdivider on the primary ladder. If the subdivider
is connected to nodes n - 1 and n of the primary ladder (Figure 5.2), then
Vn - Vn - ) is slightly less than Vn + I - Vn • It can be easily shown that for this
error to be much less than 1 LSB, Rul « Ru 2 .
Switched subdividers also exhibit long settling times. This occurs be-
cause when the subdivider switches from one segment of the primary ladder
to another, all the capacitance associated with the subdivider (MOS device
capacitance, wiring capacitance, etc.) must charge or discharge through the
resistance of the primary ladder, a particularly acute problem if the digital
input goes from zero to full-scale.
Sec. 5.1 Resistor-Ladder DAC Architectures 81

.
CD
>c
•
Q.
;:
"5
:&
Q
o
Ci
e
~

':'
j bits kbits
(a)

Fine
VREF 1-of-n Code
~
.J..

...L.

Coarse
1-of-n
Vout

Code

(b)
Fig. 5.1 Resistor-ladder DAC with switched subdivider. (a) Block diagram;
(b) possible implementation.
82 Digital-to-Analog Converter Architectures Chap. 5

n +1
··· RU 2

n
R U1
···
n -1

··· ···

..
(a) (b)

Fig. 5.2 Equivalent circuit of ladder DAC with switched subdivider. (a)
Subdividing Vn - Vn - I ; (b) subdividing VIl + 1 - VIl.

5.1.2 Intermeshed Ladder Architectures

Some of the drawbacks previously mentioned for ladder DACs can be
alleviated through the use of intermeshed ladder architectures [2, 3]. In these
architectures, a primary ladder divides the main reference voltage into equal
segments, each of which is subdivided by a separate, fixed secondary ladder.
Figure 5.3(a) illustrates such an arrangement [2], where all the switches are
controlled by a l-of-n code.
The intermeshed ladder has several advantages over single-ladder or
switched-ladder architectures. Compared with a single-ladder DAC having
the same resolution, this configuration can have smaller equivalent resistance
at each tap, thus allowing faster recovery. Also, since the secondary ladders
do not switch, their loading on the primary ladder is constant and uniform.
Furthermore, the DNL resulting from finite on-resistance of switches does not
exist here.
In the topology of Figure 5.3(a), the output node is loaded with the
parasitic capacitance of all the switches connected to the ladder. To reduce
Sec. 5.1 Resistor-Ladder DAC Architectures 83

VREF

• • •

• •

• • •
•
•
•
• • •

• •

• • •
-· (a)

VREF

• •
• __- - 0 + -....- 4

•
•

.-"""',...--"IMr-..-. • •

• • __- - + -....- 4

........ ~~--~

-· (b)
Fig.5.3 Intermeshed resistor-Jadder DACs with (a) one-level multiplexing
and (b) two-level multiplexing.
84 Digital-to-Analog Converter Architectures Chap. 5

this capacitance, the output nodes of the secondary ladders can be multiplexed
[3] as depicted in Figure 5.3(b). In this circuit, the switches connected to the
output node comprise a multiplexer and are controlled by the most significant
bits. Note that in contrast with Figure 5.3(a), the resistive path charging the
output node consists of two switches in series, but the overall settling time is
less because the output node capacitance is reduced substantially.
Another approach to reducing the settling time is to precharge the DAC
output node to a proper voltage [3]. For example, in Figure 5.3(b), the output
node of each secondary ladder can be precharged to the middle tap voltage of
that ladder so that the output voltage is already a coarse estimate of its final
value.

5.2 CURRENT-STEERING ARCHITECTURES

Most high-speed D/A converters are based on current-steering architectures.
Since these architectures can drive resistive loads directly, they do not require
high-speed amplifiers at the output and hence are potentially faster than other
types of DACs. While the high-speed switching of bipolar transistors makes
them the natural choice for current-steering DACs, many designs have been re-
cently reported in CMOS technology as well. Examples of high-speed design
include IO-bit resolution at I GHz [4] and 12-bit resolution at 125 MHz [5].

5.2.1 R-2R-Network Based Architectures

In order to realize binary weighting in a current-steering DAC, an R-2R
ladder can be incorporated so as to relax device scaling requirements [6, 7].
Figure 5.4 illustrates an architecture that employs an R-2R ladder in the
emitter network. Here, the area of the bipolar transistors is scaled in powers
of 2 from 2k - 1 AE for the MSB current source (Qk-l) to AE for the LSB
current source (Qo), where A E denotes the emitter area of a unit transistor.
Transistor Qa, identical with Qo, and its associated emitter resistors provide
proper "termination" at the end of the array to allow accurate binary scaling.
This point is clarified in the following analysis.
To see how binary weighting of currents is accomplished, we consider
a 3-bit version of this architecture, shown in Figure 5.5(a), where mismatch
effects are neglected. Since Qa and Qo have equal emitter area and emitter
resistors, their collector currents are equal, 1a = 10. Consequently, as depicted
in Figure 5.5(b), these transistors and their corresponding emitter resistors can
be replaced with an equivalent circuit consisting of a transistor with emitter
area 2AE (QOa) and an emitter resistor equal to R. Now, QOa and QI have
equal emitter area and emitter resistors; i.e., II = /0 + I a = 210 • Replacing
Sec. 5.2 Current-Steering Architectures 85

·1---.....----.. . .- -------.

••
VB ......~t__---_+--

R
_ - - - - ' l l f t f t r - -.....- ~ . _ _ _ • • • 0-4..-~'V\r--.....

Fig.5.4 Current-steering DAC with R-2R ladder in the emitter network.

VB _--+----+------+------1

(a)

(b) (c)
Fig. S.5 (a) Simplified circuit of a 3-bit current-steering DAC; (b) equivalent
circuit of (a); (c) equivalent circuit of (b).

these devices with an equivalent circuit yields that in Figure 5.5(c), from
which it follows that /2 = 11 + 10 + l« = 41a . Thus, 12, II, and 10 are
binary-weighted.
86 Digital-to-Analog Converter Architectures Chap. 5

In contrast with the binary weighting discussed in Section 4.3.2 and de-
picted in Figure 4.8, the architecture of Figure 5.4 does not require a wide
range of scaling for the resistors. Nonetheless, the transistors must still be
scaled, a requirement that results in both large chip area and large capaci-
tance at their collector nodes. To mitigate these problems, some of the LSB
transistors can remain unsealed, with the resulting error corrected by addi-
tional circuit techniques [8]. As an example, consider the two current sources
shown in Figure 5.6(a), where the emitter resistors of Q I and Q2 are scaled
by a factor of 2 but the transistors have equal area. If the voltage drop across
the emitter resistors is much greater than Vr, then 12 ~ 2/1 and

/2 II
VBE,2 - VBE, 1 = Vr In - - VT I n - (5.1 )
/52 lSI

~ Vr In2, (5.2)

where lSI and IS2 are the saturation currents of QI and Q2, respectively.
Thus, 11 is greater than its ideal value by approximately (Vr In 2)/ (2R).

Vb 1
AE AE
2R 2R

VEE
(a) (b)

Fig. 5.6 (a) Current sources with scaled emitter resistors but unsealed tran-
sistors; (b) error correction using a voltage source equal to Vr In 2.

Since 12 =1= 2/), (5.2) is merely an approximation, but its accuracy

can be improved by iteration. For example, from the above approximation,
/2 ~ 2I t + (Vr In 2)/ R, which can be substituted in (5.1):

2/ 1 + (Vr In 2)/ R
VBE ,2 - VBE, ) = Vr In - ------ (5.3)
II
Vr
~ VT(l + --) In 2. (5.4)
2RI)
Nonetheless, typically 2RI] » Vr, and (5.2) provides a reasonable approxi-
mation.
Sec. 5.2 Current-Steering Architectures 87

The above discussion indicates that the base-emitter voltage of Q I in

Figure 5.6(a) is VT In 2 volts less than its ideal value for proper scaling. This
error can be canceled by inserting a voltage source equal to VT In 2 between
the bias voltages applied to the bases of Ql and Q2 [Figure 5.6(b)]. This
voltage difference can be established by passing a current of (VT In 2)/ R bs
through a resistor Rbs interposed between the bases of Q I and Q2 [Figure
5.7(a)]. The current is proportional to absolute temperature (PTAT) and can
be generated by any of the various band gap reference circuits [9, 10]. As
an example, consider the circuit in Figure 5.7, where the emitter area of Q2
is twice that of Q I; i.e., I S2 = 21SI. The feedback loop established by the
difference amplifier A ensures that ICI =
IC2. Consequently,

VBE,2 - VBE,1 = VT In -IC2 ICI

- VT I n - (5.5)
1S2 lSI
= -VT In2. (5.6)

(a)

--------------11
RC

VEE ~-..e---- .......- -_.....

(b)
Fig.5.7 (a) Implementation of a floating voltage of Rbs1bs = Vr In 2; (b)
generation of PTAT current lbs = (V r In 2)/ Rbs.
88 Digital-to-Analog Converter Architectures Chap. 5

This voltage difference is sustained across R2 (= Rbs ) , giving IC2 =

(VT In 2)/ R bs • The output current lcs is generated by a current source con-
sisting of Q3 and R3' which are replicas of Q2 and R2, respectively. Note
that the base current of QI in Figure 5.7(a) introduces an additional voltage
drop across R bs , degrading the accuracy of correction slightly.
Another R-2R-network-based architecture is shown in Figure 5.8, where
device scaling does not exceed a factor of 2 to I, thereby reducing the
circuit area substantially [7]. This circuit consists of identical transistors
Qo, ... , Qk-l with equal emitter resistors and an R-2R network that per-
forms the binary division of the collector currents.

ro------.-----.....---I·

r--+-----.--+------+ --tll

Fig.5.8 Current-steering DAC with R-2R ladder in the collector network.

To see how this division is accomplished, we consider a 3-bit example

having the equivalent circuit shown in Figure 5.9(a) (with all the currents
switched to the output). If the circuit inside the dashed box is replaced with its
Norton equivalent, the circuit shown in Figure 5.9(b) is obtained. Combining
the parallel devices in this circuit and substituting the result with another
Norton equivalent, we arrive at Figure 5.9(c). Thus, the output current is a
binary-weighted sum of 11, 12, and 13 . This derivation also shows that if an
external resistor is tied from the output node to ground, it merely affects the
full-scale output voltage swing and has no influence on the accuracy of the
binary weighting.
The architectures described in this section can be employed to achieve
high resolutions. The small number of resistors-twice the number of bits-
Sec. 5.2 Current-Steering Architectures 89

. . - - - - -......+---+--~I.

(a)

..-----.----.....----11· I'
2R 2R
'out 'out - . . - -----e

(b) (c)

Fig.5.9 Equivalent circuits of a 3-bit current-steering DAC with an R-2R

ladder in the collector network.

used in these circuits makes it possible to laser-trim these resistors, thus cor-
recting mismatch errors. However, unlike segmented arrays, these archi-
tectures do not exploit error averaging due to a large number of nominally
identical devices and hence require tighter matching of the components.
Another drawback of these architectures is their potentially large glitch
area. To study this effect, consider the simplified circuit of a 4-bit DAC
shown in Figure 5.10. First, suppose the digital binary input is equal to 1000
and hence only the MSB current source is switched to the output. Now, if
the digital input goes to 0111, the MSB current source turns off while the
other three turn on and the output changes by I RL. In practice, however,
the digital signals driving the switches suffer from finite risetime and falltime
as well as timing skews. For example, during the transition from 1000 to
0111, all four switches may be partially off for a short time. Thus, the output
current momentarily reaches a value different from either 8/ or 7/, causing
a glitch.
Timing skews can be suppressed through the use of on-chip latches to
sample and align the incoming digital signals and apply only the sampled val-
ues to the current switches. Finite transition times and clock skews, however,
still result in output glitches.
90 Digital-to-Analog Converter Architectures Chap. 5

- -
----oVout .....- --oVout

Vout

- 8/RL ---- -,
-7/R L -_•••••••••• -

Fig. 5.10 Glitch impulse in a current-steering DAC.

5.2.2 Segmented Architectures

As mentioned in the previous section, architectures based on simple
binary weighting suffer from two important drawbacks. First, they require
tight device matching to achieve monotonicity (DNL < I LSB). Second, they
exhibit large glitch impulses. Segmented architectures are commonly used to
alleviate these problems.
Figure 5.11 shows an m-bit segmented current-steering architecture
which is based on the segmented array described in Section 4.3.2. In this
architecture, N = 2m - 1 nominally identical current sources are controlled
by a thermometer code. In a stand-alone DAC, a binary-thermometer encoder
precedes the array.
In Figure 5.11, as the digital input increases, the DAC switches more
current sources to the output without turning off any of the current sources
that are already switched to the output. Thus, the input/output characteristic
is monotonic and the glitch impulse is small. Note that while monotonicity
typically results in a small DNL, the INL may be quite large if the devices do
not match accurately.
The circuit of Figure 5.11 is called a "fully segmented" architecture
because it employs 2m - 1 equal current sources for m bits. For k ~ 8, the
Sec. 5.2 Current-Steering Architectures 91

-.
....------.__---4..._-----,..-....g Vout

...
Binary-Thermometer Decoder

=r::::::r=
Binary Input
Fig. S.11 Segmented current-steering DAC.

number of devices in the array becomes quite large, leading to a high ca-
pacitance at the output node. Furthermore, the binary-thermometer decoding
logic occupies a large area and requires substantial power dissipation. Even
though fully segmented architectures have been used for resolutions as high
as 10 bits [11] (to minimize the glitch impulse), it is often more efficient to
partition the DAC into a segmented coarse sub-DAC and a binary-weighted
fine sub-DAC whose output currents are simply added. In other words, for
a resolution of m = k + n, the k most significant bits are converted to ther-
mometer code and drive a 2k -unit segmented array, while the remaining n bits
are directly applied to an n-bit binary array. Called the partially segmented
architecture, this topology is illustrated for k = 6 and n = 4 in Figure 5.12.
Here, an R-2R ladder performs the binary weighting in the same manner as
described in Section 5.2.1.
The choice of k and n in general depends on the matching of the current
sources and the tolerable glitch area. Typical values for k range from 4 to 7.
In the architecture of Figure 5.12, the complexity of the binary-thermo-
meter code conversion, the large number of current sources, and the issues
related to routing signals place stringent requirements on floor planning and
layout. An efficient approach is to arrange the current sources and part of
the decoding in a matrix, as shown in Figure 5.13(a) [12]. Here, binary-ther-
mometer conversion is performed in two steps: row and column decoding
followed by local decoding within each cell of the matrix. In the first step, the
92 Digital-to-Analog Converter Architectures Chap. 5

-.
11 = ... =163 =10 ,...--....- -.....- -.....---4...-.--11·

Segmented Array Binary Array

Fig. 5.12 A 10-bit partially segmented current-steering DAC.

input binary word (D6 . . . Di) is partitioned into two subwords (D6DSD4 and
D3D2Dl) each of which is converted to a thermometer code. The resulting
codes are distributed across the matrix as depicted in Figure 5.13(a). In the
second step, the row and column thermometer codes are combined locally
to determine the required status of each current source. To implement local
decoding, we note that for any digital input, each row falls in one of three
categories [12]: (1) rows in which all current cells are on, (2) rows in which
all current cells are off, and (3) a certain row in which so-me of the current cells
are on. To determine the status of each cell, the row and column thermometer
codes are locally combined around each current source. Figure 5.13(b) shows
an example where two adjacent bits of the row thermometer code and one bit
of the column thermometer code are used to generate the control signal for
the current source.
While providing a simple, modular layout, the matrix configuration must
deal with two difficulties. First, the analog output line inevitably experiences
a great deal of coupling from the digital signals that flow in both horizontal
and vertical directions within the matrix. In bipolar implementations, this
effect is minimized through the use of relatively small (~ 0.5 V) differential
signals for column and row thermometer codes. In CMOS circuits, on the
other hand, these signals are typically rail-to-rail and single-ended, resulting
in substantial coupling to the analog output.
The second issue stems from the wiring capacitance of the analog output
line. This line must reach all the cells, and its total length is given primarily
by the size of each cell. Since the cells must be large enough to accommodate
local decoding (and a current source), the total length of the analog output
line and hence the output settling are quite long.
Sec. 5.2 Current-Steering Architectures 93

..... Column
Thermometer Code

.........................
Ds
~~~

1--+--+--+--1-......-+--+--1
.......·:·
~ Local
: Decoder
•••• :
!
.....
)
t

·.........................

(a)

(b)
Fig.5.13 (a) Matrix floorplan for segmented DACs, (b) local decoding.

The idea ofsegmented DACs was originally proposed by Shoeffand used

in a 12-bit converter to achieve monotonicity without trimming [13]. Shown
in Figure 5.14 is a simplified 5-bit version of this architecture consisting of a
segmented array /4-/7 and a binary-weighted array 10-/3. The basic principle
of this architecture is to switch each of the equal current sources /4-/7 to the
output in an additive fashion and use their subdivisions to provide finer steps
and hence higher resolution.
To illustrate this principle, we examine the output current as the digital
(binary) input Din = Ds · · · DI varies from zero to full-scale. For 0 :s Din ~
23 - 1, the current source 14 is switched to node P and subdivided to generate
13-/0. Thus, /3-/1 are switched to the output node according to the value of
Din, while other currents are switched to ground. Note that for Din = 2 3 - I,
loul = /4 - 10 .
When the digital input is equal to 23 , /4 is switched to the output node,
/5 to node P, and the remaining currents to ground. Thus, the difference
between the output currents corresponding to Din = 23 - I and Din = 2 3 is
equal to 10, indicating that this transition is always monotonic because 10 has
a finite positive value.
For 23 ~ Din ~ 24 - 1, /5 is subdivided to generate /3-10, and the output
current is equal to the sum of a proper combination of these currents and 14.
94 Digital-to-Analog Converter Architectures Chap. 5

lout -~----.------
.----+-- - - + - ----4I~-ofI'

.
r ::
j , ,.
/4 .
0 0 6

Segment Decoder ~.OD4

D
3 °2 D1

-oDs
Fig. 5.14 Partially segmented architecture proposed by Shoeff.

For Din = 24 , /s is switched directly to the output; i.e., lout = 14 + Is. Again,
the difference between output currents corresponding to Din = 24 - 1 and
Din = 2 is equal to 10, thereby preserving monotonicity. The same switching
4

algorithm is used for larger digital inputs.

The integral linearity ofthis architecture depends primarily on the match-
ing of /4-17. Laser-trimming or self-calibration techniques such as those de-
scribed in Section 8.3.1 can be employed to achieve a small INL.
Despite the above features, this circuit faces an important limitation
when implemented in today's technologies. The stacking of devices in current
sources 13-/0 on top of one of /4-/7 severely limits the output voltage swing
if the supply voltage is only 5 V.
The segment decoder utilized in this architecture is more than a binary-
to-thermometer converter because it must also determine which one of /4-/7
is switched to node P. A compact implementation is possible if multiple logic
levels are used [13].

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[1] H. U.PostandK.Schoppe, "A 14BitMonolithicNMOSD/AConverter,'
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[2] A. G. Dingwall and V. Zazzu, "An 8-MHz CMOS Subranging 8-Bit NO

Converter," IEEE J. Solid-State Circuits, vol. SC-20, pp. 1138-1143,
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[3] M. I. M. Pelgrom, "A IO-Bit 50-MHz CMOS D/A Converter with 75-Q
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[4] P. Vorenkampetal., "A IOs/s lOb DigitaI-to-Analog Converter," ISSCC
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[5] W. T. Sagun et aI., "A 125-MHz 12-Bit Digital-to-Analog Converter
System," Hewlett-Packard J., pp. 78-85, April 1988.
[6] G. Kelson, H. H. Stellrecht, and D. S. Perloff, "A Monolithic IO-b
Digital-to-Analog Converter Using Ion Implantation," IEEE J. Solid-
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[7] D. J. Dooley, "A Complete Monolithic 10-b D/A Converter," IEEE J.
Solid-State Circuits, vol. SC-8, pp. 404-408, Dec. 1973.
[8] P. Holloway and M. Norton, "A High Yield, Second Generation IO-Bit
Monolithic DAC," ISSCC Dig. Tech. Pap., pp. 106-107, Feb. 1976.
[9] A. P. Brokaw, "A Simple Three-Terminal IC Bandgap Reference," IEEE
J. Solid-State Circuits, vol. SC-9, pp. 388-393, Dec. 1974.
[10] R. J. Widlar, "New Developments in IC Voltage Regulators," IEEE J.
Solid-State Circuits, vol. SC-6, pp. 2-7, Feb. 1971.
[II] H. Takakura and M. Yokoyama, "A 10 Bit 80 MHz Glitchless CMOS
D/A Converter," Proc. CICC, pp. 26.5.1-26.5.3, May 1991.
[12] T. Mild, "An 80-MHz 8-Bit CMOS D/A Converter," IEEE J. Solid-State
Circuits, vol. SC-21, pp. 983-988, Dec. 1986.
[13] J. A. Shoeff, "An Inherently Monotonic 12 Bit DAC," IEEE J. Solid-State
Circuits, vol. SC-14, pp. 904-911, Dec. 1979.