IT 208 - Midterm - Group B

International Burch University

28/11/2022

Name:

Student ID:

Question Points Score

1 30
2 10
3 15
4 20
5 25
Total 100

Instructions:

1. You have two (2) hours to complete the exam.

2. Write your answers in the space provided. In case there is no space pro-
vided, you may write on the backs of pages. Please indicate clearly on the
front of the page that you have written on the back of the page.
3. You may only use a pen. You may not use any other resources, including
calculator or phone.
4. Read each question carefully and provide clear answers. Answer each
question by using analysis and show all work and your thought
process whenever possible. This will make it easier for us to give you
partial credit.
5. Upon completion, please turn in the exam sheets to the proctor in charge.

Signature:

1
Question 1: General Understanding of Topics
[7.5 pts] Explain the concept of memory hierarchy in details and provide illustration.

[7.5 pts] List the most common addressing modes and explain the technique for calculating
an effective address for each.

[10 pts] Why do we need cache memory? Explain temporal and spatial locality of reference
in cache memory. What needs to be stored inside a cache for block identification? How does
a cache know whether there is a cache hit or miss?

2
[5 pts] Answer briefly the following:

(a) What is the name of the program that translates another program written in higher
programming language like C or Java, and what does it produce?
(b) Explain the difference between static RAM and dynamic RAM.
(c) How the CPU executes instructions?
(d) What is a register?
(e) What are the basic components of a computer?

3
Question 2: Number Systems
[10 pts] Find the binary equivalent of the hexadecimal number you will get in marked fields
of the Fig.1. Fill in vertically:

1. Hexadecimal equivalent of binary number 1010110010100001.

2. Number 793 in BCD notation.
3. Hexadecimal equivalent of octal number 7432270.
4. Hexadecimal equivalent of decimal number 63.
5. Octal equivalent of binary number 101111.01110111.
6. Hexadecimal equivalent of octal number 136.14.

Figure 1: Number Systems Conversion Graph

4
Question 3: Digital Logic
[15 pts] The 1-bit adder is a combinational logic block that has three inputs and two outputs.
The three inputs are: the first operand bit a, the second operand bit b, and the carry_in.
The two outputs are: carry_out and sum.
Your task is to design the combinational logic block that generates the sum output.

(a) Complete the truth table for the sum output below.

a b carry_in sum
0 0 0
0 0 1
0 1 0
1 1 1
1 0 0
1 0 1
1 1 1

(b) Write an expression in Boolean algebra for the sum output of an 1-bit adder.

(c) Use AND, OR, and NOT logic circuits to draw a combinational logic block that
produces the sum output of an 1-bit adder. Label clearly inputs and the output.

5
Question 4: Caches
[15 pts] Consider an example of a two-level cache memory - main memory hierarchy, in which
the cache memory consists of 256 blocks (lines) of 16 words each. Total cache size is 8K
words. Main memory is addressable by a 16-bit address.

(a) Find the total size of main memory based on the information provided, and find the
number of 16-word blocks in main memory.
(b) Use this configuration example to explain: (1) the direct mapping, (2) associative map-
ping, and (3) N-way set associative mapping technique (consider N = 4).

[10 pts] A computer system has a 128 byte cache. It uses four-way set-associative mapping
with 8 bytes in each block. The physical address size is 32 bits, and the smallest addressable
unit is 1 byte. To what block frames of the cache can the address 000010AF16 be assigned?

6
Question 5: Instructions
[5 pts] Registers R1 and R2 contain data values 300 and 500 respectively (in decimal) and
the word length of the processor is 4 bytes. What is the effective address of the memory
operand for the instruction

LOAD R5, 5(R1,R2)?

[2.5 pts] The two registers are initialized as R1 = 12, R2 = 10. The instruction SUB R1,R2
is in memory location 1010H. The size of an instruction is 2 bytes. After the instruction
execution, what will be the values in PC and R1?
[5 pts] Consider a 32-bit machine where an instruction ADD R1,LOCA is stored at location
102BH. LOCA is a memory location whose value is 200AH. How many memory accesses are
required to execute this instruction assuming the instruction is stored in memory? In addi-
tion, what will be the content of PC after the instruction is fetched? Individual instruction
is 32-bit.

[5 pts] There are 30 registers, and total 44 instructions available in a general purpose com-
puter. The computer allows only 2-address instructions, where one operand can be a register
and another can be a memory location. The memory is byte addressable with 32KB in size.
What is the minimum number of bits to encode the instruction?

[5 pts] An instruction ADD R1, A is stored at memory location 2005H. R1 is processor

register, and A is a memory location with the address 200BH. Each instruction is 32-bit
long. What will be the values of PC, IR, and MAR during execution of the instruction?
Explain the purpose of PC, IR, and MAR registers.