SD2085

Low Power HARTTM Modem

Feature
⚫ Single chip, half duplex 1200 bps FSK modem The SD2085 uses phase continuous
⚫ Meets HART physical layer requirements Frequency Shift Keying (FSK) at 1200 bps,
⚫ Bell 202 shift frequencies of 1200Hz and and operates in half duplex mode per HART
2200Hz protocol. The maximum supply current
⚫ Buffered HART output for drive capability consumption in transmit mode is 85μA while
⚫ Digital signal processing provides reliable using 3.6864MHz external Clock source input
input signal detection and 3.6V power supply.
⚫ UART interface
The input HART signal is sampled by an
⚫ 2.7V to 3.6V power supply
analog to digital converter (ADC), followed
⚫ 85μA maximum supply current in transmit mode
by a digital filter and demodulator. This
⚫ -55°C to +125°C operation range
architecture ensures reliable signal detection
⚫ 20pins 5mm х 5mm x 0.75mm TQFN20
in noisy environments. A digital to analog
package
converter (DAC) is used to output 1200Hz
⚫ RoHS compliant
and 2200Hz phase continuous trapezoid
waveforms.
General Description
Required board space is very small
The SD2085 is a CMOS single chip
because of the 5mm x 5mm QFN package
modem IC used in Highway Addressable
and very few external components needed,
Remote Transducer (HART) field instruments
making it ideal for line-powered applications
and masters. This IC integrates all necessary
in both master and slave configurations.
filtering, signal detection, modulating,
demodulating, and HART signal wave shaping
functions. Thus it requires few external passive
Ordering Information
components to satisfy the HART physical layer Package Part Number
requirements. QFN20 5mm х 5mm SD2085

Pin Diagram and Descriptions

19 D_OUT
18 DVSS

16 DVSS
20 D_IN

17 NC

DVDD 1 15 AVSS
DVDD 2 SDIC 14 FSK_IN
DVSS 3 XX 13 REF
RESETb 4 2085 12 FSK_OUT
OCD 5 11 AVDD
XATL2 8
RTSb 6
XTAL1 7

DVSS 9
XCEN 10

TOP VIEW

Figure 1. Pin diagram

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 SD2085

Table 1. Pin Descriptions

Pin No. Pin Name Attribute Description
1,2 DVDD Digital power Digital supply voltage, same voltage level with AVDD.
3, 9,
DVSS Digital gnd Digital ground, same voltage level with AVSS.
16, 18
4 RESETb Digital input IC reset, active low.
5 OCD Digital output Carrier detect. A high state on CD indicates a valid carrier is detected.
Request to send. Low state enables the modulator and disables the demodulator, the IC is in
6 RTSb Digital input transmit mode. High state enables the demodulator and disables the modulator, the IC is in
receive mode.
7 XTAL1 Analog input Connection for external 3.6864MHz crystal or external clock source input.
8 XTAL2 Analog output Connection for external 3.6864MHz crystal. Floating when using an external clock source.
10 XCEN Digital input Crystal oscillator circuit (XOSC) enable, active low.
11 AVDD Analog power Analog supply voltage.
12 FSK_OUT Analog output HART FSK signal output. Connect to 4-20mA loop interface circuit.
13 REF Analog output Internal 1.5V reference voltage output. Connect a 1μF capacitor to AVSS.
14 FSK_IN Analog input FSK modulated HART signal received from 4-20mA loop interface circuit.
15 AVSS Analog gnd Analog ground.
17 NC - No Connect pin. Can be tied to DVDD or DVSS.
19 D_OUT Digital output Demodulated HART data, output to external UART.
20 D_IN Analog input Data to be transmitted. After modulation, data goes out at FSK_OUT.
EPAD AVSS Analog gnd Analog ground. For typical application, connect to pin 15.

Circuit Description
DVDD XTAL1 XTAL2 XCEN AVDD

SD2085 LDO OSC

Voltage
REF
Reference
NC

RTSb Wave
Modulator DAC Buffer
Control Logic

FSK_OUT
D_IN Shaping

OCD OCD-Detector Digital

ADC FSK_IN
D_OUT Demodulator Filter

RESETb DGND AGND

Figure 2. Function block diagram

Figure 2 is the function block diagram of duplex single chip modem that compiles with
SD2085. It is a low power HART FSK half HART physical layer requirements. SD2085

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 SD2085
includes the modulator, wave shaper, DAC, 2200Hz HART compliant trapezoidal signal
buffered HART output for transmitting data, through the wave shaping block. The signals are
and includes the ADC, digital filter, then buffered and output to FSK_OUT. The
demodulator, and carrier detect circuitry for FSK_OUT DC level is 0.75V with 0.5V~1.0V
receiving data. Other functional blocks include voltage swing.
reference voltage, crystal oscillator, and LDO.
The signal going into D_IN is a standard
As a result of such extensive integration,
UART frame with 1 start bit, 8 data bits, 1 parity
minimal external components are needed.
bit, and 1 stop bit as shown in Figure 4.
SD2085 is suitable for use in both HART field
instrument and master configurations. FSK_OUT can drive capacitive load directly.
The load should be 4.7nF to 68nF. SD2085
The SD2085 either transmits or receives
consumes more current as the capacitive load
1200Hz and 2200Hz FSK signals as shown in
increases. The supply current specifications
Figure 3. 1200Hz represents digital “1”,
shown in Table 3 are based on a 4.7nF capacitive
whereas 2200Hz represents digital “0”. The bit
load at FSK_OUT.
rate is 1200bits/second.
If driving a load with resistive element, it
Both crystal oscillator and external clock
should be coupled with a 2.2µF serial capacitor
source are supported.
as shown in Figure 5. The RLOAD range is
digital“1” digital“0”
typically 200Ω to 600Ω. A 22nF capacitor should
= 1200Hz = 2200Hz be connected between HART_OUT and ground.
V

SD2085
2.2μF
FSK_OUT
Figure 3. HART FSK signal
22nF RLOAD

FSK Modulator
When RTSb is set to low, the SD2085 Figure 5. FSK_OUT with resistive load
operates in transmit mode. The modulator
converts the NRZ digital signal at D_IN into a
sequence of phase continuous 1200Hz and

1200bps/833µs
START

D_IN STOP

8-BIT DATA + PARITY

FSK_OUT

Figure 4. SD2085 Modulator waveform

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 SD2085
FSK Demodulator
When RTSb is set to high, the SD2085 the most demanding industrial environments.
operates in receive mode. HART signal goes into Using 1% accuracy resistor and 10% accuracy
FSK_IN through an external anti-aliasing capacitor, effect of the filter on the carrier
band-pass filter. A high on OCD indicates a valid detection is still negligible.
carrier is detected. The demodulator accepts the
FSK signal at FSK_IN and restores to digital FSK_OUT

Network
HART
REF
signal at D_OUT, which is then output to external SD2085 1µF 1.2M
200k HART
UART. FSK_IN
300pF
signal
1.2M 180pF

The external band-pass filter is shown in

Figure 6. A 200kΩ resistor at the filter input
Figure 6. SD2085 external filter connection
limits current to a sufficiently low level resulting
in very high transient voltage protection
The HART bit stream is a standard UART
capability. Therefore, no additional protection
frame with a start bit, 8 data bits, 1 parity, and a
circuitry at the input terminal is needed even in
stop bit as shown in Figure 7.

HART_ IN

8 - BIT DATA + PARITY

D_ OUT
1200bps/ 833µs
START STOP

Figure 7. SD2085 Demodulator waveform

Clock Configuration 3.6864MHz clock source is connected to XTAL1.

The SD2085 provides two clocking options: XTAL2 must be floating. XCEN is set to high.
external crystal and CMOS clock input.

The typical connection for the external XTAL1

3.6864MHz crystal is shown in Figure 8. XCEN 3.6864MHz SD2085

is set to low. The crystal and capacitor should be XTAL2
as close to SD2085 as possible. DVDD XCEN

C1 Figure9. CMOS clock connection

XTAL1
8pF
3.6864
SD2085 Power-Down Mode
MHz
8pF
When RESETb is at low state, the IC is reset
XTAL2
C2 and enters into power down mode. Receive,
XCEN
transmit, and oscillator circuits are all turned off,
and the device consumes a maximum of 5µA.
Figure 8. Crystal oscillator connection
A high state at RESETb returns SD2085 to
The typical connection of CMOS clock power-on state. If not using the reset function,
input is shown in Figure 9 where an external one can tie this pin permanently to DVDD.

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 SD2085

Using the SD2085

Typical Application Diagram

Figure 10 is a typical smart transducer with FSK_IN pin through the external band-pass filter.
HART capability using SD2085 and SD2421 SD2057 demodulates the signal and passes the
(4-20mA loop-powered DAC). This digital data to the MCU through the D_OUT pin.
implementation greatly simplifies system design
To send HART signal out to the current loop,
and enhances reliability while reducing overall
the MCU sends digital data to SD2085’s D_IN
PCB size. Decouple the power supplies with 1μF
pin. SD2085 performs modulation and wave
and 0.1μF capacitors in parallel to ground, and
shaping, and send the HART signal out through
decouple the REF pin with a 1μF capacitor to
its FSK_OUT pin and the Cc capacitor to
ground.
SD2421’s C3 pin. SD2421 then passes the signal
HART signal comes in from the current to the current loop.
loop’s LOOP+ terminal, and goes into SD2085’s

VCC
FSK_OUT AVDD 3.3V

SD2085 1µF 0.1µF

VCC MODE HART REF
RESETb
XCEN
modem 1µF
1.2M
300pF 200k
DVDD
FSK_IN
D_OUT
XTAL2

XTAL1

1µF 0.1µF
RTSb
D_IN

OCD

DVSS 180pF
AVSS 1.2M

depletion
LOOP+
VCC NFET

10nF 2.2µF
Physical VDD 4-20mA
Quantity 4.7µF 100k
1.25V LV VCC BOOST Loop
transducer VREF VREF1 Voltage
VDD COMP source
VREF2 10nF

16 bit VREF IN SD2421

DRIVE
4.7µF
ADC current 1k
MCU LATCH DAC 1nF
CLOCK
COM
DATA
GND GND C1 C2 C3 LOOPRTN
Temperature 10nF 0.47µF LOOP-
sensor
0.15µF

CC 6.8nF

Figure 10. Typical 4-20mA smart transducer with HART digital communication capability

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 SD2085

Electrical Specifications
Table 2. Absolute Maximum Ratings
Symbol Parameter Minimum Maximum Unit
TA Operating temperature -55 +125 ℃
TS Storage temperature -65 +150 ℃
AVDD to AVSS Analog supply voltage -0.3 +7.0 V
DVDD to DVSS Digital supply voltage -0.3 +7.0 V
AVSS to DVSS Analog to digital ground -0.3 +0.3 V
Analog input to AVSS Analog input/output voltage -0.3 AVDD+0.3 or +7 (whichever is less) V
Digital input to DVSS Digital input/output voltage -0.3 DVDD+0.3 or +7 (whichever is less) V
θJA SOP16 thermo resistance 46 °C /W
TL Reflow temperature profile Per IPC/JEDECJ-STD-020C ℃
Human body model 4000 V
ESD
Machine model 400 V
Remarks:
1. CMOS device can easily be damaged by electrostatics. It must be stored in conductive foam, and with care taken to not exceed
the operating voltage range.
2. Turn off power before inserting or removing the device.

Table 3. Electrical Specifications (AVDD/DVDD = +2.7~+3.6V, TA = -55~+125℃, AVSS/DVSS = 0V, external crystal,
8pF at XTAL1/XTAL2, FSK_OUT with 4.7nF load, unless otherwise noted )
Symbol Parameter Minimum Typical Maximum Unit Conditions/Remarks
AVDD
Supply voltage 2.7 3.3 3.6 V
DVDD
97 125 μA External clock, -55℃ to +85℃
ADD+DVDD 130 μA External clock, -55℃ to +125℃
Demodulator mode 125 500 External crystal, -55℃ to +85℃
550 External crystal, -55℃ to +125℃
IDD1
67 80 μA External clock, -55℃ to +85℃
AVDD+DVDD 85 μA External clock, -55℃ to +125℃
Modulator mode 95 450 External crystal, -55℃ to +85℃
500 External crystal, -55℃ to +125℃
IDD0 Power-down mode 2.5 5 µA
Initial accuracy 1.48 1.5 1.52 V
VREF Load regulation 1.5 ppm/μA Tested with 500μA load
Line regulation 60 μV/V
OCD assert Carrier amplitude 90 105 115 mVp-p
FSK_IN Input voltage range 0 1.5 V
Output amplitude 500 mVp-p
“1” frequency 1200 Hz
“0” frequency 2200 Hz
FSK_OUT
Phase error 0 °
Maximum resistive
160 Ω RLOAD shown in Figure5
load
External clock Frequency accuracy 3.6496 3.6864 3.7232 MHz

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 SD2085
Symbol Parameter Minimum Typical Maximum Unit Conditions/Remarks
Digital I/O parameter
VIH Input high voltage 0.7*DVDD V
VIL Input low voltage 0.3*DVDD V
IIH Input high current ±0.1 μA
IIL Input low current ±0.1 μA
Time from RTSb falling edge to
1
t1 Carrier start time 0.3 Bit time carrier reaching its first peak.
Refer to Figure 11.
Time from RTSb rising edge to
1 carrier amplitude dropping below
t2 Carrier stop time 1 Bit time
the minimum receive amplitude.
Refer to Figure 12.
Time from RTSb rising edge to
1
t3 Carrier decay time 1 Bit time carrier amplitude dropping to ac
zero. Refer to Figure 12.
1 Time from carrier on to OCD
t4 Carrier detect on 6 Bit time
rising edge. Refer to Figure 13.
1 Time from carrier off to OCD
t5 Carrier detect off 6 Bit time
falling edge. Refer to Figure 14.
Note: Bit time is the length of time to transfer one bit of data, 1 Bit time = 1/1200Hz = 833.333µs.

Figure 11. Carrier start time Figure 12. Carrier stop/decay time

Figure 13. Carrier detect on timing Figure 14. Carrier detect off timing

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 SD2085

Packaging Information

D2
D
Nd

L
1

h
1
2 h
2

Ne
E2
E

e b
EXPOSED THERMAL
TOP VIEW PAD ZONE

BOTTOM VIEW
A

c
A1

Dimension：mm

Symbol Min. Nom. Max.

A 0.70 0.75 0.80
A1 — 0.02 0.05
b 0.25 0.30 0.35
c 0.18 0.20 0.25
D 4.90 5.00 5.10
D2 3.05 3.15 3.25
E 4.90 5.00 5.10
E2 3.05 3.15 3.25
e 0.65BSC
Ne 2.60BSC
Nd 2.60BSC
L 0.45 0.55 0.65
h 0.30 0.35 0.40
Figure 15. QFN20 mechanical specification

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