ANANTHA LAKSHMI

INSTITUTE OF TECHNOLOGY & SCIENCES

(Approved by AICTE,New Delhi &Affiliated to JNTU ,Anantapur)

Project Associates: Roll No:

M.Trilok Chandra 162G1A04F3
D.A.Nandini 162G1A04D2
K.Nandini 162G1A04D2
N.Mahendra Babu 172G5A0411
B.Ashok Kumar 172G5A0402

Under the guidance of

K.Naga Latha M. T ech
 PROJECT TITLE
A Further Optimized Mix Column Architecture
Design for the Advanced Encryption Standard
 ABSTRACT
With the evolution of The Internet, there has been a huge spurt in online transactions and
also an increase in sharing of private, confidential and sensitive information over the web.
This in turn has increased the requirement of highly secure and swift methodologies to
protect such data using modern cryptographic techniques such as the Advanced Encryption
Standard (AES). In order to achieve the same, this paper discusses significant and novel
modifications to the existing hardware architecture of the mix column step of the AES
algorithm. By adopting these techniques speed and Area optimizations are achieved as
compared to previous algorithms.
 PROBLEM DEFINITION

In conventional AES Area and Delay are more so to reduce Area

and Delay we are proposing modified form of AES.
 PROJECT OBJECTIVE
The main objective of this project is
to design AES with optimized area
and delay encryption and decryption
standards.
 EXISTING APPROACH
The Advanced Encryption Standard is a symmetric-key
algorithm for the encryption of digital data. It can encrypt data
of different sizes like 128 bit, 192 bit and 256 bit by using
cipher key of length 128 bit. It has been highly influential and
effective technique of modern cryptography.
 DRAWBACKS
The main drawback of AES is it uses more adders and shifters which
requires more area and delay.
 PROPOSED APPROACH
 Optimized Advanced Encryption Standard is a cryptographic
algorithm used to protect electronic data.
 It's a symmetric block cipher that can encrypt information.
 In this Optimized AES we use new technique called Galious Field
multiplication by which area and delay are reduced compared to
conventional AES.
 Optimized AES algorithm used different keys 128/192/256 bits in order to
encrypt and decrypt data in blocks of 128 bits.
 DESCRIPTION
 Amongst the various cryptographic techniques which exist, the most popular
methods include the Advanced Encryption Standard (AES) .
 The Architecture and working of proposed AES is almost same as that of
conventional AES. The only change made in proposed AES is Galious field
multiplication in mix column block.
 By using galious field multiplication area and delay Area and Delay are
reduced.
BLOCK DIAGRAM
 RESULTS

Conventional AES Encryption Conventional AES Decryption

Outputs of Conventional AES Encryption

Area of Conventional AES Delay of Conventional AES

Outputs of Conventional AES Decryption

Area of Conventional AES Delay of Conventional AES

Outputs of Proposed AES Encryption

Delay of AES Encryption

Area of AES Encryption
Outputs of Proposed AES Decryption

Delay of proposed AES

Area of proposed AES
 COMPARISION RESULTS

Existing AES Proposed AES

Encryption LUT’s 11962 out of 15032 11965 out of 63400

(79% used) (18% used)

Encryption Delay 49.358 ns 30.820 ns

Decryption LUT’s 11962 out of 15032 11965 out of 63400

(79% used) (18% used)

Decryption Delay 63.668 ns 36.365 ns

 APPLICATIONS
 E Mail Communication

 Electronic Financial Transactions

 ATM Machines

 Social Media
 CONCLUSION
There will be a significant improvisation in speed.

Time consumption and Area are effectively reduced.

 REFERENCES
[1] Menezes, A. and Vanstone, S. ―Handbook of Applied Cryptography‖, CRC
Press, Inc. 1996.
[2] National Bureau of Standards, NBS FIPS PUB 46, ―Data Encryption
Standard‖, U.S. Department of Commerce, January 1977
[3] Daemon, J., and Rijmen, V. ―Rijndael: The Advanced Encryption
Standard.‖, Dr. Dobb’s Journal, 3, March 2001, 137-139.
[4] B. Smith, ―An approach to graphs of linear forms (Unpublished work
style),‖ unpublished.
[5] Daemon, J., and Rijmen, V. ―The Design of Rijndael: The Wide Trail
Strategy Explained.‖ New York, Springer – Verlag, 2000.
[6] I. M. Verbauwhede, P.R. Schaumont, and, H. Kuo, "Deign and
Performance Testing of a 2.29 Gb/s Rijndael Processor," IEEE J. of Solid State-
Circuit, Vol.38, No. 3, March 2003, pp. 569 – 572.
[7] K. Gaj and P. Chodowiec, Comparison of the hardware performance of
the AES candidates using reconfigurable hardware, inThe Third AES Candidates
Conference, printed by the National Institute of Standards and Technology.
[8] J. Wang, ―Fundamentals of erbium-doped fiber amplifiers arrays
(Periodical style—Submitted for publication),‖ IEEE J. Quantum Electron.,
submitted for publication.
[9] A. J. Elbirt, W. Yip, B. Chetwynd, C. Paar, "An FPGA implementation and
performance evaluation of the AES block cipher candidate algorithm finalists,"
Proc. 3rd Advanced Encryption Standard (AES) Candidate Conference.
THANK YOU
Any Queries ?