518723, 6:40 PM. Home (index.html) Physical Design PD Verification (pd_verification.html) PD Analysis PD Essentials Discontinuity 08088 @.S Videos (videos html) § STA Numericals (sta_numericals.html) STA Numericals Extras (Extras.htm!) Ref more solved problems Problem 1: In the following circuit Each flip flop has: Setup time of 60ps. Hold time of 20ps, Clock-to-Q maximum delay of 70ps Clock-to-Q minimum delay of 50ps Each XOR gate has: Propagation delay of 100ps Contamination delay of 55ps hitps:vsi-backend-adventure.comsta_numercals html VLSI BACK-END ADVENTURE (INDEX.HTML) ‘STA Numerals | VLSI Back-End Adventure to setup and hold (digital_electronics.html#section1) page to view STA basics and some CLK wr51823, 640 PM a. If there is no clock skew, what is the may [STA Numerals | VLSI Back-End Adventure \um operating frequency of this circuit? , How much clock skew can the circuit tolerate before it might experience a hold time violation? ¢. Redesign the circuit so that it can be operated at 3GHz frequency. How much clock skew can your circuit tolerate before it might experience a hold time violation? Solution Te® Tpeq + Tpd + Tsetup Longest path: Te2 Tpcq + 3°Tpd + Tsetup Te2 70 + 3°100 + 60 = 430 ps Max Frequency = 1/Te = 2.33 GHz Teog + Ted2Thold + Tekew Shortest Path: ‘Teog + Ted 2 Thold + Tskew 50 + 552 20 + Tskew ‘skew < 85 ps Te2 Tpoq + 2'Tpd + Tsetup + Tskew To2 330 + Tekew Teog + 2Ted 2 Thold + Tskew Tskews 140 ps. Problem 2: Q. Determining the Max. Clock Frequency for a Sequential Circuit tage tons tog =2ns tea =2n8 CLK ten a™ 106 tog =208 ten 2ne the 2ns D o alt jeo—tn a A clk hitpssvsi-backend-adventure.comsta_numercal him! CLK Out aT518723, 6:40 PM. [STA Numerals | VLSI Back-End Adventure Solution Before starting timing analysis, consider the flow of data in this circuit in response to a rising clock edge, starting at flip-flop A. 1. Following the rising clock edge on Clk, a valid output appears on signal X after tClk-Q = 10 ns. 2. Avalid output Y appears at the output of inverter F, tpd = 5 ns after a valid X arrives at the gate. 3. Signal Y is clocked into flip-lop B on the next rising clock edge. This signal must arrive at least ts = 2ns before the rising clock edge. As a result, the minimum clock period, Tmin of the circuit is: ‘Tmin = tCik - Q(A) + tpd(F) + ts(B) = 10ns + Sns + 2ns = 17ns maximum clock frequency of the cit Problem 3: Q. Determining the Max. Clock Frequency the Sequential circuit shown below. tena” one ‘cua’ teg "270 teg72ne ered tgr2ne thetns te tne al oa c =2ne tg=2ns theans t ted Ina typical sequential circuit design there are often millions of flip-lop to fip-flop paths that need to be considered in calculating the maximum clock frequency. This frequency must be determined by locating the longest path among all the flip-flop paths in the circuit. For example, consider the circuit shown in above. there are three flip-flop to flip- flop paths (flop A to flop B, flop A to flop C, flop B to flop C),the delay along all three paths are: TAB = {Clk-Q(A) + ts(8) = 9 ns + 2ns = 11 ns TAC = (Clk-Q(A) + tpd(Z) + ts(C) = 9 ns + 4ns + 2ns = 15 ns hitpssvsi-backend-adventure.comsta_numercal him! a7518723, 6:40 PM. [STA Numerals | VLSI Back-End Adventure TBC = (Cik-Q(B) + tpd(Z) + ts(C) = 10 ns + 4 ns + 2 ns = 16 ns Since the TBC is the largest of the path delays, the minimum clock period for the circuit is Tmin = 16 ns and the maximum clock frequency is 1/Tmin = 62.5 MHz. Problem 4: Q. For the circuit given below calculate. + Maximum clock frequency for reliable operation. + The amount of clock skew the circuit can tolerate if it needs to operate at 5 Ghz. + How much clock skew the circuit can tolerate before it experiences a hold time violation? uw cu ck Gate Tpalps) | Tedlps) es i Sip [0S «3 Zinputnor [30 | 20 e y [Zinputxor [60 [40 }) b= a NOT 15 10 =a 23 Flip-Flop (clock-to-q) propagation delay (tpcq) = 35 ps Flip-Flop (clock-to-q) contamination delay (tecq) = 20 ps Flop data setup time (ts) = 30 ps Flop data hold time (th) = 10 ps Solution a Period > (FF propagation delay) + (max combination circuit delay) + (FF Setup time) + (max clock skew) Period > 35 + (60+20) + 30 +0 ps Period > 145 ps F< 4/(145 ps) F < 6.8965 GHz. At F= 5 GHz Period = 1/(5 Ghz) = 200 ps. Max clock skew = Clock period — (FF propagation delay + max combination circuit delay + FF Setup time) Max clock skew = 200 — (35 + (60+20) + 30) = 200-145 = 55 ps. hitpssvsi-backend-adventure.comsta_numercal him! an518723, 6:40 PM. ‘STA Numerals | VLSI Back-End Adventure For hold time violation to NOT occur. Hold time <= (FF contamination delay) + (min combinational circuit delay) - (max clock skew) ‘So hold time will get violated when ConterftléhNiinetiaeéck skew > (FF contamination delay) + (min combinational circuit delay) — (Hold Time) Max clock skew > 20 + (20+10) ~ 10 + Problem 1 Max clock skew > 40 ps + Problem 2 + Problem 3 + Problem 4 + Problem § Problem 5: Q. For the circuit given below calculate. a. setup slack b. hold slack FFT FF2 Talk-g min = 9ns Talk-g max = ‘ins min = ins. Frac = 20s] Clk = 16.68 MHz. in =2n0 Tp = 15ns Solution before proceeding with the solution we should know setup slack = RTmin(minimum required time) - ATmax(maximum arrival time) where; RTmin 2 ATmax to satisfy setup time Hold Slack = ATmin(minimum arrival time) - RTmax(maximum arrival time) where; ATmax 2 RTmin to satisfy hold time Let's solve this. hitps:vsi-backend-adventure.comsta_numercals html 57518723, 6:40 PM. ‘STA Numerals | VLSI Back-End Adventure a, Setup Slack ATmax=2+11+24+9+2+3=29ns RTmin = 2+ 5 +2 + 18(here 15ns is the time perid) = 24ns 24-29 Setup slack = ATmax - RTmi ns we can see setup is violating as ATmax is less than RTmin b. Hold Slack ATmin RTma» +9+1+6+1-2 (here Thold is considered and subtracted) 34943=16ns 16ns Hold Slack = ATmin - RTmax = 16 - 15 = tns here ATmax 2 RTmin i.e 16 2 15 (no violation) PHYSICAL DESIGN |e INTERVIEW Q&A Digital Electronics Q&A (digital_electronics.html) Physical Design MCQs _(pd_mcgs.html) STANumericals {sta_numericals.html) PD Verification (pd_verification.html) Logic Synthesis v PD Inputs v FloorPlan v PowerPlan v Placement Vv cts v Routing y hitps:vsi-backend-adventure.comsta_numercals html o7