KS 23 AL 1, Avbat is the distinction between a) Computer organization and computer architecture? b) Computer structure and computer function? ©) What ae the four main functions of a computer? 2, Mescribe followings a) stored program computer b) the four main components of any general-purpose computer + 6) the key distinguishing feature of a microprocessor 4) Moore's faw x 3+ Write an IAS program to compute the results of the following equation Y=PRAX Assume that the result of the computation does not arithmetic overflow and that X, Y, and N are positive integers with N- 1. Note: The IAS did not have assembly language only machine language a) Use the equation Sum(Y)= N(N+1)/2 when writing the IAS program b) Do it the “hard way,” without using the equation from part (a) 47 On the IAS, describe in English the process that the CPU must undertake to read a value from memory and to write a value to memory in terms of what is put into the MAR, MBR, address bus, data bus, and control bus . Given the memory contents of the IAS computer shown below, Address Contents 08A O10FA210FB 08B O10FAOFO8D __08C_020FA210"8_ Show the assembly language code for the program, starting at address O8. Explain what this program does ‘ion scheme that can be used with an obsolete bus % _ scheme known as Multibus 1. Agents are daisy-chained physically in priority order. The left most agent in the diagram receives a constant bus priority in (BPRN) signal indicating i no higher-priority agent desires the bus. If the agent does not require the bus, it asserts its ' vs priority out (BPRO) line. At the beginning of a ‘clock cycle, any agent can request a : the bus by lowering its BPRO line. This lowers the BPRN line of the next i. ; dl a ‘which is in turn required to lower its BPRO line. Thus, the signal is propagated the eng 6. Figure indicates a distributed arbitrati 1~ the chain. At the end of this chain reaction, there should be only one agent whose BPRN is asserted and whose BPRO is not. This agent has priority. If, at the beginning of a bus cycle, the bus is not busy (BUSY inactive), the agent that has priority may seize control of the bus by asserting the BUSY line It takes a certain amount of time for the BPR signal to propagate from the highestpriority agent to the lowest. Must this time be less than the clock cycle? Explain. Bus terminator terminator I “BPRN BPRO” "BPRN BPRO| [BPRN — BPRO- (highest privrity) lowest priority Master! Master L_ Master3 While browsing at Billy Bob’s computer store, you overhear a customer asking Billy Bob what is the fastest computer in the store that he can buy. Billy Bob replies, “You're looking at our Macintoshes. The fastest Mac we have runs at a clock speed of 1.2 GHz. If you really want the fastest machine, you should buy our 2.4-GHz Intel Pentium IV instead.” Is Billy Bob correct? What would you say to help this customer? For the calculation of average CPI and MIPS rate, which yielded the result of CPI = 2.24 and MIPS rate = 178. Now assume that the program can be executed in eight parallel tasks or threads with roughly equal number of instructions executed in each task. Execution is on an 8-core system with each core (processor) having the same performance as the single processor originally used. Coordination and synchronization between the parts adds an extra 25,000 instruction executions to each task. Assume the same instruction mix as in the example for each task, but increase the CPI for memory reference with cache miss to 12 cycles due to contention for memory. a) Determine the average CPI. b) Determine the corresponding MIPS rate. c) Calculate the speedup factor. d) Compare the actual speedup factor with the theoretical speedup factor determined by Amdhal’s law.10. Instruction Type | Instruction Count | Cycles Per (millions) Instruction (millions) | _- Machine A : Arithmetic and logic 8 1 Load and store 4 3 | Branch ae 7 Others a Machine A | Arithmetic and logic T Load and store | Branch 3 Lowe ae ps a) Determine the effective CPI, MIPS rate, and execution time for each machine b) Comment on the results A processor accesses main memory with an average access time of T2. A smaller cache memory is interposed between the processor and main memory. The cache has a significantly faster access time of T1 <2. The cache holds, at any time, copies of some main memory words and is designed so that the words more likely to be accessed in the near future are in the cache. Assume that the probability that the next word accessed by the processor is in the cache is H, known as the hit ratio. a) For any single memory access, what is the theoretical speedup of accessing the word in the cache rather than in main memory? b) Let T be the average access time. Express T as a function of Tl, T2, and H. What is the overall speedup as a function of H? ©) In practice, a system may be designed so that the processor must first access the cache to determine if the word is in the cache and, if itis not, then access main memory, so that on a miss (opposite of a hit), memory access time is T] + T2. Express T as a function of TI, 2, and H. Now calculate the speedup and compare to the result produced in part (b). Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of two fields: the first byte contains the opcode and the remainder the immediate operand or an operand address. a) What is the maximum directly addressable memory capacity (in bytes)? b) Discuss the impact on the system speed if the microprocessor bus has i, 32-bit local address bus and a 16-bit local data bus, or ii, a 16-bit local address bus and a 16-bit local data bus. ©) How many bits are needed for the program counter and the instruction register?“Vv 12. Consider i as a hypothetical microprocessor generating a 16-bit address (for example, assume a Program counter and the address registers are 16 bits wide) and having a 16-bit data 8) What is the maximum memory address space that the processor can access directly if it is connected to a “16-bit memory"? ») What is the maximum memory address space that the processor can access directly if it is connected to an “8-bit memory"? ©) What architectural features will allow this microprocessor to access a separate “VO space”? 4) Ifan input and an output instruction can specify an 8-bit /O port number, how many 8- bit /0 ports can the microprocessor support? How many 16-bit I/O ports? Explain 13. Consider two microprocessors having 8- and 16-bit-wide external data buses, respectively. The two processors are identical otherwise and their bus cycles take just as long. a) Suppose all instructions and operands are two bytes long. By what factor do the maximum data transfer rates differ? b) Repeat assuming that half of the operands and instructions are one byte long 14, For a synchronous read operation (Figure 3.18), the memory module must place the data on the bus sufficiently ahead of the falling edge of the Read signal to allow for signal settling. Assume a microprocessor bus is clocked at 10 MHz and that the Read signal begins to fall in the middle of the second half of T3 a) Determine the length of the memory read instruction cycle. b) When, at the latest, should memory data be placed on the bus? Allow 20 ns for the settling of data lines. 15. Consider a microprocessor that has a memory read timing as shown in Figure 3.18. After some analysis, a designer determines that the memory falls short of providing read data on time by about 180 ns a) How many wait states (clock cycles) need to be inserted for proper system operation if the bus clocking rate is 8 MHz? b) To enforce the wait states, a Ready status line is employed. Once the processor has issued a Read command, it must wait until the Ready line is asserted before attempting to read data. At what time interval must we keep the Ready line low in order to force the processor to insert the required number of wait states? 16. The Intel 8088 microprocessor has a read bus timing similar to that of Figure 3.18, but requires four processor clock cycles. The valid data is on the bus for an amount of time that extends into the fourth processor clock cycle. Assume a processor clock rate of 8 MHz. (9) What is the maximum data transfer rate? () Repeat but assume the need to insert one wait state per byte transferred.17. The memory of a particular microcomputer is built from 64K x 1 DRAMS. According to the data sheet, the cell array of the DRAM is organized into 256 rows. Each row must be refreshed at least once every 4 ms. Suppose we refresh the memory on a strictly periodic basis. a. What is the time period between successive refresh requests? b. How long a refresh address counter do we need? 18. Design a 16-bit memory of total capacity 8192 bits using SRAM chips of size 64 x | bit. Give the array configuration of the chips on the memory board showing all required input and output signals for assigning this memory to the lowest address space. The design should allow for both byte and 16-bit word accesses, 19. Consider a dynamic RAM that must be given a refresh cycle G4 times per ms. Each refresh Operation requires 150 ns; a memory cycle requires 250 ns. What percentage of the memory’ total operating time must be given to refreshes? 20. A set-associative cache consists of 64 lines, or slots, divided into four-line sets. Main memory contains 4K blocks of 128 words each. Show the format of main memory addresses. 21 Consider a machine with a byte addressable main memory of 216 bytes and block size of 8 bytes. Assume that a direct mapped cache consisting of 32 lines is used with this machine. a. How is a 16-bit memory address divided into tag, line number, and byte number? b. Into what line would bytes with each of the following addresses be stored? 1. 0001 0001 0001 1011 2. 11000011 0011 0100 3. 1101 0000 0001 1101 4. 1010 1010 1010 1010 ¢. Suppose the byte with address 0001 1010 0001 1010 is stored in the cache. What are the addresses of the other bytes stored along with it? d. How many total bytes of memory can be stored in the cache? e. Why is the tag also stored in the cache? 22. A set-associative cache has a block size of four 16-bit words and a set size of 2. The cache can accommodate a total of 4096 words. The main memory size that is cacheable is 64K x 32 bits. Design the cache structure and show how the processor's addresses are interpreted. 23, Consider a memory system with the following parameters: 1. Te=100ns Ce = 10* $/bit 2. Tm = 1200 ns Cm = 10° $/bit What is the cost of 1 Mbyte of main memory? What is the cost of 1 Mbyte of main memory using cache memory technology?h If the effective access time is 10% greater than the cache access time, what is the hit ratio H? 24. The performance of a single-level cache system for a read operation can be characterized by 7 the following equation: 4 28. Define Tb = time to transfer a Ii write references. Revise the preceding equation to account Ta=Te + (1-H) Tm where Ta is the average access time, Te is the cache access time, Tm is the memory access time (memory to processor register), and H is the hit ratio. For simplicity, we assume that the word in question is loaded into the cache in parallel with the load to processor register. ine between cache and main memory, and W = fraction of for writes as well as reads, using a write-through policy. b 26. Define Wb as the probability that a line in the cache has been altered. Provide an equation for Ta for the write-back policy. Define the terms seek time, rotational delay, access time, and transfer time. 7. Ans fol 27. Answer followings ii ii iv, v. vi. vii. viii. What common characteristics are shared by all RAID levels? Briefly define the seven RAID levels. Explain the term striped data. How is redundancy achieved in a RAID system? In the context of RAID, what is the distinction between parallel access and independent access? ‘What is the difference between CAV and CLV? What differences between a CD and a DVD account for the larger capacity of the latter? Explain serpentine recording. 28. Define the following for a disk system: a. ts=seek time; average time to position head over track b. r=rotation speed of the disk, in revolutions per second ¢. n=number of bits per sector d. N= capacity of a track, in bits e, tA=time to access a sector £. Develop a formula for tA as a function of the other parameters. 29, Consider a magnetic disk drive with 8 surfaces, 512 tracks per surface, and 64 sectors per 7 track. Sector size is 1 KB. The average seek time is 8 ms, the track-to-track access time is 1.5 ims, and the drive rotates at 3600 rpm. Successive tracks in a cylinder can be read without head movement. a. What is the disk capacity?b, What is the average access time? Assume this file is stored in successive sectors and tracks of successive cylinders, starting at sector 0, track 0, of cylinder i. c. Estimate the time required to transfer a 5-MB file. d. What is the burst transfer rate? 30. Consider a disk that rotates at 3600 rpm. The seek time to move the head between adjacent tracks is 2 ms. There are 32 sectors per track, which are stored in linear order from sector 0 through sector 31. The head sees the sectors in ascending order. Assume the read/write head is positioned at the start of sector 1 on track 8. There is a main memory buffer large enough to hold an entire track. Data is transferred between disk locations by reading from the source track into the main memory buffer and then writing the data from the buffer to the target track. a, How long will it take to transfer sector 1 on track 8 to sector 1 on track 9? b. How long will it take to transfer all the sectors of track 8 to the corresponding sectors of track 9? 31. On a typical microprocessor, a distinct I/O address is used to refer to the I/O data registers and a distinct address for the control and status registers in an I/O controller for a given device. Such registers are referred to as ports. In the Intel 8088, two I/O instruction formats are used. In one format, the 8-bit opcode specifies an I/O operation; this is followed by an 8- bit port address. Other I/O opcodes imply that the port address is in the 16-bit DX register. How many ports can the 8088 address in each I/O addressing mode? 32. A system is based on an 8-bit microprocessor and has two V/O devices. The /O controllers for this system use separate control and status registers. Both devices handle data on a 1- byte-at-a-time basis. The first device has two status lines and three control lines. The second device has three status lines and four control lines. a. How many 8-bit /O contro! module registers do we need for status reading and control of each device? b. What is the total number of needed control module registers given that the first device is an output-only device? c. How many distinct addresses are needed to control the two devices? 33. A particular system is controlled by an operator through commands entered from a keyboard. ‘The average number of commands entered in an 8-hour interval is 60. a. Suppose the processor scans the keyboard every 100 ms. How many times will the keyboard be checked in an 8-hour period? b. By what fraction would the number of processor visits to the keyboard be reduced if interrupt-driven /O were used? 34.A DMA module is transferring characters to memory using cycle stealing, from a device transmitting at 9600 bps. The processor is fetching instructions at the rate of 1 millioninstructions per second (1. MIP! 'y how much will the processor be v pe ( S). By h I the proc be slowed down due to 35. A DMA controll ; ler serves four receive-only telecommunication link: € per having a speed of 64 Kbps each. Sone per DMA came) 7 a You operate the controller in burst mode or in cycle-stealing mode? . What priority scheme would you employ for service of the DMA channels? 36. Suppose that we have a multiprogrammed computer in which each job has identical characteristics. In one computation period, T, for a job, half the time is spent in /O and the other half in processor activity. Each job runs for a total of N periods. Assume that a simple used, and that /O operations can overlap with processor operation. round-robin priority Define the following quantities: Turnaround time = actual to complete a job Throughput = average number of jobs completed per time period T Processor utilization = percentage of time that the processor is active (not waiting) ‘Compute these quantities for one, two, and four simultaneous jobs, assuming that the period T is distributed in each of the following ways: V/O first half, processor second half f. VO first and fourth quarters, processor second and third quarters Be oe 9 37. Consider a fixed partitioning scheme with equal-size partitions of 216 bytes and a total main jemory size of 224 bytes. A process table is maintained that includes a pointer to a partition for each resident process. How many bits are required for the pointer? 38. Consider a hypothetical computer with an instruction set of only two n-bit instructions. The first bit specifies the opcode, and the remaining bits specify one of the 2' -bit words of main memory. The two instructions are as follows SUBS X Subtract the contents of location X from the accumulator, and store the result in a location X and the accumulator. b. JUMP X Place address X in the program counter. 39. A word in main memory may contain either an instruction or a binary number in twos complement notation. Demonstrate that this instruction repertoire is reasonably complete by specifying how the following operations can be programmed: ‘a. Data transfer: Location X to accumulator, accumulator to location X b. Addition: Add contents of location X to accumulator ¢. Conditional branch d. Logical OR e. 1/0 Operations40. Convert the following formulas from infix to reverse Polish: a A+B+C+D+E b (A+B)x(C+D) +E « (AXB)+(CxD)+E d. (A-B)x ((C-DxEVFYG)xH 41. Given the following memory values and a one-address machine with an accumulator, what values do the following instructions load into the accumulator? Word 20 contains 40., « Word 30 Contains S0., « Word 40 contains 60., * Word 50 contains 70, LOAD IMMEDIATE 20 LOAD DIRECT 20 LOAD INDIRECT 20 LOAD IMMEDIATE 30 LOAD DIRECT 30 LOAD INDIRECT 30 42. An address field in an instruction ¢ operand located for a. immediate addressing? . direct addressing? ¢. indirect addressing? 4. register addressing? ©. register indirect addressing? ‘ontains decimal value 14. Where is the corresponding 43. Design a variable-length opcode to allow all Of the following to be encoded in a 36-bit instruction: instructions with two 15-bit addresses and one 3-bit register number b. instructions with one 15-bit address and one 3-bit register number ¢. instructions with no addresses or registers ‘“4-ARISC machine's compiler may do both a mapping of symbolic registers to actual registers and a rearrangement of instructions for pipeline efficiency. An interesting question arises as to the order in which these two operations should be done. Consider the following program fragment: LD SRI, A sload A into symbolic register | LD SR2, B ;load B into symbolic register 2 ADD SR3, SRI, SR2 jadd contents of SRI and SR2 and store in SR3 LD SR4,C LDSRS,D ADD SR6, SR4, SRS 4 First do the register mapping and then any possible instruction reordering. How many ‘machine registers are used? Has there been any pipeline improvement?b. Starting with the original program, now do instruction reordering and then anypossible mapping, How many machine registers are used? Has there been any pipeline improvement? i : i i i I 1 1, $1, I ! | 1 | ' i ' Clock ft \ IV SV ys t ' 1 1 ' | ' 1 Status, i _. ot ! lines Status signals ' H 7 1 Adres \ 1 - | ' 7 1 ( i Address ' ! ' enable 4 ! 1 i 1 ! i t | f Dats H ——— \ ties t t Valid data in Read _) | ' cycle } \ Read ' , ! 7 ' | { Data I 1 \ lines + Valid data out 1 | t 1 | ' | 1 i \ \ | (Write a rs ee A I Figure 8.4 Timing of Synchronous Bus Operations 10