ELEC 204 Digital Design – Final Exam – 05.06.

2021
Dr. Ertuğrul Başar
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NAME & SURNAME:
NUMBER:
DEPARTMENT:
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Instructions (Please Read Carefully):
1) Please carefully mark your solutions with question/part numbers (1.a), (1.b)…. Please also ensure that your scans are
clear and readable.
2) Please sign the attached honor code (you can copy-and-paste your signature or write it down and sign it).
3) Please upload your assignment as a single PDF file until 05.06.2021, 3:00 PM (sharp). Late assignments or files sent
through the email will not be considered.
For questions: [email protected]

Points:
1) 20 2) 20 3) 20 4) 20 5) 20

STUDENT HONOR CODE

I hereby certify that I have completed this exam on my own without any help from anyone else.
I understand that the only sources of authorized information in this open-book exam are
(i) the course textbook/reference book, and
(ii) the lecture notes self-taken or distributed by the instructor at Blackboard for this class.
I have not used, accessed, received or distributed any information from/to any other unauthorized source in taking this exam.
The effort in the exam thus belongs completely to me.
Signature:
Question 1 (Boolean Functions and Logic Gates) A logic circuit has four inputs (W, X, Y, and Z) along with an enable input
(EN) to implement the Boolean function as given in the below truth table.

0 0 0 0 1 0
0 0 0 1 1 1
0 0 1 0 1 0
0 0 1 1 1 0
0 1 0 0 1 0
0 1 0 1 1 0
0 1 1 0 1 0
0 1 1 1 1 0
1 0 0 0 1 0
1 0 0 1 1 1
1 0 1 0 1 0
1 0 1 1 1 1
1 1 0 0 1 0
1 1 0 1 1 1
1 1 1 0 1 0
1 1 1 1 1 1
X X X X 0 0

Solution:
(1.a) 4 PTS Find the optimized expression for .

(1.b) 4 PTS Implement this function with NAND gates only.

(1.c) 4 PTS Implement this function with NOR gates only.

(1.d) 4 PTS Implement this function using an 8-to-1 multiplexer.

Note that!
W X Y F1
000 → 𝑍
001 → 0
010 → 0
011 → 0
100 → 𝑍
101 → 𝑍
110 → 𝑍
111 → 𝑍

(1.e) 4 PTS Implement this function using a 3-to-8 line decoder.

Question 2 (Combinational Logic and Binary Numbers) Design a combinational circuit that performs the addition of two
2-bit numbers ( and ). When the control input is low, the circuit outputs a three-bit number that represents
the arithmetic sum of the inputs, otherwise the outputs are zero.
Solution:

State Table: 7 PTS

0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 0 0 1 0
0 0 1 1 0 1 1
0 1 0 0 0 0 1
0 1 0 1 0 1 0
0 1 1 0 0 1 1
0 1 1 1 1 0 0
1 0 0 0 0 1 0
1 0 0 1 0 1 1
1 0 1 0 1 0 0
1 0 1 1 1 0 1
1 1 0 0 0 1 1
1 1 0 1 1 0 0
1 1 1 0 1 0 1
1 1 1 1 1 1 0

K-map Simplification: 6 PTS

𝑧 7,10,11,13,14,15 𝑧 2,3,5,6,8,9,12,15 𝑧 1,3,4,6,9,11,12,14

𝑧 𝑥 𝑥 𝑦 𝑥 𝑦 𝑦 𝑧 𝑥 𝑦 𝑥 𝑦
𝑧 𝑥 𝑦 𝑥 𝑥 𝑦 𝑥 𝑦 𝑦
𝑥 𝑥 𝑦 𝑥 𝑦 𝑦
𝑥 𝑥 𝑦𝑦 𝑥 𝑥 𝑦 𝑦
Building Circuit: 7 PTS

𝑥 𝑥 𝑦 𝑦

𝐶𝑜𝑛𝑡𝑟𝑜𝑙

𝑊ℎ𝑒𝑛 𝑐𝑜𝑛𝑡𝑟𝑜𝑙 1 𝑜𝑢𝑡𝑝𝑢𝑡𝑠 → 0

Question 3 (Sequential Logic): Construct the state equations and the state table for the following circuit. Plot the state
diagram. For the following and inputs, draw and , where the initial values of and are 0.

Solution:

A
Y D Q

Q’

B
D Q

X Q’

CLK

State Equations: 5 PTS State Table: 5 PTS

𝑨 𝒕 𝟏 𝑿 𝑨 𝒕 𝒀 Present State Inputs Next State
1 1
𝑩 𝒕 𝟏 𝑿⨁𝑩 𝒕 𝑿𝑩 𝒕 𝑿𝑩 𝒕
0 0 0 0 0 0
For notational simplicity: 0 0 0 1 1 0
0 0 1 0 0 1
𝑨 𝒕 𝟏 𝑿𝒀 𝑨𝒀 0 0 1 1 1 1
0 1 0 0 0 1
𝑩 𝒕 𝟏 𝑿𝑩 𝑿𝑩
0 1 0 1 1 1
0 1 1 0 0 0
0 1 1 1 1 0
1 0 0 0 0 0
1 0 0 1 0 0
1 0 1 0 0 1
1 0 1 1 1 1
1 1 0 0 0 1
1 1 0 1 0 1
1 1 1 0 0 0
1 1 1 1 1 0
State Diagram: 5 PTS

Draw A(t) and B(t): 5 PTS

X(t) 0 1 0 1

Y(t) 1 1 0 1

CLK

0 1 1 0 1
A(t)

0 0 1 1 0
B(t)
Question 4 (Counters): Design a sequential circuit with positive-edged T flip-flops that counts up with clock pulses over
Fibonacci numbers (1, 2, 3, 5, 8, 13) that can be represented using 4-bit binary values . The circuit (re)starts
counting from 1 after it reaches 13. This circuit outputs 1 when the counter value is 1, 5 or 8, for other cases it outputs
0.
(4.a) Draw the state diagram of this circuit.
(4.b) Prepare the state table for this counter. Indicate every possible present state and map these states to a corresponding next
state and output value.
(4.c) Derive the simplified flip-flop input equations and output equations.
(4.d) Draw the logic diagram.

Solution:
(4.a) 4 PTS

State Assignments
1 2 3 5 8 13
0001 0010 0011 0101 1000 1101

(4.b) 6 PTS
Present State Next State Output FF Inputs

0 0 0 0 - - - - x x x x x
0 0 0 1 0 0 1 0 1 0 0 1 1
0 0 1 0 0 0 1 1 0 0 0 0 1
0 0 1 1 0 1 0 1 0 0 1 1 0
0 1 0 0 - - - - x x x x x
0 1 0 1 1 0 0 0 1 1 1 0 1
0 1 1 0 - - - - x x x x x
0 1 1 1 - - - - x x x x x
1 0 0 0 1 1 0 1 1 0 1 0 1
1 0 0 1 - - - - x x x x x
1 0 1 0 - - - - x x x x x
1 0 1 1 - - - - x x x x x
1 1 0 0 - - - - x x x x x
1 1 0 1 0 0 0 1 0 1 1 0 0
1 1 1 0 - - - - x x x x x
1 1 1 1 - - - - x x x x x
(4.c) 6 PTS
(4.d) 4 PTS
Question 5 (Programmable Logic): Tabulate the PLA programming table for the four Boolean functions listed below.
Minimize the number of product terms and draw the PLA circuit.
Solution:

 , , 0,1,5,7 3 PTS

 , , 2,4,5,6 3 PTS
 , , 0,1,2,3,4 3 PTS

 , , 3,6,7 3 PTS
 Considering both true and complemented functions, we see that four product terms are enough!

Consider , , , → , , ,
4 PTS

PLA Programming Table (T: True, C: Complement)

Inputs Outputs
Product Term x y z A (T) B (C) C (C) D (T)
1 0 0 - 1 1 - -
2 1 - 1 1 - 1 -
3 - 1 1 - 1 - 1
4 1 1 - - - 1 1

4 PTS