#include <LPC214x.

h>

int main(void) {
unsigned int LED_Data = 0x000001FF; // Initialize LED_Data to all LEDs off
IODIR0 = LED_Data; // Configure P0.18 to P0.25 as output
while (1) { // Loop forever
IOSET0 = LED_Data; // Turn on all LEDs
delay_ms(1000); // Delay for 1 second
IOCLR0 = LED_Data; // Turn off all LEDs
delay_ms(1000); // Delay for 1 second
}
}

void delay_ms(unsigned int ms) {

unsigned int i, j;
for (i = 0; i < ms; i++) {
for (j = 0; j < 8000; j++) {} // Adjust this delay value for your
specific clock speed
}
}

+------------------+
| ARM Processor |
| |
| P0.18 |
| | |
| 330 ohm |
| | |
| LED |
| | |
| 330 ohm |
| | |
| P0.25 |
+------------------+

3) Explore with suitable example pre-indexing & post-indexing addressing modes

for LDR/STR instructions

In ARM architecture, LDR and STR instructions are used to load and store data
to/from memory. These instructions can use pre-indexing and post-indexing
addressing modes to access memory.

In pre-indexing addressing mode, the base register is updated with an offset before
accessing the memory. In post-indexing addressing mode, the base register is
updated with an offset after accessing the memory.

Let's consider the following example code to understand pre-indexing and post-
indexing addressing modes for LDR/STR instructions:
LDR r1, [r0, #4] ; Load the value at address r0+4 into r1
LDR r2, [r0, #4]! ; Load the value at address r0+4 into r2, and update r0 to
r0+4
STR r3, [r0, #4] ; Store the value in r3 to address r0+4
STR r4, [r0], #4 ; Store the value in r4 to address r0, and update r0 to
r0+4
In the first instruction, the value at memory location r0+4 is loaded into register
r1 using pre-indexing addressing mode. The offset of 4 is added to the base
register r0 to form the effective memory address.
In the second instruction, the value at memory location r0+4 is loaded into
register r2 using post-indexing addressing mode. The offset of 4 is added to the
base register r0 after the memory access is complete, which means the value of r0
is updated to r0+4.

In the third instruction, the value in register r3 is stored to memory location

r0+4 using pre-indexing addressing mode. The offset of 4 is added to the base
register r0 to form the effective memory address.

In the fourth instruction, the value in register r4 is stored to memory location r0

using post-indexing addressing mode. The value of r4 is stored at the memory
location pointed to by r0, and then the value of r0 is updated to r0+4.

So, in summary, pre-indexing addressing mode updates the base register before
accessing memory, and post-indexing addressing mode updates the base register after
accessing memory. These addressing modes can be used to simplify code and improve
performance in certain situations, such as when accessing elements of an array in
memory.

4) Write note on CPSR register with significance of each field with bit format

The CPSR (Current Program Status Register) is a 32-bit register in the ARM
architecture that contains information about the current state of the processor.
The CPSR register is used to control and monitor the execution of the program. It
has four fields that represent the status of the processor and the current
execution mode:

Negative (N) Flag (Bit 31): The Negative flag is set to 1 if the result of the
previous instruction was negative, or 0 if the result was positive or zero.

Zero (Z) Flag (Bit 30): The Zero flag is set to 1 if the result of the previous
instruction was zero, or 0 if the result was non-zero.

Carry (C) Flag (Bit 29): The Carry flag is set to 1 if the previous instruction
caused a carry out of the most significant bit of the result, or 0 otherwise.

Overflow (V) Flag (Bit 28): The Overflow flag is set to 1 if the previous
instruction caused a signed overflow, or 0 otherwise.

Reserved (Bits 27-8): These bits are reserved for future use and are set to 0.

Interrupt (I) Disable (Bit 7): The Interrupt Disable bit is set to 1 if interrupts
are disabled, or 0 if they are enabled.

FIQ (Fast Interrupt Request) Disable (Bit 6): The FIQ Disable bit is set to 1 if
FIQ interrupts are disabled, or 0 if they are enabled.

IRQ (Interrupt Request) Disable (Bit 5): The IRQ Disable bit is set to 1 if IRQ
interrupts are disabled, or 0 if they are enabled.

Thumb State (Bit 4): The Thumb State bit is set to 1 if the processor is currently
in Thumb mode, or 0 if it is in ARM mode.

Execution Mode (Bits 3-0): These bits represent the current execution mode of the
processor. The possible values are:
0b10000 = User Mode
0b10001 = FIQ Mode
0b10010 = IRQ Mode
0b10011 = Supervisor Mode
0b10111 = Abort Mode
0b11011 = Undefined Mode
0b11111 = System Mode
The CPSR register is updated after every instruction execution and is used to
determine the execution mode, to enable or disable interrupts, and to check the
results of previous instructions. It is also used to determine whether the
processor is in Thumb or ARM mode. The CPSR register can be read using the MRS
(Move Register from Status) instruction and can be modified using the MSR (Move
Status Register to Register) instruction.

5) What are various Banked registers of ARM7 processor? Describe operating mode
change.

The ARM7 processor has several Banked Registers, which are copies of the registers
that are saved and restored when the processor changes between different modes of
operation. These registers are divided into two categories:

User mode Registers: These are the registers that are used when the processor is
executing in User mode. These include the General Purpose Registers (R0-R12) and
the Stack Pointer (SP).

System mode Registers: These are the registers that are used when the processor is
executing in System mode or other privileged modes such as FIQ, IRQ, Supervisor,
Abort, or Undefined modes. These include the same General Purpose Registers (R0-
R12) and the Stack Pointer (SP), but also include additional registers such as the
Saved Program Status Register (SPSR) and the Link Register (LR).

Operating mode change refers to the process of switching between different modes of
operation in the ARM7 processor. When the processor switches between different
modes, it must save the contents of the current mode's banked registers and load
the contents of the new mode's banked registers.

For example, when the processor switches from User mode to FIQ mode, it saves the
contents of the User mode banked registers (R0-R12 and SP) and loads the contents
of the FIQ mode banked registers (R8-R12 and SP). When the processor switches back
to User mode, it restores the contents of the User mode banked registers.

The operating mode of the ARM7 processor can be changed using the Mode bits in the
CPSR register. The mode can be changed using the MSR (Move to Status Register)
instruction. The processor also provides instructions such as SRS (Store Return
State) and RFE (Return from Exception) that help in the context switching process
during mode change.

6) Explain with example 3 stage pipeline architecture used in ARM processor

The ARM processor uses a 3-stage pipeline architecture to improve its performance.
The 3 stages are:

Fetch Stage: The first stage is the Fetch stage, where the processor fetches the
instruction from memory. The instruction is fetched from memory into the
instruction cache and is then loaded into the Instruction Register (IR). This stage
includes the address calculation for fetching the instruction.

Decode Stage: In the second stage, the processor decodes the instruction to
determine what operation needs to be performed. In this stage, the processor also
determines the operands that are needed to perform the operation. The decoded
instruction is stored in the Decode Register (DR), and the operand addresses are
calculated.

Execute Stage: In the final stage, the processor executes the instruction. This
stage includes the actual execution of the instruction and the storage of the
result in the appropriate register. The result is stored in the appropriate
register, and the program counter (PC) is incremented to fetch the next
instruction.

Let's consider an example of a simple ARM instruction sequence and how it is

processed through the 3-stage pipeline architecture.

ADD R1, R2, R3

SUB R4, R1, #10

Fetch Stage: The first instruction is fetched from memory and loaded into the
Instruction Register (IR). The program counter (PC) is incremented to fetch the
next instruction.

Decode Stage: The fetched instruction is decoded to determine the operation that
needs to be performed, which is an ADD operation. The processor also determines the
registers that are needed to perform the operation. In this case, the registers R2
and R3 are the operands, and the result will be stored in R1. The decoded
instruction is stored in the Decode Register (DR).

Execute Stage: The processor executes the ADD instruction and stores the result in
register R1.

Fetch Stage: The second instruction is fetched from memory and loaded into the
Instruction Register (IR). The program counter (PC) is incremented to fetch the
next instruction.

Decode Stage: The fetched instruction is decoded to determine the operation that
needs to be performed, which is a SUB operation. The processor also determines the
registers that are needed to perform the operation. In this case, the registers R1
and #10 are the operands, and the result will be stored in R4. The decoded
instruction is stored in the Decode Register (DR).

Execute Stage: The processor executes the SUB instruction and stores the result in
register R4.

This is how the ARM processor uses the 3-stage pipeline architecture to process
instructions. The pipeline allows the processor to process multiple instructions
simultaneously, which improves the overall performance of the processor.

7) Describe various registers used for ARM7 GPIO Programming

GPIO (General Purpose Input/Output) pins are used to provide the ability for the
ARM7 processor to interface with external devices. The ARM7 processor provides
several registers that are used for GPIO programming. These registers include:

Pin Data Registers (IOxPIN): These registers are used to read or write the value of
a specific GPIO pin. There are 4 Port Pin Data Registers (IOxPIN) in the ARM7
processor, where x represents the port number (0 to 3). Each register has 32 bits,
where each bit represents the value of a GPIO pin.

Pin Direction Control Registers (IOxDIR): These registers are used to configure the
direction of a specific GPIO pin as either an input or an output. There are 4 Port
Pin Direction Control Registers (IOxDIR) in the ARM7 processor, where x represents
the port number (0 to 3). Each register has 32 bits, where each bit represents the
direction of a GPIO pin.

Pin Output Set Registers (IOxSET): These registers are used to set the value of a
specific GPIO pin to 1. There are 4 Port Pin Output Set Registers (IOxSET) in the
ARM7 processor, where x represents the port number (0 to 3). Each register has 32
bits, where each bit represents a GPIO pin.

Pin Output Clear Registers (IOxCLR): These registers are used to set the value of a
specific GPIO pin to 0. There are 4 Port Pin Output Clear Registers (IOxCLR) in the
ARM7 processor, where x represents the port number (0 to 3). Each register has 32
bits, where each bit represents a GPIO pin.

Pin Output Level Registers (IOxSET, IOxCLR): These registers are used to set the
value of a specific GPIO pin to a specified value. There are 4 Port Pin Output
Level Registers (IOxSET, IOxCLR) in the ARM7 processor, where x represents the port
number (0 to 3). Each register has 32 bits, where each bit represents a GPIO pin.

Pin Interrupt Enable Registers (IOxINTEN): These registers are used to enable or
disable the interrupts generated by a specific GPIO pin. There are 4 Port Pin
Interrupt Enable Registers (IOxINTEN) in the ARM7 processor, where x represents the
port number (0 to 3). Each register has 32 bits, where each bit represents a GPIO
pin.

By using these registers, we can configure the GPIO pins of the ARM7 processor to
operate as input or output pins and can read or write data to them. These registers
are accessed by the ARM7 processor using memory-mapped I/O operations.

8) List operating states & instruction sets features of ARM7TDMI processor

The ARM7TDMI (Thumb/Debug/Multiplier/ICE) processor is a 32-bit RISC

microcontroller, which supports a 16-bit instruction set called Thumb. The
operating states and instruction set features of the ARM7TDMI processor are as
follows:

Operating States: The ARM7TDMI processor supports seven operating states, which are
as follows:

a. User Mode: This mode is used for normal program execution.

b. FIQ Mode: This mode is used for handling fast interrupt requests.

c. IRQ Mode: This mode is used for handling general-purpose interrupt requests.

d. Supervisor Mode: This mode is used for handling operating system functions and
privileged instructions.

e. Abort Mode: This mode is used for handling memory access violations.
f. Undefined Mode: This mode is used for handling undefined instructions.

g. System Mode: This mode is used for low-level system operations, such as power
management and system reset.

Instruction Sets: The ARM7TDMI processor supports two instruction sets, which are
as follows:

a. ARM Instruction Set: This instruction set consists of 32-bit instructions that
are used for high-performance applications. The ARM instruction set includes data
processing instructions, load/store instructions, branch instructions, and
coprocessor instructions.

b. Thumb Instruction Set: This instruction set consists of 16-bit instructions that
are used for code size optimization. The Thumb instruction set includes data
processing instructions, load/store instructions, branch instructions, and
conditional instructions. The Thumb instruction set is a subset of the ARM
instruction set and provides better code density and reduced power consumption.

Instruction Set Features: The ARM7TDMI processor supports several instruction set
features, which are as follows:

a. Conditional Execution: This feature allows instructions to be executed based on

a specific condition. The condition codes are set by the previous instruction and
determine whether the current instruction is executed or not.

b. Barrel Shifter: This feature allows shift and rotate operations to be performed
on the operands before or after the operation is executed.

c. Multiply and Multiply-Accumulate: This feature allows multiplication and

multiplication-accumulation operations to be performed in a single cycle.

d. Coprocessor Support: This feature allows coprocessors to be connected to the

processor and extends the processor's capabilities.

e. Memory Access Modes: The processor supports multiple memory access modes, such
as byte, half-word, and word access modes.

f. Interrupt Handling: The processor supports multiple interrupt handling modes,

such as Fast Interrupt (FIQ) and Interrupt (IRQ) modes, to handle high-priority and
low-priority interrupts, respectively.

9) Explain following ARM instructions

MVN Rd, #N
BEQ Label
ADC Rd,Rn,#N
EOR Rd, Rd
ChatGPT
MVN Rd, #N: This instruction performs a bitwise NOT operation on the 32-bit
immediate value N and stores the result in the destination register Rd. The syntax
of the instruction is as follows:

MVN Rd, #N

For example, the instruction "MVN R1, #0x000000FF" would perform a bitwise NOT on
the value 0x000000FF and store the result (0xFFFFFF00) in register R1.
BEQ Label: This instruction branches to the specified label if the Zero flag is
set. The syntax of the instruction is as follows:

BEQ Label

For example, the instruction "BEQ Loop" would branch to the label "Loop" if the
Zero flag is set.

ADC Rd, Rn, #N: This instruction performs an addition of the value N, the carry
flag, and the value in register Rn, and stores the result in register Rd. The
syntax of the instruction is as follows:

ADC Rd, Rn, #N

For example, the instruction "ADC R1, R2, #5" would add 5, the carry flag, and the
value in register R2, and store the result in register R1.

EOR Rd, Rd: This instruction performs a bitwise exclusive OR (XOR) operation
between the value in register Rd and itself, and stores the result back in register
Rd. The syntax of the instruction is as follows:

EOR Rd, Rd

For example, the instruction "EOR R1, R1" would perform a bitwise XOR operation
between the value in register R1 and itself, and store the result back in register
R1. This effectively sets the value of R1 to zero.

10) Explain following ARM instructions

MOVS Rd, Rn
MOV Rd, Rn, LSL#02
SBC Rd, Rn, #N
CMP, Rm, #N

MOVS Rd, Rn: This instruction copies the value of register Rn into register Rd and
updates the condition flags based on the result. The syntax of the instruction is
as follows:

MOVS Rd, Rn

For example, the instruction "MOVS R1, R2" would copy the value in register R2 into
register R1 and update the condition flags.

MOV Rd, Rn, LSL#02: This instruction performs a logical shift left (LSL) operation
on the value in register Rn by two bits and stores the result in register Rd. The
syntax of the instruction is as follows:

MOV Rd, Rn, LSL#02

For example, the instruction "MOV R1, R2, LSL#02" would shift the value in register
R2 left by two bits and store the result in register R1.

SBC Rd, Rn, #N: This instruction subtracts the value N and the carry flag from the
value in register Rn and stores the result in register Rd. The syntax of the
instruction is as follows:

SBC Rd, Rn, #N

For example, the instruction "SBC R1, R2, #5" would subtract 5 and the carry flag
from the value in register R2, and store the result in register R1.

CMP Rm, #N: This instruction subtracts the value N from the value in register Rm
and updates the condition flags based on the result, but does not store the result
anywhere. The syntax of the instruction is as follows:

CMP Rm, #N

For example, the instruction "CMP R1, #10" would subtract 10 from the value in
register R1 and update the condition flags. This instruction is often used to
compare two values without storing the result of the comparison.

2) Write an embedded C program to interface relay at pin number P0.18 of

LPC2148. Draw circuit diagram for the same

#include<lpc214x.h>

#define RELAY_PIN (1<<18)

void delay_ms(unsigned int ms) {

unsigned int i, j;
for(i=0; i<ms; i++) {
for(j=0; j<1000; j++) {
asm("NOP");
}
}
}

int main() {
IO0DIR |= RELAY_PIN; // set relay pin as output
while(1) {
IO0SET = RELAY_PIN; // turn on relay
delay_ms(1000); // wait for 1 second
IO0CLR = RELAY_PIN; // turn off relay
delay_ms(1000); // wait for 1 second
}
return 0;
}