JMS562

JMS562

SuperSpeed USB and eSATA Gen3

to
Dual SATA Gen3 Ports
Bridge

Preliminary Datasheet
Revision 1.0.1

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 1 Copying prohibited.
 JMS562

Revision History
Date
Version Revision Description
yyyy/mm/dd
1. Correct 1.1.1 typo
2. Add 1.3.3 description
3. Correct “XIN” description
1.0.1 2014/04/21 4. Correct “XOUT” description
5. Correct “VREG-IN” description
6. Correct “FB” description
7. Correct Reset Timing
1.0.0 2013/10/31 Release revision 1.0.0

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 2 Copying prohibited.
 JMS562

© Copyright JMicron Technology 2014.

All Rights Reserved.
Printed in Taiwan 2014
JMicron and the JMicron Logo are trademarks of JMicron Technology Corporation in Taiwan and/or other countries.
Other company, product and service names may be trademarks or service marks of others.

All information contained in this document is subject to change without notice. The products described in this
document are NOT intended for use implantation or other life supports application where malfunction may result in
injury or death to persons. The information contained in this document does not affect or change JMicron’s
product specification or warranties. Nothing in this document shall operate as an express or implied license or
environments, and is presented as an illustration. The results obtained in other operating environments may vary.

THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIEDE ON AN “AS IS” BASIS. In no event will
JMicron be liable for damages arising directly or indirectly from any use of the information contained in this
document.

JMicron Technology Corporation

1F, No.13, Innovation Road 1,
Hsinchu Science Park,
Hsinchu, Taiwan, R.O.C

For more information on JMicron products, please visit the JMicron website at
http://www.JMicron.com or send email to [email protected]

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 3 Copying prohibited.
 JMS562

Table of Contents

1. Overviews ............................................................................................................5
1.1 FUNCTION OVERVIEW ............................................................................5
1.1.1 FEATURES ..........................................................................................5
1.1.2 BLOCK DIAGRAM ...............................................................................6
1.2 SUPPORT DEVICES .................................................................................7
1.3 APPLICATION EXAMPLES .......................................................................7
1.3.1 USB 2.0, USB 3.0 and eSATA to 2 SATA Gen3 HDDs .........................7
1.3.2 USB 2.0 and USB 3.0 to three SATA Gen3 HDDs ................................7
1.3.3 USB 2.0, USB 3.0 and 2 eSATA to SATA Gen3 HDD ...........................8
2. Package Pin-Out ..................................................................................................9
2.1 PIN TYPE DEFINITION ...........................................................................10
2.2 PIN DESCRIPTION .................................................................................10
3. External SPI Flash..............................................................................................15
4. Clock & Reset.....................................................................................................16
4.1 Crystal input.............................................................................................16
4.2 Reset input ..............................................................................................16
5. Electrical Characteristics ....................................................................................17
5.1 Absolute Maximum Rating .......................................................................17
5.2 Recommended Power Supply Operation Conditions ...............................17
5.3 Recommended External Clock Source Conditions ..................................17
5.4 Power Supply DC Characteristics ............................................................18
5.4.1 USB2.0 to SATAx2 mode .................................................................18
5.4.2 USB3.0 to SATAx2 mode .................................................................19
5.5 I/O DC Characteristics .............................................................................19
5.6 Power-On Sequence ...............................................................................20
6. Internal Switch Regulator ...................................................................................22
7. Performance Benchmark ....................................................................................23
8. Package Dimension ...........................................................................................24

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 4 Copying prohibited.
 JMS562

1. Overviews
1.1 FUNCTION OVERVIEW

1.1.1 FEATURES

 Complies with Serial ATA International Organization: Serial ATA Revision 3.1
 Complies with Universal Serial Bus 3.0 Specification Revision 1.0
 Complies with USB Mass Storage Class Bulk-Only Transport (BOT) Rev. 1.0 Specification
 Complies with USB Attached SCSI Protocol (UASP) Rev. 1.0 Specification
 Supports USB Super-Speed/High-Speed/Full-Speed Operation
 Supports USB 2.0/USB 3.0 power saving mode
 Supports multi LUNs for USB 2.0/USB 3.0
 Supports port multiplier for eSATA
 Supports hardware RAID0 (striping) and RAID1 (mirror) over USB 2.0/USB 3.0/eSATA
 Flexible GPIOs for customized functions
 Provides a hardware control PWM
 Provides software utilities for downloading the upgraded firmware code under USB2.0/USB3.0/eSATA
 Design for Windows XP, Windows 7, Windows 8, MAC 10.3 or later versions
 30MHz external crystal
 An embedded 3.3V to 1.2V voltage regulator
 An embedded 5.0V to 3.3V voltage regulator
 QFN 76 package

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 5 Copying prohibited.
 JMS562

1.1.2 BLOCK DIAGRAM

USB 2.0 PHY

SATA Gen3
PHY
USB 2.0
USB 2.0 SATA MAC SATA Gen3
MAC
USB 3.0 PHY

SRAM
USB 3.0
USB 3.0 8051 SPI SPI Flash
MAC
SATA Gen3

SATA Gen3
PHY

PHY
eSATA 6G SATA MAC SATA MAC SATA Gen3
Switch VR

Peripheral
SRAM VIA ROM
Controller

JMS562

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 6 Copying prohibited.
 JMS562

1.2 SUPPORT DEVICES

 Hard disk drives

1.3 APPLICATION EXAMPLES

1.3.1 USB 2.0, USB 3.0 and eSATA to 2 SATA Gen3 HDDs

SATA Gen3
USB 2.0

USB 3.0
562
SATA Gen3
eSATA

1.3.2 USB 2.0 and USB 3.0 to three SATA Gen3 HDDs

SATA Gen3
USB 2.0

SATA Gen3
USB 3.0 562
SATA Gen3

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 7 Copying prohibited.
 JMS562

1.3.3 USB 2.0, USB 3.0 and 2 eSATA to SATA Gen3 HDD

USB 2.0

USB 3.0

SATA Gen3
eSATA
562
eSATA

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 8 Copying prohibited.
 JMS562

2. Package Pin-Out

AUX-REXT
S0_RXN
S1_RXN

S0_RXP
S1_RXP

S0_TXN
S1_TXN

S0_TXP
S1_TXP

AVDDH

AVDDH
AVDDL

AVDDL

AVDDL
AVDDL

XOUT
XIN
NC

NC
57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39
GPIO19 58 38 S2_RXP

GPIO18 59 37 S2_RXN

GPIO17/TACH-IN 60 36 AVDDL

GPIO9/D0 PWR CNTL 61 35 S2_TXN

VCCK 62 34 S2_TXP

VCCO 63 33 AVDDL

GPIO10/D0 ERR LED2 64 32 SSRXP

RST# 65 31 SSRXN

GPIO11/D0 ACT LED0 66 30 AVDDL

67 29 SSTXP

JMS562
TESTEN
VCCK 68 28 SSTXN

VREG-GND 69 27 AVDDH

VREG-GND

VREG-OUT

VREG-OUT
70

71

72
QFN 76 26

25

24
SSREXT

DP
DM

VREG-IN 73 23 LDO_3V_OUT

VREG-IN 74 22 LDO_5V_IN

FB 75 21 VCCK

VCCK 76 20 GPIO3/PWM
10

11

12

13

14

15

16

17

18

19
1

VBUS_SENSE

NC
GPIO7/S-SPI-CE

GPIO4/S-SPI-CK

GPIO2/P-SPI-CE
GPIO8/D1 PWR CNTL
GPIO0/UAI

VCCK

VCCK
GPIO5/S-SPI-SO

GPIO16/P-SPI-SO

GPIO13/P-SPI-SI

VCCK
GPIO6/S-SPI-SI

GPIO15/P-SPI-CK
GPIO14/D1 ERR LED3

GPIO12/D1 ACT LED1

GPIO1/UAO

VCCO

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 9 Copying prohibited.
 JMS562

2.1 PIN TYPE DEFINITION

Pin Type Definition

A Analog
D Digital
I Input
O Output
IO Bi-directional
S Internal Schmitt Trigger Circuit is used
L Internal weak pull-low (Max. 164K, Typical 96 K, Min. 61K)
H Internal weak pull-high (Max. 141K, Typical 93 K, Min. 66K)

2.2 PIN DESCRIPTION

Signal QFN 76 Type Description

Name

Serial ATA interface

SATA Port RX+ Signal.
S0_RXP 45 AI A 10nF capacitor should be connected between this pin and
SATA connector.
SATA Port RX- Signal.
S0_RXN 46 AI A 10nF capacitor should be connected between this pin and
SATA connector.
SATA Port TX+ Signal.
S0_TXP 49 AO A 10nF capacitor should be connected between this pin and
SATA connector.
SATA Port TX- Signal.
S0_TXN 48 AO A 10nF capacitor should be connected between this pin and
SATA connector.
SATA Port RX+ Signal.
S1_RXP 51 AI A 10nF capacitor should be connected between this pin and
SATA connector.
SATA Port RX- Signal.
S1_RXN 52 AI A 10nF capacitor should be connected between this pin and
SATA connector.
SATA Port TX+ Signal.
S1_TXP 55 AO A 10nF capacitor should be connected between this pin and
SATA connector.
SATA Port TX- Signal.
S1_TXN 54 AO A 10nF capacitor should be connected between this pin and
SATA connector.
SATA Port RX+ Signal.
S2_RXP 38 AI A 10nF capacitor should be connected between this pin and
SATA connector.

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 10 Copying prohibited.
 JMS562

Signal QFN 76 Type Description

Name
SATA Port RX- Signal.
S2_RXN 37 AI A 10nF capacitor should be connected between this pin and
SATA connector.
SATA Port TX+ Signal.
S2_TXP 34 AO A 10nF capacitor should be connected between this pin and
SATA connector.
SATA Port TX- Signal.
S2_TXN 35 AO A 10nF capacitor should be connected between this pin and
SATA connector.
External Reference Resistance.
REXT 43 AI
A 12K1% external resistor should be connected to this pin.
USB 3.0 interface

SSRXP 32 AI Super Speed RX+ Signal.

SSRXN 31 AI Super Speed RX- Signal.
Super Speed TX+ Signal.
SSTXP 29 AO A 100nF capacitor should be connected between this pin and
USB connector.
Super Speed TX- Signal.
SSTXN 28 AO A 100nF capacitor should be connected between this pin and
USB connector.
External Reference Resistance.
SSREXT 26 AI
A 12K1% external resistor should be connected to this pin.

USB 2.0 interface

DM 24 AIO USB 2.0 Bus D- Signal.

DP 25 AIO USB 2.0 Bus D+ Signal.
5V to 3.3V LDO Power Input.
LDO_5V_IN 22 AI This pin should be connected to the 5V input or USB
connector 5V.
Capacitance for internal LDO of USB 2.0.
LDO_3V_ A capacitance to ground is recommended on this pin. The
23 AO value should be 1uF.
OUT
The output voltage range is 3.3V±10%.

VBUS_ USB 2.0/USB 3.0 Cable Power Input

16 AI
SENSE This pin should be connected to USB connector 5V.

Crystal Interface
Crystal Input/Oscillator Input.
It is connected to a 30MHz crystal or crystal oscillator. The
XIN 42 AI variation range should be ±30ppm. And the input voltage
should range in 3.3V±5%.

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 11 Copying prohibited.
 JMS562

Signal QFN 76 Type Description

Name
Crystal Output.
It is connected to a crystal. While crystal oscillator is applied,
XOUT 41 AO this pin should be reserved as No Connection (NC). The
output variation range is around ±30ppm (input dependent).
And the output voltage range is 3.3V±5% (input dependent).

Switching Regulator

VREG-GND 69,70 AI Switching Regulator Ground.

Switch Output Pin.

VREG-OUT 71,72 AO
An external inductor should be connected to this pin.

VREG-IN 73,74 AI Switching Regulator 3.3V Power Supply.

FB 75 AI Feedback pin which is connected to 1.2V core voltage.

Control and GPIOs

System Global Reset Input.

Active-low to reset the entire chip.
RST# 65 DIS
An external RC should be connected to this pin. Please refer
to the following section for detailed description.
MP Test Mode Enable.
TESTEN 67 DIS This pin is reserved for IC mass production testing.
Please set this pin to low under normal operation.
8051 UART Input / GPIO [0].
GPIO[0] 3 DIOH
This pin only preserves for UART function.
8051 UART Output / GPIO [1].
This pin can be programmed by customized firmware and
GPIO[1] 1 DIOH
also be programmed to the UART interface by customized
firmware.
Primary Serial Flash (CE) / GPIO [2]
GPIO[2] 18 DIOH This pin only preserves for SPI chip enable.

GPIO [3].
GPIO[3] 20 DIOH
This pin only preserves for FAN function.
Secondary Serial Flash (SCK) / GPIO [4]
GPIO[4] 7 DIOH This pin can be programmed as special function or normal
GPIO function.
Secondary Serial Flash (SO) / GPIO [5]
GPIO[5] 6 DIOH This pin can be programmed as special function or normal
GPIO function.
Secondary Serial Flash (SI) / GPIO [6]
GPIO[6] 2 DIOH
This pin only preserves for UART function.
Secondary Serial Flash (CE) / GPIO [7]
GPIO[7] 5 DIOH This pin can be programmed as special function or normal
GPIO function.

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 12 Copying prohibited.
 JMS562

Signal QFN 76 Type Description

Name

GPIO [8].
GPIO[8] 8 DIOH
This pin only preserves for enable hard drive power.
GPIO [9].
GPIO[9] 61 DIOH
This pin only preserves for enable hard drive power.
GPIO [10].
GPIO[10] 64 DIOH
This pin can be programmed by customized firmware.
GPIO [11].
GPIO[11] 66 DIOH
This pin can be programmed by customized firmware.
GPIO [12].
GPIO[12] 11 DIOH
This pin can be programmed by customized firmware.
Primary Serial Flash (SI) / GPIO [13]
GPIO[13] 15 DIOH This pin can be programmed as special function or normal
GPIO function.
GPIO [14].
GPIO[14] 9 DIOH
This pin can be programmed by customized firmware.
Primary Serial Flash (SCK) / GPIO [15]
GPIO[15] 13 DIOH This pin can be programmed as special function or normal
GPIO function.
Primary Serial Flash (SO) / GPIO [16]
GPIO[16] 14 DIOH This pin can be programmed as special function or normal
GPIO function.
GPIO [17].
GPIO[17] 60 DIOH
This pin only preserves for FAN function.
GPIO [18].
GPIO[18] 59 DIOH
This pin can be programmed by customized firmware.
GPIO [19].
GPIO[19] 58 DIOH
This pin can be programmed by customized firmware.

Power and Ground

VCCO 10,63 P Digital I/O Power Supply.

4,12, 17
VCCK 21, 62, 68 P Digital Core Power Supply.
76

AVDDH 27,40, 50 P Analog I/O Power Supply.

30, 33, 36
AVDDL 44, 47, 53 P Analog Core Power Supply.
56

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 13 Copying prohibited.
 JMS562

Signal QFN 76 Type Description

Name

Other

NC 19,39, 57 -- Not Connected or Connected to Ground.

LED Indicator
If user has an application for LED function, please contact JMicron’s AE before PCB layout.

GPIO initial value

All GPIOs set as input mode with pull-high resistor while in reset.

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 14 Copying prohibited.
 JMS562

3. External SPI Flash

Vendor Name Model Name Comment
MXIC 25L400 1E
MXIC 25L4005 AMC
MXIC 25L1605 DM2I
MXIC 25L8005 MC
MXIC 25L4006E
MXIC 25L8006E
MXIC 25L8035E
AMIC A25L040M-F
AMIC A25L016M-F
AMIC A25L032M-F
Winbond W25X40BLSNIG
Winbond 25X40CLNIG
Winbond 25Q80BLNIG
Winbond 25X40CLVIG
Giga Device 25Q40T
vpowerwins FM25F04
ESMT F25L04PAG1SM

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 15 Copying prohibited.
 JMS562

4. Clock & Reset

4.1 Crystal input

Single crystal input at 30MHz is needed.

4.2 Reset input

The reset input pin is the Schmitt trigger input pin. All functions will be initialized by reset except the
Analog Power-On Reset Circuit depending on the Power on-off.

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 16 Copying prohibited.
 JMS562

5. Electrical Characteristics
5.1 Absolute Maximum Rating

Parameter Symbol Condition Min Max Unit

Digital I/O power supply VCCO(ABS) -0.3 3.47 V
Digital core power supply VCCK(ABS) -0.3 1.26 V
Analog I/O power supply AVDDH(ABS) -0.3 3.47 V
Analog core power supply AVDDL(ABS) -0.3 1.26 V
USB VBUS power supply VBUS -0.3 5.5 V
Digital I/O input voltage VI(D) -0.3 3.47 V
o
Storage Temperature TSTORAGE -40 150 C

5.2 Recommended Power Supply Operation Conditions

Parameter Symbol Condition Min Typical Max Unit

Digital I/O power supply VCCO 3.13 3.3 3.47 V
Digital core power supply VCCK 1.14 1.2 1.26 V
Analog I/O power supply AVDDH 3.13 3.3 3.47 V
Analog core power supply AVDDL 1.14 1.2 1.26 V
Digital I/O input voltage VI(D) 0 3.3 3.47 V
o
Ambient operation temperature TA 0 70 C
o
Junction Temperature TJ -40 125 C

5.3 Recommended External Clock Source Conditions

Parameter Symbol Condition Min Typical Max Unit

External reference clock 30 MHz
Clock Duty Cycle 45 50 55 %

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 17 Copying prohibited.
 JMS562

5.4 Power Supply DC Characteristics

The maximum and minimum values are measured at the max and min power supply levels respectively.

5.4.1 USB2.0 to SATAx2 mode

@S0 state

Parameter Symbol Condition Min Typical Max Unit

VCCO and
3.3V power supply Operate @3.3V 40.6 47.9 55.1 mA
ACDDH
VCCK and
1.2V power supply Operate @1.2V 315.5 319.6 323.1 mA
AVDDL

@S4 state

Parameter Symbol Condition Min Typical Max Unit

VCCO and
3.3V power supply Operate @3.3V 18.5 18.6 18.6 mA
ACDDH
VCCK and
1.2V power supply Operate @1.2V 207.8 209.1 210.0 mA
AVDDL

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 18 Copying prohibited.
 JMS562

5.4.2 USB3.0 to SATAx2 mode

@U0 state

Parameter Symbol Condition Min Typical Max Unit

VCCO and
3.3V power supply Operate @3.3V 44.9 53.1 60.3 mA
ACDDH
VCCK and
1.2V power supply Operate @1.2V 437.8 439.3 441.4 mA
AVDDL

@U3 state (suspend @S4)

Parameter Symbol Condition Min Typical Max Unit

VCCO and
3.3V power supply Operate @3.3V 28.4 28.4 28.4 mA
ACDDH
VCCK and
1.2V power supply Operate @1.2V 324.4 325 325.6 mA
AVDDL

5.5 I/O DC Characteristics

Parameter Symbol Condition Min Typical Max Unit

Input low voltage VIL 0.7 V
Input high voltage VIH 1.5 V
Output low voltage VOL 0.3 V
Output high voltage VOH 1.9 V

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 19 Copying prohibited.
 JMS562

5.6 Power-On Sequence

The Power-On sequence rules are defined in this section. Designers should follow all the rules for
external power designs. Detailed explanations are listed as below.
T1

VCCO

2.0V

T3

T2 VCCK

0.88V

T4

RST#

2.0V

T5

T1: Rise time for 3.3V power rail from 0.0V to 3.3V
T2: Rise time for 1.2V power rail from 0.0V to 1.2V
T3: Rise time for 3.3V power rail from 0.0V to 2.0V
T4: Rise time for 1.2V power rail from 0.0V to 0.88V
T5: Rise time for RST# signal from 0.0V to 2.0V

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 20 Copying prohibited.
 JMS562

The recommended power sequence and timing requirements are listed as below.

Time Minimum Maximum

T1 0.0 ms 10 ms
T2 0.0 ms 10. ms
T3 0.0 ms 8 ms
T4 0.0 ms 8 ms
T5 100 ms 500 ms

The RESET timing constrain is based on the external RC reset circuits. In order to control the charge
and discharge time for RC circuits, minimum and maximum requirements are listed. If designers apply
timing control chip to control the reset signal, the only requirement will be minimum value. In other
words, the maximum value can be skipped without problems.

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 21 Copying prohibited.
 JMS562

6. Internal Switch Regulator

Input Voltage Range: 2.375V ~ 5.500V
Output Voltage Range: 1.0V ~ 1.4 (programmable)
Output Voltage Accuracy : ILOAD= 650mA, VOUT±10%
Max. Output Current : 650mA
Over-Current Protection (OCP): Yes (1,500mA)
Output Capacitor: 20uF
Output Inductor: 3.3uH
Start-up Time : < 1.5 ms
Thermal Shutdown: No
Faster Shutdown: No

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 22 Copying prohibited.
 JMS562

7. Performance Benchmark
USB3.0 UAS Performance 400 MB/s
USB2.0 UAS Performance 42 MB/s

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 23 Copying prohibited.
 JMS562

8. Package Dimension

 QFN 76 9x9 mm2

Revision 1.0.1
© JMicron 2014. All rights reserved. Page 24 Copying prohibited.