Albert P. Malvino Jerald A Brown
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Zlatko PentekAlbert P. Malvino Jerald A Brown
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Zlatko Pentek| 32 [ | LL More LOGIC GATES ‘This chapter introduces NoR and NAND gates, devices that are widely used in industry. You will also learn about De Morgan's theorems: they help you to rearrange and simplify logic circuits 3-1 NOR GATES “The Nor gate has two or more input signals but only one ‘output signal. Al inputs must be low to get a high output In other words, the Nok gate recognizes only the input word whose bits are all 0s. ‘Two-Input Gate Figure 3-Ia shows the logical structure of a NoR gate, which is an on gate followed by an inverter. Therefore, the final output is NOT the OR of the inputs. Originally called a NoT-OR gate, the circuit is now referred to as a NOR gate. Figure 3-1b is the standard symbol for a NOR gate, Notice that the inverter triangle has been deleted and the smalt circle or bubble moved to the ox-gate output. The bubble is a reminder of the inversion that follows the oRing With Fig. 3-1a and b the following ideas are clear. If both inputs are low, the final output is high. If one input is low and the other high, the output is low. And if both inputs are high, the output is low Table 3-1 summarizes the circuit action. As you see, the [Nok gate recognizes only the input word whose bits are all 0s, In other words, all inputs must be low to get a high output 32 TABLE 3-1. TWO- INPUT Nor GATE, > A+B 0 0 eee |e dentally, the boolean equation for a 2-input NOR gate y=A4B BD Read this as “Y equals Nor A ox B.”” If you use this equation, remember that the oring is done first, then the to a ‘oR gates: (a) input (b) 4-inpu. Three-Input Gate Regardless of how many inputs a NOR gate has, it is still logically equivalent to an ox gate followed by an inverter For instance, Fig. 3-2a shows a 3-input Nor gate. The 3 inputs are ORed, and the result is inverted. Therefore, the boolean equation is Y=AFBTC 2) The analysis of Fig. 3-22 goes like this. If all inputs are low, the result of oning is low; therefore, the final output ‘TABLE 3-2. THREE-INPUT Nor GATE ae cl aeBee 000 1 oor o On ° gl ° 100 0 to 0 ii 0 o tia 0 is high. If one or more inputs are high, the result of oning is high; so the final output is low. Table 3-2 summarizes the action of a 3-input Now gate As you see, the circuit recognizes only the input word whose bits are 0s. In other words, all inputs must be low to get a high output. Four-Input Gate Figure 3-2 is the symbol for a 4-input Nor gate. The ‘inputs are ORed, and the result is inverted. For this reason, the boolean equation is Y¥=AFB+CFD G3) ‘The corresponding truth table has input words from 0000 to 1111. Word 0000 gives a 1 output; all other words produce a 0 output. (For practice, you should construct the truth table of the 4-input NoR gate.) 3-2 DE MORGAN'S FIRST THEOREM Most mathematicians ignored boolean algbebra when it first appeared; some even ridiculed it. But Augustus De Morgan saw that it offered profound insights. He was the first to acclaim Boole’s great achievement. Always a warm and likable man, De Morgan himself hhad paved the way for boolean algebra by discovering two important theorems. This section introduces the first theo- The First Theorem Figure 3-3a is « 2-input Nor gate, analyzed earlier. As you recall, the boolean equation is AB and Table 3-3 is the truth table. Fig. 3-3 De Morgan's fist theorem: (a) Now gate; (b) awe gate with inverted inputs, Figure 3-3b has the inputs inverted before they reach the AND gate, Therefore, the boolean equation is y=4B 1 both inputs are Jow in Fig. 3-35, the AND gate has high inputs; therefore, the final output is high. If one or more inputs are high, one or more AND-gate inputs must be low and the final output is low. Table 34 summarizes these ideas. TABLE 3-3 TABLE 34 Compare Tables 3-3 and 3-4. They're identical. This ‘means that the two circuits are logically equivalent; given the same inputs, the outputs are the same. In other words, the circuits of Fig. 3-3 are interchangeable. De Morgan discovered the foregoing equivalence long before logic circuits were invented. His first theorem says AYB B G4) ‘The left member of this equation represents Fig. 3-3a: the right member, Fig. 3-3b, Equation 3-4 says that Fig. 3-34 and b are equivalent (interchangeable) Bubbled ano Gate Figure 3-4a shows an AND gate with inverted inputs. This circuit is so widely used that the abbreviated logie symbol of Fig. 3-46 has been adopted. Notice that the inverter triangles have been deleted and the bubbles moved to the Chapter 3 More Logic Gates 3B Fig. 3-4 xp gate with inverted inputs: (a) cireit (B) abbreviated symbol. AND-gate inputs, From now on, we will refer to Fig. 3-46 as a bubbled AND gare; the bubbles are a reminder of the inversion that takes place before aNDing. q>— - =D- 345 De Morgan's first theorem, Figure 3-5 is a graphic summary of De Morgan's first theorem. A nok gate and a bubbled AND gate are equivalent. AAs shown later, because the circuits are interchangeable, you can often reduce complicated logic circuits to simpler forms. More than Two Inputs When 3 inputs are involved, De Morgan’s first theorem is written AFB +C=ABC (3-5) For 4 inputs A¥BSCFD (3-6) In both cases, the theorem says that the complement of a suum equals the product of the complements Fig. 3-6 De Morgan’s first theorem: (a) 3-input eiruits: (b) 4 input circuits B4 Digital Computer Electronics Here’s what really counts. Equation 3-5 says that a 3- input Nor gate and a 3-input bubbled aNb gate are equivalent (see Fig. 3-6a), Equation 3-6 means that a 4-input NOR gate and a 4-input bubbled AND gate are equivalent (Fig. 3-6b), Memorize these equivalent circuits; they are a visual statement of De Morgans first theorem. [Notice in Fig. 3-6 how the input edges of the NOR gate land the bubbled aND gate have been extended. This is ‘common drafting practice when there are many input signals. ‘The same idea applies to any type of gate. EXAMPLE 3-1 Prove that Fig. 3-7a and are equivalent. p> p> a we Fig. 3:7 Equivalent De Morgan circuit. SOLUTION ‘The final Nor gate in Fig, 3-7a is equivalent to a bubbled AND gate, This allows us to redraw the circuit as shown in Fig. 3-76, ‘Double inversion produces noninversion; therefore. cach double inversion in Fig. 3-7b cancels out, leaving the simplified citcuit of Fig. 3-7e. Figure 37a and ¢ are therefore equivalent Remember the idea. Given a logic circuit, you can replace any NOR’ gate by a bubbled AND gate. Then any double inversion (a pair of bubbles in a series path) cancels out ‘Sometimes you wind up with a simpler logic circuit than you started with; sometimes not. ‘But the point remains. De Morgan's first theorem enables you to rearrange a logic circuit with the hope of finding a ‘simpler equivalent cigcuit or perhaps getting more insight into how the original circuit works, 3-3 NAND GATES ‘The NAND gate has two or more input signals but only one ‘output signal. All input signals must be high to get a low ‘output —D o—t 9 Fig, 3-8 sano gate: (a) logical meaning; (b) standard symbol. ‘Two-Input Gate Figure 3-8a shows the logical structure of a NAND gate, an AND gate followed by an inverter. Therefore, the final ‘output is NoT the AND of the inputs. Originally called a NOT-AND gate, the circuit is now referred to as @ NAND gate Figure 3-8b is the standard symbol for a NAND gate, The inverter triangle has been deleted and the bubble moved to the aND-gate output. If one or more inputs are low, the result of aNDing is low; therefore, the final inverted output is high. Only when all inputs are high docs the ANDing produce a high signal; then the final output is low. Table 3-5 summarizes the action of a 2-input NAND gate. As shown, the NAND gate recognizes any input word with ‘one or more 0s. That is, one or more low inputs produce «high output. The boolean equation for a 2-input NAND gate is y= on Read this as “Y equals Nor AB.” If you use this equation, remember that the aNDing is done first then the inversion Fig, 3.9 Nano gates: (a) input; () input. ‘Three-Input Gate Regardless of how many inputs a NAND gate has, it's still logically equivalent to an AND gate followed by an inverter. For example, Fig. 3-9a shows a 3-input NAND gate, The inputs are ANDed, and the product is inverted. Therefore, the boolean equation is Y = FBC G8) Here is the analysis of Fig. 3-94. If one or more inputs are low, the result of anbing is low; therefore, the final output is high, If all inputs are high, the aNbing gives high signal; so the final output is low Table 3-6 is the truth table for a 3-input NAND gate. As indicated, the circuit recognizes words with one or more Os. This means that one or more low inputs produce a high output. TABLE 3.5, TABLE 3-6. THREE- TWO-INPUT INPUT NaNb GATE, NaNb GATE AB C| ABC A B| AB —— = Oo Ot oot oor] ot orf a o1ol| 1 rol t ord} ot Lalo roo} t a oe fi ole i Laiilo Four-Input Gate Figure 3-96 is the symbol for a 4-input NaNp gate, The inputs are ANDed, and the result is inverted. Therefore, the boolean equation is y = ABCD a9 If you construct the truth table, you will have input words from 0000 to 1111. All words from 0000 through 1110 Produce & 1 output; only the word L111 gives 2 0 output 3-4 DE MORGAN'S SECOND THEOREM ‘The proof of De Morgan’s second theorem is similar to the proof given for the first theorem. What follows is a brief explanation, ‘The Second Theorem ‘When two inputs are used, De Morgan's second theorem says that AB=R+8 G-10) In words, the complement of a product equals the sum of the complements. The eft member of this equation repre Sents a NAND gate (Fig. 3-10a); the right member stands > 0 Fig, 3-10 De Morgan's second theorem: (a) NAND gate: (b) 0% {gate with inverted inputs: (c) bubbled oR gate Chapter 3 More Logic Gates 3B for an on gate with inverted inputs (Fig, 3-10b). Therefore, De Morgan's second theorem boils down to the fact that Fig, 3-10a and 6 are equivalent EXAMPLE 3-2 Prove that Fig. 3-13a and c ate equivalent aD - 4 Fig. 3-11 De Morgan's second theorem, Bubbled on Gate ‘The circuit of Fig. 3-10b is so widely used that the abbreviated logic symbol of Fig. 3-10c has been adopted. From now on we will refer to Fig. 3-10c as a bubbled ow ‘gate; the bubbles are a reminder of the inversion that takes place before oRing. Figure 3-11 isa visual statement of De Morgan's second theorem: a NAND gate and a bubbled oR gate are equivalent. This equivalence allows you to replace one circuit by the other whenever desired. This may lead to a simpler logic circuit or give you more insight into how the original circuit works, More than Two Inputs ‘When 3 inputs are involved, De Morgan's second theorem is written ABC =A +B+C Gin 1-4 inputs are used, ABCD = 4+8+E+D (3-12) ‘These equations say that the complement of a product equals the sum of the complements. oe o » Fig, 3-12 De Morgan’s second theorem: (a) 3-input circuits () input circuits Figure 3-12 is a visual summary of the second theorem. Whether 3 or 4 inputs are involved, a NAND gate and a bubbled on gate are equivalent (interchangeable) 3G Digital Computer Electronics Ln oo we Fig. 3:13 Equivalent circuits, SOLUTION Replace the final NAND gate in Fig. 3-13a by a bubbled or gate. This gives Fig. 3-13b. The double inversions cancel out, Ieaving the simplified circuit of Fig. 3-13c. Figure 3-13a and c are therefore equivalent. Driven by the same inputs, either circuit produces the same output as the other. So if you're loaded with NaND gates, build Fig. 3-134. If four Shelves are full of AND and OR gates, build Fig 3-13¢ Incidentally, most people find Fig. 3-13b easier to analyze than Fig. 3-13a, For this reason, if you build Fig. 3-134, draw the circuit like Fig. 3-136. Anyone who sees Fig 3-13) on a Schematic diagram knows that the bubbled oR gate isthe same as a NAND gate and that the built-up circuit is (Wo NAND gates working into a NAND gate. EXAMPLE 3-3 Figure 3-14 shows a circuit called a control matrix. At frst, it looks complicated, but on closer inspection its relatively simple because ofthe repetition of NAND gates. De Morgan's theorem tells us that NAND gates driving NAND gates are coquivalent to AND gates driving oR gates. ‘The upper set of inputs T; t0 Tare called timing signals, conly one of them is high at a time. 7, goes high first, then Tz, then Ts, and so on, These signals control the rate and sequence of computer operations. The lower set of inputs LDA, ADD, SUB, and OUT are ‘computer instructions; only one of them is high at a time. The outputs Cy, Ep. Lys ---+ 10 Lo control different registers in the computer. ‘Answer the following questions about the control matrix: 2. Which outputs are high when 7, is high? b. IFT, and LDA are high, which outputs are high? cc. When T, and SUB are high, which outputs are high? i+# | F “Tate ret YOY 4 & fe ty fp 3414 Control matrix, SOLUTION a. Visualize T, high. You can quickly check out each gate and realize that Ey and Ly are the only high outputs b. This time T, and LDA are high, Check each gate and you can see that L,, and F; are the only high outputs, ¢. When 7, and SUB are high, the high outputs are Z,, Sis and Ey 3-5 EXCLUSIVE-OR GATES ‘An ok gate recognizes words with one or more Is. The EXCLUSIVE-OR gate is different; it recognizes only words that have an odd number of Is. ‘Two Inputs Figure 3-15a shows one way to build an EXCLUSIVE-oR gate, abbreviated xoR. The upper AND gate forms the product AB, and the lower AND gate gives AB. Therefore, the Boolean equation is v= 7B + AB G13) vy wens ‘or Fig. 3-18 (a) exctusive-ok gate. (b) A 2-input ExcLUSWE-OR ate, Here's what the circuit does. In Fig. 3-15a two low inputs mean both AND gates have low outputs; so the final ‘output is low. If A is low and B is high, the upper AND. gate has a high output; therefore, the final output is high Likewise, a high A and low B result in a final output that js high. If both inputs are high, both aNp gates have low ‘outputs and the final output is low. Table 3-7 shows the truth table for a 2-input EXCLUSIVE. ‘on gate. The output is high when A or B is high but not both; this is why the circuit is known as an EXCLUSIVE-OR ‘gate. In other words, the output is a | only when the inputs are different Chapter 9 More Logic Gates. 37 TABLE 3-7. TWO- INPUT xor GATE ———— AB! AB+ AB oo 0 L I L 0 I Logic Symbol and Boolean Sign Figure 3-15b is the standard symbot for a 2-input XoR gate. ‘Whenever you sce this symbol, remember the action: the inputs must be different to get a high output ‘A word equation for Fig. 3-15b is y Axor B Gy) In boolean algebra the sign @ stands for xoR addition ‘This means that Eq. 3-14 can be written Y=A@B GS) Read this as “Y equals A xo B.” Given the inputs, you can substitute and solve for the output, For instance, if both inputs are low, y=0@0=0 because xoRed with O gives 0. If one input is low and the other high, =0@1=1 because 0 xored with I produces 1. And so on. Here's a summary of the four possible xoR additions: 0@0 0 1 I ©008 1 D0 1 Remember these four results; we will be using xOR addition when we get fo arithmetic circuits Four Inputs In Fig. 3-164 the upper gate produces A @ B, while the lower gate gives C @ D. The final gate xoxs both of these ‘sums to get A®HOCOD G16) 38 Digital Computer Electronics or Fig. 316 A 4input exciusive-on gate: (a) circuit with 2-input OR gates (b loge symbol. It’s possible to substitute input values into the equation and solve for the output. For instance, if A through C are low and D is high, = 0@9@0@V o@! =1 ‘One way to get the truth table is to plow through all the input possibilities. ‘Alternatively, you can analyze Fig. 3-16a as follows. If all inputs are Os, the fist two gates have O outputs; so the final gate has a 0 output, If A to Care Os and D is a 1, the ‘upper gate has a 0 output, the lower gate has a 1 output, and the final gate has @ 1 output, In this way, you can analyze the circuit action for all input words. Table 3-8 summarizes the action, Here is an important property: each input word with an odd number of Is produces a I output. For instance, the first input word to produce a I output is 0001; this word has an odd number of Is, The next word with a 1 output is 0010; again an odd number of Is. A 1 output also occurs for these words: 0100, 111, 1000, 1011, 1101, and 1110, all of which have an odd number of 1s. ‘The circuit of Fig. 3-16a recognizes words with an odd number of 1s; it disregards words with an even number of 1s, Figure 3-16a is a 4-input xOR gate, In this book, we will use the abbreviated symbol of Fig. 3-16b to represent 4a 4-input xor gate. When you see this symbol, remember the action: the circuit recognizes words with an odd number of Is. Any Number of Inputs Using 2-input xo gates as building blocks, we can make XOR gates with any number of inputs. For example, Fig. TABLE 3-8. FOUR-INPUT xor GATE, Comment A Even | 0 oad 0 aa 0 Even | 0 oad 0 Even | 0 Even | 0 Odd 0 oad 1 Even 1 Even I Odd 1 Even 1 oud 1 owe 1 Even 1 ee-e--e [| Hono-e-cH o-oo ols a 0 0 1 1 o 0 1 _ o 0 1 1 0 0 1 1 = a>)- » Fig. 317 xox gates: (a) input; (>) 6input. 3:17a shows the abbreviated symbol fora 3-input xoR gate, and Fig. 3-176 is the symbol for a 6-input xoR gate. The final output of any XOR gate is the XoR sum of the inputs: Y=Aa@B@c Gn What you have to remember for practical work is ths: fan XOR gate, no matter how many inputs, recognizes only ‘words with an odd number of Is. Parity Even parity means a word has an even number of 1s. For instance, 110011 has even parity because it contains four Is, Odd parity means a word has an odd number of Is. As ‘an example, 110001 has odd parity because it contains thre Is, Here are two more examples: 11110000 1111 0011 1111 0000 1111 0111 (Even parity) (Odd parity) The first word has even parity because it contains ten Is; the second word has odd parity because it contains eleven Is. XOR gates are ideal for testing the parity of a word, XoR {gates recognize words with an odd number of Is. Therefore, ceven-parity words produce a low output and odd-parity words produce a high output EXAMPLE 3-4 ‘What is the output of Fig. 3-18 for each of these input words? a. 1010 1100 1000 1100, b. 1010 1100 1000 F101 00 ig. 318 Odd-paity tester. SOLUTION a. The word has seven Is, an odd number. Therefore, the output signal is opp =1 . The word has eight Is, an even number. Now opp =0 This is an example of an odd-party tester. An even- Parity word produces a low output. An odd-parity word results in a high output. EXAMPLE 3-5 The 7-bit register of Fig. 3-19 stores the leter A in ASCIL form. What does the 8-bit output word equal”? Chapter 3 More Logic Gates. 39 oe Inaction or ta ite ‘ot word wth odd write Fig. 3:19 Oud-parity generator. SOLUTION ‘The ASCII code for letter A is 100 0001, (see Table 1-6 for the ASCH code). This word has an even parity, which means that the XOR gate has a 0 output Because of the inverter, the overall output of the circuit is the 8-bit word 1100 0001 Notice that this has odd parity. ‘The circuit is called an odd-parity generator because it produces an 8-bit output word with odd party. If the register ‘word has even parity, 0 comes out of the XOR gate and the codd-parity bit is 1. On the other hand, if the register word hhas odd parity, a I comes out of the XOR gate and the odd- party bit is 0. No matter what the register contents, the ‘odd-parity bit and the register bits form a new 8-bit word that has odd parity ‘What is the practical application? Because of transients, noise, and other disturbances, [-bit errors sometimes occur in transmitted data. For instance, the letter A may be transmitted over phone lines in ASCH form: 100.0001 (A) Somewhere along the line, one of the bits may be changed. Ifthe X, bit changes, the received data will be 1000011) 40 Digital Computer Electronics Because of the I-bit error, we receive letter C when letter A was actually sent. One solution is to transmit an odd-parity bit along with the data word and have an xOR gate test each received ‘word for odd parity. For instance, with a circuit ike Fig. 3-19 the letter A would be transmitted as 1100 0001 ‘An xOr gate will test this word when it is received. If no error has occurred, the Xor gate will recognize the word. On the other hand, if a I-bit error has crept in, the XOR gate will disregard the received word and the data can be rejected. ‘A final point, When errors come, they are usually 1-bit errors, This is why the method described catches most of the errors in transmitted data EXAMPLE 3-6 What does the circuit of Fig. 3-20 do? y Fig. 3:20 SOLUTION When INVERT = 0 and A = 0, y=0@0=0 When INVERT = 0 and A y=0@1=1 In either case, the output is the same as A; that is, y=A for a low INVERT signal (On the other hand, when INVERT = 1 and A y When INVERT = 1 and A = 1, y This time, the output is the complement of A. As an equation, y=A for a high INVERT signal ‘To summarize, the circuit of Fig. 3-20 does either of two things. It transmits 4 when [VERT is 0 and A when INVERT is 1. 3-6 THE CONTROLLED INVERTER ‘The preceding example suggests the idea of a controlled inverter, a circuit that transmits a binary word or its I's complement. The 1' Complement ‘Complement each bit in a word and the new word you get is the 1s complement. For instance, given 1100 O11 the 1’s complement is 011 1000 Each bit in the original word is inverted to get the I's complement The Cireuit The xoR gates of Fig. 3-21 form a controlled inverter (sometimes called a programmed inverter). This circuit can transmit the register contents or the 1's complement of the register contents. As demonstrated in Example 3-6, cach XOR gate acts like this. A low INVERT results in and a high INVERT gives So each bit is either transmitted or inverted before reaching the final output. Visualize the register contents as a word AAs © + Ap and the final output as a word YY, ** » Yo. Then a low INVERT means Yao ++ Yo = Arg = Ay (On the other hand, a high INVERT results in YoYo" * + Yo = Avy As « concrete example, suppose the register word is ADAgs ++ Ay = L110 0110 ‘Then, & low INVERT gives an output word of Yi¥q" ++ Yo = 110 0110 and a high INVERT produces Yi¥e* ++ Yo = 0001 1001 The controlled inverter of Fig, 3-21 is important, Later ‘you will see how it is used in solving arithmetic and logic problems. For now, all you need to remember is the key idea. The output word from a controlled inverter equals the + bene +3 x = y % Ve 3-21 Controlled inverter Chapter $ More Logic Gates 41 input word when INVERT is low; the output word equals the I's complement when INVERT is high. Boldface Notation After you understand an idea, it simplifies discussions and equations if you use a symbol, letter, or other sign to represent the idea, From now on, boldface letters will stand for binary words. For instance, instead of writing Aye* ++ Ay = 1110 0110 wwe can write A= 11100110 Likewise, instead of Yr¥e° + Yp = 0001 1001 the simpler equation Y = 0001 1001 ccan be used. ‘This is another example of chunking. We are replacing long strings like AyA, +» * Ay and YY, >» Yo by A and Y. This chunked notation will be convenient when we get to computer analysis. ‘This is how to summarize the action of a controlled inverter: ‘A when INVERT = 0 when INVERT = | (oie: A boldface leter with an overbar means that each bit in the word is complemented: if A is a word, A is its 1's complement.) 3-7 EXCLUSIVE-NOR GATES ‘The EXCLUSIVE-NOR gate, abbreviated xNOR, is logically equivalent to an xoR gate followed by an inverter. For example, Fig. 3-22a shows a input xNoR gate, Figure 3-226 is an abbreviated way to draw the same circuit Opt dpb Fig. 322 A2-inputxvon gate: (a) citcuit;(b) abbreviated symbol 42> digital Computer Electronics TABLE 3.9. TWO-INPUT xNOR GATE, ecole -e-e|s| Jree-|= Because of the inversion on the output side, the truth table of an xNOR gate is the complement of an XO truth table, As shown in Table 3-9, the output is high when the inputs are the same. For this reason, the 2-input NOR gate is ideally suited for bie comparison, recognizing when two input bits are identical. (Example 3-7 tells you more about bit comparison.) aD o w Fig. 3:23 xvoR gates (a) 3+nput; (b) input Figure 3-23a is the symbol for a 3-input xox gate, and Fig. 3-23bis the d-input xo gate. Because ofthe inversion ‘on the output side, these XNOR gates perform the comple- mentary function of xox gates. Instead of recognizing odd- parity words, xNoR gates recognize even-parity words. EXAMPLE 3-7 What does the circuit of Fig. 3-24 do? SOLUTION ‘The citeuitis a word comparator: it recognizes two ident words. Here is how it works. The leftmost XNOR gate compares A, and By; if they are the same, ¥ is a 1. The second XNOR gate compares A, and By: if they are the same, Y, isa 1, In tum, the remaining XNOR gates compare the bits that are left, producing a 1 output For equal bits and a 0 output for unequal bits. Ifthe words A and B are identical, all xNOR gates have high outputs and the AND gate has a high EQUAL. If words ‘A and B differ in one or more bit positions, the AND gate has a low EQUAL, % Ie Jn |e [hn Yr Fig, 324 Word comparator GLOSSARY controlled inverter This circuit produces the 1's comple- ment ofthe input word. One application is binary subtrac- tion. It is sometimes called a programmed inverter. De Morgan's theorems The frst theorem says that a NoR ate is equivalent to a bubbled 4ND gate. The second theorem says that @ NAND gate is equivalent to a bubbled on gate. even parity An even number of 1s in a binary word NAND gate EZuivalent to an AND gate followed by an inverter. All inputs must be high to get a low output, Non gate Equivalent toanok gate followed by an inverter All inputs must be low to get a high output. ‘odd parity An odd number of Is in a binary word. arity generator A circuit that produces either an odd- or ceven-parity bit to go along with the data, XNOR gale Equivalent to an EXCLUSIVE-OR gate followed bby an inverter. The output is high only when the input word thas even party. XOR gafe An EXCLUSIVE-OR gate. It has a high output only when the input word has odd parity. For a 2-input XOR gate, the output is high only when the inputs are different SELF-TESTING REVIEW Read each of the following and provide the missing words. Answers appear at the beginning of the next question, 1. A-nor gate has «vo or more input signals, AIL inputs must be — to get a high output. A NoR gate recognizes only the input word whose bits are The NoR gate is logically equivalent to an or gate followed by an 2. (low, Os, inverter) De Morgan's first theorem says that a NOR gate is equivalent to a bubbled gate 3. (AND) ANAND gate is equivalent to an AND gate followed by an inverter. All inputs must be to get a low output. De Morgan's second theorem says that a NAND gate is equivalent to a bubbled gate 4. (high, oR) An xox gate recognizes only words with an —_____ number of Is. The 2-input xor gate has a high output only when the input bits are XOR gates are ideal for testing parity because even-parity words produce a ‘output and odd-parity words produce a output. 5. (odd, different, low, high) An odd-patity generator produces an odd-parity bit to go along with the data, Chapter 3 More Logic Gates 43. ‘The parity of the transmitted data is An XOR gate can test each received word for parity rejecting words with parity (odd, even) A controlled inverter is a logic circuit that transmits a binary word or its plement, PROBLEMS 7. (I's) The EXCLUSIVE-NOR gate is equivalent to an XOR gate followed by an inverter. Because of this, even-parity words produce a high output 341, In Fig. 3-25a the two inputs are connected to- gether. If A is low, what is Y? If A is high, what is ¥? Does the circuit act like a noninverter or an inverter? tp >—: i : ~~ yo 1 Fig. 3.25, 3-2. What is the output in Fig. 3-25b if both inputs are low? If one is low and the other high? If both are high? Does the cireuit act like an OR gate or an AND gate? 3-3, Figure 3.26 shows a Nox-gate crosshar switch, If all X and Y inputs are high, which of the Z outputs is high? If all inputs are high except X; and ¥,, which Z output is high? If X, and ¥y are low and all other inputs are high, which Z output is high? 3-4, In Fig. 3-26, you want Z; to be 1 and all other Z ‘outputs to be 0. What values must the X and ¥ inputs have? 35. 36. 31. 38. 39. 310, ‘The outputs in Fig. 3-27 are cross-coupled back to the inputs of the NoR gates. If R = O and § = 1, what do Q and Q equal? . of s Fig, 3:27 Cross-coupled Nox gates R= Lands equal? Q? Prove that Fig. 3-280 and b are equivalent. ‘What isthe output in Fig. 3-28a if all inputs are Os. I all inputs are 1s? What isthe output in Fig. 3-280 if all inputs are 0s. If all inputs are 1s? A.NoR has 6 inputs. How many input words are in its truth table? What i the only input word thet produces a 1 output? In Fig. 3-28a how many input words are there in the truth table? ‘What isthe output in Fig. 3-29 if all inputs are low? If all inputs are high? O in Fig, 3-27, what does Q "TS yyy Fig. 3.26 wos-pate crossbar switch 44 Digital Computer Electronics
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