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DAC Programs

The document contains VHDL code for generating different types of waveforms - sawtooth, sine, square, and triangular - to output on a DAC. The code defines entities with ports for a clock input and DAC output. It contains architectures that use processes to increment counters on the clock edge and output changing bit patterns to generate the different waveform shapes. Placement constraints are also specified to map the ports to FPGA pins.

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sudhanva p kashyap
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© © All Rights Reserved
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34 views

DAC Programs

The document contains VHDL code for generating different types of waveforms - sawtooth, sine, square, and triangular - to output on a DAC. The code defines entities with ports for a clock input and DAC output. It contains architectures that use processes to increment counters on the clock edge and output changing bit patterns to generate the different waveform shapes. Placement constraints are also specified to map the ports to FPGA pins.

Uploaded by

sudhanva p kashyap
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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DAC Programs

----Sawtooth----

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity swatooth_wave is
Port ( clk : in std_logic;
rst : in std_logic;
dac_out : out std_logic_vector(0 to 7));
end swatooth_wave;
architecture Behavioral of swatooth_wave is
signal temp : std_logic_vector(3 downto 0);
signal counter : std_logic_vector(0 to 7);
signal en :std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
temp <= temp + '1' ;
end if;
end process;
process(temp(3))
begin
if rst='1' then
counter <= "00000000";
elsif rising_edge(temp(3)) then
counter <= counter + 1 ;
end if;
end process;
dac_out <=counter;
end Behavioral;

--UCF--

NET "clk" LOC = "p55" ;


NET "dac_out<0>" LOC = "p24" ;
NET "dac_out<1>" LOC = "p22" ;
NET "dac_out<2>" LOC = "p21" ;
NET "dac_out<3>" LOC = "p17" ;
NET "dac_out<4>" LOC = "p15" ;
NET "dac_out<5>" LOC = "p14" ;
NET "dac_out<6>" LOC = "p12" ;
NET "dac_out<7>" LOC = "p1" ;
NET "rst" LOC = "p80" ;
----Sine----

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_arith.ALL;

entity sin is
Port (dac: out STD_LOGIC_VECTOR (7 downto 0);
clk: in STD_LOGIC);
end sin;

architecture Behavioral of sin is


signal clk_div:STD_LOGIC_VECTOR (25 downto 0);
signal clkdiv:std_logic;
signal temp:STD_LOGIC_VECTOR(143 downto 0):=x"00" & x"08" & x"1E" &
x"40" & x"6A" & x"96" & x"C0" & x"E2" & x"F8" & x"FF" & x"F8" & x"E2" &
x"C0" & x"96" & x"6A" & x"40" & x"1E" & x"08";
begin
process(clk)
begin
if(clk='1' and clk'event) then
clk_div<= clk_div+1;
end if;
clkdiv<=clk_div(3);
end process;

process(clkdiv)
variable state: std_logic;
variable shift:integer range 0 to 144;
begin
if(rising_edge(clkdiv)) then
if( shift=136) then
shift:=0;
else
shift:=shift+8;
end if;
dac<=temp((shift+7) downto shift);
end if;
end process;
end Behavioral;

--UCF--

NET "clk" loc ="p55";


NET "dac<7>" LOC = "p24" ;
NET "dac<6>" LOC = "p22" ;
NET "dac<5>" LOC = "p21" ;
NET "dac<4>" LOC = "p17" ;
NET "dac<3>" LOC = "p15" ;
NET "dac<2>" LOC = "p14" ;
NET "dac<1>" LOC = "p12" ;
NET "dac<0>" LOC = "p1" ;
----square-----

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity square_wave is
Port ( clk : in std_logic;
rst : in std_logic;
dac_out : out std_logic_vector(0 to 7));
end square_wave;
architecture Behavioral of square_wave is
signal count:std_logic_vector(15 downto 0):=x"0000";
begin
process(rst,clk)
begin
if rst='1' then dac_out<="00000000";
elsif rising_edge(clk) then
count<=count+1;
end if;
if count=x"0000" then dac_out<=x"00";
elsif count(8)='1' then dac_out<=x"FF";
end if;
end process;
end Behavioral;

--UCF--

NET "clk" LOC = "p55" ;


NET "dac_out<0>" LOC = "p24" ;
NET "dac_out<1>" LOC = "p22" ;
NET "dac_out<2>" LOC = "p21" ;
NET "dac_out<3>" LOC = "p17" ;
NET "dac_out<4>" LOC = "p15" ;
NET "dac_out<5>" LOC = "p14" ;
NET "dac_out<6>" LOC = "p12" ;
NET "dac_out<7>" LOC = "p1" ;
NET "rst" LOC = "p80" ;
-----Triangular-----

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity triangular_wave is
Port ( clk : in std_logic;
rst : in std_logic;
dac_out : out std_logic_vector(0 to 7));
end triangular_wave ;
architecture Behavioral of triangular_wave is
signal counter : std_logic_vector(0 to 8);
signal temp : std_logic_vector(3 downto 0);
signal en :std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
temp <= temp + '1' ;
end if;
end process;
process(temp(3))
begin
if rst='1' then
counter <= "000000000";
elsif rising_edge(temp(3)) then
counter <= counter + 1 ;
if counter(0)='1' then
dac_out <=counter(1 to 8);
else
dac_out <=not(counter(1 to 8));
end if;
end if;
end process;
end Behavioral;

--UCF--

NET "clk" LOC = "p55" ;


NET "dac_out<0>" LOC = "p24" ;
NET "dac_out<1>" LOC = "p22" ;
NET "dac_out<2>" LOC = "p21" ;
NET "dac_out<3>" LOC = "p17" ;
NET "dac_out<4>" LOC = "p15" ;
NET "dac_out<5>" LOC = "p14" ;
NET "dac_out<6>" LOC = "p12" ;
NET "dac_out<7>" LOC = "p1" ;
NET "rst" LOC = "p80" ;

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