BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani

Pilani Campus
AUGS/ AGSR Division

SECOND SEMESTER 2022-23

COURSE HANDOUT
Date: 14.01.2023

In addition to part I (General Handout for all courses appended to the Time table) this portion gives further
specific details regarding the course.
Course No : CS/EEE/INSTR F241
Course Title : Microprocessors Programming and Interfacing
Instructor-in-Charge : Dr. Vinay Chamola
Instructor(s) : Dr. GSS Chalapathi
Tutorial Instructors : Dr. Vinay Chamola, Dr. GSS Chalapathi, Naga Siva Sai Reddy,
Anubhav Elhence, Jyoti Pandey
Practical Instructors : Ziyaur, Akanksha, Suraj, Radha, Prem sai, Pranay, Jeevan, Buddhi,
Surabhi, Sumitra, Amit, Anukaran, Parul, Sankalp, Mritunjay, Divya,

1. Course Description: Programmers model of processor, processor architecture; Instruction set, modular
assembly programming using subroutines, macros etc.; Timing diagrams; Concept of interrupts: hardware &
software interrupts, Interrupt handling techniques, Interrupt controllers; Types of Memory & memory
interfacing; Programmable Peripheral devices and I/O Interfacing; DMA controller and its interfacing: Design
of processor based system. This course will have laboratory component.

2. Scope and Objective of the Course:This course is a basic introduction to processor ISA, Assembly
programming, Computer & Embedded Architecture. Intel 80x86 is used as a platform through the course.
8086 - 80486 Programmers model of processor, processor architecture; Instruction set, modular assembly
programming using subroutines, macros etc.; Timing diagrams; Concept of interrupts: hardware & software
interrupts, Interrupt handling techniques, Interrupt controllers. Types of Memory & memory interfacing.
Programmable Peripheral devices and I/O Interfacing, DMA controller and its interfacing. Design of
processor based system.

3. Text Books: Barry B Brey, The Intel Microprocessors.Pearson, Eight Ed. 2009.
4. Reference Books:Douglas V Hall, Microprocessor and Interfacing, TMH, Second Edition.
5. Course Plan:
Module Lecture Lecture Session Reference Learning outcomes
No. Session (Text book)
1 1 Compute Architecture, Memory & I/O Chapter 1 Learn: Introduction to
organization, CISC/RISC processors Microprocessor and
Microcomputers
1 2-3 Programmer's Model Chapter 2 Learn:Microprocessor & its
architecture
1 4-6 Addressing Modes Chapter 3 Learn:Assembly
Programming
1 7-15 Instruction Set & ALP Chapter 4-6, 8 Learn:Assembly
Programming

1
 BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani
Pilani Campus
AUGS/ AGSR Division

2 16-18 Pin Out, Modes of operation, Clocking, Buses Chapter 9 Learn:8086/8088 Hardware
Specifications
2 19-21 Memory Devices, Address Decoding- Memory Chapter -10 Learn:Memory Interface
Interface 8086- 80386, Protected Memory and Protected memory
2 22 Basic I/O interfacing (I/O mapped I/O and Chapter 11.1, Learn:I/O Interfacing
Memory mapped I/O) I/O port address 11.2
decoding, Protected Mode
2 23-25 8255 Chapter 11.3 Learn:Programmable
Peripheral Devices
3 26-27 Types of interrupts, Vector tables, Priority Chapter 12.1, Learn:Interrupts
Schemes 12.2,
3 28-29 8259 Chapter 12.4 Learn:Interrupt Controller
3 30-32 8253/8254 Chapter 11.4 Learn:Programmable Timer
3 33-34 ADC, DAC, DMA Chapter 11.6 Learn:Converters
3 35-38 Basic Operation, 8237, Shared Bus, Disk Chapter -13 Learn:DMA controller
Memory Systems, Video Displays
3 39-40 Processor based system design Chapter 15 Learn:System Design

6. Evaluation Scheme: (* Note: The weightage associate with various evaluation components may be
changed during the semester as per AUGSD instructions / COVID-19 associated dynamics)

Component Duration Weightage Date & Time Nature of component

(%) (Close Book/ Open Book)
Mid-Semester Test 90 Min. 30% TBA 16 March 2023 FN1
Lab (Regular) 2h 10% TBA TBA
Tutorial exams periodic 10% TBA Periodic
Lab test 1h 10% TBA
Comprehensive 3h 40% TBA 15/05/2023 FN
Examination

7. Chamber Consultation Hour: To be announced in the class

8. Notices: Will be shared by email periodically to students.
9. Make-up Policy: Make up will be allowed for genuine cases. No make up for Lab/ Tut test.
10. Note (if any): A student who scores less than 20% marks will be highly likely to be awarded NC.

Instructor-in-charge
Course No. CS/EEE/INSTR F241