G.

KIRAN KUMAR
#20 Kaveri Layout Analog And Memory Layout Engineer
Bangalore (India)
Phone: +91 9986332025
E-Mail: [email protected]
Carrier objective: To work in competitive and
innovative layout structures
PROFESSIONAL
SUMMARY

o Sr Engineer at GLOBALFOUNDRIES Bangalore: 3 YEARS OF experience in Leading team on

Technology based memory and analog layout designs(GMS) for multiple R&D projects
(12nm,28nm,22FDSOI,55BCDLite and 130nm) and advanced nodes including layout innovations, tasks
assignment and technologies performance step-up.
o Design Engineer – II at Sivalley Technology Pvt Ltd : 3 YEARS OF experience in layout
development on different nodes (90nm, 65nm and 28nm,14nm,7nm,5nm). Expertise in LVS, DRC,
EM/IR, density fixes for different nodes.

WORK HISTORY
Sr Engineer at GLOBALFOUNDRIES Bangalore: (2019-Till date)

PROJECT NAME: CDA ROLE: Layout Lead

FULL CHIP-1 :TS03Q05_CDA_PKG  Driven the Layout team Lead Role with the team of 8 members for
FULL CHIP-2 :TS03Q05_CDA_WFR Class-D padcage.
Tech Node : 28BCDLite  Worked on 12V H-Bridge layout to meet frequency of 20Hz to 20 KHz.
Customer :GLOBALFOUNDRIES  Scheduled regular Meetings with device model team, PDK team and
resolved LVS of Esdnfet_12p0 device in layout, and the DRC errors
(BUGS) within the device near the PC, BLKSD, RX, BP interfaces
within time.
 Worked on TS03Q05_CDA_PKG & TS03Q05_CDA_WFR Top level
integration.
 Integrated full chip with 3 different voltage based IO which consists
closed loop and open loop system internally.
PROJECT NAME: HTOL_PUF ROLE: Layout Lead
FULL CHIP-1 :MPW2250_HTOL_PUF  PUF is a compitative Physically Unclonable fingerprint solution.
FULL CHIP-2 :MPW2250_HTOL_DM  Created SOS environment for MPW2249 & MPW2250 HTOL_PUF.
Tech Node : 22FDX_PLUS  Taken full ownership on all 14 Macros top level integration.
Customer : GLOBALFOUNDRIES  Leading 3 members team to design quality layouts within deadline.
 Conducted regular syncup meetings to track the task status.
 Worked on LEF generation for all types of Pinouts for RTL to GDS.
 Worked on Floorplan and PDL to estimate area of each cell of the
macro. And integrated with 28 padcage.
 Communicating with design team and stakeholder to deliver designs as
per the expectations.
PROJECT NAME: 12FDX RRAM ROLE: Layout Lead
Tech Node : 12FDX  Worked on 12FDX cadence environment for 12FDX RRAM test
Customer : GLOBALFOUNDRIES structures.
 Trained team to learn TRED method and guided them to develop their
skills to design DOES.
 Initiated TRED (Text Based Relative Edge Design) method in 12FDX to
migrate RRAM DOE structures from 22FDX.
 Worked with all the stakeholders (Malta team, Dresden team) and
designed sample DOEs for the structures like ARRAY_FLY,
FET_ARRAY to achieve competitive footprint.
 12FDX RRAM is planned as future vehicle, so used this chance to make
improvements in parameterization methods:
 Increased transparency
 Increased user flexibility
 Enabled easier DOE generation
PROJECT NAME:PUF Array ROLE: Layout Lead
Tech Node : 22FDX_PLUS  Designed F22PUFK1A SLM with reference PUF reference sense Amp.
Customer : GLOBALFOUNDRIES  Integrated array and Sense Amp with 1X25 padset.
PROJECT NAME:TS22D02_DH46_PUF ROLE: Layout Lead
Tech Node : 22FDX_PLUS  F22PUFK1A is designed to characterize reference sense Amp with
 Worked on 8 macros top level integration.
Customer : GLOBALFOUNDRIES different gate lengths and widths.
 Managed team of 2 members and design quality Layouts.
 Designed DOEs against DRCs rules to check Vt variation within devices.
PROJECT NAME: LCOS  At pad level Sense Amplifier layout routing is taken care to meet
operating conditions and ROLE: Layout
taken care Lead and PBIAS voltages (1000
of NBIAS
Tech Node : 22FDX_PLUS  Achieved Cell Area is X= 3.18 um & Y= 3.2 um (less than area
Customer : SONY µm2) routing.
 proposed by Sony)
Driven layout design to stabilize operation and the effect of tilt settings
 Designed
across PVTlayout
and toofminimize
2 APMOMs withinmismatch.
SA input 3.3X3.3(um) in a single unit cell
 which were shared among transistors.
Verified checklist and submitted .gds without any waivers.
 Came out with the technique of suitable choice of metal stack layers to
PROJECT NAME: PANDA accommodate both DCAP andROLE: APMOM together with the stringent
Tech Node : 130GePD  spacing requirement.
Worked on 4TUS 5u Pixel Array.
Customer : GLOBALFOUNDRIES 
 Innovatively
Worked added
on Top DCAPs
level for 8~10fF
integration for 4T4Salong with APMOM
& 4TUS caps to meet
Pixel Arrays.
 Sony requirement.
Followed up with WRB to wave FABDRC violations.

 Communicated
As this Imagingwitharraystakeholders and cleared
Test Chip consists of 3T,their
4T,doubts on design.
4T 4-shared designs
 22FDX
to be carried over improvements with the increment of arraymade
LCOS pixel driver layout had been customized and size GF to
discuss
targetingcustomization
4mm sensor die of apmom
based on to customer
place 2 apmoms
demand.in smaller area like
 3.2umx3.2um
Team designed with Sony in
16 Chips the various
with future. pixel array combinations.
 Contributed on
Contributed in aall
layout design
16 chips to show
reviews possibility
to increase of GFofinLayouts
quality makingand
minimum width
delivered on time. of apmom in 22FDX-HV smaller.
PROJECT NAME: RRAM ROLE: Layout Lead
Tech Node : 28BCDLite  Migrated 22FDX RRAM SLMs to 28BCDLite.
Customer : GLOBALFOUNDRIES  Created SOS environment for MPW0367.
 Driven the layout Team with the team of 4 members for SLPE_RRAM
 Designed Layouts for FLYCELL, Array Fly, FETA, 8x8 Array (1T) and
Mini Array structures.
 Designed Layouts for 45 SLMs and enabled other teams for completing
and gds submission.
 Had discussions with Project Manager and resolved many issues by the
support of Fab team and device teams.
 Based on the customer requirement, migrated RRAM BEOL from
22FDX (C1/C2) to 28BCDLite (M3/M4) (5U1x_1T8x_LB).
 Explored SG/ZG access devices to enable a competitive 28BCDLite
RRAM bitcell . Confidently led the team to get best quality layouts for
SEED proposal within short duration.
PROJECTNAME:MPW06A9_DTCO_RTN55 ROLE: Layout Lead
Tech Node : 55BCDL  Created SOS Work Area for MPW06A9_DTCO_RTN55.
Customer : GLOBALFOUNDRIES  Managed team of 2 members to design 2 SLM's within short duration.
 Worked on SLMs, PC donut devices DGXPFET & NFET. Each SLM
with 6 DUTs.
 Generated Fill for all 12 SLMs to release designs in PTRF.
 Had a regular discussion with team and stakeholders to get estimated
design output.
 The motivation of this project is to study the RTS behavior based on the
custom layouts of PC donut and HVT donut devices.
PROJECT NAME:SONY IREF ROLE:
Tech Node : 22FDX_PLUS  Designed Layout for IREF Current Mirror with interdigitized matching.
Customer : SONY  Taken care of PVT variations while matching the devices.
 Verified all checks to improve quality of layout.
 MPW2248 SONY IREF Current Mirror product in 22FDX is designed to
investigate SONY feedback on IREF mismatch to 15uA by inter-
digitation matching. This is a value addition for GF in case the PDK
improvements are required based on the model hardware correlation
results
Education

2006-2009 o PhD Thesis in Microelectronics at LAAS-CEMES/CNRS laboratories

(Toulouse, France). "Modeling and simulation of extended defects and
dopant diffusion in Si, SOI and SiGe for advanced MOSFETS".
2005-2006 o Master Degree in Design of Microelectronic and Microsystems Circuits at
the Paul Sabatier University of Toulouse, France
2002-2005 o Engineer degree in Electronic and Digital Technologies at the engineering
school of the University of Nantes, France
2000-2002 o University level preparation (mathematics & physics) for entry to french
institutes of technology "Grandes Ecoles"
2000 o Baccalaureat in mathematics, Casablanca (Morocco)

Skills
CMOS devices o Development of physical models related to relaxed silicon-germanium
alloys, strained silicon, and silicon-on-insulator materials
o Process and device simulation of 65nm SOI and 45nm SiGe
(STMicroelectronics) and 28nm, 20nm and 22FDX (Globalfoundries)
o Physical characterization: TEM, SIMS (CEMES-LAAS/CNRS)
Dissemination o International conferences: E-MRS 2008, EUROSOI 2009, E-MRS 2009,
ESSDERC 2009, SOI Conference 2009, SSDM 2010, IEDM 2010, E-MRS
2012, ISTDM 2012, IIT 2012, ESC 2013, SISPAD 2014, ESSDERC 2014
o 12 papers in peer-reviewed international journals
o Author and co-author of more than 10 submitted patents
Programming o C/C++, fortran, java, Tcl
Computing o TSUPREM4, MEDICI, Synopsys Sentaurus Process, Spice, Silvaco (Athena,
Atlas), Matlab, Maple, Mentor graphic, Knowledge of VHDL, VHDL AMS
Operating o Windows, Linux, Unix, MacOS
systems

Languages
 Arabic: mother tongue
 French: Fluent
 English: Fluent
 German: B2 level
Activities
 Tennis, football, chess
 Travelling, Cinema, music
 Papers
- E.M. Bazizi, I. Chakarov, T. Herrmann, A. Zaka, L. Jiang, X. Wu, S.M. Pandey, F. Benistant,
D. Reid, A.R. Brown, C. Alexander, C. Millar, A. Asenov. "Advanced TCAD Simulation of
Local Mismatch in 14nm CMOS Technology FinFETs". SISPAD 2015, September 9-11,
2015, Washington, DC, USA.

- E. M. Bazizi, I. Chakarov, T. Herrmann, A. Zaka, L. Jiang, X. Wu, S. M. Pandey, F.

Benistant, D. Reid, A. R. Brown, C. Alexander, C. Millar, A. Asenov. "Impact of Backplane
Configuration on the Statistical Variability in 22nm FDSOI CMOS", SISPAD 2015,
September 9-11, 2015, Washington, DC, USA

- E.M. Bazizi, A. Zaka, T. Hermann, F. Benistant, J.H.M. Tin, J.P. Goh, L. Jiang, M. Joshi, H.
Van Meer, K. Korablev, "USJ Engineering Impacts on FinFETs and RDF Investigation
using Full 3D Process/Device Simulation", SISPAD 2014, September 9-11, 2015,
Yokohama, Japan.

- E.M. Bazizi, A. Zaka, T. Herrmann, F. Benistant, J.H.M. Tin, J.P. Goh, L. Jiang, M. Joshi, H.
van Meer, K. Korablev, “Advanced TCAD for predictive FinFETs Vth mismatch using full
3D process/device simulation”, ESSDERC 2014, September 22-26, 2014, Venice, Italy.

- F. Benistant, J. Phang, T. Herrmann, E.M. Bazizi, A. Zaka, L. Jiang, “TCAD Modeling for
next generation CMOS devices”, IIT 2014, 20th International Conference on Ion
Implantation Technology, June 26 – July 04, Portland, Oregon, USA.

- F. Benistant, E. M. Bazizi, L. Jiang, J. H. M. Tin, and J. P. Goh, “Full 3D process/device

simulations re-using 2D TCAD knowledge for optimizing n and p-type FinFET transistors”,
ISTDM 2014, 7th International Silicon-Germanium Technology and Device Meeting, June
02-04, Singapore

- E. M. Bazizi, A. Zaka, G. Dilliway, B. Bai, M. Wiatr, F. Benistant, M. Horstmann,

“Investigation of Embedded SiGe Source/Drain for 28nm HKMG PFET Performance
Enhancement”, 223rd ECS meeting, May 12-16, 2013, Toronto, ON, Canada

- E. M. Bazizi, A. Zaka, G. Dilliway, B. Bai, M. Wiatr, F. Benistant, M. Horstmann,

“Investigation of Embedded SiGe Source/Drain for 28nm HKMG PFET Performance
Enhancement”, ECS Transactions, 2013, Vol.53 (3), pp.27-32

- E.M. Bazizi, A. Zaka, F. Benistant, “Analysis of USJ formation with combined RTA/laser
annealing conditions for 28 nm high-k/metal gate CMOS technology using advanced TCAD
for process and device simulation”, May 2013, Solid-State Electronics, Volume 83, Pages
61–65.

- E. M. Bazizi, S. M. Pandey, C. Wang, I. Jiang, S. Chu, F. Benistant, T. Herrmann, J. Faul, D.-

W. Franke, M. Wiatr, M. Horstmann “Analysis of USJ Formation with Combined
RTA/Laser Annealing Conditions for 28nm High-K/Metal Gate CMOS Technology Using
Advanced TCAD for Process and Device Simulation” ISTDM 2012, 6th International
Silicon-Germanium Technology and Device Meeting, June 04-06, Berkeley, CA.

- E. M. Bazizi, K. R. C. Mok, F. Benistant, S. H. Yeong, R. S. Teo, and C. Zechner, “TCAD

simulation of the co-implantation species C, F, and N in MOS transistors”, AIP Conf. Proc.,
vol. 1496, p. 249, 2012
- B.J. Pawlak, T. Janssens, S. Singh, I. Kuzma-Filipek, J. Robbelein, N.E. Posthuma, J.
Poortmans, F. Cristiano, E.M. Bazizi, “Studies of implanted boron emitters for solar cell
applications”, Progress in Photovoltaics: Research and Applications, 20 (2012), pp. 106–110

- F. Cristiano, Z. Essa, Y. Qiu, Y. Spiegel, F. Torregrosa, J. Duchaine, P. Boulenc, C.

Tavernier. O. Cojocaru, D. Blavette, D. Mangelinck, P.F. Fazzini, M. Quillec, M. Bazizi, M.
Hackenberg, S. Boninelli, “Implantation-induced structural defects in highly activated
USJs: Boron precipitation and trapping in pre-amorphised silicon”. 12th International
Workshop on Junction Technology (IWJT), 2012

- E. M. Bazizi, P. F. Fazzini, F. Cristiano, A. Pakfar, C. Tavernier, F. Payet, T. Skotnicki, C.

Zechner, N. Zographos, D. Matveev, N.E.B. Cowern, N.S. Bennett, C. Ahn, J. C. Yoon,
“Transfer of physically-based models from process to device simulations: Application to
advanced Strained Si/SiGe MOSFETs”. 2010 IEEE International Electron Devices Meeting
(IEDM), San Francisco, CA, United States, 6-8 December

- E. M. Bazizi, P. F. Fazzini, A. Pakfar, C. Tavernier, B. Vandelle, H. Kheyrandish, S. Paul, W.

Lerch, F. Cristiano, “Modeling of the effect of the buried Si-SiO2 interface on transient
enhanced boron diffusion in silicon on insulator”, Journal of Applied Physics, Volume 107,
Issue 7, pp. 074503-074503-4 (2010).

- E.M. Bazizi, A. Pakfar, P.F. Fazzini, F. Cristiano, C. Tavernier, A. Claverie, N. Zographos, C.

Zechner, E. Scheid, “Transfer of physically-based models from process to device
simulations: Application to advanced SOI MOSFETs”, Thin Solid Films, Volume 518,
Issue 9, 26 February 2010, Pages 2427–2430. Proceedings of the EMRS 2009 Spring Meeting

- E.M. Bazizi, A. Pakfar, P. F. Fazzini, F. Cristiano, C. Tavernier, A. Claverie, A. Burenkov, P.

Pichler, “Comparison between 65nm bulk and PD-SOI MOSFETs: Si/BOX interface effect
on point defects and doping profiles”, Solid State Device Research Conference, ESSDERC
2009

- E.M. Bazizi ; A. Pakfar ; P. F. Fazzini ; F. Cristiano ; C. Tavernier ; A. Claverie ; A. Burenkov

; P. Pichler, “PD-SOI MOSFETs: interface effect on point defects and doping profiles”, SOI
Conference, 2009 IEEE International Date of Conference: 5-8 Oct. 2009

- M. Gavelle, E. M. Bazizi, E. Scheid, P. F. Fazzini, F. Cristiano, C. Armand, W. Lerch, and S.

Paul. Y. Campidelli, A. Halimaoui, “Detailed investigation of Ge-Si interdiffusion in the full
range of Si1-xGex(0<=x<=1) composition”, Journal of Applied Physics, Volume 104, Issue
11, pp. 113524-113524-7 (2008)

- E.M. Bazizi, P.F. Fazzini, C. Zechner, A. Tsibizov, H. Kheyrandish, A. Pakfar, L. Ciampolini,

C. Tavernier, F. Cristiano, “Modelling of Boron Trapping at End-of-Range defects in pre-
amorphized ultra-shallow junctions”, Materials Science and Engineering: B, Volumes 154–
155, 5 December 2008, Pages 275–278.

- M. Gavelle, E. M. Bazizi, E. Scheid, C. Armand, P. F. Fazzini, O. Marcelot, Y. Campidelli, A.

Halimaoui, F. Cristiano, “Study of silicon–germanium interdiffusion from pure germanium
deposited layers”, Materials Science & Engineering: B, Volumes 154–155, 5 December 2008,
Pages 110–113
- J. Delalleau, A Pakfar, E. M. Bazizi, R. Simola, C. Tavernier, “Continuum simulation of
solid phase epitaxial regrowth of amorphized silicon including most advanced physical
interactions”, Physica Status Solidi (A) Applications and Materials 208(3):608 – 611, March
2011

- F. Cristiano, E.M. Bazizi, P.F. Fazzini, S. Paul, W. Lerch, S. Boninelli, R. Duffy, A. Pakfar,
H. Bourdon, F. Milesi, “Defect evolution and C+/F+ co-implantation in millisecond Flash
annealed ultra-shallow junctions”, International Workshop on Junction Technology (IWJT),
2008

- F. Cristiano, E. M. Bazizi, P. F. Fazzini, S. Boninelli, R. Duffy, A. Pakfar, S. Paul, W. Lerch,

"Extended Defects Evolution in Pre-Amorphised Silicon after Millisecond Flash Anneals",
Materials Science Forum, Vols. 573-574, pp. 269-277, 2008
 Patents
File # Title Country Status
Method for MOSFET resistance decomposition using regular devices Germany Scheduled for Review
High Voltage FinFET Device and Method of Realization India Signing
DD062 Super-Steep Retrograde Well (SSRW) for advanced CMOS nodes Germany Final Disposition: Patent

DD062-US-NP SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SEMICONDUCTOR DEVICES INCLUDING A RETROGRADE WELL United States of America Issued
DD089 Embedded S/D graded Si Ge with optimized angle for PFET stress related mobility enhancement Germany Final Disposition: Patent
Performance Enhancement in Transistors by Providing a Graded Embedded Strain-Inducing Semiconductor Region
DD089-CN-NP with Adapted Angles with Respect to the Substrate Surface China Pending
Performance Enhancement in Transistors by Providing a Graded Embedded Strain-Inducing Semiconductor Region
DD089-TW-NP with Adapted Angles with Respect to the Substrate Surface Taiwan R.O.C. Issued
Performance Enhancement in Transistors by Providing a Graded Embedded Strain-Inducing Semiconductor Region
DD089-US-NP with Adapted Angles with Respect to the Substrate Surface United States of America Issued
Optimized anneal scheme including sub-melt laser anneal on HKMG CMOS technologies for device performance
DD131 improvement without degrading the narrow width effects Germany Final Disposition: Trade Secret
Dual HK oxide gate stack to improve effective work function adjustment and reliability in 28nm HKMG VLSI CMOS
ED010 technologies Germany Final Disposition: Patent
ED025 Optimized threshold voltage length dependence of high-k nMOSFET using Fluorine implantation Germany Final Disposition: Patent
Method of Forming a Semiconductor Device Structure Employing Fluorine Doping and According Semiconductor
ED025-CN-NP Device Structure China Pending
Method of Forming a Semiconductor Device Structure Employing Fluorine Doping and According Semiconductor
ED025-TW-NP Device Structure Taiwan R.O.C. Pending
Method of Forming a Semiconductor Device Structure Employing Fluorine Doping and According Semiconductor
ED025-US-NP Device Structure United States of America Issued
ED107 Optimized NMOS implant/anneal scheme for a full LSA-compliant flow Germany Final Disposition: Patent
ED107-US-DIV METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED IMPLANTATION PROCESSES United States of America Pending
ED107-US-NP METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED IMPLANTATION PROCESSES United States of America Issued

HD101 Integration of Wordline in HKMG technologies incorporating an overhang to the Floating Storage Node of a NVM cell Germany Final Disposition: Patent
HD101-US-NP SEMICONDUCTOR STRUCTURE INCLUDING A NONVOLATILE MEMORY CELL AND METHOD FOR THE FORMATION THEREOF United States of America Pending
HD101-US-PSP SEMICONDUCTOR STRUCTURE INCLUDING A NONVOLATILE MEMORY CELL AND METHOD FOR THE FORMATION THEREOF United States of America Pending
HD106 Oxide Spacer to modulate floating gate to select gate distance in non-volatile memory cell Germany Final Disposition: Combined
IAUS002 Low-Cost Extreme Low-Vt Devices in FDSOI United States of America Open
ID020 Bias-independent N-MOSCAP in FEoL Germany Final Disposition: Patent
ID020-US-NP CAPACITIVE STRUCTURE IN A SEMICONDUCTOR DEVICE HAVING REDUCED CAPACITANCE VARIABILITY United States of America Pending
ID052 Method of integrating Source and Erase Gate regions in a NVM cell Germany Final Disposition: Trade Secret
ID065 Manufacturing method for Voltage Independent MOS Capacitor Germany Final Disposition: Patent
ID065-US-NP MOS CAPACITIVE STRUCTURE OF REDUCED CAPACITANCE VARIABILITY United States of America Pending
ID109 Adjustable ultra high resistor passive device on SOI Germany Final Disposition: Patent
ID119 Optimized annealing scheme for improved NFET / PFET devices Germany Open
 EU projects

Active project
- III-V-MOS: Technology CAD for III-V Semiconductor-based MOSFETs
Call (part) Identifier: FP7-ICT-2013-11
- MARS

completed:
ATOMICS